From d48136cb1a992adc631325ddab1bf4cf879691c8 Mon Sep 17 00:00:00 2001 From: davidscherer Date: Tue, 30 May 2023 18:57:16 +0200 Subject: [PATCH] added testbench for ams slave --- BMS_Testbench/BMS_Software_V1/.cproject | 329 + BMS_Testbench/BMS_Software_V1/.mxproject | 25 + BMS_Testbench/BMS_Software_V1/.project | 32 + .../com.st.stm32cube.ide.mcu.sfrview.prefs | 2 + .../.settings/language.settings.xml | 47 + .../.settings/stm32cubeide.project.prefs | 4 + .../.vscode/c_cpp_properties.json | 20 + .../BMS_Software_V1/.vscode/launch.json | 34 + .../BMS_Software_V1/.vscode/settings.json | 4 + .../BMS_Software_V1/.vscode/tasks.json | 50 + .../BMS_Software_V1/BMS_Software Debug.launch | 78 + .../BMS_Software_V1/BMS_Software.ioc | 199 + .../Core/Inc/ADBMS_Abstraction.h | 82 + .../Core/Inc/ADBMS_CMD_MAKROS.h | 191 + .../Core/Inc/ADBMS_LL_Driver.h | 44 + .../BMS_Software_V1/Core/Inc/AMS_CAN.h | 49 + .../BMS_Software_V1/Core/Inc/AMS_HighLevel.h | 46 + .../BMS_Software_V1/Core/Inc/Testbench.h | 32 + .../BMS_Software_V1/Core/Inc/common_defs.h | 13 + BMS_Testbench/BMS_Software_V1/Core/Inc/main.h | 83 + .../Core/Inc/stm32f3xx_hal_conf.h | 359 + .../BMS_Software_V1/Core/Inc/stm32f3xx_it.h | 67 + .../Core/Src/ADBMS_Abstraction.c | 422 + .../Core/Src/ADBMS_LL_Driver.c | 230 + .../BMS_Software_V1/Core/Src/AMS_CAN.c | 193 + .../BMS_Software_V1/Core/Src/AMS_HighLevel.c | 304 + .../BMS_Software_V1/Core/Src/Testbench.c | 149 + BMS_Testbench/BMS_Software_V1/Core/Src/main.c | 479 + .../Core/Src/stm32f3xx_hal_msp.c | 337 + .../BMS_Software_V1/Core/Src/stm32f3xx_it.c | 217 + .../BMS_Software_V1/Core/Src/syscalls.c | 176 + .../BMS_Software_V1/Core/Src/sysmem.c | 79 + .../Core/Src/system_stm32f3xx.c | 291 + .../Core/Startup/startup_stm32f302cctx.s | 441 + .../BMS_Software_V1/Debug/BMS_Software.elf | Bin 0 -> 1084440 bytes .../BMS_Software_V1/Debug/BMS_Software.list | 16215 +++++++ .../BMS_Software_V1/Debug/BMS_Software.map | 4236 ++ .../Debug/Core/Src/ADBMS_Abstraction.d | 65 + .../Debug/Core/Src/ADBMS_Abstraction.o | Bin 0 -> 911232 bytes .../Debug/Core/Src/ADBMS_Abstraction.su | 26 + .../Debug/Core/Src/ADBMS_LL_Driver.d | 62 + .../Debug/Core/Src/ADBMS_LL_Driver.o | Bin 0 -> 901280 bytes .../Debug/Core/Src/ADBMS_LL_Driver.su | 12 + .../BMS_Software_V1/Debug/Core/Src/AMS_CAN.d | 74 + .../BMS_Software_V1/Debug/Core/Src/AMS_CAN.o | Bin 0 -> 902868 bytes .../BMS_Software_V1/Debug/Core/Src/AMS_CAN.su | 5 + .../Debug/Core/Src/AMS_HighLevel.d | 67 + .../Debug/Core/Src/AMS_HighLevel.o | Bin 0 -> 908092 bytes .../Debug/Core/Src/AMS_HighLevel.su | 11 + .../Debug/Core/Src/Testbench.d | 75 + .../Debug/Core/Src/Testbench.o | Bin 0 -> 903148 bytes .../Debug/Core/Src/Testbench.su | 5 + .../Debug/Core/Src/UART_Console.d | 73 + .../BMS_Software_V1/Debug/Core/Src/main.d | 76 + .../BMS_Software_V1/Debug/Core/Src/main.o | Bin 0 -> 912960 bytes .../BMS_Software_V1/Debug/Core/Src/main.su | 12 + .../Debug/Core/Src/stm32f3xx_hal_msp.d | 60 + .../Debug/Core/Src/stm32f3xx_hal_msp.o | Bin 0 -> 902700 bytes .../Debug/Core/Src/stm32f3xx_hal_msp.su | 7 + .../Debug/Core/Src/stm32f3xx_it.d | 62 + .../Debug/Core/Src/stm32f3xx_it.o | Bin 0 -> 893384 bytes .../Debug/Core/Src/stm32f3xx_it.su | 10 + .../BMS_Software_V1/Debug/Core/Src/subdir.mk | 57 + .../BMS_Software_V1/Debug/Core/Src/syscalls.d | 1 + .../BMS_Software_V1/Debug/Core/Src/syscalls.o | Bin 0 -> 76920 bytes .../Debug/Core/Src/syscalls.su | 18 + .../BMS_Software_V1/Debug/Core/Src/sysmem.d | 1 + .../BMS_Software_V1/Debug/Core/Src/sysmem.o | Bin 0 -> 46592 bytes .../BMS_Software_V1/Debug/Core/Src/sysmem.su | 1 + .../Debug/Core/Src/system_stm32f3xx.d | 59 + .../Debug/Core/Src/system_stm32f3xx.o | Bin 0 -> 889904 bytes .../Debug/Core/Src/system_stm32f3xx.su | 2 + .../Core/Startup/startup_stm32f302cctx.d | 2 + .../Core/Startup/startup_stm32f302cctx.o | Bin 0 -> 6156 bytes .../Debug/Core/Startup/subdir.mk | 27 + .../STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.d | 60 + .../STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o | Bin 0 -> 901500 bytes .../STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.su | 25 + .../Src/stm32f3xx_hal_can.d | 60 + .../Src/stm32f3xx_hal_can.o | Bin 0 -> 911828 bytes .../Src/stm32f3xx_hal_can.su | 36 + .../Src/stm32f3xx_hal_cortex.d | 60 + .../Src/stm32f3xx_hal_cortex.o | Bin 0 -> 906760 bytes .../Src/stm32f3xx_hal_cortex.su | 32 + .../Src/stm32f3xx_hal_dma.d | 60 + .../Src/stm32f3xx_hal_dma.o | Bin 0 -> 898404 bytes .../Src/stm32f3xx_hal_dma.su | 14 + .../Src/stm32f3xx_hal_exti.d | 60 + .../Src/stm32f3xx_hal_exti.o | Bin 0 -> 894772 bytes .../Src/stm32f3xx_hal_exti.su | 9 + .../Src/stm32f3xx_hal_flash.d | 60 + .../Src/stm32f3xx_hal_flash.o | Bin 0 -> 896588 bytes .../Src/stm32f3xx_hal_flash.su | 14 + .../Src/stm32f3xx_hal_flash_ex.d | 60 + .../Src/stm32f3xx_hal_flash_ex.o | Bin 0 -> 900208 bytes .../Src/stm32f3xx_hal_flash_ex.su | 16 + .../Src/stm32f3xx_hal_gpio.d | 60 + .../Src/stm32f3xx_hal_gpio.o | Bin 0 -> 894636 bytes .../Src/stm32f3xx_hal_gpio.su | 8 + .../Src/stm32f3xx_hal_i2c.d | 60 + .../Src/stm32f3xx_hal_i2c.o | Bin 0 -> 960584 bytes .../Src/stm32f3xx_hal_i2c.su | 79 + .../Src/stm32f3xx_hal_i2c_ex.d | 60 + .../Src/stm32f3xx_hal_i2c_ex.o | Bin 0 -> 894732 bytes .../Src/stm32f3xx_hal_i2c_ex.su | 6 + .../Src/stm32f3xx_hal_pwr.d | 60 + .../Src/stm32f3xx_hal_pwr.o | Bin 0 -> 893132 bytes .../Src/stm32f3xx_hal_pwr.su | 12 + .../Src/stm32f3xx_hal_pwr_ex.d | 60 + .../Src/stm32f3xx_hal_pwr_ex.o | Bin 0 -> 889908 bytes .../Src/stm32f3xx_hal_pwr_ex.su | 5 + .../Src/stm32f3xx_hal_rcc.d | 60 + .../Src/stm32f3xx_hal_rcc.o | Bin 0 -> 910656 bytes .../Src/stm32f3xx_hal_rcc.su | 14 + .../Src/stm32f3xx_hal_rcc_ex.d | 60 + .../Src/stm32f3xx_hal_rcc_ex.o | Bin 0 -> 896032 bytes .../Src/stm32f3xx_hal_rcc_ex.su | 4 + .../Src/stm32f3xx_hal_spi.d | 60 + .../Src/stm32f3xx_hal_spi.o | Bin 0 -> 933568 bytes .../Src/stm32f3xx_hal_spi.su | 56 + .../Src/stm32f3xx_hal_spi_ex.d | 60 + .../Src/stm32f3xx_hal_spi_ex.o | Bin 0 -> 890816 bytes .../Src/stm32f3xx_hal_spi_ex.su | 1 + .../Src/stm32f3xx_hal_tim.d | 60 + .../Src/stm32f3xx_hal_tim.o | Bin 0 -> 886436 bytes .../Src/stm32f3xx_hal_tim.su | 0 .../Src/stm32f3xx_hal_tim_ex.d | 60 + .../Src/stm32f3xx_hal_tim_ex.o | Bin 0 -> 886444 bytes .../Src/stm32f3xx_hal_tim_ex.su | 0 .../STM32F3xx_HAL_Driver/Src/subdir.mk | 78 + BMS_Testbench/BMS_Software_V1/Debug/makefile | 94 + .../BMS_Software_V1/Debug/objects.list | 30 + .../BMS_Software_V1/Debug/objects.mk | 9 + .../BMS_Software_V1/Debug/sources.mk | 27 + .../Device/ST/STM32F3xx/Include/stm32f302xc.h | 12735 +++++ .../Device/ST/STM32F3xx/Include/stm32f3xx.h | 286 + .../ST/STM32F3xx/Include/system_stm32f3xx.h | 106 + .../CMSIS/Device/ST/STM32F3xx/License.md | 83 + .../Drivers/CMSIS/Include/cmsis_armcc.h | 865 + .../Drivers/CMSIS/Include/cmsis_armclang.h | 1869 + .../Drivers/CMSIS/Include/cmsis_compiler.h | 266 + .../Drivers/CMSIS/Include/cmsis_gcc.h | 2085 + .../Drivers/CMSIS/Include/cmsis_iccarm.h | 935 + .../Drivers/CMSIS/Include/cmsis_version.h | 39 + .../Drivers/CMSIS/Include/core_armv8mbl.h | 1918 + .../Drivers/CMSIS/Include/core_armv8mml.h | 2927 ++ .../Drivers/CMSIS/Include/core_cm0.h | 949 + .../Drivers/CMSIS/Include/core_cm0plus.h | 1083 + .../Drivers/CMSIS/Include/core_cm1.h | 976 + .../Drivers/CMSIS/Include/core_cm23.h | 1993 + .../Drivers/CMSIS/Include/core_cm3.h | 1941 + .../Drivers/CMSIS/Include/core_cm33.h | 3002 ++ .../Drivers/CMSIS/Include/core_cm4.h | 2129 + .../Drivers/CMSIS/Include/core_cm7.h | 2671 ++ .../Drivers/CMSIS/Include/core_sc000.h | 1022 + .../Drivers/CMSIS/Include/core_sc300.h | 1915 + .../Drivers/CMSIS/Include/mpu_armv7.h | 270 + .../Drivers/CMSIS/Include/mpu_armv8.h | 333 + .../Drivers/CMSIS/Include/tz_context.h | 70 + .../BMS_Software_V1/Drivers/CMSIS/LICENSE.txt | 201 + .../Inc/Legacy/stm32_hal_legacy.h | 3850 ++ .../STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h | 945 + .../Inc/stm32f3xx_hal_can.h | 842 + .../Inc/stm32f3xx_hal_cortex.h | 426 + .../Inc/stm32f3xx_hal_def.h | 177 + .../Inc/stm32f3xx_hal_dma.h | 454 + .../Inc/stm32f3xx_hal_dma_ex.h | 274 + .../Inc/stm32f3xx_hal_exti.h | 404 + .../Inc/stm32f3xx_hal_flash.h | 381 + .../Inc/stm32f3xx_hal_flash_ex.h | 475 + .../Inc/stm32f3xx_hal_gpio.h | 325 + .../Inc/stm32f3xx_hal_gpio_ex.h | 1522 + .../Inc/stm32f3xx_hal_i2c.h | 838 + .../Inc/stm32f3xx_hal_i2c_ex.h | 180 + .../Inc/stm32f3xx_hal_pwr.h | 219 + .../Inc/stm32f3xx_hal_pwr_ex.h | 322 + .../Inc/stm32f3xx_hal_rcc.h | 1740 + .../Inc/stm32f3xx_hal_rcc_ex.h | 3827 ++ .../Inc/stm32f3xx_hal_spi.h | 852 + .../Inc/stm32f3xx_hal_spi_ex.h | 75 + .../Inc/stm32f3xx_hal_tim.h | 2533 + .../Inc/stm32f3xx_hal_tim_ex.h | 343 + .../Inc/stm32f3xx_ll_bus.h | 1063 + .../Inc/stm32f3xx_ll_cortex.h | 640 + .../Inc/stm32f3xx_ll_dma.h | 1996 + .../Inc/stm32f3xx_ll_exti.h | 1383 + .../Inc/stm32f3xx_ll_gpio.h | 980 + .../Inc/stm32f3xx_ll_i2c.h | 2275 + .../Inc/stm32f3xx_ll_pwr.h | 554 + .../Inc/stm32f3xx_ll_rcc.h | 2842 ++ .../Inc/stm32f3xx_ll_system.h | 1724 + .../Inc/stm32f3xx_ll_utils.h | 282 + .../Drivers/STM32F3xx_HAL_Driver/License.md | 3 + .../STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c | 531 + .../Src/stm32f3xx_hal_can.c | 2420 + .../Src/stm32f3xx_hal_cortex.c | 513 + .../Src/stm32f3xx_hal_dma.c | 900 + .../Src/stm32f3xx_hal_exti.c | 621 + .../Src/stm32f3xx_hal_flash.c | 695 + .../Src/stm32f3xx_hal_flash_ex.c | 983 + .../Src/stm32f3xx_hal_gpio.c | 542 + .../Src/stm32f3xx_hal_i2c.c | 6794 +++ .../Src/stm32f3xx_hal_i2c_ex.c | 367 + .../Src/stm32f3xx_hal_pwr.c | 461 + .../Src/stm32f3xx_hal_pwr_ex.c | 272 + .../Src/stm32f3xx_hal_rcc.c | 1224 + .../Src/stm32f3xx_hal_rcc_ex.c | 1584 + .../Src/stm32f3xx_hal_spi.c | 4458 ++ .../Src/stm32f3xx_hal_spi_ex.c | 115 + .../Src/stm32f3xx_hal_tim.c | 7942 +++ .../Src/stm32f3xx_hal_tim_ex.c | 2554 + BMS_Testbench/BMS_Software_V1/Makefile | 193 + .../STM32-for-VSCode.config.yaml | 107 + BMS_Testbench/BMS_Software_V1/STM32F102xx.svd | 9041 ++++ BMS_Testbench/BMS_Software_V1/STM32F302.svd | 39943 ++++++++++++++++ .../BMS_Software_V1/STM32F302CCTX_FLASH.ld | 185 + .../BMS_Software_V1/STM32F302CCTx_FLASH.ld | 189 + BMS_Testbench/BMS_Software_V1/STM32Make.make | 265 + .../BMS_Software_V1/ams-slave-23 Debug.launch | 77 + .../BMS_Software_V1/ams-slave-23.ioc | 199 + .../BMS_Software_V1/build/ADBMS_Abstraction.d | 63 + .../build/ADBMS_Abstraction.lst | 2389 + .../BMS_Software_V1/build/ADBMS_Abstraction.o | Bin 0 -> 24584 bytes .../BMS_Software_V1/build/ADBMS_LL_Driver.d | 60 + .../BMS_Software_V1/build/ADBMS_LL_Driver.lst | 1600 + .../BMS_Software_V1/build/ADBMS_LL_Driver.o | Bin 0 -> 19084 bytes BMS_Testbench/BMS_Software_V1/build/AMS_CAN.d | 71 + .../BMS_Software_V1/build/AMS_CAN.lst | 942 + BMS_Testbench/BMS_Software_V1/build/AMS_CAN.o | Bin 0 -> 14036 bytes .../BMS_Software_V1/build/AMS_HighLevel.d | 64 + .../BMS_Software_V1/build/AMS_HighLevel.lst | 1530 + .../BMS_Software_V1/build/AMS_HighLevel.o | Bin 0 -> 19816 bytes .../BMS_Software_V1/build/Testbench.d | 72 + .../BMS_Software_V1/build/Testbench.lst | 1048 + .../BMS_Software_V1/build/Testbench.o | Bin 0 -> 14460 bytes .../BMS_Software_V1/build/ams-slave-23.bin | Bin 0 -> 15684 bytes .../BMS_Software_V1/build/ams-slave-23.elf | Bin 0 -> 357412 bytes .../BMS_Software_V1/build/ams-slave-23.hex | 986 + .../BMS_Software_V1/build/ams-slave-23.map | 2940 ++ BMS_Testbench/BMS_Software_V1/build/main.d | 73 + BMS_Testbench/BMS_Software_V1/build/main.lst | 2091 + BMS_Testbench/BMS_Software_V1/build/main.o | Bin 0 -> 25076 bytes .../build/startup_stm32f302xc.d | 1 + .../build/startup_stm32f302xc.o | Bin 0 -> 6292 bytes .../BMS_Software_V1/build/stm32f3xx_hal.d | 57 + .../BMS_Software_V1/build/stm32f3xx_hal.lst | 1527 + .../BMS_Software_V1/build/stm32f3xx_hal.o | Bin 0 -> 16968 bytes .../BMS_Software_V1/build/stm32f3xx_hal_can.d | 58 + .../build/stm32f3xx_hal_can.lst | 7264 +++ .../BMS_Software_V1/build/stm32f3xx_hal_can.o | Bin 0 -> 30700 bytes .../build/stm32f3xx_hal_cortex.d | 58 + .../build/stm32f3xx_hal_cortex.lst | 5049 ++ .../build/stm32f3xx_hal_cortex.o | Bin 0 -> 21976 bytes .../BMS_Software_V1/build/stm32f3xx_hal_dma.d | 58 + .../build/stm32f3xx_hal_dma.lst | 3047 ++ .../BMS_Software_V1/build/stm32f3xx_hal_dma.o | Bin 0 -> 16136 bytes .../build/stm32f3xx_hal_exti.d | 58 + .../build/stm32f3xx_hal_exti.lst | 1819 + .../build/stm32f3xx_hal_exti.o | Bin 0 -> 13340 bytes .../build/stm32f3xx_hal_flash.d | 58 + .../build/stm32f3xx_hal_flash.lst | 2165 + .../build/stm32f3xx_hal_flash.o | Bin 0 -> 13736 bytes .../build/stm32f3xx_hal_flash_ex.d | 58 + .../build/stm32f3xx_hal_flash_ex.lst | 4277 ++ .../build/stm32f3xx_hal_flash_ex.o | Bin 0 -> 19112 bytes .../build/stm32f3xx_hal_gpio.d | 58 + .../build/stm32f3xx_hal_gpio.lst | 1676 + .../build/stm32f3xx_hal_gpio.o | Bin 0 -> 10964 bytes .../BMS_Software_V1/build/stm32f3xx_hal_i2c.d | 58 + .../build/stm32f3xx_hal_i2c.lst | 25237 ++++++++++ .../BMS_Software_V1/build/stm32f3xx_hal_i2c.o | Bin 0 -> 101776 bytes .../build/stm32f3xx_hal_i2c_ex.d | 58 + .../build/stm32f3xx_hal_i2c_ex.lst | 916 + .../build/stm32f3xx_hal_i2c_ex.o | Bin 0 -> 11076 bytes .../BMS_Software_V1/build/stm32f3xx_hal_msp.d | 58 + .../build/stm32f3xx_hal_msp.lst | 1276 + .../BMS_Software_V1/build/stm32f3xx_hal_msp.o | Bin 0 -> 18888 bytes .../BMS_Software_V1/build/stm32f3xx_hal_pwr.d | 58 + .../build/stm32f3xx_hal_pwr.lst | 991 + .../BMS_Software_V1/build/stm32f3xx_hal_pwr.o | Bin 0 -> 8752 bytes .../build/stm32f3xx_hal_pwr_ex.d | 58 + .../build/stm32f3xx_hal_pwr_ex.lst | 499 + .../build/stm32f3xx_hal_pwr_ex.o | Bin 0 -> 5500 bytes .../BMS_Software_V1/build/stm32f3xx_hal_rcc.d | 58 + .../build/stm32f3xx_hal_rcc.lst | 6322 +++ .../BMS_Software_V1/build/stm32f3xx_hal_rcc.o | Bin 0 -> 28924 bytes .../build/stm32f3xx_hal_rcc_ex.d | 58 + .../build/stm32f3xx_hal_rcc_ex.lst | 4835 ++ .../build/stm32f3xx_hal_rcc_ex.o | Bin 0 -> 14460 bytes .../BMS_Software_V1/build/stm32f3xx_hal_spi.d | 58 + .../build/stm32f3xx_hal_spi.lst | 15193 ++++++ .../BMS_Software_V1/build/stm32f3xx_hal_spi.o | Bin 0 -> 60336 bytes .../build/stm32f3xx_hal_spi_ex.d | 58 + .../build/stm32f3xx_hal_spi_ex.lst | 236 + .../build/stm32f3xx_hal_spi_ex.o | Bin 0 -> 7056 bytes .../BMS_Software_V1/build/stm32f3xx_hal_tim.d | 58 + .../build/stm32f3xx_hal_tim.lst | 30 + .../BMS_Software_V1/build/stm32f3xx_hal_tim.o | Bin 0 -> 1968 bytes .../build/stm32f3xx_hal_tim_ex.d | 58 + .../build/stm32f3xx_hal_tim_ex.lst | 30 + .../build/stm32f3xx_hal_tim_ex.o | Bin 0 -> 1972 bytes .../BMS_Software_V1/build/stm32f3xx_it.d | 60 + .../BMS_Software_V1/build/stm32f3xx_it.lst | 507 + .../BMS_Software_V1/build/stm32f3xx_it.o | Bin 0 -> 8340 bytes .../BMS_Software_V1/build/syscalls.d | 1 + .../BMS_Software_V1/build/syscalls.lst | 861 + .../BMS_Software_V1/build/syscalls.o | Bin 0 -> 12744 bytes BMS_Testbench/BMS_Software_V1/build/sysmem.d | 1 + .../BMS_Software_V1/build/sysmem.lst | 230 + BMS_Testbench/BMS_Software_V1/build/sysmem.o | Bin 0 -> 4384 bytes .../BMS_Software_V1/build/system_stm32f3xx.d | 57 + .../build/system_stm32f3xx.lst | 575 + .../BMS_Software_V1/build/system_stm32f3xx.o | Bin 0 -> 6200 bytes BMS_Testbench/BMS_Software_V1/openocd.cfg | 10 + .../BMS_Software_V1/startup_stm32f302xc.s | 441 + 315 files changed, 288831 insertions(+) create mode 100644 BMS_Testbench/BMS_Software_V1/.cproject create mode 100644 BMS_Testbench/BMS_Software_V1/.mxproject create mode 100644 BMS_Testbench/BMS_Software_V1/.project create mode 100644 BMS_Testbench/BMS_Software_V1/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs create mode 100644 BMS_Testbench/BMS_Software_V1/.settings/language.settings.xml create mode 100644 BMS_Testbench/BMS_Software_V1/.settings/stm32cubeide.project.prefs create mode 100644 BMS_Testbench/BMS_Software_V1/.vscode/c_cpp_properties.json create mode 100644 BMS_Testbench/BMS_Software_V1/.vscode/launch.json create mode 100644 BMS_Testbench/BMS_Software_V1/.vscode/settings.json create mode 100644 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BMS_Testbench/BMS_Software_V1/openocd.cfg create mode 100644 BMS_Testbench/BMS_Software_V1/startup_stm32f302xc.s diff --git a/BMS_Testbench/BMS_Software_V1/.cproject b/BMS_Testbench/BMS_Software_V1/.cproject new file mode 100644 index 0000000..96da51a --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.cproject @@ -0,0 +1,329 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/.mxproject b/BMS_Testbench/BMS_Software_V1/.mxproject new file mode 100644 index 0000000..9d0b942 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.mxproject @@ -0,0 +1,25 @@ +[PreviousLibFiles] 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+ +[PreviousUsedCubeIDEFiles] +SourceFiles=Core\Src\main.c;Core\Src\stm32f3xx_it.c;Core\Src\stm32f3xx_hal_msp.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_can.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_gpio.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_dma.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_cortex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_exti.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32F3xx\Source\Templates\system_stm32f3xx.c;Core\Src\system_stm32f3xx.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_can.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_gpio.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_dma.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_cortex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_exti.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32F3xx\Source\Templates\system_stm32f3xx.c;Core\Src\system_stm32f3xx.c;;; +HeaderPath=Drivers\STM32F3xx_HAL_Driver\Inc;Drivers\STM32F3xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F3xx\Include;Drivers\CMSIS\Include;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32F302xC;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=..\Core\Inc\stm32f3xx_it.h +HeaderFiles#1=..\Core\Inc\stm32f3xx_hal_conf.h +HeaderFiles#2=..\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Core\Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=..\Core\Src\stm32f3xx_it.c +SourceFiles#1=..\Core\Src\stm32f3xx_hal_msp.c +SourceFiles#2=..\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Core\Src +SourceFiles=; + diff --git a/BMS_Testbench/BMS_Software_V1/.project b/BMS_Testbench/BMS_Software_V1/.project new file mode 100644 index 0000000..5aaff8f --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.project @@ -0,0 +1,32 @@ + + + BMS_Software + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/BMS_Testbench/BMS_Software_V1/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/BMS_Testbench/BMS_Software_V1/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs new file mode 100644 index 0000000..9a16796 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} diff --git a/BMS_Testbench/BMS_Software_V1/.settings/language.settings.xml b/BMS_Testbench/BMS_Software_V1/.settings/language.settings.xml new file mode 100644 index 0000000..d7b202f --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.settings/language.settings.xml @@ -0,0 +1,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/.settings/stm32cubeide.project.prefs b/BMS_Testbench/BMS_Software_V1/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..57775d1 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.settings/stm32cubeide.project.prefs @@ -0,0 +1,4 @@ +66BE74F758C12D739921AEA421D593D3=0 +8DF89ED150041C4CBC7CB9A9CAA90856=0331FDAB209A428E438CDF6850F54DEA +DC22A860405A8BF2F2C095E5B6529F12=0331FDAB209A428E438CDF6850F54DEA +eclipse.preferences.version=1 diff --git a/BMS_Testbench/BMS_Software_V1/.vscode/c_cpp_properties.json b/BMS_Testbench/BMS_Software_V1/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..2e9f878 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.vscode/c_cpp_properties.json @@ -0,0 +1,20 @@ +{ + "configurations": [ + { + "name": "STM32", + "includePath": [ + "Core/Inc", + "Drivers/CMSIS/Device/ST/STM32F3xx/Include", + "Drivers/CMSIS/Include", + "Drivers/STM32F3xx_HAL_Driver/Inc", + "Drivers/STM32F3xx_HAL_Driver/Inc/Legacy" + ], + "defines": [ + "STM32F302xC", + "USE_HAL_DRIVER" + ], + "compilerPath": "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/arm-none-eabi-gcc" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/.vscode/launch.json b/BMS_Testbench/BMS_Software_V1/.vscode/launch.json new file mode 100644 index 0000000..57753fd --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.vscode/launch.json @@ -0,0 +1,34 @@ +{ + "configurations": [ + { + "showDevDebugOutput": "parsed", + "cwd": "${workspaceRoot}", + "executable": "./build/ams-slave-23.elf", + "name": "Debug STM32", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "preLaunchTask": "Build STM", + "device": "stm32f302xc.s", + "configFiles": [ + "openocd.cfg" + ], + "svdFile": "STM32F102xx.svd" + }, + { + "showDevDebugOutput": "parsed", + "cwd": "${workspaceRoot}", + "executable": "./build/ams-slave-23.elf", + "name": "Attach STM32", + "request": "attach", + "type": "cortex-debug", + "servertype": "openocd", + "preLaunchTask": "Build STM", + "device": "stm32f302xc.s", + "configFiles": [ + "openocd.cfg" + ], + "svdFile": "STM32F102xx.svd" + } + ] +} \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/.vscode/settings.json b/BMS_Testbench/BMS_Software_V1/.vscode/settings.json new file mode 100644 index 0000000..93579b3 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.vscode/settings.json @@ -0,0 +1,4 @@ +{ + "cortex-debug.armToolchainPath": "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin", + "cortex-debug.openocdPath": "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/openocd/0.12.0-1.1/.content/bin/openocd" +} \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/.vscode/tasks.json b/BMS_Testbench/BMS_Software_V1/.vscode/tasks.json new file mode 100644 index 0000000..39d8d34 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/.vscode/tasks.json @@ -0,0 +1,50 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Build STM", + "type": "process", + "command": "${command:stm32-for-vscode.build}", + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + }, + { + "label": "Build Clean STM", + "type": "process", + "command": "${command:stm32-for-vscode.cleanBuild}", + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + }, + { + "label": "Flash STM", + "type": "process", + "command": "${command:stm32-for-vscode.flash}", + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + } + ] +} \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/BMS_Software Debug.launch b/BMS_Testbench/BMS_Software_V1/BMS_Software Debug.launch new file mode 100644 index 0000000..336dc5c --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/BMS_Software Debug.launch @@ -0,0 +1,78 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/BMS_Testbench/BMS_Software_V1/BMS_Software.ioc b/BMS_Testbench/BMS_Software_V1/BMS_Software.ioc new file mode 100644 index 0000000..fb83f0c --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/BMS_Software.ioc @@ -0,0 +1,199 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +CAN.ABOM=ENABLE +CAN.BS1=CAN_BS1_13TQ +CAN.BS2=CAN_BS2_2TQ +CAN.CalculateBaudRate=500000 +CAN.CalculateTimeBit=2000 +CAN.CalculateTimeQuantum=125.0 +CAN.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2,Prescaler,NART,ABOM +CAN.NART=ENABLE +CAN.Prescaler=2 +File.Version=6 +KeepUserPlacement=false +Mcu.CPN=STM32F302CCT6 +Mcu.Family=STM32F3 +Mcu.IP0=CAN +Mcu.IP1=I2C1 +Mcu.IP2=I2C2 +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=SPI1 +Mcu.IP6=SYS +Mcu.IPNb=7 +Mcu.Name=STM32F302C(B-C)Tx +Mcu.Package=LQFP48 +Mcu.Pin0=PF0-OSC_IN +Mcu.Pin1=PF1-OSC_OUT +Mcu.Pin10=PA9 +Mcu.Pin11=PA10 +Mcu.Pin12=PA11 +Mcu.Pin13=PA12 +Mcu.Pin14=PA13 +Mcu.Pin15=PA14 +Mcu.Pin16=PA15 +Mcu.Pin17=PB3 +Mcu.Pin18=PB7 +Mcu.Pin2=PA4 +Mcu.Pin3=PA5 +Mcu.Pin4=PA6 +Mcu.Pin5=PA7 +Mcu.Pin6=PB13 +Mcu.Pin7=PB14 +Mcu.Pin8=PB15 +Mcu.Pin9=PA8 +Mcu.PinsNb=19 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F302CCTx +MxCube.Version=6.7.0 +MxDb.Version=DB.6.0.70 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.USB_LP_CAN_RX0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA10.Locked=true +PA10.Mode=I2C +PA10.Signal=I2C2_SDA +PA11.Locked=true +PA11.Mode=CAN_Activate +PA11.Signal=CAN_RX +PA12.Locked=true +PA12.Mode=CAN_Activate +PA12.Signal=CAN_TX +PA13.Locked=true +PA13.Mode=Trace_Asynchronous_SW +PA13.Signal=SYS_JTMS-SWDIO +PA14.Locked=true +PA14.Mode=Trace_Asynchronous_SW +PA14.Signal=SYS_JTCK-SWCLK +PA15.GPIOParameters=GPIO_Label +PA15.GPIO_Label=TMP_SCL +PA15.Locked=true +PA15.Mode=I2C +PA15.Signal=I2C1_SCL +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=CSB +PA4.Locked=true +PA4.Signal=GPIO_Output +PA5.Locked=true +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Locked=true +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Locked=true +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI +PA8.GPIOParameters=GPIO_Label +PA8.GPIO_Label=Status_3 +PA8.Locked=true +PA8.Signal=GPIO_Output +PA9.Locked=true +PA9.Mode=I2C +PA9.Signal=I2C2_SCL +PB13.GPIOParameters=GPIO_Label +PB13.GPIO_Label=Status_0 +PB13.Locked=true +PB13.Signal=GPIO_Output +PB14.GPIOParameters=GPIO_Label +PB14.GPIO_Label=Status_1 +PB14.Locked=true +PB14.Signal=GPIO_Output +PB15.GPIOParameters=GPIO_Label +PB15.GPIO_Label=Status_2 +PB15.Locked=true +PB15.Signal=GPIO_Output +PB3.Mode=Trace_Asynchronous_SW +PB3.Signal=SYS_JTDO-TRACESWO +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=TMP_SDA +PB7.Locked=true +PB7.Mode=I2C +PB7.Signal=I2C1_SDA +PF0-OSC_IN.Mode=HSE-External-Oscillator +PF0-OSC_IN.Signal=RCC_OSC_IN +PF1-OSC_OUT.Mode=HSE-External-Oscillator +PF1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F302CCTx +ProjectManager.FirmwarePackage=STM32Cube FW_F3 V1.11.3 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=false +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain=STM32CubeIDE +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=BMS_Software.ioc +ProjectManager.ProjectName=BMS_Software +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_CAN_Init-CAN-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_I2C2_Init-I2C2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true +RCC.ADC12outputFreq_Value=32000000 +RCC.AHBFreq_Value=16000000 +RCC.APB1Freq_Value=16000000 +RCC.APB1TimFreq_Value=16000000 +RCC.APB2Freq_Value=16000000 +RCC.APB2TimFreq_Value=16000000 +RCC.CortexFreq_Value=16000000 +RCC.FCLKCortexFreq_Value=16000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=16000000 +RCC.HSEPLLFreq_Value=16000000 +RCC.HSE_VALUE=16000000 +RCC.HSIPLLFreq_Value=4000000 +RCC.HSI_VALUE=8000000 +RCC.I2C1Freq_Value=8000000 +RCC.I2C2Freq_Value=8000000 +RCC.IPParameters=ADC12outputFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSEPLLFreq_Value,HSE_VALUE,HSIPLLFreq_Value,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,LSE_VALUE,LSI_VALUE,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSourceVirtual,TIM1Freq_Value,TIM2Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOOutput2Freq_Value +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=40000 +RCC.MCOFreq_Value=16000000 +RCC.PLLCLKFreq_Value=32000000 +RCC.PLLMCOFreq_Value=16000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RTCFreq_Value=40000 +RCC.RTCHSEDivFreq_Value=500000 +RCC.SYSCLKFreq_VALUE=16000000 +RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_HSE +RCC.TIM1Freq_Value=16000000 +RCC.TIM2Freq_Value=16000000 +RCC.USART1Freq_Value=16000000 +RCC.USART2Freq_Value=16000000 +RCC.USART3Freq_Value=16000000 +RCC.USBFreq_Value=32000000 +RCC.VCOOutput2Freq_Value=16000000 +SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_32 +SPI1.CalculateBaudRate=500.0 KBits/s +SPI1.DataSize=SPI_DATASIZE_8BIT +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +board=custom +isbadioc=false diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_Abstraction.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_Abstraction.h new file mode 100644 index 0000000..ecbe692 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_Abstraction.h @@ -0,0 +1,82 @@ +/* + * ADBMS_Abstraction.h + * + * Created on: 14.07.2022 + * Author: max + */ + +#ifndef INC_ADBMS_ABSTRACTION_H_ +#define INC_ADBMS_ABSTRACTION_H_ + +#include "ADBMS_LL_Driver.h" +#include "ADBMS_CMD_MAKROS.h" +#include "main.h" + +#define MAXIMUM_CELL_VOLTAGES 18 +#define MAXIMUM_AUX_VOLTAGES 10 +#define MAXIMUM_GPIO 10 + +#define DEFAULT_UV 1562//(VUV + 1)*16*100uV Default Setting 2.5V +#define DEFAULT_OV 2625//(VOV)*16*100uV Default Setting 4.2V + +typedef struct +{ + uint16 cellVoltages[MAXIMUM_CELL_VOLTAGES]; + uint16 auxVoltages[MAXIMUM_AUX_VOLTAGES]; + + uint16 internalDieTemp; + uint16 analogSupplyVoltage; + uint16 digitalSupplyVoltage; + uint16 sumOfCellMeasurements; + uint16 refVoltage; + + uint16 GPIO_Values[MAXIMUM_GPIO]; + + uint32 overVoltage; + uint32 underVoltage; + +} Cell_Module; + + + +uint8 initAMS(SPI_HandleTypeDef* hspi, uint8 numofcells, uint8 numofaux); +uint8 amsWakeUp(); + +uint8 amsCellMeasurement(Cell_Module *module); +uint8 amsConfigCellMeasurement(uint8 numberofChannels); + +uint8 amsAuxMeasurement(Cell_Module *module); +uint8 amsConfigAuxMeasurement(uint16 Channels); + +uint8 amsInternalStatusMeasurement(Cell_Module *module); + +uint8 amsConfigGPIO(uint16 gpios); +uint8 amsSetGPIO(uint16 gpios); +uint8 readGPIO(Cell_Module* module); + +uint8 amsConfigBalancing(uint32 Channels); +uint8 amsStartBalancing(uint8 dutyCycle); +uint8 amsStopBalancing(); + +uint8 amsSelfTest(); + +uint8 amsConfigUnderVoltage(uint16 underVoltage); + +uint8 amsCheckUnderOverVoltage(Cell_Module *module); +uint8 amsConfigOverVoltage(uint16 overVoltage); + +uint8 amscheckOpenCellWire(Cell_Module *module); + +uint8 amsClearStatus(); +uint8 amsClearAux(); +uint8 amsClearCells(); + +uint8 amsSendWarning(); +uint8 amsSendError(); + +uint8 amsClearWarning(); +uint8 amsClearError(); + +uint8 amsReadCellVoltages(Cell_Module *module); + +#endif /* INC_ADBMS_ABSTRACTION_H_ */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_CMD_MAKROS.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_CMD_MAKROS.h new file mode 100644 index 0000000..9589e5c --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_CMD_MAKROS.h @@ -0,0 +1,191 @@ +/* + * ADBMS_CMD_MAKROS.h + * + * Created on: 14.07.2022 + * Author: max + */ + +#ifndef INC_ADBMS_CMD_MAKROS_H_ +#define INC_ADBMS_CMD_MAKROS_H_ + +#define WRCFGA 0x0001 //Write Configuration Register Group A +#define RDCFGA 0x0002 //Read Configuration Register Group A +#define WRCFGB 0x0024 //Write Configuration Register Group B +#define RDCFGB 0x0026 //Read Configuration Register Group B + +#define RDCVA 0x0004 //Read Cell Voltage Register Group A +#define RDCVB 0x0006 //Read Cell Voltage Register Group B +#define RDCVC 0x0008 //Read Cell Voltage Register Group C +#define RDCVD 0x000A //Read Cell Voltage Register Group D +#define RDCVE 0x0009 //Read Cell Voltage Register Group E +#define RDCVF 0x000B //Read Cell Voltage Register Group F + +#define RDAUXA 0x000C //Read Auxilliary Register Group A +#define RDAUXB 0x000E //Read Auxilliary Register Group B +#define RDAUXC 0x000D //Read Auxilliary Register Group C +#define RDAUXD 0x000F //Read Auxilliary Register Group D + +#define RDSTATA 0x0010//Read Status Register Group A +#define RDSTATB 0x0012//Read Status Register Group B + +#define WRSCTRL 0x0014 //Write S Control Register Group +#define WRPWM 0x0020//Write PWM Register Group +#define WRPSB 0x001A //Write PWM/S Control Register Group +#define RDSCTRL 0x0016 //Read S Control Register Group +#define RDPWM 0x0022//Read PWM Register Group +#define RDPSB 0x001E //Read PWM/S Control Register Group B +#define STSCTRL 0x0019 //Start S Control Pulsing and Poll Status +#define CLRSCTRL 0x0018 //Clear S Control Register Group + +#define ADCV 0x0260 //Start Cell Voltage Conversion +#define ADOW 0x0228 //Start Open Wire ADC Conversion and Poll Status +#define CVST 0x0207//Start Self Test Cell Voltage Conversion and Poll Status +#define ADOL 0x201//Start Overlap Measurement of Cell 7 and 13 Voltages +#define ADAX 0x460 //Start GPIOs ADC Conversion and Poll Status +#define ADAXD 0x400 //Start GPIOs ADC Conversion with Digital Redundancy and Poll Status +#define AXOW 0x410 //Start GPIOs Open Wire ADC Conversion and Poll Status +#define AXST 0x407 //Start Self Test GPIOs Conversion and Poll Status +#define ADSTAT 0x468 //Start Status Group ADC Conversion and Poll Status +#define ADSTATD 0x408//Start Status Group ADC Conversion with Digital Redundany and Poll Status +#define STATST 0x40F //Start Self Test Status Group Conversion and Poll Status +#define ADCVAX 0x46F//Start Combiinden Cell Voltage and GPIO 1, GPIO2, Conversion and Poll Status +#define ADCVSC 0x467//Start Combined Cell Voltage and SC Conversion and Poll Status + +#define CLRCELL 0x711//Clear Cell Voltage Register Groups +#define CLRAUX 0x712//Clear Auxiliary Register Groups +#define CLRSTAT 0x713//Clear Status Register Groups +#define PLADC 0x714//Poll ADC Conversion Status +#define DIAGN 0x715//Diagnos MUX and Poll Status +#define WRCOMM 0x721//Write COMM Register Group +#define RDCOMM 0x722//Read COMM Register Group +#define STCOMM 0x723//Start I2C/SPI Communication +#define MUTE 0x28//Mute Discharge +#define UNMUTE 0x29//Unmute Discharge + + +/*ADC Modes + * ADCOPT(CFGAR0,Bit 0) = 0 ADCOPT(CFGAR0,Bit 0) = 1 + * 00 422Hz mode 1kHz mode + * 01 27kHz mode (fast) 14kHz mode + * 10 7kHz mode (normal) 3kHz mode + * 11 26Hz mode (filtered) 2kHz mode + */ +#define MD00 (0x00<<7) +#define MD01 (0x01<<7) +#define MD10 (0x02<<7) +#define MD11 (0x03<<7) + +//Discharge Permitted if DCP = 1 +#define DCP (0x01<<4) + +/*Cell Selection for ADC Conversion + * 000: All Cells + * 001: Cells 1,7,13 + * 010: Cells 2,8,14 + * 011: Cells 3,9,15 + * 100: Cells 4,10,16 + * 101: Cells 5,11,17 + * 110: Cells 6,12,18 + */ +#define CH000 (0x00) +#define CH001 (0x01) +#define CH010 (0x02) +#define CH011 (0x03) +#define CH100 (0x04) +#define CH101 (0x05) +#define CH110 (0x06) + + +/* Pull-Up/Pull-Down Current for Open Wire Conversion + * 0 Pull down current + * 1 Pull up current + */ +#define PUP (0x01<<6) + + +/*Self Test Mode Selection + * ST01 for Self Test 1 + * ST02 for Self Test 2 + * for value consultate Datasheet + */ +#define ST01 (0x01<<5) +#define ST10 (0x02<<5) + +/* GPIO Selection for ADC Converion + * 000: GPIO1 to 5, 2nd Reference, GPIO 6 to 9 + * 001: GPIO1 and GPIO6 + * 010 GPIO2 and GPIO7 + * 011 GPIO3 and GPIO8 + * 100 GPIO4 and GPIO9 + * 101 GPIO5 + * 110 2nd Reference + */ + +#define CHG000 (0x00) +#define CHG001 (0x01) +#define CHG010 (0x02) +#define CHG011 (0x03) +#define CHG100 (0x04) +#define CHG101 (0x05) +#define CHG110 (0x06) + +/* Status Group Selection + * 000: SC,ITMP,VA,VD + * 001: SC + * 010: ITMP + * 011: VA + * 100: VD + */ + +#define CHST000 (0x00) +#define CHST001 (0x01) +#define CHST010 (0x02) +#define CHST011 (0x03) +#define CHST100 (0x04) + +#define PEC_FIELD_SIZE 2 + +#define CFG_GROUP_A_SIZE 6 +#define CFG_GROUP_B_SIZE 6 +#define CV_GROUP_A_SIZE 6 +#define CV_GROUP_B_SIZE 6 +#define CV_GROUP_C_SIZE 6 +#define CV_GROUP_D_SIZE 6 +#define CV_GROUP_E_SIZE 6 +#define CV_GROUP_F_SIZE 6 + +#define AUX_GROUP_A_SIZE 6 +#define AUX_GROUP_B_SIZE 6 +#define AUX_GROUP_C_SIZE 6 +#define AUX_GROUP_D_SIZE 6 + +#define STATUS_GROUP_A_SIZE 6 +#define STATUS_GROUP_B_SIZE 6 +#define COMM_GROUP_SIZE 6 +#define S_CONTROL_GROUP_SIZE 6 +#define PWM_GROUP_SIZE 6 +#define PWM_S_CONTROL_GROUP_B_SIZE 6 + +#define CFG_GROUP_A_ID 1 +#define CFG_GROUP_B_ID 2 +#define CV_GROUP_A_ID 3 +#define CV_GROUP_B_ID 4 +#define CV_GROUP_C_ID 5 +#define CV_GROUP_D_ID 6 +#define CV_GROUP_E_ID 7 +#define CV_GROUP_F_ID 8 + +#define AUX_GROUP_A_ID 9 +#define AUX_GROUP_B_ID 10 +#define AUX_GROUP_C_ID 11 +#define AUX_GROUP_D_ID 12 + +#define STATUS_GROUP_A_ID 13 +#define STATUS_GROUP_B_ID 14 +#define COMM_GROUP_ID 15 +#define S_CONTROL_GROUP_ID 16 +#define PWM_GROUP_ID 17 +#define PWM_S_CONTROL_GROUP_B_ID 18 + + +#endif /* INC_ADBMS_CMD_MAKROS_H_ */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_LL_Driver.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_LL_Driver.h new file mode 100644 index 0000000..d8834b3 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/ADBMS_LL_Driver.h @@ -0,0 +1,44 @@ +/* + * ADBMS_LL_Driver.h + * + * Created on: 05.06.2022 + * Author: max + */ + +#ifndef ADBMS_LL_DRIVER_H_ +#define ADBMS_LL_DRIVER_H_ + +#define TARGET_STM32 + + + +#include "main.h" + + +#ifdef TARGET_STM32 + typedef uint8_t uint8; + typedef uint16_t uint16; + typedef uint32_t uint32; +#endif + + +uint8 adbmsDriverInit(); +uint8 calculatePEC(uint8* data, uint8 datalen); +uint16 updatePEC(uint16 currentPEC, uint8 din); +uint8 checkPEC(uint8* data, uint8 datalen); + +uint8 writeCMD(uint16 command, uint8* args, uint8 arglen); +uint8 readCMD(uint16 command, uint8* buffer, uint8 buflen); + +void mcuAdbmsCSLow(); +void mcuAdbmsCSHigh(); + +uint8 mcuSPITransmit(uint8* buffer, uint8 buffersize); +uint8 mcuSPIReceive(uint8* buffer, uint8 buffersize); +uint8 mcuSPITransmitReceive(uint8* rxbuffer, uint8* txbuffer, uint8 buffersize); + +uint8 wakeUpCmd(); +void mcuDelay(uint16 delay); + + +#endif /* ADBMS_LL_DRIVER_H_ */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/AMS_CAN.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/AMS_CAN.h new file mode 100644 index 0000000..76c2ade --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/AMS_CAN.h @@ -0,0 +1,49 @@ +/* + * AMS_CAN.h + * + * Created on: Mar 19, 2022 + * Author: jasper + */ + +#ifndef INC_AMS_CAN_H_ +#define INC_AMS_CAN_H_ + +#include "main.h" + +#include "stm32f3xx_hal.h" +#include "stm32f3xx_hal_can.h" +#include "stm32f3xx_hal_def.h" + +#include + +#define CAN_ID_SLAVE_ERROR 0x001 +#define CAN_ID_CLOCK_SYNC 0x002 +#define CAN_ID_MASTER_HEARTBEAT 0x010 +#define CAN_ID_AMS_SLAVE_HEARTBEAT_BASE 0x600 +#define CAN_HEARTBEAT_TX_TIMEOUT 10 +/* ms */ +#define BMS_IN_TEST_MODE 1 // set to test the BMS use < sudo ip link set can0 up type can bitrate 500000 > // Use for Test Mode only for reducing weight of the handler +#define BMS_TEST_ID 0 + +extern CAN_HandleTypeDef* ams_can_handle; + +void ams_can_init(CAN_HandleTypeDef* ams, CAN_HandleTypeDef* car); + +void ams_can_handle_ams_msg(CAN_RxHeaderTypeDef* header, uint8_t* data); + +void ams_can_send_heartbeat(); +/** + * @brief Send an AMS Error via CAN. + * + * @param error_code The kind of error + * @param transmission_timeout How long to wait for the transmission to complete + * after starting it (in ms). Set to 0 for no wait. + */ +/*void ams_can_send_error(AMS_ErrorCode error_code, + uint32_t transmission_timeout);*/ + +HAL_StatusTypeDef ams_can_wait_for_free_mailboxes(CAN_HandleTypeDef* handle, + int num_mailboxes, + uint32_t timeout); + +#endif /* INC_AMS_CAN_H_ */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/AMS_HighLevel.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/AMS_HighLevel.h new file mode 100644 index 0000000..91f6245 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/AMS_HighLevel.h @@ -0,0 +1,46 @@ +/* + * AMS_HighLevel.h + * + * Created on: 20.07.2022 + * Author: max + */ + +#ifndef INC_AMS_HIGHLEVEL_H_ +#define INC_AMS_HIGHLEVEL_H_ + +#include "ADBMS_Abstraction.h" +#include "ADBMS_LL_Driver.h" +#include "ADBMS_CMD_MAKROS.h" + + + +typedef enum {AMSDEACTIVE, AMSIDLE, AMSCHARGING, AMSIDLEBALANCING, AMSDISCHARGING, AMSWARNING, AMSERROR} amsState; + +extern amsState currentAMSState; +extern Cell_Module module; +extern uint32_t balancedCells; +extern uint8_t BalancingActive; +extern uint8_t stateofcharge; + +extern uint8_t amserrorcode; +extern uint8_t amswarningcode; + +extern uint8_t numberofCells; +extern uint8_t numberofAux; + + +void AMS_Init(); +void AMS_Loop(); + +uint8_t AMS_Balancing_Loop(); +uint8_t AMS_Idle_Loop(); +uint8_t AMS_Warning_Loop(); +uint8_t AMS_Error_Loop(); +uint8_t AMS_Charging_Loop(); +uint8_t AMS_Discharging_Loop(); + +uint8_t writeWarningLog(uint8_t warningCode); +uint8_t writeErrorLog(uint8_t errorCode); +uint8_t integrateCurrent(); + +#endif /* INC_AMS_HIGHLEVEL_H_ */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/Testbench.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/Testbench.h new file mode 100644 index 0000000..a358abc --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/Testbench.h @@ -0,0 +1,32 @@ +/* + * Testbench.h + * + * Created on: 13.03.2023 + * Author: david + */ + +#ifndef SRC_TESTBENCH_H_ +#define SRC_TESTBENCH_H_ + +#include "main.h" + +#include "stm32f3xx_hal.h" +#include "stm32f3xx_hal_can.h" +#include "stm32f3xx_hal_def.h" +#include "ADBMS_Abstraction.h" + +#include + +extern Cell_Module module; + +#define CAN_TEST 0x1 +#define VOLTAGE_TEST 0x2 +#define TEMP_TEST 0x3 +#define EPROM_TEST 0x4 +#define BALANCING_TEST 0x5 + + + +void testLoop(uint8_t* action); + +#endif /* SRC_TESTBENCH_H_ */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/common_defs.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/common_defs.h new file mode 100644 index 0000000..4e9ac5f --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/common_defs.h @@ -0,0 +1,13 @@ +/* + * common_defs.h + * + * Created on: 23 Mar 2022 + * Author: Jasper + */ + +#ifndef INC_COMMON_DEFS_H_ +#define INC_COMMON_DEFS_H_ + +#define N_CELLS 17 + +#endif /* INC_COMMON_DEFS_H_ */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/main.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/main.h new file mode 100644 index 0000000..6ea45f8 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/main.h @@ -0,0 +1,83 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define CSB_Pin GPIO_PIN_4 +#define CSB_GPIO_Port GPIOA +#define Status_0_Pin GPIO_PIN_13 +#define Status_0_GPIO_Port GPIOB +#define Status_1_Pin GPIO_PIN_14 +#define Status_1_GPIO_Port GPIOB +#define Status_2_Pin GPIO_PIN_15 +#define Status_2_GPIO_Port GPIOB +#define Status_3_Pin GPIO_PIN_8 +#define Status_3_GPIO_Port GPIOA +#define TMP_SCL_Pin GPIO_PIN_15 +#define TMP_SCL_GPIO_Port GPIOA +#define TMP_SDA_Pin GPIO_PIN_7 +#define TMP_SDA_GPIO_Port GPIOB + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/stm32f3xx_hal_conf.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/stm32f3xx_hal_conf.h new file mode 100644 index 0000000..d2b6f92 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/stm32f3xx_hal_conf.h @@ -0,0 +1,359 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f3xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_HAL_CONF_H +#define __STM32F3xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ + +#define HAL_MODULE_ENABLED + /*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +#define HAL_CAN_MODULE_ENABLED +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_PCCARD_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_HRTIM_MODULE_ENABLED */ +/*#define HAL_OPAMP_MODULE_ENABLED */ +/*#define HAL_SDADC_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)16000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief Time out for LSE start up value in ms. + */ +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + * - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal) + * - External clock not generated on EVAL 373 + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ + +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)15) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 0 +#define DATA_CACHE_ENABLE 0 +#define USE_SPI_CRC 0U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* OPAMP register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f3xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f3xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f3xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f3xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f3xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f3xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f3xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f3xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f3xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32f3xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f3xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f3xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f3xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f3xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f3xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f3xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f3xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED + #include "stm32f3xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f3xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f3xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f3xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f3xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED + #include "stm32f3xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f3xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f3xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f3xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SDADC_MODULE_ENABLED + #include "stm32f3xx_hal_sdadc.h" +#endif /* HAL_SDADC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f3xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f3xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f3xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f3xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32f3xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f3xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f3xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f3xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_HAL_CONF_H */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Inc/stm32f3xx_it.h b/BMS_Testbench/BMS_Software_V1/Core/Inc/stm32f3xx_it.h new file mode 100644 index 0000000..ba25618 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Inc/stm32f3xx_it.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f3xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_IT_H +#define __STM32F3xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void USB_LP_CAN_RX0_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_IT_H */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/ADBMS_Abstraction.c b/BMS_Testbench/BMS_Software_V1/Core/Src/ADBMS_Abstraction.c new file mode 100644 index 0000000..607810e --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/ADBMS_Abstraction.c @@ -0,0 +1,422 @@ +/* + * ADBMS_Abstraction.c + * + * Created on: 14.07.2022 + * Author: max + */ + +#include "ADBMS_Abstraction.h" + + + +uint8 numberofcells; +uint8 numberofauxchannels; + +uint8 initAMS(SPI_HandleTypeDef* hspi, uint8 numofcells, uint8 numofaux) +{ + adbmsDriverInit(hspi); + numberofcells = numofcells; + numberofauxchannels = numofaux; + + + amsWakeUp(); + amsStopBalancing(); + amsConfigOverVoltage(DEFAULT_OV); + amsConfigUnderVoltage(DEFAULT_UV); + amsConfigAuxMeasurement(0xFFFF); + + return 0; +} + +uint8 amsWakeUp() +{ + uint8 buf[6]; + readCMD(RDCFGA, buf, 6); + return 0; +} + +uint8 amsCellMeasurement(Cell_Module *module) +{ + uint8_t rxbuffer[CV_GROUP_A_SIZE]; + writeCMD((ADCV | CH000 | MD10), rxbuffer, 0); + mcuDelay(5); + amsReadCellVoltages(module); + return 0; +} + +uint8 amsConfigCellMeasurement(uint8 numberofChannels) +{ + numberofcells = numberofChannels; + return 0; +} + +uint8 amsAuxMeasurement(Cell_Module *module) +{ + uint8 args; + uint8 rxbuf[AUX_GROUP_A_SIZE]; + writeCMD(ADAX | MD01 | CHG000, &args, 0); + + mcuDelay(5); + + readCMD(RDAUXA, rxbuf, AUX_GROUP_A_SIZE); + + module->auxVoltages[0] = rxbuf[0] | (rxbuf[1]<<8); + module->auxVoltages[1] = rxbuf[2] | (rxbuf[3]<<8); + module->auxVoltages[2] = rxbuf[4] | (rxbuf[5]<<8); + + readCMD(RDAUXB, rxbuf, AUX_GROUP_A_SIZE); + + module->auxVoltages[3] = rxbuf[0] | (rxbuf[1]<<8); + module->auxVoltages[4] = rxbuf[2] | (rxbuf[3]<<8); + module->refVoltage = rxbuf[4] | (rxbuf[5]<<8); + + readCMD(RDAUXC, rxbuf, AUX_GROUP_A_SIZE); + + module->auxVoltages[5] = rxbuf[0] | (rxbuf[1]<<8); + module->auxVoltages[6] = rxbuf[2] | (rxbuf[3]<<8); + module->auxVoltages[7] = rxbuf[4] | (rxbuf[5]<<8); + + readCMD(RDAUXD, rxbuf, AUX_GROUP_A_SIZE); + + module->auxVoltages[8] = rxbuf[0] | (rxbuf[1]<<8); + + return 0; +} + +uint8 amsInternalStatusMeasurement(Cell_Module *module) +{ + uint8 rxbuffer[STATUS_GROUP_A_SIZE]; + writeCMD(ADSTAT | MD01 | CHST000, rxbuffer, STATUS_GROUP_A_SIZE); + mcuDelay(5); + + readCMD(RDSTATA, rxbuffer, STATUS_GROUP_A_SIZE); + + module->sumOfCellMeasurements = rxbuffer[0] | (rxbuffer[1]<<8); + module->internalDieTemp = rxbuffer[2] | (rxbuffer[3]<<8); + module->analogSupplyVoltage = rxbuffer[4] | (rxbuffer[5]<<8); + + readCMD(RDSTATB, rxbuffer, STATUS_GROUP_B_SIZE); + module->digitalSupplyVoltage = rxbuffer[0] | (rxbuffer[1]<<8); + + + return 0; +} + +uint8 amsConfigAuxMeasurement(uint16 Channels) +{ + uint8 buf[CFG_GROUP_A_SIZE]; + + readCMD(RDCFGA, buf, CFG_GROUP_A_SIZE); + buf[0] |= 0xF8; + writeCMD(WRCFGA, buf, CFG_GROUP_A_SIZE); + + readCMD(RDCFGB, buf, CFG_GROUP_B_SIZE); + buf[0] |= 0x0F; + writeCMD(WRCFGB, buf, CFG_GROUP_B_SIZE); + return 0; +} + +uint8 amsConfigGPIO(uint16 gpios) +{ + return 0; +} + +uint8 amsSetGPIO(uint16 gpios) +{ + return 0; +} + +uint8 readGPIO(Cell_Module* module) +{ + return 0; +} + +uint8 amsConfigBalancing(uint32 Channels) +{ + + uint8 regbuffer[CFG_GROUP_A_SIZE]; + readCMD(RDCFGA, regbuffer, CFG_GROUP_A_SIZE); + + regbuffer[4] = Channels & 0xFF; + regbuffer[5] &= 0xF0; + regbuffer[5] |= (Channels>>8) & 0x0F; + writeCMD(WRCFGA, regbuffer, CFG_GROUP_A_SIZE); + + readCMD(RDCFGB, regbuffer, CFG_GROUP_B_SIZE); + regbuffer[0] &= 0x0F; + regbuffer[0] |= (Channels>>8) & 0xF0; + regbuffer[1] &= 0xFC; + regbuffer[1] |= 0x03 & (Channels>>16); + writeCMD(WRCFGB, regbuffer, CFG_GROUP_B_SIZE); + + return 0; +} + +uint8 amsStartBalancing(uint8 dutyCycle) +{ + writeCMD(UNMUTE, NULL, 0); + return 0; +} + +uint8 amsStopBalancing() +{ + writeCMD(MUTE, NULL, 0); + return 0; +} + +uint8 amsSelfTest() +{ + return 0; +} + + + +uint8 amsConfigUnderVoltage(uint16 underVoltage) +{ + uint8 buffer[CFG_GROUP_A_SIZE]; + readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); + + buffer[1] = (uint8) underVoltage & 0xFF; + uint8 ovuv = buffer[2] & 0xF0; + ovuv |= (uint8) (underVoltage >> 8) & 0x0F; + buffer[2] = ovuv; + + writeCMD(WRCFGA, buffer, CFG_GROUP_A_SIZE); + + return 0; +} + +uint8 amsCheckUnderOverVoltage(Cell_Module *module) +{ + uint8 regbuffer[STATUS_GROUP_B_SIZE]; + uint32 overundervoltages = 0; + readCMD(RDSTATB, regbuffer, STATUS_GROUP_B_SIZE); + overundervoltages = regbuffer[2] | (regbuffer[3]<<8) | (regbuffer[4]<<16); + module->overVoltage = 0; + module->underVoltage = 0; + for(uint8 n = 0; n < 12; n++) + { + uint8 overvolt = (overundervoltages>>(2*n+1)) & 0x01; + uint8 undervolt = (overundervoltages>>(2*n))&0x01; + + module->overVoltage |= overvolt<underVoltage |= undervolt<>(2*n+1)) & 0x01; + uint8 undervolt = (overundervoltages>>(2*n))&0x01; + + module->overVoltage |= (uint32) overvolt<<(n+12); + module->underVoltage |= (uint32) undervolt<<(n+12); + } + + + return 0; +} + +uint8 amsConfigOverVoltage(uint16 overVoltage) +{ + uint8 buffer[CFG_GROUP_B_SIZE]; + + readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); + buffer[2] &= 0x0F; + buffer[2] |= (uint8) overVoltage << 4; + buffer[3] = (uint8)(overVoltage>>4); + + writeCMD(WRCFGA, buffer, CFG_GROUP_A_SIZE); + + return 0; +} + +/* +void dumpRegister(UART_HandleTypeDef *huart, uint8 RegID, uint8* buffer) +{ + switch(RegID) + { + case CFG_GROUP_A_ID: + readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); + break; + case CFG_GROUP_B_ID: + readCMD(RDCFGB, buffer, CFG_GROUP_A_SIZE); + break; + case CV_GROUP_A_ID: + readCMD(RDCVA, buffer, CFG_GROUP_A_SIZE); + break; + case CV_GROUP_B_ID: + readCMD(RDCVB, buffer, CFG_GROUP_A_SIZE); + break; + case CV_GROUP_C_ID: + readCMD(RDCVC, buffer, CFG_GROUP_A_SIZE); + break; + case CV_GROUP_D_ID: + readCMD(RDCVD, buffer, CFG_GROUP_A_SIZE); + break; + case CV_GROUP_E_ID: + readCMD(RDCVE, buffer, CFG_GROUP_A_SIZE); + break; + case CV_GROUP_F_ID: + readCMD(RDCVF, buffer, CFG_GROUP_A_SIZE); + break; + case AUX_GROUP_A_ID: + readCMD(RDAUXA, buffer, CFG_GROUP_A_SIZE); + break; + case AUX_GROUP_B_ID: + readCMD(RDAUXB, buffer, CFG_GROUP_A_SIZE); + break; + case AUX_GROUP_C_ID: + readCMD(RDAUXC, buffer, CFG_GROUP_A_SIZE); + break; + case AUX_GROUP_D_ID: + readCMD(RDAUXD, buffer, CFG_GROUP_A_SIZE); + break; + case STATUS_GROUP_A_ID: + readCMD(RDSTATA, buffer, CFG_GROUP_A_SIZE); + break; + case STATUS_GROUP_B_ID: + readCMD(RDSTATB, buffer, CFG_GROUP_A_SIZE); + break; + case COMM_GROUP_ID: + readCMD(RDCOMM, buffer, CFG_GROUP_A_SIZE); + break; + case S_CONTROL_GROUP_ID: + readCMD(RDSCTRL, buffer, CFG_GROUP_A_SIZE); + break; + case PWM_GROUP_ID: + readCMD(RDPWM, buffer, CFG_GROUP_A_SIZE); + break; + case PWM_S_CONTROL_GROUP_B_ID: + readCMD(RDPSB, buffer, CFG_GROUP_A_SIZE); + break; + } +} +*/ + +uint8 amsClearStatus() +{ + uint8 buffer[6]; + writeCMD(CLRSTAT, buffer, 0); + return 0; +} +uint8 amsClearAux() +{ + uint8 buffer[6]; + writeCMD(CLRAUX, buffer, 0); + return 0; +} +uint8 amsClearCells() +{ + uint8 buffer[6]; + writeCMD(CLRCELL, buffer, 0); + return 0; +} + +uint8 amsSendWarning() +{ + //HAL_GPIO_WritePin(AMS_Warning_GPIO_Port, AMS_Warning_Pin, GPIO_PIN_SET); + return 0; +} + +uint8 amsSendError() +{ + //HAL_GPIO_WritePin(AMS_Error_GPIO_Port, AMS_Error_Pin, GPIO_PIN_SET); + return 0; +} + +uint8 amsClearWarning() +{ + //HAL_GPIO_WritePin(AMS_Warning_GPIO_Port, AMS_Warning_Pin, GPIO_PIN_RESET); + return 0; +} + +uint8 amsClearError() +{ + //HAL_GPIO_WritePin(AMS_Error_GPIO_Port, AMS_Error_Pin, GPIO_PIN_RESET); + return 0; +} + +uint8 amscheckOpenCellWire(Cell_Module *module) +{ + uint8 args; + uint16 cellspu[18]; + + writeCMD(ADOW |MD01|CH000|PUP , &args, 0); //run Pull Up at least Twice + HAL_Delay(5); + writeCMD(ADOW |MD01|CH000|PUP , &args, 0); //run Pull Up at least Twice + HAL_Delay(5); + + amsReadCellVoltages(module); + + for(uint8_t n = 0; n cellVoltages[n]; + } + + + writeCMD(ADOW |MD01|CH000, &args, 0); //run Pull Up at least Twice + HAL_Delay(5); + writeCMD(ADOW |MD01|CH000, &args, 0); //run Pull Up at least Twice + HAL_Delay(5); + + amsReadCellVoltages(module); + + for(uint8 n = 1; n < numberofcells; n++) + { + int dv = cellspu[n]-module->cellVoltages[n]; + if(dv < -4000) + { + return (1+n); + } + } + if((cellspu[0] == 0) || (cellspu[0] == 0xFFFF)) + { + return 1; + } + if(module->cellVoltages[numberofcells-1] == 0) + { + return 19; + } + + return 0; +} + +uint8 amsReadCellVoltages(Cell_Module *module) +{ + uint8 rxbuffer[CV_GROUP_A_SIZE]; + readCMD(RDCVA, rxbuffer, CV_GROUP_A_SIZE); + module->cellVoltages[0] = rxbuffer[0] | (rxbuffer[1]<<8); + module->cellVoltages[1] = rxbuffer[2] | (rxbuffer[3]<<8); + module->cellVoltages[2] = rxbuffer[4] | (rxbuffer[5]<<8); + + readCMD(RDCVB, rxbuffer, CV_GROUP_A_SIZE); + module->cellVoltages[3] = rxbuffer[0] | (rxbuffer[1]<<8); + module->cellVoltages[4] = rxbuffer[2] | (rxbuffer[3]<<8); + module->cellVoltages[5] = rxbuffer[4] | (rxbuffer[5]<<8); + + readCMD(RDCVC, rxbuffer, CV_GROUP_A_SIZE); + module->cellVoltages[6] = rxbuffer[0] | (rxbuffer[1]<<8); + module->cellVoltages[7] = rxbuffer[2] | (rxbuffer[3]<<8); + module->cellVoltages[8] = rxbuffer[4] | (rxbuffer[5]<<8); + + readCMD(RDCVD, rxbuffer, CV_GROUP_A_SIZE); + module->cellVoltages[9] = rxbuffer[0] | (rxbuffer[1]<<8); + module->cellVoltages[10] = rxbuffer[2] | (rxbuffer[3]<<8); + module->cellVoltages[11] = rxbuffer[4] | (rxbuffer[5]<<8); + + readCMD(RDCVE, rxbuffer, CV_GROUP_A_SIZE); + module->cellVoltages[12] = rxbuffer[0] | (rxbuffer[1]<<8); + module->cellVoltages[13] = rxbuffer[2] | (rxbuffer[3]<<8); + module->cellVoltages[14] = rxbuffer[4] | (rxbuffer[5]<<8); + + readCMD(RDCVF, rxbuffer, CV_GROUP_A_SIZE); + module->cellVoltages[15] = rxbuffer[0] | (rxbuffer[1]<<8); + module->cellVoltages[16] = rxbuffer[2] | (rxbuffer[3]<<8); + module->cellVoltages[17] = rxbuffer[4] | (rxbuffer[5]<<8); + + return 0; +} diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/ADBMS_LL_Driver.c b/BMS_Testbench/BMS_Software_V1/Core/Src/ADBMS_LL_Driver.c new file mode 100644 index 0000000..0c0faeb --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/ADBMS_LL_Driver.c @@ -0,0 +1,230 @@ +/* + * ADBMS_LL_Driver.c + * + * Created on: 05.06.2022 + * Author: max + */ +#include "ADBMS_LL_Driver.h" + + +#define INITAL_PEC 0x0010 +#define ADBMS_SPI_TIMEOUT 1000 //Timeout in ms + +SPI_HandleTypeDef* adbmsspi; + +uint8 adbmsDriverInit(SPI_HandleTypeDef* hspi) +{ + mcuAdbmsCSLow(); + HAL_Delay(1); + mcuAdbmsCSHigh(); + adbmsspi = hspi; + return 0; +} + +uint8 calculatePEC(uint8_t* data, uint8_t datalen) +{ + uint16 currentpec = INITAL_PEC; + if(datalen >= 3) + { + for(int i = 0; i < (datalen-2); i++) + { + for(int n = 0; n < 8;n++) + { + uint8 din = data[i] << (n); + currentpec = updatePEC(currentpec, din); + } + } + + data[datalen-2] = (currentpec>>7) & 0xFF; + data[datalen-1] = (currentpec<<1) & 0xFF; + return 0; + } + + else + { + return 1; + } +} + +uint8 checkPEC(uint8* data, uint8 datalen) +{ + if(datalen <= 3) + { + return 255; + } + + uint16 currentpec = INITAL_PEC; + + for(int i = 0; i < (datalen-2); i++) + { + for(int n = 0; n < 8;n++) + { + uint8 din = data[i] << (n); + currentpec = updatePEC(currentpec, din); + } + } + + uint8 pechigh = (currentpec>>7) & 0xFF; + uint8 peclow = (currentpec<<1) & 0xFF; + + if((pechigh == data[datalen-2]) && (peclow == data[datalen-1])) + { + return 0; + } + + return 1; + +} + +uint16 updatePEC(uint16 currentPEC, uint8 din) +{ + din = (din>>7) & 0x01; + uint8 in0 = din ^ ((currentPEC >> 14) &0x01); + uint8 in3 = in0 ^ ((currentPEC >> 2) &0x01); + uint8 in4 = in0 ^ ((currentPEC >> 3) &0x01); + uint8 in7 = in0 ^ ((currentPEC >> 6) &0x01); + uint8 in8 = in0 ^ ((currentPEC >> 7) &0x01); + uint8 in10 = in0 ^ ((currentPEC >> 9) &0x01); + uint8 in14 = in0 ^ ((currentPEC >> 13) &0x01); + + uint16 newPEC = 0; + + newPEC |= in14<<14; + newPEC |= (currentPEC & (0x01<<12))<<1; + newPEC |= (currentPEC & (0x01<<11))<<1; + newPEC |= (currentPEC & (0x01<<10))<<1; + newPEC |= in10<<10; + newPEC |= (currentPEC & (0x01<<8))<<1; + newPEC |= in8<<8; + newPEC |= in7<<7; + newPEC |= (currentPEC & (0x01<<5))<<1; + newPEC |= (currentPEC & (0x01<<4))<<1; + newPEC |= in4<<4; + newPEC |= in3<<3; + newPEC |= (currentPEC & (0x01<<1))<<1; + newPEC |= (currentPEC & (0x01))<<1; + newPEC |= in0; + + + return newPEC; +} + +uint8 writeCMD(uint16 command, uint8* args, uint8 arglen) +{ + if(arglen > 0) + { + uint8 buffer[6+arglen]; + buffer[0] = (command >> 8) & 0xFF; + buffer[1] = (command) & 0xFF; + calculatePEC(buffer, 4); + for(uint8 i = 0; i < arglen; i++) + { + buffer[4+i] = args[i]; + } + + calculatePEC(&buffer[4], arglen+2); //Calculate PEC of Data Part with offset of 4 Bytes for CMD and CMD PEC + + mcuAdbmsCSLow(); + mcuSPITransmit(buffer, 6+arglen); + mcuAdbmsCSHigh(); + + } + else + { + uint8 buffer[4]; + buffer[0] = (command >> 8) & 0xFF; + buffer[1] = (command) & 0xFF; + calculatePEC(buffer, 4); + + mcuAdbmsCSLow(); + + mcuSPITransmit(buffer, 4); + + mcuAdbmsCSHigh(); + } + + return 0; +} + +uint8 readCMD(uint16 command, uint8* buffer, uint8 buflen) +{ + //uint8* txbuffer = (uint8*) malloc(6+buflen); + //uint8* rxbuffer = (uint8*) malloc(6+buflen); + uint8 txbuffer[6+buflen]; + uint8 rxbuffer[6+buflen]; + + txbuffer[0] = (command >> 8) & 0xFF; + txbuffer[1] = (command) & 0xFF; + calculatePEC(txbuffer, 4); + + mcuAdbmsCSLow(); + mcuSPITransmitReceive(rxbuffer, txbuffer, 6+buflen); + mcuAdbmsCSHigh(); + + + for(uint8 i = 0; i 100) { + Error_Handler(); + } else { + return 1; + } + } + +} + +void mcuAdbmsCSLow() +{ + HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_RESET); +} + +void mcuAdbmsCSHigh() +{ + HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_SET); +} + +uint8 mcuSPITransmit(uint8* buffer, uint8 buffersize) +{ + HAL_StatusTypeDef status; + //status = HAL_SPI_Transmit(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOUT); + //uint8 *rxbuf = (uint8*) malloc(buffersize); + uint8 rxbuf[buffersize]; + status = HAL_SPI_TransmitReceive(adbmsspi, buffer, rxbuf, buffersize, ADBMS_SPI_TIMEOUT); + __HAL_SPI_CLEAR_OVRFLAG(adbmsspi); + //free(rxbuf); + return status; +} + +uint8 mcuSPIReceive(uint8* buffer, uint8 buffersize) +{ + HAL_StatusTypeDef status; + status = HAL_SPI_Receive(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOUT); + return status; +} + +uint8 mcuSPITransmitReceive(uint8* rxbuffer, uint8* txbuffer, uint8 buffersize) +{ + HAL_StatusTypeDef status; + status = HAL_SPI_TransmitReceive(adbmsspi, txbuffer, rxbuffer, buffersize, ADBMS_SPI_TIMEOUT); + return status; +} + +inline void mcuDelay(uint16 delay) +{ + HAL_Delay(delay); +} + + diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/AMS_CAN.c b/BMS_Testbench/BMS_Software_V1/Core/Src/AMS_CAN.c new file mode 100644 index 0000000..0fa145c --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/AMS_CAN.c @@ -0,0 +1,193 @@ +/* + * AMS_CAN.c + * + * Created on: Mar 19, 2022 + * Author: jasper + */ + +#include "AMS_CAN.h" + +#include "ADBMS_Abstraction.h" + + +#include "common_defs.h" +#include "main.h" +#include "AMS_HighLevel.h" +#include "stm32f3xx.h" +#include "stm32f3xx_hal.h" +#include "stm32f3xx_hal_can.h" + +#include + +int PENDING_MESSAGE_HANDLE = 0; +uint8_t canTestData[8] = {0,0,0,0,0,0,0,0}; + + +CAN_HandleTypeDef* ams_can_handle; + +void ams_can_init(CAN_HandleTypeDef* ams_handle, + CAN_HandleTypeDef* car_handle) { + ams_can_handle = ams_handle; + + // Start peripheral + if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { + ams_can_handle = car_handle; + if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { + Error_Handler(); + } + } + + // Config filter + CAN_FilterTypeDef can_filter; + can_filter.FilterActivation = CAN_FILTER_ENABLE; + can_filter.FilterBank = 0; + can_filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; + /* Message ID is in the MSBs of the FilterId register */ + can_filter.FilterIdHigh = CAN_ID_CLOCK_SYNC << (16 - 11); + can_filter.FilterIdLow = 0; + /* Filter the 11 MSBs (i.e. a StdId) */ + + if(BMS_IN_TEST_MODE == 1){ + can_filter.FilterMaskIdHigh = BMS_TEST_ID; // alleNachrichtenIds werden akzeptiert + }else{ + can_filter.FilterMaskIdHigh = 0xFFE0; + } + + can_filter.FilterMaskIdLow = 0; + can_filter.FilterMode = CAN_FILTERMODE_IDMASK; + can_filter.FilterScale = CAN_FILTERSCALE_32BIT; + can_filter.SlaveStartFilterBank = 0; + if (HAL_CAN_ConfigFilter(ams_can_handle, &can_filter) != HAL_OK) { + Error_Handler(); + } + can_filter.FilterBank++; + can_filter.FilterIdHigh = CAN_ID_MASTER_HEARTBEAT << (16 - 11); + can_filter.FilterIdLow = 0; + if (HAL_CAN_ConfigFilter(ams_can_handle, &can_filter) != HAL_OK) { + Error_Handler(); + } + + // Activate RX notifications + if (HAL_CAN_ActivateNotification(ams_can_handle, + CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { + Error_Handler(); + } +} + +static int cb_triggered = 0; + +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef* handle) { + static CAN_RxHeaderTypeDef header; + static uint8_t data[8]; + cb_triggered = 1; + + if (HAL_CAN_GetRxMessage(handle, CAN_RX_FIFO0, &header, data) != HAL_OK) { + Error_Handler(); + } + + if (handle == ams_can_handle) { + ams_can_handle_ams_msg(&header, data); + } else { + Error_Handler(); + } +} + +void ams_can_handle_ams_msg(CAN_RxHeaderTypeDef* header, uint8_t* data) { + + if(BMS_IN_TEST_MODE == 1){ + PENDING_MESSAGE_HANDLE = 1; + for(int i = 0; i < 8; i++){ + canTestData[i] = data[i]; + } + return; + } + + + if (header->IDE != CAN_ID_STD) { + return; + } + + switch (header->StdId) { + case CAN_ID_CLOCK_SYNC: +// clock_sync_handle_clock_sync_frame(data[0]); + break; + case CAN_ID_MASTER_HEARTBEAT: +// clock_sync_handle_master_heartbeat(); + break; + } +} + +void ams_can_send_heartbeat() { + static CAN_TxHeaderTypeDef header; + static uint8_t data[8]; + + header.IDE = CAN_ID_STD; + header.DLC = 8; + header.RTR = CAN_RTR_DATA; + header.TransmitGlobalTime = DISABLE; + + // Send voltages + for (int msg_id = 0; msg_id < 5; msg_id++) { + header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new format + for (int i = 0; i < 4; i++) { + int cell = msg_id * 4 + i; + uint16_t v = (cell < N_CELLS) ? module.cellVoltages[cell] : 0; + data[2 * i + 0] = v & 0xFF; + data[2 * i + 1] = v >> 8; + } + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, + CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + } + } + + // Send temperatures + /*for (int temp_msg_id = 0; temp_msg_id < 8; temp_msg_id++) { + int msg_id = temp_msg_id + 3; + header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (slave_id << 4) | msg_id; + for (int i = 0; i < 4; i++) { + int sensor = temp_msg_id * 4 + i; + uint16_t temp = temperatures[sensor]; + data[2 * i + 0] = temp & 0xFF; + data[2 * i + 1] = temp >> 8; + } + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, + CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + } + }*/ +} + +/*void ams_can_send_error(AMS_ErrorCode error_code, + uint32_t transmission_timeout) { + static CAN_TxHeaderTypeDef header; + header.IDE = CAN_ID_STD; + header.DLC = 8; + header.RTR = CAN_RTR_DATA; + header.TransmitGlobalTime = DISABLE; + header.StdId = CAN_ID_SLAVE_ERROR; + + static uint8_t data[8]; + data[0] = slave_id; + data[1] = error_code; + + HAL_CAN_AbortTxRequest(ams_can_handle, + CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2); + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + ams_can_wait_for_free_mailboxes(ams_can_handle, 3, transmission_timeout); +}*/ + +HAL_StatusTypeDef ams_can_wait_for_free_mailboxes(CAN_HandleTypeDef* handle, + int num_mailboxes, + uint32_t timeout) { + uint32_t end = HAL_GetTick() + timeout; + while (HAL_GetTick() < end) { + if (HAL_CAN_GetTxMailboxesFreeLevel(handle) >= num_mailboxes) { + return HAL_OK; + } + } + return HAL_TIMEOUT; +} diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/AMS_HighLevel.c b/BMS_Testbench/BMS_Software_V1/Core/Src/AMS_HighLevel.c new file mode 100644 index 0000000..a1aa56e --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/AMS_HighLevel.c @@ -0,0 +1,304 @@ +/* + * AMS_HighLevel.c + * + * Created on: 20.07.2022 + * Author: max + */ + + +#include "AMS_HighLevel.h" + +Cell_Module module; +uint32_t balancedCells = 0; +uint8_t BalancingActive = 0; +uint8_t stateofcharge = 100; +int64_t currentintegrator = 0; +uint32_t lastticks = 0; +uint32_t currenttick = 0; +uint8_t eepromconfigured = 0; + +uint8_t internalbalancingalgo = 1; +uint16_t startbalancingthreshold = 41000; +uint16_t stopbalancingthreshold = 30000; +uint16_t balancingvoltagedelta = 10; + + +uint16_t amsuv = 0; +uint16_t amsov = 0; + +uint8_t amserrorcode = 0; +uint8_t amswarningcode = 0; + +uint8_t numberofCells = 17; +uint8_t numberofAux = 0; + + +amsState currentAMSState = AMSDEACTIVE; +amsState lastAMSState = AMSDEACTIVE; + +void AMS_Init(SPI_HandleTypeDef *hspi) +{ + if(eepromconfigured == 1) + { + /*amsov = eepromcellovervoltage>>4; + amsuv = (eepromcellundervoltage-1)>>4; + numberofCells = eepromnumofcells; + numberofAux = eepromnumofaux; + initAMS(hspi, eepromnumofcells, eepromnumofaux);*/ + amsConfigOverVoltage(amsov); + amsConfigUnderVoltage(amsuv); + } + else + { + initAMS(hspi, numberofCells, numberofAux); + amsov = DEFAULT_OV; + amsuv = DEFAULT_UV; + } + + + currentAMSState = AMSIDLE; + + +} + +void AMS_Loop() +{ + + //On Transition Functions called ones if the State Changed + + if(currentAMSState != lastAMSState) + { + switch(currentAMSState) + { + case AMSIDLE: + break; + case AMSDEACTIVE: + break; + case AMSCHARGING: + break; + case AMSIDLEBALANCING: + break; + case AMSDISCHARGING: + break; + case AMSWARNING: + writeWarningLog(0x01); + break; + case AMSERROR: + writeErrorLog(amserrorcode); + break; + } + lastAMSState = currentAMSState; + } + + //Main Loops for different AMS States + + switch(currentAMSState) + { + case AMSIDLE: + AMS_Idle_Loop(); + break; + case AMSDEACTIVE: + break; + case AMSCHARGING: + break; + case AMSIDLEBALANCING: + AMS_Idle_Loop(); + break; + case AMSDISCHARGING: + break; + case AMSWARNING: + AMS_Warning_Loop(); + break; + case AMSERROR: + break; + } +} + +uint8_t AMS_Idle_Loop() +{ + amsWakeUp(); + amsConfigOverVoltage(amsov); + amsConfigUnderVoltage(amsuv); + amsConfigAuxMeasurement(0xFFFF); + amsClearAux(); + amsCellMeasurement(&module); + amsInternalStatusMeasurement(&module); + amsAuxMeasurement(&module); + amsCheckUnderOverVoltage(&module); + integrateCurrent(); + + static uint32_t channelstobalance = 1; + + channelstobalance = 0x1FFFF; + /* if(channelstobalance & 0x20000){ + channelstobalance = 1; + }*/ + + amsConfigBalancing(channelstobalance); + amsStartBalancing(100); + + if((module.overVoltage | module.underVoltage)) + { + //amsSendWarning(); + // currentAMSState = AMSWARNING; + } + + // AMS_Balancing_Loop(); + + /* if(BalancingActive) + { + amsStartBalancing(100); + } + else + { + amsStopBalancing(); + }*/ + //amsConfigBalancing(balancedCells); + //volatile amscheck = amscheckOpenCellWire(&module); + return 0; +} + +uint8_t AMS_Warning_Loop() +{ + + amsWakeUp(); + amsConfigOverVoltage(amsov); + amsConfigUnderVoltage(amsuv); + amsConfigAuxMeasurement(0xFFFF); + amsClearAux(); + amsCellMeasurement(&module); + amsInternalStatusMeasurement(&module); + amsAuxMeasurement(&module); + amsCheckUnderOverVoltage(&module); + + if(!(module.overVoltage | module.underVoltage)) + { + currentAMSState = AMSIDLE; + amsClearWarning(); + } + amsStopBalancing(); + + return 0; +} + +uint8_t AMS_Error_Loop() +{ + return 0; +} + +uint8_t AMS_Charging_Loop() +{ + return 0; +} + +uint8_t AMS_Discharging_Loop() +{ + return 0; +} + +uint8_t AMS_Balancing_Loop() +{ + uint8_t balancingdone = 1; + if((eepromconfigured == 1) && (internalbalancingalgo == 1) && (module.internalDieTemp<28000/*Thermal Protection 93°C*/)) //If the EEPROM is configured and the internal Balancing Algorithm should be used + { + uint16_t highestcellvoltage = module.cellVoltages[0]; + uint16_t lowestcellvoltage = module.cellVoltages[0]; + uint8_t highestcell = 0; + uint8_t lowestcell = 0; + + for(uint8_t n = 0; n < numberofCells; n++) + { + if(module.cellVoltages[n] > highestcellvoltage) + { + highestcellvoltage = module.cellVoltages[n]; + highestcell = n; + } + if(module.cellVoltages[n] < lowestcellvoltage) + { + lowestcellvoltage = module.cellVoltages[n]; + lowestcell = n; + } + } + + if(currentAMSState == AMSCHARGING) //Balancing is only Active if the BMS is in Charging Mode + { + + uint32_t channelstobalance = 0; + + if(highestcellvoltage > startbalancingthreshold) + { + for(uint8_t n = 0; n < numberofCells; n++) + { + if(module.cellVoltages[n] > stopbalancingthreshold) + { + uint16_t dv = module.cellVoltages[n]-lowestcellvoltage; + if(dv > (balancingvoltagedelta*1000)) + { + balancingdone = 0; + channelstobalance |= 1< balancingvoltagedelta) + { + balancingdone = 0; + channelstobalance |= 1< +#include "ADBMS_Abstraction.h" +#include "main.h" + + +void canTestSendTemperatures(uint16_t* data){ + static CAN_TxHeaderTypeDef header; + + header.IDE = CAN_ID_STD; + header.DLC = 8; + header.RTR = CAN_RTR_DATA; + header.TransmitGlobalTime = DISABLE; + uint8_t buffer[24]; + uint8_t tmp[8]; + + for(int i = 0; i < 12; i++){ + buffer[((i*2)+1)] = data[i] >> 8; + buffer[(i*2)] = data[i]; + } + + for(int i = 0; i < 8; i++){ + tmp[i] = buffer[i]; + } + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + } + + int m = 0; + for(int i = 8; i < 16; i++){ + tmp[m] = buffer[i]; + m++; + } + + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + } + m = 0; + for(int i = 16; i < 24; i++){ + tmp[m] = buffer[i]; + m++; + } + + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + } +} + +void canTestSendAnswer(uint8_t* data){ + static CAN_TxHeaderTypeDef header; + + header.IDE = CAN_ID_STD; + header.DLC = 8; + header.RTR = CAN_RTR_DATA; + header.TransmitGlobalTime = DISABLE; + + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, + CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + } +} + +void resetData(uint8_t* data){ + for(int i = 0; i < 8; i++){ + data[0] = 0; + } + +} +void readTemperatures(){ + uint8_t last_error = 0; + int N_SENSORS = 12; + uint16_t temperatures[N_SENSORS]; + for (int i = 0; i < N_SENSORS; i++) { + if (sensor_read(i, &temperatures[i]) != HAL_OK) { + sensor_init(i); + last_error = HAL_GetTick(); + } + } + canTestSendTemperatures(temperatures); +} + +void testLoop(uint8_t* data){ + uint8_t action = data[0]; + switch(action){ + case CAN_TEST: + HAL_Delay(100); + canTestSendAnswer(data); + break; + case VOLTAGE_TEST: + HAL_Delay(100); + amsReadCellVoltages(&module); + ams_can_send_heartbeat(); + break; + case TEMP_TEST: + HAL_Delay(1000); + readTemperatures(); + break; + case EPROM_TEST: + HAL_Delay(1000); + for(uint16_t i = 1; i < 9; i++ ){ + if(i == 4){ + writeeeprom(i*3, 0x42); + }else{ + writeeeprom(i*3, 0x69); + } + } + + HAL_Delay(1000); + for(uint16_t i = 1; i < 9; i++ ){ + data[i-1] = readeeprom(i*3); + } + canTestSendAnswer(data); + break; + case BALANCING_TEST: + HAL_Delay(1000); + for(int i = 0; i < 17; i++){ + amsConfigBalancing(0x00001<CCR1 = 0x01FF; +// HAL_TIM_Base_Start(&htim2); + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + writeeeprom(1, 69); + uint16_t temperatures[N_SENSORS]; + AMS_Loop(); + while (1){ + if(BMS_IN_TEST_MODE == 1 ){ ////&& PENDING_MESSAGE_HANDLE == 1 + testLoop(&canTestData); + /* USER CODE END WHILE */ + /* USER CODE BEGIN 3 */ + + for (int i = 0; i < N_SENSORS; i++) { + if (sensor_read(i, &temperatures[i]) != HAL_OK) { + sensor_init(i); + last_error = HAL_GetTick(); + } + } + if(BMS_IN_TEST_MODE != 1){ + ams_can_send_heartbeat(); //for testing + } + } + } + + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C2; + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; + PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief CAN Initialization Function + * @param None + * @retval None + */ +static void MX_CAN_Init(void) +{ + + /* USER CODE BEGIN CAN_Init 0 */ + + /* USER CODE END CAN_Init 0 */ + + /* USER CODE BEGIN CAN_Init 1 */ + + /* USER CODE END CAN_Init 1 */ + hcan.Instance = CAN; + hcan.Init.Prescaler = 2; + hcan.Init.Mode = CAN_MODE_NORMAL; + hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan.Init.TimeSeg1 = CAN_BS1_13TQ; + hcan.Init.TimeSeg2 = CAN_BS2_2TQ; + hcan.Init.TimeTriggeredMode = DISABLE; + hcan.Init.AutoBusOff = ENABLE; + hcan.Init.AutoWakeUp = DISABLE; + hcan.Init.AutoRetransmission = ENABLE; + hcan.Init.ReceiveFifoLocked = DISABLE; + hcan.Init.TransmitFifoPriority = DISABLE; + if (HAL_CAN_Init(&hcan) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CAN_Init 2 */ + + /* USER CODE END CAN_Init 2 */ + +} + +/** + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + + /* USER CODE BEGIN I2C1_Init 0 */ + + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + hi2c1.Init.Timing = 0x2000090E; + hi2c1.Init.OwnAddress1 = 0; + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c1.Init.OwnAddress2 = 0; + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + +/** + * @brief I2C2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C2_Init(void) +{ + + /* USER CODE BEGIN I2C2_Init 0 */ + + /* USER CODE END I2C2_Init 0 */ + + /* USER CODE BEGIN I2C2_Init 1 */ + + /* USER CODE END I2C2_Init 1 */ + hi2c2.Instance = I2C2; + hi2c2.Init.Timing = 0x2000090E; + hi2c2.Init.OwnAddress1 = 0; + hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c2.Init.OwnAddress2 = 0; + hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c2) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C2_Init 2 */ + + /* USER CODE END I2C2_Init 2 */ + +} + +/** + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 7; + hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, CSB_Pin|Status_3_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, Status_0_Pin|Status_1_Pin|Status_2_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : CSB_Pin Status_3_Pin */ + GPIO_InitStruct.Pin = CSB_Pin|Status_3_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : Status_0_Pin Status_1_Pin Status_2_Pin */ + GPIO_InitStruct.Pin = Status_0_Pin|Status_1_Pin|Status_2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ +HAL_StatusTypeDef sensor_init(int n) { + uint16_t addr = (0b1000000 | n) << 1; + uint8_t data[] = {0}; + return HAL_I2C_Master_Transmit(&hi2c1, addr, data, sizeof(data), 100); +} + +HAL_StatusTypeDef sensor_read(int n, uint16_t *res) { + uint16_t addr = (0b1000000 | n) << 1; + addr |= 1; // Read + uint8_t result[2]; + HAL_StatusTypeDef status = + HAL_I2C_Master_Receive(&hi2c1, addr, result, sizeof(result), 100); + if (status == HAL_OK) { + *res = (result[0] << 8) | result[1]; + } + return status; +} + +uint8_t readeeprom(uint16_t address){ + uint8_t data = 0; + //uint8_t* address2 = (uint8_t*) &address; + //HAL_I2C_Master_Transmit(&hi2c2, 0xA0, address2, 2, 1000); + //HAL_I2C_Master_Receive(&hi2c2, 0xA0, &data, 1, 1000); + HAL_I2C_Mem_Read(&hi2c2, 0xA0, address, 2, &data, 1 , 1000); + //HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + // uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) + return data; +} + +void writeeeprom(uint16_t address, uint8_t data){ + HAL_I2C_Mem_Write(&hi2c2, 0xA0, address, 2, &data, 1, 1000); + HAL_Delay(5); +} +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/stm32f3xx_hal_msp.c b/BMS_Testbench/BMS_Software_V1/Core/Src/stm32f3xx_hal_msp.c new file mode 100644 index 0000000..d1d6933 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/stm32f3xx_hal_msp.c @@ -0,0 +1,337 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f3xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief CAN MSP Initialization +* This function configures the hardware resources used in this example +* @param hcan: CAN handle pointer +* @retval None +*/ +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hcan->Instance==CAN) + { + /* USER CODE BEGIN CAN_MspInit 0 */ + + /* USER CODE END CAN_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CAN1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**CAN GPIO Configuration + PA11 ------> CAN_RX + PA12 ------> CAN_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_CAN; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* CAN interrupt Init */ + HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); + /* USER CODE BEGIN CAN_MspInit 1 */ + + /* USER CODE END CAN_MspInit 1 */ + } + +} + +/** +* @brief CAN MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hcan: CAN handle pointer +* @retval None +*/ +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + if(hcan->Instance==CAN) + { + /* USER CODE BEGIN CAN_MspDeInit 0 */ + + /* USER CODE END CAN_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CAN1_CLK_DISABLE(); + + /**CAN GPIO Configuration + PA11 ------> CAN_RX + PA12 ------> CAN_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + + /* CAN interrupt DeInit */ + HAL_NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn); + /* USER CODE BEGIN CAN_MspDeInit 1 */ + + /* USER CODE END CAN_MspDeInit 1 */ + } + +} + +/** +* @brief I2C MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**I2C1 GPIO Configuration + PA15 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = TMP_SCL_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(TMP_SCL_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = TMP_SDA_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + HAL_GPIO_Init(TMP_SDA_GPIO_Port, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + /* USER CODE BEGIN I2C1_MspInit 1 */ + + /* USER CODE END I2C1_MspInit 1 */ + } + else if(hi2c->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspInit 0 */ + + /* USER CODE END I2C2_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**I2C2 GPIO Configuration + PA9 ------> I2C2_SCL + PA10 ------> I2C2_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C2_CLK_ENABLE(); + /* USER CODE BEGIN I2C2_MspInit 1 */ + + /* USER CODE END I2C2_MspInit 1 */ + } + +} + +/** +* @brief I2C MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + if(hi2c->Instance==I2C1) + { + /* USER CODE BEGIN I2C1_MspDeInit 0 */ + + /* USER CODE END I2C1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /**I2C1 GPIO Configuration + PA15 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + HAL_GPIO_DeInit(TMP_SCL_GPIO_Port, TMP_SCL_Pin); + + HAL_GPIO_DeInit(TMP_SDA_GPIO_Port, TMP_SDA_Pin); + + /* USER CODE BEGIN I2C1_MspDeInit 1 */ + + /* USER CODE END I2C1_MspDeInit 1 */ + } + else if(hi2c->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspDeInit 0 */ + + /* USER CODE END I2C2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C2_CLK_DISABLE(); + + /**I2C2 GPIO Configuration + PA9 ------> I2C2_SCL + PA10 ------> I2C2_SDA + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10); + + /* USER CODE BEGIN I2C2_MspDeInit 1 */ + + /* USER CODE END I2C2_MspDeInit 1 */ + } + +} + +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/stm32f3xx_it.c b/BMS_Testbench/BMS_Software_V1/Core/Src/stm32f3xx_it.c new file mode 100644 index 0000000..182abcb --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/stm32f3xx_it.c @@ -0,0 +1,217 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f3xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f3xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern CAN_HandleTypeDef hcan; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F3xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f3xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USB low priority or CAN_RX0 interrupts. + */ +void USB_LP_CAN_RX0_IRQHandler(void) +{ + /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ + + /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan); + /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ + + /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/syscalls.c b/BMS_Testbench/BMS_Software_V1/Core/Src/syscalls.c new file mode 100644 index 0000000..f4278b7 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/sysmem.c b/BMS_Testbench/BMS_Software_V1/Core/Src/sysmem.c new file mode 100644 index 0000000..54081ac --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/BMS_Testbench/BMS_Software_V1/Core/Src/system_stm32f3xx.c b/BMS_Testbench/BMS_Software_V1/Core/Src/system_stm32f3xx.c new file mode 100644 index 0000000..495dd8d --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Src/system_stm32f3xx.c @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file system_stm32f3xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f3xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F3xx device + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * USB Clock | DISABLE + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f3xx_system + * @{ + */ + +/** @addtogroup STM32F3xx_System_Private_Includes + * @{ + */ + +#include "stm32f3xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ +uint32_t SystemCoreClock = 8000000; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * @param None + * @retval None + */ +void SystemInit(void) +{ +/* FPU settings --------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + +#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + } + else + { + /* HSI oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; + } +#else + if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + } +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/BMS_Testbench/BMS_Software_V1/Core/Startup/startup_stm32f302cctx.s b/BMS_Testbench/BMS_Software_V1/Core/Startup/startup_stm32f302cctx.s new file mode 100644 index 0000000..d946fff --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Core/Startup/startup_stm32f302cctx.s @@ -0,0 +1,441 @@ +/** + ****************************************************************************** + * @file startup_stm32f302xc.s + * @author MCD Application Team + * @brief STM32F302xB/STM32F302xC devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TSC_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN_TX_IRQHandler + .word USB_LP_CAN_RX0_IRQHandler + .word CAN_RX1_IRQHandler + .word CAN_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word 0 + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word COMP1_2_IRQHandler + .word COMP4_6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_RMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TSC_IRQHandler + .thumb_set EXTI2_TSC_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN_TX_IRQHandler + .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN_RX0_IRQHandler + .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP1_2_IRQHandler + .thumb_set COMP1_2_IRQHandler,Default_Handler + + .weak COMP4_6_IRQHandler + .thumb_set COMP4_6_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_RMP_IRQHandler + .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Debug/BMS_Software.elf b/BMS_Testbench/BMS_Software_V1/Debug/BMS_Software.elf new file mode 100755 index 0000000000000000000000000000000000000000..b53aa1676d96b00cfd03e3b27de98a854f563bd2 GIT binary patch literal 1084440 zcmeFZ3wTu3)jzz?oVlF2F_Xyv$xIR^nTTjm!$m~~Ya|$fV4;GRCfFuibOul(AchQ< z0a1ZheMM|*30kYRwY6S~+Nx2ZYF}*CHW6Df(HeX4UL6FRArr{=TYH~#GJ&A&`}KRi z|MxvR&oeV;t-bczYybA;?6vpWS$E#78bwi<@n>OU7*Us$GHoJ$D>wNWvohO67QxRL zR>%r?IuqX-M6`k>jM2xzl_+|;g{TPlS`ZKPu@eWWq`yFXB4d$G-1!jCO>Y8?kC{%1 zMmovMKZ$@uKq4R!kO)WwBmxoviGV~vA|Mfv2uK7Z0ulj=ya5sxwQp&WB2-9B2=Pi8xiq8l599`0<;2qZaZsaM%=fVH*=Y;>T zzFhl`uFuhQt}H!M`q4atZ{#)74f=S$hTPHlNuGHA$8EEs%@dxq*5?1hI{o1TETu%F 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00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00006358 08000188 08000188 00010188 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000030 080064e0 080064e0 000164e0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08006510 08006510 00020014 2**0 + CONTENTS + 4 .ARM 00000000 08006510 08006510 00020014 2**0 + CONTENTS + 5 .preinit_array 00000000 08006510 08006510 00020014 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 08006510 08006510 00016510 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08006514 08006514 00016514 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000014 20000000 08006518 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000258 20000018 0800652c 00020018 2**3 + ALLOC + 10 ._user_heap_stack 00000600 20000270 0800652c 00020270 2**0 + ALLOC + 11 .ARM.attributes 00000030 00000000 00000000 00020014 2**0 + CONTENTS, READONLY + 12 .debug_info 0000f54c 00000000 00000000 00020044 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 00002965 00000000 00000000 0002f590 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_aranges 00000cc8 00000000 00000000 00031ef8 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_ranges 00000bf0 00000000 00000000 00032bc0 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_macro 0001c25c 00000000 00000000 000337b0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_line 0000feb9 00000000 00000000 0004fa0c 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_str 000a2242 00000000 00000000 0005f8c5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .comment 00000050 00000000 00000000 00101b07 2**0 + CONTENTS, READONLY + 20 .debug_frame 000033cc 00000000 00000000 00101b58 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +08000188 <__do_global_dtors_aux>: + 8000188: b510 push {r4, lr} + 800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>) + 800018c: 7823 ldrb r3, [r4, #0] + 800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16> + 8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>) + 8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12> + 8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>) + 8000196: f3af 8000 nop.w + 800019a: 2301 movs r3, #1 + 800019c: 7023 strb r3, [r4, #0] + 800019e: bd10 pop {r4, pc} + 80001a0: 20000018 .word 0x20000018 + 80001a4: 00000000 .word 0x00000000 + 80001a8: 080064c8 .word 0x080064c8 + +080001ac : + 80001ac: b508 push {r3, lr} + 80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc ) + 80001b0: b11b cbz r3, 80001ba + 80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 ) + 80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 ) + 80001b6: f3af 8000 nop.w + 80001ba: bd08 pop {r3, pc} + 80001bc: 00000000 .word 0x00000000 + 80001c0: 2000001c .word 0x2000001c + 80001c4: 080064c8 .word 0x080064c8 + +080001c8 : + +uint8 numberofcells; +uint8 numberofauxchannels; + +uint8 initAMS(SPI_HandleTypeDef* hspi, uint8 numofcells, uint8 numofaux) +{ + 80001c8: b580 push {r7, lr} + 80001ca: b082 sub sp, #8 + 80001cc: af00 add r7, sp, #0 + 80001ce: 6078 str r0, [r7, #4] + 80001d0: 460b mov r3, r1 + 80001d2: 70fb strb r3, [r7, #3] + 80001d4: 4613 mov r3, r2 + 80001d6: 70bb strb r3, [r7, #2] + adbmsDriverInit(hspi); + 80001d8: 6878 ldr r0, [r7, #4] + 80001da: f000 fba7 bl 800092c + numberofcells = numofcells; + 80001de: 4a0d ldr r2, [pc, #52] ; (8000214 ) + 80001e0: 78fb ldrb r3, [r7, #3] + 80001e2: 7013 strb r3, [r2, #0] + numberofauxchannels = numofaux; + 80001e4: 4a0c ldr r2, [pc, #48] ; (8000218 ) + 80001e6: 78bb ldrb r3, [r7, #2] + 80001e8: 7013 strb r3, [r2, #0] + + + amsWakeUp(); + 80001ea: f000 f817 bl 800021c + amsStopBalancing(); + 80001ee: f000 f9ad bl 800054c + amsConfigOverVoltage(DEFAULT_OV); + 80001f2: f640 2041 movw r0, #2625 ; 0xa41 + 80001f6: f000 fa6e bl 80006d6 + amsConfigUnderVoltage(DEFAULT_UV); + 80001fa: f240 601a movw r0, #1562 ; 0x61a + 80001fe: f000 f9af bl 8000560 + amsConfigAuxMeasurement(0xFFFF); + 8000202: f64f 70ff movw r0, #65535 ; 0xffff + 8000206: f000 f90d bl 8000424 + + return 0; + 800020a: 2300 movs r3, #0 +} + 800020c: 4618 mov r0, r3 + 800020e: 3708 adds r7, #8 + 8000210: 46bd mov sp, r7 + 8000212: bd80 pop {r7, pc} + 8000214: 20000034 .word 0x20000034 + 8000218: 20000035 .word 0x20000035 + +0800021c : + +uint8 amsWakeUp() +{ + 800021c: b580 push {r7, lr} + 800021e: b082 sub sp, #8 + 8000220: af00 add r7, sp, #0 + uint8 buf[6]; + readCMD(RDCFGA, buf, 6); + 8000222: 463b mov r3, r7 + 8000224: 2206 movs r2, #6 + 8000226: 4619 mov r1, r3 + 8000228: 2002 movs r0, #2 + 800022a: f000 fdab bl 8000d84 + return 0; + 800022e: 2300 movs r3, #0 +} + 8000230: 4618 mov r0, r3 + 8000232: 3708 adds r7, #8 + 8000234: 46bd mov sp, r7 + 8000236: bd80 pop {r7, pc} + +08000238 : + +uint8 amsCellMeasurement(Cell_Module *module) +{ + 8000238: b580 push {r7, lr} + 800023a: b084 sub sp, #16 + 800023c: af00 add r7, sp, #0 + 800023e: 6078 str r0, [r7, #4] + uint8_t rxbuffer[CV_GROUP_A_SIZE]; + writeCMD((ADCV | CH000 | MD10), rxbuffer, 0); + 8000240: f107 0308 add.w r3, r7, #8 + 8000244: 2200 movs r2, #0 + 8000246: 4619 mov r1, r3 + 8000248: f44f 7058 mov.w r0, #864 ; 0x360 + 800024c: f000 fd11 bl 8000c72 + mcuDelay(5); + 8000250: 2005 movs r0, #5 + 8000252: f000 fecd bl 8000ff0 + amsReadCellVoltages(module); + 8000256: 6878 ldr r0, [r7, #4] + 8000258: f000 fa80 bl 800075c + return 0; + 800025c: 2300 movs r3, #0 +} + 800025e: 4618 mov r0, r3 + 8000260: 3710 adds r7, #16 + 8000262: 46bd mov sp, r7 + 8000264: bd80 pop {r7, pc} + +08000266 : + numberofcells = numberofChannels; + return 0; +} + +uint8 amsAuxMeasurement(Cell_Module *module) +{ + 8000266: b580 push {r7, lr} + 8000268: b084 sub sp, #16 + 800026a: af00 add r7, sp, #0 + 800026c: 6078 str r0, [r7, #4] + uint8 args; + uint8 rxbuf[AUX_GROUP_A_SIZE]; + writeCMD(ADAX | MD01 | CHG000, &args, 0); + 800026e: f107 030f add.w r3, r7, #15 + 8000272: 2200 movs r2, #0 + 8000274: 4619 mov r1, r3 + 8000276: f44f 609c mov.w r0, #1248 ; 0x4e0 + 800027a: f000 fcfa bl 8000c72 + + mcuDelay(5); + 800027e: 2005 movs r0, #5 + 8000280: f000 feb6 bl 8000ff0 + + readCMD(RDAUXA, rxbuf, AUX_GROUP_A_SIZE); + 8000284: f107 0308 add.w r3, r7, #8 + 8000288: 2206 movs r2, #6 + 800028a: 4619 mov r1, r3 + 800028c: 200c movs r0, #12 + 800028e: f000 fd79 bl 8000d84 + + module->auxVoltages[0] = rxbuf[0] | (rxbuf[1]<<8); + 8000292: 7a3b ldrb r3, [r7, #8] + 8000294: b21a sxth r2, r3 + 8000296: 7a7b ldrb r3, [r7, #9] + 8000298: 021b lsls r3, r3, #8 + 800029a: b21b sxth r3, r3 + 800029c: 4313 orrs r3, r2 + 800029e: b21b sxth r3, r3 + 80002a0: b29a uxth r2, r3 + 80002a2: 687b ldr r3, [r7, #4] + 80002a4: 849a strh r2, [r3, #36] ; 0x24 + module->auxVoltages[1] = rxbuf[2] | (rxbuf[3]<<8); + 80002a6: 7abb ldrb r3, [r7, #10] + 80002a8: b21a sxth r2, r3 + 80002aa: 7afb ldrb r3, [r7, #11] + 80002ac: 021b lsls r3, r3, #8 + 80002ae: b21b sxth r3, r3 + 80002b0: 4313 orrs r3, r2 + 80002b2: b21b sxth r3, r3 + 80002b4: b29a uxth r2, r3 + 80002b6: 687b ldr r3, [r7, #4] + 80002b8: 84da strh r2, [r3, #38] ; 0x26 + module->auxVoltages[2] = rxbuf[4] | (rxbuf[5]<<8); + 80002ba: 7b3b ldrb r3, [r7, #12] + 80002bc: b21a sxth r2, r3 + 80002be: 7b7b ldrb r3, [r7, #13] + 80002c0: 021b lsls r3, r3, #8 + 80002c2: b21b sxth r3, r3 + 80002c4: 4313 orrs r3, r2 + 80002c6: b21b sxth r3, r3 + 80002c8: b29a uxth r2, r3 + 80002ca: 687b ldr r3, [r7, #4] + 80002cc: 851a strh r2, [r3, #40] ; 0x28 + + readCMD(RDAUXB, rxbuf, AUX_GROUP_A_SIZE); + 80002ce: f107 0308 add.w r3, r7, #8 + 80002d2: 2206 movs r2, #6 + 80002d4: 4619 mov r1, r3 + 80002d6: 200e movs r0, #14 + 80002d8: f000 fd54 bl 8000d84 + + module->auxVoltages[3] = rxbuf[0] | (rxbuf[1]<<8); + 80002dc: 7a3b ldrb r3, [r7, #8] + 80002de: b21a sxth r2, r3 + 80002e0: 7a7b ldrb r3, [r7, #9] + 80002e2: 021b lsls r3, r3, #8 + 80002e4: b21b sxth r3, r3 + 80002e6: 4313 orrs r3, r2 + 80002e8: b21b sxth r3, r3 + 80002ea: b29a uxth r2, r3 + 80002ec: 687b ldr r3, [r7, #4] + 80002ee: 855a strh r2, [r3, #42] ; 0x2a + module->auxVoltages[4] = rxbuf[2] | (rxbuf[3]<<8); + 80002f0: 7abb ldrb r3, [r7, #10] + 80002f2: b21a sxth r2, r3 + 80002f4: 7afb ldrb r3, [r7, #11] + 80002f6: 021b lsls r3, r3, #8 + 80002f8: b21b sxth r3, r3 + 80002fa: 4313 orrs r3, r2 + 80002fc: b21b sxth r3, r3 + 80002fe: b29a uxth r2, r3 + 8000300: 687b ldr r3, [r7, #4] + 8000302: 859a strh r2, [r3, #44] ; 0x2c + module->refVoltage = rxbuf[4] | (rxbuf[5]<<8); + 8000304: 7b3b ldrb r3, [r7, #12] + 8000306: b21a sxth r2, r3 + 8000308: 7b7b ldrb r3, [r7, #13] + 800030a: 021b lsls r3, r3, #8 + 800030c: b21b sxth r3, r3 + 800030e: 4313 orrs r3, r2 + 8000310: b21b sxth r3, r3 + 8000312: b29a uxth r2, r3 + 8000314: 687b ldr r3, [r7, #4] + 8000316: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + readCMD(RDAUXC, rxbuf, AUX_GROUP_A_SIZE); + 800031a: f107 0308 add.w r3, r7, #8 + 800031e: 2206 movs r2, #6 + 8000320: 4619 mov r1, r3 + 8000322: 200d movs r0, #13 + 8000324: f000 fd2e bl 8000d84 + + module->auxVoltages[5] = rxbuf[0] | (rxbuf[1]<<8); + 8000328: 7a3b ldrb r3, [r7, #8] + 800032a: b21a sxth r2, r3 + 800032c: 7a7b ldrb r3, [r7, #9] + 800032e: 021b lsls r3, r3, #8 + 8000330: b21b sxth r3, r3 + 8000332: 4313 orrs r3, r2 + 8000334: b21b sxth r3, r3 + 8000336: b29a uxth r2, r3 + 8000338: 687b ldr r3, [r7, #4] + 800033a: 85da strh r2, [r3, #46] ; 0x2e + module->auxVoltages[6] = rxbuf[2] | (rxbuf[3]<<8); + 800033c: 7abb ldrb r3, [r7, #10] + 800033e: b21a sxth r2, r3 + 8000340: 7afb ldrb r3, [r7, #11] + 8000342: 021b lsls r3, r3, #8 + 8000344: b21b sxth r3, r3 + 8000346: 4313 orrs r3, r2 + 8000348: b21b sxth r3, r3 + 800034a: b29a uxth r2, r3 + 800034c: 687b ldr r3, [r7, #4] + 800034e: 861a strh r2, [r3, #48] ; 0x30 + module->auxVoltages[7] = rxbuf[4] | (rxbuf[5]<<8); + 8000350: 7b3b ldrb r3, [r7, #12] + 8000352: b21a sxth r2, r3 + 8000354: 7b7b ldrb r3, [r7, #13] + 8000356: 021b lsls r3, r3, #8 + 8000358: b21b sxth r3, r3 + 800035a: 4313 orrs r3, r2 + 800035c: b21b sxth r3, r3 + 800035e: b29a uxth r2, r3 + 8000360: 687b ldr r3, [r7, #4] + 8000362: 865a strh r2, [r3, #50] ; 0x32 + + readCMD(RDAUXD, rxbuf, AUX_GROUP_A_SIZE); + 8000364: f107 0308 add.w r3, r7, #8 + 8000368: 2206 movs r2, #6 + 800036a: 4619 mov r1, r3 + 800036c: 200f movs r0, #15 + 800036e: f000 fd09 bl 8000d84 + + module->auxVoltages[8] = rxbuf[0] | (rxbuf[1]<<8); + 8000372: 7a3b ldrb r3, [r7, #8] + 8000374: b21a sxth r2, r3 + 8000376: 7a7b ldrb r3, [r7, #9] + 8000378: 021b lsls r3, r3, #8 + 800037a: b21b sxth r3, r3 + 800037c: 4313 orrs r3, r2 + 800037e: b21b sxth r3, r3 + 8000380: b29a uxth r2, r3 + 8000382: 687b ldr r3, [r7, #4] + 8000384: 869a strh r2, [r3, #52] ; 0x34 + + return 0; + 8000386: 2300 movs r3, #0 +} + 8000388: 4618 mov r0, r3 + 800038a: 3710 adds r7, #16 + 800038c: 46bd mov sp, r7 + 800038e: bd80 pop {r7, pc} + +08000390 : + +uint8 amsInternalStatusMeasurement(Cell_Module *module) +{ + 8000390: b580 push {r7, lr} + 8000392: b084 sub sp, #16 + 8000394: af00 add r7, sp, #0 + 8000396: 6078 str r0, [r7, #4] + uint8 rxbuffer[STATUS_GROUP_A_SIZE]; + writeCMD(ADSTAT | MD01 | CHST000, rxbuffer, STATUS_GROUP_A_SIZE); + 8000398: f107 0308 add.w r3, r7, #8 + 800039c: 2206 movs r2, #6 + 800039e: 4619 mov r1, r3 + 80003a0: f44f 609d mov.w r0, #1256 ; 0x4e8 + 80003a4: f000 fc65 bl 8000c72 + mcuDelay(5); + 80003a8: 2005 movs r0, #5 + 80003aa: f000 fe21 bl 8000ff0 + + readCMD(RDSTATA, rxbuffer, STATUS_GROUP_A_SIZE); + 80003ae: f107 0308 add.w r3, r7, #8 + 80003b2: 2206 movs r2, #6 + 80003b4: 4619 mov r1, r3 + 80003b6: 2010 movs r0, #16 + 80003b8: f000 fce4 bl 8000d84 + + module->sumOfCellMeasurements = rxbuffer[0] | (rxbuffer[1]<<8); + 80003bc: 7a3b ldrb r3, [r7, #8] + 80003be: b21a sxth r2, r3 + 80003c0: 7a7b ldrb r3, [r7, #9] + 80003c2: 021b lsls r3, r3, #8 + 80003c4: b21b sxth r3, r3 + 80003c6: 4313 orrs r3, r2 + 80003c8: b21b sxth r3, r3 + 80003ca: b29a uxth r2, r3 + 80003cc: 687b ldr r3, [r7, #4] + 80003ce: 87da strh r2, [r3, #62] ; 0x3e + module->internalDieTemp = rxbuffer[2] | (rxbuffer[3]<<8); + 80003d0: 7abb ldrb r3, [r7, #10] + 80003d2: b21a sxth r2, r3 + 80003d4: 7afb ldrb r3, [r7, #11] + 80003d6: 021b lsls r3, r3, #8 + 80003d8: b21b sxth r3, r3 + 80003da: 4313 orrs r3, r2 + 80003dc: b21b sxth r3, r3 + 80003de: b29a uxth r2, r3 + 80003e0: 687b ldr r3, [r7, #4] + 80003e2: 871a strh r2, [r3, #56] ; 0x38 + module->analogSupplyVoltage = rxbuffer[4] | (rxbuffer[5]<<8); + 80003e4: 7b3b ldrb r3, [r7, #12] + 80003e6: b21a sxth r2, r3 + 80003e8: 7b7b ldrb r3, [r7, #13] + 80003ea: 021b lsls r3, r3, #8 + 80003ec: b21b sxth r3, r3 + 80003ee: 4313 orrs r3, r2 + 80003f0: b21b sxth r3, r3 + 80003f2: b29a uxth r2, r3 + 80003f4: 687b ldr r3, [r7, #4] + 80003f6: 875a strh r2, [r3, #58] ; 0x3a + + readCMD(RDSTATB, rxbuffer, STATUS_GROUP_B_SIZE); + 80003f8: f107 0308 add.w r3, r7, #8 + 80003fc: 2206 movs r2, #6 + 80003fe: 4619 mov r1, r3 + 8000400: 2012 movs r0, #18 + 8000402: f000 fcbf bl 8000d84 + module->digitalSupplyVoltage = rxbuffer[0] | (rxbuffer[1]<<8); + 8000406: 7a3b ldrb r3, [r7, #8] + 8000408: b21a sxth r2, r3 + 800040a: 7a7b ldrb r3, [r7, #9] + 800040c: 021b lsls r3, r3, #8 + 800040e: b21b sxth r3, r3 + 8000410: 4313 orrs r3, r2 + 8000412: b21b sxth r3, r3 + 8000414: b29a uxth r2, r3 + 8000416: 687b ldr r3, [r7, #4] + 8000418: 879a strh r2, [r3, #60] ; 0x3c + + + return 0; + 800041a: 2300 movs r3, #0 +} + 800041c: 4618 mov r0, r3 + 800041e: 3710 adds r7, #16 + 8000420: 46bd mov sp, r7 + 8000422: bd80 pop {r7, pc} + +08000424 : + +uint8 amsConfigAuxMeasurement(uint16 Channels) +{ + 8000424: b580 push {r7, lr} + 8000426: b084 sub sp, #16 + 8000428: af00 add r7, sp, #0 + 800042a: 4603 mov r3, r0 + 800042c: 80fb strh r3, [r7, #6] + uint8 buf[CFG_GROUP_A_SIZE]; + + readCMD(RDCFGA, buf, CFG_GROUP_A_SIZE); + 800042e: f107 0308 add.w r3, r7, #8 + 8000432: 2206 movs r2, #6 + 8000434: 4619 mov r1, r3 + 8000436: 2002 movs r0, #2 + 8000438: f000 fca4 bl 8000d84 + buf[0] |= 0xF8; + 800043c: 7a3b ldrb r3, [r7, #8] + 800043e: f063 0307 orn r3, r3, #7 + 8000442: b2db uxtb r3, r3 + 8000444: 723b strb r3, [r7, #8] + writeCMD(WRCFGA, buf, CFG_GROUP_A_SIZE); + 8000446: f107 0308 add.w r3, r7, #8 + 800044a: 2206 movs r2, #6 + 800044c: 4619 mov r1, r3 + 800044e: 2001 movs r0, #1 + 8000450: f000 fc0f bl 8000c72 + + readCMD(RDCFGB, buf, CFG_GROUP_B_SIZE); + 8000454: f107 0308 add.w r3, r7, #8 + 8000458: 2206 movs r2, #6 + 800045a: 4619 mov r1, r3 + 800045c: 2026 movs r0, #38 ; 0x26 + 800045e: f000 fc91 bl 8000d84 + buf[0] |= 0x0F; + 8000462: 7a3b ldrb r3, [r7, #8] + 8000464: f043 030f orr.w r3, r3, #15 + 8000468: b2db uxtb r3, r3 + 800046a: 723b strb r3, [r7, #8] + writeCMD(WRCFGB, buf, CFG_GROUP_B_SIZE); + 800046c: f107 0308 add.w r3, r7, #8 + 8000470: 2206 movs r2, #6 + 8000472: 4619 mov r1, r3 + 8000474: 2024 movs r0, #36 ; 0x24 + 8000476: f000 fbfc bl 8000c72 + return 0; + 800047a: 2300 movs r3, #0 +} + 800047c: 4618 mov r0, r3 + 800047e: 3710 adds r7, #16 + 8000480: 46bd mov sp, r7 + 8000482: bd80 pop {r7, pc} + +08000484 : +{ + return 0; +} + +uint8 amsConfigBalancing(uint32 Channels) +{ + 8000484: b580 push {r7, lr} + 8000486: b084 sub sp, #16 + 8000488: af00 add r7, sp, #0 + 800048a: 6078 str r0, [r7, #4] + + uint8 regbuffer[CFG_GROUP_A_SIZE]; + readCMD(RDCFGA, regbuffer, CFG_GROUP_A_SIZE); + 800048c: f107 0308 add.w r3, r7, #8 + 8000490: 2206 movs r2, #6 + 8000492: 4619 mov r1, r3 + 8000494: 2002 movs r0, #2 + 8000496: f000 fc75 bl 8000d84 + + regbuffer[4] = Channels & 0xFF; + 800049a: 687b ldr r3, [r7, #4] + 800049c: b2db uxtb r3, r3 + 800049e: 733b strb r3, [r7, #12] + regbuffer[5] &= 0xF0; + 80004a0: 7b7b ldrb r3, [r7, #13] + 80004a2: f023 030f bic.w r3, r3, #15 + 80004a6: b2db uxtb r3, r3 + 80004a8: 737b strb r3, [r7, #13] + regbuffer[5] |= (Channels>>8) & 0x0F; + 80004aa: 7b7a ldrb r2, [r7, #13] + 80004ac: 687b ldr r3, [r7, #4] + 80004ae: 0a1b lsrs r3, r3, #8 + 80004b0: b2db uxtb r3, r3 + 80004b2: f003 030f and.w r3, r3, #15 + 80004b6: b2db uxtb r3, r3 + 80004b8: 4313 orrs r3, r2 + 80004ba: b2db uxtb r3, r3 + 80004bc: 737b strb r3, [r7, #13] + writeCMD(WRCFGA, regbuffer, CFG_GROUP_A_SIZE); + 80004be: f107 0308 add.w r3, r7, #8 + 80004c2: 2206 movs r2, #6 + 80004c4: 4619 mov r1, r3 + 80004c6: 2001 movs r0, #1 + 80004c8: f000 fbd3 bl 8000c72 + + readCMD(RDCFGB, regbuffer, CFG_GROUP_B_SIZE); + 80004cc: f107 0308 add.w r3, r7, #8 + 80004d0: 2206 movs r2, #6 + 80004d2: 4619 mov r1, r3 + 80004d4: 2026 movs r0, #38 ; 0x26 + 80004d6: f000 fc55 bl 8000d84 + regbuffer[0] &= 0x0F; + 80004da: 7a3b ldrb r3, [r7, #8] + 80004dc: f003 030f and.w r3, r3, #15 + 80004e0: b2db uxtb r3, r3 + 80004e2: 723b strb r3, [r7, #8] + regbuffer[0] |= (Channels>>8) & 0xF0; + 80004e4: 7a3a ldrb r2, [r7, #8] + 80004e6: 687b ldr r3, [r7, #4] + 80004e8: 0a1b lsrs r3, r3, #8 + 80004ea: b2db uxtb r3, r3 + 80004ec: f023 030f bic.w r3, r3, #15 + 80004f0: b2db uxtb r3, r3 + 80004f2: 4313 orrs r3, r2 + 80004f4: b2db uxtb r3, r3 + 80004f6: 723b strb r3, [r7, #8] + regbuffer[1] &= 0xFC; + 80004f8: 7a7b ldrb r3, [r7, #9] + 80004fa: f023 0303 bic.w r3, r3, #3 + 80004fe: b2db uxtb r3, r3 + 8000500: 727b strb r3, [r7, #9] + regbuffer[1] |= 0x03 & (Channels>>16); + 8000502: 7a7a ldrb r2, [r7, #9] + 8000504: 687b ldr r3, [r7, #4] + 8000506: 0c1b lsrs r3, r3, #16 + 8000508: b2db uxtb r3, r3 + 800050a: f003 0303 and.w r3, r3, #3 + 800050e: b2db uxtb r3, r3 + 8000510: 4313 orrs r3, r2 + 8000512: b2db uxtb r3, r3 + 8000514: 727b strb r3, [r7, #9] + writeCMD(WRCFGB, regbuffer, CFG_GROUP_B_SIZE); + 8000516: f107 0308 add.w r3, r7, #8 + 800051a: 2206 movs r2, #6 + 800051c: 4619 mov r1, r3 + 800051e: 2024 movs r0, #36 ; 0x24 + 8000520: f000 fba7 bl 8000c72 + + return 0; + 8000524: 2300 movs r3, #0 +} + 8000526: 4618 mov r0, r3 + 8000528: 3710 adds r7, #16 + 800052a: 46bd mov sp, r7 + 800052c: bd80 pop {r7, pc} + +0800052e : + +uint8 amsStartBalancing(uint8 dutyCycle) +{ + 800052e: b580 push {r7, lr} + 8000530: b082 sub sp, #8 + 8000532: af00 add r7, sp, #0 + 8000534: 4603 mov r3, r0 + 8000536: 71fb strb r3, [r7, #7] + writeCMD(UNMUTE, NULL, 0); + 8000538: 2200 movs r2, #0 + 800053a: 2100 movs r1, #0 + 800053c: 2029 movs r0, #41 ; 0x29 + 800053e: f000 fb98 bl 8000c72 + return 0; + 8000542: 2300 movs r3, #0 +} + 8000544: 4618 mov r0, r3 + 8000546: 3708 adds r7, #8 + 8000548: 46bd mov sp, r7 + 800054a: bd80 pop {r7, pc} + +0800054c : + +uint8 amsStopBalancing() +{ + 800054c: b580 push {r7, lr} + 800054e: af00 add r7, sp, #0 + writeCMD(MUTE, NULL, 0); + 8000550: 2200 movs r2, #0 + 8000552: 2100 movs r1, #0 + 8000554: 2028 movs r0, #40 ; 0x28 + 8000556: f000 fb8c bl 8000c72 + return 0; + 800055a: 2300 movs r3, #0 +} + 800055c: 4618 mov r0, r3 + 800055e: bd80 pop {r7, pc} + +08000560 : +} + + + +uint8 amsConfigUnderVoltage(uint16 underVoltage) +{ + 8000560: b580 push {r7, lr} + 8000562: b084 sub sp, #16 + 8000564: af00 add r7, sp, #0 + 8000566: 4603 mov r3, r0 + 8000568: 80fb strh r3, [r7, #6] + uint8 buffer[CFG_GROUP_A_SIZE]; + readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); + 800056a: f107 0308 add.w r3, r7, #8 + 800056e: 2206 movs r2, #6 + 8000570: 4619 mov r1, r3 + 8000572: 2002 movs r0, #2 + 8000574: f000 fc06 bl 8000d84 + + buffer[1] = (uint8) underVoltage & 0xFF; + 8000578: 88fb ldrh r3, [r7, #6] + 800057a: b2db uxtb r3, r3 + 800057c: 727b strb r3, [r7, #9] + uint8 ovuv = buffer[2] & 0xF0; + 800057e: 7abb ldrb r3, [r7, #10] + 8000580: f023 030f bic.w r3, r3, #15 + 8000584: 73fb strb r3, [r7, #15] + ovuv |= (uint8) (underVoltage >> 8) & 0x0F; + 8000586: 88fb ldrh r3, [r7, #6] + 8000588: 0a1b lsrs r3, r3, #8 + 800058a: b29b uxth r3, r3 + 800058c: b25b sxtb r3, r3 + 800058e: f003 030f and.w r3, r3, #15 + 8000592: b25a sxtb r2, r3 + 8000594: f997 300f ldrsb.w r3, [r7, #15] + 8000598: 4313 orrs r3, r2 + 800059a: b25b sxtb r3, r3 + 800059c: 73fb strb r3, [r7, #15] + buffer[2] = ovuv; + 800059e: 7bfb ldrb r3, [r7, #15] + 80005a0: 72bb strb r3, [r7, #10] + + writeCMD(WRCFGA, buffer, CFG_GROUP_A_SIZE); + 80005a2: f107 0308 add.w r3, r7, #8 + 80005a6: 2206 movs r2, #6 + 80005a8: 4619 mov r1, r3 + 80005aa: 2001 movs r0, #1 + 80005ac: f000 fb61 bl 8000c72 + + return 0; + 80005b0: 2300 movs r3, #0 +} + 80005b2: 4618 mov r0, r3 + 80005b4: 3710 adds r7, #16 + 80005b6: 46bd mov sp, r7 + 80005b8: bd80 pop {r7, pc} + +080005ba : + +uint8 amsCheckUnderOverVoltage(Cell_Module *module) +{ + 80005ba: b580 push {r7, lr} + 80005bc: b088 sub sp, #32 + 80005be: af00 add r7, sp, #0 + 80005c0: 6078 str r0, [r7, #4] + uint8 regbuffer[STATUS_GROUP_B_SIZE]; + uint32 overundervoltages = 0; + 80005c2: 2300 movs r3, #0 + 80005c4: 61bb str r3, [r7, #24] + readCMD(RDSTATB, regbuffer, STATUS_GROUP_B_SIZE); + 80005c6: f107 030c add.w r3, r7, #12 + 80005ca: 2206 movs r2, #6 + 80005cc: 4619 mov r1, r3 + 80005ce: 2012 movs r0, #18 + 80005d0: f000 fbd8 bl 8000d84 + overundervoltages = regbuffer[2] | (regbuffer[3]<<8) | (regbuffer[4]<<16); + 80005d4: 7bbb ldrb r3, [r7, #14] + 80005d6: 461a mov r2, r3 + 80005d8: 7bfb ldrb r3, [r7, #15] + 80005da: 021b lsls r3, r3, #8 + 80005dc: 431a orrs r2, r3 + 80005de: 7c3b ldrb r3, [r7, #16] + 80005e0: 041b lsls r3, r3, #16 + 80005e2: 4313 orrs r3, r2 + 80005e4: 61bb str r3, [r7, #24] + module->overVoltage = 0; + 80005e6: 687b ldr r3, [r7, #4] + 80005e8: 2200 movs r2, #0 + 80005ea: 659a str r2, [r3, #88] ; 0x58 + module->underVoltage = 0; + 80005ec: 687b ldr r3, [r7, #4] + 80005ee: 2200 movs r2, #0 + 80005f0: 65da str r2, [r3, #92] ; 0x5c + for(uint8 n = 0; n < 12; n++) + 80005f2: 2300 movs r3, #0 + 80005f4: 77fb strb r3, [r7, #31] + 80005f6: e027 b.n 8000648 + { + uint8 overvolt = (overundervoltages>>(2*n+1)) & 0x01; + 80005f8: 7ffb ldrb r3, [r7, #31] + 80005fa: 005b lsls r3, r3, #1 + 80005fc: 3301 adds r3, #1 + 80005fe: 69ba ldr r2, [r7, #24] + 8000600: fa22 f303 lsr.w r3, r2, r3 + 8000604: b2db uxtb r3, r3 + 8000606: f003 0301 and.w r3, r3, #1 + 800060a: 757b strb r3, [r7, #21] + uint8 undervolt = (overundervoltages>>(2*n))&0x01; + 800060c: 7ffb ldrb r3, [r7, #31] + 800060e: 005b lsls r3, r3, #1 + 8000610: 69ba ldr r2, [r7, #24] + 8000612: fa22 f303 lsr.w r3, r2, r3 + 8000616: b2db uxtb r3, r3 + 8000618: f003 0301 and.w r3, r3, #1 + 800061c: 753b strb r3, [r7, #20] + + module->overVoltage |= overvolt<underVoltage |= undervolt< + } + + readCMD(RDAUXD,regbuffer,AUX_GROUP_D_SIZE); + 800064e: f107 030c add.w r3, r7, #12 + 8000652: 2206 movs r2, #6 + 8000654: 4619 mov r1, r3 + 8000656: 200f movs r0, #15 + 8000658: f000 fb94 bl 8000d84 + overundervoltages = 0; + 800065c: 2300 movs r3, #0 + 800065e: 61bb str r3, [r7, #24] + overundervoltages = regbuffer[4] | (regbuffer[5]<<8); + 8000660: 7c3b ldrb r3, [r7, #16] + 8000662: 461a mov r2, r3 + 8000664: 7c7b ldrb r3, [r7, #17] + 8000666: 021b lsls r3, r3, #8 + 8000668: 4313 orrs r3, r2 + 800066a: 61bb str r3, [r7, #24] + + for(uint8 n = 0; n < 6; n++) + 800066c: 2300 movs r3, #0 + 800066e: 77bb strb r3, [r7, #30] + 8000670: e029 b.n 80006c6 + { + uint8 overvolt = (overundervoltages>>(2*n+1)) & 0x01; + 8000672: 7fbb ldrb r3, [r7, #30] + 8000674: 005b lsls r3, r3, #1 + 8000676: 3301 adds r3, #1 + 8000678: 69ba ldr r2, [r7, #24] + 800067a: fa22 f303 lsr.w r3, r2, r3 + 800067e: b2db uxtb r3, r3 + 8000680: f003 0301 and.w r3, r3, #1 + 8000684: 75fb strb r3, [r7, #23] + uint8 undervolt = (overundervoltages>>(2*n))&0x01; + 8000686: 7fbb ldrb r3, [r7, #30] + 8000688: 005b lsls r3, r3, #1 + 800068a: 69ba ldr r2, [r7, #24] + 800068c: fa22 f303 lsr.w r3, r2, r3 + 8000690: b2db uxtb r3, r3 + 8000692: f003 0301 and.w r3, r3, #1 + 8000696: 75bb strb r3, [r7, #22] + + module->overVoltage |= (uint32) overvolt<<(n+12); + 8000698: 687b ldr r3, [r7, #4] + 800069a: 6d9a ldr r2, [r3, #88] ; 0x58 + 800069c: 7df9 ldrb r1, [r7, #23] + 800069e: 7fbb ldrb r3, [r7, #30] + 80006a0: 330c adds r3, #12 + 80006a2: fa01 f303 lsl.w r3, r1, r3 + 80006a6: 431a orrs r2, r3 + 80006a8: 687b ldr r3, [r7, #4] + 80006aa: 659a str r2, [r3, #88] ; 0x58 + module->underVoltage |= (uint32) undervolt<<(n+12); + 80006ac: 687b ldr r3, [r7, #4] + 80006ae: 6dda ldr r2, [r3, #92] ; 0x5c + 80006b0: 7db9 ldrb r1, [r7, #22] + 80006b2: 7fbb ldrb r3, [r7, #30] + 80006b4: 330c adds r3, #12 + 80006b6: fa01 f303 lsl.w r3, r1, r3 + 80006ba: 431a orrs r2, r3 + 80006bc: 687b ldr r3, [r7, #4] + 80006be: 65da str r2, [r3, #92] ; 0x5c + for(uint8 n = 0; n < 6; n++) + 80006c0: 7fbb ldrb r3, [r7, #30] + 80006c2: 3301 adds r3, #1 + 80006c4: 77bb strb r3, [r7, #30] + 80006c6: 7fbb ldrb r3, [r7, #30] + 80006c8: 2b05 cmp r3, #5 + 80006ca: d9d2 bls.n 8000672 + } + + + return 0; + 80006cc: 2300 movs r3, #0 +} + 80006ce: 4618 mov r0, r3 + 80006d0: 3720 adds r7, #32 + 80006d2: 46bd mov sp, r7 + 80006d4: bd80 pop {r7, pc} + +080006d6 : + +uint8 amsConfigOverVoltage(uint16 overVoltage) +{ + 80006d6: b580 push {r7, lr} + 80006d8: b084 sub sp, #16 + 80006da: af00 add r7, sp, #0 + 80006dc: 4603 mov r3, r0 + 80006de: 80fb strh r3, [r7, #6] + uint8 buffer[CFG_GROUP_B_SIZE]; + + readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); + 80006e0: f107 0308 add.w r3, r7, #8 + 80006e4: 2206 movs r2, #6 + 80006e6: 4619 mov r1, r3 + 80006e8: 2002 movs r0, #2 + 80006ea: f000 fb4b bl 8000d84 + buffer[2] &= 0x0F; + 80006ee: 7abb ldrb r3, [r7, #10] + 80006f0: f003 030f and.w r3, r3, #15 + 80006f4: b2db uxtb r3, r3 + 80006f6: 72bb strb r3, [r7, #10] + buffer[2] |= (uint8) overVoltage << 4; + 80006f8: 7abb ldrb r3, [r7, #10] + 80006fa: b25a sxtb r2, r3 + 80006fc: 88fb ldrh r3, [r7, #6] + 80006fe: b2db uxtb r3, r3 + 8000700: 011b lsls r3, r3, #4 + 8000702: b25b sxtb r3, r3 + 8000704: 4313 orrs r3, r2 + 8000706: b25b sxtb r3, r3 + 8000708: b2db uxtb r3, r3 + 800070a: 72bb strb r3, [r7, #10] + buffer[3] = (uint8)(overVoltage>>4); + 800070c: 88fb ldrh r3, [r7, #6] + 800070e: 091b lsrs r3, r3, #4 + 8000710: b29b uxth r3, r3 + 8000712: b2db uxtb r3, r3 + 8000714: 72fb strb r3, [r7, #11] + + writeCMD(WRCFGA, buffer, CFG_GROUP_A_SIZE); + 8000716: f107 0308 add.w r3, r7, #8 + 800071a: 2206 movs r2, #6 + 800071c: 4619 mov r1, r3 + 800071e: 2001 movs r0, #1 + 8000720: f000 faa7 bl 8000c72 + + return 0; + 8000724: 2300 movs r3, #0 +} + 8000726: 4618 mov r0, r3 + 8000728: 3710 adds r7, #16 + 800072a: 46bd mov sp, r7 + 800072c: bd80 pop {r7, pc} + +0800072e : + uint8 buffer[6]; + writeCMD(CLRSTAT, buffer, 0); + return 0; +} +uint8 amsClearAux() +{ + 800072e: b580 push {r7, lr} + 8000730: b082 sub sp, #8 + 8000732: af00 add r7, sp, #0 + uint8 buffer[6]; + writeCMD(CLRAUX, buffer, 0); + 8000734: 463b mov r3, r7 + 8000736: 2200 movs r2, #0 + 8000738: 4619 mov r1, r3 + 800073a: f240 7012 movw r0, #1810 ; 0x712 + 800073e: f000 fa98 bl 8000c72 + return 0; + 8000742: 2300 movs r3, #0 +} + 8000744: 4618 mov r0, r3 + 8000746: 3708 adds r7, #8 + 8000748: 46bd mov sp, r7 + 800074a: bd80 pop {r7, pc} + +0800074c : + //HAL_GPIO_WritePin(AMS_Error_GPIO_Port, AMS_Error_Pin, GPIO_PIN_SET); + return 0; +} + +uint8 amsClearWarning() +{ + 800074c: b480 push {r7} + 800074e: af00 add r7, sp, #0 + //HAL_GPIO_WritePin(AMS_Warning_GPIO_Port, AMS_Warning_Pin, GPIO_PIN_RESET); + return 0; + 8000750: 2300 movs r3, #0 +} + 8000752: 4618 mov r0, r3 + 8000754: 46bd mov sp, r7 + 8000756: f85d 7b04 ldr.w r7, [sp], #4 + 800075a: 4770 bx lr + +0800075c : + + return 0; +} + +uint8 amsReadCellVoltages(Cell_Module *module) +{ + 800075c: b580 push {r7, lr} + 800075e: b084 sub sp, #16 + 8000760: af00 add r7, sp, #0 + 8000762: 6078 str r0, [r7, #4] + uint8 rxbuffer[CV_GROUP_A_SIZE]; + readCMD(RDCVA, rxbuffer, CV_GROUP_A_SIZE); + 8000764: f107 0308 add.w r3, r7, #8 + 8000768: 2206 movs r2, #6 + 800076a: 4619 mov r1, r3 + 800076c: 2004 movs r0, #4 + 800076e: f000 fb09 bl 8000d84 + module->cellVoltages[0] = rxbuffer[0] | (rxbuffer[1]<<8); + 8000772: 7a3b ldrb r3, [r7, #8] + 8000774: b21a sxth r2, r3 + 8000776: 7a7b ldrb r3, [r7, #9] + 8000778: 021b lsls r3, r3, #8 + 800077a: b21b sxth r3, r3 + 800077c: 4313 orrs r3, r2 + 800077e: b21b sxth r3, r3 + 8000780: b29a uxth r2, r3 + 8000782: 687b ldr r3, [r7, #4] + 8000784: 801a strh r2, [r3, #0] + module->cellVoltages[1] = rxbuffer[2] | (rxbuffer[3]<<8); + 8000786: 7abb ldrb r3, [r7, #10] + 8000788: b21a sxth r2, r3 + 800078a: 7afb ldrb r3, [r7, #11] + 800078c: 021b lsls r3, r3, #8 + 800078e: b21b sxth r3, r3 + 8000790: 4313 orrs r3, r2 + 8000792: b21b sxth r3, r3 + 8000794: b29a uxth r2, r3 + 8000796: 687b ldr r3, [r7, #4] + 8000798: 805a strh r2, [r3, #2] + module->cellVoltages[2] = rxbuffer[4] | (rxbuffer[5]<<8); + 800079a: 7b3b ldrb r3, [r7, #12] + 800079c: b21a sxth r2, r3 + 800079e: 7b7b ldrb r3, [r7, #13] + 80007a0: 021b lsls r3, r3, #8 + 80007a2: b21b sxth r3, r3 + 80007a4: 4313 orrs r3, r2 + 80007a6: b21b sxth r3, r3 + 80007a8: b29a uxth r2, r3 + 80007aa: 687b ldr r3, [r7, #4] + 80007ac: 809a strh r2, [r3, #4] + + readCMD(RDCVB, rxbuffer, CV_GROUP_A_SIZE); + 80007ae: f107 0308 add.w r3, r7, #8 + 80007b2: 2206 movs r2, #6 + 80007b4: 4619 mov r1, r3 + 80007b6: 2006 movs r0, #6 + 80007b8: f000 fae4 bl 8000d84 + module->cellVoltages[3] = rxbuffer[0] | (rxbuffer[1]<<8); + 80007bc: 7a3b ldrb r3, [r7, #8] + 80007be: b21a sxth r2, r3 + 80007c0: 7a7b ldrb r3, [r7, #9] + 80007c2: 021b lsls r3, r3, #8 + 80007c4: b21b sxth r3, r3 + 80007c6: 4313 orrs r3, r2 + 80007c8: b21b sxth r3, r3 + 80007ca: b29a uxth r2, r3 + 80007cc: 687b ldr r3, [r7, #4] + 80007ce: 80da strh r2, [r3, #6] + module->cellVoltages[4] = rxbuffer[2] | (rxbuffer[3]<<8); + 80007d0: 7abb ldrb r3, [r7, #10] + 80007d2: b21a sxth r2, r3 + 80007d4: 7afb ldrb r3, [r7, #11] + 80007d6: 021b lsls r3, r3, #8 + 80007d8: b21b sxth r3, r3 + 80007da: 4313 orrs r3, r2 + 80007dc: b21b sxth r3, r3 + 80007de: b29a uxth r2, r3 + 80007e0: 687b ldr r3, [r7, #4] + 80007e2: 811a strh r2, [r3, #8] + module->cellVoltages[5] = rxbuffer[4] | (rxbuffer[5]<<8); + 80007e4: 7b3b ldrb r3, [r7, #12] + 80007e6: b21a sxth r2, r3 + 80007e8: 7b7b ldrb r3, [r7, #13] + 80007ea: 021b lsls r3, r3, #8 + 80007ec: b21b sxth r3, r3 + 80007ee: 4313 orrs r3, r2 + 80007f0: b21b sxth r3, r3 + 80007f2: b29a uxth r2, r3 + 80007f4: 687b ldr r3, [r7, #4] + 80007f6: 815a strh r2, [r3, #10] + + readCMD(RDCVC, rxbuffer, CV_GROUP_A_SIZE); + 80007f8: f107 0308 add.w r3, r7, #8 + 80007fc: 2206 movs r2, #6 + 80007fe: 4619 mov r1, r3 + 8000800: 2008 movs r0, #8 + 8000802: f000 fabf bl 8000d84 + module->cellVoltages[6] = rxbuffer[0] | (rxbuffer[1]<<8); + 8000806: 7a3b ldrb r3, [r7, #8] + 8000808: b21a sxth r2, r3 + 800080a: 7a7b ldrb r3, [r7, #9] + 800080c: 021b lsls r3, r3, #8 + 800080e: b21b sxth r3, r3 + 8000810: 4313 orrs r3, r2 + 8000812: b21b sxth r3, r3 + 8000814: b29a uxth r2, r3 + 8000816: 687b ldr r3, [r7, #4] + 8000818: 819a strh r2, [r3, #12] + module->cellVoltages[7] = rxbuffer[2] | (rxbuffer[3]<<8); + 800081a: 7abb ldrb r3, [r7, #10] + 800081c: b21a sxth r2, r3 + 800081e: 7afb ldrb r3, [r7, #11] + 8000820: 021b lsls r3, r3, #8 + 8000822: b21b sxth r3, r3 + 8000824: 4313 orrs r3, r2 + 8000826: b21b sxth r3, r3 + 8000828: b29a uxth r2, r3 + 800082a: 687b ldr r3, [r7, #4] + 800082c: 81da strh r2, [r3, #14] + module->cellVoltages[8] = rxbuffer[4] | (rxbuffer[5]<<8); + 800082e: 7b3b ldrb r3, [r7, #12] + 8000830: b21a sxth r2, r3 + 8000832: 7b7b ldrb r3, [r7, #13] + 8000834: 021b lsls r3, r3, #8 + 8000836: b21b sxth r3, r3 + 8000838: 4313 orrs r3, r2 + 800083a: b21b sxth r3, r3 + 800083c: b29a uxth r2, r3 + 800083e: 687b ldr r3, [r7, #4] + 8000840: 821a strh r2, [r3, #16] + + readCMD(RDCVD, rxbuffer, CV_GROUP_A_SIZE); + 8000842: f107 0308 add.w r3, r7, #8 + 8000846: 2206 movs r2, #6 + 8000848: 4619 mov r1, r3 + 800084a: 200a movs r0, #10 + 800084c: f000 fa9a bl 8000d84 + module->cellVoltages[9] = rxbuffer[0] | (rxbuffer[1]<<8); + 8000850: 7a3b ldrb r3, [r7, #8] + 8000852: b21a sxth r2, r3 + 8000854: 7a7b ldrb r3, [r7, #9] + 8000856: 021b lsls r3, r3, #8 + 8000858: b21b sxth r3, r3 + 800085a: 4313 orrs r3, r2 + 800085c: b21b sxth r3, r3 + 800085e: b29a uxth r2, r3 + 8000860: 687b ldr r3, [r7, #4] + 8000862: 825a strh r2, [r3, #18] + module->cellVoltages[10] = rxbuffer[2] | (rxbuffer[3]<<8); + 8000864: 7abb ldrb r3, [r7, #10] + 8000866: b21a sxth r2, r3 + 8000868: 7afb ldrb r3, [r7, #11] + 800086a: 021b lsls r3, r3, #8 + 800086c: b21b sxth r3, r3 + 800086e: 4313 orrs r3, r2 + 8000870: b21b sxth r3, r3 + 8000872: b29a uxth r2, r3 + 8000874: 687b ldr r3, [r7, #4] + 8000876: 829a strh r2, [r3, #20] + module->cellVoltages[11] = rxbuffer[4] | (rxbuffer[5]<<8); + 8000878: 7b3b ldrb r3, [r7, #12] + 800087a: b21a sxth r2, r3 + 800087c: 7b7b ldrb r3, [r7, #13] + 800087e: 021b lsls r3, r3, #8 + 8000880: b21b sxth r3, r3 + 8000882: 4313 orrs r3, r2 + 8000884: b21b sxth r3, r3 + 8000886: b29a uxth r2, r3 + 8000888: 687b ldr r3, [r7, #4] + 800088a: 82da strh r2, [r3, #22] + + readCMD(RDCVE, rxbuffer, CV_GROUP_A_SIZE); + 800088c: f107 0308 add.w r3, r7, #8 + 8000890: 2206 movs r2, #6 + 8000892: 4619 mov r1, r3 + 8000894: 2009 movs r0, #9 + 8000896: f000 fa75 bl 8000d84 + module->cellVoltages[12] = rxbuffer[0] | (rxbuffer[1]<<8); + 800089a: 7a3b ldrb r3, [r7, #8] + 800089c: b21a sxth r2, r3 + 800089e: 7a7b ldrb r3, [r7, #9] + 80008a0: 021b lsls r3, r3, #8 + 80008a2: b21b sxth r3, r3 + 80008a4: 4313 orrs r3, r2 + 80008a6: b21b sxth r3, r3 + 80008a8: b29a uxth r2, r3 + 80008aa: 687b ldr r3, [r7, #4] + 80008ac: 831a strh r2, [r3, #24] + module->cellVoltages[13] = rxbuffer[2] | (rxbuffer[3]<<8); + 80008ae: 7abb ldrb r3, [r7, #10] + 80008b0: b21a sxth r2, r3 + 80008b2: 7afb ldrb r3, [r7, #11] + 80008b4: 021b lsls r3, r3, #8 + 80008b6: b21b sxth r3, r3 + 80008b8: 4313 orrs r3, r2 + 80008ba: b21b sxth r3, r3 + 80008bc: b29a uxth r2, r3 + 80008be: 687b ldr r3, [r7, #4] + 80008c0: 835a strh r2, [r3, #26] + module->cellVoltages[14] = rxbuffer[4] | (rxbuffer[5]<<8); + 80008c2: 7b3b ldrb r3, [r7, #12] + 80008c4: b21a sxth r2, r3 + 80008c6: 7b7b ldrb r3, [r7, #13] + 80008c8: 021b lsls r3, r3, #8 + 80008ca: b21b sxth r3, r3 + 80008cc: 4313 orrs r3, r2 + 80008ce: b21b sxth r3, r3 + 80008d0: b29a uxth r2, r3 + 80008d2: 687b ldr r3, [r7, #4] + 80008d4: 839a strh r2, [r3, #28] + + readCMD(RDCVF, rxbuffer, CV_GROUP_A_SIZE); + 80008d6: f107 0308 add.w r3, r7, #8 + 80008da: 2206 movs r2, #6 + 80008dc: 4619 mov r1, r3 + 80008de: 200b movs r0, #11 + 80008e0: f000 fa50 bl 8000d84 + module->cellVoltages[15] = rxbuffer[0] | (rxbuffer[1]<<8); + 80008e4: 7a3b ldrb r3, [r7, #8] + 80008e6: b21a sxth r2, r3 + 80008e8: 7a7b ldrb r3, [r7, #9] + 80008ea: 021b lsls r3, r3, #8 + 80008ec: b21b sxth r3, r3 + 80008ee: 4313 orrs r3, r2 + 80008f0: b21b sxth r3, r3 + 80008f2: b29a uxth r2, r3 + 80008f4: 687b ldr r3, [r7, #4] + 80008f6: 83da strh r2, [r3, #30] + module->cellVoltages[16] = rxbuffer[2] | (rxbuffer[3]<<8); + 80008f8: 7abb ldrb r3, [r7, #10] + 80008fa: b21a sxth r2, r3 + 80008fc: 7afb ldrb r3, [r7, #11] + 80008fe: 021b lsls r3, r3, #8 + 8000900: b21b sxth r3, r3 + 8000902: 4313 orrs r3, r2 + 8000904: b21b sxth r3, r3 + 8000906: b29a uxth r2, r3 + 8000908: 687b ldr r3, [r7, #4] + 800090a: 841a strh r2, [r3, #32] + module->cellVoltages[17] = rxbuffer[4] | (rxbuffer[5]<<8); + 800090c: 7b3b ldrb r3, [r7, #12] + 800090e: b21a sxth r2, r3 + 8000910: 7b7b ldrb r3, [r7, #13] + 8000912: 021b lsls r3, r3, #8 + 8000914: b21b sxth r3, r3 + 8000916: 4313 orrs r3, r2 + 8000918: b21b sxth r3, r3 + 800091a: b29a uxth r2, r3 + 800091c: 687b ldr r3, [r7, #4] + 800091e: 845a strh r2, [r3, #34] ; 0x22 + + return 0; + 8000920: 2300 movs r3, #0 +} + 8000922: 4618 mov r0, r3 + 8000924: 3710 adds r7, #16 + 8000926: 46bd mov sp, r7 + 8000928: bd80 pop {r7, pc} + ... + +0800092c : +#define ADBMS_SPI_TIMEOUT 1000 //Timeout in ms + +SPI_HandleTypeDef* adbmsspi; + +uint8 adbmsDriverInit(SPI_HandleTypeDef* hspi) +{ + 800092c: b580 push {r7, lr} + 800092e: b082 sub sp, #8 + 8000930: af00 add r7, sp, #0 + 8000932: 6078 str r0, [r7, #4] + mcuAdbmsCSLow(); + 8000934: f000 fad8 bl 8000ee8 + HAL_Delay(1); + 8000938: 2001 movs r0, #1 + 800093a: f001 fc9f bl 800227c + mcuAdbmsCSHigh(); + 800093e: f000 fadd bl 8000efc + adbmsspi = hspi; + 8000942: 4a04 ldr r2, [pc, #16] ; (8000954 ) + 8000944: 687b ldr r3, [r7, #4] + 8000946: 6013 str r3, [r2, #0] + return 0; + 8000948: 2300 movs r3, #0 +} + 800094a: 4618 mov r0, r3 + 800094c: 3708 adds r7, #8 + 800094e: 46bd mov sp, r7 + 8000950: bd80 pop {r7, pc} + 8000952: bf00 nop + 8000954: 20000038 .word 0x20000038 + +08000958 : + +uint8 calculatePEC(uint8_t* data, uint8_t datalen) +{ + 8000958: b580 push {r7, lr} + 800095a: b086 sub sp, #24 + 800095c: af00 add r7, sp, #0 + 800095e: 6078 str r0, [r7, #4] + 8000960: 460b mov r3, r1 + 8000962: 70fb strb r3, [r7, #3] + uint16 currentpec = INITAL_PEC; + 8000964: 2310 movs r3, #16 + 8000966: 82fb strh r3, [r7, #22] + if(datalen >= 3) + 8000968: 78fb ldrb r3, [r7, #3] + 800096a: 2b02 cmp r3, #2 + 800096c: d937 bls.n 80009de + { + for(int i = 0; i < (datalen-2); i++) + 800096e: 2300 movs r3, #0 + 8000970: 613b str r3, [r7, #16] + 8000972: e01c b.n 80009ae + { + for(int n = 0; n < 8;n++) + 8000974: 2300 movs r3, #0 + 8000976: 60fb str r3, [r7, #12] + 8000978: e013 b.n 80009a2 + { + uint8 din = data[i] << (n); + 800097a: 693b ldr r3, [r7, #16] + 800097c: 687a ldr r2, [r7, #4] + 800097e: 4413 add r3, r2 + 8000980: 781b ldrb r3, [r3, #0] + 8000982: 461a mov r2, r3 + 8000984: 68fb ldr r3, [r7, #12] + 8000986: fa02 f303 lsl.w r3, r2, r3 + 800098a: 72fb strb r3, [r7, #11] + currentpec = updatePEC(currentpec, din); + 800098c: 7afa ldrb r2, [r7, #11] + 800098e: 8afb ldrh r3, [r7, #22] + 8000990: 4611 mov r1, r2 + 8000992: 4618 mov r0, r3 + 8000994: f000 f878 bl 8000a88 + 8000998: 4603 mov r3, r0 + 800099a: 82fb strh r3, [r7, #22] + for(int n = 0; n < 8;n++) + 800099c: 68fb ldr r3, [r7, #12] + 800099e: 3301 adds r3, #1 + 80009a0: 60fb str r3, [r7, #12] + 80009a2: 68fb ldr r3, [r7, #12] + 80009a4: 2b07 cmp r3, #7 + 80009a6: dde8 ble.n 800097a + for(int i = 0; i < (datalen-2); i++) + 80009a8: 693b ldr r3, [r7, #16] + 80009aa: 3301 adds r3, #1 + 80009ac: 613b str r3, [r7, #16] + 80009ae: 78fb ldrb r3, [r7, #3] + 80009b0: 3b02 subs r3, #2 + 80009b2: 693a ldr r2, [r7, #16] + 80009b4: 429a cmp r2, r3 + 80009b6: dbdd blt.n 8000974 + } + } + + data[datalen-2] = (currentpec>>7) & 0xFF; + 80009b8: 8afb ldrh r3, [r7, #22] + 80009ba: 09db lsrs r3, r3, #7 + 80009bc: b299 uxth r1, r3 + 80009be: 78fb ldrb r3, [r7, #3] + 80009c0: 3b02 subs r3, #2 + 80009c2: 687a ldr r2, [r7, #4] + 80009c4: 4413 add r3, r2 + 80009c6: b2ca uxtb r2, r1 + 80009c8: 701a strb r2, [r3, #0] + data[datalen-1] = (currentpec<<1) & 0xFF; + 80009ca: 8afb ldrh r3, [r7, #22] + 80009cc: 0059 lsls r1, r3, #1 + 80009ce: 78fb ldrb r3, [r7, #3] + 80009d0: 3b01 subs r3, #1 + 80009d2: 687a ldr r2, [r7, #4] + 80009d4: 4413 add r3, r2 + 80009d6: b2ca uxtb r2, r1 + 80009d8: 701a strb r2, [r3, #0] + return 0; + 80009da: 2300 movs r3, #0 + 80009dc: e000 b.n 80009e0 + } + + else + { + return 1; + 80009de: 2301 movs r3, #1 + } +} + 80009e0: 4618 mov r0, r3 + 80009e2: 3718 adds r7, #24 + 80009e4: 46bd mov sp, r7 + 80009e6: bd80 pop {r7, pc} + +080009e8 : + +uint8 checkPEC(uint8* data, uint8 datalen) +{ + 80009e8: b580 push {r7, lr} + 80009ea: b086 sub sp, #24 + 80009ec: af00 add r7, sp, #0 + 80009ee: 6078 str r0, [r7, #4] + 80009f0: 460b mov r3, r1 + 80009f2: 70fb strb r3, [r7, #3] + if(datalen <= 3) + 80009f4: 78fb ldrb r3, [r7, #3] + 80009f6: 2b03 cmp r3, #3 + 80009f8: d801 bhi.n 80009fe + { + return 255; + 80009fa: 23ff movs r3, #255 ; 0xff + 80009fc: e040 b.n 8000a80 + } + + uint16 currentpec = INITAL_PEC; + 80009fe: 2310 movs r3, #16 + 8000a00: 82fb strh r3, [r7, #22] + + for(int i = 0; i < (datalen-2); i++) + 8000a02: 2300 movs r3, #0 + 8000a04: 613b str r3, [r7, #16] + 8000a06: e01c b.n 8000a42 + { + for(int n = 0; n < 8;n++) + 8000a08: 2300 movs r3, #0 + 8000a0a: 60fb str r3, [r7, #12] + 8000a0c: e013 b.n 8000a36 + { + uint8 din = data[i] << (n); + 8000a0e: 693b ldr r3, [r7, #16] + 8000a10: 687a ldr r2, [r7, #4] + 8000a12: 4413 add r3, r2 + 8000a14: 781b ldrb r3, [r3, #0] + 8000a16: 461a mov r2, r3 + 8000a18: 68fb ldr r3, [r7, #12] + 8000a1a: fa02 f303 lsl.w r3, r2, r3 + 8000a1e: 727b strb r3, [r7, #9] + currentpec = updatePEC(currentpec, din); + 8000a20: 7a7a ldrb r2, [r7, #9] + 8000a22: 8afb ldrh r3, [r7, #22] + 8000a24: 4611 mov r1, r2 + 8000a26: 4618 mov r0, r3 + 8000a28: f000 f82e bl 8000a88 + 8000a2c: 4603 mov r3, r0 + 8000a2e: 82fb strh r3, [r7, #22] + for(int n = 0; n < 8;n++) + 8000a30: 68fb ldr r3, [r7, #12] + 8000a32: 3301 adds r3, #1 + 8000a34: 60fb str r3, [r7, #12] + 8000a36: 68fb ldr r3, [r7, #12] + 8000a38: 2b07 cmp r3, #7 + 8000a3a: dde8 ble.n 8000a0e + for(int i = 0; i < (datalen-2); i++) + 8000a3c: 693b ldr r3, [r7, #16] + 8000a3e: 3301 adds r3, #1 + 8000a40: 613b str r3, [r7, #16] + 8000a42: 78fb ldrb r3, [r7, #3] + 8000a44: 3b02 subs r3, #2 + 8000a46: 693a ldr r2, [r7, #16] + 8000a48: 429a cmp r2, r3 + 8000a4a: dbdd blt.n 8000a08 + } + } + + uint8 pechigh = (currentpec>>7) & 0xFF; + 8000a4c: 8afb ldrh r3, [r7, #22] + 8000a4e: 09db lsrs r3, r3, #7 + 8000a50: b29b uxth r3, r3 + 8000a52: 72fb strb r3, [r7, #11] + uint8 peclow = (currentpec<<1) & 0xFF; + 8000a54: 8afb ldrh r3, [r7, #22] + 8000a56: 005b lsls r3, r3, #1 + 8000a58: 72bb strb r3, [r7, #10] + + if((pechigh == data[datalen-2]) && (peclow == data[datalen-1])) + 8000a5a: 78fb ldrb r3, [r7, #3] + 8000a5c: 3b02 subs r3, #2 + 8000a5e: 687a ldr r2, [r7, #4] + 8000a60: 4413 add r3, r2 + 8000a62: 781b ldrb r3, [r3, #0] + 8000a64: 7afa ldrb r2, [r7, #11] + 8000a66: 429a cmp r2, r3 + 8000a68: d109 bne.n 8000a7e + 8000a6a: 78fb ldrb r3, [r7, #3] + 8000a6c: 3b01 subs r3, #1 + 8000a6e: 687a ldr r2, [r7, #4] + 8000a70: 4413 add r3, r2 + 8000a72: 781b ldrb r3, [r3, #0] + 8000a74: 7aba ldrb r2, [r7, #10] + 8000a76: 429a cmp r2, r3 + 8000a78: d101 bne.n 8000a7e + { + return 0; + 8000a7a: 2300 movs r3, #0 + 8000a7c: e000 b.n 8000a80 + } + + return 1; + 8000a7e: 2301 movs r3, #1 + +} + 8000a80: 4618 mov r0, r3 + 8000a82: 3718 adds r7, #24 + 8000a84: 46bd mov sp, r7 + 8000a86: bd80 pop {r7, pc} + +08000a88 : + +uint16 updatePEC(uint16 currentPEC, uint8 din) +{ + 8000a88: b480 push {r7} + 8000a8a: b087 sub sp, #28 + 8000a8c: af00 add r7, sp, #0 + 8000a8e: 4603 mov r3, r0 + 8000a90: 460a mov r2, r1 + 8000a92: 80fb strh r3, [r7, #6] + 8000a94: 4613 mov r3, r2 + 8000a96: 717b strb r3, [r7, #5] + din = (din>>7) & 0x01; + 8000a98: 797b ldrb r3, [r7, #5] + 8000a9a: 09db lsrs r3, r3, #7 + 8000a9c: 717b strb r3, [r7, #5] + uint8 in0 = din ^ ((currentPEC >> 14) &0x01); + 8000a9e: 88fb ldrh r3, [r7, #6] + 8000aa0: 0b9b lsrs r3, r3, #14 + 8000aa2: b29b uxth r3, r3 + 8000aa4: b25b sxtb r3, r3 + 8000aa6: f003 0301 and.w r3, r3, #1 + 8000aaa: b25a sxtb r2, r3 + 8000aac: f997 3005 ldrsb.w r3, [r7, #5] + 8000ab0: 4053 eors r3, r2 + 8000ab2: b25b sxtb r3, r3 + 8000ab4: 75fb strb r3, [r7, #23] + uint8 in3 = in0 ^ ((currentPEC >> 2) &0x01); + 8000ab6: 88fb ldrh r3, [r7, #6] + 8000ab8: 089b lsrs r3, r3, #2 + 8000aba: b29b uxth r3, r3 + 8000abc: b25b sxtb r3, r3 + 8000abe: f003 0301 and.w r3, r3, #1 + 8000ac2: b25a sxtb r2, r3 + 8000ac4: f997 3017 ldrsb.w r3, [r7, #23] + 8000ac8: 4053 eors r3, r2 + 8000aca: b25b sxtb r3, r3 + 8000acc: 75bb strb r3, [r7, #22] + uint8 in4 = in0 ^ ((currentPEC >> 3) &0x01); + 8000ace: 88fb ldrh r3, [r7, #6] + 8000ad0: 08db lsrs r3, r3, #3 + 8000ad2: b29b uxth r3, r3 + 8000ad4: b25b sxtb r3, r3 + 8000ad6: f003 0301 and.w r3, r3, #1 + 8000ada: b25a sxtb r2, r3 + 8000adc: f997 3017 ldrsb.w r3, [r7, #23] + 8000ae0: 4053 eors r3, r2 + 8000ae2: b25b sxtb r3, r3 + 8000ae4: 757b strb r3, [r7, #21] + uint8 in7 = in0 ^ ((currentPEC >> 6) &0x01); + 8000ae6: 88fb ldrh r3, [r7, #6] + 8000ae8: 099b lsrs r3, r3, #6 + 8000aea: b29b uxth r3, r3 + 8000aec: b25b sxtb r3, r3 + 8000aee: f003 0301 and.w r3, r3, #1 + 8000af2: b25a sxtb r2, r3 + 8000af4: f997 3017 ldrsb.w r3, [r7, #23] + 8000af8: 4053 eors r3, r2 + 8000afa: b25b sxtb r3, r3 + 8000afc: 753b strb r3, [r7, #20] + uint8 in8 = in0 ^ ((currentPEC >> 7) &0x01); + 8000afe: 88fb ldrh r3, [r7, #6] + 8000b00: 09db lsrs r3, r3, #7 + 8000b02: b29b uxth r3, r3 + 8000b04: b25b sxtb r3, r3 + 8000b06: f003 0301 and.w r3, r3, #1 + 8000b0a: b25a sxtb r2, r3 + 8000b0c: f997 3017 ldrsb.w r3, [r7, #23] + 8000b10: 4053 eors r3, r2 + 8000b12: b25b sxtb r3, r3 + 8000b14: 74fb strb r3, [r7, #19] + uint8 in10 = in0 ^ ((currentPEC >> 9) &0x01); + 8000b16: 88fb ldrh r3, [r7, #6] + 8000b18: 0a5b lsrs r3, r3, #9 + 8000b1a: b29b uxth r3, r3 + 8000b1c: b25b sxtb r3, r3 + 8000b1e: f003 0301 and.w r3, r3, #1 + 8000b22: b25a sxtb r2, r3 + 8000b24: f997 3017 ldrsb.w r3, [r7, #23] + 8000b28: 4053 eors r3, r2 + 8000b2a: b25b sxtb r3, r3 + 8000b2c: 74bb strb r3, [r7, #18] + uint8 in14 = in0 ^ ((currentPEC >> 13) &0x01); + 8000b2e: 88fb ldrh r3, [r7, #6] + 8000b30: 0b5b lsrs r3, r3, #13 + 8000b32: b29b uxth r3, r3 + 8000b34: b25b sxtb r3, r3 + 8000b36: f003 0301 and.w r3, r3, #1 + 8000b3a: b25a sxtb r2, r3 + 8000b3c: f997 3017 ldrsb.w r3, [r7, #23] + 8000b40: 4053 eors r3, r2 + 8000b42: b25b sxtb r3, r3 + 8000b44: 747b strb r3, [r7, #17] + + uint16 newPEC = 0; + 8000b46: 2300 movs r3, #0 + 8000b48: 81fb strh r3, [r7, #14] + + newPEC |= in14<<14; + 8000b4a: 7c7b ldrb r3, [r7, #17] + 8000b4c: 039b lsls r3, r3, #14 + 8000b4e: b21a sxth r2, r3 + 8000b50: f9b7 300e ldrsh.w r3, [r7, #14] + 8000b54: 4313 orrs r3, r2 + 8000b56: b21b sxth r3, r3 + 8000b58: 81fb strh r3, [r7, #14] + newPEC |= (currentPEC & (0x01<<12))<<1; + 8000b5a: 88fb ldrh r3, [r7, #6] + 8000b5c: 005b lsls r3, r3, #1 + 8000b5e: b21b sxth r3, r3 + 8000b60: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8000b64: b21a sxth r2, r3 + 8000b66: f9b7 300e ldrsh.w r3, [r7, #14] + 8000b6a: 4313 orrs r3, r2 + 8000b6c: b21b sxth r3, r3 + 8000b6e: 81fb strh r3, [r7, #14] + newPEC |= (currentPEC & (0x01<<11))<<1; + 8000b70: 88fb ldrh r3, [r7, #6] + 8000b72: 005b lsls r3, r3, #1 + 8000b74: b21b sxth r3, r3 + 8000b76: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8000b7a: b21a sxth r2, r3 + 8000b7c: f9b7 300e ldrsh.w r3, [r7, #14] + 8000b80: 4313 orrs r3, r2 + 8000b82: b21b sxth r3, r3 + 8000b84: 81fb strh r3, [r7, #14] + newPEC |= (currentPEC & (0x01<<10))<<1; + 8000b86: 88fb ldrh r3, [r7, #6] + 8000b88: 005b lsls r3, r3, #1 + 8000b8a: b21b sxth r3, r3 + 8000b8c: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8000b90: b21a sxth r2, r3 + 8000b92: f9b7 300e ldrsh.w r3, [r7, #14] + 8000b96: 4313 orrs r3, r2 + 8000b98: b21b sxth r3, r3 + 8000b9a: 81fb strh r3, [r7, #14] + newPEC |= in10<<10; + 8000b9c: 7cbb ldrb r3, [r7, #18] + 8000b9e: 029b lsls r3, r3, #10 + 8000ba0: b21a sxth r2, r3 + 8000ba2: f9b7 300e ldrsh.w r3, [r7, #14] + 8000ba6: 4313 orrs r3, r2 + 8000ba8: b21b sxth r3, r3 + 8000baa: 81fb strh r3, [r7, #14] + newPEC |= (currentPEC & (0x01<<8))<<1; + 8000bac: 88fb ldrh r3, [r7, #6] + 8000bae: 005b lsls r3, r3, #1 + 8000bb0: b21b sxth r3, r3 + 8000bb2: f403 7300 and.w r3, r3, #512 ; 0x200 + 8000bb6: b21a sxth r2, r3 + 8000bb8: f9b7 300e ldrsh.w r3, [r7, #14] + 8000bbc: 4313 orrs r3, r2 + 8000bbe: b21b sxth r3, r3 + 8000bc0: 81fb strh r3, [r7, #14] + newPEC |= in8<<8; + 8000bc2: 7cfb ldrb r3, [r7, #19] + 8000bc4: 021b lsls r3, r3, #8 + 8000bc6: b21a sxth r2, r3 + 8000bc8: f9b7 300e ldrsh.w r3, [r7, #14] + 8000bcc: 4313 orrs r3, r2 + 8000bce: b21b sxth r3, r3 + 8000bd0: 81fb strh r3, [r7, #14] + newPEC |= in7<<7; + 8000bd2: 7d3b ldrb r3, [r7, #20] + 8000bd4: 01db lsls r3, r3, #7 + 8000bd6: b21a sxth r2, r3 + 8000bd8: f9b7 300e ldrsh.w r3, [r7, #14] + 8000bdc: 4313 orrs r3, r2 + 8000bde: b21b sxth r3, r3 + 8000be0: 81fb strh r3, [r7, #14] + newPEC |= (currentPEC & (0x01<<5))<<1; + 8000be2: 88fb ldrh r3, [r7, #6] + 8000be4: 005b lsls r3, r3, #1 + 8000be6: b21b sxth r3, r3 + 8000be8: f003 0340 and.w r3, r3, #64 ; 0x40 + 8000bec: b21a sxth r2, r3 + 8000bee: f9b7 300e ldrsh.w r3, [r7, #14] + 8000bf2: 4313 orrs r3, r2 + 8000bf4: b21b sxth r3, r3 + 8000bf6: 81fb strh r3, [r7, #14] + newPEC |= (currentPEC & (0x01<<4))<<1; + 8000bf8: 88fb ldrh r3, [r7, #6] + 8000bfa: 005b lsls r3, r3, #1 + 8000bfc: b21b sxth r3, r3 + 8000bfe: f003 0320 and.w r3, r3, #32 + 8000c02: b21a sxth r2, r3 + 8000c04: f9b7 300e ldrsh.w r3, [r7, #14] + 8000c08: 4313 orrs r3, r2 + 8000c0a: b21b sxth r3, r3 + 8000c0c: 81fb strh r3, [r7, #14] + newPEC |= in4<<4; + 8000c0e: 7d7b ldrb r3, [r7, #21] + 8000c10: 011b lsls r3, r3, #4 + 8000c12: b21a sxth r2, r3 + 8000c14: f9b7 300e ldrsh.w r3, [r7, #14] + 8000c18: 4313 orrs r3, r2 + 8000c1a: b21b sxth r3, r3 + 8000c1c: 81fb strh r3, [r7, #14] + newPEC |= in3<<3; + 8000c1e: 7dbb ldrb r3, [r7, #22] + 8000c20: 00db lsls r3, r3, #3 + 8000c22: b21a sxth r2, r3 + 8000c24: f9b7 300e ldrsh.w r3, [r7, #14] + 8000c28: 4313 orrs r3, r2 + 8000c2a: b21b sxth r3, r3 + 8000c2c: 81fb strh r3, [r7, #14] + newPEC |= (currentPEC & (0x01<<1))<<1; + 8000c2e: 88fb ldrh r3, [r7, #6] + 8000c30: 005b lsls r3, r3, #1 + 8000c32: b21b sxth r3, r3 + 8000c34: f003 0304 and.w r3, r3, #4 + 8000c38: b21a sxth r2, r3 + 8000c3a: f9b7 300e ldrsh.w r3, [r7, #14] + 8000c3e: 4313 orrs r3, r2 + 8000c40: b21b sxth r3, r3 + 8000c42: 81fb strh r3, [r7, #14] + newPEC |= (currentPEC & (0x01))<<1; + 8000c44: 88fb ldrh r3, [r7, #6] + 8000c46: 005b lsls r3, r3, #1 + 8000c48: b21b sxth r3, r3 + 8000c4a: f003 0302 and.w r3, r3, #2 + 8000c4e: b21a sxth r2, r3 + 8000c50: f9b7 300e ldrsh.w r3, [r7, #14] + 8000c54: 4313 orrs r3, r2 + 8000c56: b21b sxth r3, r3 + 8000c58: 81fb strh r3, [r7, #14] + newPEC |= in0; + 8000c5a: 7dfb ldrb r3, [r7, #23] + 8000c5c: b29a uxth r2, r3 + 8000c5e: 89fb ldrh r3, [r7, #14] + 8000c60: 4313 orrs r3, r2 + 8000c62: 81fb strh r3, [r7, #14] + + + return newPEC; + 8000c64: 89fb ldrh r3, [r7, #14] +} + 8000c66: 4618 mov r0, r3 + 8000c68: 371c adds r7, #28 + 8000c6a: 46bd mov sp, r7 + 8000c6c: f85d 7b04 ldr.w r7, [sp], #4 + 8000c70: 4770 bx lr + +08000c72 : + +uint8 writeCMD(uint16 command, uint8* args, uint8 arglen) +{ + 8000c72: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8000c76: b087 sub sp, #28 + 8000c78: af00 add r7, sp, #0 + 8000c7a: 4603 mov r3, r0 + 8000c7c: 6039 str r1, [r7, #0] + 8000c7e: 80fb strh r3, [r7, #6] + 8000c80: 4613 mov r3, r2 + 8000c82: 717b strb r3, [r7, #5] + if(arglen > 0) + 8000c84: 797b ldrb r3, [r7, #5] + 8000c86: 2b00 cmp r3, #0 + 8000c88: d05e beq.n 8000d48 + { + 8000c8a: 466b mov r3, sp + 8000c8c: 461e mov r6, r3 + uint8 buffer[6+arglen]; + 8000c8e: 797b ldrb r3, [r7, #5] + 8000c90: 1d99 adds r1, r3, #6 + 8000c92: 1e4b subs r3, r1, #1 + 8000c94: 613b str r3, [r7, #16] + 8000c96: 460a mov r2, r1 + 8000c98: 2300 movs r3, #0 + 8000c9a: 4690 mov r8, r2 + 8000c9c: 4699 mov r9, r3 + 8000c9e: f04f 0200 mov.w r2, #0 + 8000ca2: f04f 0300 mov.w r3, #0 + 8000ca6: ea4f 03c9 mov.w r3, r9, lsl #3 + 8000caa: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8000cae: ea4f 02c8 mov.w r2, r8, lsl #3 + 8000cb2: 460a mov r2, r1 + 8000cb4: 2300 movs r3, #0 + 8000cb6: 4614 mov r4, r2 + 8000cb8: 461d mov r5, r3 + 8000cba: f04f 0200 mov.w r2, #0 + 8000cbe: f04f 0300 mov.w r3, #0 + 8000cc2: 00eb lsls r3, r5, #3 + 8000cc4: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8000cc8: 00e2 lsls r2, r4, #3 + 8000cca: 460b mov r3, r1 + 8000ccc: 3307 adds r3, #7 + 8000cce: 08db lsrs r3, r3, #3 + 8000cd0: 00db lsls r3, r3, #3 + 8000cd2: ebad 0d03 sub.w sp, sp, r3 + 8000cd6: 466b mov r3, sp + 8000cd8: 3300 adds r3, #0 + 8000cda: 60fb str r3, [r7, #12] + buffer[0] = (command >> 8) & 0xFF; + 8000cdc: 88fb ldrh r3, [r7, #6] + 8000cde: 0a1b lsrs r3, r3, #8 + 8000ce0: b29b uxth r3, r3 + 8000ce2: b2da uxtb r2, r3 + 8000ce4: 68fb ldr r3, [r7, #12] + 8000ce6: 701a strb r2, [r3, #0] + buffer[1] = (command) & 0xFF; + 8000ce8: 88fb ldrh r3, [r7, #6] + 8000cea: b2da uxtb r2, r3 + 8000cec: 68fb ldr r3, [r7, #12] + 8000cee: 705a strb r2, [r3, #1] + calculatePEC(buffer, 4); + 8000cf0: 2104 movs r1, #4 + 8000cf2: 68f8 ldr r0, [r7, #12] + 8000cf4: f7ff fe30 bl 8000958 + for(uint8 i = 0; i < arglen; i++) + 8000cf8: 2300 movs r3, #0 + 8000cfa: 75fb strb r3, [r7, #23] + 8000cfc: e00a b.n 8000d14 + { + buffer[4+i] = args[i]; + 8000cfe: 7dfb ldrb r3, [r7, #23] + 8000d00: 683a ldr r2, [r7, #0] + 8000d02: 441a add r2, r3 + 8000d04: 7dfb ldrb r3, [r7, #23] + 8000d06: 3304 adds r3, #4 + 8000d08: 7811 ldrb r1, [r2, #0] + 8000d0a: 68fa ldr r2, [r7, #12] + 8000d0c: 54d1 strb r1, [r2, r3] + for(uint8 i = 0; i < arglen; i++) + 8000d0e: 7dfb ldrb r3, [r7, #23] + 8000d10: 3301 adds r3, #1 + 8000d12: 75fb strb r3, [r7, #23] + 8000d14: 7dfa ldrb r2, [r7, #23] + 8000d16: 797b ldrb r3, [r7, #5] + 8000d18: 429a cmp r2, r3 + 8000d1a: d3f0 bcc.n 8000cfe + } + + calculatePEC(&buffer[4], arglen+2); //Calculate PEC of Data Part with offset of 4 Bytes for CMD and CMD PEC + 8000d1c: 68fb ldr r3, [r7, #12] + 8000d1e: 1d1a adds r2, r3, #4 + 8000d20: 797b ldrb r3, [r7, #5] + 8000d22: 3302 adds r3, #2 + 8000d24: b2db uxtb r3, r3 + 8000d26: 4619 mov r1, r3 + 8000d28: 4610 mov r0, r2 + 8000d2a: f7ff fe15 bl 8000958 + + mcuAdbmsCSLow(); + 8000d2e: f000 f8db bl 8000ee8 + mcuSPITransmit(buffer, 6+arglen); + 8000d32: 797b ldrb r3, [r7, #5] + 8000d34: 3306 adds r3, #6 + 8000d36: b2db uxtb r3, r3 + 8000d38: 4619 mov r1, r3 + 8000d3a: 68f8 ldr r0, [r7, #12] + 8000d3c: f000 f8e8 bl 8000f10 + mcuAdbmsCSHigh(); + 8000d40: f000 f8dc bl 8000efc + 8000d44: 46b5 mov sp, r6 + 8000d46: e017 b.n 8000d78 + + } + else + { + uint8 buffer[4]; + buffer[0] = (command >> 8) & 0xFF; + 8000d48: 88fb ldrh r3, [r7, #6] + 8000d4a: 0a1b lsrs r3, r3, #8 + 8000d4c: b29b uxth r3, r3 + 8000d4e: b2db uxtb r3, r3 + 8000d50: 723b strb r3, [r7, #8] + buffer[1] = (command) & 0xFF; + 8000d52: 88fb ldrh r3, [r7, #6] + 8000d54: b2db uxtb r3, r3 + 8000d56: 727b strb r3, [r7, #9] + calculatePEC(buffer, 4); + 8000d58: f107 0308 add.w r3, r7, #8 + 8000d5c: 2104 movs r1, #4 + 8000d5e: 4618 mov r0, r3 + 8000d60: f7ff fdfa bl 8000958 + + mcuAdbmsCSLow(); + 8000d64: f000 f8c0 bl 8000ee8 + + mcuSPITransmit(buffer, 4); + 8000d68: f107 0308 add.w r3, r7, #8 + 8000d6c: 2104 movs r1, #4 + 8000d6e: 4618 mov r0, r3 + 8000d70: f000 f8ce bl 8000f10 + + mcuAdbmsCSHigh(); + 8000d74: f000 f8c2 bl 8000efc + } + + return 0; + 8000d78: 2300 movs r3, #0 +} + 8000d7a: 4618 mov r0, r3 + 8000d7c: 371c adds r7, #28 + 8000d7e: 46bd mov sp, r7 + 8000d80: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + +08000d84 : + +uint8 readCMD(uint16 command, uint8* buffer, uint8 buflen) +{ + 8000d84: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8000d88: b08b sub sp, #44 ; 0x2c + 8000d8a: af00 add r7, sp, #0 + 8000d8c: 4603 mov r3, r0 + 8000d8e: 60b9 str r1, [r7, #8] + 8000d90: 81fb strh r3, [r7, #14] + 8000d92: 4613 mov r3, r2 + 8000d94: 737b strb r3, [r7, #13] + 8000d96: 466b mov r3, sp + 8000d98: 461e mov r6, r3 + //uint8* txbuffer = (uint8*) malloc(6+buflen); + //uint8* rxbuffer = (uint8*) malloc(6+buflen); + uint8 txbuffer[6+buflen]; + 8000d9a: 7b7b ldrb r3, [r7, #13] + 8000d9c: 1d99 adds r1, r3, #6 + 8000d9e: 1e4b subs r3, r1, #1 + 8000da0: 627b str r3, [r7, #36] ; 0x24 + 8000da2: 460a mov r2, r1 + 8000da4: 2300 movs r3, #0 + 8000da6: 603a str r2, [r7, #0] + 8000da8: 607b str r3, [r7, #4] + 8000daa: f04f 0200 mov.w r2, #0 + 8000dae: f04f 0300 mov.w r3, #0 + 8000db2: 6878 ldr r0, [r7, #4] + 8000db4: 00c3 lsls r3, r0, #3 + 8000db6: 6838 ldr r0, [r7, #0] + 8000db8: ea43 7350 orr.w r3, r3, r0, lsr #29 + 8000dbc: 6838 ldr r0, [r7, #0] + 8000dbe: 00c2 lsls r2, r0, #3 + 8000dc0: 460a mov r2, r1 + 8000dc2: 2300 movs r3, #0 + 8000dc4: 4692 mov sl, r2 + 8000dc6: 469b mov fp, r3 + 8000dc8: f04f 0200 mov.w r2, #0 + 8000dcc: f04f 0300 mov.w r3, #0 + 8000dd0: ea4f 03cb mov.w r3, fp, lsl #3 + 8000dd4: ea43 735a orr.w r3, r3, sl, lsr #29 + 8000dd8: ea4f 02ca mov.w r2, sl, lsl #3 + 8000ddc: 460b mov r3, r1 + 8000dde: 3307 adds r3, #7 + 8000de0: 08db lsrs r3, r3, #3 + 8000de2: 00db lsls r3, r3, #3 + 8000de4: ebad 0d03 sub.w sp, sp, r3 + 8000de8: 466b mov r3, sp + 8000dea: 3300 adds r3, #0 + 8000dec: 61fb str r3, [r7, #28] + uint8 rxbuffer[6+buflen]; + 8000dee: 7b7b ldrb r3, [r7, #13] + 8000df0: 1d99 adds r1, r3, #6 + 8000df2: 1e4b subs r3, r1, #1 + 8000df4: 61bb str r3, [r7, #24] + 8000df6: 460a mov r2, r1 + 8000df8: 2300 movs r3, #0 + 8000dfa: 4690 mov r8, r2 + 8000dfc: 4699 mov r9, r3 + 8000dfe: f04f 0200 mov.w r2, #0 + 8000e02: f04f 0300 mov.w r3, #0 + 8000e06: ea4f 03c9 mov.w r3, r9, lsl #3 + 8000e0a: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8000e0e: ea4f 02c8 mov.w r2, r8, lsl #3 + 8000e12: 460a mov r2, r1 + 8000e14: 2300 movs r3, #0 + 8000e16: 4614 mov r4, r2 + 8000e18: 461d mov r5, r3 + 8000e1a: f04f 0200 mov.w r2, #0 + 8000e1e: f04f 0300 mov.w r3, #0 + 8000e22: 00eb lsls r3, r5, #3 + 8000e24: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8000e28: 00e2 lsls r2, r4, #3 + 8000e2a: 460b mov r3, r1 + 8000e2c: 3307 adds r3, #7 + 8000e2e: 08db lsrs r3, r3, #3 + 8000e30: 00db lsls r3, r3, #3 + 8000e32: ebad 0d03 sub.w sp, sp, r3 + 8000e36: 466b mov r3, sp + 8000e38: 3300 adds r3, #0 + 8000e3a: 617b str r3, [r7, #20] + + txbuffer[0] = (command >> 8) & 0xFF; + 8000e3c: 89fb ldrh r3, [r7, #14] + 8000e3e: 0a1b lsrs r3, r3, #8 + 8000e40: b29b uxth r3, r3 + 8000e42: b2da uxtb r2, r3 + 8000e44: 69fb ldr r3, [r7, #28] + 8000e46: 701a strb r2, [r3, #0] + txbuffer[1] = (command) & 0xFF; + 8000e48: 89fb ldrh r3, [r7, #14] + 8000e4a: b2da uxtb r2, r3 + 8000e4c: 69fb ldr r3, [r7, #28] + 8000e4e: 705a strb r2, [r3, #1] + calculatePEC(txbuffer, 4); + 8000e50: 2104 movs r1, #4 + 8000e52: 69f8 ldr r0, [r7, #28] + 8000e54: f7ff fd80 bl 8000958 + + mcuAdbmsCSLow(); + 8000e58: f000 f846 bl 8000ee8 + mcuSPITransmitReceive(rxbuffer, txbuffer, 6+buflen); + 8000e5c: 7b7b ldrb r3, [r7, #13] + 8000e5e: 3306 adds r3, #6 + 8000e60: b2db uxtb r3, r3 + 8000e62: 461a mov r2, r3 + 8000e64: 69f9 ldr r1, [r7, #28] + 8000e66: 6978 ldr r0, [r7, #20] + 8000e68: f000 f8a6 bl 8000fb8 + mcuAdbmsCSHigh(); + 8000e6c: f000 f846 bl 8000efc + + + for(uint8 i = 0; i + { + buffer[i] = rxbuffer[i+4]; + 8000e78: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 8000e7c: 1d1a adds r2, r3, #4 + 8000e7e: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 8000e82: 68b9 ldr r1, [r7, #8] + 8000e84: 440b add r3, r1 + 8000e86: 6979 ldr r1, [r7, #20] + 8000e88: 5c8a ldrb r2, [r1, r2] + 8000e8a: 701a strb r2, [r3, #0] + for(uint8 i = 0; i + } + + uint8 peccheck = checkPEC(&rxbuffer[4], buflen+2); + 8000ea0: 697b ldr r3, [r7, #20] + 8000ea2: 1d1a adds r2, r3, #4 + 8000ea4: 7b7b ldrb r3, [r7, #13] + 8000ea6: 3302 adds r3, #2 + 8000ea8: b2db uxtb r3, r3 + 8000eaa: 4619 mov r1, r3 + 8000eac: 4610 mov r0, r2 + 8000eae: f7ff fd9b bl 80009e8 + 8000eb2: 4603 mov r3, r0 + 8000eb4: 74fb strb r3, [r7, #19] + + //free(txbuffer); + //free(rxbuffer); + + if(peccheck == 0) + 8000eb6: 7cfb ldrb r3, [r7, #19] + 8000eb8: 2b00 cmp r3, #0 + 8000eba: d101 bne.n 8000ec0 + return 0; + 8000ebc: 2300 movs r3, #0 + 8000ebe: e00b b.n 8000ed8 + else + { + static int err_cnt = 0; + if (err_cnt++ > 100) { + 8000ec0: 4b08 ldr r3, [pc, #32] ; (8000ee4 ) + 8000ec2: 681b ldr r3, [r3, #0] + 8000ec4: 1c5a adds r2, r3, #1 + 8000ec6: 4907 ldr r1, [pc, #28] ; (8000ee4 ) + 8000ec8: 600a str r2, [r1, #0] + 8000eca: 2b64 cmp r3, #100 ; 0x64 + 8000ecc: dd03 ble.n 8000ed6 + Error_Handler(); + 8000ece: f000 ffb3 bl 8001e38 + 8000ed2: 46b5 mov sp, r6 + } else { + return 1; + } + } + +} + 8000ed4: e001 b.n 8000eda + return 1; + 8000ed6: 2301 movs r3, #1 + 8000ed8: 46b5 mov sp, r6 +} + 8000eda: 4618 mov r0, r3 + 8000edc: 372c adds r7, #44 ; 0x2c + 8000ede: 46bd mov sp, r7 + 8000ee0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8000ee4: 2000003c .word 0x2000003c + +08000ee8 : + +void mcuAdbmsCSLow() +{ + 8000ee8: b580 push {r7, lr} + 8000eea: af00 add r7, sp, #0 + HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_RESET); + 8000eec: 2200 movs r2, #0 + 8000eee: 2110 movs r1, #16 + 8000ef0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8000ef4: f002 faf2 bl 80034dc +} + 8000ef8: bf00 nop + 8000efa: bd80 pop {r7, pc} + +08000efc : + +void mcuAdbmsCSHigh() +{ + 8000efc: b580 push {r7, lr} + 8000efe: af00 add r7, sp, #0 + HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_SET); + 8000f00: 2201 movs r2, #1 + 8000f02: 2110 movs r1, #16 + 8000f04: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8000f08: f002 fae8 bl 80034dc +} + 8000f0c: bf00 nop + 8000f0e: bd80 pop {r7, pc} + +08000f10 : + +uint8 mcuSPITransmit(uint8* buffer, uint8 buffersize) +{ + 8000f10: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8000f14: b089 sub sp, #36 ; 0x24 + 8000f16: af02 add r7, sp, #8 + 8000f18: 6078 str r0, [r7, #4] + 8000f1a: 460b mov r3, r1 + 8000f1c: 70fb strb r3, [r7, #3] + 8000f1e: 466b mov r3, sp + 8000f20: 461e mov r6, r3 + HAL_StatusTypeDef status; + //status = HAL_SPI_Transmit(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOUT); + //uint8 *rxbuf = (uint8*) malloc(buffersize); + uint8 rxbuf[buffersize]; + 8000f22: 78f9 ldrb r1, [r7, #3] + 8000f24: 460b mov r3, r1 + 8000f26: 3b01 subs r3, #1 + 8000f28: 617b str r3, [r7, #20] + 8000f2a: b2cb uxtb r3, r1 + 8000f2c: 2200 movs r2, #0 + 8000f2e: 4698 mov r8, r3 + 8000f30: 4691 mov r9, r2 + 8000f32: f04f 0200 mov.w r2, #0 + 8000f36: f04f 0300 mov.w r3, #0 + 8000f3a: ea4f 03c9 mov.w r3, r9, lsl #3 + 8000f3e: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8000f42: ea4f 02c8 mov.w r2, r8, lsl #3 + 8000f46: b2cb uxtb r3, r1 + 8000f48: 2200 movs r2, #0 + 8000f4a: 461c mov r4, r3 + 8000f4c: 4615 mov r5, r2 + 8000f4e: f04f 0200 mov.w r2, #0 + 8000f52: f04f 0300 mov.w r3, #0 + 8000f56: 00eb lsls r3, r5, #3 + 8000f58: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8000f5c: 00e2 lsls r2, r4, #3 + 8000f5e: 460b mov r3, r1 + 8000f60: 3307 adds r3, #7 + 8000f62: 08db lsrs r3, r3, #3 + 8000f64: 00db lsls r3, r3, #3 + 8000f66: ebad 0d03 sub.w sp, sp, r3 + 8000f6a: ab02 add r3, sp, #8 + 8000f6c: 3300 adds r3, #0 + 8000f6e: 613b str r3, [r7, #16] + status = HAL_SPI_TransmitReceive(adbmsspi, buffer, rxbuf, buffersize, ADBMS_SPI_TIMEOUT); + 8000f70: 4b10 ldr r3, [pc, #64] ; (8000fb4 ) + 8000f72: 6818 ldr r0, [r3, #0] + 8000f74: 78fb ldrb r3, [r7, #3] + 8000f76: b29b uxth r3, r3 + 8000f78: f44f 727a mov.w r2, #1000 ; 0x3e8 + 8000f7c: 9200 str r2, [sp, #0] + 8000f7e: 693a ldr r2, [r7, #16] + 8000f80: 6879 ldr r1, [r7, #4] + 8000f82: f004 fefe bl 8005d82 + 8000f86: 4603 mov r3, r0 + 8000f88: 73fb strb r3, [r7, #15] + __HAL_SPI_CLEAR_OVRFLAG(adbmsspi); + 8000f8a: 2300 movs r3, #0 + 8000f8c: 60bb str r3, [r7, #8] + 8000f8e: 4b09 ldr r3, [pc, #36] ; (8000fb4 ) + 8000f90: 681b ldr r3, [r3, #0] + 8000f92: 681b ldr r3, [r3, #0] + 8000f94: 68db ldr r3, [r3, #12] + 8000f96: 60bb str r3, [r7, #8] + 8000f98: 4b06 ldr r3, [pc, #24] ; (8000fb4 ) + 8000f9a: 681b ldr r3, [r3, #0] + 8000f9c: 681b ldr r3, [r3, #0] + 8000f9e: 689b ldr r3, [r3, #8] + 8000fa0: 60bb str r3, [r7, #8] + 8000fa2: 68bb ldr r3, [r7, #8] + //free(rxbuf); + return status; + 8000fa4: 7bfb ldrb r3, [r7, #15] + 8000fa6: 46b5 mov sp, r6 +} + 8000fa8: 4618 mov r0, r3 + 8000faa: 371c adds r7, #28 + 8000fac: 46bd mov sp, r7 + 8000fae: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8000fb2: bf00 nop + 8000fb4: 20000038 .word 0x20000038 + +08000fb8 : + status = HAL_SPI_Receive(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOUT); + return status; +} + +uint8 mcuSPITransmitReceive(uint8* rxbuffer, uint8* txbuffer, uint8 buffersize) +{ + 8000fb8: b580 push {r7, lr} + 8000fba: b088 sub sp, #32 + 8000fbc: af02 add r7, sp, #8 + 8000fbe: 60f8 str r0, [r7, #12] + 8000fc0: 60b9 str r1, [r7, #8] + 8000fc2: 4613 mov r3, r2 + 8000fc4: 71fb strb r3, [r7, #7] + HAL_StatusTypeDef status; + status = HAL_SPI_TransmitReceive(adbmsspi, txbuffer, rxbuffer, buffersize, ADBMS_SPI_TIMEOUT); + 8000fc6: 4b09 ldr r3, [pc, #36] ; (8000fec ) + 8000fc8: 6818 ldr r0, [r3, #0] + 8000fca: 79fb ldrb r3, [r7, #7] + 8000fcc: b29b uxth r3, r3 + 8000fce: f44f 727a mov.w r2, #1000 ; 0x3e8 + 8000fd2: 9200 str r2, [sp, #0] + 8000fd4: 68fa ldr r2, [r7, #12] + 8000fd6: 68b9 ldr r1, [r7, #8] + 8000fd8: f004 fed3 bl 8005d82 + 8000fdc: 4603 mov r3, r0 + 8000fde: 75fb strb r3, [r7, #23] + return status; + 8000fe0: 7dfb ldrb r3, [r7, #23] +} + 8000fe2: 4618 mov r0, r3 + 8000fe4: 3718 adds r7, #24 + 8000fe6: 46bd mov sp, r7 + 8000fe8: bd80 pop {r7, pc} + 8000fea: bf00 nop + 8000fec: 20000038 .word 0x20000038 + +08000ff0 : + +inline void mcuDelay(uint16 delay) +{ + 8000ff0: b580 push {r7, lr} + 8000ff2: b082 sub sp, #8 + 8000ff4: af00 add r7, sp, #0 + 8000ff6: 4603 mov r3, r0 + 8000ff8: 80fb strh r3, [r7, #6] + HAL_Delay(delay); + 8000ffa: 88fb ldrh r3, [r7, #6] + 8000ffc: 4618 mov r0, r3 + 8000ffe: f001 f93d bl 800227c +} + 8001002: bf00 nop + 8001004: 3708 adds r7, #8 + 8001006: 46bd mov sp, r7 + 8001008: bd80 pop {r7, pc} + ... + +0800100c : + + +CAN_HandleTypeDef* ams_can_handle; + +void ams_can_init(CAN_HandleTypeDef* ams_handle, + CAN_HandleTypeDef* car_handle) { + 800100c: b580 push {r7, lr} + 800100e: b08c sub sp, #48 ; 0x30 + 8001010: af00 add r7, sp, #0 + 8001012: 6078 str r0, [r7, #4] + 8001014: 6039 str r1, [r7, #0] + ams_can_handle = ams_handle; + 8001016: 4a2e ldr r2, [pc, #184] ; (80010d0 ) + 8001018: 687b ldr r3, [r7, #4] + 800101a: 6013 str r3, [r2, #0] + + // Start peripheral + if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { + 800101c: 4b2c ldr r3, [pc, #176] ; (80010d0 ) + 800101e: 681b ldr r3, [r3, #0] + 8001020: 4618 mov r0, r3 + 8001022: f001 fb14 bl 800264e + 8001026: 4603 mov r3, r0 + 8001028: 2b00 cmp r3, #0 + 800102a: d00c beq.n 8001046 + ams_can_handle = car_handle; + 800102c: 4a28 ldr r2, [pc, #160] ; (80010d0 ) + 800102e: 683b ldr r3, [r7, #0] + 8001030: 6013 str r3, [r2, #0] + if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { + 8001032: 4b27 ldr r3, [pc, #156] ; (80010d0 ) + 8001034: 681b ldr r3, [r3, #0] + 8001036: 4618 mov r0, r3 + 8001038: f001 fb09 bl 800264e + 800103c: 4603 mov r3, r0 + 800103e: 2b00 cmp r3, #0 + 8001040: d001 beq.n 8001046 + Error_Handler(); + 8001042: f000 fef9 bl 8001e38 + } + } + + // Config filter + CAN_FilterTypeDef can_filter; + can_filter.FilterActivation = CAN_FILTER_ENABLE; + 8001046: 2301 movs r3, #1 + 8001048: 62bb str r3, [r7, #40] ; 0x28 + can_filter.FilterBank = 0; + 800104a: 2300 movs r3, #0 + 800104c: 61fb str r3, [r7, #28] + can_filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; + 800104e: 2300 movs r3, #0 + 8001050: 61bb str r3, [r7, #24] + /* Message ID is in the MSBs of the FilterId register */ + can_filter.FilterIdHigh = CAN_ID_CLOCK_SYNC << (16 - 11); + 8001052: 2340 movs r3, #64 ; 0x40 + 8001054: 60bb str r3, [r7, #8] + can_filter.FilterIdLow = 0; + 8001056: 2300 movs r3, #0 + 8001058: 60fb str r3, [r7, #12] + /* Filter the 11 MSBs (i.e. a StdId) */ + + if(BMS_IN_TEST_MODE == 1){ + can_filter.FilterMaskIdHigh = BMS_TEST_ID; // alleNachrichtenIds werden akzeptiert + 800105a: 2300 movs r3, #0 + 800105c: 613b str r3, [r7, #16] + }else{ + can_filter.FilterMaskIdHigh = 0xFFE0; + } + + can_filter.FilterMaskIdLow = 0; + 800105e: 2300 movs r3, #0 + 8001060: 617b str r3, [r7, #20] + can_filter.FilterMode = CAN_FILTERMODE_IDMASK; + 8001062: 2300 movs r3, #0 + 8001064: 623b str r3, [r7, #32] + can_filter.FilterScale = CAN_FILTERSCALE_32BIT; + 8001066: 2301 movs r3, #1 + 8001068: 627b str r3, [r7, #36] ; 0x24 + can_filter.SlaveStartFilterBank = 0; + 800106a: 2300 movs r3, #0 + 800106c: 62fb str r3, [r7, #44] ; 0x2c + if (HAL_CAN_ConfigFilter(ams_can_handle, &can_filter) != HAL_OK) { + 800106e: 4b18 ldr r3, [pc, #96] ; (80010d0 ) + 8001070: 681b ldr r3, [r3, #0] + 8001072: f107 0208 add.w r2, r7, #8 + 8001076: 4611 mov r1, r2 + 8001078: 4618 mov r0, r3 + 800107a: f001 fa1e bl 80024ba + 800107e: 4603 mov r3, r0 + 8001080: 2b00 cmp r3, #0 + 8001082: d001 beq.n 8001088 + Error_Handler(); + 8001084: f000 fed8 bl 8001e38 + } + can_filter.FilterBank++; + 8001088: 69fb ldr r3, [r7, #28] + 800108a: 3301 adds r3, #1 + 800108c: 61fb str r3, [r7, #28] + can_filter.FilterIdHigh = CAN_ID_MASTER_HEARTBEAT << (16 - 11); + 800108e: f44f 7300 mov.w r3, #512 ; 0x200 + 8001092: 60bb str r3, [r7, #8] + can_filter.FilterIdLow = 0; + 8001094: 2300 movs r3, #0 + 8001096: 60fb str r3, [r7, #12] + if (HAL_CAN_ConfigFilter(ams_can_handle, &can_filter) != HAL_OK) { + 8001098: 4b0d ldr r3, [pc, #52] ; (80010d0 ) + 800109a: 681b ldr r3, [r3, #0] + 800109c: f107 0208 add.w r2, r7, #8 + 80010a0: 4611 mov r1, r2 + 80010a2: 4618 mov r0, r3 + 80010a4: f001 fa09 bl 80024ba + 80010a8: 4603 mov r3, r0 + 80010aa: 2b00 cmp r3, #0 + 80010ac: d001 beq.n 80010b2 + Error_Handler(); + 80010ae: f000 fec3 bl 8001e38 + } + + // Activate RX notifications + if (HAL_CAN_ActivateNotification(ams_can_handle, + 80010b2: 4b07 ldr r3, [pc, #28] ; (80010d0 ) + 80010b4: 681b ldr r3, [r3, #0] + 80010b6: 2102 movs r1, #2 + 80010b8: 4618 mov r0, r3 + 80010ba: f001 fd2e bl 8002b1a + 80010be: 4603 mov r3, r0 + 80010c0: 2b00 cmp r3, #0 + 80010c2: d001 beq.n 80010c8 + CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { + Error_Handler(); + 80010c4: f000 feb8 bl 8001e38 + } +} + 80010c8: bf00 nop + 80010ca: 3730 adds r7, #48 ; 0x30 + 80010cc: 46bd mov sp, r7 + 80010ce: bd80 pop {r7, pc} + 80010d0: 2000004c .word 0x2000004c + +080010d4 : + +static int cb_triggered = 0; + +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef* handle) { + 80010d4: b580 push {r7, lr} + 80010d6: b082 sub sp, #8 + 80010d8: af00 add r7, sp, #0 + 80010da: 6078 str r0, [r7, #4] + static CAN_RxHeaderTypeDef header; + static uint8_t data[8]; + cb_triggered = 1; + 80010dc: 4b0e ldr r3, [pc, #56] ; (8001118 ) + 80010de: 2201 movs r2, #1 + 80010e0: 601a str r2, [r3, #0] + + if (HAL_CAN_GetRxMessage(handle, CAN_RX_FIFO0, &header, data) != HAL_OK) { + 80010e2: 4b0e ldr r3, [pc, #56] ; (800111c ) + 80010e4: 4a0e ldr r2, [pc, #56] ; (8001120 ) + 80010e6: 2100 movs r1, #0 + 80010e8: 6878 ldr r0, [r7, #4] + 80010ea: f001 fc04 bl 80028f6 + 80010ee: 4603 mov r3, r0 + 80010f0: 2b00 cmp r3, #0 + 80010f2: d001 beq.n 80010f8 + Error_Handler(); + 80010f4: f000 fea0 bl 8001e38 + } + + if (handle == ams_can_handle) { + 80010f8: 4b0a ldr r3, [pc, #40] ; (8001124 ) + 80010fa: 681b ldr r3, [r3, #0] + 80010fc: 687a ldr r2, [r7, #4] + 80010fe: 429a cmp r2, r3 + 8001100: d104 bne.n 800110c + ams_can_handle_ams_msg(&header, data); + 8001102: 4906 ldr r1, [pc, #24] ; (800111c ) + 8001104: 4806 ldr r0, [pc, #24] ; (8001120 ) + 8001106: f000 f80f bl 8001128 + } else { + Error_Handler(); + } +} + 800110a: e001 b.n 8001110 + Error_Handler(); + 800110c: f000 fe94 bl 8001e38 +} + 8001110: bf00 nop + 8001112: 3708 adds r7, #8 + 8001114: 46bd mov sp, r7 + 8001116: bd80 pop {r7, pc} + 8001118: 20000050 .word 0x20000050 + 800111c: 20000070 .word 0x20000070 + 8001120: 20000054 .word 0x20000054 + 8001124: 2000004c .word 0x2000004c + +08001128 : + +void ams_can_handle_ams_msg(CAN_RxHeaderTypeDef* header, uint8_t* data) { + 8001128: b480 push {r7} + 800112a: b085 sub sp, #20 + 800112c: af00 add r7, sp, #0 + 800112e: 6078 str r0, [r7, #4] + 8001130: 6039 str r1, [r7, #0] + + if(BMS_IN_TEST_MODE == 1){ + PENDING_MESSAGE_HANDLE = 1; + 8001132: 4b0e ldr r3, [pc, #56] ; (800116c ) + 8001134: 2201 movs r2, #1 + 8001136: 601a str r2, [r3, #0] + for(int i = 0; i < 8; i++){ + 8001138: 2300 movs r3, #0 + 800113a: 60fb str r3, [r7, #12] + 800113c: e00b b.n 8001156 + canTestData[i] = data[i]; + 800113e: 68fb ldr r3, [r7, #12] + 8001140: 683a ldr r2, [r7, #0] + 8001142: 4413 add r3, r2 + 8001144: 7819 ldrb r1, [r3, #0] + 8001146: 4a0a ldr r2, [pc, #40] ; (8001170 ) + 8001148: 68fb ldr r3, [r7, #12] + 800114a: 4413 add r3, r2 + 800114c: 460a mov r2, r1 + 800114e: 701a strb r2, [r3, #0] + for(int i = 0; i < 8; i++){ + 8001150: 68fb ldr r3, [r7, #12] + 8001152: 3301 adds r3, #1 + 8001154: 60fb str r3, [r7, #12] + 8001156: 68fb ldr r3, [r7, #12] + 8001158: 2b07 cmp r3, #7 + 800115a: ddf0 ble.n 800113e + } + return; + 800115c: bf00 nop + 800115e: bf00 nop + break; + case CAN_ID_MASTER_HEARTBEAT: +// clock_sync_handle_master_heartbeat(); + break; + } +} + 8001160: 3714 adds r7, #20 + 8001162: 46bd mov sp, r7 + 8001164: f85d 7b04 ldr.w r7, [sp], #4 + 8001168: 4770 bx lr + 800116a: bf00 nop + 800116c: 20000040 .word 0x20000040 + 8001170: 20000044 .word 0x20000044 + +08001174 : + +void ams_can_send_heartbeat() { + 8001174: b580 push {r7, lr} + 8001176: b086 sub sp, #24 + 8001178: af00 add r7, sp, #0 + static CAN_TxHeaderTypeDef header; + static uint8_t data[8]; + + header.IDE = CAN_ID_STD; + 800117a: 4b2c ldr r3, [pc, #176] ; (800122c ) + 800117c: 2200 movs r2, #0 + 800117e: 609a str r2, [r3, #8] + header.DLC = 8; + 8001180: 4b2a ldr r3, [pc, #168] ; (800122c ) + 8001182: 2208 movs r2, #8 + 8001184: 611a str r2, [r3, #16] + header.RTR = CAN_RTR_DATA; + 8001186: 4b29 ldr r3, [pc, #164] ; (800122c ) + 8001188: 2200 movs r2, #0 + 800118a: 60da str r2, [r3, #12] + header.TransmitGlobalTime = DISABLE; + 800118c: 4b27 ldr r3, [pc, #156] ; (800122c ) + 800118e: 2200 movs r2, #0 + 8001190: 751a strb r2, [r3, #20] + + // Send voltages + for (int msg_id = 0; msg_id < 5; msg_id++) { + 8001192: 2300 movs r3, #0 + 8001194: 617b str r3, [r7, #20] + 8001196: e040 b.n 800121a + header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new format + 8001198: 697b ldr r3, [r7, #20] + 800119a: f443 63c0 orr.w r3, r3, #1536 ; 0x600 + 800119e: 461a mov r2, r3 + 80011a0: 4b22 ldr r3, [pc, #136] ; (800122c ) + 80011a2: 601a str r2, [r3, #0] + for (int i = 0; i < 4; i++) { + 80011a4: 2300 movs r3, #0 + 80011a6: 613b str r3, [r7, #16] + 80011a8: e020 b.n 80011ec + int cell = msg_id * 4 + i; + 80011aa: 697b ldr r3, [r7, #20] + 80011ac: 009b lsls r3, r3, #2 + 80011ae: 693a ldr r2, [r7, #16] + 80011b0: 4413 add r3, r2 + 80011b2: 60fb str r3, [r7, #12] + uint16_t v = (cell < N_CELLS) ? module.cellVoltages[cell] : 0; + 80011b4: 68fb ldr r3, [r7, #12] + 80011b6: 2b10 cmp r3, #16 + 80011b8: dc04 bgt.n 80011c4 + 80011ba: 4a1d ldr r2, [pc, #116] ; (8001230 ) + 80011bc: 68fb ldr r3, [r7, #12] + 80011be: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 80011c2: e000 b.n 80011c6 + 80011c4: 2300 movs r3, #0 + 80011c6: 817b strh r3, [r7, #10] + data[2 * i + 0] = v & 0xFF; + 80011c8: 693b ldr r3, [r7, #16] + 80011ca: 005b lsls r3, r3, #1 + 80011cc: 897a ldrh r2, [r7, #10] + 80011ce: b2d1 uxtb r1, r2 + 80011d0: 4a18 ldr r2, [pc, #96] ; (8001234 ) + 80011d2: 54d1 strb r1, [r2, r3] + data[2 * i + 1] = v >> 8; + 80011d4: 897b ldrh r3, [r7, #10] + 80011d6: 0a1b lsrs r3, r3, #8 + 80011d8: b29a uxth r2, r3 + 80011da: 693b ldr r3, [r7, #16] + 80011dc: 005b lsls r3, r3, #1 + 80011de: 3301 adds r3, #1 + 80011e0: b2d1 uxtb r1, r2 + 80011e2: 4a14 ldr r2, [pc, #80] ; (8001234 ) + 80011e4: 54d1 strb r1, [r2, r3] + for (int i = 0; i < 4; i++) { + 80011e6: 693b ldr r3, [r7, #16] + 80011e8: 3301 adds r3, #1 + 80011ea: 613b str r3, [r7, #16] + 80011ec: 693b ldr r3, [r7, #16] + 80011ee: 2b03 cmp r3, #3 + 80011f0: dddb ble.n 80011aa + } + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, + 80011f2: 4b11 ldr r3, [pc, #68] ; (8001238 ) + 80011f4: 681b ldr r3, [r3, #0] + 80011f6: 220a movs r2, #10 + 80011f8: 2101 movs r1, #1 + 80011fa: 4618 mov r0, r3 + 80011fc: f000 f81e bl 800123c + 8001200: 4603 mov r3, r0 + 8001202: 2b00 cmp r3, #0 + 8001204: d106 bne.n 8001214 + CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + 8001206: 4b0c ldr r3, [pc, #48] ; (8001238 ) + 8001208: 6818 ldr r0, [r3, #0] + 800120a: 1d3b adds r3, r7, #4 + 800120c: 4a09 ldr r2, [pc, #36] ; (8001234 ) + 800120e: 4907 ldr r1, [pc, #28] ; (800122c ) + 8001210: f001 fa61 bl 80026d6 + for (int msg_id = 0; msg_id < 5; msg_id++) { + 8001214: 697b ldr r3, [r7, #20] + 8001216: 3301 adds r3, #1 + 8001218: 617b str r3, [r7, #20] + 800121a: 697b ldr r3, [r7, #20] + 800121c: 2b04 cmp r3, #4 + 800121e: ddbb ble.n 8001198 + CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + } + }*/ +} + 8001220: bf00 nop + 8001222: bf00 nop + 8001224: 3718 adds r7, #24 + 8001226: 46bd mov sp, r7 + 8001228: bd80 pop {r7, pc} + 800122a: bf00 nop + 800122c: 20000078 .word 0x20000078 + 8001230: 20000098 .word 0x20000098 + 8001234: 20000090 .word 0x20000090 + 8001238: 2000004c .word 0x2000004c + +0800123c : + ams_can_wait_for_free_mailboxes(ams_can_handle, 3, transmission_timeout); +}*/ + +HAL_StatusTypeDef ams_can_wait_for_free_mailboxes(CAN_HandleTypeDef* handle, + int num_mailboxes, + uint32_t timeout) { + 800123c: b580 push {r7, lr} + 800123e: b086 sub sp, #24 + 8001240: af00 add r7, sp, #0 + 8001242: 60f8 str r0, [r7, #12] + 8001244: 60b9 str r1, [r7, #8] + 8001246: 607a str r2, [r7, #4] + uint32_t end = HAL_GetTick() + timeout; + 8001248: f001 f80c bl 8002264 + 800124c: 4602 mov r2, r0 + 800124e: 687b ldr r3, [r7, #4] + 8001250: 4413 add r3, r2 + 8001252: 617b str r3, [r7, #20] + while (HAL_GetTick() < end) { + 8001254: e008 b.n 8001268 + if (HAL_CAN_GetTxMailboxesFreeLevel(handle) >= num_mailboxes) { + 8001256: 68f8 ldr r0, [r7, #12] + 8001258: f001 fb18 bl 800288c + 800125c: 4602 mov r2, r0 + 800125e: 68bb ldr r3, [r7, #8] + 8001260: 429a cmp r2, r3 + 8001262: d301 bcc.n 8001268 + return HAL_OK; + 8001264: 2300 movs r3, #0 + 8001266: e006 b.n 8001276 + while (HAL_GetTick() < end) { + 8001268: f000 fffc bl 8002264 + 800126c: 4602 mov r2, r0 + 800126e: 697b ldr r3, [r7, #20] + 8001270: 4293 cmp r3, r2 + 8001272: d8f0 bhi.n 8001256 + } + } + return HAL_TIMEOUT; + 8001274: 2303 movs r3, #3 +} + 8001276: 4618 mov r0, r3 + 8001278: 3718 adds r7, #24 + 800127a: 46bd mov sp, r7 + 800127c: bd80 pop {r7, pc} + ... + +08001280 : + +amsState currentAMSState = AMSDEACTIVE; +amsState lastAMSState = AMSDEACTIVE; + +void AMS_Init(SPI_HandleTypeDef *hspi) +{ + 8001280: b580 push {r7, lr} + 8001282: b082 sub sp, #8 + 8001284: af00 add r7, sp, #0 + 8001286: 6078 str r0, [r7, #4] + if(eepromconfigured == 1) + 8001288: 4b12 ldr r3, [pc, #72] ; (80012d4 ) + 800128a: 781b ldrb r3, [r3, #0] + 800128c: 2b01 cmp r3, #1 + 800128e: d10a bne.n 80012a6 + /*amsov = eepromcellovervoltage>>4; + amsuv = (eepromcellundervoltage-1)>>4; + numberofCells = eepromnumofcells; + numberofAux = eepromnumofaux; + initAMS(hspi, eepromnumofcells, eepromnumofaux);*/ + amsConfigOverVoltage(amsov); + 8001290: 4b11 ldr r3, [pc, #68] ; (80012d8 ) + 8001292: 881b ldrh r3, [r3, #0] + 8001294: 4618 mov r0, r3 + 8001296: f7ff fa1e bl 80006d6 + amsConfigUnderVoltage(amsuv); + 800129a: 4b10 ldr r3, [pc, #64] ; (80012dc ) + 800129c: 881b ldrh r3, [r3, #0] + 800129e: 4618 mov r0, r3 + 80012a0: f7ff f95e bl 8000560 + 80012a4: e00f b.n 80012c6 + } + else + { + initAMS(hspi, numberofCells, numberofAux); + 80012a6: 4b0e ldr r3, [pc, #56] ; (80012e0 ) + 80012a8: 781b ldrb r3, [r3, #0] + 80012aa: 4a0e ldr r2, [pc, #56] ; (80012e4 ) + 80012ac: 7812 ldrb r2, [r2, #0] + 80012ae: 4619 mov r1, r3 + 80012b0: 6878 ldr r0, [r7, #4] + 80012b2: f7fe ff89 bl 80001c8 + amsov = DEFAULT_OV; + 80012b6: 4b08 ldr r3, [pc, #32] ; (80012d8 ) + 80012b8: f640 2241 movw r2, #2625 ; 0xa41 + 80012bc: 801a strh r2, [r3, #0] + amsuv = DEFAULT_UV; + 80012be: 4b07 ldr r3, [pc, #28] ; (80012dc ) + 80012c0: f240 621a movw r2, #1562 ; 0x61a + 80012c4: 801a strh r2, [r3, #0] + } + + + currentAMSState = AMSIDLE; + 80012c6: 4b08 ldr r3, [pc, #32] ; (80012e8 ) + 80012c8: 2201 movs r2, #1 + 80012ca: 701a strb r2, [r3, #0] + + +} + 80012cc: bf00 nop + 80012ce: 3708 adds r7, #8 + 80012d0: 46bd mov sp, r7 + 80012d2: bd80 pop {r7, pc} + 80012d4: 20000108 .word 0x20000108 + 80012d8: 2000010c .word 0x2000010c + 80012dc: 2000010a .word 0x2000010a + 80012e0: 20000000 .word 0x20000000 + 80012e4: 2000010f .word 0x2000010f + 80012e8: 20000110 .word 0x20000110 + +080012ec : + +void AMS_Loop() +{ + 80012ec: b580 push {r7, lr} + 80012ee: af00 add r7, sp, #0 + + //On Transition Functions called ones if the State Changed + + if(currentAMSState != lastAMSState) + 80012f0: 4b25 ldr r3, [pc, #148] ; (8001388 ) + 80012f2: 781a ldrb r2, [r3, #0] + 80012f4: 4b25 ldr r3, [pc, #148] ; (800138c ) + 80012f6: 781b ldrb r3, [r3, #0] + 80012f8: 429a cmp r2, r3 + 80012fa: d023 beq.n 8001344 + { + switch(currentAMSState) + 80012fc: 4b22 ldr r3, [pc, #136] ; (8001388 ) + 80012fe: 781b ldrb r3, [r3, #0] + 8001300: 2b06 cmp r3, #6 + 8001302: d81b bhi.n 800133c + 8001304: a201 add r2, pc, #4 ; (adr r2, 800130c ) + 8001306: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800130a: bf00 nop + 800130c: 0800133d .word 0x0800133d + 8001310: 0800133d .word 0x0800133d + 8001314: 0800133d .word 0x0800133d + 8001318: 0800133d .word 0x0800133d + 800131c: 0800133d .word 0x0800133d + 8001320: 08001329 .word 0x08001329 + 8001324: 08001331 .word 0x08001331 + case AMSIDLEBALANCING: + break; + case AMSDISCHARGING: + break; + case AMSWARNING: + writeWarningLog(0x01); + 8001328: 2001 movs r0, #1 + 800132a: f000 f8a7 bl 800147c + break; + 800132e: e005 b.n 800133c + case AMSERROR: + writeErrorLog(amserrorcode); + 8001330: 4b17 ldr r3, [pc, #92] ; (8001390 ) + 8001332: 781b ldrb r3, [r3, #0] + 8001334: 4618 mov r0, r3 + 8001336: f000 f8ad bl 8001494 + break; + 800133a: bf00 nop + } + lastAMSState = currentAMSState; + 800133c: 4b12 ldr r3, [pc, #72] ; (8001388 ) + 800133e: 781a ldrb r2, [r3, #0] + 8001340: 4b12 ldr r3, [pc, #72] ; (800138c ) + 8001342: 701a strb r2, [r3, #0] + } + + //Main Loops for different AMS States + + switch(currentAMSState) + 8001344: 4b10 ldr r3, [pc, #64] ; (8001388 ) + 8001346: 781b ldrb r3, [r3, #0] + 8001348: 2b06 cmp r3, #6 + 800134a: d81b bhi.n 8001384 + 800134c: a201 add r2, pc, #4 ; (adr r2, 8001354 ) + 800134e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8001352: bf00 nop + 8001354: 08001383 .word 0x08001383 + 8001358: 08001371 .word 0x08001371 + 800135c: 08001383 .word 0x08001383 + 8001360: 08001377 .word 0x08001377 + 8001364: 08001383 .word 0x08001383 + 8001368: 0800137d .word 0x0800137d + 800136c: 08001383 .word 0x08001383 + { + case AMSIDLE: + AMS_Idle_Loop(); + 8001370: f000 f810 bl 8001394 + break; + 8001374: e006 b.n 8001384 + case AMSDEACTIVE: + break; + case AMSCHARGING: + break; + case AMSIDLEBALANCING: + AMS_Idle_Loop(); + 8001376: f000 f80d bl 8001394 + break; + 800137a: e003 b.n 8001384 + case AMSDISCHARGING: + break; + case AMSWARNING: + AMS_Warning_Loop(); + 800137c: f000 f844 bl 8001408 + break; + 8001380: e000 b.n 8001384 + break; + 8001382: bf00 nop + case AMSERROR: + break; + } +} + 8001384: bf00 nop + 8001386: bd80 pop {r7, pc} + 8001388: 20000110 .word 0x20000110 + 800138c: 20000111 .word 0x20000111 + 8001390: 2000010e .word 0x2000010e + +08001394 : + +uint8_t AMS_Idle_Loop() +{ + 8001394: b580 push {r7, lr} + 8001396: af00 add r7, sp, #0 + amsWakeUp(); + 8001398: f7fe ff40 bl 800021c + amsConfigOverVoltage(amsov); + 800139c: 4b15 ldr r3, [pc, #84] ; (80013f4 ) + 800139e: 881b ldrh r3, [r3, #0] + 80013a0: 4618 mov r0, r3 + 80013a2: f7ff f998 bl 80006d6 + amsConfigUnderVoltage(amsuv); + 80013a6: 4b14 ldr r3, [pc, #80] ; (80013f8 ) + 80013a8: 881b ldrh r3, [r3, #0] + 80013aa: 4618 mov r0, r3 + 80013ac: f7ff f8d8 bl 8000560 + amsConfigAuxMeasurement(0xFFFF); + 80013b0: f64f 70ff movw r0, #65535 ; 0xffff + 80013b4: f7ff f836 bl 8000424 + amsClearAux(); + 80013b8: f7ff f9b9 bl 800072e + amsCellMeasurement(&module); + 80013bc: 480f ldr r0, [pc, #60] ; (80013fc ) + 80013be: f7fe ff3b bl 8000238 + amsInternalStatusMeasurement(&module); + 80013c2: 480e ldr r0, [pc, #56] ; (80013fc ) + 80013c4: f7fe ffe4 bl 8000390 + amsAuxMeasurement(&module); + 80013c8: 480c ldr r0, [pc, #48] ; (80013fc ) + 80013ca: f7fe ff4c bl 8000266 + amsCheckUnderOverVoltage(&module); + 80013ce: 480b ldr r0, [pc, #44] ; (80013fc ) + 80013d0: f7ff f8f3 bl 80005ba + integrateCurrent(); + 80013d4: f000 f86a bl 80014ac + + static uint32_t channelstobalance = 1; + + channelstobalance = 0x1FFFF; + 80013d8: 4b09 ldr r3, [pc, #36] ; (8001400 ) + 80013da: 4a0a ldr r2, [pc, #40] ; (8001404 ) + 80013dc: 601a str r2, [r3, #0] + /* if(channelstobalance & 0x20000){ + channelstobalance = 1; + }*/ + + amsConfigBalancing(channelstobalance); + 80013de: 4b08 ldr r3, [pc, #32] ; (8001400 ) + 80013e0: 681b ldr r3, [r3, #0] + 80013e2: 4618 mov r0, r3 + 80013e4: f7ff f84e bl 8000484 + amsStartBalancing(100); + 80013e8: 2064 movs r0, #100 ; 0x64 + 80013ea: f7ff f8a0 bl 800052e + { + amsStopBalancing(); + }*/ + //amsConfigBalancing(balancedCells); + //volatile amscheck = amscheckOpenCellWire(&module); + return 0; + 80013ee: 2300 movs r3, #0 +} + 80013f0: 4618 mov r0, r3 + 80013f2: bd80 pop {r7, pc} + 80013f4: 2000010c .word 0x2000010c + 80013f8: 2000010a .word 0x2000010a + 80013fc: 20000098 .word 0x20000098 + 8001400: 20000004 .word 0x20000004 + 8001404: 0001ffff .word 0x0001ffff + +08001408 : + +uint8_t AMS_Warning_Loop() +{ + 8001408: b580 push {r7, lr} + 800140a: af00 add r7, sp, #0 + + amsWakeUp(); + 800140c: f7fe ff06 bl 800021c + amsConfigOverVoltage(amsov); + 8001410: 4b16 ldr r3, [pc, #88] ; (800146c ) + 8001412: 881b ldrh r3, [r3, #0] + 8001414: 4618 mov r0, r3 + 8001416: f7ff f95e bl 80006d6 + amsConfigUnderVoltage(amsuv); + 800141a: 4b15 ldr r3, [pc, #84] ; (8001470 ) + 800141c: 881b ldrh r3, [r3, #0] + 800141e: 4618 mov r0, r3 + 8001420: f7ff f89e bl 8000560 + amsConfigAuxMeasurement(0xFFFF); + 8001424: f64f 70ff movw r0, #65535 ; 0xffff + 8001428: f7fe fffc bl 8000424 + amsClearAux(); + 800142c: f7ff f97f bl 800072e + amsCellMeasurement(&module); + 8001430: 4810 ldr r0, [pc, #64] ; (8001474 ) + 8001432: f7fe ff01 bl 8000238 + amsInternalStatusMeasurement(&module); + 8001436: 480f ldr r0, [pc, #60] ; (8001474 ) + 8001438: f7fe ffaa bl 8000390 + amsAuxMeasurement(&module); + 800143c: 480d ldr r0, [pc, #52] ; (8001474 ) + 800143e: f7fe ff12 bl 8000266 + amsCheckUnderOverVoltage(&module); + 8001442: 480c ldr r0, [pc, #48] ; (8001474 ) + 8001444: f7ff f8b9 bl 80005ba + + if(!(module.overVoltage | module.underVoltage)) + 8001448: 4b0a ldr r3, [pc, #40] ; (8001474 ) + 800144a: 6d9a ldr r2, [r3, #88] ; 0x58 + 800144c: 4b09 ldr r3, [pc, #36] ; (8001474 ) + 800144e: 6ddb ldr r3, [r3, #92] ; 0x5c + 8001450: 4313 orrs r3, r2 + 8001452: 2b00 cmp r3, #0 + 8001454: d104 bne.n 8001460 + { + currentAMSState = AMSIDLE; + 8001456: 4b08 ldr r3, [pc, #32] ; (8001478 ) + 8001458: 2201 movs r2, #1 + 800145a: 701a strb r2, [r3, #0] + amsClearWarning(); + 800145c: f7ff f976 bl 800074c + } + amsStopBalancing(); + 8001460: f7ff f874 bl 800054c + + return 0; + 8001464: 2300 movs r3, #0 +} + 8001466: 4618 mov r0, r3 + 8001468: bd80 pop {r7, pc} + 800146a: bf00 nop + 800146c: 2000010c .word 0x2000010c + 8001470: 2000010a .word 0x2000010a + 8001474: 20000098 .word 0x20000098 + 8001478: 20000110 .word 0x20000110 + +0800147c : + } + return balancingdone; +} + +uint8_t writeWarningLog(uint8_t warningCode) +{ + 800147c: b480 push {r7} + 800147e: b083 sub sp, #12 + 8001480: af00 add r7, sp, #0 + 8001482: 4603 mov r3, r0 + 8001484: 71fb strb r3, [r7, #7] + //eepromWriteWarningLog(warningCode); + return 0; + 8001486: 2300 movs r3, #0 +} + 8001488: 4618 mov r0, r3 + 800148a: 370c adds r7, #12 + 800148c: 46bd mov sp, r7 + 800148e: f85d 7b04 ldr.w r7, [sp], #4 + 8001492: 4770 bx lr + +08001494 : +uint8_t writeErrorLog(uint8_t errorCode) +{ + 8001494: b480 push {r7} + 8001496: b083 sub sp, #12 + 8001498: af00 add r7, sp, #0 + 800149a: 4603 mov r3, r0 + 800149c: 71fb strb r3, [r7, #7] + //eepromWriteErrorLog(errorCode); + return 0; + 800149e: 2300 movs r3, #0 +} + 80014a0: 4618 mov r0, r3 + 80014a2: 370c adds r7, #12 + 80014a4: 46bd mov sp, r7 + 80014a6: f85d 7b04 ldr.w r7, [sp], #4 + 80014aa: 4770 bx lr + +080014ac : + +uint8_t integrateCurrent() +{ + 80014ac: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 80014b0: af00 add r7, sp, #0 + lastticks = currenttick; + 80014b2: 4b17 ldr r3, [pc, #92] ; (8001510 ) + 80014b4: 681b ldr r3, [r3, #0] + 80014b6: 4a17 ldr r2, [pc, #92] ; (8001514 ) + 80014b8: 6013 str r3, [r2, #0] + currenttick = HAL_GetTick(); + 80014ba: f000 fed3 bl 8002264 + 80014be: 4603 mov r3, r0 + 80014c0: 4a13 ldr r2, [pc, #76] ; (8001510 ) + 80014c2: 6013 str r3, [r2, #0] + if(currenttick < lastticks) + 80014c4: 4b12 ldr r3, [pc, #72] ; (8001510 ) + 80014c6: 681a ldr r2, [r3, #0] + 80014c8: 4b12 ldr r3, [pc, #72] ; (8001514 ) + 80014ca: 681b ldr r3, [r3, #0] + 80014cc: 429a cmp r2, r3 + 80014ce: d21a bcs.n 8001506 + { + currentintegrator += (module.auxVoltages[0] - module.auxVoltages[2])*(currenttick-lastticks); + 80014d0: 4b11 ldr r3, [pc, #68] ; (8001518 ) + 80014d2: 8c9b ldrh r3, [r3, #36] ; 0x24 + 80014d4: 461a mov r2, r3 + 80014d6: 4b10 ldr r3, [pc, #64] ; (8001518 ) + 80014d8: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80014da: 1ad3 subs r3, r2, r3 + 80014dc: 4619 mov r1, r3 + 80014de: 4b0c ldr r3, [pc, #48] ; (8001510 ) + 80014e0: 681a ldr r2, [r3, #0] + 80014e2: 4b0c ldr r3, [pc, #48] ; (8001514 ) + 80014e4: 681b ldr r3, [r3, #0] + 80014e6: 1ad3 subs r3, r2, r3 + 80014e8: fb01 f303 mul.w r3, r1, r3 + 80014ec: 2200 movs r2, #0 + 80014ee: 461c mov r4, r3 + 80014f0: 4615 mov r5, r2 + 80014f2: 4b0a ldr r3, [pc, #40] ; (800151c ) + 80014f4: e9d3 2300 ldrd r2, r3, [r3] + 80014f8: eb14 0802 adds.w r8, r4, r2 + 80014fc: eb45 0903 adc.w r9, r5, r3 + 8001500: 4b06 ldr r3, [pc, #24] ; (800151c ) + 8001502: e9c3 8900 strd r8, r9, [r3] + } + return 0; + 8001506: 2300 movs r3, #0 +} + 8001508: 4618 mov r0, r3 + 800150a: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 800150e: bf00 nop + 8001510: 20000104 .word 0x20000104 + 8001514: 20000100 .word 0x20000100 + 8001518: 20000098 .word 0x20000098 + 800151c: 200000f8 .word 0x200000f8 + +08001520 : +#include +#include "ADBMS_Abstraction.h" +#include "main.h" + + +void canTestSendTemperatures(uint16_t* data){ + 8001520: b580 push {r7, lr} + 8001522: b092 sub sp, #72 ; 0x48 + 8001524: af00 add r7, sp, #0 + 8001526: 6078 str r0, [r7, #4] + static CAN_TxHeaderTypeDef header; + + header.IDE = CAN_ID_STD; + 8001528: 4b59 ldr r3, [pc, #356] ; (8001690 ) + 800152a: 2200 movs r2, #0 + 800152c: 609a str r2, [r3, #8] + header.DLC = 8; + 800152e: 4b58 ldr r3, [pc, #352] ; (8001690 ) + 8001530: 2208 movs r2, #8 + 8001532: 611a str r2, [r3, #16] + header.RTR = CAN_RTR_DATA; + 8001534: 4b56 ldr r3, [pc, #344] ; (8001690 ) + 8001536: 2200 movs r2, #0 + 8001538: 60da str r2, [r3, #12] + header.TransmitGlobalTime = DISABLE; + 800153a: 4b55 ldr r3, [pc, #340] ; (8001690 ) + 800153c: 2200 movs r2, #0 + 800153e: 751a strb r2, [r3, #20] + uint8_t buffer[24]; + uint8_t tmp[8]; + + for(int i = 0; i < 12; i++){ + 8001540: 2300 movs r3, #0 + 8001542: 647b str r3, [r7, #68] ; 0x44 + 8001544: e01d b.n 8001582 + buffer[((i*2)+1)] = data[i] >> 8; + 8001546: 6c7b ldr r3, [r7, #68] ; 0x44 + 8001548: 005b lsls r3, r3, #1 + 800154a: 687a ldr r2, [r7, #4] + 800154c: 4413 add r3, r2 + 800154e: 881b ldrh r3, [r3, #0] + 8001550: 0a1b lsrs r3, r3, #8 + 8001552: b29a uxth r2, r3 + 8001554: 6c7b ldr r3, [r7, #68] ; 0x44 + 8001556: 005b lsls r3, r3, #1 + 8001558: 3301 adds r3, #1 + 800155a: b2d2 uxtb r2, r2 + 800155c: 3348 adds r3, #72 ; 0x48 + 800155e: 443b add r3, r7 + 8001560: f803 2c2c strb.w r2, [r3, #-44] + buffer[(i*2)] = data[i]; + 8001564: 6c7b ldr r3, [r7, #68] ; 0x44 + 8001566: 005b lsls r3, r3, #1 + 8001568: 687a ldr r2, [r7, #4] + 800156a: 4413 add r3, r2 + 800156c: 881a ldrh r2, [r3, #0] + 800156e: 6c7b ldr r3, [r7, #68] ; 0x44 + 8001570: 005b lsls r3, r3, #1 + 8001572: b2d2 uxtb r2, r2 + 8001574: 3348 adds r3, #72 ; 0x48 + 8001576: 443b add r3, r7 + 8001578: f803 2c2c strb.w r2, [r3, #-44] + for(int i = 0; i < 12; i++){ + 800157c: 6c7b ldr r3, [r7, #68] ; 0x44 + 800157e: 3301 adds r3, #1 + 8001580: 647b str r3, [r7, #68] ; 0x44 + 8001582: 6c7b ldr r3, [r7, #68] ; 0x44 + 8001584: 2b0b cmp r3, #11 + 8001586: ddde ble.n 8001546 + } + + for(int i = 0; i < 8; i++){ + 8001588: 2300 movs r3, #0 + 800158a: 643b str r3, [r7, #64] ; 0x40 + 800158c: e00d b.n 80015aa + tmp[i] = buffer[i]; + 800158e: f107 021c add.w r2, r7, #28 + 8001592: 6c3b ldr r3, [r7, #64] ; 0x40 + 8001594: 4413 add r3, r2 + 8001596: 7819 ldrb r1, [r3, #0] + 8001598: f107 0214 add.w r2, r7, #20 + 800159c: 6c3b ldr r3, [r7, #64] ; 0x40 + 800159e: 4413 add r3, r2 + 80015a0: 460a mov r2, r1 + 80015a2: 701a strb r2, [r3, #0] + for(int i = 0; i < 8; i++){ + 80015a4: 6c3b ldr r3, [r7, #64] ; 0x40 + 80015a6: 3301 adds r3, #1 + 80015a8: 643b str r3, [r7, #64] ; 0x40 + 80015aa: 6c3b ldr r3, [r7, #64] ; 0x40 + 80015ac: 2b07 cmp r3, #7 + 80015ae: ddee ble.n 800158e + } + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 80015b0: 4b38 ldr r3, [pc, #224] ; (8001694 ) + 80015b2: 681b ldr r3, [r3, #0] + 80015b4: 220a movs r2, #10 + 80015b6: 2101 movs r1, #1 + 80015b8: 4618 mov r0, r3 + 80015ba: f7ff fe3f bl 800123c + 80015be: 4603 mov r3, r0 + 80015c0: 2b00 cmp r3, #0 + 80015c2: d108 bne.n 80015d6 + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + 80015c4: 4b33 ldr r3, [pc, #204] ; (8001694 ) + 80015c6: 6818 ldr r0, [r3, #0] + 80015c8: f107 0310 add.w r3, r7, #16 + 80015cc: f107 0214 add.w r2, r7, #20 + 80015d0: 492f ldr r1, [pc, #188] ; (8001690 ) + 80015d2: f001 f880 bl 80026d6 + } + + int m = 0; + 80015d6: 2300 movs r3, #0 + 80015d8: 63fb str r3, [r7, #60] ; 0x3c + for(int i = 8; i < 16; i++){ + 80015da: 2308 movs r3, #8 + 80015dc: 63bb str r3, [r7, #56] ; 0x38 + 80015de: e010 b.n 8001602 + tmp[m] = buffer[i]; + 80015e0: f107 021c add.w r2, r7, #28 + 80015e4: 6bbb ldr r3, [r7, #56] ; 0x38 + 80015e6: 4413 add r3, r2 + 80015e8: 7819 ldrb r1, [r3, #0] + 80015ea: f107 0214 add.w r2, r7, #20 + 80015ee: 6bfb ldr r3, [r7, #60] ; 0x3c + 80015f0: 4413 add r3, r2 + 80015f2: 460a mov r2, r1 + 80015f4: 701a strb r2, [r3, #0] + m++; + 80015f6: 6bfb ldr r3, [r7, #60] ; 0x3c + 80015f8: 3301 adds r3, #1 + 80015fa: 63fb str r3, [r7, #60] ; 0x3c + for(int i = 8; i < 16; i++){ + 80015fc: 6bbb ldr r3, [r7, #56] ; 0x38 + 80015fe: 3301 adds r3, #1 + 8001600: 63bb str r3, [r7, #56] ; 0x38 + 8001602: 6bbb ldr r3, [r7, #56] ; 0x38 + 8001604: 2b0f cmp r3, #15 + 8001606: ddeb ble.n 80015e0 + } + + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 8001608: 4b22 ldr r3, [pc, #136] ; (8001694 ) + 800160a: 681b ldr r3, [r3, #0] + 800160c: 220a movs r2, #10 + 800160e: 2101 movs r1, #1 + 8001610: 4618 mov r0, r3 + 8001612: f7ff fe13 bl 800123c + 8001616: 4603 mov r3, r0 + 8001618: 2b00 cmp r3, #0 + 800161a: d108 bne.n 800162e + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + 800161c: 4b1d ldr r3, [pc, #116] ; (8001694 ) + 800161e: 6818 ldr r0, [r3, #0] + 8001620: f107 030c add.w r3, r7, #12 + 8001624: f107 0214 add.w r2, r7, #20 + 8001628: 4919 ldr r1, [pc, #100] ; (8001690 ) + 800162a: f001 f854 bl 80026d6 + } + m = 0; + 800162e: 2300 movs r3, #0 + 8001630: 63fb str r3, [r7, #60] ; 0x3c + for(int i = 16; i < 24; i++){ + 8001632: 2310 movs r3, #16 + 8001634: 637b str r3, [r7, #52] ; 0x34 + 8001636: e010 b.n 800165a + tmp[m] = buffer[i]; + 8001638: f107 021c add.w r2, r7, #28 + 800163c: 6b7b ldr r3, [r7, #52] ; 0x34 + 800163e: 4413 add r3, r2 + 8001640: 7819 ldrb r1, [r3, #0] + 8001642: f107 0214 add.w r2, r7, #20 + 8001646: 6bfb ldr r3, [r7, #60] ; 0x3c + 8001648: 4413 add r3, r2 + 800164a: 460a mov r2, r1 + 800164c: 701a strb r2, [r3, #0] + m++; + 800164e: 6bfb ldr r3, [r7, #60] ; 0x3c + 8001650: 3301 adds r3, #1 + 8001652: 63fb str r3, [r7, #60] ; 0x3c + for(int i = 16; i < 24; i++){ + 8001654: 6b7b ldr r3, [r7, #52] ; 0x34 + 8001656: 3301 adds r3, #1 + 8001658: 637b str r3, [r7, #52] ; 0x34 + 800165a: 6b7b ldr r3, [r7, #52] ; 0x34 + 800165c: 2b17 cmp r3, #23 + 800165e: ddeb ble.n 8001638 + } + + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 8001660: 4b0c ldr r3, [pc, #48] ; (8001694 ) + 8001662: 681b ldr r3, [r3, #0] + 8001664: 220a movs r2, #10 + 8001666: 2101 movs r1, #1 + 8001668: 4618 mov r0, r3 + 800166a: f7ff fde7 bl 800123c + 800166e: 4603 mov r3, r0 + 8001670: 2b00 cmp r3, #0 + 8001672: d108 bne.n 8001686 + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + 8001674: 4b07 ldr r3, [pc, #28] ; (8001694 ) + 8001676: 6818 ldr r0, [r3, #0] + 8001678: f107 0308 add.w r3, r7, #8 + 800167c: f107 0214 add.w r2, r7, #20 + 8001680: 4903 ldr r1, [pc, #12] ; (8001690 ) + 8001682: f001 f828 bl 80026d6 + } +} + 8001686: bf00 nop + 8001688: 3748 adds r7, #72 ; 0x48 + 800168a: 46bd mov sp, r7 + 800168c: bd80 pop {r7, pc} + 800168e: bf00 nop + 8001690: 20000114 .word 0x20000114 + 8001694: 2000004c .word 0x2000004c + +08001698 : + +void canTestSendAnswer(uint8_t* data){ + 8001698: b580 push {r7, lr} + 800169a: b084 sub sp, #16 + 800169c: af00 add r7, sp, #0 + 800169e: 6078 str r0, [r7, #4] + static CAN_TxHeaderTypeDef header; + + header.IDE = CAN_ID_STD; + 80016a0: 4b10 ldr r3, [pc, #64] ; (80016e4 ) + 80016a2: 2200 movs r2, #0 + 80016a4: 609a str r2, [r3, #8] + header.DLC = 8; + 80016a6: 4b0f ldr r3, [pc, #60] ; (80016e4 ) + 80016a8: 2208 movs r2, #8 + 80016aa: 611a str r2, [r3, #16] + header.RTR = CAN_RTR_DATA; + 80016ac: 4b0d ldr r3, [pc, #52] ; (80016e4 ) + 80016ae: 2200 movs r2, #0 + 80016b0: 60da str r2, [r3, #12] + header.TransmitGlobalTime = DISABLE; + 80016b2: 4b0c ldr r3, [pc, #48] ; (80016e4 ) + 80016b4: 2200 movs r2, #0 + 80016b6: 751a strb r2, [r3, #20] + + if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, + 80016b8: 4b0b ldr r3, [pc, #44] ; (80016e8 ) + 80016ba: 681b ldr r3, [r3, #0] + 80016bc: 220a movs r2, #10 + 80016be: 2101 movs r1, #1 + 80016c0: 4618 mov r0, r3 + 80016c2: f7ff fdbb bl 800123c + 80016c6: 4603 mov r3, r0 + 80016c8: 2b00 cmp r3, #0 + 80016ca: d107 bne.n 80016dc + CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + uint32_t mailbox; + HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + 80016cc: 4b06 ldr r3, [pc, #24] ; (80016e8 ) + 80016ce: 6818 ldr r0, [r3, #0] + 80016d0: f107 030c add.w r3, r7, #12 + 80016d4: 687a ldr r2, [r7, #4] + 80016d6: 4903 ldr r1, [pc, #12] ; (80016e4 ) + 80016d8: f000 fffd bl 80026d6 + } +} + 80016dc: bf00 nop + 80016de: 3710 adds r7, #16 + 80016e0: 46bd mov sp, r7 + 80016e2: bd80 pop {r7, pc} + 80016e4: 2000012c .word 0x2000012c + 80016e8: 2000004c .word 0x2000004c + +080016ec : + +void resetData(uint8_t* data){ + 80016ec: b480 push {r7} + 80016ee: b085 sub sp, #20 + 80016f0: af00 add r7, sp, #0 + 80016f2: 6078 str r0, [r7, #4] + for(int i = 0; i < 8; i++){ + 80016f4: 2300 movs r3, #0 + 80016f6: 60fb str r3, [r7, #12] + 80016f8: e005 b.n 8001706 + data[0] = 0; + 80016fa: 687b ldr r3, [r7, #4] + 80016fc: 2200 movs r2, #0 + 80016fe: 701a strb r2, [r3, #0] + for(int i = 0; i < 8; i++){ + 8001700: 68fb ldr r3, [r7, #12] + 8001702: 3301 adds r3, #1 + 8001704: 60fb str r3, [r7, #12] + 8001706: 68fb ldr r3, [r7, #12] + 8001708: 2b07 cmp r3, #7 + 800170a: ddf6 ble.n 80016fa + } + +} + 800170c: bf00 nop + 800170e: bf00 nop + 8001710: 3714 adds r7, #20 + 8001712: 46bd mov sp, r7 + 8001714: f85d 7b04 ldr.w r7, [sp], #4 + 8001718: 4770 bx lr + +0800171a : +void readTemperatures(){ + 800171a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800171e: b086 sub sp, #24 + 8001720: af00 add r7, sp, #0 + 8001722: 466b mov r3, sp + 8001724: 4698 mov r8, r3 + uint8_t last_error = 0; + 8001726: 2300 movs r3, #0 + 8001728: 74fb strb r3, [r7, #19] + int N_SENSORS = 12; + 800172a: 230c movs r3, #12 + 800172c: 60fb str r3, [r7, #12] + uint16_t temperatures[N_SENSORS]; + 800172e: 68fe ldr r6, [r7, #12] + 8001730: 1e73 subs r3, r6, #1 + 8001732: 60bb str r3, [r7, #8] + 8001734: 4632 mov r2, r6 + 8001736: 2300 movs r3, #0 + 8001738: 4614 mov r4, r2 + 800173a: 461d mov r5, r3 + 800173c: f04f 0200 mov.w r2, #0 + 8001740: f04f 0300 mov.w r3, #0 + 8001744: 012b lsls r3, r5, #4 + 8001746: ea43 7314 orr.w r3, r3, r4, lsr #28 + 800174a: 0122 lsls r2, r4, #4 + 800174c: 4632 mov r2, r6 + 800174e: 2300 movs r3, #0 + 8001750: 4610 mov r0, r2 + 8001752: 4619 mov r1, r3 + 8001754: f04f 0200 mov.w r2, #0 + 8001758: f04f 0300 mov.w r3, #0 + 800175c: 010b lsls r3, r1, #4 + 800175e: ea43 7310 orr.w r3, r3, r0, lsr #28 + 8001762: 0102 lsls r2, r0, #4 + 8001764: 4633 mov r3, r6 + 8001766: 005b lsls r3, r3, #1 + 8001768: 3307 adds r3, #7 + 800176a: 08db lsrs r3, r3, #3 + 800176c: 00db lsls r3, r3, #3 + 800176e: ebad 0d03 sub.w sp, sp, r3 + 8001772: 466b mov r3, sp + 8001774: 3301 adds r3, #1 + 8001776: 085b lsrs r3, r3, #1 + 8001778: 005b lsls r3, r3, #1 + 800177a: 607b str r3, [r7, #4] + for (int i = 0; i < N_SENSORS; i++) { + 800177c: 2300 movs r3, #0 + 800177e: 617b str r3, [r7, #20] + 8001780: e014 b.n 80017ac + if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 8001782: 697b ldr r3, [r7, #20] + 8001784: 005b lsls r3, r3, #1 + 8001786: 687a ldr r2, [r7, #4] + 8001788: 4413 add r3, r2 + 800178a: 4619 mov r1, r3 + 800178c: 6978 ldr r0, [r7, #20] + 800178e: f000 fae9 bl 8001d64 + 8001792: 4603 mov r3, r0 + 8001794: 2b00 cmp r3, #0 + 8001796: d006 beq.n 80017a6 + sensor_init(i); + 8001798: 6978 ldr r0, [r7, #20] + 800179a: f000 fac5 bl 8001d28 + last_error = HAL_GetTick(); + 800179e: f000 fd61 bl 8002264 + 80017a2: 4603 mov r3, r0 + 80017a4: 74fb strb r3, [r7, #19] + for (int i = 0; i < N_SENSORS; i++) { + 80017a6: 697b ldr r3, [r7, #20] + 80017a8: 3301 adds r3, #1 + 80017aa: 617b str r3, [r7, #20] + 80017ac: 697a ldr r2, [r7, #20] + 80017ae: 68fb ldr r3, [r7, #12] + 80017b0: 429a cmp r2, r3 + 80017b2: dbe6 blt.n 8001782 + } + } + canTestSendTemperatures(temperatures); + 80017b4: 6878 ldr r0, [r7, #4] + 80017b6: f7ff feb3 bl 8001520 + 80017ba: 46c5 mov sp, r8 +} + 80017bc: bf00 nop + 80017be: 3718 adds r7, #24 + 80017c0: 46bd mov sp, r7 + 80017c2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + ... + +080017c8 : + +void testLoop(uint8_t* data){ + 80017c8: b580 push {r7, lr} + 80017ca: b086 sub sp, #24 + 80017cc: af00 add r7, sp, #0 + 80017ce: 6078 str r0, [r7, #4] + uint8_t action = data[0]; + 80017d0: 687b ldr r3, [r7, #4] + 80017d2: 781b ldrb r3, [r3, #0] + 80017d4: 73fb strb r3, [r7, #15] + switch(action){ + 80017d6: 7bfb ldrb r3, [r7, #15] + 80017d8: 3b01 subs r3, #1 + 80017da: 2b04 cmp r3, #4 + 80017dc: f200 8091 bhi.w 8001902 + 80017e0: a201 add r2, pc, #4 ; (adr r2, 80017e8 ) + 80017e2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80017e6: bf00 nop + 80017e8: 080017fd .word 0x080017fd + 80017ec: 0800180b .word 0x0800180b + 80017f0: 0800181d .word 0x0800181d + 80017f4: 0800182b .word 0x0800182b + 80017f8: 080018ab .word 0x080018ab + case CAN_TEST: + HAL_Delay(100); + 80017fc: 2064 movs r0, #100 ; 0x64 + 80017fe: f000 fd3d bl 800227c + canTestSendAnswer(data); + 8001802: 6878 ldr r0, [r7, #4] + 8001804: f7ff ff48 bl 8001698 + break; + 8001808: e07b b.n 8001902 + case VOLTAGE_TEST: + HAL_Delay(100); + 800180a: 2064 movs r0, #100 ; 0x64 + 800180c: f000 fd36 bl 800227c + amsReadCellVoltages(&module); + 8001810: 483f ldr r0, [pc, #252] ; (8001910 ) + 8001812: f7fe ffa3 bl 800075c + ams_can_send_heartbeat(); + 8001816: f7ff fcad bl 8001174 + break; + 800181a: e072 b.n 8001902 + case TEMP_TEST: + HAL_Delay(1000); + 800181c: f44f 707a mov.w r0, #1000 ; 0x3e8 + 8001820: f000 fd2c bl 800227c + readTemperatures(); + 8001824: f7ff ff79 bl 800171a + break; + 8001828: e06b b.n 8001902 + case EPROM_TEST: + HAL_Delay(1000); + 800182a: f44f 707a mov.w r0, #1000 ; 0x3e8 + 800182e: f000 fd25 bl 800227c + for(uint16_t i = 1; i < 9; i++ ){ + 8001832: 2301 movs r3, #1 + 8001834: 82fb strh r3, [r7, #22] + 8001836: e016 b.n 8001866 + if(i == 4){ + 8001838: 8afb ldrh r3, [r7, #22] + 800183a: 2b04 cmp r3, #4 + 800183c: d108 bne.n 8001850 + writeeeprom(i*3, 0x42); + 800183e: 8afa ldrh r2, [r7, #22] + 8001840: 4613 mov r3, r2 + 8001842: 005b lsls r3, r3, #1 + 8001844: 4413 add r3, r2 + 8001846: 2142 movs r1, #66 ; 0x42 + 8001848: 4618 mov r0, r3 + 800184a: f000 fad7 bl 8001dfc + 800184e: e007 b.n 8001860 + }else{ + writeeeprom(i*3, 0x69); + 8001850: 8afa ldrh r2, [r7, #22] + 8001852: 4613 mov r3, r2 + 8001854: 005b lsls r3, r3, #1 + 8001856: 4413 add r3, r2 + 8001858: 2169 movs r1, #105 ; 0x69 + 800185a: 4618 mov r0, r3 + 800185c: f000 face bl 8001dfc + for(uint16_t i = 1; i < 9; i++ ){ + 8001860: 8afb ldrh r3, [r7, #22] + 8001862: 3301 adds r3, #1 + 8001864: 82fb strh r3, [r7, #22] + 8001866: 8afb ldrh r3, [r7, #22] + 8001868: 2b08 cmp r3, #8 + 800186a: d9e5 bls.n 8001838 + } + } + + HAL_Delay(1000); + 800186c: f44f 707a mov.w r0, #1000 ; 0x3e8 + 8001870: f000 fd04 bl 800227c + for(uint16_t i = 1; i < 9; i++ ){ + 8001874: 2301 movs r3, #1 + 8001876: 82bb strh r3, [r7, #20] + 8001878: e010 b.n 800189c + data[i-1] = readeeprom(i*3); + 800187a: 8aba ldrh r2, [r7, #20] + 800187c: 4613 mov r3, r2 + 800187e: 005b lsls r3, r3, #1 + 8001880: 4413 add r3, r2 + 8001882: 4618 mov r0, r3 + 8001884: f000 fa9e bl 8001dc4 + 8001888: 4601 mov r1, r0 + 800188a: 8abb ldrh r3, [r7, #20] + 800188c: 3b01 subs r3, #1 + 800188e: 687a ldr r2, [r7, #4] + 8001890: 4413 add r3, r2 + 8001892: b2ca uxtb r2, r1 + 8001894: 701a strb r2, [r3, #0] + for(uint16_t i = 1; i < 9; i++ ){ + 8001896: 8abb ldrh r3, [r7, #20] + 8001898: 3301 adds r3, #1 + 800189a: 82bb strh r3, [r7, #20] + 800189c: 8abb ldrh r3, [r7, #20] + 800189e: 2b08 cmp r3, #8 + 80018a0: d9eb bls.n 800187a + } + canTestSendAnswer(data); + 80018a2: 6878 ldr r0, [r7, #4] + 80018a4: f7ff fef8 bl 8001698 + break; + 80018a8: e02b b.n 8001902 + case BALANCING_TEST: + HAL_Delay(1000); + 80018aa: f44f 707a mov.w r0, #1000 ; 0x3e8 + 80018ae: f000 fce5 bl 800227c + for(int i = 0; i < 17; i++){ + 80018b2: 2300 movs r3, #0 + 80018b4: 613b str r3, [r7, #16] + 80018b6: e010 b.n 80018da + amsConfigBalancing(0x00001< + amsStartBalancing(10); + 80018c6: 200a movs r0, #10 + 80018c8: f7fe fe31 bl 800052e + HAL_Delay(1000); + 80018cc: f44f 707a mov.w r0, #1000 ; 0x3e8 + 80018d0: f000 fcd4 bl 800227c + for(int i = 0; i < 17; i++){ + 80018d4: 693b ldr r3, [r7, #16] + 80018d6: 3301 adds r3, #1 + 80018d8: 613b str r3, [r7, #16] + 80018da: 693b ldr r3, [r7, #16] + 80018dc: 2b10 cmp r3, #16 + 80018de: ddeb ble.n 80018b8 + } + HAL_Delay(1000); + 80018e0: f44f 707a mov.w r0, #1000 ; 0x3e8 + 80018e4: f000 fcca bl 800227c + amsConfigBalancing(0x1FFFF); + 80018e8: 480a ldr r0, [pc, #40] ; (8001914 ) + 80018ea: f7fe fdcb bl 8000484 + amsStartBalancing(10); + 80018ee: 200a movs r0, #10 + 80018f0: f7fe fe1d bl 800052e + HAL_Delay(1000); + 80018f4: f44f 707a mov.w r0, #1000 ; 0x3e8 + 80018f8: f000 fcc0 bl 800227c + amsStopBalancing(); + 80018fc: f7fe fe26 bl 800054c + break; + 8001900: bf00 nop + + } + resetData(data); + 8001902: 6878 ldr r0, [r7, #4] + 8001904: f7ff fef2 bl 80016ec +} + 8001908: bf00 nop + 800190a: 3718 adds r7, #24 + 800190c: 46bd mov sp, r7 + 800190e: bd80 pop {r7, pc} + 8001910: 20000098 .word 0x20000098 + 8001914: 0001ffff .word 0x0001ffff + +08001918

: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8001918: b580 push {r7, lr} + 800191a: b088 sub sp, #32 + 800191c: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 800191e: f000 fc47 bl 80021b0 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 8001922: f000 f853 bl 80019cc + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8001926: f000 f99b bl 8001c60 + MX_CAN_Init(); + 800192a: f000 f8a5 bl 8001a78 + MX_I2C1_Init(); + 800192e: f000 f8d9 bl 8001ae4 + MX_I2C2_Init(); + 8001932: f000 f917 bl 8001b64 + MX_SPI1_Init(); + 8001936: f000 f955 bl 8001be4 + /* USER CODE BEGIN 2 */ + // eepromInitParameters(); + for (int i = 0; i < N_SENSORS; i++) { + 800193a: 2300 movs r3, #0 + 800193c: 61fb str r3, [r7, #28] + 800193e: e00d b.n 800195c + if (sensor_init(i) != HAL_OK) { + 8001940: 69f8 ldr r0, [r7, #28] + 8001942: f000 f9f1 bl 8001d28 + 8001946: 4603 mov r3, r0 + 8001948: 2b00 cmp r3, #0 + 800194a: d004 beq.n 8001956 + last_error = HAL_GetTick(); + 800194c: f000 fc8a bl 8002264 + 8001950: 4603 mov r3, r0 + 8001952: 4a1a ldr r2, [pc, #104] ; (80019bc ) + 8001954: 6013 str r3, [r2, #0] + for (int i = 0; i < N_SENSORS; i++) { + 8001956: 69fb ldr r3, [r7, #28] + 8001958: 3301 adds r3, #1 + 800195a: 61fb str r3, [r7, #28] + 800195c: 69fb ldr r3, [r7, #28] + 800195e: 2b0b cmp r3, #11 + 8001960: ddee ble.n 8001940 + } + } + + AMS_Init(&hspi1); + 8001962: 4817 ldr r0, [pc, #92] ; (80019c0 ) + 8001964: f7ff fc8c bl 8001280 + ams_can_init(&hcan, &hcan); + 8001968: 4916 ldr r1, [pc, #88] ; (80019c4 ) + 800196a: 4816 ldr r0, [pc, #88] ; (80019c4 ) + 800196c: f7ff fb4e bl 800100c +// HAL_TIM_Base_Start(&htim2); + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + writeeeprom(1, 69); + 8001970: 2145 movs r1, #69 ; 0x45 + 8001972: 2001 movs r0, #1 + 8001974: f000 fa42 bl 8001dfc + uint16_t temperatures[N_SENSORS]; + AMS_Loop(); + 8001978: f7ff fcb8 bl 80012ec + while (1){ + if(BMS_IN_TEST_MODE == 1 ){ ////&& PENDING_MESSAGE_HANDLE == 1 + testLoop(&canTestData); + 800197c: 4812 ldr r0, [pc, #72] ; (80019c8 ) + 800197e: f7ff ff23 bl 80017c8 + /* USER CODE END WHILE */ + /* USER CODE BEGIN 3 */ + + for (int i = 0; i < N_SENSORS; i++) { + 8001982: 2300 movs r3, #0 + 8001984: 61bb str r3, [r7, #24] + 8001986: e015 b.n 80019b4 + if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 8001988: 463a mov r2, r7 + 800198a: 69bb ldr r3, [r7, #24] + 800198c: 005b lsls r3, r3, #1 + 800198e: 4413 add r3, r2 + 8001990: 4619 mov r1, r3 + 8001992: 69b8 ldr r0, [r7, #24] + 8001994: f000 f9e6 bl 8001d64 + 8001998: 4603 mov r3, r0 + 800199a: 2b00 cmp r3, #0 + 800199c: d007 beq.n 80019ae + sensor_init(i); + 800199e: 69b8 ldr r0, [r7, #24] + 80019a0: f000 f9c2 bl 8001d28 + last_error = HAL_GetTick(); + 80019a4: f000 fc5e bl 8002264 + 80019a8: 4603 mov r3, r0 + 80019aa: 4a04 ldr r2, [pc, #16] ; (80019bc ) + 80019ac: 6013 str r3, [r2, #0] + for (int i = 0; i < N_SENSORS; i++) { + 80019ae: 69bb ldr r3, [r7, #24] + 80019b0: 3301 adds r3, #1 + 80019b2: 61bb str r3, [r7, #24] + 80019b4: 69bb ldr r3, [r7, #24] + 80019b6: 2b0b cmp r3, #11 + 80019b8: dde6 ble.n 8001988 + if(BMS_IN_TEST_MODE == 1 ){ ////&& PENDING_MESSAGE_HANDLE == 1 + 80019ba: e7df b.n 800197c + 80019bc: 20000268 .word 0x20000268 + 80019c0: 20000204 .word 0x20000204 + 80019c4: 20000144 .word 0x20000144 + 80019c8: 20000044 .word 0x20000044 + +080019cc : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 80019cc: b580 push {r7, lr} + 80019ce: b09c sub sp, #112 ; 0x70 + 80019d0: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 80019d2: f107 0348 add.w r3, r7, #72 ; 0x48 + 80019d6: 2228 movs r2, #40 ; 0x28 + 80019d8: 2100 movs r1, #0 + 80019da: 4618 mov r0, r3 + 80019dc: f004 fd6c bl 80064b8 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 80019e0: f107 0334 add.w r3, r7, #52 ; 0x34 + 80019e4: 2200 movs r2, #0 + 80019e6: 601a str r2, [r3, #0] + 80019e8: 605a str r2, [r3, #4] + 80019ea: 609a str r2, [r3, #8] + 80019ec: 60da str r2, [r3, #12] + 80019ee: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 80019f0: 463b mov r3, r7 + 80019f2: 2234 movs r2, #52 ; 0x34 + 80019f4: 2100 movs r1, #0 + 80019f6: 4618 mov r0, r3 + 80019f8: f004 fd5e bl 80064b8 + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE; + 80019fc: 2303 movs r3, #3 + 80019fe: 64bb str r3, [r7, #72] ; 0x48 + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 8001a00: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8001a04: 64fb str r3, [r7, #76] ; 0x4c + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 8001a06: 2301 movs r3, #1 + 8001a08: 65bb str r3, [r7, #88] ; 0x58 + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8001a0a: 2310 movs r3, #16 + 8001a0c: 65fb str r3, [r7, #92] ; 0x5c + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 8001a0e: 2300 movs r3, #0 + 8001a10: 667b str r3, [r7, #100] ; 0x64 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8001a12: f107 0348 add.w r3, r7, #72 ; 0x48 + 8001a16: 4618 mov r0, r3 + 8001a18: f002 fd50 bl 80044bc + 8001a1c: 4603 mov r3, r0 + 8001a1e: 2b00 cmp r3, #0 + 8001a20: d001 beq.n 8001a26 + { + Error_Handler(); + 8001a22: f000 fa09 bl 8001e38 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8001a26: 230f movs r3, #15 + 8001a28: 637b str r3, [r7, #52] ; 0x34 + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; + 8001a2a: 2301 movs r3, #1 + 8001a2c: 63bb str r3, [r7, #56] ; 0x38 + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8001a2e: 2300 movs r3, #0 + 8001a30: 63fb str r3, [r7, #60] ; 0x3c + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8001a32: 2300 movs r3, #0 + 8001a34: 643b str r3, [r7, #64] ; 0x40 + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8001a36: 2300 movs r3, #0 + 8001a38: 647b str r3, [r7, #68] ; 0x44 + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 8001a3a: f107 0334 add.w r3, r7, #52 ; 0x34 + 8001a3e: 2100 movs r1, #0 + 8001a40: 4618 mov r0, r3 + 8001a42: f003 fd79 bl 8005538 + 8001a46: 4603 mov r3, r0 + 8001a48: 2b00 cmp r3, #0 + 8001a4a: d001 beq.n 8001a50 + { + Error_Handler(); + 8001a4c: f000 f9f4 bl 8001e38 + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C2; + 8001a50: 2360 movs r3, #96 ; 0x60 + 8001a52: 603b str r3, [r7, #0] + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; + 8001a54: 2300 movs r3, #0 + 8001a56: 61fb str r3, [r7, #28] + PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_HSI; + 8001a58: 2300 movs r3, #0 + 8001a5a: 623b str r3, [r7, #32] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8001a5c: 463b mov r3, r7 + 8001a5e: 4618 mov r0, r3 + 8001a60: f003 ff52 bl 8005908 + 8001a64: 4603 mov r3, r0 + 8001a66: 2b00 cmp r3, #0 + 8001a68: d001 beq.n 8001a6e + { + Error_Handler(); + 8001a6a: f000 f9e5 bl 8001e38 + } +} + 8001a6e: bf00 nop + 8001a70: 3770 adds r7, #112 ; 0x70 + 8001a72: 46bd mov sp, r7 + 8001a74: bd80 pop {r7, pc} + ... + +08001a78 : + * @brief CAN Initialization Function + * @param None + * @retval None + */ +static void MX_CAN_Init(void) +{ + 8001a78: b580 push {r7, lr} + 8001a7a: af00 add r7, sp, #0 + /* USER CODE END CAN_Init 0 */ + + /* USER CODE BEGIN CAN_Init 1 */ + + /* USER CODE END CAN_Init 1 */ + hcan.Instance = CAN; + 8001a7c: 4b17 ldr r3, [pc, #92] ; (8001adc ) + 8001a7e: 4a18 ldr r2, [pc, #96] ; (8001ae0 ) + 8001a80: 601a str r2, [r3, #0] + hcan.Init.Prescaler = 2; + 8001a82: 4b16 ldr r3, [pc, #88] ; (8001adc ) + 8001a84: 2202 movs r2, #2 + 8001a86: 605a str r2, [r3, #4] + hcan.Init.Mode = CAN_MODE_NORMAL; + 8001a88: 4b14 ldr r3, [pc, #80] ; (8001adc ) + 8001a8a: 2200 movs r2, #0 + 8001a8c: 609a str r2, [r3, #8] + hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; + 8001a8e: 4b13 ldr r3, [pc, #76] ; (8001adc ) + 8001a90: 2200 movs r2, #0 + 8001a92: 60da str r2, [r3, #12] + hcan.Init.TimeSeg1 = CAN_BS1_13TQ; + 8001a94: 4b11 ldr r3, [pc, #68] ; (8001adc ) + 8001a96: f44f 2240 mov.w r2, #786432 ; 0xc0000 + 8001a9a: 611a str r2, [r3, #16] + hcan.Init.TimeSeg2 = CAN_BS2_2TQ; + 8001a9c: 4b0f ldr r3, [pc, #60] ; (8001adc ) + 8001a9e: f44f 1280 mov.w r2, #1048576 ; 0x100000 + 8001aa2: 615a str r2, [r3, #20] + hcan.Init.TimeTriggeredMode = DISABLE; + 8001aa4: 4b0d ldr r3, [pc, #52] ; (8001adc ) + 8001aa6: 2200 movs r2, #0 + 8001aa8: 761a strb r2, [r3, #24] + hcan.Init.AutoBusOff = ENABLE; + 8001aaa: 4b0c ldr r3, [pc, #48] ; (8001adc ) + 8001aac: 2201 movs r2, #1 + 8001aae: 765a strb r2, [r3, #25] + hcan.Init.AutoWakeUp = DISABLE; + 8001ab0: 4b0a ldr r3, [pc, #40] ; (8001adc ) + 8001ab2: 2200 movs r2, #0 + 8001ab4: 769a strb r2, [r3, #26] + hcan.Init.AutoRetransmission = ENABLE; + 8001ab6: 4b09 ldr r3, [pc, #36] ; (8001adc ) + 8001ab8: 2201 movs r2, #1 + 8001aba: 76da strb r2, [r3, #27] + hcan.Init.ReceiveFifoLocked = DISABLE; + 8001abc: 4b07 ldr r3, [pc, #28] ; (8001adc ) + 8001abe: 2200 movs r2, #0 + 8001ac0: 771a strb r2, [r3, #28] + hcan.Init.TransmitFifoPriority = DISABLE; + 8001ac2: 4b06 ldr r3, [pc, #24] ; (8001adc ) + 8001ac4: 2200 movs r2, #0 + 8001ac6: 775a strb r2, [r3, #29] + if (HAL_CAN_Init(&hcan) != HAL_OK) + 8001ac8: 4804 ldr r0, [pc, #16] ; (8001adc ) + 8001aca: f000 fbfb bl 80022c4 + 8001ace: 4603 mov r3, r0 + 8001ad0: 2b00 cmp r3, #0 + 8001ad2: d001 beq.n 8001ad8 + { + Error_Handler(); + 8001ad4: f000 f9b0 bl 8001e38 + } + /* USER CODE BEGIN CAN_Init 2 */ + + /* USER CODE END CAN_Init 2 */ + +} + 8001ad8: bf00 nop + 8001ada: bd80 pop {r7, pc} + 8001adc: 20000144 .word 0x20000144 + 8001ae0: 40006400 .word 0x40006400 + +08001ae4 : + * @brief I2C1 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C1_Init(void) +{ + 8001ae4: b580 push {r7, lr} + 8001ae6: af00 add r7, sp, #0 + /* USER CODE END I2C1_Init 0 */ + + /* USER CODE BEGIN I2C1_Init 1 */ + + /* USER CODE END I2C1_Init 1 */ + hi2c1.Instance = I2C1; + 8001ae8: 4b1b ldr r3, [pc, #108] ; (8001b58 ) + 8001aea: 4a1c ldr r2, [pc, #112] ; (8001b5c ) + 8001aec: 601a str r2, [r3, #0] + hi2c1.Init.Timing = 0x2000090E; + 8001aee: 4b1a ldr r3, [pc, #104] ; (8001b58 ) + 8001af0: 4a1b ldr r2, [pc, #108] ; (8001b60 ) + 8001af2: 605a str r2, [r3, #4] + hi2c1.Init.OwnAddress1 = 0; + 8001af4: 4b18 ldr r3, [pc, #96] ; (8001b58 ) + 8001af6: 2200 movs r2, #0 + 8001af8: 609a str r2, [r3, #8] + hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8001afa: 4b17 ldr r3, [pc, #92] ; (8001b58 ) + 8001afc: 2201 movs r2, #1 + 8001afe: 60da str r2, [r3, #12] + hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8001b00: 4b15 ldr r3, [pc, #84] ; (8001b58 ) + 8001b02: 2200 movs r2, #0 + 8001b04: 611a str r2, [r3, #16] + hi2c1.Init.OwnAddress2 = 0; + 8001b06: 4b14 ldr r3, [pc, #80] ; (8001b58 ) + 8001b08: 2200 movs r2, #0 + 8001b0a: 615a str r2, [r3, #20] + hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 8001b0c: 4b12 ldr r3, [pc, #72] ; (8001b58 ) + 8001b0e: 2200 movs r2, #0 + 8001b10: 619a str r2, [r3, #24] + hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8001b12: 4b11 ldr r3, [pc, #68] ; (8001b58 ) + 8001b14: 2200 movs r2, #0 + 8001b16: 61da str r2, [r3, #28] + hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8001b18: 4b0f ldr r3, [pc, #60] ; (8001b58 ) + 8001b1a: 2200 movs r2, #0 + 8001b1c: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 8001b1e: 480e ldr r0, [pc, #56] ; (8001b58 ) + 8001b20: f001 fcf4 bl 800350c + 8001b24: 4603 mov r3, r0 + 8001b26: 2b00 cmp r3, #0 + 8001b28: d001 beq.n 8001b2e + { + Error_Handler(); + 8001b2a: f000 f985 bl 8001e38 + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 8001b2e: 2100 movs r1, #0 + 8001b30: 4809 ldr r0, [pc, #36] ; (8001b58 ) + 8001b32: f002 fc2b bl 800438c + 8001b36: 4603 mov r3, r0 + 8001b38: 2b00 cmp r3, #0 + 8001b3a: d001 beq.n 8001b40 + { + Error_Handler(); + 8001b3c: f000 f97c bl 8001e38 + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 8001b40: 2100 movs r1, #0 + 8001b42: 4805 ldr r0, [pc, #20] ; (8001b58 ) + 8001b44: f002 fc6d bl 8004422 + 8001b48: 4603 mov r3, r0 + 8001b4a: 2b00 cmp r3, #0 + 8001b4c: d001 beq.n 8001b52 + { + Error_Handler(); + 8001b4e: f000 f973 bl 8001e38 + } + /* USER CODE BEGIN I2C1_Init 2 */ + + /* USER CODE END I2C1_Init 2 */ + +} + 8001b52: bf00 nop + 8001b54: bd80 pop {r7, pc} + 8001b56: bf00 nop + 8001b58: 2000016c .word 0x2000016c + 8001b5c: 40005400 .word 0x40005400 + 8001b60: 2000090e .word 0x2000090e + +08001b64 : + * @brief I2C2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C2_Init(void) +{ + 8001b64: b580 push {r7, lr} + 8001b66: af00 add r7, sp, #0 + /* USER CODE END I2C2_Init 0 */ + + /* USER CODE BEGIN I2C2_Init 1 */ + + /* USER CODE END I2C2_Init 1 */ + hi2c2.Instance = I2C2; + 8001b68: 4b1b ldr r3, [pc, #108] ; (8001bd8 ) + 8001b6a: 4a1c ldr r2, [pc, #112] ; (8001bdc ) + 8001b6c: 601a str r2, [r3, #0] + hi2c2.Init.Timing = 0x2000090E; + 8001b6e: 4b1a ldr r3, [pc, #104] ; (8001bd8 ) + 8001b70: 4a1b ldr r2, [pc, #108] ; (8001be0 ) + 8001b72: 605a str r2, [r3, #4] + hi2c2.Init.OwnAddress1 = 0; + 8001b74: 4b18 ldr r3, [pc, #96] ; (8001bd8 ) + 8001b76: 2200 movs r2, #0 + 8001b78: 609a str r2, [r3, #8] + hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 8001b7a: 4b17 ldr r3, [pc, #92] ; (8001bd8 ) + 8001b7c: 2201 movs r2, #1 + 8001b7e: 60da str r2, [r3, #12] + hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 8001b80: 4b15 ldr r3, [pc, #84] ; (8001bd8 ) + 8001b82: 2200 movs r2, #0 + 8001b84: 611a str r2, [r3, #16] + hi2c2.Init.OwnAddress2 = 0; + 8001b86: 4b14 ldr r3, [pc, #80] ; (8001bd8 ) + 8001b88: 2200 movs r2, #0 + 8001b8a: 615a str r2, [r3, #20] + hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 8001b8c: 4b12 ldr r3, [pc, #72] ; (8001bd8 ) + 8001b8e: 2200 movs r2, #0 + 8001b90: 619a str r2, [r3, #24] + hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 8001b92: 4b11 ldr r3, [pc, #68] ; (8001bd8 ) + 8001b94: 2200 movs r2, #0 + 8001b96: 61da str r2, [r3, #28] + hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 8001b98: 4b0f ldr r3, [pc, #60] ; (8001bd8 ) + 8001b9a: 2200 movs r2, #0 + 8001b9c: 621a str r2, [r3, #32] + if (HAL_I2C_Init(&hi2c2) != HAL_OK) + 8001b9e: 480e ldr r0, [pc, #56] ; (8001bd8 ) + 8001ba0: f001 fcb4 bl 800350c + 8001ba4: 4603 mov r3, r0 + 8001ba6: 2b00 cmp r3, #0 + 8001ba8: d001 beq.n 8001bae + { + Error_Handler(); + 8001baa: f000 f945 bl 8001e38 + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 8001bae: 2100 movs r1, #0 + 8001bb0: 4809 ldr r0, [pc, #36] ; (8001bd8 ) + 8001bb2: f002 fbeb bl 800438c + 8001bb6: 4603 mov r3, r0 + 8001bb8: 2b00 cmp r3, #0 + 8001bba: d001 beq.n 8001bc0 + { + Error_Handler(); + 8001bbc: f000 f93c bl 8001e38 + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) + 8001bc0: 2100 movs r1, #0 + 8001bc2: 4805 ldr r0, [pc, #20] ; (8001bd8 ) + 8001bc4: f002 fc2d bl 8004422 + 8001bc8: 4603 mov r3, r0 + 8001bca: 2b00 cmp r3, #0 + 8001bcc: d001 beq.n 8001bd2 + { + Error_Handler(); + 8001bce: f000 f933 bl 8001e38 + } + /* USER CODE BEGIN I2C2_Init 2 */ + + /* USER CODE END I2C2_Init 2 */ + +} + 8001bd2: bf00 nop + 8001bd4: bd80 pop {r7, pc} + 8001bd6: bf00 nop + 8001bd8: 200001b8 .word 0x200001b8 + 8001bdc: 40005800 .word 0x40005800 + 8001be0: 2000090e .word 0x2000090e + +08001be4 : + * @brief SPI1 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI1_Init(void) +{ + 8001be4: b580 push {r7, lr} + 8001be6: af00 add r7, sp, #0 + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + /* SPI1 parameter configuration*/ + hspi1.Instance = SPI1; + 8001be8: 4b1b ldr r3, [pc, #108] ; (8001c58 ) + 8001bea: 4a1c ldr r2, [pc, #112] ; (8001c5c ) + 8001bec: 601a str r2, [r3, #0] + hspi1.Init.Mode = SPI_MODE_MASTER; + 8001bee: 4b1a ldr r3, [pc, #104] ; (8001c58 ) + 8001bf0: f44f 7282 mov.w r2, #260 ; 0x104 + 8001bf4: 605a str r2, [r3, #4] + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 8001bf6: 4b18 ldr r3, [pc, #96] ; (8001c58 ) + 8001bf8: 2200 movs r2, #0 + 8001bfa: 609a str r2, [r3, #8] + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 8001bfc: 4b16 ldr r3, [pc, #88] ; (8001c58 ) + 8001bfe: f44f 62e0 mov.w r2, #1792 ; 0x700 + 8001c02: 60da str r2, [r3, #12] + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 8001c04: 4b14 ldr r3, [pc, #80] ; (8001c58 ) + 8001c06: 2200 movs r2, #0 + 8001c08: 611a str r2, [r3, #16] + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 8001c0a: 4b13 ldr r3, [pc, #76] ; (8001c58 ) + 8001c0c: 2200 movs r2, #0 + 8001c0e: 615a str r2, [r3, #20] + hspi1.Init.NSS = SPI_NSS_SOFT; + 8001c10: 4b11 ldr r3, [pc, #68] ; (8001c58 ) + 8001c12: f44f 7200 mov.w r2, #512 ; 0x200 + 8001c16: 619a str r2, [r3, #24] + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; + 8001c18: 4b0f ldr r3, [pc, #60] ; (8001c58 ) + 8001c1a: 2220 movs r2, #32 + 8001c1c: 61da str r2, [r3, #28] + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 8001c1e: 4b0e ldr r3, [pc, #56] ; (8001c58 ) + 8001c20: 2200 movs r2, #0 + 8001c22: 621a str r2, [r3, #32] + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 8001c24: 4b0c ldr r3, [pc, #48] ; (8001c58 ) + 8001c26: 2200 movs r2, #0 + 8001c28: 625a str r2, [r3, #36] ; 0x24 + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8001c2a: 4b0b ldr r3, [pc, #44] ; (8001c58 ) + 8001c2c: 2200 movs r2, #0 + 8001c2e: 629a str r2, [r3, #40] ; 0x28 + hspi1.Init.CRCPolynomial = 7; + 8001c30: 4b09 ldr r3, [pc, #36] ; (8001c58 ) + 8001c32: 2207 movs r2, #7 + 8001c34: 62da str r2, [r3, #44] ; 0x2c + hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + 8001c36: 4b08 ldr r3, [pc, #32] ; (8001c58 ) + 8001c38: 2200 movs r2, #0 + 8001c3a: 631a str r2, [r3, #48] ; 0x30 + hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + 8001c3c: 4b06 ldr r3, [pc, #24] ; (8001c58 ) + 8001c3e: 2208 movs r2, #8 + 8001c40: 635a str r2, [r3, #52] ; 0x34 + if (HAL_SPI_Init(&hspi1) != HAL_OK) + 8001c42: 4805 ldr r0, [pc, #20] ; (8001c58 ) + 8001c44: f003 fff2 bl 8005c2c + 8001c48: 4603 mov r3, r0 + 8001c4a: 2b00 cmp r3, #0 + 8001c4c: d001 beq.n 8001c52 + { + Error_Handler(); + 8001c4e: f000 f8f3 bl 8001e38 + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + 8001c52: bf00 nop + 8001c54: bd80 pop {r7, pc} + 8001c56: bf00 nop + 8001c58: 20000204 .word 0x20000204 + 8001c5c: 40013000 .word 0x40013000 + +08001c60 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8001c60: b580 push {r7, lr} + 8001c62: b088 sub sp, #32 + 8001c64: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001c66: f107 030c add.w r3, r7, #12 + 8001c6a: 2200 movs r2, #0 + 8001c6c: 601a str r2, [r3, #0] + 8001c6e: 605a str r2, [r3, #4] + 8001c70: 609a str r2, [r3, #8] + 8001c72: 60da str r2, [r3, #12] + 8001c74: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOF_CLK_ENABLE(); + 8001c76: 4b2a ldr r3, [pc, #168] ; (8001d20 ) + 8001c78: 695b ldr r3, [r3, #20] + 8001c7a: 4a29 ldr r2, [pc, #164] ; (8001d20 ) + 8001c7c: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 + 8001c80: 6153 str r3, [r2, #20] + 8001c82: 4b27 ldr r3, [pc, #156] ; (8001d20 ) + 8001c84: 695b ldr r3, [r3, #20] + 8001c86: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8001c8a: 60bb str r3, [r7, #8] + 8001c8c: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001c8e: 4b24 ldr r3, [pc, #144] ; (8001d20 ) + 8001c90: 695b ldr r3, [r3, #20] + 8001c92: 4a23 ldr r2, [pc, #140] ; (8001d20 ) + 8001c94: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001c98: 6153 str r3, [r2, #20] + 8001c9a: 4b21 ldr r3, [pc, #132] ; (8001d20 ) + 8001c9c: 695b ldr r3, [r3, #20] + 8001c9e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001ca2: 607b str r3, [r7, #4] + 8001ca4: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001ca6: 4b1e ldr r3, [pc, #120] ; (8001d20 ) + 8001ca8: 695b ldr r3, [r3, #20] + 8001caa: 4a1d ldr r2, [pc, #116] ; (8001d20 ) + 8001cac: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8001cb0: 6153 str r3, [r2, #20] + 8001cb2: 4b1b ldr r3, [pc, #108] ; (8001d20 ) + 8001cb4: 695b ldr r3, [r3, #20] + 8001cb6: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8001cba: 603b str r3, [r7, #0] + 8001cbc: 683b ldr r3, [r7, #0] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, CSB_Pin|Status_3_Pin, GPIO_PIN_RESET); + 8001cbe: 2200 movs r2, #0 + 8001cc0: f44f 7188 mov.w r1, #272 ; 0x110 + 8001cc4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001cc8: f001 fc08 bl 80034dc + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, Status_0_Pin|Status_1_Pin|Status_2_Pin, GPIO_PIN_RESET); + 8001ccc: 2200 movs r2, #0 + 8001cce: f44f 4160 mov.w r1, #57344 ; 0xe000 + 8001cd2: 4814 ldr r0, [pc, #80] ; (8001d24 ) + 8001cd4: f001 fc02 bl 80034dc + + /*Configure GPIO pins : CSB_Pin Status_3_Pin */ + GPIO_InitStruct.Pin = CSB_Pin|Status_3_Pin; + 8001cd8: f44f 7388 mov.w r3, #272 ; 0x110 + 8001cdc: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001cde: 2301 movs r3, #1 + 8001ce0: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001ce2: 2300 movs r3, #0 + 8001ce4: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001ce6: 2300 movs r3, #0 + 8001ce8: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001cea: f107 030c add.w r3, r7, #12 + 8001cee: 4619 mov r1, r3 + 8001cf0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001cf4: f001 fa78 bl 80031e8 + + /*Configure GPIO pins : Status_0_Pin Status_1_Pin Status_2_Pin */ + GPIO_InitStruct.Pin = Status_0_Pin|Status_1_Pin|Status_2_Pin; + 8001cf8: f44f 4360 mov.w r3, #57344 ; 0xe000 + 8001cfc: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8001cfe: 2301 movs r3, #1 + 8001d00: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001d02: 2300 movs r3, #0 + 8001d04: 617b str r3, [r7, #20] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001d06: 2300 movs r3, #0 + 8001d08: 61bb str r3, [r7, #24] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001d0a: f107 030c add.w r3, r7, #12 + 8001d0e: 4619 mov r1, r3 + 8001d10: 4804 ldr r0, [pc, #16] ; (8001d24 ) + 8001d12: f001 fa69 bl 80031e8 + +} + 8001d16: bf00 nop + 8001d18: 3720 adds r7, #32 + 8001d1a: 46bd mov sp, r7 + 8001d1c: bd80 pop {r7, pc} + 8001d1e: bf00 nop + 8001d20: 40021000 .word 0x40021000 + 8001d24: 48000400 .word 0x48000400 + +08001d28 : + +/* USER CODE BEGIN 4 */ +HAL_StatusTypeDef sensor_init(int n) { + 8001d28: b580 push {r7, lr} + 8001d2a: b086 sub sp, #24 + 8001d2c: af02 add r7, sp, #8 + 8001d2e: 6078 str r0, [r7, #4] + uint16_t addr = (0b1000000 | n) << 1; + 8001d30: 687b ldr r3, [r7, #4] + 8001d32: 005b lsls r3, r3, #1 + 8001d34: b21b sxth r3, r3 + 8001d36: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8001d3a: b21b sxth r3, r3 + 8001d3c: 81fb strh r3, [r7, #14] + uint8_t data[] = {0}; + 8001d3e: 2300 movs r3, #0 + 8001d40: 733b strb r3, [r7, #12] + return HAL_I2C_Master_Transmit(&hi2c1, addr, data, sizeof(data), 100); + 8001d42: f107 020c add.w r2, r7, #12 + 8001d46: 89f9 ldrh r1, [r7, #14] + 8001d48: 2364 movs r3, #100 ; 0x64 + 8001d4a: 9300 str r3, [sp, #0] + 8001d4c: 2301 movs r3, #1 + 8001d4e: 4804 ldr r0, [pc, #16] ; (8001d60 ) + 8001d50: f001 fc6c bl 800362c + 8001d54: 4603 mov r3, r0 +} + 8001d56: 4618 mov r0, r3 + 8001d58: 3710 adds r7, #16 + 8001d5a: 46bd mov sp, r7 + 8001d5c: bd80 pop {r7, pc} + 8001d5e: bf00 nop + 8001d60: 2000016c .word 0x2000016c + +08001d64 : + +HAL_StatusTypeDef sensor_read(int n, uint16_t *res) { + 8001d64: b580 push {r7, lr} + 8001d66: b086 sub sp, #24 + 8001d68: af02 add r7, sp, #8 + 8001d6a: 6078 str r0, [r7, #4] + 8001d6c: 6039 str r1, [r7, #0] + uint16_t addr = (0b1000000 | n) << 1; + 8001d6e: 687b ldr r3, [r7, #4] + 8001d70: 005b lsls r3, r3, #1 + 8001d72: b21b sxth r3, r3 + 8001d74: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8001d78: b21b sxth r3, r3 + 8001d7a: 81fb strh r3, [r7, #14] + addr |= 1; // Read + 8001d7c: 89fb ldrh r3, [r7, #14] + 8001d7e: f043 0301 orr.w r3, r3, #1 + 8001d82: 81fb strh r3, [r7, #14] + uint8_t result[2]; + HAL_StatusTypeDef status = + HAL_I2C_Master_Receive(&hi2c1, addr, result, sizeof(result), 100); + 8001d84: f107 0208 add.w r2, r7, #8 + 8001d88: 89f9 ldrh r1, [r7, #14] + 8001d8a: 2364 movs r3, #100 ; 0x64 + 8001d8c: 9300 str r3, [sp, #0] + 8001d8e: 2302 movs r3, #2 + 8001d90: 480b ldr r0, [pc, #44] ; (8001dc0 ) + 8001d92: f001 fd3f bl 8003814 + 8001d96: 4603 mov r3, r0 + 8001d98: 737b strb r3, [r7, #13] + if (status == HAL_OK) { + 8001d9a: 7b7b ldrb r3, [r7, #13] + 8001d9c: 2b00 cmp r3, #0 + 8001d9e: d109 bne.n 8001db4 + *res = (result[0] << 8) | result[1]; + 8001da0: 7a3b ldrb r3, [r7, #8] + 8001da2: 021b lsls r3, r3, #8 + 8001da4: b21a sxth r2, r3 + 8001da6: 7a7b ldrb r3, [r7, #9] + 8001da8: b21b sxth r3, r3 + 8001daa: 4313 orrs r3, r2 + 8001dac: b21b sxth r3, r3 + 8001dae: b29a uxth r2, r3 + 8001db0: 683b ldr r3, [r7, #0] + 8001db2: 801a strh r2, [r3, #0] + } + return status; + 8001db4: 7b7b ldrb r3, [r7, #13] +} + 8001db6: 4618 mov r0, r3 + 8001db8: 3710 adds r7, #16 + 8001dba: 46bd mov sp, r7 + 8001dbc: bd80 pop {r7, pc} + 8001dbe: bf00 nop + 8001dc0: 2000016c .word 0x2000016c + +08001dc4 : + +uint8_t readeeprom(uint16_t address){ + 8001dc4: b580 push {r7, lr} + 8001dc6: b088 sub sp, #32 + 8001dc8: af04 add r7, sp, #16 + 8001dca: 4603 mov r3, r0 + 8001dcc: 80fb strh r3, [r7, #6] + uint8_t data = 0; + 8001dce: 2300 movs r3, #0 + 8001dd0: 73fb strb r3, [r7, #15] + //uint8_t* address2 = (uint8_t*) &address; + //HAL_I2C_Master_Transmit(&hi2c2, 0xA0, address2, 2, 1000); + //HAL_I2C_Master_Receive(&hi2c2, 0xA0, &data, 1, 1000); + HAL_I2C_Mem_Read(&hi2c2, 0xA0, address, 2, &data, 1 , 1000); + 8001dd2: 88fa ldrh r2, [r7, #6] + 8001dd4: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001dd8: 9302 str r3, [sp, #8] + 8001dda: 2301 movs r3, #1 + 8001ddc: 9301 str r3, [sp, #4] + 8001dde: f107 030f add.w r3, r7, #15 + 8001de2: 9300 str r3, [sp, #0] + 8001de4: 2302 movs r3, #2 + 8001de6: 21a0 movs r1, #160 ; 0xa0 + 8001de8: 4803 ldr r0, [pc, #12] ; (8001df8 ) + 8001dea: f001 ff1d bl 8003c28 + //HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + // uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) + return data; + 8001dee: 7bfb ldrb r3, [r7, #15] +} + 8001df0: 4618 mov r0, r3 + 8001df2: 3710 adds r7, #16 + 8001df4: 46bd mov sp, r7 + 8001df6: bd80 pop {r7, pc} + 8001df8: 200001b8 .word 0x200001b8 + +08001dfc : + +void writeeeprom(uint16_t address, uint8_t data){ + 8001dfc: b580 push {r7, lr} + 8001dfe: b086 sub sp, #24 + 8001e00: af04 add r7, sp, #16 + 8001e02: 4603 mov r3, r0 + 8001e04: 460a mov r2, r1 + 8001e06: 80fb strh r3, [r7, #6] + 8001e08: 4613 mov r3, r2 + 8001e0a: 717b strb r3, [r7, #5] + HAL_I2C_Mem_Write(&hi2c2, 0xA0, address, 2, &data, 1, 1000); + 8001e0c: 88fa ldrh r2, [r7, #6] + 8001e0e: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001e12: 9302 str r3, [sp, #8] + 8001e14: 2301 movs r3, #1 + 8001e16: 9301 str r3, [sp, #4] + 8001e18: 1d7b adds r3, r7, #5 + 8001e1a: 9300 str r3, [sp, #0] + 8001e1c: 2302 movs r3, #2 + 8001e1e: 21a0 movs r1, #160 ; 0xa0 + 8001e20: 4804 ldr r0, [pc, #16] ; (8001e34 ) + 8001e22: f001 fded bl 8003a00 + HAL_Delay(5); + 8001e26: 2005 movs r0, #5 + 8001e28: f000 fa28 bl 800227c +} + 8001e2c: bf00 nop + 8001e2e: 3708 adds r7, #8 + 8001e30: 46bd mov sp, r7 + 8001e32: bd80 pop {r7, pc} + 8001e34: 200001b8 .word 0x200001b8 + +08001e38 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8001e38: b480 push {r7} + 8001e3a: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8001e3c: b672 cpsid i +} + 8001e3e: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8001e40: e7fe b.n 8001e40 + ... + +08001e44 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8001e44: b480 push {r7} + 8001e46: b083 sub sp, #12 + 8001e48: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8001e4a: 4b0f ldr r3, [pc, #60] ; (8001e88 ) + 8001e4c: 699b ldr r3, [r3, #24] + 8001e4e: 4a0e ldr r2, [pc, #56] ; (8001e88 ) + 8001e50: f043 0301 orr.w r3, r3, #1 + 8001e54: 6193 str r3, [r2, #24] + 8001e56: 4b0c ldr r3, [pc, #48] ; (8001e88 ) + 8001e58: 699b ldr r3, [r3, #24] + 8001e5a: f003 0301 and.w r3, r3, #1 + 8001e5e: 607b str r3, [r7, #4] + 8001e60: 687b ldr r3, [r7, #4] + __HAL_RCC_PWR_CLK_ENABLE(); + 8001e62: 4b09 ldr r3, [pc, #36] ; (8001e88 ) + 8001e64: 69db ldr r3, [r3, #28] + 8001e66: 4a08 ldr r2, [pc, #32] ; (8001e88 ) + 8001e68: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8001e6c: 61d3 str r3, [r2, #28] + 8001e6e: 4b06 ldr r3, [pc, #24] ; (8001e88 ) + 8001e70: 69db ldr r3, [r3, #28] + 8001e72: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001e76: 603b str r3, [r7, #0] + 8001e78: 683b ldr r3, [r7, #0] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8001e7a: bf00 nop + 8001e7c: 370c adds r7, #12 + 8001e7e: 46bd mov sp, r7 + 8001e80: f85d 7b04 ldr.w r7, [sp], #4 + 8001e84: 4770 bx lr + 8001e86: bf00 nop + 8001e88: 40021000 .word 0x40021000 + +08001e8c : +* This function configures the hardware resources used in this example +* @param hcan: CAN handle pointer +* @retval None +*/ +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + 8001e8c: b580 push {r7, lr} + 8001e8e: b08a sub sp, #40 ; 0x28 + 8001e90: af00 add r7, sp, #0 + 8001e92: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001e94: f107 0314 add.w r3, r7, #20 + 8001e98: 2200 movs r2, #0 + 8001e9a: 601a str r2, [r3, #0] + 8001e9c: 605a str r2, [r3, #4] + 8001e9e: 609a str r2, [r3, #8] + 8001ea0: 60da str r2, [r3, #12] + 8001ea2: 611a str r2, [r3, #16] + if(hcan->Instance==CAN) + 8001ea4: 687b ldr r3, [r7, #4] + 8001ea6: 681b ldr r3, [r3, #0] + 8001ea8: 4a1c ldr r2, [pc, #112] ; (8001f1c ) + 8001eaa: 4293 cmp r3, r2 + 8001eac: d131 bne.n 8001f12 + { + /* USER CODE BEGIN CAN_MspInit 0 */ + + /* USER CODE END CAN_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CAN1_CLK_ENABLE(); + 8001eae: 4b1c ldr r3, [pc, #112] ; (8001f20 ) + 8001eb0: 69db ldr r3, [r3, #28] + 8001eb2: 4a1b ldr r2, [pc, #108] ; (8001f20 ) + 8001eb4: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 + 8001eb8: 61d3 str r3, [r2, #28] + 8001eba: 4b19 ldr r3, [pc, #100] ; (8001f20 ) + 8001ebc: 69db ldr r3, [r3, #28] + 8001ebe: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8001ec2: 613b str r3, [r7, #16] + 8001ec4: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001ec6: 4b16 ldr r3, [pc, #88] ; (8001f20 ) + 8001ec8: 695b ldr r3, [r3, #20] + 8001eca: 4a15 ldr r2, [pc, #84] ; (8001f20 ) + 8001ecc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001ed0: 6153 str r3, [r2, #20] + 8001ed2: 4b13 ldr r3, [pc, #76] ; (8001f20 ) + 8001ed4: 695b ldr r3, [r3, #20] + 8001ed6: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001eda: 60fb str r3, [r7, #12] + 8001edc: 68fb ldr r3, [r7, #12] + /**CAN GPIO Configuration + PA11 ------> CAN_RX + PA12 ------> CAN_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 8001ede: f44f 53c0 mov.w r3, #6144 ; 0x1800 + 8001ee2: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001ee4: 2302 movs r3, #2 + 8001ee6: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001ee8: 2300 movs r3, #0 + 8001eea: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8001eec: 2303 movs r3, #3 + 8001eee: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF9_CAN; + 8001ef0: 2309 movs r3, #9 + 8001ef2: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8001ef4: f107 0314 add.w r3, r7, #20 + 8001ef8: 4619 mov r1, r3 + 8001efa: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001efe: f001 f973 bl 80031e8 + + /* CAN interrupt Init */ + HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); + 8001f02: 2200 movs r2, #0 + 8001f04: 2100 movs r1, #0 + 8001f06: 2014 movs r0, #20 + 8001f08: f001 f937 bl 800317a + HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); + 8001f0c: 2014 movs r0, #20 + 8001f0e: f001 f950 bl 80031b2 + /* USER CODE BEGIN CAN_MspInit 1 */ + + /* USER CODE END CAN_MspInit 1 */ + } + +} + 8001f12: bf00 nop + 8001f14: 3728 adds r7, #40 ; 0x28 + 8001f16: 46bd mov sp, r7 + 8001f18: bd80 pop {r7, pc} + 8001f1a: bf00 nop + 8001f1c: 40006400 .word 0x40006400 + 8001f20: 40021000 .word 0x40021000 + +08001f24 : +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + 8001f24: b580 push {r7, lr} + 8001f26: b08c sub sp, #48 ; 0x30 + 8001f28: af00 add r7, sp, #0 + 8001f2a: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8001f2c: f107 031c add.w r3, r7, #28 + 8001f30: 2200 movs r2, #0 + 8001f32: 601a str r2, [r3, #0] + 8001f34: 605a str r2, [r3, #4] + 8001f36: 609a str r2, [r3, #8] + 8001f38: 60da str r2, [r3, #12] + 8001f3a: 611a str r2, [r3, #16] + if(hi2c->Instance==I2C1) + 8001f3c: 687b ldr r3, [r7, #4] + 8001f3e: 681b ldr r3, [r3, #0] + 8001f40: 4a3e ldr r2, [pc, #248] ; (800203c ) + 8001f42: 4293 cmp r3, r2 + 8001f44: d146 bne.n 8001fd4 + { + /* USER CODE BEGIN I2C1_MspInit 0 */ + + /* USER CODE END I2C1_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001f46: 4b3e ldr r3, [pc, #248] ; (8002040 ) + 8001f48: 695b ldr r3, [r3, #20] + 8001f4a: 4a3d ldr r2, [pc, #244] ; (8002040 ) + 8001f4c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001f50: 6153 str r3, [r2, #20] + 8001f52: 4b3b ldr r3, [pc, #236] ; (8002040 ) + 8001f54: 695b ldr r3, [r3, #20] + 8001f56: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001f5a: 61bb str r3, [r7, #24] + 8001f5c: 69bb ldr r3, [r7, #24] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8001f5e: 4b38 ldr r3, [pc, #224] ; (8002040 ) + 8001f60: 695b ldr r3, [r3, #20] + 8001f62: 4a37 ldr r2, [pc, #220] ; (8002040 ) + 8001f64: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8001f68: 6153 str r3, [r2, #20] + 8001f6a: 4b35 ldr r3, [pc, #212] ; (8002040 ) + 8001f6c: 695b ldr r3, [r3, #20] + 8001f6e: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8001f72: 617b str r3, [r7, #20] + 8001f74: 697b ldr r3, [r7, #20] + /**I2C1 GPIO Configuration + PA15 ------> I2C1_SCL + PB7 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = TMP_SCL_Pin; + 8001f76: f44f 4300 mov.w r3, #32768 ; 0x8000 + 8001f7a: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8001f7c: 2312 movs r3, #18 + 8001f7e: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001f80: 2300 movs r3, #0 + 8001f82: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8001f84: 2303 movs r3, #3 + 8001f86: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8001f88: 2304 movs r3, #4 + 8001f8a: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(TMP_SCL_GPIO_Port, &GPIO_InitStruct); + 8001f8c: f107 031c add.w r3, r7, #28 + 8001f90: 4619 mov r1, r3 + 8001f92: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001f96: f001 f927 bl 80031e8 + + GPIO_InitStruct.Pin = TMP_SDA_Pin; + 8001f9a: 2380 movs r3, #128 ; 0x80 + 8001f9c: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8001f9e: 2312 movs r3, #18 + 8001fa0: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001fa2: 2300 movs r3, #0 + 8001fa4: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8001fa6: 2303 movs r3, #3 + 8001fa8: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 8001faa: 2304 movs r3, #4 + 8001fac: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(TMP_SDA_GPIO_Port, &GPIO_InitStruct); + 8001fae: f107 031c add.w r3, r7, #28 + 8001fb2: 4619 mov r1, r3 + 8001fb4: 4823 ldr r0, [pc, #140] ; (8002044 ) + 8001fb6: f001 f917 bl 80031e8 + + /* Peripheral clock enable */ + __HAL_RCC_I2C1_CLK_ENABLE(); + 8001fba: 4b21 ldr r3, [pc, #132] ; (8002040 ) + 8001fbc: 69db ldr r3, [r3, #28] + 8001fbe: 4a20 ldr r2, [pc, #128] ; (8002040 ) + 8001fc0: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 8001fc4: 61d3 str r3, [r2, #28] + 8001fc6: 4b1e ldr r3, [pc, #120] ; (8002040 ) + 8001fc8: 69db ldr r3, [r3, #28] + 8001fca: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8001fce: 613b str r3, [r7, #16] + 8001fd0: 693b ldr r3, [r7, #16] + /* USER CODE BEGIN I2C2_MspInit 1 */ + + /* USER CODE END I2C2_MspInit 1 */ + } + +} + 8001fd2: e02e b.n 8002032 + else if(hi2c->Instance==I2C2) + 8001fd4: 687b ldr r3, [r7, #4] + 8001fd6: 681b ldr r3, [r3, #0] + 8001fd8: 4a1b ldr r2, [pc, #108] ; (8002048 ) + 8001fda: 4293 cmp r3, r2 + 8001fdc: d129 bne.n 8002032 + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001fde: 4b18 ldr r3, [pc, #96] ; (8002040 ) + 8001fe0: 695b ldr r3, [r3, #20] + 8001fe2: 4a17 ldr r2, [pc, #92] ; (8002040 ) + 8001fe4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001fe8: 6153 str r3, [r2, #20] + 8001fea: 4b15 ldr r3, [pc, #84] ; (8002040 ) + 8001fec: 695b ldr r3, [r3, #20] + 8001fee: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001ff2: 60fb str r3, [r7, #12] + 8001ff4: 68fb ldr r3, [r7, #12] + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + 8001ff6: f44f 63c0 mov.w r3, #1536 ; 0x600 + 8001ffa: 61fb str r3, [r7, #28] + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 8001ffc: 2312 movs r3, #18 + 8001ffe: 623b str r3, [r7, #32] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8002000: 2300 movs r3, #0 + 8002002: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 8002004: 2303 movs r3, #3 + 8002006: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + 8002008: 2304 movs r3, #4 + 800200a: 62fb str r3, [r7, #44] ; 0x2c + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800200c: f107 031c add.w r3, r7, #28 + 8002010: 4619 mov r1, r3 + 8002012: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8002016: f001 f8e7 bl 80031e8 + __HAL_RCC_I2C2_CLK_ENABLE(); + 800201a: 4b09 ldr r3, [pc, #36] ; (8002040 ) + 800201c: 69db ldr r3, [r3, #28] + 800201e: 4a08 ldr r2, [pc, #32] ; (8002040 ) + 8002020: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 + 8002024: 61d3 str r3, [r2, #28] + 8002026: 4b06 ldr r3, [pc, #24] ; (8002040 ) + 8002028: 69db ldr r3, [r3, #28] + 800202a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800202e: 60bb str r3, [r7, #8] + 8002030: 68bb ldr r3, [r7, #8] +} + 8002032: bf00 nop + 8002034: 3730 adds r7, #48 ; 0x30 + 8002036: 46bd mov sp, r7 + 8002038: bd80 pop {r7, pc} + 800203a: bf00 nop + 800203c: 40005400 .word 0x40005400 + 8002040: 40021000 .word 0x40021000 + 8002044: 48000400 .word 0x48000400 + 8002048: 40005800 .word 0x40005800 + +0800204c : +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + 800204c: b580 push {r7, lr} + 800204e: b08a sub sp, #40 ; 0x28 + 8002050: af00 add r7, sp, #0 + 8002052: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8002054: f107 0314 add.w r3, r7, #20 + 8002058: 2200 movs r2, #0 + 800205a: 601a str r2, [r3, #0] + 800205c: 605a str r2, [r3, #4] + 800205e: 609a str r2, [r3, #8] + 8002060: 60da str r2, [r3, #12] + 8002062: 611a str r2, [r3, #16] + if(hspi->Instance==SPI1) + 8002064: 687b ldr r3, [r7, #4] + 8002066: 681b ldr r3, [r3, #0] + 8002068: 4a17 ldr r2, [pc, #92] ; (80020c8 ) + 800206a: 4293 cmp r3, r2 + 800206c: d128 bne.n 80020c0 + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + 800206e: 4b17 ldr r3, [pc, #92] ; (80020cc ) + 8002070: 699b ldr r3, [r3, #24] + 8002072: 4a16 ldr r2, [pc, #88] ; (80020cc ) + 8002074: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 8002078: 6193 str r3, [r2, #24] + 800207a: 4b14 ldr r3, [pc, #80] ; (80020cc ) + 800207c: 699b ldr r3, [r3, #24] + 800207e: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8002082: 613b str r3, [r7, #16] + 8002084: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8002086: 4b11 ldr r3, [pc, #68] ; (80020cc ) + 8002088: 695b ldr r3, [r3, #20] + 800208a: 4a10 ldr r2, [pc, #64] ; (80020cc ) + 800208c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8002090: 6153 str r3, [r2, #20] + 8002092: 4b0e ldr r3, [pc, #56] ; (80020cc ) + 8002094: 695b ldr r3, [r3, #20] + 8002096: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800209a: 60fb str r3, [r7, #12] + 800209c: 68fb ldr r3, [r7, #12] + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 800209e: 23e0 movs r3, #224 ; 0xe0 + 80020a0: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80020a2: 2302 movs r3, #2 + 80020a4: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80020a6: 2300 movs r3, #0 + 80020a8: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 80020aa: 2303 movs r3, #3 + 80020ac: 623b str r3, [r7, #32] + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 80020ae: 2305 movs r3, #5 + 80020b0: 627b str r3, [r7, #36] ; 0x24 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80020b2: f107 0314 add.w r3, r7, #20 + 80020b6: 4619 mov r1, r3 + 80020b8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 80020bc: f001 f894 bl 80031e8 + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + 80020c0: bf00 nop + 80020c2: 3728 adds r7, #40 ; 0x28 + 80020c4: 46bd mov sp, r7 + 80020c6: bd80 pop {r7, pc} + 80020c8: 40013000 .word 0x40013000 + 80020cc: 40021000 .word 0x40021000 + +080020d0 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 80020d0: b480 push {r7} + 80020d2: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 80020d4: e7fe b.n 80020d4 + +080020d6 : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 80020d6: b480 push {r7} + 80020d8: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 80020da: e7fe b.n 80020da + +080020dc : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 80020dc: b480 push {r7} + 80020de: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 80020e0: e7fe b.n 80020e0 + +080020e2 : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 80020e2: b480 push {r7} + 80020e4: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 80020e6: e7fe b.n 80020e6 + +080020e8 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 80020e8: b480 push {r7} + 80020ea: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 80020ec: e7fe b.n 80020ec + +080020ee : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 80020ee: b480 push {r7} + 80020f0: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 80020f2: bf00 nop + 80020f4: 46bd mov sp, r7 + 80020f6: f85d 7b04 ldr.w r7, [sp], #4 + 80020fa: 4770 bx lr + +080020fc : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 80020fc: b480 push {r7} + 80020fe: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8002100: bf00 nop + 8002102: 46bd mov sp, r7 + 8002104: f85d 7b04 ldr.w r7, [sp], #4 + 8002108: 4770 bx lr + +0800210a : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 800210a: b480 push {r7} + 800210c: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 800210e: bf00 nop + 8002110: 46bd mov sp, r7 + 8002112: f85d 7b04 ldr.w r7, [sp], #4 + 8002116: 4770 bx lr + +08002118 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8002118: b580 push {r7, lr} + 800211a: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 800211c: f000 f88e bl 800223c + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8002120: bf00 nop + 8002122: bd80 pop {r7, pc} + +08002124 : + +/** + * @brief This function handles USB low priority or CAN_RX0 interrupts. + */ +void USB_LP_CAN_RX0_IRQHandler(void) +{ + 8002124: b580 push {r7, lr} + 8002126: af00 add r7, sp, #0 + /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ + + /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan); + 8002128: 4802 ldr r0, [pc, #8] ; (8002134 ) + 800212a: f000 fd1c bl 8002b66 + /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ + + /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ +} + 800212e: bf00 nop + 8002130: bd80 pop {r7, pc} + 8002132: bf00 nop + 8002134: 20000144 .word 0x20000144 + +08002138 : + * @brief Setup the microcontroller system + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8002138: b480 push {r7} + 800213a: af00 add r7, sp, #0 +/* FPU settings --------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 800213c: 4b06 ldr r3, [pc, #24] ; (8002158 ) + 800213e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8002142: 4a05 ldr r2, [pc, #20] ; (8002158 ) + 8002144: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8002148: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 800214c: bf00 nop + 800214e: 46bd mov sp, r7 + 8002150: f85d 7b04 ldr.w r7, [sp], #4 + 8002154: 4770 bx lr + 8002156: bf00 nop + 8002158: e000ed00 .word 0xe000ed00 + +0800215c : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + 800215c: f8df d034 ldr.w sp, [pc, #52] ; 8002194 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8002160: 480d ldr r0, [pc, #52] ; (8002198 ) + ldr r1, =_edata + 8002162: 490e ldr r1, [pc, #56] ; (800219c ) + ldr r2, =_sidata + 8002164: 4a0e ldr r2, [pc, #56] ; (80021a0 ) + movs r3, #0 + 8002166: 2300 movs r3, #0 + b LoopCopyDataInit + 8002168: e002 b.n 8002170 + +0800216a : + +CopyDataInit: + ldr r4, [r2, r3] + 800216a: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 800216c: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 800216e: 3304 adds r3, #4 + +08002170 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8002170: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8002172: 428c cmp r4, r1 + bcc CopyDataInit + 8002174: d3f9 bcc.n 800216a + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8002176: 4a0b ldr r2, [pc, #44] ; (80021a4 ) + ldr r4, =_ebss + 8002178: 4c0b ldr r4, [pc, #44] ; (80021a8 ) + movs r3, #0 + 800217a: 2300 movs r3, #0 + b LoopFillZerobss + 800217c: e001 b.n 8002182 + +0800217e : + +FillZerobss: + str r3, [r2] + 800217e: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8002180: 3204 adds r2, #4 + +08002182 : + +LoopFillZerobss: + cmp r2, r4 + 8002182: 42a2 cmp r2, r4 + bcc FillZerobss + 8002184: d3fb bcc.n 800217e + +/* Call the clock system intitialization function.*/ + bl SystemInit + 8002186: f7ff ffd7 bl 8002138 +/* Call static constructors */ + bl __libc_init_array + 800218a: f004 f971 bl 8006470 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 800218e: f7ff fbc3 bl 8001918
+ +08002192 : + +LoopForever: + b LoopForever + 8002192: e7fe b.n 8002192 + ldr sp, =_estack /* Atollic update: set stack pointer */ + 8002194: 2000a000 .word 0x2000a000 + ldr r0, =_sdata + 8002198: 20000000 .word 0x20000000 + ldr r1, =_edata + 800219c: 20000014 .word 0x20000014 + ldr r2, =_sidata + 80021a0: 08006518 .word 0x08006518 + ldr r2, =_sbss + 80021a4: 20000018 .word 0x20000018 + ldr r4, =_ebss + 80021a8: 20000270 .word 0x20000270 + +080021ac : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80021ac: e7fe b.n 80021ac + ... + +080021b0 : + * In the default implementation,Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 80021b0: b580 push {r7, lr} + 80021b2: af00 add r7, sp, #0 + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 80021b4: 4b08 ldr r3, [pc, #32] ; (80021d8 ) + 80021b6: 681b ldr r3, [r3, #0] + 80021b8: 4a07 ldr r2, [pc, #28] ; (80021d8 ) + 80021ba: f043 0310 orr.w r3, r3, #16 + 80021be: 6013 str r3, [r2, #0] +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 80021c0: 2003 movs r0, #3 + 80021c2: f000 ffcf bl 8003164 + + /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 80021c6: 200f movs r0, #15 + 80021c8: f000 f808 bl 80021dc + + /* Init the low level hardware */ + HAL_MspInit(); + 80021cc: f7ff fe3a bl 8001e44 + + /* Return function status */ + return HAL_OK; + 80021d0: 2300 movs r3, #0 +} + 80021d2: 4618 mov r0, r3 + 80021d4: bd80 pop {r7, pc} + 80021d6: bf00 nop + 80021d8: 40022000 .word 0x40022000 + +080021dc : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 80021dc: b580 push {r7, lr} + 80021de: b082 sub sp, #8 + 80021e0: af00 add r7, sp, #0 + 80021e2: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 80021e4: 4b12 ldr r3, [pc, #72] ; (8002230 ) + 80021e6: 681a ldr r2, [r3, #0] + 80021e8: 4b12 ldr r3, [pc, #72] ; (8002234 ) + 80021ea: 781b ldrb r3, [r3, #0] + 80021ec: 4619 mov r1, r3 + 80021ee: f44f 737a mov.w r3, #1000 ; 0x3e8 + 80021f2: fbb3 f3f1 udiv r3, r3, r1 + 80021f6: fbb2 f3f3 udiv r3, r2, r3 + 80021fa: 4618 mov r0, r3 + 80021fc: f000 ffe7 bl 80031ce + 8002200: 4603 mov r3, r0 + 8002202: 2b00 cmp r3, #0 + 8002204: d001 beq.n 800220a + { + return HAL_ERROR; + 8002206: 2301 movs r3, #1 + 8002208: e00e b.n 8002228 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 800220a: 687b ldr r3, [r7, #4] + 800220c: 2b0f cmp r3, #15 + 800220e: d80a bhi.n 8002226 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8002210: 2200 movs r2, #0 + 8002212: 6879 ldr r1, [r7, #4] + 8002214: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8002218: f000 ffaf bl 800317a + uwTickPrio = TickPriority; + 800221c: 4a06 ldr r2, [pc, #24] ; (8002238 ) + 800221e: 687b ldr r3, [r7, #4] + 8002220: 6013 str r3, [r2, #0] + else + { + return HAL_ERROR; + } + /* Return function status */ + return HAL_OK; + 8002222: 2300 movs r3, #0 + 8002224: e000 b.n 8002228 + return HAL_ERROR; + 8002226: 2301 movs r3, #1 +} + 8002228: 4618 mov r0, r3 + 800222a: 3708 adds r7, #8 + 800222c: 46bd mov sp, r7 + 800222e: bd80 pop {r7, pc} + 8002230: 20000008 .word 0x20000008 + 8002234: 20000010 .word 0x20000010 + 8002238: 2000000c .word 0x2000000c + +0800223c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 800223c: b480 push {r7} + 800223e: af00 add r7, sp, #0 + uwTick += uwTickFreq; + 8002240: 4b06 ldr r3, [pc, #24] ; (800225c ) + 8002242: 781b ldrb r3, [r3, #0] + 8002244: 461a mov r2, r3 + 8002246: 4b06 ldr r3, [pc, #24] ; (8002260 ) + 8002248: 681b ldr r3, [r3, #0] + 800224a: 4413 add r3, r2 + 800224c: 4a04 ldr r2, [pc, #16] ; (8002260 ) + 800224e: 6013 str r3, [r2, #0] +} + 8002250: bf00 nop + 8002252: 46bd mov sp, r7 + 8002254: f85d 7b04 ldr.w r7, [sp], #4 + 8002258: 4770 bx lr + 800225a: bf00 nop + 800225c: 20000010 .word 0x20000010 + 8002260: 2000026c .word 0x2000026c + +08002264 : + * @note The function is declared as __Weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 8002264: b480 push {r7} + 8002266: af00 add r7, sp, #0 + return uwTick; + 8002268: 4b03 ldr r3, [pc, #12] ; (8002278 ) + 800226a: 681b ldr r3, [r3, #0] +} + 800226c: 4618 mov r0, r3 + 800226e: 46bd mov sp, r7 + 8002270: f85d 7b04 ldr.w r7, [sp], #4 + 8002274: 4770 bx lr + 8002276: bf00 nop + 8002278: 2000026c .word 0x2000026c + +0800227c : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 800227c: b580 push {r7, lr} + 800227e: b084 sub sp, #16 + 8002280: af00 add r7, sp, #0 + 8002282: 6078 str r0, [r7, #4] + uint32_t tickstart = HAL_GetTick(); + 8002284: f7ff ffee bl 8002264 + 8002288: 60b8 str r0, [r7, #8] + uint32_t wait = Delay; + 800228a: 687b ldr r3, [r7, #4] + 800228c: 60fb str r3, [r7, #12] + + /* Add freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 800228e: 68fb ldr r3, [r7, #12] + 8002290: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8002294: d005 beq.n 80022a2 + { + wait += (uint32_t)(uwTickFreq); + 8002296: 4b0a ldr r3, [pc, #40] ; (80022c0 ) + 8002298: 781b ldrb r3, [r3, #0] + 800229a: 461a mov r2, r3 + 800229c: 68fb ldr r3, [r7, #12] + 800229e: 4413 add r3, r2 + 80022a0: 60fb str r3, [r7, #12] + } + + while((HAL_GetTick() - tickstart) < wait) + 80022a2: bf00 nop + 80022a4: f7ff ffde bl 8002264 + 80022a8: 4602 mov r2, r0 + 80022aa: 68bb ldr r3, [r7, #8] + 80022ac: 1ad3 subs r3, r2, r3 + 80022ae: 68fa ldr r2, [r7, #12] + 80022b0: 429a cmp r2, r3 + 80022b2: d8f7 bhi.n 80022a4 + { + } +} + 80022b4: bf00 nop + 80022b6: bf00 nop + 80022b8: 3710 adds r7, #16 + 80022ba: 46bd mov sp, r7 + 80022bc: bd80 pop {r7, pc} + 80022be: bf00 nop + 80022c0: 20000010 .word 0x20000010 + +080022c4 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + 80022c4: b580 push {r7, lr} + 80022c6: b084 sub sp, #16 + 80022c8: af00 add r7, sp, #0 + 80022ca: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + 80022cc: 687b ldr r3, [r7, #4] + 80022ce: 2b00 cmp r3, #0 + 80022d0: d101 bne.n 80022d6 + { + return HAL_ERROR; + 80022d2: 2301 movs r3, #1 + 80022d4: e0ed b.n 80024b2 + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else + if (hcan->State == HAL_CAN_STATE_RESET) + 80022d6: 687b ldr r3, [r7, #4] + 80022d8: f893 3020 ldrb.w r3, [r3, #32] + 80022dc: b2db uxtb r3, r3 + 80022de: 2b00 cmp r3, #0 + 80022e0: d102 bne.n 80022e8 + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + 80022e2: 6878 ldr r0, [r7, #4] + 80022e4: f7ff fdd2 bl 8001e8c + } +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 80022e8: 687b ldr r3, [r7, #4] + 80022ea: 681b ldr r3, [r3, #0] + 80022ec: 681a ldr r2, [r3, #0] + 80022ee: 687b ldr r3, [r7, #4] + 80022f0: 681b ldr r3, [r3, #0] + 80022f2: f042 0201 orr.w r2, r2, #1 + 80022f6: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80022f8: f7ff ffb4 bl 8002264 + 80022fc: 60f8 str r0, [r7, #12] + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 80022fe: e012 b.n 8002326 + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 8002300: f7ff ffb0 bl 8002264 + 8002304: 4602 mov r2, r0 + 8002306: 68fb ldr r3, [r7, #12] + 8002308: 1ad3 subs r3, r2, r3 + 800230a: 2b0a cmp r3, #10 + 800230c: d90b bls.n 8002326 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 800230e: 687b ldr r3, [r7, #4] + 8002310: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002312: f443 3200 orr.w r2, r3, #131072 ; 0x20000 + 8002316: 687b ldr r3, [r7, #4] + 8002318: 625a str r2, [r3, #36] ; 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 800231a: 687b ldr r3, [r7, #4] + 800231c: 2205 movs r2, #5 + 800231e: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 8002322: 2301 movs r3, #1 + 8002324: e0c5 b.n 80024b2 + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 8002326: 687b ldr r3, [r7, #4] + 8002328: 681b ldr r3, [r3, #0] + 800232a: 685b ldr r3, [r3, #4] + 800232c: f003 0301 and.w r3, r3, #1 + 8002330: 2b00 cmp r3, #0 + 8002332: d0e5 beq.n 8002300 + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 8002334: 687b ldr r3, [r7, #4] + 8002336: 681b ldr r3, [r3, #0] + 8002338: 681a ldr r2, [r3, #0] + 800233a: 687b ldr r3, [r7, #4] + 800233c: 681b ldr r3, [r3, #0] + 800233e: f022 0202 bic.w r2, r2, #2 + 8002342: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8002344: f7ff ff8e bl 8002264 + 8002348: 60f8 str r0, [r7, #12] + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 800234a: e012 b.n 8002372 + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 800234c: f7ff ff8a bl 8002264 + 8002350: 4602 mov r2, r0 + 8002352: 68fb ldr r3, [r7, #12] + 8002354: 1ad3 subs r3, r2, r3 + 8002356: 2b0a cmp r3, #10 + 8002358: d90b bls.n 8002372 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 800235a: 687b ldr r3, [r7, #4] + 800235c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800235e: f443 3200 orr.w r2, r3, #131072 ; 0x20000 + 8002362: 687b ldr r3, [r7, #4] + 8002364: 625a str r2, [r3, #36] ; 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 8002366: 687b ldr r3, [r7, #4] + 8002368: 2205 movs r2, #5 + 800236a: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 800236e: 2301 movs r3, #1 + 8002370: e09f b.n 80024b2 + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 8002372: 687b ldr r3, [r7, #4] + 8002374: 681b ldr r3, [r3, #0] + 8002376: 685b ldr r3, [r3, #4] + 8002378: f003 0302 and.w r3, r3, #2 + 800237c: 2b00 cmp r3, #0 + 800237e: d1e5 bne.n 800234c + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + 8002380: 687b ldr r3, [r7, #4] + 8002382: 7e1b ldrb r3, [r3, #24] + 8002384: 2b01 cmp r3, #1 + 8002386: d108 bne.n 800239a + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 8002388: 687b ldr r3, [r7, #4] + 800238a: 681b ldr r3, [r3, #0] + 800238c: 681a ldr r2, [r3, #0] + 800238e: 687b ldr r3, [r7, #4] + 8002390: 681b ldr r3, [r3, #0] + 8002392: f042 0280 orr.w r2, r2, #128 ; 0x80 + 8002396: 601a str r2, [r3, #0] + 8002398: e007 b.n 80023aa + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 800239a: 687b ldr r3, [r7, #4] + 800239c: 681b ldr r3, [r3, #0] + 800239e: 681a ldr r2, [r3, #0] + 80023a0: 687b ldr r3, [r7, #4] + 80023a2: 681b ldr r3, [r3, #0] + 80023a4: f022 0280 bic.w r2, r2, #128 ; 0x80 + 80023a8: 601a str r2, [r3, #0] + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + 80023aa: 687b ldr r3, [r7, #4] + 80023ac: 7e5b ldrb r3, [r3, #25] + 80023ae: 2b01 cmp r3, #1 + 80023b0: d108 bne.n 80023c4 + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 80023b2: 687b ldr r3, [r7, #4] + 80023b4: 681b ldr r3, [r3, #0] + 80023b6: 681a ldr r2, [r3, #0] + 80023b8: 687b ldr r3, [r7, #4] + 80023ba: 681b ldr r3, [r3, #0] + 80023bc: f042 0240 orr.w r2, r2, #64 ; 0x40 + 80023c0: 601a str r2, [r3, #0] + 80023c2: e007 b.n 80023d4 + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 80023c4: 687b ldr r3, [r7, #4] + 80023c6: 681b ldr r3, [r3, #0] + 80023c8: 681a ldr r2, [r3, #0] + 80023ca: 687b ldr r3, [r7, #4] + 80023cc: 681b ldr r3, [r3, #0] + 80023ce: f022 0240 bic.w r2, r2, #64 ; 0x40 + 80023d2: 601a str r2, [r3, #0] + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + 80023d4: 687b ldr r3, [r7, #4] + 80023d6: 7e9b ldrb r3, [r3, #26] + 80023d8: 2b01 cmp r3, #1 + 80023da: d108 bne.n 80023ee + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 80023dc: 687b ldr r3, [r7, #4] + 80023de: 681b ldr r3, [r3, #0] + 80023e0: 681a ldr r2, [r3, #0] + 80023e2: 687b ldr r3, [r7, #4] + 80023e4: 681b ldr r3, [r3, #0] + 80023e6: f042 0220 orr.w r2, r2, #32 + 80023ea: 601a str r2, [r3, #0] + 80023ec: e007 b.n 80023fe + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 80023ee: 687b ldr r3, [r7, #4] + 80023f0: 681b ldr r3, [r3, #0] + 80023f2: 681a ldr r2, [r3, #0] + 80023f4: 687b ldr r3, [r7, #4] + 80023f6: 681b ldr r3, [r3, #0] + 80023f8: f022 0220 bic.w r2, r2, #32 + 80023fc: 601a str r2, [r3, #0] + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + 80023fe: 687b ldr r3, [r7, #4] + 8002400: 7edb ldrb r3, [r3, #27] + 8002402: 2b01 cmp r3, #1 + 8002404: d108 bne.n 8002418 + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 8002406: 687b ldr r3, [r7, #4] + 8002408: 681b ldr r3, [r3, #0] + 800240a: 681a ldr r2, [r3, #0] + 800240c: 687b ldr r3, [r7, #4] + 800240e: 681b ldr r3, [r3, #0] + 8002410: f022 0210 bic.w r2, r2, #16 + 8002414: 601a str r2, [r3, #0] + 8002416: e007 b.n 8002428 + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 8002418: 687b ldr r3, [r7, #4] + 800241a: 681b ldr r3, [r3, #0] + 800241c: 681a ldr r2, [r3, #0] + 800241e: 687b ldr r3, [r7, #4] + 8002420: 681b ldr r3, [r3, #0] + 8002422: f042 0210 orr.w r2, r2, #16 + 8002426: 601a str r2, [r3, #0] + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + 8002428: 687b ldr r3, [r7, #4] + 800242a: 7f1b ldrb r3, [r3, #28] + 800242c: 2b01 cmp r3, #1 + 800242e: d108 bne.n 8002442 + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 8002430: 687b ldr r3, [r7, #4] + 8002432: 681b ldr r3, [r3, #0] + 8002434: 681a ldr r2, [r3, #0] + 8002436: 687b ldr r3, [r7, #4] + 8002438: 681b ldr r3, [r3, #0] + 800243a: f042 0208 orr.w r2, r2, #8 + 800243e: 601a str r2, [r3, #0] + 8002440: e007 b.n 8002452 + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 8002442: 687b ldr r3, [r7, #4] + 8002444: 681b ldr r3, [r3, #0] + 8002446: 681a ldr r2, [r3, #0] + 8002448: 687b ldr r3, [r7, #4] + 800244a: 681b ldr r3, [r3, #0] + 800244c: f022 0208 bic.w r2, r2, #8 + 8002450: 601a str r2, [r3, #0] + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + 8002452: 687b ldr r3, [r7, #4] + 8002454: 7f5b ldrb r3, [r3, #29] + 8002456: 2b01 cmp r3, #1 + 8002458: d108 bne.n 800246c + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 800245a: 687b ldr r3, [r7, #4] + 800245c: 681b ldr r3, [r3, #0] + 800245e: 681a ldr r2, [r3, #0] + 8002460: 687b ldr r3, [r7, #4] + 8002462: 681b ldr r3, [r3, #0] + 8002464: f042 0204 orr.w r2, r2, #4 + 8002468: 601a str r2, [r3, #0] + 800246a: e007 b.n 800247c + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 800246c: 687b ldr r3, [r7, #4] + 800246e: 681b ldr r3, [r3, #0] + 8002470: 681a ldr r2, [r3, #0] + 8002472: 687b ldr r3, [r7, #4] + 8002474: 681b ldr r3, [r3, #0] + 8002476: f022 0204 bic.w r2, r2, #4 + 800247a: 601a str r2, [r3, #0] + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + 800247c: 687b ldr r3, [r7, #4] + 800247e: 689a ldr r2, [r3, #8] + 8002480: 687b ldr r3, [r7, #4] + 8002482: 68db ldr r3, [r3, #12] + 8002484: 431a orrs r2, r3 + 8002486: 687b ldr r3, [r7, #4] + 8002488: 691b ldr r3, [r3, #16] + 800248a: 431a orrs r2, r3 + 800248c: 687b ldr r3, [r7, #4] + 800248e: 695b ldr r3, [r3, #20] + 8002490: ea42 0103 orr.w r1, r2, r3 + 8002494: 687b ldr r3, [r7, #4] + 8002496: 685b ldr r3, [r3, #4] + 8002498: 1e5a subs r2, r3, #1 + 800249a: 687b ldr r3, [r7, #4] + 800249c: 681b ldr r3, [r3, #0] + 800249e: 430a orrs r2, r1 + 80024a0: 61da str r2, [r3, #28] + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 80024a2: 687b ldr r3, [r7, #4] + 80024a4: 2200 movs r2, #0 + 80024a6: 625a str r2, [r3, #36] ; 0x24 + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + 80024a8: 687b ldr r3, [r7, #4] + 80024aa: 2201 movs r2, #1 + 80024ac: f883 2020 strb.w r2, [r3, #32] + + /* Return function status */ + return HAL_OK; + 80024b0: 2300 movs r3, #0 +} + 80024b2: 4618 mov r0, r3 + 80024b4: 3710 adds r7, #16 + 80024b6: 46bd mov sp, r7 + 80024b8: bd80 pop {r7, pc} + +080024ba : + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +{ + 80024ba: b480 push {r7} + 80024bc: b087 sub sp, #28 + 80024be: af00 add r7, sp, #0 + 80024c0: 6078 str r0, [r7, #4] + 80024c2: 6039 str r1, [r7, #0] + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip = hcan->Instance; + 80024c4: 687b ldr r3, [r7, #4] + 80024c6: 681b ldr r3, [r3, #0] + 80024c8: 617b str r3, [r7, #20] + HAL_CAN_StateTypeDef state = hcan->State; + 80024ca: 687b ldr r3, [r7, #4] + 80024cc: f893 3020 ldrb.w r3, [r3, #32] + 80024d0: 74fb strb r3, [r7, #19] + + if ((state == HAL_CAN_STATE_READY) || + 80024d2: 7cfb ldrb r3, [r7, #19] + 80024d4: 2b01 cmp r3, #1 + 80024d6: d003 beq.n 80024e0 + 80024d8: 7cfb ldrb r3, [r7, #19] + 80024da: 2b02 cmp r3, #2 + 80024dc: f040 80aa bne.w 8002634 + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + 80024e0: 697b ldr r3, [r7, #20] + 80024e2: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 80024e6: f043 0201 orr.w r2, r3, #1 + 80024ea: 697b ldr r3, [r7, #20] + 80024ec: f8c3 2200 str.w r2, [r3, #512] ; 0x200 + + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + 80024f0: 683b ldr r3, [r7, #0] + 80024f2: 695b ldr r3, [r3, #20] + 80024f4: f003 031f and.w r3, r3, #31 + 80024f8: 2201 movs r2, #1 + 80024fa: fa02 f303 lsl.w r3, r2, r3 + 80024fe: 60fb str r3, [r7, #12] + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + 8002500: 697b ldr r3, [r7, #20] + 8002502: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c + 8002506: 68fb ldr r3, [r7, #12] + 8002508: 43db mvns r3, r3 + 800250a: 401a ands r2, r3 + 800250c: 697b ldr r3, [r7, #20] + 800250e: f8c3 221c str.w r2, [r3, #540] ; 0x21c + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + 8002512: 683b ldr r3, [r7, #0] + 8002514: 69db ldr r3, [r3, #28] + 8002516: 2b00 cmp r3, #0 + 8002518: d123 bne.n 8002562 + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + 800251a: 697b ldr r3, [r7, #20] + 800251c: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c + 8002520: 68fb ldr r3, [r7, #12] + 8002522: 43db mvns r3, r3 + 8002524: 401a ands r2, r3 + 8002526: 697b ldr r3, [r7, #20] + 8002528: f8c3 220c str.w r2, [r3, #524] ; 0x20c + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 800252c: 683b ldr r3, [r7, #0] + 800252e: 68db ldr r3, [r3, #12] + 8002530: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 8002532: 683b ldr r3, [r7, #0] + 8002534: 685b ldr r3, [r3, #4] + 8002536: b29b uxth r3, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 8002538: 683a ldr r2, [r7, #0] + 800253a: 6952 ldr r2, [r2, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 800253c: 4319 orrs r1, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 800253e: 697b ldr r3, [r7, #20] + 8002540: 3248 adds r2, #72 ; 0x48 + 8002542: f843 1032 str.w r1, [r3, r2, lsl #3] + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 8002546: 683b ldr r3, [r7, #0] + 8002548: 689b ldr r3, [r3, #8] + 800254a: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + 800254c: 683b ldr r3, [r7, #0] + 800254e: 681b ldr r3, [r3, #0] + 8002550: b29a uxth r2, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 8002552: 683b ldr r3, [r7, #0] + 8002554: 695b ldr r3, [r3, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 8002556: 430a orrs r2, r1 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 8002558: 6979 ldr r1, [r7, #20] + 800255a: 3348 adds r3, #72 ; 0x48 + 800255c: 00db lsls r3, r3, #3 + 800255e: 440b add r3, r1 + 8002560: 605a str r2, [r3, #4] + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + 8002562: 683b ldr r3, [r7, #0] + 8002564: 69db ldr r3, [r3, #28] + 8002566: 2b01 cmp r3, #1 + 8002568: d122 bne.n 80025b0 + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + 800256a: 697b ldr r3, [r7, #20] + 800256c: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c + 8002570: 68fb ldr r3, [r7, #12] + 8002572: 431a orrs r2, r3 + 8002574: 697b ldr r3, [r7, #20] + 8002576: f8c3 220c str.w r2, [r3, #524] ; 0x20c + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 800257a: 683b ldr r3, [r7, #0] + 800257c: 681b ldr r3, [r3, #0] + 800257e: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 8002580: 683b ldr r3, [r7, #0] + 8002582: 685b ldr r3, [r3, #4] + 8002584: b29b uxth r3, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 8002586: 683a ldr r2, [r7, #0] + 8002588: 6952 ldr r2, [r2, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 800258a: 4319 orrs r1, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 800258c: 697b ldr r3, [r7, #20] + 800258e: 3248 adds r2, #72 ; 0x48 + 8002590: f843 1032 str.w r1, [r3, r2, lsl #3] + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 8002594: 683b ldr r3, [r7, #0] + 8002596: 689b ldr r3, [r3, #8] + 8002598: 0419 lsls r1, r3, #16 + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + 800259a: 683b ldr r3, [r7, #0] + 800259c: 68db ldr r3, [r3, #12] + 800259e: b29a uxth r2, r3 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 80025a0: 683b ldr r3, [r7, #0] + 80025a2: 695b ldr r3, [r3, #20] + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 80025a4: 430a orrs r2, r1 + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 80025a6: 6979 ldr r1, [r7, #20] + 80025a8: 3348 adds r3, #72 ; 0x48 + 80025aa: 00db lsls r3, r3, #3 + 80025ac: 440b add r3, r1 + 80025ae: 605a str r2, [r3, #4] + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + 80025b0: 683b ldr r3, [r7, #0] + 80025b2: 699b ldr r3, [r3, #24] + 80025b4: 2b00 cmp r3, #0 + 80025b6: d109 bne.n 80025cc + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + 80025b8: 697b ldr r3, [r7, #20] + 80025ba: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 80025be: 68fb ldr r3, [r7, #12] + 80025c0: 43db mvns r3, r3 + 80025c2: 401a ands r2, r3 + 80025c4: 697b ldr r3, [r7, #20] + 80025c6: f8c3 2204 str.w r2, [r3, #516] ; 0x204 + 80025ca: e007 b.n 80025dc + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + 80025cc: 697b ldr r3, [r7, #20] + 80025ce: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204 + 80025d2: 68fb ldr r3, [r7, #12] + 80025d4: 431a orrs r2, r3 + 80025d6: 697b ldr r3, [r7, #20] + 80025d8: f8c3 2204 str.w r2, [r3, #516] ; 0x204 + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + 80025dc: 683b ldr r3, [r7, #0] + 80025de: 691b ldr r3, [r3, #16] + 80025e0: 2b00 cmp r3, #0 + 80025e2: d109 bne.n 80025f8 + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + 80025e4: 697b ldr r3, [r7, #20] + 80025e6: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214 + 80025ea: 68fb ldr r3, [r7, #12] + 80025ec: 43db mvns r3, r3 + 80025ee: 401a ands r2, r3 + 80025f0: 697b ldr r3, [r7, #20] + 80025f2: f8c3 2214 str.w r2, [r3, #532] ; 0x214 + 80025f6: e007 b.n 8002608 + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + 80025f8: 697b ldr r3, [r7, #20] + 80025fa: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214 + 80025fe: 68fb ldr r3, [r7, #12] + 8002600: 431a orrs r2, r3 + 8002602: 697b ldr r3, [r7, #20] + 8002604: f8c3 2214 str.w r2, [r3, #532] ; 0x214 + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + 8002608: 683b ldr r3, [r7, #0] + 800260a: 6a1b ldr r3, [r3, #32] + 800260c: 2b01 cmp r3, #1 + 800260e: d107 bne.n 8002620 + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + 8002610: 697b ldr r3, [r7, #20] + 8002612: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c + 8002616: 68fb ldr r3, [r7, #12] + 8002618: 431a orrs r2, r3 + 800261a: 697b ldr r3, [r7, #20] + 800261c: f8c3 221c str.w r2, [r3, #540] ; 0x21c + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + 8002620: 697b ldr r3, [r7, #20] + 8002622: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 8002626: f023 0201 bic.w r2, r3, #1 + 800262a: 697b ldr r3, [r7, #20] + 800262c: f8c3 2200 str.w r2, [r3, #512] ; 0x200 + + /* Return function status */ + return HAL_OK; + 8002630: 2300 movs r3, #0 + 8002632: e006 b.n 8002642 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 8002634: 687b ldr r3, [r7, #4] + 8002636: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002638: f443 2280 orr.w r2, r3, #262144 ; 0x40000 + 800263c: 687b ldr r3, [r7, #4] + 800263e: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 8002640: 2301 movs r3, #1 + } +} + 8002642: 4618 mov r0, r3 + 8002644: 371c adds r7, #28 + 8002646: 46bd mov sp, r7 + 8002648: f85d 7b04 ldr.w r7, [sp], #4 + 800264c: 4770 bx lr + +0800264e : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + 800264e: b580 push {r7, lr} + 8002650: b084 sub sp, #16 + 8002652: af00 add r7, sp, #0 + 8002654: 6078 str r0, [r7, #4] + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + 8002656: 687b ldr r3, [r7, #4] + 8002658: f893 3020 ldrb.w r3, [r3, #32] + 800265c: b2db uxtb r3, r3 + 800265e: 2b01 cmp r3, #1 + 8002660: d12e bne.n 80026c0 + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + 8002662: 687b ldr r3, [r7, #4] + 8002664: 2202 movs r2, #2 + 8002666: f883 2020 strb.w r2, [r3, #32] + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 800266a: 687b ldr r3, [r7, #4] + 800266c: 681b ldr r3, [r3, #0] + 800266e: 681a ldr r2, [r3, #0] + 8002670: 687b ldr r3, [r7, #4] + 8002672: 681b ldr r3, [r3, #0] + 8002674: f022 0201 bic.w r2, r2, #1 + 8002678: 601a str r2, [r3, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 800267a: f7ff fdf3 bl 8002264 + 800267e: 60f8 str r0, [r7, #12] + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + 8002680: e012 b.n 80026a8 + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 8002682: f7ff fdef bl 8002264 + 8002686: 4602 mov r2, r0 + 8002688: 68fb ldr r3, [r7, #12] + 800268a: 1ad3 subs r3, r2, r3 + 800268c: 2b0a cmp r3, #10 + 800268e: d90b bls.n 80026a8 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 8002690: 687b ldr r3, [r7, #4] + 8002692: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002694: f443 3200 orr.w r2, r3, #131072 ; 0x20000 + 8002698: 687b ldr r3, [r7, #4] + 800269a: 625a str r2, [r3, #36] ; 0x24 + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + 800269c: 687b ldr r3, [r7, #4] + 800269e: 2205 movs r2, #5 + 80026a0: f883 2020 strb.w r2, [r3, #32] + + return HAL_ERROR; + 80026a4: 2301 movs r3, #1 + 80026a6: e012 b.n 80026ce + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + 80026a8: 687b ldr r3, [r7, #4] + 80026aa: 681b ldr r3, [r3, #0] + 80026ac: 685b ldr r3, [r3, #4] + 80026ae: f003 0301 and.w r3, r3, #1 + 80026b2: 2b00 cmp r3, #0 + 80026b4: d1e5 bne.n 8002682 + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 80026b6: 687b ldr r3, [r7, #4] + 80026b8: 2200 movs r2, #0 + 80026ba: 625a str r2, [r3, #36] ; 0x24 + + /* Return function status */ + return HAL_OK; + 80026bc: 2300 movs r3, #0 + 80026be: e006 b.n 80026ce + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + 80026c0: 687b ldr r3, [r7, #4] + 80026c2: 6a5b ldr r3, [r3, #36] ; 0x24 + 80026c4: f443 2200 orr.w r2, r3, #524288 ; 0x80000 + 80026c8: 687b ldr r3, [r7, #4] + 80026ca: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 80026cc: 2301 movs r3, #1 + } +} + 80026ce: 4618 mov r0, r3 + 80026d0: 3710 adds r7, #16 + 80026d2: 46bd mov sp, r7 + 80026d4: bd80 pop {r7, pc} + +080026d6 : + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +{ + 80026d6: b480 push {r7} + 80026d8: b089 sub sp, #36 ; 0x24 + 80026da: af00 add r7, sp, #0 + 80026dc: 60f8 str r0, [r7, #12] + 80026de: 60b9 str r1, [r7, #8] + 80026e0: 607a str r2, [r7, #4] + 80026e2: 603b str r3, [r7, #0] + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + 80026e4: 68fb ldr r3, [r7, #12] + 80026e6: f893 3020 ldrb.w r3, [r3, #32] + 80026ea: 77fb strb r3, [r7, #31] + uint32_t tsr = READ_REG(hcan->Instance->TSR); + 80026ec: 68fb ldr r3, [r7, #12] + 80026ee: 681b ldr r3, [r3, #0] + 80026f0: 689b ldr r3, [r3, #8] + 80026f2: 61bb str r3, [r7, #24] + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + 80026f4: 7ffb ldrb r3, [r7, #31] + 80026f6: 2b01 cmp r3, #1 + 80026f8: d003 beq.n 8002702 + 80026fa: 7ffb ldrb r3, [r7, #31] + 80026fc: 2b02 cmp r3, #2 + 80026fe: f040 80b8 bne.w 8002872 + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + 8002702: 69bb ldr r3, [r7, #24] + 8002704: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8002708: 2b00 cmp r3, #0 + 800270a: d10a bne.n 8002722 + ((tsr & CAN_TSR_TME1) != 0U) || + 800270c: 69bb ldr r3, [r7, #24] + 800270e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + if (((tsr & CAN_TSR_TME0) != 0U) || + 8002712: 2b00 cmp r3, #0 + 8002714: d105 bne.n 8002722 + ((tsr & CAN_TSR_TME2) != 0U)) + 8002716: 69bb ldr r3, [r7, #24] + 8002718: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + ((tsr & CAN_TSR_TME1) != 0U) || + 800271c: 2b00 cmp r3, #0 + 800271e: f000 80a0 beq.w 8002862 + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + 8002722: 69bb ldr r3, [r7, #24] + 8002724: 0e1b lsrs r3, r3, #24 + 8002726: f003 0303 and.w r3, r3, #3 + 800272a: 617b str r3, [r7, #20] + + /* Check transmit mailbox value */ + if (transmitmailbox > 2U) + 800272c: 697b ldr r3, [r7, #20] + 800272e: 2b02 cmp r3, #2 + 8002730: d907 bls.n 8002742 + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; + 8002732: 68fb ldr r3, [r7, #12] + 8002734: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002736: f443 0200 orr.w r2, r3, #8388608 ; 0x800000 + 800273a: 68fb ldr r3, [r7, #12] + 800273c: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 800273e: 2301 movs r3, #1 + 8002740: e09e b.n 8002880 + } + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + 8002742: 2201 movs r2, #1 + 8002744: 697b ldr r3, [r7, #20] + 8002746: 409a lsls r2, r3 + 8002748: 683b ldr r3, [r7, #0] + 800274a: 601a str r2, [r3, #0] + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + 800274c: 68bb ldr r3, [r7, #8] + 800274e: 689b ldr r3, [r3, #8] + 8002750: 2b00 cmp r3, #0 + 8002752: d10d bne.n 8002770 + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + 8002754: 68bb ldr r3, [r7, #8] + 8002756: 681b ldr r3, [r3, #0] + 8002758: 055a lsls r2, r3, #21 + pHeader->RTR); + 800275a: 68bb ldr r3, [r7, #8] + 800275c: 68db ldr r3, [r3, #12] + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + 800275e: 68f9 ldr r1, [r7, #12] + 8002760: 6809 ldr r1, [r1, #0] + 8002762: 431a orrs r2, r3 + 8002764: 697b ldr r3, [r7, #20] + 8002766: 3318 adds r3, #24 + 8002768: 011b lsls r3, r3, #4 + 800276a: 440b add r3, r1 + 800276c: 601a str r2, [r3, #0] + 800276e: e00f b.n 8002790 + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 8002770: 68bb ldr r3, [r7, #8] + 8002772: 685b ldr r3, [r3, #4] + 8002774: 00da lsls r2, r3, #3 + pHeader->IDE | + 8002776: 68bb ldr r3, [r7, #8] + 8002778: 689b ldr r3, [r3, #8] + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 800277a: 431a orrs r2, r3 + pHeader->RTR); + 800277c: 68bb ldr r3, [r7, #8] + 800277e: 68db ldr r3, [r3, #12] + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 8002780: 68f9 ldr r1, [r7, #12] + 8002782: 6809 ldr r1, [r1, #0] + pHeader->IDE | + 8002784: 431a orrs r2, r3 + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 8002786: 697b ldr r3, [r7, #20] + 8002788: 3318 adds r3, #24 + 800278a: 011b lsls r3, r3, #4 + 800278c: 440b add r3, r1 + 800278e: 601a str r2, [r3, #0] + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + 8002790: 68fb ldr r3, [r7, #12] + 8002792: 6819 ldr r1, [r3, #0] + 8002794: 68bb ldr r3, [r7, #8] + 8002796: 691a ldr r2, [r3, #16] + 8002798: 697b ldr r3, [r7, #20] + 800279a: 3318 adds r3, #24 + 800279c: 011b lsls r3, r3, #4 + 800279e: 440b add r3, r1 + 80027a0: 3304 adds r3, #4 + 80027a2: 601a str r2, [r3, #0] + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + 80027a4: 68bb ldr r3, [r7, #8] + 80027a6: 7d1b ldrb r3, [r3, #20] + 80027a8: 2b01 cmp r3, #1 + 80027aa: d111 bne.n 80027d0 + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + 80027ac: 68fb ldr r3, [r7, #12] + 80027ae: 681a ldr r2, [r3, #0] + 80027b0: 697b ldr r3, [r7, #20] + 80027b2: 3318 adds r3, #24 + 80027b4: 011b lsls r3, r3, #4 + 80027b6: 4413 add r3, r2 + 80027b8: 3304 adds r3, #4 + 80027ba: 681b ldr r3, [r3, #0] + 80027bc: 68fa ldr r2, [r7, #12] + 80027be: 6811 ldr r1, [r2, #0] + 80027c0: f443 7280 orr.w r2, r3, #256 ; 0x100 + 80027c4: 697b ldr r3, [r7, #20] + 80027c6: 3318 adds r3, #24 + 80027c8: 011b lsls r3, r3, #4 + 80027ca: 440b add r3, r1 + 80027cc: 3304 adds r3, #4 + 80027ce: 601a str r2, [r3, #0] + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + 80027d0: 687b ldr r3, [r7, #4] + 80027d2: 3307 adds r3, #7 + 80027d4: 781b ldrb r3, [r3, #0] + 80027d6: 061a lsls r2, r3, #24 + 80027d8: 687b ldr r3, [r7, #4] + 80027da: 3306 adds r3, #6 + 80027dc: 781b ldrb r3, [r3, #0] + 80027de: 041b lsls r3, r3, #16 + 80027e0: 431a orrs r2, r3 + 80027e2: 687b ldr r3, [r7, #4] + 80027e4: 3305 adds r3, #5 + 80027e6: 781b ldrb r3, [r3, #0] + 80027e8: 021b lsls r3, r3, #8 + 80027ea: 4313 orrs r3, r2 + 80027ec: 687a ldr r2, [r7, #4] + 80027ee: 3204 adds r2, #4 + 80027f0: 7812 ldrb r2, [r2, #0] + 80027f2: 4610 mov r0, r2 + 80027f4: 68fa ldr r2, [r7, #12] + 80027f6: 6811 ldr r1, [r2, #0] + 80027f8: ea43 0200 orr.w r2, r3, r0 + 80027fc: 697b ldr r3, [r7, #20] + 80027fe: 011b lsls r3, r3, #4 + 8002800: 440b add r3, r1 + 8002802: f503 73c6 add.w r3, r3, #396 ; 0x18c + 8002806: 601a str r2, [r3, #0] + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + 8002808: 687b ldr r3, [r7, #4] + 800280a: 3303 adds r3, #3 + 800280c: 781b ldrb r3, [r3, #0] + 800280e: 061a lsls r2, r3, #24 + 8002810: 687b ldr r3, [r7, #4] + 8002812: 3302 adds r3, #2 + 8002814: 781b ldrb r3, [r3, #0] + 8002816: 041b lsls r3, r3, #16 + 8002818: 431a orrs r2, r3 + 800281a: 687b ldr r3, [r7, #4] + 800281c: 3301 adds r3, #1 + 800281e: 781b ldrb r3, [r3, #0] + 8002820: 021b lsls r3, r3, #8 + 8002822: 4313 orrs r3, r2 + 8002824: 687a ldr r2, [r7, #4] + 8002826: 7812 ldrb r2, [r2, #0] + 8002828: 4610 mov r0, r2 + 800282a: 68fa ldr r2, [r7, #12] + 800282c: 6811 ldr r1, [r2, #0] + 800282e: ea43 0200 orr.w r2, r3, r0 + 8002832: 697b ldr r3, [r7, #20] + 8002834: 011b lsls r3, r3, #4 + 8002836: 440b add r3, r1 + 8002838: f503 73c4 add.w r3, r3, #392 ; 0x188 + 800283c: 601a str r2, [r3, #0] + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + 800283e: 68fb ldr r3, [r7, #12] + 8002840: 681a ldr r2, [r3, #0] + 8002842: 697b ldr r3, [r7, #20] + 8002844: 3318 adds r3, #24 + 8002846: 011b lsls r3, r3, #4 + 8002848: 4413 add r3, r2 + 800284a: 681b ldr r3, [r3, #0] + 800284c: 68fa ldr r2, [r7, #12] + 800284e: 6811 ldr r1, [r2, #0] + 8002850: f043 0201 orr.w r2, r3, #1 + 8002854: 697b ldr r3, [r7, #20] + 8002856: 3318 adds r3, #24 + 8002858: 011b lsls r3, r3, #4 + 800285a: 440b add r3, r1 + 800285c: 601a str r2, [r3, #0] + + /* Return function status */ + return HAL_OK; + 800285e: 2300 movs r3, #0 + 8002860: e00e b.n 8002880 + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 8002862: 68fb ldr r3, [r7, #12] + 8002864: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002866: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 + 800286a: 68fb ldr r3, [r7, #12] + 800286c: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 800286e: 2301 movs r3, #1 + 8002870: e006 b.n 8002880 + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 8002872: 68fb ldr r3, [r7, #12] + 8002874: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002876: f443 2280 orr.w r2, r3, #262144 ; 0x40000 + 800287a: 68fb ldr r3, [r7, #12] + 800287c: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 800287e: 2301 movs r3, #1 + } +} + 8002880: 4618 mov r0, r3 + 8002882: 3724 adds r7, #36 ; 0x24 + 8002884: 46bd mov sp, r7 + 8002886: f85d 7b04 ldr.w r7, [sp], #4 + 800288a: 4770 bx lr + +0800288c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + 800288c: b480 push {r7} + 800288e: b085 sub sp, #20 + 8002890: af00 add r7, sp, #0 + 8002892: 6078 str r0, [r7, #4] + uint32_t freelevel = 0U; + 8002894: 2300 movs r3, #0 + 8002896: 60fb str r3, [r7, #12] + HAL_CAN_StateTypeDef state = hcan->State; + 8002898: 687b ldr r3, [r7, #4] + 800289a: f893 3020 ldrb.w r3, [r3, #32] + 800289e: 72fb strb r3, [r7, #11] + + if ((state == HAL_CAN_STATE_READY) || + 80028a0: 7afb ldrb r3, [r7, #11] + 80028a2: 2b01 cmp r3, #1 + 80028a4: d002 beq.n 80028ac + 80028a6: 7afb ldrb r3, [r7, #11] + 80028a8: 2b02 cmp r3, #2 + 80028aa: d11d bne.n 80028e8 + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + 80028ac: 687b ldr r3, [r7, #4] + 80028ae: 681b ldr r3, [r3, #0] + 80028b0: 689b ldr r3, [r3, #8] + 80028b2: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 80028b6: 2b00 cmp r3, #0 + 80028b8: d002 beq.n 80028c0 + { + freelevel++; + 80028ba: 68fb ldr r3, [r7, #12] + 80028bc: 3301 adds r3, #1 + 80028be: 60fb str r3, [r7, #12] + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + 80028c0: 687b ldr r3, [r7, #4] + 80028c2: 681b ldr r3, [r3, #0] + 80028c4: 689b ldr r3, [r3, #8] + 80028c6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 80028ca: 2b00 cmp r3, #0 + 80028cc: d002 beq.n 80028d4 + { + freelevel++; + 80028ce: 68fb ldr r3, [r7, #12] + 80028d0: 3301 adds r3, #1 + 80028d2: 60fb str r3, [r7, #12] + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + 80028d4: 687b ldr r3, [r7, #4] + 80028d6: 681b ldr r3, [r3, #0] + 80028d8: 689b ldr r3, [r3, #8] + 80028da: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80028de: 2b00 cmp r3, #0 + 80028e0: d002 beq.n 80028e8 + { + freelevel++; + 80028e2: 68fb ldr r3, [r7, #12] + 80028e4: 3301 adds r3, #1 + 80028e6: 60fb str r3, [r7, #12] + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; + 80028e8: 68fb ldr r3, [r7, #12] +} + 80028ea: 4618 mov r0, r3 + 80028ec: 3714 adds r7, #20 + 80028ee: 46bd mov sp, r7 + 80028f0: f85d 7b04 ldr.w r7, [sp], #4 + 80028f4: 4770 bx lr + +080028f6 : + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + 80028f6: b480 push {r7} + 80028f8: b087 sub sp, #28 + 80028fa: af00 add r7, sp, #0 + 80028fc: 60f8 str r0, [r7, #12] + 80028fe: 60b9 str r1, [r7, #8] + 8002900: 607a str r2, [r7, #4] + 8002902: 603b str r3, [r7, #0] + HAL_CAN_StateTypeDef state = hcan->State; + 8002904: 68fb ldr r3, [r7, #12] + 8002906: f893 3020 ldrb.w r3, [r3, #32] + 800290a: 75fb strb r3, [r7, #23] + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + 800290c: 7dfb ldrb r3, [r7, #23] + 800290e: 2b01 cmp r3, #1 + 8002910: d003 beq.n 800291a + 8002912: 7dfb ldrb r3, [r7, #23] + 8002914: 2b02 cmp r3, #2 + 8002916: f040 80f3 bne.w 8002b00 + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 800291a: 68bb ldr r3, [r7, #8] + 800291c: 2b00 cmp r3, #0 + 800291e: d10e bne.n 800293e + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + 8002920: 68fb ldr r3, [r7, #12] + 8002922: 681b ldr r3, [r3, #0] + 8002924: 68db ldr r3, [r3, #12] + 8002926: f003 0303 and.w r3, r3, #3 + 800292a: 2b00 cmp r3, #0 + 800292c: d116 bne.n 800295c + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 800292e: 68fb ldr r3, [r7, #12] + 8002930: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002932: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 + 8002936: 68fb ldr r3, [r7, #12] + 8002938: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 800293a: 2301 movs r3, #1 + 800293c: e0e7 b.n 8002b0e + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + 800293e: 68fb ldr r3, [r7, #12] + 8002940: 681b ldr r3, [r3, #0] + 8002942: 691b ldr r3, [r3, #16] + 8002944: f003 0303 and.w r3, r3, #3 + 8002948: 2b00 cmp r3, #0 + 800294a: d107 bne.n 800295c + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 800294c: 68fb ldr r3, [r7, #12] + 800294e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002950: f443 1200 orr.w r2, r3, #2097152 ; 0x200000 + 8002954: 68fb ldr r3, [r7, #12] + 8002956: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 8002958: 2301 movs r3, #1 + 800295a: e0d8 b.n 8002b0e + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + 800295c: 68fb ldr r3, [r7, #12] + 800295e: 681a ldr r2, [r3, #0] + 8002960: 68bb ldr r3, [r7, #8] + 8002962: 331b adds r3, #27 + 8002964: 011b lsls r3, r3, #4 + 8002966: 4413 add r3, r2 + 8002968: 681b ldr r3, [r3, #0] + 800296a: f003 0204 and.w r2, r3, #4 + 800296e: 687b ldr r3, [r7, #4] + 8002970: 609a str r2, [r3, #8] + if (pHeader->IDE == CAN_ID_STD) + 8002972: 687b ldr r3, [r7, #4] + 8002974: 689b ldr r3, [r3, #8] + 8002976: 2b00 cmp r3, #0 + 8002978: d10c bne.n 8002994 + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + 800297a: 68fb ldr r3, [r7, #12] + 800297c: 681a ldr r2, [r3, #0] + 800297e: 68bb ldr r3, [r7, #8] + 8002980: 331b adds r3, #27 + 8002982: 011b lsls r3, r3, #4 + 8002984: 4413 add r3, r2 + 8002986: 681b ldr r3, [r3, #0] + 8002988: 0d5b lsrs r3, r3, #21 + 800298a: f3c3 020a ubfx r2, r3, #0, #11 + 800298e: 687b ldr r3, [r7, #4] + 8002990: 601a str r2, [r3, #0] + 8002992: e00b b.n 80029ac + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + 8002994: 68fb ldr r3, [r7, #12] + 8002996: 681a ldr r2, [r3, #0] + 8002998: 68bb ldr r3, [r7, #8] + 800299a: 331b adds r3, #27 + 800299c: 011b lsls r3, r3, #4 + 800299e: 4413 add r3, r2 + 80029a0: 681b ldr r3, [r3, #0] + 80029a2: 08db lsrs r3, r3, #3 + 80029a4: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000 + 80029a8: 687b ldr r3, [r7, #4] + 80029aa: 605a str r2, [r3, #4] + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + 80029ac: 68fb ldr r3, [r7, #12] + 80029ae: 681a ldr r2, [r3, #0] + 80029b0: 68bb ldr r3, [r7, #8] + 80029b2: 331b adds r3, #27 + 80029b4: 011b lsls r3, r3, #4 + 80029b6: 4413 add r3, r2 + 80029b8: 681b ldr r3, [r3, #0] + 80029ba: f003 0202 and.w r2, r3, #2 + 80029be: 687b ldr r3, [r7, #4] + 80029c0: 60da str r2, [r3, #12] + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + 80029c2: 68fb ldr r3, [r7, #12] + 80029c4: 681a ldr r2, [r3, #0] + 80029c6: 68bb ldr r3, [r7, #8] + 80029c8: 331b adds r3, #27 + 80029ca: 011b lsls r3, r3, #4 + 80029cc: 4413 add r3, r2 + 80029ce: 3304 adds r3, #4 + 80029d0: 681b ldr r3, [r3, #0] + 80029d2: f003 020f and.w r2, r3, #15 + 80029d6: 687b ldr r3, [r7, #4] + 80029d8: 611a str r2, [r3, #16] + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + 80029da: 68fb ldr r3, [r7, #12] + 80029dc: 681a ldr r2, [r3, #0] + 80029de: 68bb ldr r3, [r7, #8] + 80029e0: 331b adds r3, #27 + 80029e2: 011b lsls r3, r3, #4 + 80029e4: 4413 add r3, r2 + 80029e6: 3304 adds r3, #4 + 80029e8: 681b ldr r3, [r3, #0] + 80029ea: 0a1b lsrs r3, r3, #8 + 80029ec: b2da uxtb r2, r3 + 80029ee: 687b ldr r3, [r7, #4] + 80029f0: 619a str r2, [r3, #24] + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + 80029f2: 68fb ldr r3, [r7, #12] + 80029f4: 681a ldr r2, [r3, #0] + 80029f6: 68bb ldr r3, [r7, #8] + 80029f8: 331b adds r3, #27 + 80029fa: 011b lsls r3, r3, #4 + 80029fc: 4413 add r3, r2 + 80029fe: 3304 adds r3, #4 + 8002a00: 681b ldr r3, [r3, #0] + 8002a02: 0c1b lsrs r3, r3, #16 + 8002a04: b29a uxth r2, r3 + 8002a06: 687b ldr r3, [r7, #4] + 8002a08: 615a str r2, [r3, #20] + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + 8002a0a: 68fb ldr r3, [r7, #12] + 8002a0c: 681a ldr r2, [r3, #0] + 8002a0e: 68bb ldr r3, [r7, #8] + 8002a10: 011b lsls r3, r3, #4 + 8002a12: 4413 add r3, r2 + 8002a14: f503 73dc add.w r3, r3, #440 ; 0x1b8 + 8002a18: 681b ldr r3, [r3, #0] + 8002a1a: b2da uxtb r2, r3 + 8002a1c: 683b ldr r3, [r7, #0] + 8002a1e: 701a strb r2, [r3, #0] + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + 8002a20: 68fb ldr r3, [r7, #12] + 8002a22: 681a ldr r2, [r3, #0] + 8002a24: 68bb ldr r3, [r7, #8] + 8002a26: 011b lsls r3, r3, #4 + 8002a28: 4413 add r3, r2 + 8002a2a: f503 73dc add.w r3, r3, #440 ; 0x1b8 + 8002a2e: 681b ldr r3, [r3, #0] + 8002a30: 0a1a lsrs r2, r3, #8 + 8002a32: 683b ldr r3, [r7, #0] + 8002a34: 3301 adds r3, #1 + 8002a36: b2d2 uxtb r2, r2 + 8002a38: 701a strb r2, [r3, #0] + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + 8002a3a: 68fb ldr r3, [r7, #12] + 8002a3c: 681a ldr r2, [r3, #0] + 8002a3e: 68bb ldr r3, [r7, #8] + 8002a40: 011b lsls r3, r3, #4 + 8002a42: 4413 add r3, r2 + 8002a44: f503 73dc add.w r3, r3, #440 ; 0x1b8 + 8002a48: 681b ldr r3, [r3, #0] + 8002a4a: 0c1a lsrs r2, r3, #16 + 8002a4c: 683b ldr r3, [r7, #0] + 8002a4e: 3302 adds r3, #2 + 8002a50: b2d2 uxtb r2, r2 + 8002a52: 701a strb r2, [r3, #0] + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + 8002a54: 68fb ldr r3, [r7, #12] + 8002a56: 681a ldr r2, [r3, #0] + 8002a58: 68bb ldr r3, [r7, #8] + 8002a5a: 011b lsls r3, r3, #4 + 8002a5c: 4413 add r3, r2 + 8002a5e: f503 73dc add.w r3, r3, #440 ; 0x1b8 + 8002a62: 681b ldr r3, [r3, #0] + 8002a64: 0e1a lsrs r2, r3, #24 + 8002a66: 683b ldr r3, [r7, #0] + 8002a68: 3303 adds r3, #3 + 8002a6a: b2d2 uxtb r2, r2 + 8002a6c: 701a strb r2, [r3, #0] + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + 8002a6e: 68fb ldr r3, [r7, #12] + 8002a70: 681a ldr r2, [r3, #0] + 8002a72: 68bb ldr r3, [r7, #8] + 8002a74: 011b lsls r3, r3, #4 + 8002a76: 4413 add r3, r2 + 8002a78: f503 73de add.w r3, r3, #444 ; 0x1bc + 8002a7c: 681a ldr r2, [r3, #0] + 8002a7e: 683b ldr r3, [r7, #0] + 8002a80: 3304 adds r3, #4 + 8002a82: b2d2 uxtb r2, r2 + 8002a84: 701a strb r2, [r3, #0] + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + 8002a86: 68fb ldr r3, [r7, #12] + 8002a88: 681a ldr r2, [r3, #0] + 8002a8a: 68bb ldr r3, [r7, #8] + 8002a8c: 011b lsls r3, r3, #4 + 8002a8e: 4413 add r3, r2 + 8002a90: f503 73de add.w r3, r3, #444 ; 0x1bc + 8002a94: 681b ldr r3, [r3, #0] + 8002a96: 0a1a lsrs r2, r3, #8 + 8002a98: 683b ldr r3, [r7, #0] + 8002a9a: 3305 adds r3, #5 + 8002a9c: b2d2 uxtb r2, r2 + 8002a9e: 701a strb r2, [r3, #0] + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + 8002aa0: 68fb ldr r3, [r7, #12] + 8002aa2: 681a ldr r2, [r3, #0] + 8002aa4: 68bb ldr r3, [r7, #8] + 8002aa6: 011b lsls r3, r3, #4 + 8002aa8: 4413 add r3, r2 + 8002aaa: f503 73de add.w r3, r3, #444 ; 0x1bc + 8002aae: 681b ldr r3, [r3, #0] + 8002ab0: 0c1a lsrs r2, r3, #16 + 8002ab2: 683b ldr r3, [r7, #0] + 8002ab4: 3306 adds r3, #6 + 8002ab6: b2d2 uxtb r2, r2 + 8002ab8: 701a strb r2, [r3, #0] + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + 8002aba: 68fb ldr r3, [r7, #12] + 8002abc: 681a ldr r2, [r3, #0] + 8002abe: 68bb ldr r3, [r7, #8] + 8002ac0: 011b lsls r3, r3, #4 + 8002ac2: 4413 add r3, r2 + 8002ac4: f503 73de add.w r3, r3, #444 ; 0x1bc + 8002ac8: 681b ldr r3, [r3, #0] + 8002aca: 0e1a lsrs r2, r3, #24 + 8002acc: 683b ldr r3, [r7, #0] + 8002ace: 3307 adds r3, #7 + 8002ad0: b2d2 uxtb r2, r2 + 8002ad2: 701a strb r2, [r3, #0] + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 8002ad4: 68bb ldr r3, [r7, #8] + 8002ad6: 2b00 cmp r3, #0 + 8002ad8: d108 bne.n 8002aec + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + 8002ada: 68fb ldr r3, [r7, #12] + 8002adc: 681b ldr r3, [r3, #0] + 8002ade: 68da ldr r2, [r3, #12] + 8002ae0: 68fb ldr r3, [r7, #12] + 8002ae2: 681b ldr r3, [r3, #0] + 8002ae4: f042 0220 orr.w r2, r2, #32 + 8002ae8: 60da str r2, [r3, #12] + 8002aea: e007 b.n 8002afc + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + 8002aec: 68fb ldr r3, [r7, #12] + 8002aee: 681b ldr r3, [r3, #0] + 8002af0: 691a ldr r2, [r3, #16] + 8002af2: 68fb ldr r3, [r7, #12] + 8002af4: 681b ldr r3, [r3, #0] + 8002af6: f042 0220 orr.w r2, r2, #32 + 8002afa: 611a str r2, [r3, #16] + } + + /* Return function status */ + return HAL_OK; + 8002afc: 2300 movs r3, #0 + 8002afe: e006 b.n 8002b0e + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 8002b00: 68fb ldr r3, [r7, #12] + 8002b02: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002b04: f443 2280 orr.w r2, r3, #262144 ; 0x40000 + 8002b08: 68fb ldr r3, [r7, #12] + 8002b0a: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 8002b0c: 2301 movs r3, #1 + } +} + 8002b0e: 4618 mov r0, r3 + 8002b10: 371c adds r7, #28 + 8002b12: 46bd mov sp, r7 + 8002b14: f85d 7b04 ldr.w r7, [sp], #4 + 8002b18: 4770 bx lr + +08002b1a : + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + 8002b1a: b480 push {r7} + 8002b1c: b085 sub sp, #20 + 8002b1e: af00 add r7, sp, #0 + 8002b20: 6078 str r0, [r7, #4] + 8002b22: 6039 str r1, [r7, #0] + HAL_CAN_StateTypeDef state = hcan->State; + 8002b24: 687b ldr r3, [r7, #4] + 8002b26: f893 3020 ldrb.w r3, [r3, #32] + 8002b2a: 73fb strb r3, [r7, #15] + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + 8002b2c: 7bfb ldrb r3, [r7, #15] + 8002b2e: 2b01 cmp r3, #1 + 8002b30: d002 beq.n 8002b38 + 8002b32: 7bfb ldrb r3, [r7, #15] + 8002b34: 2b02 cmp r3, #2 + 8002b36: d109 bne.n 8002b4c + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + 8002b38: 687b ldr r3, [r7, #4] + 8002b3a: 681b ldr r3, [r3, #0] + 8002b3c: 6959 ldr r1, [r3, #20] + 8002b3e: 687b ldr r3, [r7, #4] + 8002b40: 681b ldr r3, [r3, #0] + 8002b42: 683a ldr r2, [r7, #0] + 8002b44: 430a orrs r2, r1 + 8002b46: 615a str r2, [r3, #20] + + /* Return function status */ + return HAL_OK; + 8002b48: 2300 movs r3, #0 + 8002b4a: e006 b.n 8002b5a + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 8002b4c: 687b ldr r3, [r7, #4] + 8002b4e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002b50: f443 2280 orr.w r2, r3, #262144 ; 0x40000 + 8002b54: 687b ldr r3, [r7, #4] + 8002b56: 625a str r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 8002b58: 2301 movs r3, #1 + } +} + 8002b5a: 4618 mov r0, r3 + 8002b5c: 3714 adds r7, #20 + 8002b5e: 46bd mov sp, r7 + 8002b60: f85d 7b04 ldr.w r7, [sp], #4 + 8002b64: 4770 bx lr + +08002b66 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + 8002b66: b580 push {r7, lr} + 8002b68: b08a sub sp, #40 ; 0x28 + 8002b6a: af00 add r7, sp, #0 + 8002b6c: 6078 str r0, [r7, #4] + uint32_t errorcode = HAL_CAN_ERROR_NONE; + 8002b6e: 2300 movs r3, #0 + 8002b70: 627b str r3, [r7, #36] ; 0x24 + uint32_t interrupts = READ_REG(hcan->Instance->IER); + 8002b72: 687b ldr r3, [r7, #4] + 8002b74: 681b ldr r3, [r3, #0] + 8002b76: 695b ldr r3, [r3, #20] + 8002b78: 623b str r3, [r7, #32] + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + 8002b7a: 687b ldr r3, [r7, #4] + 8002b7c: 681b ldr r3, [r3, #0] + 8002b7e: 685b ldr r3, [r3, #4] + 8002b80: 61fb str r3, [r7, #28] + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + 8002b82: 687b ldr r3, [r7, #4] + 8002b84: 681b ldr r3, [r3, #0] + 8002b86: 689b ldr r3, [r3, #8] + 8002b88: 61bb str r3, [r7, #24] + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + 8002b8a: 687b ldr r3, [r7, #4] + 8002b8c: 681b ldr r3, [r3, #0] + 8002b8e: 68db ldr r3, [r3, #12] + 8002b90: 617b str r3, [r7, #20] + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + 8002b92: 687b ldr r3, [r7, #4] + 8002b94: 681b ldr r3, [r3, #0] + 8002b96: 691b ldr r3, [r3, #16] + 8002b98: 613b str r3, [r7, #16] + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + 8002b9a: 687b ldr r3, [r7, #4] + 8002b9c: 681b ldr r3, [r3, #0] + 8002b9e: 699b ldr r3, [r3, #24] + 8002ba0: 60fb str r3, [r7, #12] + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + 8002ba2: 6a3b ldr r3, [r7, #32] + 8002ba4: f003 0301 and.w r3, r3, #1 + 8002ba8: 2b00 cmp r3, #0 + 8002baa: d07c beq.n 8002ca6 + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + 8002bac: 69bb ldr r3, [r7, #24] + 8002bae: f003 0301 and.w r3, r3, #1 + 8002bb2: 2b00 cmp r3, #0 + 8002bb4: d023 beq.n 8002bfe + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + 8002bb6: 687b ldr r3, [r7, #4] + 8002bb8: 681b ldr r3, [r3, #0] + 8002bba: 2201 movs r2, #1 + 8002bbc: 609a str r2, [r3, #8] + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + 8002bbe: 69bb ldr r3, [r7, #24] + 8002bc0: f003 0302 and.w r3, r3, #2 + 8002bc4: 2b00 cmp r3, #0 + 8002bc6: d003 beq.n 8002bd0 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + 8002bc8: 6878 ldr r0, [r7, #4] + 8002bca: f000 f983 bl 8002ed4 + 8002bce: e016 b.n 8002bfe +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + 8002bd0: 69bb ldr r3, [r7, #24] + 8002bd2: f003 0304 and.w r3, r3, #4 + 8002bd6: 2b00 cmp r3, #0 + 8002bd8: d004 beq.n 8002be4 + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + 8002bda: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002bdc: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 8002be0: 627b str r3, [r7, #36] ; 0x24 + 8002be2: e00c b.n 8002bfe + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + 8002be4: 69bb ldr r3, [r7, #24] + 8002be6: f003 0308 and.w r3, r3, #8 + 8002bea: 2b00 cmp r3, #0 + 8002bec: d004 beq.n 8002bf8 + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + 8002bee: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002bf0: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 8002bf4: 627b str r3, [r7, #36] ; 0x24 + 8002bf6: e002 b.n 8002bfe +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + 8002bf8: 6878 ldr r0, [r7, #4] + 8002bfa: f000 f989 bl 8002f10 + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + 8002bfe: 69bb ldr r3, [r7, #24] + 8002c00: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002c04: 2b00 cmp r3, #0 + 8002c06: d024 beq.n 8002c52 + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + 8002c08: 687b ldr r3, [r7, #4] + 8002c0a: 681b ldr r3, [r3, #0] + 8002c0c: f44f 7280 mov.w r2, #256 ; 0x100 + 8002c10: 609a str r2, [r3, #8] + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + 8002c12: 69bb ldr r3, [r7, #24] + 8002c14: f403 7300 and.w r3, r3, #512 ; 0x200 + 8002c18: 2b00 cmp r3, #0 + 8002c1a: d003 beq.n 8002c24 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + 8002c1c: 6878 ldr r0, [r7, #4] + 8002c1e: f000 f963 bl 8002ee8 + 8002c22: e016 b.n 8002c52 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + 8002c24: 69bb ldr r3, [r7, #24] + 8002c26: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002c2a: 2b00 cmp r3, #0 + 8002c2c: d004 beq.n 8002c38 + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + 8002c2e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002c30: f443 5300 orr.w r3, r3, #8192 ; 0x2000 + 8002c34: 627b str r3, [r7, #36] ; 0x24 + 8002c36: e00c b.n 8002c52 + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + 8002c38: 69bb ldr r3, [r7, #24] + 8002c3a: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8002c3e: 2b00 cmp r3, #0 + 8002c40: d004 beq.n 8002c4c + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + 8002c42: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002c44: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8002c48: 627b str r3, [r7, #36] ; 0x24 + 8002c4a: e002 b.n 8002c52 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + 8002c4c: 6878 ldr r0, [r7, #4] + 8002c4e: f000 f969 bl 8002f24 + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + 8002c52: 69bb ldr r3, [r7, #24] + 8002c54: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8002c58: 2b00 cmp r3, #0 + 8002c5a: d024 beq.n 8002ca6 + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + 8002c5c: 687b ldr r3, [r7, #4] + 8002c5e: 681b ldr r3, [r3, #0] + 8002c60: f44f 3280 mov.w r2, #65536 ; 0x10000 + 8002c64: 609a str r2, [r3, #8] + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + 8002c66: 69bb ldr r3, [r7, #24] + 8002c68: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002c6c: 2b00 cmp r3, #0 + 8002c6e: d003 beq.n 8002c78 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + 8002c70: 6878 ldr r0, [r7, #4] + 8002c72: f000 f943 bl 8002efc + 8002c76: e016 b.n 8002ca6 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + 8002c78: 69bb ldr r3, [r7, #24] + 8002c7a: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8002c7e: 2b00 cmp r3, #0 + 8002c80: d004 beq.n 8002c8c + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + 8002c82: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002c84: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8002c88: 627b str r3, [r7, #36] ; 0x24 + 8002c8a: e00c b.n 8002ca6 + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + 8002c8c: 69bb ldr r3, [r7, #24] + 8002c8e: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8002c92: 2b00 cmp r3, #0 + 8002c94: d004 beq.n 8002ca0 + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + 8002c96: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002c98: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002c9c: 627b str r3, [r7, #36] ; 0x24 + 8002c9e: e002 b.n 8002ca6 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + 8002ca0: 6878 ldr r0, [r7, #4] + 8002ca2: f000 f949 bl 8002f38 + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + 8002ca6: 6a3b ldr r3, [r7, #32] + 8002ca8: f003 0308 and.w r3, r3, #8 + 8002cac: 2b00 cmp r3, #0 + 8002cae: d00c beq.n 8002cca + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + 8002cb0: 697b ldr r3, [r7, #20] + 8002cb2: f003 0310 and.w r3, r3, #16 + 8002cb6: 2b00 cmp r3, #0 + 8002cb8: d007 beq.n 8002cca + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + 8002cba: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002cbc: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8002cc0: 627b str r3, [r7, #36] ; 0x24 + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + 8002cc2: 687b ldr r3, [r7, #4] + 8002cc4: 681b ldr r3, [r3, #0] + 8002cc6: 2210 movs r2, #16 + 8002cc8: 60da str r2, [r3, #12] + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + 8002cca: 6a3b ldr r3, [r7, #32] + 8002ccc: f003 0304 and.w r3, r3, #4 + 8002cd0: 2b00 cmp r3, #0 + 8002cd2: d00b beq.n 8002cec + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + 8002cd4: 697b ldr r3, [r7, #20] + 8002cd6: f003 0308 and.w r3, r3, #8 + 8002cda: 2b00 cmp r3, #0 + 8002cdc: d006 beq.n 8002cec + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + 8002cde: 687b ldr r3, [r7, #4] + 8002ce0: 681b ldr r3, [r3, #0] + 8002ce2: 2208 movs r2, #8 + 8002ce4: 60da str r2, [r3, #12] +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + 8002ce6: 6878 ldr r0, [r7, #4] + 8002ce8: f000 f930 bl 8002f4c +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + 8002cec: 6a3b ldr r3, [r7, #32] + 8002cee: f003 0302 and.w r3, r3, #2 + 8002cf2: 2b00 cmp r3, #0 + 8002cf4: d009 beq.n 8002d0a + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + 8002cf6: 687b ldr r3, [r7, #4] + 8002cf8: 681b ldr r3, [r3, #0] + 8002cfa: 68db ldr r3, [r3, #12] + 8002cfc: f003 0303 and.w r3, r3, #3 + 8002d00: 2b00 cmp r3, #0 + 8002d02: d002 beq.n 8002d0a +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + 8002d04: 6878 ldr r0, [r7, #4] + 8002d06: f7fe f9e5 bl 80010d4 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + 8002d0a: 6a3b ldr r3, [r7, #32] + 8002d0c: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002d10: 2b00 cmp r3, #0 + 8002d12: d00c beq.n 8002d2e + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + 8002d14: 693b ldr r3, [r7, #16] + 8002d16: f003 0310 and.w r3, r3, #16 + 8002d1a: 2b00 cmp r3, #0 + 8002d1c: d007 beq.n 8002d2e + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + 8002d1e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002d20: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8002d24: 627b str r3, [r7, #36] ; 0x24 + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + 8002d26: 687b ldr r3, [r7, #4] + 8002d28: 681b ldr r3, [r3, #0] + 8002d2a: 2210 movs r2, #16 + 8002d2c: 611a str r2, [r3, #16] + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + 8002d2e: 6a3b ldr r3, [r7, #32] + 8002d30: f003 0320 and.w r3, r3, #32 + 8002d34: 2b00 cmp r3, #0 + 8002d36: d00b beq.n 8002d50 + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + 8002d38: 693b ldr r3, [r7, #16] + 8002d3a: f003 0308 and.w r3, r3, #8 + 8002d3e: 2b00 cmp r3, #0 + 8002d40: d006 beq.n 8002d50 + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + 8002d42: 687b ldr r3, [r7, #4] + 8002d44: 681b ldr r3, [r3, #0] + 8002d46: 2208 movs r2, #8 + 8002d48: 611a str r2, [r3, #16] +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + 8002d4a: 6878 ldr r0, [r7, #4] + 8002d4c: f000 f912 bl 8002f74 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + 8002d50: 6a3b ldr r3, [r7, #32] + 8002d52: f003 0310 and.w r3, r3, #16 + 8002d56: 2b00 cmp r3, #0 + 8002d58: d009 beq.n 8002d6e + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + 8002d5a: 687b ldr r3, [r7, #4] + 8002d5c: 681b ldr r3, [r3, #0] + 8002d5e: 691b ldr r3, [r3, #16] + 8002d60: f003 0303 and.w r3, r3, #3 + 8002d64: 2b00 cmp r3, #0 + 8002d66: d002 beq.n 8002d6e +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + 8002d68: 6878 ldr r0, [r7, #4] + 8002d6a: f000 f8f9 bl 8002f60 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + 8002d6e: 6a3b ldr r3, [r7, #32] + 8002d70: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002d74: 2b00 cmp r3, #0 + 8002d76: d00b beq.n 8002d90 + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + 8002d78: 69fb ldr r3, [r7, #28] + 8002d7a: f003 0310 and.w r3, r3, #16 + 8002d7e: 2b00 cmp r3, #0 + 8002d80: d006 beq.n 8002d90 + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + 8002d82: 687b ldr r3, [r7, #4] + 8002d84: 681b ldr r3, [r3, #0] + 8002d86: 2210 movs r2, #16 + 8002d88: 605a str r2, [r3, #4] +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); + 8002d8a: 6878 ldr r0, [r7, #4] + 8002d8c: f000 f8fc bl 8002f88 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + 8002d90: 6a3b ldr r3, [r7, #32] + 8002d92: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8002d96: 2b00 cmp r3, #0 + 8002d98: d00b beq.n 8002db2 + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + 8002d9a: 69fb ldr r3, [r7, #28] + 8002d9c: f003 0308 and.w r3, r3, #8 + 8002da0: 2b00 cmp r3, #0 + 8002da2: d006 beq.n 8002db2 + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + 8002da4: 687b ldr r3, [r7, #4] + 8002da6: 681b ldr r3, [r3, #0] + 8002da8: 2208 movs r2, #8 + 8002daa: 605a str r2, [r3, #4] +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + 8002dac: 6878 ldr r0, [r7, #4] + 8002dae: f000 f8f5 bl 8002f9c +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + 8002db2: 6a3b ldr r3, [r7, #32] + 8002db4: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8002db8: 2b00 cmp r3, #0 + 8002dba: d07b beq.n 8002eb4 + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + 8002dbc: 69fb ldr r3, [r7, #28] + 8002dbe: f003 0304 and.w r3, r3, #4 + 8002dc2: 2b00 cmp r3, #0 + 8002dc4: d072 beq.n 8002eac + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + 8002dc6: 6a3b ldr r3, [r7, #32] + 8002dc8: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002dcc: 2b00 cmp r3, #0 + 8002dce: d008 beq.n 8002de2 + ((esrflags & CAN_ESR_EWGF) != 0U)) + 8002dd0: 68fb ldr r3, [r7, #12] + 8002dd2: f003 0301 and.w r3, r3, #1 + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + 8002dd6: 2b00 cmp r3, #0 + 8002dd8: d003 beq.n 8002de2 + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + 8002dda: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002ddc: f043 0301 orr.w r3, r3, #1 + 8002de0: 627b str r3, [r7, #36] ; 0x24 + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + 8002de2: 6a3b ldr r3, [r7, #32] + 8002de4: f403 7300 and.w r3, r3, #512 ; 0x200 + 8002de8: 2b00 cmp r3, #0 + 8002dea: d008 beq.n 8002dfe + ((esrflags & CAN_ESR_EPVF) != 0U)) + 8002dec: 68fb ldr r3, [r7, #12] + 8002dee: f003 0302 and.w r3, r3, #2 + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + 8002df2: 2b00 cmp r3, #0 + 8002df4: d003 beq.n 8002dfe + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + 8002df6: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002df8: f043 0302 orr.w r3, r3, #2 + 8002dfc: 627b str r3, [r7, #36] ; 0x24 + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + 8002dfe: 6a3b ldr r3, [r7, #32] + 8002e00: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8002e04: 2b00 cmp r3, #0 + 8002e06: d008 beq.n 8002e1a + ((esrflags & CAN_ESR_BOFF) != 0U)) + 8002e08: 68fb ldr r3, [r7, #12] + 8002e0a: f003 0304 and.w r3, r3, #4 + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + 8002e0e: 2b00 cmp r3, #0 + 8002e10: d003 beq.n 8002e1a + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + 8002e12: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002e14: f043 0304 orr.w r3, r3, #4 + 8002e18: 627b str r3, [r7, #36] ; 0x24 + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + 8002e1a: 6a3b ldr r3, [r7, #32] + 8002e1c: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8002e20: 2b00 cmp r3, #0 + 8002e22: d043 beq.n 8002eac + ((esrflags & CAN_ESR_LEC) != 0U)) + 8002e24: 68fb ldr r3, [r7, #12] + 8002e26: f003 0370 and.w r3, r3, #112 ; 0x70 + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + 8002e2a: 2b00 cmp r3, #0 + 8002e2c: d03e beq.n 8002eac + { + switch (esrflags & CAN_ESR_LEC) + 8002e2e: 68fb ldr r3, [r7, #12] + 8002e30: f003 0370 and.w r3, r3, #112 ; 0x70 + 8002e34: 2b60 cmp r3, #96 ; 0x60 + 8002e36: d02b beq.n 8002e90 + 8002e38: 2b60 cmp r3, #96 ; 0x60 + 8002e3a: d82e bhi.n 8002e9a + 8002e3c: 2b50 cmp r3, #80 ; 0x50 + 8002e3e: d022 beq.n 8002e86 + 8002e40: 2b50 cmp r3, #80 ; 0x50 + 8002e42: d82a bhi.n 8002e9a + 8002e44: 2b40 cmp r3, #64 ; 0x40 + 8002e46: d019 beq.n 8002e7c + 8002e48: 2b40 cmp r3, #64 ; 0x40 + 8002e4a: d826 bhi.n 8002e9a + 8002e4c: 2b30 cmp r3, #48 ; 0x30 + 8002e4e: d010 beq.n 8002e72 + 8002e50: 2b30 cmp r3, #48 ; 0x30 + 8002e52: d822 bhi.n 8002e9a + 8002e54: 2b10 cmp r3, #16 + 8002e56: d002 beq.n 8002e5e + 8002e58: 2b20 cmp r3, #32 + 8002e5a: d005 beq.n 8002e68 + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + 8002e5c: e01d b.n 8002e9a + errorcode |= HAL_CAN_ERROR_STF; + 8002e5e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002e60: f043 0308 orr.w r3, r3, #8 + 8002e64: 627b str r3, [r7, #36] ; 0x24 + break; + 8002e66: e019 b.n 8002e9c + errorcode |= HAL_CAN_ERROR_FOR; + 8002e68: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002e6a: f043 0310 orr.w r3, r3, #16 + 8002e6e: 627b str r3, [r7, #36] ; 0x24 + break; + 8002e70: e014 b.n 8002e9c + errorcode |= HAL_CAN_ERROR_ACK; + 8002e72: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002e74: f043 0320 orr.w r3, r3, #32 + 8002e78: 627b str r3, [r7, #36] ; 0x24 + break; + 8002e7a: e00f b.n 8002e9c + errorcode |= HAL_CAN_ERROR_BR; + 8002e7c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002e7e: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8002e82: 627b str r3, [r7, #36] ; 0x24 + break; + 8002e84: e00a b.n 8002e9c + errorcode |= HAL_CAN_ERROR_BD; + 8002e86: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002e88: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8002e8c: 627b str r3, [r7, #36] ; 0x24 + break; + 8002e8e: e005 b.n 8002e9c + errorcode |= HAL_CAN_ERROR_CRC; + 8002e90: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002e92: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002e96: 627b str r3, [r7, #36] ; 0x24 + break; + 8002e98: e000 b.n 8002e9c + break; + 8002e9a: bf00 nop + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + 8002e9c: 687b ldr r3, [r7, #4] + 8002e9e: 681b ldr r3, [r3, #0] + 8002ea0: 699a ldr r2, [r3, #24] + 8002ea2: 687b ldr r3, [r7, #4] + 8002ea4: 681b ldr r3, [r3, #0] + 8002ea6: f022 0270 bic.w r2, r2, #112 ; 0x70 + 8002eaa: 619a str r2, [r3, #24] + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + 8002eac: 687b ldr r3, [r7, #4] + 8002eae: 681b ldr r3, [r3, #0] + 8002eb0: 2204 movs r2, #4 + 8002eb2: 605a str r2, [r3, #4] + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + 8002eb4: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002eb6: 2b00 cmp r3, #0 + 8002eb8: d008 beq.n 8002ecc + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + 8002eba: 687b ldr r3, [r7, #4] + 8002ebc: 6a5a ldr r2, [r3, #36] ; 0x24 + 8002ebe: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002ec0: 431a orrs r2, r3 + 8002ec2: 687b ldr r3, [r7, #4] + 8002ec4: 625a str r2, [r3, #36] ; 0x24 +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); + 8002ec6: 6878 ldr r0, [r7, #4] + 8002ec8: f000 f872 bl 8002fb0 +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } +} + 8002ecc: bf00 nop + 8002ece: 3728 adds r7, #40 ; 0x28 + 8002ed0: 46bd mov sp, r7 + 8002ed2: bd80 pop {r7, pc} + +08002ed4 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 8002ed4: b480 push {r7} + 8002ed6: b083 sub sp, #12 + 8002ed8: af00 add r7, sp, #0 + 8002eda: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + 8002edc: bf00 nop + 8002ede: 370c adds r7, #12 + 8002ee0: 46bd mov sp, r7 + 8002ee2: f85d 7b04 ldr.w r7, [sp], #4 + 8002ee6: 4770 bx lr + +08002ee8 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 8002ee8: b480 push {r7} + 8002eea: b083 sub sp, #12 + 8002eec: af00 add r7, sp, #0 + 8002eee: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + 8002ef0: bf00 nop + 8002ef2: 370c adds r7, #12 + 8002ef4: 46bd mov sp, r7 + 8002ef6: f85d 7b04 ldr.w r7, [sp], #4 + 8002efa: 4770 bx lr + +08002efc : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + 8002efc: b480 push {r7} + 8002efe: b083 sub sp, #12 + 8002f00: af00 add r7, sp, #0 + 8002f02: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + 8002f04: bf00 nop + 8002f06: 370c adds r7, #12 + 8002f08: 46bd mov sp, r7 + 8002f0a: f85d 7b04 ldr.w r7, [sp], #4 + 8002f0e: 4770 bx lr + +08002f10 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + 8002f10: b480 push {r7} + 8002f12: b083 sub sp, #12 + 8002f14: af00 add r7, sp, #0 + 8002f16: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + 8002f18: bf00 nop + 8002f1a: 370c adds r7, #12 + 8002f1c: 46bd mov sp, r7 + 8002f1e: f85d 7b04 ldr.w r7, [sp], #4 + 8002f22: 4770 bx lr + +08002f24 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + 8002f24: b480 push {r7} + 8002f26: b083 sub sp, #12 + 8002f28: af00 add r7, sp, #0 + 8002f2a: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + 8002f2c: bf00 nop + 8002f2e: 370c adds r7, #12 + 8002f30: 46bd mov sp, r7 + 8002f32: f85d 7b04 ldr.w r7, [sp], #4 + 8002f36: 4770 bx lr + +08002f38 : + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + 8002f38: b480 push {r7} + 8002f3a: b083 sub sp, #12 + 8002f3c: af00 add r7, sp, #0 + 8002f3e: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + 8002f40: bf00 nop + 8002f42: 370c adds r7, #12 + 8002f44: 46bd mov sp, r7 + 8002f46: f85d 7b04 ldr.w r7, [sp], #4 + 8002f4a: 4770 bx lr + +08002f4c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + 8002f4c: b480 push {r7} + 8002f4e: b083 sub sp, #12 + 8002f50: af00 add r7, sp, #0 + 8002f52: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + 8002f54: bf00 nop + 8002f56: 370c adds r7, #12 + 8002f58: 46bd mov sp, r7 + 8002f5a: f85d 7b04 ldr.w r7, [sp], #4 + 8002f5e: 4770 bx lr + +08002f60 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + 8002f60: b480 push {r7} + 8002f62: b083 sub sp, #12 + 8002f64: af00 add r7, sp, #0 + 8002f66: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + 8002f68: bf00 nop + 8002f6a: 370c adds r7, #12 + 8002f6c: 46bd mov sp, r7 + 8002f6e: f85d 7b04 ldr.w r7, [sp], #4 + 8002f72: 4770 bx lr + +08002f74 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + 8002f74: b480 push {r7} + 8002f76: b083 sub sp, #12 + 8002f78: af00 add r7, sp, #0 + 8002f7a: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + 8002f7c: bf00 nop + 8002f7e: 370c adds r7, #12 + 8002f80: 46bd mov sp, r7 + 8002f82: f85d 7b04 ldr.w r7, [sp], #4 + 8002f86: 4770 bx lr + +08002f88 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + 8002f88: b480 push {r7} + 8002f8a: b083 sub sp, #12 + 8002f8c: af00 add r7, sp, #0 + 8002f8e: 6078 str r0, [r7, #4] + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + 8002f90: bf00 nop + 8002f92: 370c adds r7, #12 + 8002f94: 46bd mov sp, r7 + 8002f96: f85d 7b04 ldr.w r7, [sp], #4 + 8002f9a: 4770 bx lr + +08002f9c : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + 8002f9c: b480 push {r7} + 8002f9e: b083 sub sp, #12 + 8002fa0: af00 add r7, sp, #0 + 8002fa2: 6078 str r0, [r7, #4] + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + 8002fa4: bf00 nop + 8002fa6: 370c adds r7, #12 + 8002fa8: 46bd mov sp, r7 + 8002faa: f85d 7b04 ldr.w r7, [sp], #4 + 8002fae: 4770 bx lr + +08002fb0 : + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + 8002fb0: b480 push {r7} + 8002fb2: b083 sub sp, #12 + 8002fb4: af00 add r7, sp, #0 + 8002fb6: 6078 str r0, [r7, #4] + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + 8002fb8: bf00 nop + 8002fba: 370c adds r7, #12 + 8002fbc: 46bd mov sp, r7 + 8002fbe: f85d 7b04 ldr.w r7, [sp], #4 + 8002fc2: 4770 bx lr + +08002fc4 <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8002fc4: b480 push {r7} + 8002fc6: b085 sub sp, #20 + 8002fc8: af00 add r7, sp, #0 + 8002fca: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8002fcc: 687b ldr r3, [r7, #4] + 8002fce: f003 0307 and.w r3, r3, #7 + 8002fd2: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 8002fd4: 4b0c ldr r3, [pc, #48] ; (8003008 <__NVIC_SetPriorityGrouping+0x44>) + 8002fd6: 68db ldr r3, [r3, #12] + 8002fd8: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8002fda: 68ba ldr r2, [r7, #8] + 8002fdc: f64f 03ff movw r3, #63743 ; 0xf8ff + 8002fe0: 4013 ands r3, r2 + 8002fe2: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 8002fe4: 68fb ldr r3, [r7, #12] + 8002fe6: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8002fe8: 68bb ldr r3, [r7, #8] + 8002fea: 4313 orrs r3, r2 + reg_value = (reg_value | + 8002fec: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 8002ff0: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8002ff4: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 8002ff6: 4a04 ldr r2, [pc, #16] ; (8003008 <__NVIC_SetPriorityGrouping+0x44>) + 8002ff8: 68bb ldr r3, [r7, #8] + 8002ffa: 60d3 str r3, [r2, #12] +} + 8002ffc: bf00 nop + 8002ffe: 3714 adds r7, #20 + 8003000: 46bd mov sp, r7 + 8003002: f85d 7b04 ldr.w r7, [sp], #4 + 8003006: 4770 bx lr + 8003008: e000ed00 .word 0xe000ed00 + +0800300c <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 800300c: b480 push {r7} + 800300e: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8003010: 4b04 ldr r3, [pc, #16] ; (8003024 <__NVIC_GetPriorityGrouping+0x18>) + 8003012: 68db ldr r3, [r3, #12] + 8003014: 0a1b lsrs r3, r3, #8 + 8003016: f003 0307 and.w r3, r3, #7 +} + 800301a: 4618 mov r0, r3 + 800301c: 46bd mov sp, r7 + 800301e: f85d 7b04 ldr.w r7, [sp], #4 + 8003022: 4770 bx lr + 8003024: e000ed00 .word 0xe000ed00 + +08003028 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8003028: b480 push {r7} + 800302a: b083 sub sp, #12 + 800302c: af00 add r7, sp, #0 + 800302e: 4603 mov r3, r0 + 8003030: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8003032: f997 3007 ldrsb.w r3, [r7, #7] + 8003036: 2b00 cmp r3, #0 + 8003038: db0b blt.n 8003052 <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 800303a: 79fb ldrb r3, [r7, #7] + 800303c: f003 021f and.w r2, r3, #31 + 8003040: 4907 ldr r1, [pc, #28] ; (8003060 <__NVIC_EnableIRQ+0x38>) + 8003042: f997 3007 ldrsb.w r3, [r7, #7] + 8003046: 095b lsrs r3, r3, #5 + 8003048: 2001 movs r0, #1 + 800304a: fa00 f202 lsl.w r2, r0, r2 + 800304e: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 8003052: bf00 nop + 8003054: 370c adds r7, #12 + 8003056: 46bd mov sp, r7 + 8003058: f85d 7b04 ldr.w r7, [sp], #4 + 800305c: 4770 bx lr + 800305e: bf00 nop + 8003060: e000e100 .word 0xe000e100 + +08003064 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 8003064: b480 push {r7} + 8003066: b083 sub sp, #12 + 8003068: af00 add r7, sp, #0 + 800306a: 4603 mov r3, r0 + 800306c: 6039 str r1, [r7, #0] + 800306e: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 8003070: f997 3007 ldrsb.w r3, [r7, #7] + 8003074: 2b00 cmp r3, #0 + 8003076: db0a blt.n 800308e <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8003078: 683b ldr r3, [r7, #0] + 800307a: b2da uxtb r2, r3 + 800307c: 490c ldr r1, [pc, #48] ; (80030b0 <__NVIC_SetPriority+0x4c>) + 800307e: f997 3007 ldrsb.w r3, [r7, #7] + 8003082: 0112 lsls r2, r2, #4 + 8003084: b2d2 uxtb r2, r2 + 8003086: 440b add r3, r1 + 8003088: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 800308c: e00a b.n 80030a4 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 800308e: 683b ldr r3, [r7, #0] + 8003090: b2da uxtb r2, r3 + 8003092: 4908 ldr r1, [pc, #32] ; (80030b4 <__NVIC_SetPriority+0x50>) + 8003094: 79fb ldrb r3, [r7, #7] + 8003096: f003 030f and.w r3, r3, #15 + 800309a: 3b04 subs r3, #4 + 800309c: 0112 lsls r2, r2, #4 + 800309e: b2d2 uxtb r2, r2 + 80030a0: 440b add r3, r1 + 80030a2: 761a strb r2, [r3, #24] +} + 80030a4: bf00 nop + 80030a6: 370c adds r7, #12 + 80030a8: 46bd mov sp, r7 + 80030aa: f85d 7b04 ldr.w r7, [sp], #4 + 80030ae: 4770 bx lr + 80030b0: e000e100 .word 0xe000e100 + 80030b4: e000ed00 .word 0xe000ed00 + +080030b8 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80030b8: b480 push {r7} + 80030ba: b089 sub sp, #36 ; 0x24 + 80030bc: af00 add r7, sp, #0 + 80030be: 60f8 str r0, [r7, #12] + 80030c0: 60b9 str r1, [r7, #8] + 80030c2: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 80030c4: 68fb ldr r3, [r7, #12] + 80030c6: f003 0307 and.w r3, r3, #7 + 80030ca: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 80030cc: 69fb ldr r3, [r7, #28] + 80030ce: f1c3 0307 rsb r3, r3, #7 + 80030d2: 2b04 cmp r3, #4 + 80030d4: bf28 it cs + 80030d6: 2304 movcs r3, #4 + 80030d8: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 80030da: 69fb ldr r3, [r7, #28] + 80030dc: 3304 adds r3, #4 + 80030de: 2b06 cmp r3, #6 + 80030e0: d902 bls.n 80030e8 + 80030e2: 69fb ldr r3, [r7, #28] + 80030e4: 3b03 subs r3, #3 + 80030e6: e000 b.n 80030ea + 80030e8: 2300 movs r3, #0 + 80030ea: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 80030ec: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 80030f0: 69bb ldr r3, [r7, #24] + 80030f2: fa02 f303 lsl.w r3, r2, r3 + 80030f6: 43da mvns r2, r3 + 80030f8: 68bb ldr r3, [r7, #8] + 80030fa: 401a ands r2, r3 + 80030fc: 697b ldr r3, [r7, #20] + 80030fe: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8003100: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + 8003104: 697b ldr r3, [r7, #20] + 8003106: fa01 f303 lsl.w r3, r1, r3 + 800310a: 43d9 mvns r1, r3 + 800310c: 687b ldr r3, [r7, #4] + 800310e: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8003110: 4313 orrs r3, r2 + ); +} + 8003112: 4618 mov r0, r3 + 8003114: 3724 adds r7, #36 ; 0x24 + 8003116: 46bd mov sp, r7 + 8003118: f85d 7b04 ldr.w r7, [sp], #4 + 800311c: 4770 bx lr + ... + +08003120 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 8003120: b580 push {r7, lr} + 8003122: b082 sub sp, #8 + 8003124: af00 add r7, sp, #0 + 8003126: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8003128: 687b ldr r3, [r7, #4] + 800312a: 3b01 subs r3, #1 + 800312c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8003130: d301 bcc.n 8003136 + { + return (1UL); /* Reload value impossible */ + 8003132: 2301 movs r3, #1 + 8003134: e00f b.n 8003156 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8003136: 4a0a ldr r2, [pc, #40] ; (8003160 ) + 8003138: 687b ldr r3, [r7, #4] + 800313a: 3b01 subs r3, #1 + 800313c: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 800313e: 210f movs r1, #15 + 8003140: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 8003144: f7ff ff8e bl 8003064 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8003148: 4b05 ldr r3, [pc, #20] ; (8003160 ) + 800314a: 2200 movs r2, #0 + 800314c: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 800314e: 4b04 ldr r3, [pc, #16] ; (8003160 ) + 8003150: 2207 movs r2, #7 + 8003152: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8003154: 2300 movs r3, #0 +} + 8003156: 4618 mov r0, r3 + 8003158: 3708 adds r7, #8 + 800315a: 46bd mov sp, r7 + 800315c: bd80 pop {r7, pc} + 800315e: bf00 nop + 8003160: e000e010 .word 0xe000e010 + +08003164 : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 8003164: b580 push {r7, lr} + 8003166: b082 sub sp, #8 + 8003168: af00 add r7, sp, #0 + 800316a: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 800316c: 6878 ldr r0, [r7, #4] + 800316e: f7ff ff29 bl 8002fc4 <__NVIC_SetPriorityGrouping> +} + 8003172: bf00 nop + 8003174: 3708 adds r7, #8 + 8003176: 46bd mov sp, r7 + 8003178: bd80 pop {r7, pc} + +0800317a : + * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 800317a: b580 push {r7, lr} + 800317c: b086 sub sp, #24 + 800317e: af00 add r7, sp, #0 + 8003180: 4603 mov r3, r0 + 8003182: 60b9 str r1, [r7, #8] + 8003184: 607a str r2, [r7, #4] + 8003186: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00U; + 8003188: 2300 movs r3, #0 + 800318a: 617b str r3, [r7, #20] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 800318c: f7ff ff3e bl 800300c <__NVIC_GetPriorityGrouping> + 8003190: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8003192: 687a ldr r2, [r7, #4] + 8003194: 68b9 ldr r1, [r7, #8] + 8003196: 6978 ldr r0, [r7, #20] + 8003198: f7ff ff8e bl 80030b8 + 800319c: 4602 mov r2, r0 + 800319e: f997 300f ldrsb.w r3, [r7, #15] + 80031a2: 4611 mov r1, r2 + 80031a4: 4618 mov r0, r3 + 80031a6: f7ff ff5d bl 8003064 <__NVIC_SetPriority> +} + 80031aa: bf00 nop + 80031ac: 3718 adds r7, #24 + 80031ae: 46bd mov sp, r7 + 80031b0: bd80 pop {r7, pc} + +080031b2 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80031b2: b580 push {r7, lr} + 80031b4: b082 sub sp, #8 + 80031b6: af00 add r7, sp, #0 + 80031b8: 4603 mov r3, r0 + 80031ba: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 80031bc: f997 3007 ldrsb.w r3, [r7, #7] + 80031c0: 4618 mov r0, r3 + 80031c2: f7ff ff31 bl 8003028 <__NVIC_EnableIRQ> +} + 80031c6: bf00 nop + 80031c8: 3708 adds r7, #8 + 80031ca: 46bd mov sp, r7 + 80031cc: bd80 pop {r7, pc} + +080031ce : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 80031ce: b580 push {r7, lr} + 80031d0: b082 sub sp, #8 + 80031d2: af00 add r7, sp, #0 + 80031d4: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 80031d6: 6878 ldr r0, [r7, #4] + 80031d8: f7ff ffa2 bl 8003120 + 80031dc: 4603 mov r3, r0 +} + 80031de: 4618 mov r0, r3 + 80031e0: 3708 adds r7, #8 + 80031e2: 46bd mov sp, r7 + 80031e4: bd80 pop {r7, pc} + ... + +080031e8 : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 80031e8: b480 push {r7} + 80031ea: b087 sub sp, #28 + 80031ec: af00 add r7, sp, #0 + 80031ee: 6078 str r0, [r7, #4] + 80031f0: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 80031f2: 2300 movs r3, #0 + 80031f4: 617b str r3, [r7, #20] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80031f6: e154 b.n 80034a2 + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + 80031f8: 683b ldr r3, [r7, #0] + 80031fa: 681a ldr r2, [r3, #0] + 80031fc: 2101 movs r1, #1 + 80031fe: 697b ldr r3, [r7, #20] + 8003200: fa01 f303 lsl.w r3, r1, r3 + 8003204: 4013 ands r3, r2 + 8003206: 60fb str r3, [r7, #12] + + if (iocurrent != 0x00u) + 8003208: 68fb ldr r3, [r7, #12] + 800320a: 2b00 cmp r3, #0 + 800320c: f000 8146 beq.w 800349c + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8003210: 683b ldr r3, [r7, #0] + 8003212: 685b ldr r3, [r3, #4] + 8003214: f003 0303 and.w r3, r3, #3 + 8003218: 2b01 cmp r3, #1 + 800321a: d005 beq.n 8003228 + 800321c: 683b ldr r3, [r7, #0] + 800321e: 685b ldr r3, [r3, #4] + 8003220: f003 0303 and.w r3, r3, #3 + 8003224: 2b02 cmp r3, #2 + 8003226: d130 bne.n 800328a + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8003228: 687b ldr r3, [r7, #4] + 800322a: 689b ldr r3, [r3, #8] + 800322c: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + 800322e: 697b ldr r3, [r7, #20] + 8003230: 005b lsls r3, r3, #1 + 8003232: 2203 movs r2, #3 + 8003234: fa02 f303 lsl.w r3, r2, r3 + 8003238: 43db mvns r3, r3 + 800323a: 693a ldr r2, [r7, #16] + 800323c: 4013 ands r3, r2 + 800323e: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2u)); + 8003240: 683b ldr r3, [r7, #0] + 8003242: 68da ldr r2, [r3, #12] + 8003244: 697b ldr r3, [r7, #20] + 8003246: 005b lsls r3, r3, #1 + 8003248: fa02 f303 lsl.w r3, r2, r3 + 800324c: 693a ldr r2, [r7, #16] + 800324e: 4313 orrs r3, r2 + 8003250: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8003252: 687b ldr r3, [r7, #4] + 8003254: 693a ldr r2, [r7, #16] + 8003256: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8003258: 687b ldr r3, [r7, #4] + 800325a: 685b ldr r3, [r3, #4] + 800325c: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 800325e: 2201 movs r2, #1 + 8003260: 697b ldr r3, [r7, #20] + 8003262: fa02 f303 lsl.w r3, r2, r3 + 8003266: 43db mvns r3, r3 + 8003268: 693a ldr r2, [r7, #16] + 800326a: 4013 ands r3, r2 + 800326c: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 800326e: 683b ldr r3, [r7, #0] + 8003270: 685b ldr r3, [r3, #4] + 8003272: 091b lsrs r3, r3, #4 + 8003274: f003 0201 and.w r2, r3, #1 + 8003278: 697b ldr r3, [r7, #20] + 800327a: fa02 f303 lsl.w r3, r2, r3 + 800327e: 693a ldr r2, [r7, #16] + 8003280: 4313 orrs r3, r2 + 8003282: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8003284: 687b ldr r3, [r7, #4] + 8003286: 693a ldr r2, [r7, #16] + 8003288: 605a str r2, [r3, #4] + } + + if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 800328a: 683b ldr r3, [r7, #0] + 800328c: 685b ldr r3, [r3, #4] + 800328e: f003 0303 and.w r3, r3, #3 + 8003292: 2b03 cmp r3, #3 + 8003294: d017 beq.n 80032c6 + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8003296: 687b ldr r3, [r7, #4] + 8003298: 68db ldr r3, [r3, #12] + 800329a: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + 800329c: 697b ldr r3, [r7, #20] + 800329e: 005b lsls r3, r3, #1 + 80032a0: 2203 movs r2, #3 + 80032a2: fa02 f303 lsl.w r3, r2, r3 + 80032a6: 43db mvns r3, r3 + 80032a8: 693a ldr r2, [r7, #16] + 80032aa: 4013 ands r3, r2 + 80032ac: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2u)); + 80032ae: 683b ldr r3, [r7, #0] + 80032b0: 689a ldr r2, [r3, #8] + 80032b2: 697b ldr r3, [r7, #20] + 80032b4: 005b lsls r3, r3, #1 + 80032b6: fa02 f303 lsl.w r3, r2, r3 + 80032ba: 693a ldr r2, [r7, #16] + 80032bc: 4313 orrs r3, r2 + 80032be: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 80032c0: 687b ldr r3, [r7, #4] + 80032c2: 693a ldr r2, [r7, #16] + 80032c4: 60da str r2, [r3, #12] + } + + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 80032c6: 683b ldr r3, [r7, #0] + 80032c8: 685b ldr r3, [r3, #4] + 80032ca: f003 0303 and.w r3, r3, #3 + 80032ce: 2b02 cmp r3, #2 + 80032d0: d123 bne.n 800331a + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + 80032d2: 697b ldr r3, [r7, #20] + 80032d4: 08da lsrs r2, r3, #3 + 80032d6: 687b ldr r3, [r7, #4] + 80032d8: 3208 adds r2, #8 + 80032da: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80032de: 613b str r3, [r7, #16] + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + 80032e0: 697b ldr r3, [r7, #20] + 80032e2: f003 0307 and.w r3, r3, #7 + 80032e6: 009b lsls r3, r3, #2 + 80032e8: 220f movs r2, #15 + 80032ea: fa02 f303 lsl.w r3, r2, r3 + 80032ee: 43db mvns r3, r3 + 80032f0: 693a ldr r2, [r7, #16] + 80032f2: 4013 ands r3, r2 + 80032f4: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + 80032f6: 683b ldr r3, [r7, #0] + 80032f8: 691a ldr r2, [r3, #16] + 80032fa: 697b ldr r3, [r7, #20] + 80032fc: f003 0307 and.w r3, r3, #7 + 8003300: 009b lsls r3, r3, #2 + 8003302: fa02 f303 lsl.w r3, r2, r3 + 8003306: 693a ldr r2, [r7, #16] + 8003308: 4313 orrs r3, r2 + 800330a: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3u] = temp; + 800330c: 697b ldr r3, [r7, #20] + 800330e: 08da lsrs r2, r3, #3 + 8003310: 687b ldr r3, [r7, #4] + 8003312: 3208 adds r2, #8 + 8003314: 6939 ldr r1, [r7, #16] + 8003316: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 800331a: 687b ldr r3, [r7, #4] + 800331c: 681b ldr r3, [r3, #0] + 800331e: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); + 8003320: 697b ldr r3, [r7, #20] + 8003322: 005b lsls r3, r3, #1 + 8003324: 2203 movs r2, #3 + 8003326: fa02 f303 lsl.w r3, r2, r3 + 800332a: 43db mvns r3, r3 + 800332c: 693a ldr r2, [r7, #16] + 800332e: 4013 ands r3, r2 + 8003330: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 8003332: 683b ldr r3, [r7, #0] + 8003334: 685b ldr r3, [r3, #4] + 8003336: f003 0203 and.w r2, r3, #3 + 800333a: 697b ldr r3, [r7, #20] + 800333c: 005b lsls r3, r3, #1 + 800333e: fa02 f303 lsl.w r3, r2, r3 + 8003342: 693a ldr r2, [r7, #16] + 8003344: 4313 orrs r3, r2 + 8003346: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8003348: 687b ldr r3, [r7, #4] + 800334a: 693a ldr r2, [r7, #16] + 800334c: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 800334e: 683b ldr r3, [r7, #0] + 8003350: 685b ldr r3, [r3, #4] + 8003352: f403 3340 and.w r3, r3, #196608 ; 0x30000 + 8003356: 2b00 cmp r3, #0 + 8003358: f000 80a0 beq.w 800349c + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800335c: 4b58 ldr r3, [pc, #352] ; (80034c0 ) + 800335e: 699b ldr r3, [r3, #24] + 8003360: 4a57 ldr r2, [pc, #348] ; (80034c0 ) + 8003362: f043 0301 orr.w r3, r3, #1 + 8003366: 6193 str r3, [r2, #24] + 8003368: 4b55 ldr r3, [pc, #340] ; (80034c0 ) + 800336a: 699b ldr r3, [r3, #24] + 800336c: f003 0301 and.w r3, r3, #1 + 8003370: 60bb str r3, [r7, #8] + 8003372: 68bb ldr r3, [r7, #8] + + temp = SYSCFG->EXTICR[position >> 2u]; + 8003374: 4a53 ldr r2, [pc, #332] ; (80034c4 ) + 8003376: 697b ldr r3, [r7, #20] + 8003378: 089b lsrs r3, r3, #2 + 800337a: 3302 adds r3, #2 + 800337c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003380: 613b str r3, [r7, #16] + temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 8003382: 697b ldr r3, [r7, #20] + 8003384: f003 0303 and.w r3, r3, #3 + 8003388: 009b lsls r3, r3, #2 + 800338a: 220f movs r2, #15 + 800338c: fa02 f303 lsl.w r3, r2, r3 + 8003390: 43db mvns r3, r3 + 8003392: 693a ldr r2, [r7, #16] + 8003394: 4013 ands r3, r2 + 8003396: 613b str r3, [r7, #16] + temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 8003398: 687b ldr r3, [r7, #4] + 800339a: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 + 800339e: d019 beq.n 80033d4 + 80033a0: 687b ldr r3, [r7, #4] + 80033a2: 4a49 ldr r2, [pc, #292] ; (80034c8 ) + 80033a4: 4293 cmp r3, r2 + 80033a6: d013 beq.n 80033d0 + 80033a8: 687b ldr r3, [r7, #4] + 80033aa: 4a48 ldr r2, [pc, #288] ; (80034cc ) + 80033ac: 4293 cmp r3, r2 + 80033ae: d00d beq.n 80033cc + 80033b0: 687b ldr r3, [r7, #4] + 80033b2: 4a47 ldr r2, [pc, #284] ; (80034d0 ) + 80033b4: 4293 cmp r3, r2 + 80033b6: d007 beq.n 80033c8 + 80033b8: 687b ldr r3, [r7, #4] + 80033ba: 4a46 ldr r2, [pc, #280] ; (80034d4 ) + 80033bc: 4293 cmp r3, r2 + 80033be: d101 bne.n 80033c4 + 80033c0: 2304 movs r3, #4 + 80033c2: e008 b.n 80033d6 + 80033c4: 2305 movs r3, #5 + 80033c6: e006 b.n 80033d6 + 80033c8: 2303 movs r3, #3 + 80033ca: e004 b.n 80033d6 + 80033cc: 2302 movs r3, #2 + 80033ce: e002 b.n 80033d6 + 80033d0: 2301 movs r3, #1 + 80033d2: e000 b.n 80033d6 + 80033d4: 2300 movs r3, #0 + 80033d6: 697a ldr r2, [r7, #20] + 80033d8: f002 0203 and.w r2, r2, #3 + 80033dc: 0092 lsls r2, r2, #2 + 80033de: 4093 lsls r3, r2 + 80033e0: 693a ldr r2, [r7, #16] + 80033e2: 4313 orrs r3, r2 + 80033e4: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2u] = temp; + 80033e6: 4937 ldr r1, [pc, #220] ; (80034c4 ) + 80033e8: 697b ldr r3, [r7, #20] + 80033ea: 089b lsrs r3, r3, #2 + 80033ec: 3302 adds r3, #2 + 80033ee: 693a ldr r2, [r7, #16] + 80033f0: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + 80033f4: 4b38 ldr r3, [pc, #224] ; (80034d8 ) + 80033f6: 681b ldr r3, [r3, #0] + 80033f8: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 80033fa: 68fb ldr r3, [r7, #12] + 80033fc: 43db mvns r3, r3 + 80033fe: 693a ldr r2, [r7, #16] + 8003400: 4013 ands r3, r2 + 8003402: 613b str r3, [r7, #16] + if((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 8003404: 683b ldr r3, [r7, #0] + 8003406: 685b ldr r3, [r3, #4] + 8003408: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800340c: 2b00 cmp r3, #0 + 800340e: d003 beq.n 8003418 + { + temp |= iocurrent; + 8003410: 693a ldr r2, [r7, #16] + 8003412: 68fb ldr r3, [r7, #12] + 8003414: 4313 orrs r3, r2 + 8003416: 613b str r3, [r7, #16] + } + EXTI->IMR = temp; + 8003418: 4a2f ldr r2, [pc, #188] ; (80034d8 ) + 800341a: 693b ldr r3, [r7, #16] + 800341c: 6013 str r3, [r2, #0] + + temp = EXTI->EMR; + 800341e: 4b2e ldr r3, [pc, #184] ; (80034d8 ) + 8003420: 685b ldr r3, [r3, #4] + 8003422: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8003424: 68fb ldr r3, [r7, #12] + 8003426: 43db mvns r3, r3 + 8003428: 693a ldr r2, [r7, #16] + 800342a: 4013 ands r3, r2 + 800342c: 613b str r3, [r7, #16] + if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 800342e: 683b ldr r3, [r7, #0] + 8003430: 685b ldr r3, [r3, #4] + 8003432: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8003436: 2b00 cmp r3, #0 + 8003438: d003 beq.n 8003442 + { + temp |= iocurrent; + 800343a: 693a ldr r2, [r7, #16] + 800343c: 68fb ldr r3, [r7, #12] + 800343e: 4313 orrs r3, r2 + 8003440: 613b str r3, [r7, #16] + } + EXTI->EMR = temp; + 8003442: 4a25 ldr r2, [pc, #148] ; (80034d8 ) + 8003444: 693b ldr r3, [r7, #16] + 8003446: 6053 str r3, [r2, #4] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + 8003448: 4b23 ldr r3, [pc, #140] ; (80034d8 ) + 800344a: 689b ldr r3, [r3, #8] + 800344c: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 800344e: 68fb ldr r3, [r7, #12] + 8003450: 43db mvns r3, r3 + 8003452: 693a ldr r2, [r7, #16] + 8003454: 4013 ands r3, r2 + 8003456: 613b str r3, [r7, #16] + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 8003458: 683b ldr r3, [r7, #0] + 800345a: 685b ldr r3, [r3, #4] + 800345c: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8003460: 2b00 cmp r3, #0 + 8003462: d003 beq.n 800346c + { + temp |= iocurrent; + 8003464: 693a ldr r2, [r7, #16] + 8003466: 68fb ldr r3, [r7, #12] + 8003468: 4313 orrs r3, r2 + 800346a: 613b str r3, [r7, #16] + } + EXTI->RTSR = temp; + 800346c: 4a1a ldr r2, [pc, #104] ; (80034d8 ) + 800346e: 693b ldr r3, [r7, #16] + 8003470: 6093 str r3, [r2, #8] + + temp = EXTI->FTSR; + 8003472: 4b19 ldr r3, [pc, #100] ; (80034d8 ) + 8003474: 68db ldr r3, [r3, #12] + 8003476: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8003478: 68fb ldr r3, [r7, #12] + 800347a: 43db mvns r3, r3 + 800347c: 693a ldr r2, [r7, #16] + 800347e: 4013 ands r3, r2 + 8003480: 613b str r3, [r7, #16] + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 8003482: 683b ldr r3, [r7, #0] + 8003484: 685b ldr r3, [r3, #4] + 8003486: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800348a: 2b00 cmp r3, #0 + 800348c: d003 beq.n 8003496 + { + temp |= iocurrent; + 800348e: 693a ldr r2, [r7, #16] + 8003490: 68fb ldr r3, [r7, #12] + 8003492: 4313 orrs r3, r2 + 8003494: 613b str r3, [r7, #16] + } + EXTI->FTSR = temp; + 8003496: 4a10 ldr r2, [pc, #64] ; (80034d8 ) + 8003498: 693b ldr r3, [r7, #16] + 800349a: 60d3 str r3, [r2, #12] + } + } + + position++; + 800349c: 697b ldr r3, [r7, #20] + 800349e: 3301 adds r3, #1 + 80034a0: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0x00u) + 80034a2: 683b ldr r3, [r7, #0] + 80034a4: 681a ldr r2, [r3, #0] + 80034a6: 697b ldr r3, [r7, #20] + 80034a8: fa22 f303 lsr.w r3, r2, r3 + 80034ac: 2b00 cmp r3, #0 + 80034ae: f47f aea3 bne.w 80031f8 + } +} + 80034b2: bf00 nop + 80034b4: bf00 nop + 80034b6: 371c adds r7, #28 + 80034b8: 46bd mov sp, r7 + 80034ba: f85d 7b04 ldr.w r7, [sp], #4 + 80034be: 4770 bx lr + 80034c0: 40021000 .word 0x40021000 + 80034c4: 40010000 .word 0x40010000 + 80034c8: 48000400 .word 0x48000400 + 80034cc: 48000800 .word 0x48000800 + 80034d0: 48000c00 .word 0x48000c00 + 80034d4: 48001000 .word 0x48001000 + 80034d8: 40010400 .word 0x40010400 + +080034dc : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80034dc: b480 push {r7} + 80034de: b083 sub sp, #12 + 80034e0: af00 add r7, sp, #0 + 80034e2: 6078 str r0, [r7, #4] + 80034e4: 460b mov r3, r1 + 80034e6: 807b strh r3, [r7, #2] + 80034e8: 4613 mov r3, r2 + 80034ea: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + 80034ec: 787b ldrb r3, [r7, #1] + 80034ee: 2b00 cmp r3, #0 + 80034f0: d003 beq.n 80034fa + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 80034f2: 887a ldrh r2, [r7, #2] + 80034f4: 687b ldr r3, [r7, #4] + 80034f6: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 80034f8: e002 b.n 8003500 + GPIOx->BRR = (uint32_t)GPIO_Pin; + 80034fa: 887a ldrh r2, [r7, #2] + 80034fc: 687b ldr r3, [r7, #4] + 80034fe: 629a str r2, [r3, #40] ; 0x28 +} + 8003500: bf00 nop + 8003502: 370c adds r7, #12 + 8003504: 46bd mov sp, r7 + 8003506: f85d 7b04 ldr.w r7, [sp], #4 + 800350a: 4770 bx lr + +0800350c : + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + 800350c: b580 push {r7, lr} + 800350e: b082 sub sp, #8 + 8003510: af00 add r7, sp, #0 + 8003512: 6078 str r0, [r7, #4] + /* Check the I2C handle allocation */ + if (hi2c == NULL) + 8003514: 687b ldr r3, [r7, #4] + 8003516: 2b00 cmp r3, #0 + 8003518: d101 bne.n 800351e + { + return HAL_ERROR; + 800351a: 2301 movs r3, #1 + 800351c: e081 b.n 8003622 + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + 800351e: 687b ldr r3, [r7, #4] + 8003520: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8003524: b2db uxtb r3, r3 + 8003526: 2b00 cmp r3, #0 + 8003528: d106 bne.n 8003538 + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + 800352a: 687b ldr r3, [r7, #4] + 800352c: 2200 movs r2, #0 + 800352e: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); + 8003532: 6878 ldr r0, [r7, #4] + 8003534: f7fe fcf6 bl 8001f24 +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + 8003538: 687b ldr r3, [r7, #4] + 800353a: 2224 movs r2, #36 ; 0x24 + 800353c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8003540: 687b ldr r3, [r7, #4] + 8003542: 681b ldr r3, [r3, #0] + 8003544: 681a ldr r2, [r3, #0] + 8003546: 687b ldr r3, [r7, #4] + 8003548: 681b ldr r3, [r3, #0] + 800354a: f022 0201 bic.w r2, r2, #1 + 800354e: 601a str r2, [r3, #0] + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 8003550: 687b ldr r3, [r7, #4] + 8003552: 685a ldr r2, [r3, #4] + 8003554: 687b ldr r3, [r7, #4] + 8003556: 681b ldr r3, [r3, #0] + 8003558: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 + 800355c: 611a str r2, [r3, #16] + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 800355e: 687b ldr r3, [r7, #4] + 8003560: 681b ldr r3, [r3, #0] + 8003562: 689a ldr r2, [r3, #8] + 8003564: 687b ldr r3, [r7, #4] + 8003566: 681b ldr r3, [r3, #0] + 8003568: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 800356c: 609a str r2, [r3, #8] + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 800356e: 687b ldr r3, [r7, #4] + 8003570: 68db ldr r3, [r3, #12] + 8003572: 2b01 cmp r3, #1 + 8003574: d107 bne.n 8003586 + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 8003576: 687b ldr r3, [r7, #4] + 8003578: 689a ldr r2, [r3, #8] + 800357a: 687b ldr r3, [r7, #4] + 800357c: 681b ldr r3, [r3, #0] + 800357e: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 8003582: 609a str r2, [r3, #8] + 8003584: e006 b.n 8003594 + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 8003586: 687b ldr r3, [r7, #4] + 8003588: 689a ldr r2, [r3, #8] + 800358a: 687b ldr r3, [r7, #4] + 800358c: 681b ldr r3, [r3, #0] + 800358e: f442 4204 orr.w r2, r2, #33792 ; 0x8400 + 8003592: 609a str r2, [r3, #8] + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 8003594: 687b ldr r3, [r7, #4] + 8003596: 68db ldr r3, [r3, #12] + 8003598: 2b02 cmp r3, #2 + 800359a: d104 bne.n 80035a6 + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + 800359c: 687b ldr r3, [r7, #4] + 800359e: 681b ldr r3, [r3, #0] + 80035a0: f44f 6200 mov.w r2, #2048 ; 0x800 + 80035a4: 605a str r2, [r3, #4] + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 80035a6: 687b ldr r3, [r7, #4] + 80035a8: 681b ldr r3, [r3, #0] + 80035aa: 685b ldr r3, [r3, #4] + 80035ac: 687a ldr r2, [r7, #4] + 80035ae: 6812 ldr r2, [r2, #0] + 80035b0: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000 + 80035b4: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80035b8: 6053 str r3, [r2, #4] + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 80035ba: 687b ldr r3, [r7, #4] + 80035bc: 681b ldr r3, [r3, #0] + 80035be: 68da ldr r2, [r3, #12] + 80035c0: 687b ldr r3, [r7, #4] + 80035c2: 681b ldr r3, [r3, #0] + 80035c4: f422 4200 bic.w r2, r2, #32768 ; 0x8000 + 80035c8: 60da str r2, [r3, #12] + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 80035ca: 687b ldr r3, [r7, #4] + 80035cc: 691a ldr r2, [r3, #16] + 80035ce: 687b ldr r3, [r7, #4] + 80035d0: 695b ldr r3, [r3, #20] + 80035d2: ea42 0103 orr.w r1, r2, r3 + (hi2c->Init.OwnAddress2Masks << 8)); + 80035d6: 687b ldr r3, [r7, #4] + 80035d8: 699b ldr r3, [r3, #24] + 80035da: 021a lsls r2, r3, #8 + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 80035dc: 687b ldr r3, [r7, #4] + 80035de: 681b ldr r3, [r3, #0] + 80035e0: 430a orrs r2, r1 + 80035e2: 60da str r2, [r3, #12] + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 80035e4: 687b ldr r3, [r7, #4] + 80035e6: 69d9 ldr r1, [r3, #28] + 80035e8: 687b ldr r3, [r7, #4] + 80035ea: 6a1a ldr r2, [r3, #32] + 80035ec: 687b ldr r3, [r7, #4] + 80035ee: 681b ldr r3, [r3, #0] + 80035f0: 430a orrs r2, r1 + 80035f2: 601a str r2, [r3, #0] + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + 80035f4: 687b ldr r3, [r7, #4] + 80035f6: 681b ldr r3, [r3, #0] + 80035f8: 681a ldr r2, [r3, #0] + 80035fa: 687b ldr r3, [r7, #4] + 80035fc: 681b ldr r3, [r3, #0] + 80035fe: f042 0201 orr.w r2, r2, #1 + 8003602: 601a str r2, [r3, #0] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8003604: 687b ldr r3, [r7, #4] + 8003606: 2200 movs r2, #0 + 8003608: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 800360a: 687b ldr r3, [r7, #4] + 800360c: 2220 movs r2, #32 + 800360e: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->PreviousState = I2C_STATE_NONE; + 8003612: 687b ldr r3, [r7, #4] + 8003614: 2200 movs r2, #0 + 8003616: 631a str r2, [r3, #48] ; 0x30 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8003618: 687b ldr r3, [r7, #4] + 800361a: 2200 movs r2, #0 + 800361c: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + return HAL_OK; + 8003620: 2300 movs r3, #0 +} + 8003622: 4618 mov r0, r3 + 8003624: 3708 adds r7, #8 + 8003626: 46bd mov sp, r7 + 8003628: bd80 pop {r7, pc} + ... + +0800362c : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + 800362c: b580 push {r7, lr} + 800362e: b088 sub sp, #32 + 8003630: af02 add r7, sp, #8 + 8003632: 60f8 str r0, [r7, #12] + 8003634: 607a str r2, [r7, #4] + 8003636: 461a mov r2, r3 + 8003638: 460b mov r3, r1 + 800363a: 817b strh r3, [r7, #10] + 800363c: 4613 mov r3, r2 + 800363e: 813b strh r3, [r7, #8] + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + 8003640: 68fb ldr r3, [r7, #12] + 8003642: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8003646: b2db uxtb r3, r3 + 8003648: 2b20 cmp r3, #32 + 800364a: f040 80da bne.w 8003802 + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 800364e: 68fb ldr r3, [r7, #12] + 8003650: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8003654: 2b01 cmp r3, #1 + 8003656: d101 bne.n 800365c + 8003658: 2302 movs r3, #2 + 800365a: e0d3 b.n 8003804 + 800365c: 68fb ldr r3, [r7, #12] + 800365e: 2201 movs r2, #1 + 8003660: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8003664: f7fe fdfe bl 8002264 + 8003668: 6178 str r0, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 800366a: 697b ldr r3, [r7, #20] + 800366c: 9300 str r3, [sp, #0] + 800366e: 2319 movs r3, #25 + 8003670: 2201 movs r2, #1 + 8003672: f44f 4100 mov.w r1, #32768 ; 0x8000 + 8003676: 68f8 ldr r0, [r7, #12] + 8003678: f000 fcbc bl 8003ff4 + 800367c: 4603 mov r3, r0 + 800367e: 2b00 cmp r3, #0 + 8003680: d001 beq.n 8003686 + { + return HAL_ERROR; + 8003682: 2301 movs r3, #1 + 8003684: e0be b.n 8003804 + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + 8003686: 68fb ldr r3, [r7, #12] + 8003688: 2221 movs r2, #33 ; 0x21 + 800368a: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_MASTER; + 800368e: 68fb ldr r3, [r7, #12] + 8003690: 2210 movs r2, #16 + 8003692: f883 2042 strb.w r2, [r3, #66] ; 0x42 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8003696: 68fb ldr r3, [r7, #12] + 8003698: 2200 movs r2, #0 + 800369a: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 800369c: 68fb ldr r3, [r7, #12] + 800369e: 687a ldr r2, [r7, #4] + 80036a0: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 80036a2: 68fb ldr r3, [r7, #12] + 80036a4: 893a ldrh r2, [r7, #8] + 80036a6: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 80036a8: 68fb ldr r3, [r7, #12] + 80036aa: 2200 movs r2, #0 + 80036ac: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 80036ae: 68fb ldr r3, [r7, #12] + 80036b0: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80036b2: b29b uxth r3, r3 + 80036b4: 2bff cmp r3, #255 ; 0xff + 80036b6: d90e bls.n 80036d6 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 80036b8: 68fb ldr r3, [r7, #12] + 80036ba: 22ff movs r2, #255 ; 0xff + 80036bc: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 80036be: 68fb ldr r3, [r7, #12] + 80036c0: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80036c2: b2da uxtb r2, r3 + 80036c4: 8979 ldrh r1, [r7, #10] + 80036c6: 4b51 ldr r3, [pc, #324] ; (800380c ) + 80036c8: 9300 str r3, [sp, #0] + 80036ca: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 80036ce: 68f8 ldr r0, [r7, #12] + 80036d0: f000 fe2e bl 8004330 + 80036d4: e06c b.n 80037b0 + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 80036d6: 68fb ldr r3, [r7, #12] + 80036d8: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80036da: b29a uxth r2, r3 + 80036dc: 68fb ldr r3, [r7, #12] + 80036de: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 80036e0: 68fb ldr r3, [r7, #12] + 80036e2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80036e4: b2da uxtb r2, r3 + 80036e6: 8979 ldrh r1, [r7, #10] + 80036e8: 4b48 ldr r3, [pc, #288] ; (800380c ) + 80036ea: 9300 str r3, [sp, #0] + 80036ec: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 80036f0: 68f8 ldr r0, [r7, #12] + 80036f2: f000 fe1d bl 8004330 + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + 80036f6: e05b b.n 80037b0 + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 80036f8: 697a ldr r2, [r7, #20] + 80036fa: 6a39 ldr r1, [r7, #32] + 80036fc: 68f8 ldr r0, [r7, #12] + 80036fe: f000 fcb9 bl 8004074 + 8003702: 4603 mov r3, r0 + 8003704: 2b00 cmp r3, #0 + 8003706: d001 beq.n 800370c + { + return HAL_ERROR; + 8003708: 2301 movs r3, #1 + 800370a: e07b b.n 8003804 + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 800370c: 68fb ldr r3, [r7, #12] + 800370e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003710: 781a ldrb r2, [r3, #0] + 8003712: 68fb ldr r3, [r7, #12] + 8003714: 681b ldr r3, [r3, #0] + 8003716: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8003718: 68fb ldr r3, [r7, #12] + 800371a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800371c: 1c5a adds r2, r3, #1 + 800371e: 68fb ldr r3, [r7, #12] + 8003720: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferCount--; + 8003722: 68fb ldr r3, [r7, #12] + 8003724: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003726: b29b uxth r3, r3 + 8003728: 3b01 subs r3, #1 + 800372a: b29a uxth r2, r3 + 800372c: 68fb ldr r3, [r7, #12] + 800372e: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 8003730: 68fb ldr r3, [r7, #12] + 8003732: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003734: 3b01 subs r3, #1 + 8003736: b29a uxth r2, r3 + 8003738: 68fb ldr r3, [r7, #12] + 800373a: 851a strh r2, [r3, #40] ; 0x28 + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 800373c: 68fb ldr r3, [r7, #12] + 800373e: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003740: b29b uxth r3, r3 + 8003742: 2b00 cmp r3, #0 + 8003744: d034 beq.n 80037b0 + 8003746: 68fb ldr r3, [r7, #12] + 8003748: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800374a: 2b00 cmp r3, #0 + 800374c: d130 bne.n 80037b0 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 800374e: 697b ldr r3, [r7, #20] + 8003750: 9300 str r3, [sp, #0] + 8003752: 6a3b ldr r3, [r7, #32] + 8003754: 2200 movs r2, #0 + 8003756: 2180 movs r1, #128 ; 0x80 + 8003758: 68f8 ldr r0, [r7, #12] + 800375a: f000 fc4b bl 8003ff4 + 800375e: 4603 mov r3, r0 + 8003760: 2b00 cmp r3, #0 + 8003762: d001 beq.n 8003768 + { + return HAL_ERROR; + 8003764: 2301 movs r3, #1 + 8003766: e04d b.n 8003804 + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8003768: 68fb ldr r3, [r7, #12] + 800376a: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800376c: b29b uxth r3, r3 + 800376e: 2bff cmp r3, #255 ; 0xff + 8003770: d90e bls.n 8003790 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8003772: 68fb ldr r3, [r7, #12] + 8003774: 22ff movs r2, #255 ; 0xff + 8003776: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8003778: 68fb ldr r3, [r7, #12] + 800377a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800377c: b2da uxtb r2, r3 + 800377e: 8979 ldrh r1, [r7, #10] + 8003780: 2300 movs r3, #0 + 8003782: 9300 str r3, [sp, #0] + 8003784: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8003788: 68f8 ldr r0, [r7, #12] + 800378a: f000 fdd1 bl 8004330 + 800378e: e00f b.n 80037b0 + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8003790: 68fb ldr r3, [r7, #12] + 8003792: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003794: b29a uxth r2, r3 + 8003796: 68fb ldr r3, [r7, #12] + 8003798: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 800379a: 68fb ldr r3, [r7, #12] + 800379c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800379e: b2da uxtb r2, r3 + 80037a0: 8979 ldrh r1, [r7, #10] + 80037a2: 2300 movs r3, #0 + 80037a4: 9300 str r3, [sp, #0] + 80037a6: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 80037aa: 68f8 ldr r0, [r7, #12] + 80037ac: f000 fdc0 bl 8004330 + while (hi2c->XferCount > 0U) + 80037b0: 68fb ldr r3, [r7, #12] + 80037b2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80037b4: b29b uxth r3, r3 + 80037b6: 2b00 cmp r3, #0 + 80037b8: d19e bne.n 80036f8 + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 80037ba: 697a ldr r2, [r7, #20] + 80037bc: 6a39 ldr r1, [r7, #32] + 80037be: 68f8 ldr r0, [r7, #12] + 80037c0: f000 fc98 bl 80040f4 + 80037c4: 4603 mov r3, r0 + 80037c6: 2b00 cmp r3, #0 + 80037c8: d001 beq.n 80037ce + { + return HAL_ERROR; + 80037ca: 2301 movs r3, #1 + 80037cc: e01a b.n 8003804 + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 80037ce: 68fb ldr r3, [r7, #12] + 80037d0: 681b ldr r3, [r3, #0] + 80037d2: 2220 movs r2, #32 + 80037d4: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 80037d6: 68fb ldr r3, [r7, #12] + 80037d8: 681b ldr r3, [r3, #0] + 80037da: 6859 ldr r1, [r3, #4] + 80037dc: 68fb ldr r3, [r7, #12] + 80037de: 681a ldr r2, [r3, #0] + 80037e0: 4b0b ldr r3, [pc, #44] ; (8003810 ) + 80037e2: 400b ands r3, r1 + 80037e4: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 80037e6: 68fb ldr r3, [r7, #12] + 80037e8: 2220 movs r2, #32 + 80037ea: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80037ee: 68fb ldr r3, [r7, #12] + 80037f0: 2200 movs r2, #0 + 80037f2: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80037f6: 68fb ldr r3, [r7, #12] + 80037f8: 2200 movs r2, #0 + 80037fa: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 80037fe: 2300 movs r3, #0 + 8003800: e000 b.n 8003804 + } + else + { + return HAL_BUSY; + 8003802: 2302 movs r3, #2 + } +} + 8003804: 4618 mov r0, r3 + 8003806: 3718 adds r7, #24 + 8003808: 46bd mov sp, r7 + 800380a: bd80 pop {r7, pc} + 800380c: 80002000 .word 0x80002000 + 8003810: fe00e800 .word 0xfe00e800 + +08003814 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + 8003814: b580 push {r7, lr} + 8003816: b088 sub sp, #32 + 8003818: af02 add r7, sp, #8 + 800381a: 60f8 str r0, [r7, #12] + 800381c: 607a str r2, [r7, #4] + 800381e: 461a mov r2, r3 + 8003820: 460b mov r3, r1 + 8003822: 817b strh r3, [r7, #10] + 8003824: 4613 mov r3, r2 + 8003826: 813b strh r3, [r7, #8] + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + 8003828: 68fb ldr r3, [r7, #12] + 800382a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 800382e: b2db uxtb r3, r3 + 8003830: 2b20 cmp r3, #32 + 8003832: f040 80db bne.w 80039ec + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8003836: 68fb ldr r3, [r7, #12] + 8003838: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 800383c: 2b01 cmp r3, #1 + 800383e: d101 bne.n 8003844 + 8003840: 2302 movs r3, #2 + 8003842: e0d4 b.n 80039ee + 8003844: 68fb ldr r3, [r7, #12] + 8003846: 2201 movs r2, #1 + 8003848: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 800384c: f7fe fd0a bl 8002264 + 8003850: 6178 str r0, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 8003852: 697b ldr r3, [r7, #20] + 8003854: 9300 str r3, [sp, #0] + 8003856: 2319 movs r3, #25 + 8003858: 2201 movs r2, #1 + 800385a: f44f 4100 mov.w r1, #32768 ; 0x8000 + 800385e: 68f8 ldr r0, [r7, #12] + 8003860: f000 fbc8 bl 8003ff4 + 8003864: 4603 mov r3, r0 + 8003866: 2b00 cmp r3, #0 + 8003868: d001 beq.n 800386e + { + return HAL_ERROR; + 800386a: 2301 movs r3, #1 + 800386c: e0bf b.n 80039ee + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + 800386e: 68fb ldr r3, [r7, #12] + 8003870: 2222 movs r2, #34 ; 0x22 + 8003872: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_MASTER; + 8003876: 68fb ldr r3, [r7, #12] + 8003878: 2210 movs r2, #16 + 800387a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 800387e: 68fb ldr r3, [r7, #12] + 8003880: 2200 movs r2, #0 + 8003882: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 8003884: 68fb ldr r3, [r7, #12] + 8003886: 687a ldr r2, [r7, #4] + 8003888: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 800388a: 68fb ldr r3, [r7, #12] + 800388c: 893a ldrh r2, [r7, #8] + 800388e: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 8003890: 68fb ldr r3, [r7, #12] + 8003892: 2200 movs r2, #0 + 8003894: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8003896: 68fb ldr r3, [r7, #12] + 8003898: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800389a: b29b uxth r3, r3 + 800389c: 2bff cmp r3, #255 ; 0xff + 800389e: d90e bls.n 80038be + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 80038a0: 68fb ldr r3, [r7, #12] + 80038a2: 22ff movs r2, #255 ; 0xff + 80038a4: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 80038a6: 68fb ldr r3, [r7, #12] + 80038a8: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80038aa: b2da uxtb r2, r3 + 80038ac: 8979 ldrh r1, [r7, #10] + 80038ae: 4b52 ldr r3, [pc, #328] ; (80039f8 ) + 80038b0: 9300 str r3, [sp, #0] + 80038b2: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 80038b6: 68f8 ldr r0, [r7, #12] + 80038b8: f000 fd3a bl 8004330 + 80038bc: e06d b.n 800399a + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 80038be: 68fb ldr r3, [r7, #12] + 80038c0: 8d5b ldrh r3, [r3, #42] ; 0x2a + 80038c2: b29a uxth r2, r3 + 80038c4: 68fb ldr r3, [r7, #12] + 80038c6: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 80038c8: 68fb ldr r3, [r7, #12] + 80038ca: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80038cc: b2da uxtb r2, r3 + 80038ce: 8979 ldrh r1, [r7, #10] + 80038d0: 4b49 ldr r3, [pc, #292] ; (80039f8 ) + 80038d2: 9300 str r3, [sp, #0] + 80038d4: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 80038d8: 68f8 ldr r0, [r7, #12] + 80038da: f000 fd29 bl 8004330 + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + 80038de: e05c b.n 800399a + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 80038e0: 697a ldr r2, [r7, #20] + 80038e2: 6a39 ldr r1, [r7, #32] + 80038e4: 68f8 ldr r0, [r7, #12] + 80038e6: f000 fc41 bl 800416c + 80038ea: 4603 mov r3, r0 + 80038ec: 2b00 cmp r3, #0 + 80038ee: d001 beq.n 80038f4 + { + return HAL_ERROR; + 80038f0: 2301 movs r3, #1 + 80038f2: e07c b.n 80039ee + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 80038f4: 68fb ldr r3, [r7, #12] + 80038f6: 681b ldr r3, [r3, #0] + 80038f8: 6a5a ldr r2, [r3, #36] ; 0x24 + 80038fa: 68fb ldr r3, [r7, #12] + 80038fc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80038fe: b2d2 uxtb r2, r2 + 8003900: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8003902: 68fb ldr r3, [r7, #12] + 8003904: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003906: 1c5a adds r2, r3, #1 + 8003908: 68fb ldr r3, [r7, #12] + 800390a: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferSize--; + 800390c: 68fb ldr r3, [r7, #12] + 800390e: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003910: 3b01 subs r3, #1 + 8003912: b29a uxth r2, r3 + 8003914: 68fb ldr r3, [r7, #12] + 8003916: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8003918: 68fb ldr r3, [r7, #12] + 800391a: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800391c: b29b uxth r3, r3 + 800391e: 3b01 subs r3, #1 + 8003920: b29a uxth r2, r3 + 8003922: 68fb ldr r3, [r7, #12] + 8003924: 855a strh r2, [r3, #42] ; 0x2a + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8003926: 68fb ldr r3, [r7, #12] + 8003928: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800392a: b29b uxth r3, r3 + 800392c: 2b00 cmp r3, #0 + 800392e: d034 beq.n 800399a + 8003930: 68fb ldr r3, [r7, #12] + 8003932: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003934: 2b00 cmp r3, #0 + 8003936: d130 bne.n 800399a + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 8003938: 697b ldr r3, [r7, #20] + 800393a: 9300 str r3, [sp, #0] + 800393c: 6a3b ldr r3, [r7, #32] + 800393e: 2200 movs r2, #0 + 8003940: 2180 movs r1, #128 ; 0x80 + 8003942: 68f8 ldr r0, [r7, #12] + 8003944: f000 fb56 bl 8003ff4 + 8003948: 4603 mov r3, r0 + 800394a: 2b00 cmp r3, #0 + 800394c: d001 beq.n 8003952 + { + return HAL_ERROR; + 800394e: 2301 movs r3, #1 + 8003950: e04d b.n 80039ee + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8003952: 68fb ldr r3, [r7, #12] + 8003954: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003956: b29b uxth r3, r3 + 8003958: 2bff cmp r3, #255 ; 0xff + 800395a: d90e bls.n 800397a + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 800395c: 68fb ldr r3, [r7, #12] + 800395e: 22ff movs r2, #255 ; 0xff + 8003960: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8003962: 68fb ldr r3, [r7, #12] + 8003964: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003966: b2da uxtb r2, r3 + 8003968: 8979 ldrh r1, [r7, #10] + 800396a: 2300 movs r3, #0 + 800396c: 9300 str r3, [sp, #0] + 800396e: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8003972: 68f8 ldr r0, [r7, #12] + 8003974: f000 fcdc bl 8004330 + 8003978: e00f b.n 800399a + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 800397a: 68fb ldr r3, [r7, #12] + 800397c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800397e: b29a uxth r2, r3 + 8003980: 68fb ldr r3, [r7, #12] + 8003982: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8003984: 68fb ldr r3, [r7, #12] + 8003986: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003988: b2da uxtb r2, r3 + 800398a: 8979 ldrh r1, [r7, #10] + 800398c: 2300 movs r3, #0 + 800398e: 9300 str r3, [sp, #0] + 8003990: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8003994: 68f8 ldr r0, [r7, #12] + 8003996: f000 fccb bl 8004330 + while (hi2c->XferCount > 0U) + 800399a: 68fb ldr r3, [r7, #12] + 800399c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800399e: b29b uxth r3, r3 + 80039a0: 2b00 cmp r3, #0 + 80039a2: d19d bne.n 80038e0 + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 80039a4: 697a ldr r2, [r7, #20] + 80039a6: 6a39 ldr r1, [r7, #32] + 80039a8: 68f8 ldr r0, [r7, #12] + 80039aa: f000 fba3 bl 80040f4 + 80039ae: 4603 mov r3, r0 + 80039b0: 2b00 cmp r3, #0 + 80039b2: d001 beq.n 80039b8 + { + return HAL_ERROR; + 80039b4: 2301 movs r3, #1 + 80039b6: e01a b.n 80039ee + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 80039b8: 68fb ldr r3, [r7, #12] + 80039ba: 681b ldr r3, [r3, #0] + 80039bc: 2220 movs r2, #32 + 80039be: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 80039c0: 68fb ldr r3, [r7, #12] + 80039c2: 681b ldr r3, [r3, #0] + 80039c4: 6859 ldr r1, [r3, #4] + 80039c6: 68fb ldr r3, [r7, #12] + 80039c8: 681a ldr r2, [r3, #0] + 80039ca: 4b0c ldr r3, [pc, #48] ; (80039fc ) + 80039cc: 400b ands r3, r1 + 80039ce: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 80039d0: 68fb ldr r3, [r7, #12] + 80039d2: 2220 movs r2, #32 + 80039d4: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80039d8: 68fb ldr r3, [r7, #12] + 80039da: 2200 movs r2, #0 + 80039dc: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80039e0: 68fb ldr r3, [r7, #12] + 80039e2: 2200 movs r2, #0 + 80039e4: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 80039e8: 2300 movs r3, #0 + 80039ea: e000 b.n 80039ee + } + else + { + return HAL_BUSY; + 80039ec: 2302 movs r3, #2 + } +} + 80039ee: 4618 mov r0, r3 + 80039f0: 3718 adds r7, #24 + 80039f2: 46bd mov sp, r7 + 80039f4: bd80 pop {r7, pc} + 80039f6: bf00 nop + 80039f8: 80002400 .word 0x80002400 + 80039fc: fe00e800 .word 0xfe00e800 + +08003a00 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8003a00: b580 push {r7, lr} + 8003a02: b088 sub sp, #32 + 8003a04: af02 add r7, sp, #8 + 8003a06: 60f8 str r0, [r7, #12] + 8003a08: 4608 mov r0, r1 + 8003a0a: 4611 mov r1, r2 + 8003a0c: 461a mov r2, r3 + 8003a0e: 4603 mov r3, r0 + 8003a10: 817b strh r3, [r7, #10] + 8003a12: 460b mov r3, r1 + 8003a14: 813b strh r3, [r7, #8] + 8003a16: 4613 mov r3, r2 + 8003a18: 80fb strh r3, [r7, #6] + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 8003a1a: 68fb ldr r3, [r7, #12] + 8003a1c: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8003a20: b2db uxtb r3, r3 + 8003a22: 2b20 cmp r3, #32 + 8003a24: f040 80f9 bne.w 8003c1a + { + if ((pData == NULL) || (Size == 0U)) + 8003a28: 6a3b ldr r3, [r7, #32] + 8003a2a: 2b00 cmp r3, #0 + 8003a2c: d002 beq.n 8003a34 + 8003a2e: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8003a30: 2b00 cmp r3, #0 + 8003a32: d105 bne.n 8003a40 + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 8003a34: 68fb ldr r3, [r7, #12] + 8003a36: f44f 7200 mov.w r2, #512 ; 0x200 + 8003a3a: 645a str r2, [r3, #68] ; 0x44 + return HAL_ERROR; + 8003a3c: 2301 movs r3, #1 + 8003a3e: e0ed b.n 8003c1c + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + 8003a40: 68fb ldr r3, [r7, #12] + 8003a42: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8003a46: 2b01 cmp r3, #1 + 8003a48: d101 bne.n 8003a4e + 8003a4a: 2302 movs r3, #2 + 8003a4c: e0e6 b.n 8003c1c + 8003a4e: 68fb ldr r3, [r7, #12] + 8003a50: 2201 movs r2, #1 + 8003a52: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8003a56: f7fe fc05 bl 8002264 + 8003a5a: 6178 str r0, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 8003a5c: 697b ldr r3, [r7, #20] + 8003a5e: 9300 str r3, [sp, #0] + 8003a60: 2319 movs r3, #25 + 8003a62: 2201 movs r2, #1 + 8003a64: f44f 4100 mov.w r1, #32768 ; 0x8000 + 8003a68: 68f8 ldr r0, [r7, #12] + 8003a6a: f000 fac3 bl 8003ff4 + 8003a6e: 4603 mov r3, r0 + 8003a70: 2b00 cmp r3, #0 + 8003a72: d001 beq.n 8003a78 + { + return HAL_ERROR; + 8003a74: 2301 movs r3, #1 + 8003a76: e0d1 b.n 8003c1c + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + 8003a78: 68fb ldr r3, [r7, #12] + 8003a7a: 2221 movs r2, #33 ; 0x21 + 8003a7c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_MEM; + 8003a80: 68fb ldr r3, [r7, #12] + 8003a82: 2240 movs r2, #64 ; 0x40 + 8003a84: f883 2042 strb.w r2, [r3, #66] ; 0x42 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8003a88: 68fb ldr r3, [r7, #12] + 8003a8a: 2200 movs r2, #0 + 8003a8c: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 8003a8e: 68fb ldr r3, [r7, #12] + 8003a90: 6a3a ldr r2, [r7, #32] + 8003a92: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 8003a94: 68fb ldr r3, [r7, #12] + 8003a96: 8cba ldrh r2, [r7, #36] ; 0x24 + 8003a98: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 8003a9a: 68fb ldr r3, [r7, #12] + 8003a9c: 2200 movs r2, #0 + 8003a9e: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + 8003aa0: 88f8 ldrh r0, [r7, #6] + 8003aa2: 893a ldrh r2, [r7, #8] + 8003aa4: 8979 ldrh r1, [r7, #10] + 8003aa6: 697b ldr r3, [r7, #20] + 8003aa8: 9301 str r3, [sp, #4] + 8003aaa: 6abb ldr r3, [r7, #40] ; 0x28 + 8003aac: 9300 str r3, [sp, #0] + 8003aae: 4603 mov r3, r0 + 8003ab0: 68f8 ldr r0, [r7, #12] + 8003ab2: f000 f9d3 bl 8003e5c + 8003ab6: 4603 mov r3, r0 + 8003ab8: 2b00 cmp r3, #0 + 8003aba: d005 beq.n 8003ac8 + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003abc: 68fb ldr r3, [r7, #12] + 8003abe: 2200 movs r2, #0 + 8003ac0: f883 2040 strb.w r2, [r3, #64] ; 0x40 + return HAL_ERROR; + 8003ac4: 2301 movs r3, #1 + 8003ac6: e0a9 b.n 8003c1c + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8003ac8: 68fb ldr r3, [r7, #12] + 8003aca: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003acc: b29b uxth r3, r3 + 8003ace: 2bff cmp r3, #255 ; 0xff + 8003ad0: d90e bls.n 8003af0 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8003ad2: 68fb ldr r3, [r7, #12] + 8003ad4: 22ff movs r2, #255 ; 0xff + 8003ad6: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + 8003ad8: 68fb ldr r3, [r7, #12] + 8003ada: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003adc: b2da uxtb r2, r3 + 8003ade: 8979 ldrh r1, [r7, #10] + 8003ae0: 2300 movs r3, #0 + 8003ae2: 9300 str r3, [sp, #0] + 8003ae4: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8003ae8: 68f8 ldr r0, [r7, #12] + 8003aea: f000 fc21 bl 8004330 + 8003aee: e00f b.n 8003b10 + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8003af0: 68fb ldr r3, [r7, #12] + 8003af2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003af4: b29a uxth r2, r3 + 8003af6: 68fb ldr r3, [r7, #12] + 8003af8: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 8003afa: 68fb ldr r3, [r7, #12] + 8003afc: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003afe: b2da uxtb r2, r3 + 8003b00: 8979 ldrh r1, [r7, #10] + 8003b02: 2300 movs r3, #0 + 8003b04: 9300 str r3, [sp, #0] + 8003b06: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8003b0a: 68f8 ldr r0, [r7, #12] + 8003b0c: f000 fc10 bl 8004330 + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8003b10: 697a ldr r2, [r7, #20] + 8003b12: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8003b14: 68f8 ldr r0, [r7, #12] + 8003b16: f000 faad bl 8004074 + 8003b1a: 4603 mov r3, r0 + 8003b1c: 2b00 cmp r3, #0 + 8003b1e: d001 beq.n 8003b24 + { + return HAL_ERROR; + 8003b20: 2301 movs r3, #1 + 8003b22: e07b b.n 8003c1c + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 8003b24: 68fb ldr r3, [r7, #12] + 8003b26: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003b28: 781a ldrb r2, [r3, #0] + 8003b2a: 68fb ldr r3, [r7, #12] + 8003b2c: 681b ldr r3, [r3, #0] + 8003b2e: 629a str r2, [r3, #40] ; 0x28 + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8003b30: 68fb ldr r3, [r7, #12] + 8003b32: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003b34: 1c5a adds r2, r3, #1 + 8003b36: 68fb ldr r3, [r7, #12] + 8003b38: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferCount--; + 8003b3a: 68fb ldr r3, [r7, #12] + 8003b3c: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003b3e: b29b uxth r3, r3 + 8003b40: 3b01 subs r3, #1 + 8003b42: b29a uxth r2, r3 + 8003b44: 68fb ldr r3, [r7, #12] + 8003b46: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferSize--; + 8003b48: 68fb ldr r3, [r7, #12] + 8003b4a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003b4c: 3b01 subs r3, #1 + 8003b4e: b29a uxth r2, r3 + 8003b50: 68fb ldr r3, [r7, #12] + 8003b52: 851a strh r2, [r3, #40] ; 0x28 + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8003b54: 68fb ldr r3, [r7, #12] + 8003b56: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003b58: b29b uxth r3, r3 + 8003b5a: 2b00 cmp r3, #0 + 8003b5c: d034 beq.n 8003bc8 + 8003b5e: 68fb ldr r3, [r7, #12] + 8003b60: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003b62: 2b00 cmp r3, #0 + 8003b64: d130 bne.n 8003bc8 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 8003b66: 697b ldr r3, [r7, #20] + 8003b68: 9300 str r3, [sp, #0] + 8003b6a: 6abb ldr r3, [r7, #40] ; 0x28 + 8003b6c: 2200 movs r2, #0 + 8003b6e: 2180 movs r1, #128 ; 0x80 + 8003b70: 68f8 ldr r0, [r7, #12] + 8003b72: f000 fa3f bl 8003ff4 + 8003b76: 4603 mov r3, r0 + 8003b78: 2b00 cmp r3, #0 + 8003b7a: d001 beq.n 8003b80 + { + return HAL_ERROR; + 8003b7c: 2301 movs r3, #1 + 8003b7e: e04d b.n 8003c1c + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8003b80: 68fb ldr r3, [r7, #12] + 8003b82: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003b84: b29b uxth r3, r3 + 8003b86: 2bff cmp r3, #255 ; 0xff + 8003b88: d90e bls.n 8003ba8 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8003b8a: 68fb ldr r3, [r7, #12] + 8003b8c: 22ff movs r2, #255 ; 0xff + 8003b8e: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8003b90: 68fb ldr r3, [r7, #12] + 8003b92: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003b94: b2da uxtb r2, r3 + 8003b96: 8979 ldrh r1, [r7, #10] + 8003b98: 2300 movs r3, #0 + 8003b9a: 9300 str r3, [sp, #0] + 8003b9c: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8003ba0: 68f8 ldr r0, [r7, #12] + 8003ba2: f000 fbc5 bl 8004330 + 8003ba6: e00f b.n 8003bc8 + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8003ba8: 68fb ldr r3, [r7, #12] + 8003baa: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003bac: b29a uxth r2, r3 + 8003bae: 68fb ldr r3, [r7, #12] + 8003bb0: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8003bb2: 68fb ldr r3, [r7, #12] + 8003bb4: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003bb6: b2da uxtb r2, r3 + 8003bb8: 8979 ldrh r1, [r7, #10] + 8003bba: 2300 movs r3, #0 + 8003bbc: 9300 str r3, [sp, #0] + 8003bbe: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8003bc2: 68f8 ldr r0, [r7, #12] + 8003bc4: f000 fbb4 bl 8004330 + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + 8003bc8: 68fb ldr r3, [r7, #12] + 8003bca: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003bcc: b29b uxth r3, r3 + 8003bce: 2b00 cmp r3, #0 + 8003bd0: d19e bne.n 8003b10 + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8003bd2: 697a ldr r2, [r7, #20] + 8003bd4: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8003bd6: 68f8 ldr r0, [r7, #12] + 8003bd8: f000 fa8c bl 80040f4 + 8003bdc: 4603 mov r3, r0 + 8003bde: 2b00 cmp r3, #0 + 8003be0: d001 beq.n 8003be6 + { + return HAL_ERROR; + 8003be2: 2301 movs r3, #1 + 8003be4: e01a b.n 8003c1c + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8003be6: 68fb ldr r3, [r7, #12] + 8003be8: 681b ldr r3, [r3, #0] + 8003bea: 2220 movs r2, #32 + 8003bec: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8003bee: 68fb ldr r3, [r7, #12] + 8003bf0: 681b ldr r3, [r3, #0] + 8003bf2: 6859 ldr r1, [r3, #4] + 8003bf4: 68fb ldr r3, [r7, #12] + 8003bf6: 681a ldr r2, [r3, #0] + 8003bf8: 4b0a ldr r3, [pc, #40] ; (8003c24 ) + 8003bfa: 400b ands r3, r1 + 8003bfc: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 8003bfe: 68fb ldr r3, [r7, #12] + 8003c00: 2220 movs r2, #32 + 8003c02: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8003c06: 68fb ldr r3, [r7, #12] + 8003c08: 2200 movs r2, #0 + 8003c0a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003c0e: 68fb ldr r3, [r7, #12] + 8003c10: 2200 movs r2, #0 + 8003c12: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8003c16: 2300 movs r3, #0 + 8003c18: e000 b.n 8003c1c + } + else + { + return HAL_BUSY; + 8003c1a: 2302 movs r3, #2 + } +} + 8003c1c: 4618 mov r0, r3 + 8003c1e: 3718 adds r7, #24 + 8003c20: 46bd mov sp, r7 + 8003c22: bd80 pop {r7, pc} + 8003c24: fe00e800 .word 0xfe00e800 + +08003c28 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8003c28: b580 push {r7, lr} + 8003c2a: b088 sub sp, #32 + 8003c2c: af02 add r7, sp, #8 + 8003c2e: 60f8 str r0, [r7, #12] + 8003c30: 4608 mov r0, r1 + 8003c32: 4611 mov r1, r2 + 8003c34: 461a mov r2, r3 + 8003c36: 4603 mov r3, r0 + 8003c38: 817b strh r3, [r7, #10] + 8003c3a: 460b mov r3, r1 + 8003c3c: 813b strh r3, [r7, #8] + 8003c3e: 4613 mov r3, r2 + 8003c40: 80fb strh r3, [r7, #6] + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 8003c42: 68fb ldr r3, [r7, #12] + 8003c44: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8003c48: b2db uxtb r3, r3 + 8003c4a: 2b20 cmp r3, #32 + 8003c4c: f040 80fd bne.w 8003e4a + { + if ((pData == NULL) || (Size == 0U)) + 8003c50: 6a3b ldr r3, [r7, #32] + 8003c52: 2b00 cmp r3, #0 + 8003c54: d002 beq.n 8003c5c + 8003c56: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8003c58: 2b00 cmp r3, #0 + 8003c5a: d105 bne.n 8003c68 + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 8003c5c: 68fb ldr r3, [r7, #12] + 8003c5e: f44f 7200 mov.w r2, #512 ; 0x200 + 8003c62: 645a str r2, [r3, #68] ; 0x44 + return HAL_ERROR; + 8003c64: 2301 movs r3, #1 + 8003c66: e0f1 b.n 8003e4c + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + 8003c68: 68fb ldr r3, [r7, #12] + 8003c6a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 8003c6e: 2b01 cmp r3, #1 + 8003c70: d101 bne.n 8003c76 + 8003c72: 2302 movs r3, #2 + 8003c74: e0ea b.n 8003e4c + 8003c76: 68fb ldr r3, [r7, #12] + 8003c78: 2201 movs r2, #1 + 8003c7a: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8003c7e: f7fe faf1 bl 8002264 + 8003c82: 6178 str r0, [r7, #20] + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + 8003c84: 697b ldr r3, [r7, #20] + 8003c86: 9300 str r3, [sp, #0] + 8003c88: 2319 movs r3, #25 + 8003c8a: 2201 movs r2, #1 + 8003c8c: f44f 4100 mov.w r1, #32768 ; 0x8000 + 8003c90: 68f8 ldr r0, [r7, #12] + 8003c92: f000 f9af bl 8003ff4 + 8003c96: 4603 mov r3, r0 + 8003c98: 2b00 cmp r3, #0 + 8003c9a: d001 beq.n 8003ca0 + { + return HAL_ERROR; + 8003c9c: 2301 movs r3, #1 + 8003c9e: e0d5 b.n 8003e4c + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + 8003ca0: 68fb ldr r3, [r7, #12] + 8003ca2: 2222 movs r2, #34 ; 0x22 + 8003ca4: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_MEM; + 8003ca8: 68fb ldr r3, [r7, #12] + 8003caa: 2240 movs r2, #64 ; 0x40 + 8003cac: f883 2042 strb.w r2, [r3, #66] ; 0x42 + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8003cb0: 68fb ldr r3, [r7, #12] + 8003cb2: 2200 movs r2, #0 + 8003cb4: 645a str r2, [r3, #68] ; 0x44 + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + 8003cb6: 68fb ldr r3, [r7, #12] + 8003cb8: 6a3a ldr r2, [r7, #32] + 8003cba: 625a str r2, [r3, #36] ; 0x24 + hi2c->XferCount = Size; + 8003cbc: 68fb ldr r3, [r7, #12] + 8003cbe: 8cba ldrh r2, [r7, #36] ; 0x24 + 8003cc0: 855a strh r2, [r3, #42] ; 0x2a + hi2c->XferISR = NULL; + 8003cc2: 68fb ldr r3, [r7, #12] + 8003cc4: 2200 movs r2, #0 + 8003cc6: 635a str r2, [r3, #52] ; 0x34 + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + 8003cc8: 88f8 ldrh r0, [r7, #6] + 8003cca: 893a ldrh r2, [r7, #8] + 8003ccc: 8979 ldrh r1, [r7, #10] + 8003cce: 697b ldr r3, [r7, #20] + 8003cd0: 9301 str r3, [sp, #4] + 8003cd2: 6abb ldr r3, [r7, #40] ; 0x28 + 8003cd4: 9300 str r3, [sp, #0] + 8003cd6: 4603 mov r3, r0 + 8003cd8: 68f8 ldr r0, [r7, #12] + 8003cda: f000 f913 bl 8003f04 + 8003cde: 4603 mov r3, r0 + 8003ce0: 2b00 cmp r3, #0 + 8003ce2: d005 beq.n 8003cf0 + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003ce4: 68fb ldr r3, [r7, #12] + 8003ce6: 2200 movs r2, #0 + 8003ce8: f883 2040 strb.w r2, [r3, #64] ; 0x40 + return HAL_ERROR; + 8003cec: 2301 movs r3, #1 + 8003cee: e0ad b.n 8003e4c + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8003cf0: 68fb ldr r3, [r7, #12] + 8003cf2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003cf4: b29b uxth r3, r3 + 8003cf6: 2bff cmp r3, #255 ; 0xff + 8003cf8: d90e bls.n 8003d18 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8003cfa: 68fb ldr r3, [r7, #12] + 8003cfc: 22ff movs r2, #255 ; 0xff + 8003cfe: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 8003d00: 68fb ldr r3, [r7, #12] + 8003d02: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003d04: b2da uxtb r2, r3 + 8003d06: 8979 ldrh r1, [r7, #10] + 8003d08: 4b52 ldr r3, [pc, #328] ; (8003e54 ) + 8003d0a: 9300 str r3, [sp, #0] + 8003d0c: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8003d10: 68f8 ldr r0, [r7, #12] + 8003d12: f000 fb0d bl 8004330 + 8003d16: e00f b.n 8003d38 + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8003d18: 68fb ldr r3, [r7, #12] + 8003d1a: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003d1c: b29a uxth r2, r3 + 8003d1e: 68fb ldr r3, [r7, #12] + 8003d20: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8003d22: 68fb ldr r3, [r7, #12] + 8003d24: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003d26: b2da uxtb r2, r3 + 8003d28: 8979 ldrh r1, [r7, #10] + 8003d2a: 4b4a ldr r3, [pc, #296] ; (8003e54 ) + 8003d2c: 9300 str r3, [sp, #0] + 8003d2e: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8003d32: 68f8 ldr r0, [r7, #12] + 8003d34: f000 fafc bl 8004330 + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + 8003d38: 697b ldr r3, [r7, #20] + 8003d3a: 9300 str r3, [sp, #0] + 8003d3c: 6abb ldr r3, [r7, #40] ; 0x28 + 8003d3e: 2200 movs r2, #0 + 8003d40: 2104 movs r1, #4 + 8003d42: 68f8 ldr r0, [r7, #12] + 8003d44: f000 f956 bl 8003ff4 + 8003d48: 4603 mov r3, r0 + 8003d4a: 2b00 cmp r3, #0 + 8003d4c: d001 beq.n 8003d52 + { + return HAL_ERROR; + 8003d4e: 2301 movs r3, #1 + 8003d50: e07c b.n 8003e4c + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 8003d52: 68fb ldr r3, [r7, #12] + 8003d54: 681b ldr r3, [r3, #0] + 8003d56: 6a5a ldr r2, [r3, #36] ; 0x24 + 8003d58: 68fb ldr r3, [r7, #12] + 8003d5a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003d5c: b2d2 uxtb r2, r2 + 8003d5e: 701a strb r2, [r3, #0] + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + 8003d60: 68fb ldr r3, [r7, #12] + 8003d62: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003d64: 1c5a adds r2, r3, #1 + 8003d66: 68fb ldr r3, [r7, #12] + 8003d68: 625a str r2, [r3, #36] ; 0x24 + + hi2c->XferSize--; + 8003d6a: 68fb ldr r3, [r7, #12] + 8003d6c: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003d6e: 3b01 subs r3, #1 + 8003d70: b29a uxth r2, r3 + 8003d72: 68fb ldr r3, [r7, #12] + 8003d74: 851a strh r2, [r3, #40] ; 0x28 + hi2c->XferCount--; + 8003d76: 68fb ldr r3, [r7, #12] + 8003d78: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003d7a: b29b uxth r3, r3 + 8003d7c: 3b01 subs r3, #1 + 8003d7e: b29a uxth r2, r3 + 8003d80: 68fb ldr r3, [r7, #12] + 8003d82: 855a strh r2, [r3, #42] ; 0x2a + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 8003d84: 68fb ldr r3, [r7, #12] + 8003d86: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003d88: b29b uxth r3, r3 + 8003d8a: 2b00 cmp r3, #0 + 8003d8c: d034 beq.n 8003df8 + 8003d8e: 68fb ldr r3, [r7, #12] + 8003d90: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003d92: 2b00 cmp r3, #0 + 8003d94: d130 bne.n 8003df8 + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 8003d96: 697b ldr r3, [r7, #20] + 8003d98: 9300 str r3, [sp, #0] + 8003d9a: 6abb ldr r3, [r7, #40] ; 0x28 + 8003d9c: 2200 movs r2, #0 + 8003d9e: 2180 movs r1, #128 ; 0x80 + 8003da0: 68f8 ldr r0, [r7, #12] + 8003da2: f000 f927 bl 8003ff4 + 8003da6: 4603 mov r3, r0 + 8003da8: 2b00 cmp r3, #0 + 8003daa: d001 beq.n 8003db0 + { + return HAL_ERROR; + 8003dac: 2301 movs r3, #1 + 8003dae: e04d b.n 8003e4c + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + 8003db0: 68fb ldr r3, [r7, #12] + 8003db2: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003db4: b29b uxth r3, r3 + 8003db6: 2bff cmp r3, #255 ; 0xff + 8003db8: d90e bls.n 8003dd8 + { + hi2c->XferSize = MAX_NBYTE_SIZE; + 8003dba: 68fb ldr r3, [r7, #12] + 8003dbc: 22ff movs r2, #255 ; 0xff + 8003dbe: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + 8003dc0: 68fb ldr r3, [r7, #12] + 8003dc2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003dc4: b2da uxtb r2, r3 + 8003dc6: 8979 ldrh r1, [r7, #10] + 8003dc8: 2300 movs r3, #0 + 8003dca: 9300 str r3, [sp, #0] + 8003dcc: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8003dd0: 68f8 ldr r0, [r7, #12] + 8003dd2: f000 faad bl 8004330 + 8003dd6: e00f b.n 8003df8 + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + 8003dd8: 68fb ldr r3, [r7, #12] + 8003dda: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003ddc: b29a uxth r2, r3 + 8003dde: 68fb ldr r3, [r7, #12] + 8003de0: 851a strh r2, [r3, #40] ; 0x28 + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 8003de2: 68fb ldr r3, [r7, #12] + 8003de4: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8003de6: b2da uxtb r2, r3 + 8003de8: 8979 ldrh r1, [r7, #10] + 8003dea: 2300 movs r3, #0 + 8003dec: 9300 str r3, [sp, #0] + 8003dee: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8003df2: 68f8 ldr r0, [r7, #12] + 8003df4: f000 fa9c bl 8004330 + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + 8003df8: 68fb ldr r3, [r7, #12] + 8003dfa: 8d5b ldrh r3, [r3, #42] ; 0x2a + 8003dfc: b29b uxth r3, r3 + 8003dfe: 2b00 cmp r3, #0 + 8003e00: d19a bne.n 8003d38 + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 8003e02: 697a ldr r2, [r7, #20] + 8003e04: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8003e06: 68f8 ldr r0, [r7, #12] + 8003e08: f000 f974 bl 80040f4 + 8003e0c: 4603 mov r3, r0 + 8003e0e: 2b00 cmp r3, #0 + 8003e10: d001 beq.n 8003e16 + { + return HAL_ERROR; + 8003e12: 2301 movs r3, #1 + 8003e14: e01a b.n 8003e4c + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 8003e16: 68fb ldr r3, [r7, #12] + 8003e18: 681b ldr r3, [r3, #0] + 8003e1a: 2220 movs r2, #32 + 8003e1c: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 8003e1e: 68fb ldr r3, [r7, #12] + 8003e20: 681b ldr r3, [r3, #0] + 8003e22: 6859 ldr r1, [r3, #4] + 8003e24: 68fb ldr r3, [r7, #12] + 8003e26: 681a ldr r2, [r3, #0] + 8003e28: 4b0b ldr r3, [pc, #44] ; (8003e58 ) + 8003e2a: 400b ands r3, r1 + 8003e2c: 6053 str r3, [r2, #4] + + hi2c->State = HAL_I2C_STATE_READY; + 8003e2e: 68fb ldr r3, [r7, #12] + 8003e30: 2220 movs r2, #32 + 8003e32: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8003e36: 68fb ldr r3, [r7, #12] + 8003e38: 2200 movs r2, #0 + 8003e3a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8003e3e: 68fb ldr r3, [r7, #12] + 8003e40: 2200 movs r2, #0 + 8003e42: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8003e46: 2300 movs r3, #0 + 8003e48: e000 b.n 8003e4c + } + else + { + return HAL_BUSY; + 8003e4a: 2302 movs r3, #2 + } +} + 8003e4c: 4618 mov r0, r3 + 8003e4e: 3718 adds r7, #24 + 8003e50: 46bd mov sp, r7 + 8003e52: bd80 pop {r7, pc} + 8003e54: 80002400 .word 0x80002400 + 8003e58: fe00e800 .word 0xfe00e800 + +08003e5c : + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + 8003e5c: b580 push {r7, lr} + 8003e5e: b086 sub sp, #24 + 8003e60: af02 add r7, sp, #8 + 8003e62: 60f8 str r0, [r7, #12] + 8003e64: 4608 mov r0, r1 + 8003e66: 4611 mov r1, r2 + 8003e68: 461a mov r2, r3 + 8003e6a: 4603 mov r3, r0 + 8003e6c: 817b strh r3, [r7, #10] + 8003e6e: 460b mov r3, r1 + 8003e70: 813b strh r3, [r7, #8] + 8003e72: 4613 mov r3, r2 + 8003e74: 80fb strh r3, [r7, #6] + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + 8003e76: 88fb ldrh r3, [r7, #6] + 8003e78: b2da uxtb r2, r3 + 8003e7a: 8979 ldrh r1, [r7, #10] + 8003e7c: 4b20 ldr r3, [pc, #128] ; (8003f00 ) + 8003e7e: 9300 str r3, [sp, #0] + 8003e80: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 8003e84: 68f8 ldr r0, [r7, #12] + 8003e86: f000 fa53 bl 8004330 + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 8003e8a: 69fa ldr r2, [r7, #28] + 8003e8c: 69b9 ldr r1, [r7, #24] + 8003e8e: 68f8 ldr r0, [r7, #12] + 8003e90: f000 f8f0 bl 8004074 + 8003e94: 4603 mov r3, r0 + 8003e96: 2b00 cmp r3, #0 + 8003e98: d001 beq.n 8003e9e + { + return HAL_ERROR; + 8003e9a: 2301 movs r3, #1 + 8003e9c: e02c b.n 8003ef8 + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 8003e9e: 88fb ldrh r3, [r7, #6] + 8003ea0: 2b01 cmp r3, #1 + 8003ea2: d105 bne.n 8003eb0 + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 8003ea4: 893b ldrh r3, [r7, #8] + 8003ea6: b2da uxtb r2, r3 + 8003ea8: 68fb ldr r3, [r7, #12] + 8003eaa: 681b ldr r3, [r3, #0] + 8003eac: 629a str r2, [r3, #40] ; 0x28 + 8003eae: e015 b.n 8003edc + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 8003eb0: 893b ldrh r3, [r7, #8] + 8003eb2: 0a1b lsrs r3, r3, #8 + 8003eb4: b29b uxth r3, r3 + 8003eb6: b2da uxtb r2, r3 + 8003eb8: 68fb ldr r3, [r7, #12] + 8003eba: 681b ldr r3, [r3, #0] + 8003ebc: 629a str r2, [r3, #40] ; 0x28 + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 8003ebe: 69fa ldr r2, [r7, #28] + 8003ec0: 69b9 ldr r1, [r7, #24] + 8003ec2: 68f8 ldr r0, [r7, #12] + 8003ec4: f000 f8d6 bl 8004074 + 8003ec8: 4603 mov r3, r0 + 8003eca: 2b00 cmp r3, #0 + 8003ecc: d001 beq.n 8003ed2 + { + return HAL_ERROR; + 8003ece: 2301 movs r3, #1 + 8003ed0: e012 b.n 8003ef8 + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 8003ed2: 893b ldrh r3, [r7, #8] + 8003ed4: b2da uxtb r2, r3 + 8003ed6: 68fb ldr r3, [r7, #12] + 8003ed8: 681b ldr r3, [r3, #0] + 8003eda: 629a str r2, [r3, #40] ; 0x28 + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + 8003edc: 69fb ldr r3, [r7, #28] + 8003ede: 9300 str r3, [sp, #0] + 8003ee0: 69bb ldr r3, [r7, #24] + 8003ee2: 2200 movs r2, #0 + 8003ee4: 2180 movs r1, #128 ; 0x80 + 8003ee6: 68f8 ldr r0, [r7, #12] + 8003ee8: f000 f884 bl 8003ff4 + 8003eec: 4603 mov r3, r0 + 8003eee: 2b00 cmp r3, #0 + 8003ef0: d001 beq.n 8003ef6 + { + return HAL_ERROR; + 8003ef2: 2301 movs r3, #1 + 8003ef4: e000 b.n 8003ef8 + } + + return HAL_OK; + 8003ef6: 2300 movs r3, #0 +} + 8003ef8: 4618 mov r0, r3 + 8003efa: 3710 adds r7, #16 + 8003efc: 46bd mov sp, r7 + 8003efe: bd80 pop {r7, pc} + 8003f00: 80002000 .word 0x80002000 + +08003f04 : + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + 8003f04: b580 push {r7, lr} + 8003f06: b086 sub sp, #24 + 8003f08: af02 add r7, sp, #8 + 8003f0a: 60f8 str r0, [r7, #12] + 8003f0c: 4608 mov r0, r1 + 8003f0e: 4611 mov r1, r2 + 8003f10: 461a mov r2, r3 + 8003f12: 4603 mov r3, r0 + 8003f14: 817b strh r3, [r7, #10] + 8003f16: 460b mov r3, r1 + 8003f18: 813b strh r3, [r7, #8] + 8003f1a: 4613 mov r3, r2 + 8003f1c: 80fb strh r3, [r7, #6] + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + 8003f1e: 88fb ldrh r3, [r7, #6] + 8003f20: b2da uxtb r2, r3 + 8003f22: 8979 ldrh r1, [r7, #10] + 8003f24: 4b20 ldr r3, [pc, #128] ; (8003fa8 ) + 8003f26: 9300 str r3, [sp, #0] + 8003f28: 2300 movs r3, #0 + 8003f2a: 68f8 ldr r0, [r7, #12] + 8003f2c: f000 fa00 bl 8004330 + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 8003f30: 69fa ldr r2, [r7, #28] + 8003f32: 69b9 ldr r1, [r7, #24] + 8003f34: 68f8 ldr r0, [r7, #12] + 8003f36: f000 f89d bl 8004074 + 8003f3a: 4603 mov r3, r0 + 8003f3c: 2b00 cmp r3, #0 + 8003f3e: d001 beq.n 8003f44 + { + return HAL_ERROR; + 8003f40: 2301 movs r3, #1 + 8003f42: e02c b.n 8003f9e + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 8003f44: 88fb ldrh r3, [r7, #6] + 8003f46: 2b01 cmp r3, #1 + 8003f48: d105 bne.n 8003f56 + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 8003f4a: 893b ldrh r3, [r7, #8] + 8003f4c: b2da uxtb r2, r3 + 8003f4e: 68fb ldr r3, [r7, #12] + 8003f50: 681b ldr r3, [r3, #0] + 8003f52: 629a str r2, [r3, #40] ; 0x28 + 8003f54: e015 b.n 8003f82 + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 8003f56: 893b ldrh r3, [r7, #8] + 8003f58: 0a1b lsrs r3, r3, #8 + 8003f5a: b29b uxth r3, r3 + 8003f5c: b2da uxtb r2, r3 + 8003f5e: 68fb ldr r3, [r7, #12] + 8003f60: 681b ldr r3, [r3, #0] + 8003f62: 629a str r2, [r3, #40] ; 0x28 + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 8003f64: 69fa ldr r2, [r7, #28] + 8003f66: 69b9 ldr r1, [r7, #24] + 8003f68: 68f8 ldr r0, [r7, #12] + 8003f6a: f000 f883 bl 8004074 + 8003f6e: 4603 mov r3, r0 + 8003f70: 2b00 cmp r3, #0 + 8003f72: d001 beq.n 8003f78 + { + return HAL_ERROR; + 8003f74: 2301 movs r3, #1 + 8003f76: e012 b.n 8003f9e + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 8003f78: 893b ldrh r3, [r7, #8] + 8003f7a: b2da uxtb r2, r3 + 8003f7c: 68fb ldr r3, [r7, #12] + 8003f7e: 681b ldr r3, [r3, #0] + 8003f80: 629a str r2, [r3, #40] ; 0x28 + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + 8003f82: 69fb ldr r3, [r7, #28] + 8003f84: 9300 str r3, [sp, #0] + 8003f86: 69bb ldr r3, [r7, #24] + 8003f88: 2200 movs r2, #0 + 8003f8a: 2140 movs r1, #64 ; 0x40 + 8003f8c: 68f8 ldr r0, [r7, #12] + 8003f8e: f000 f831 bl 8003ff4 + 8003f92: 4603 mov r3, r0 + 8003f94: 2b00 cmp r3, #0 + 8003f96: d001 beq.n 8003f9c + { + return HAL_ERROR; + 8003f98: 2301 movs r3, #1 + 8003f9a: e000 b.n 8003f9e + } + + return HAL_OK; + 8003f9c: 2300 movs r3, #0 +} + 8003f9e: 4618 mov r0, r3 + 8003fa0: 3710 adds r7, #16 + 8003fa2: 46bd mov sp, r7 + 8003fa4: bd80 pop {r7, pc} + 8003fa6: bf00 nop + 8003fa8: 80002000 .word 0x80002000 + +08003fac : + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + 8003fac: b480 push {r7} + 8003fae: b083 sub sp, #12 + 8003fb0: af00 add r7, sp, #0 + 8003fb2: 6078 str r0, [r7, #4] + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 8003fb4: 687b ldr r3, [r7, #4] + 8003fb6: 681b ldr r3, [r3, #0] + 8003fb8: 699b ldr r3, [r3, #24] + 8003fba: f003 0302 and.w r3, r3, #2 + 8003fbe: 2b02 cmp r3, #2 + 8003fc0: d103 bne.n 8003fca + { + hi2c->Instance->TXDR = 0x00U; + 8003fc2: 687b ldr r3, [r7, #4] + 8003fc4: 681b ldr r3, [r3, #0] + 8003fc6: 2200 movs r2, #0 + 8003fc8: 629a str r2, [r3, #40] ; 0x28 + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 8003fca: 687b ldr r3, [r7, #4] + 8003fcc: 681b ldr r3, [r3, #0] + 8003fce: 699b ldr r3, [r3, #24] + 8003fd0: f003 0301 and.w r3, r3, #1 + 8003fd4: 2b01 cmp r3, #1 + 8003fd6: d007 beq.n 8003fe8 + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 8003fd8: 687b ldr r3, [r7, #4] + 8003fda: 681b ldr r3, [r3, #0] + 8003fdc: 699a ldr r2, [r3, #24] + 8003fde: 687b ldr r3, [r7, #4] + 8003fe0: 681b ldr r3, [r3, #0] + 8003fe2: f042 0201 orr.w r2, r2, #1 + 8003fe6: 619a str r2, [r3, #24] + } +} + 8003fe8: bf00 nop + 8003fea: 370c adds r7, #12 + 8003fec: 46bd mov sp, r7 + 8003fee: f85d 7b04 ldr.w r7, [sp], #4 + 8003ff2: 4770 bx lr + +08003ff4 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + 8003ff4: b580 push {r7, lr} + 8003ff6: b084 sub sp, #16 + 8003ff8: af00 add r7, sp, #0 + 8003ffa: 60f8 str r0, [r7, #12] + 8003ffc: 60b9 str r1, [r7, #8] + 8003ffe: 603b str r3, [r7, #0] + 8004000: 4613 mov r3, r2 + 8004002: 71fb strb r3, [r7, #7] + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 8004004: e022 b.n 800404c + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8004006: 683b ldr r3, [r7, #0] + 8004008: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800400c: d01e beq.n 800404c + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800400e: f7fe f929 bl 8002264 + 8004012: 4602 mov r2, r0 + 8004014: 69bb ldr r3, [r7, #24] + 8004016: 1ad3 subs r3, r2, r3 + 8004018: 683a ldr r2, [r7, #0] + 800401a: 429a cmp r2, r3 + 800401c: d302 bcc.n 8004024 + 800401e: 683b ldr r3, [r7, #0] + 8004020: 2b00 cmp r3, #0 + 8004022: d113 bne.n 800404c + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8004024: 68fb ldr r3, [r7, #12] + 8004026: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004028: f043 0220 orr.w r2, r3, #32 + 800402c: 68fb ldr r3, [r7, #12] + 800402e: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8004030: 68fb ldr r3, [r7, #12] + 8004032: 2220 movs r2, #32 + 8004034: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8004038: 68fb ldr r3, [r7, #12] + 800403a: 2200 movs r2, #0 + 800403c: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004040: 68fb ldr r3, [r7, #12] + 8004042: 2200 movs r2, #0 + 8004044: f883 2040 strb.w r2, [r3, #64] ; 0x40 + return HAL_ERROR; + 8004048: 2301 movs r3, #1 + 800404a: e00f b.n 800406c + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 800404c: 68fb ldr r3, [r7, #12] + 800404e: 681b ldr r3, [r3, #0] + 8004050: 699a ldr r2, [r3, #24] + 8004052: 68bb ldr r3, [r7, #8] + 8004054: 4013 ands r3, r2 + 8004056: 68ba ldr r2, [r7, #8] + 8004058: 429a cmp r2, r3 + 800405a: bf0c ite eq + 800405c: 2301 moveq r3, #1 + 800405e: 2300 movne r3, #0 + 8004060: b2db uxtb r3, r3 + 8004062: 461a mov r2, r3 + 8004064: 79fb ldrb r3, [r7, #7] + 8004066: 429a cmp r2, r3 + 8004068: d0cd beq.n 8004006 + } + } + } + return HAL_OK; + 800406a: 2300 movs r3, #0 +} + 800406c: 4618 mov r0, r3 + 800406e: 3710 adds r7, #16 + 8004070: 46bd mov sp, r7 + 8004072: bd80 pop {r7, pc} + +08004074 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 8004074: b580 push {r7, lr} + 8004076: b084 sub sp, #16 + 8004078: af00 add r7, sp, #0 + 800407a: 60f8 str r0, [r7, #12] + 800407c: 60b9 str r1, [r7, #8] + 800407e: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 8004080: e02c b.n 80040dc + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + 8004082: 687a ldr r2, [r7, #4] + 8004084: 68b9 ldr r1, [r7, #8] + 8004086: 68f8 ldr r0, [r7, #12] + 8004088: f000 f8dc bl 8004244 + 800408c: 4603 mov r3, r0 + 800408e: 2b00 cmp r3, #0 + 8004090: d001 beq.n 8004096 + { + return HAL_ERROR; + 8004092: 2301 movs r3, #1 + 8004094: e02a b.n 80040ec + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8004096: 68bb ldr r3, [r7, #8] + 8004098: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 800409c: d01e beq.n 80040dc + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 800409e: f7fe f8e1 bl 8002264 + 80040a2: 4602 mov r2, r0 + 80040a4: 687b ldr r3, [r7, #4] + 80040a6: 1ad3 subs r3, r2, r3 + 80040a8: 68ba ldr r2, [r7, #8] + 80040aa: 429a cmp r2, r3 + 80040ac: d302 bcc.n 80040b4 + 80040ae: 68bb ldr r3, [r7, #8] + 80040b0: 2b00 cmp r3, #0 + 80040b2: d113 bne.n 80040dc + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 80040b4: 68fb ldr r3, [r7, #12] + 80040b6: 6c5b ldr r3, [r3, #68] ; 0x44 + 80040b8: f043 0220 orr.w r2, r3, #32 + 80040bc: 68fb ldr r3, [r7, #12] + 80040be: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 80040c0: 68fb ldr r3, [r7, #12] + 80040c2: 2220 movs r2, #32 + 80040c4: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80040c8: 68fb ldr r3, [r7, #12] + 80040ca: 2200 movs r2, #0 + 80040cc: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80040d0: 68fb ldr r3, [r7, #12] + 80040d2: 2200 movs r2, #0 + 80040d4: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 80040d8: 2301 movs r3, #1 + 80040da: e007 b.n 80040ec + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 80040dc: 68fb ldr r3, [r7, #12] + 80040de: 681b ldr r3, [r3, #0] + 80040e0: 699b ldr r3, [r3, #24] + 80040e2: f003 0302 and.w r3, r3, #2 + 80040e6: 2b02 cmp r3, #2 + 80040e8: d1cb bne.n 8004082 + } + } + } + return HAL_OK; + 80040ea: 2300 movs r3, #0 +} + 80040ec: 4618 mov r0, r3 + 80040ee: 3710 adds r7, #16 + 80040f0: 46bd mov sp, r7 + 80040f2: bd80 pop {r7, pc} + +080040f4 : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 80040f4: b580 push {r7, lr} + 80040f6: b084 sub sp, #16 + 80040f8: af00 add r7, sp, #0 + 80040fa: 60f8 str r0, [r7, #12] + 80040fc: 60b9 str r1, [r7, #8] + 80040fe: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8004100: e028 b.n 8004154 + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + 8004102: 687a ldr r2, [r7, #4] + 8004104: 68b9 ldr r1, [r7, #8] + 8004106: 68f8 ldr r0, [r7, #12] + 8004108: f000 f89c bl 8004244 + 800410c: 4603 mov r3, r0 + 800410e: 2b00 cmp r3, #0 + 8004110: d001 beq.n 8004116 + { + return HAL_ERROR; + 8004112: 2301 movs r3, #1 + 8004114: e026 b.n 8004164 + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8004116: f7fe f8a5 bl 8002264 + 800411a: 4602 mov r2, r0 + 800411c: 687b ldr r3, [r7, #4] + 800411e: 1ad3 subs r3, r2, r3 + 8004120: 68ba ldr r2, [r7, #8] + 8004122: 429a cmp r2, r3 + 8004124: d302 bcc.n 800412c + 8004126: 68bb ldr r3, [r7, #8] + 8004128: 2b00 cmp r3, #0 + 800412a: d113 bne.n 8004154 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 800412c: 68fb ldr r3, [r7, #12] + 800412e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004130: f043 0220 orr.w r2, r3, #32 + 8004134: 68fb ldr r3, [r7, #12] + 8004136: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8004138: 68fb ldr r3, [r7, #12] + 800413a: 2220 movs r2, #32 + 800413c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 8004140: 68fb ldr r3, [r7, #12] + 8004142: 2200 movs r2, #0 + 8004144: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004148: 68fb ldr r3, [r7, #12] + 800414a: 2200 movs r2, #0 + 800414c: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 8004150: 2301 movs r3, #1 + 8004152: e007 b.n 8004164 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 8004154: 68fb ldr r3, [r7, #12] + 8004156: 681b ldr r3, [r3, #0] + 8004158: 699b ldr r3, [r3, #24] + 800415a: f003 0320 and.w r3, r3, #32 + 800415e: 2b20 cmp r3, #32 + 8004160: d1cf bne.n 8004102 + } + } + return HAL_OK; + 8004162: 2300 movs r3, #0 +} + 8004164: 4618 mov r0, r3 + 8004166: 3710 adds r7, #16 + 8004168: 46bd mov sp, r7 + 800416a: bd80 pop {r7, pc} + +0800416c : + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + 800416c: b580 push {r7, lr} + 800416e: b084 sub sp, #16 + 8004170: af00 add r7, sp, #0 + 8004172: 60f8 str r0, [r7, #12] + 8004174: 60b9 str r1, [r7, #8] + 8004176: 607a str r2, [r7, #4] + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 8004178: e055 b.n 8004226 + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + 800417a: 687a ldr r2, [r7, #4] + 800417c: 68b9 ldr r1, [r7, #8] + 800417e: 68f8 ldr r0, [r7, #12] + 8004180: f000 f860 bl 8004244 + 8004184: 4603 mov r3, r0 + 8004186: 2b00 cmp r3, #0 + 8004188: d001 beq.n 800418e + { + return HAL_ERROR; + 800418a: 2301 movs r3, #1 + 800418c: e053 b.n 8004236 + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + 800418e: 68fb ldr r3, [r7, #12] + 8004190: 681b ldr r3, [r3, #0] + 8004192: 699b ldr r3, [r3, #24] + 8004194: f003 0320 and.w r3, r3, #32 + 8004198: 2b20 cmp r3, #32 + 800419a: d129 bne.n 80041f0 + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + 800419c: 68fb ldr r3, [r7, #12] + 800419e: 681b ldr r3, [r3, #0] + 80041a0: 699b ldr r3, [r3, #24] + 80041a2: f003 0304 and.w r3, r3, #4 + 80041a6: 2b04 cmp r3, #4 + 80041a8: d105 bne.n 80041b6 + 80041aa: 68fb ldr r3, [r7, #12] + 80041ac: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80041ae: 2b00 cmp r3, #0 + 80041b0: d001 beq.n 80041b6 + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + 80041b2: 2300 movs r3, #0 + 80041b4: e03f b.n 8004236 + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 80041b6: 68fb ldr r3, [r7, #12] + 80041b8: 681b ldr r3, [r3, #0] + 80041ba: 2220 movs r2, #32 + 80041bc: 61da str r2, [r3, #28] + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 80041be: 68fb ldr r3, [r7, #12] + 80041c0: 681b ldr r3, [r3, #0] + 80041c2: 6859 ldr r1, [r3, #4] + 80041c4: 68fb ldr r3, [r7, #12] + 80041c6: 681a ldr r2, [r3, #0] + 80041c8: 4b1d ldr r3, [pc, #116] ; (8004240 ) + 80041ca: 400b ands r3, r1 + 80041cc: 6053 str r3, [r2, #4] + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 80041ce: 68fb ldr r3, [r7, #12] + 80041d0: 2200 movs r2, #0 + 80041d2: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 80041d4: 68fb ldr r3, [r7, #12] + 80041d6: 2220 movs r2, #32 + 80041d8: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80041dc: 68fb ldr r3, [r7, #12] + 80041de: 2200 movs r2, #0 + 80041e0: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80041e4: 68fb ldr r3, [r7, #12] + 80041e6: 2200 movs r2, #0 + 80041e8: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 80041ec: 2301 movs r3, #1 + 80041ee: e022 b.n 8004236 + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 80041f0: f7fe f838 bl 8002264 + 80041f4: 4602 mov r2, r0 + 80041f6: 687b ldr r3, [r7, #4] + 80041f8: 1ad3 subs r3, r2, r3 + 80041fa: 68ba ldr r2, [r7, #8] + 80041fc: 429a cmp r2, r3 + 80041fe: d302 bcc.n 8004206 + 8004200: 68bb ldr r3, [r7, #8] + 8004202: 2b00 cmp r3, #0 + 8004204: d10f bne.n 8004226 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 8004206: 68fb ldr r3, [r7, #12] + 8004208: 6c5b ldr r3, [r3, #68] ; 0x44 + 800420a: f043 0220 orr.w r2, r3, #32 + 800420e: 68fb ldr r3, [r7, #12] + 8004210: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8004212: 68fb ldr r3, [r7, #12] + 8004214: 2220 movs r2, #32 + 8004216: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 800421a: 68fb ldr r3, [r7, #12] + 800421c: 2200 movs r2, #0 + 800421e: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 8004222: 2301 movs r3, #1 + 8004224: e007 b.n 8004236 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 8004226: 68fb ldr r3, [r7, #12] + 8004228: 681b ldr r3, [r3, #0] + 800422a: 699b ldr r3, [r3, #24] + 800422c: f003 0304 and.w r3, r3, #4 + 8004230: 2b04 cmp r3, #4 + 8004232: d1a2 bne.n 800417a + } + } + return HAL_OK; + 8004234: 2300 movs r3, #0 +} + 8004236: 4618 mov r0, r3 + 8004238: 3710 adds r7, #16 + 800423a: 46bd mov sp, r7 + 800423c: bd80 pop {r7, pc} + 800423e: bf00 nop + 8004240: fe00e800 .word 0xfe00e800 + +08004244 : + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + 8004244: b580 push {r7, lr} + 8004246: b084 sub sp, #16 + 8004248: af00 add r7, sp, #0 + 800424a: 60f8 str r0, [r7, #12] + 800424c: 60b9 str r1, [r7, #8] + 800424e: 607a str r2, [r7, #4] + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 8004250: 68fb ldr r3, [r7, #12] + 8004252: 681b ldr r3, [r3, #0] + 8004254: 699b ldr r3, [r3, #24] + 8004256: f003 0310 and.w r3, r3, #16 + 800425a: 2b10 cmp r3, #16 + 800425c: d161 bne.n 8004322 + { + /* In case of Soft End condition, generate the STOP condition */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 800425e: 68fb ldr r3, [r7, #12] + 8004260: 681b ldr r3, [r3, #0] + 8004262: 685b ldr r3, [r3, #4] + 8004264: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8004268: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 + 800426c: d02b beq.n 80042c6 + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + 800426e: 68fb ldr r3, [r7, #12] + 8004270: 681b ldr r3, [r3, #0] + 8004272: 685a ldr r2, [r3, #4] + 8004274: 68fb ldr r3, [r7, #12] + 8004276: 681b ldr r3, [r3, #0] + 8004278: f442 4280 orr.w r2, r2, #16384 ; 0x4000 + 800427c: 605a str r2, [r3, #4] + } + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 800427e: e022 b.n 80042c6 + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8004280: 68bb ldr r3, [r7, #8] + 8004282: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8004286: d01e beq.n 80042c6 + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8004288: f7fd ffec bl 8002264 + 800428c: 4602 mov r2, r0 + 800428e: 687b ldr r3, [r7, #4] + 8004290: 1ad3 subs r3, r2, r3 + 8004292: 68ba ldr r2, [r7, #8] + 8004294: 429a cmp r2, r3 + 8004296: d302 bcc.n 800429e + 8004298: 68bb ldr r3, [r7, #8] + 800429a: 2b00 cmp r3, #0 + 800429c: d113 bne.n 80042c6 + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 800429e: 68fb ldr r3, [r7, #12] + 80042a0: 6c5b ldr r3, [r3, #68] ; 0x44 + 80042a2: f043 0220 orr.w r2, r3, #32 + 80042a6: 68fb ldr r3, [r7, #12] + 80042a8: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 80042aa: 68fb ldr r3, [r7, #12] + 80042ac: 2220 movs r2, #32 + 80042ae: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 80042b2: 68fb ldr r3, [r7, #12] + 80042b4: 2200 movs r2, #0 + 80042b6: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80042ba: 68fb ldr r3, [r7, #12] + 80042bc: 2200 movs r2, #0 + 80042be: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 80042c2: 2301 movs r3, #1 + 80042c4: e02e b.n 8004324 + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 80042c6: 68fb ldr r3, [r7, #12] + 80042c8: 681b ldr r3, [r3, #0] + 80042ca: 699b ldr r3, [r3, #24] + 80042cc: f003 0320 and.w r3, r3, #32 + 80042d0: 2b20 cmp r3, #32 + 80042d2: d1d5 bne.n 8004280 + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 80042d4: 68fb ldr r3, [r7, #12] + 80042d6: 681b ldr r3, [r3, #0] + 80042d8: 2210 movs r2, #16 + 80042da: 61da str r2, [r3, #28] + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 80042dc: 68fb ldr r3, [r7, #12] + 80042de: 681b ldr r3, [r3, #0] + 80042e0: 2220 movs r2, #32 + 80042e2: 61da str r2, [r3, #28] + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + 80042e4: 68f8 ldr r0, [r7, #12] + 80042e6: f7ff fe61 bl 8003fac + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + 80042ea: 68fb ldr r3, [r7, #12] + 80042ec: 681b ldr r3, [r3, #0] + 80042ee: 6859 ldr r1, [r3, #4] + 80042f0: 68fb ldr r3, [r7, #12] + 80042f2: 681a ldr r2, [r3, #0] + 80042f4: 4b0d ldr r3, [pc, #52] ; (800432c ) + 80042f6: 400b ands r3, r1 + 80042f8: 6053 str r3, [r2, #4] + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 80042fa: 68fb ldr r3, [r7, #12] + 80042fc: 6c5b ldr r3, [r3, #68] ; 0x44 + 80042fe: f043 0204 orr.w r2, r3, #4 + 8004302: 68fb ldr r3, [r7, #12] + 8004304: 645a str r2, [r3, #68] ; 0x44 + hi2c->State = HAL_I2C_STATE_READY; + 8004306: 68fb ldr r3, [r7, #12] + 8004308: 2220 movs r2, #32 + 800430a: f883 2041 strb.w r2, [r3, #65] ; 0x41 + hi2c->Mode = HAL_I2C_MODE_NONE; + 800430e: 68fb ldr r3, [r7, #12] + 8004310: 2200 movs r2, #0 + 8004312: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004316: 68fb ldr r3, [r7, #12] + 8004318: 2200 movs r2, #0 + 800431a: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_ERROR; + 800431e: 2301 movs r3, #1 + 8004320: e000 b.n 8004324 + } + return HAL_OK; + 8004322: 2300 movs r3, #0 +} + 8004324: 4618 mov r0, r3 + 8004326: 3710 adds r7, #16 + 8004328: 46bd mov sp, r7 + 800432a: bd80 pop {r7, pc} + 800432c: fe00e800 .word 0xfe00e800 + +08004330 : + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + 8004330: b480 push {r7} + 8004332: b085 sub sp, #20 + 8004334: af00 add r7, sp, #0 + 8004336: 60f8 str r0, [r7, #12] + 8004338: 607b str r3, [r7, #4] + 800433a: 460b mov r3, r1 + 800433c: 817b strh r3, [r7, #10] + 800433e: 4613 mov r3, r2 + 8004340: 727b strb r3, [r7, #9] + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, + 8004342: 68fb ldr r3, [r7, #12] + 8004344: 681b ldr r3, [r3, #0] + 8004346: 685a ldr r2, [r3, #4] + 8004348: 69bb ldr r3, [r7, #24] + 800434a: 0d5b lsrs r3, r3, #21 + 800434c: f403 6180 and.w r1, r3, #1024 ; 0x400 + 8004350: 4b0d ldr r3, [pc, #52] ; (8004388 ) + 8004352: 430b orrs r3, r1 + 8004354: 43db mvns r3, r3 + 8004356: ea02 0103 and.w r1, r2, r3 + 800435a: 897b ldrh r3, [r7, #10] + 800435c: f3c3 0209 ubfx r2, r3, #0, #10 + 8004360: 7a7b ldrb r3, [r7, #9] + 8004362: 041b lsls r3, r3, #16 + 8004364: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8004368: 431a orrs r2, r3 + 800436a: 687b ldr r3, [r7, #4] + 800436c: 431a orrs r2, r3 + 800436e: 69bb ldr r3, [r7, #24] + 8004370: 431a orrs r2, r3 + 8004372: 68fb ldr r3, [r7, #12] + 8004374: 681b ldr r3, [r3, #0] + 8004376: 430a orrs r2, r1 + 8004378: 605a str r2, [r3, #4] + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); +} + 800437a: bf00 nop + 800437c: 3714 adds r7, #20 + 800437e: 46bd mov sp, r7 + 8004380: f85d 7b04 ldr.w r7, [sp], #4 + 8004384: 4770 bx lr + 8004386: bf00 nop + 8004388: 03ff63ff .word 0x03ff63ff + +0800438c : + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + 800438c: b480 push {r7} + 800438e: b083 sub sp, #12 + 8004390: af00 add r7, sp, #0 + 8004392: 6078 str r0, [r7, #4] + 8004394: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 8004396: 687b ldr r3, [r7, #4] + 8004398: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 800439c: b2db uxtb r3, r3 + 800439e: 2b20 cmp r3, #32 + 80043a0: d138 bne.n 8004414 + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 80043a2: 687b ldr r3, [r7, #4] + 80043a4: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 80043a8: 2b01 cmp r3, #1 + 80043aa: d101 bne.n 80043b0 + 80043ac: 2302 movs r3, #2 + 80043ae: e032 b.n 8004416 + 80043b0: 687b ldr r3, [r7, #4] + 80043b2: 2201 movs r2, #1 + 80043b4: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + hi2c->State = HAL_I2C_STATE_BUSY; + 80043b8: 687b ldr r3, [r7, #4] + 80043ba: 2224 movs r2, #36 ; 0x24 + 80043bc: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 80043c0: 687b ldr r3, [r7, #4] + 80043c2: 681b ldr r3, [r3, #0] + 80043c4: 681a ldr r2, [r3, #0] + 80043c6: 687b ldr r3, [r7, #4] + 80043c8: 681b ldr r3, [r3, #0] + 80043ca: f022 0201 bic.w r2, r2, #1 + 80043ce: 601a str r2, [r3, #0] + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 80043d0: 687b ldr r3, [r7, #4] + 80043d2: 681b ldr r3, [r3, #0] + 80043d4: 681a ldr r2, [r3, #0] + 80043d6: 687b ldr r3, [r7, #4] + 80043d8: 681b ldr r3, [r3, #0] + 80043da: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 80043de: 601a str r2, [r3, #0] + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + 80043e0: 687b ldr r3, [r7, #4] + 80043e2: 681b ldr r3, [r3, #0] + 80043e4: 6819 ldr r1, [r3, #0] + 80043e6: 687b ldr r3, [r7, #4] + 80043e8: 681b ldr r3, [r3, #0] + 80043ea: 683a ldr r2, [r7, #0] + 80043ec: 430a orrs r2, r1 + 80043ee: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 80043f0: 687b ldr r3, [r7, #4] + 80043f2: 681b ldr r3, [r3, #0] + 80043f4: 681a ldr r2, [r3, #0] + 80043f6: 687b ldr r3, [r7, #4] + 80043f8: 681b ldr r3, [r3, #0] + 80043fa: f042 0201 orr.w r2, r2, #1 + 80043fe: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 8004400: 687b ldr r3, [r7, #4] + 8004402: 2220 movs r2, #32 + 8004404: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 8004408: 687b ldr r3, [r7, #4] + 800440a: 2200 movs r2, #0 + 800440c: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 8004410: 2300 movs r3, #0 + 8004412: e000 b.n 8004416 + } + else + { + return HAL_BUSY; + 8004414: 2302 movs r3, #2 + } +} + 8004416: 4618 mov r0, r3 + 8004418: 370c adds r7, #12 + 800441a: 46bd mov sp, r7 + 800441c: f85d 7b04 ldr.w r7, [sp], #4 + 8004420: 4770 bx lr + +08004422 : + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + 8004422: b480 push {r7} + 8004424: b085 sub sp, #20 + 8004426: af00 add r7, sp, #0 + 8004428: 6078 str r0, [r7, #4] + 800442a: 6039 str r1, [r7, #0] + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + 800442c: 687b ldr r3, [r7, #4] + 800442e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41 + 8004432: b2db uxtb r3, r3 + 8004434: 2b20 cmp r3, #32 + 8004436: d139 bne.n 80044ac + { + /* Process Locked */ + __HAL_LOCK(hi2c); + 8004438: 687b ldr r3, [r7, #4] + 800443a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 800443e: 2b01 cmp r3, #1 + 8004440: d101 bne.n 8004446 + 8004442: 2302 movs r3, #2 + 8004444: e033 b.n 80044ae + 8004446: 687b ldr r3, [r7, #4] + 8004448: 2201 movs r2, #1 + 800444a: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + hi2c->State = HAL_I2C_STATE_BUSY; + 800444e: 687b ldr r3, [r7, #4] + 8004450: 2224 movs r2, #36 ; 0x24 + 8004452: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + 8004456: 687b ldr r3, [r7, #4] + 8004458: 681b ldr r3, [r3, #0] + 800445a: 681a ldr r2, [r3, #0] + 800445c: 687b ldr r3, [r7, #4] + 800445e: 681b ldr r3, [r3, #0] + 8004460: f022 0201 bic.w r2, r2, #1 + 8004464: 601a str r2, [r3, #0] + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + 8004466: 687b ldr r3, [r7, #4] + 8004468: 681b ldr r3, [r3, #0] + 800446a: 681b ldr r3, [r3, #0] + 800446c: 60fb str r3, [r7, #12] + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + 800446e: 68fb ldr r3, [r7, #12] + 8004470: f423 6370 bic.w r3, r3, #3840 ; 0xf00 + 8004474: 60fb str r3, [r7, #12] + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + 8004476: 683b ldr r3, [r7, #0] + 8004478: 021b lsls r3, r3, #8 + 800447a: 68fa ldr r2, [r7, #12] + 800447c: 4313 orrs r3, r2 + 800447e: 60fb str r3, [r7, #12] + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + 8004480: 687b ldr r3, [r7, #4] + 8004482: 681b ldr r3, [r3, #0] + 8004484: 68fa ldr r2, [r7, #12] + 8004486: 601a str r2, [r3, #0] + + __HAL_I2C_ENABLE(hi2c); + 8004488: 687b ldr r3, [r7, #4] + 800448a: 681b ldr r3, [r3, #0] + 800448c: 681a ldr r2, [r3, #0] + 800448e: 687b ldr r3, [r7, #4] + 8004490: 681b ldr r3, [r3, #0] + 8004492: f042 0201 orr.w r2, r2, #1 + 8004496: 601a str r2, [r3, #0] + + hi2c->State = HAL_I2C_STATE_READY; + 8004498: 687b ldr r3, [r7, #4] + 800449a: 2220 movs r2, #32 + 800449c: f883 2041 strb.w r2, [r3, #65] ; 0x41 + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + 80044a0: 687b ldr r3, [r7, #4] + 80044a2: 2200 movs r2, #0 + 80044a4: f883 2040 strb.w r2, [r3, #64] ; 0x40 + + return HAL_OK; + 80044a8: 2300 movs r3, #0 + 80044aa: e000 b.n 80044ae + } + else + { + return HAL_BUSY; + 80044ac: 2302 movs r3, #2 + } +} + 80044ae: 4618 mov r0, r3 + 80044b0: 3714 adds r7, #20 + 80044b2: 46bd mov sp, r7 + 80044b4: f85d 7b04 ldr.w r7, [sp], #4 + 80044b8: 4770 bx lr + ... + +080044bc : + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 80044bc: b580 push {r7, lr} + 80044be: f5ad 7d00 sub.w sp, sp, #512 ; 0x200 + 80044c2: af00 add r7, sp, #0 + 80044c4: f507 7300 add.w r3, r7, #512 ; 0x200 + 80044c8: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80044cc: 6018 str r0, [r3, #0] +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + uint32_t pll_config2; +#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + 80044ce: f507 7300 add.w r3, r7, #512 ; 0x200 + 80044d2: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80044d6: 681b ldr r3, [r3, #0] + 80044d8: 2b00 cmp r3, #0 + 80044da: d102 bne.n 80044e2 + { + return HAL_ERROR; + 80044dc: 2301 movs r3, #1 + 80044de: f001 b823 b.w 8005528 + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 80044e2: f507 7300 add.w r3, r7, #512 ; 0x200 + 80044e6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80044ea: 681b ldr r3, [r3, #0] + 80044ec: 681b ldr r3, [r3, #0] + 80044ee: f003 0301 and.w r3, r3, #1 + 80044f2: 2b00 cmp r3, #0 + 80044f4: f000 817d beq.w 80047f2 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 80044f8: 4bbc ldr r3, [pc, #752] ; (80047ec ) + 80044fa: 685b ldr r3, [r3, #4] + 80044fc: f003 030c and.w r3, r3, #12 + 8004500: 2b04 cmp r3, #4 + 8004502: d00c beq.n 800451e + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + 8004504: 4bb9 ldr r3, [pc, #740] ; (80047ec ) + 8004506: 685b ldr r3, [r3, #4] + 8004508: f003 030c and.w r3, r3, #12 + 800450c: 2b08 cmp r3, #8 + 800450e: d15c bne.n 80045ca + 8004510: 4bb6 ldr r3, [pc, #728] ; (80047ec ) + 8004512: 685b ldr r3, [r3, #4] + 8004514: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8004518: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800451c: d155 bne.n 80045ca + 800451e: f44f 3300 mov.w r3, #131072 ; 0x20000 + 8004522: f8c7 31f0 str.w r3, [r7, #496] ; 0x1f0 + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004526: f8d7 31f0 ldr.w r3, [r7, #496] ; 0x1f0 + 800452a: fa93 f3a3 rbit r3, r3 + 800452e: f8c7 31ec str.w r3, [r7, #492] ; 0x1ec + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; + 8004532: f8d7 31ec ldr.w r3, [r7, #492] ; 0x1ec + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8004536: fab3 f383 clz r3, r3 + 800453a: b2db uxtb r3, r3 + 800453c: 095b lsrs r3, r3, #5 + 800453e: b2db uxtb r3, r3 + 8004540: f043 0301 orr.w r3, r3, #1 + 8004544: b2db uxtb r3, r3 + 8004546: 2b01 cmp r3, #1 + 8004548: d102 bne.n 8004550 + 800454a: 4ba8 ldr r3, [pc, #672] ; (80047ec ) + 800454c: 681b ldr r3, [r3, #0] + 800454e: e015 b.n 800457c + 8004550: f44f 3300 mov.w r3, #131072 ; 0x20000 + 8004554: f8c7 31e8 str.w r3, [r7, #488] ; 0x1e8 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004558: f8d7 31e8 ldr.w r3, [r7, #488] ; 0x1e8 + 800455c: fa93 f3a3 rbit r3, r3 + 8004560: f8c7 31e4 str.w r3, [r7, #484] ; 0x1e4 + 8004564: f44f 3300 mov.w r3, #131072 ; 0x20000 + 8004568: f8c7 31e0 str.w r3, [r7, #480] ; 0x1e0 + 800456c: f8d7 31e0 ldr.w r3, [r7, #480] ; 0x1e0 + 8004570: fa93 f3a3 rbit r3, r3 + 8004574: f8c7 31dc str.w r3, [r7, #476] ; 0x1dc + 8004578: 4b9c ldr r3, [pc, #624] ; (80047ec ) + 800457a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800457c: f44f 3200 mov.w r2, #131072 ; 0x20000 + 8004580: f8c7 21d8 str.w r2, [r7, #472] ; 0x1d8 + 8004584: f8d7 21d8 ldr.w r2, [r7, #472] ; 0x1d8 + 8004588: fa92 f2a2 rbit r2, r2 + 800458c: f8c7 21d4 str.w r2, [r7, #468] ; 0x1d4 + return result; + 8004590: f8d7 21d4 ldr.w r2, [r7, #468] ; 0x1d4 + 8004594: fab2 f282 clz r2, r2 + 8004598: b2d2 uxtb r2, r2 + 800459a: f042 0220 orr.w r2, r2, #32 + 800459e: b2d2 uxtb r2, r2 + 80045a0: f002 021f and.w r2, r2, #31 + 80045a4: 2101 movs r1, #1 + 80045a6: fa01 f202 lsl.w r2, r1, r2 + 80045aa: 4013 ands r3, r2 + 80045ac: 2b00 cmp r3, #0 + 80045ae: f000 811f beq.w 80047f0 + 80045b2: f507 7300 add.w r3, r7, #512 ; 0x200 + 80045b6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80045ba: 681b ldr r3, [r3, #0] + 80045bc: 685b ldr r3, [r3, #4] + 80045be: 2b00 cmp r3, #0 + 80045c0: f040 8116 bne.w 80047f0 + { + return HAL_ERROR; + 80045c4: 2301 movs r3, #1 + 80045c6: f000 bfaf b.w 8005528 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 80045ca: f507 7300 add.w r3, r7, #512 ; 0x200 + 80045ce: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80045d2: 681b ldr r3, [r3, #0] + 80045d4: 685b ldr r3, [r3, #4] + 80045d6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80045da: d106 bne.n 80045ea + 80045dc: 4b83 ldr r3, [pc, #524] ; (80047ec ) + 80045de: 681b ldr r3, [r3, #0] + 80045e0: 4a82 ldr r2, [pc, #520] ; (80047ec ) + 80045e2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80045e6: 6013 str r3, [r2, #0] + 80045e8: e036 b.n 8004658 + 80045ea: f507 7300 add.w r3, r7, #512 ; 0x200 + 80045ee: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80045f2: 681b ldr r3, [r3, #0] + 80045f4: 685b ldr r3, [r3, #4] + 80045f6: 2b00 cmp r3, #0 + 80045f8: d10c bne.n 8004614 + 80045fa: 4b7c ldr r3, [pc, #496] ; (80047ec ) + 80045fc: 681b ldr r3, [r3, #0] + 80045fe: 4a7b ldr r2, [pc, #492] ; (80047ec ) + 8004600: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8004604: 6013 str r3, [r2, #0] + 8004606: 4b79 ldr r3, [pc, #484] ; (80047ec ) + 8004608: 681b ldr r3, [r3, #0] + 800460a: 4a78 ldr r2, [pc, #480] ; (80047ec ) + 800460c: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8004610: 6013 str r3, [r2, #0] + 8004612: e021 b.n 8004658 + 8004614: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004618: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 800461c: 681b ldr r3, [r3, #0] + 800461e: 685b ldr r3, [r3, #4] + 8004620: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8004624: d10c bne.n 8004640 + 8004626: 4b71 ldr r3, [pc, #452] ; (80047ec ) + 8004628: 681b ldr r3, [r3, #0] + 800462a: 4a70 ldr r2, [pc, #448] ; (80047ec ) + 800462c: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8004630: 6013 str r3, [r2, #0] + 8004632: 4b6e ldr r3, [pc, #440] ; (80047ec ) + 8004634: 681b ldr r3, [r3, #0] + 8004636: 4a6d ldr r2, [pc, #436] ; (80047ec ) + 8004638: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 800463c: 6013 str r3, [r2, #0] + 800463e: e00b b.n 8004658 + 8004640: 4b6a ldr r3, [pc, #424] ; (80047ec ) + 8004642: 681b ldr r3, [r3, #0] + 8004644: 4a69 ldr r2, [pc, #420] ; (80047ec ) + 8004646: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 800464a: 6013 str r3, [r2, #0] + 800464c: 4b67 ldr r3, [pc, #412] ; (80047ec ) + 800464e: 681b ldr r3, [r3, #0] + 8004650: 4a66 ldr r2, [pc, #408] ; (80047ec ) + 8004652: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8004656: 6013 str r3, [r2, #0] + +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + /* Configure the HSE predivision factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + 8004658: 4b64 ldr r3, [pc, #400] ; (80047ec ) + 800465a: 6adb ldr r3, [r3, #44] ; 0x2c + 800465c: f023 020f bic.w r2, r3, #15 + 8004660: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004664: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8004668: 681b ldr r3, [r3, #0] + 800466a: 689b ldr r3, [r3, #8] + 800466c: 495f ldr r1, [pc, #380] ; (80047ec ) + 800466e: 4313 orrs r3, r2 + 8004670: 62cb str r3, [r1, #44] ; 0x2c +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8004672: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004676: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 800467a: 681b ldr r3, [r3, #0] + 800467c: 685b ldr r3, [r3, #4] + 800467e: 2b00 cmp r3, #0 + 8004680: d059 beq.n 8004736 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004682: f7fd fdef bl 8002264 + 8004686: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 800468a: e00a b.n 80046a2 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 800468c: f7fd fdea bl 8002264 + 8004690: 4602 mov r2, r0 + 8004692: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8004696: 1ad3 subs r3, r2, r3 + 8004698: 2b64 cmp r3, #100 ; 0x64 + 800469a: d902 bls.n 80046a2 + { + return HAL_TIMEOUT; + 800469c: 2303 movs r3, #3 + 800469e: f000 bf43 b.w 8005528 + 80046a2: f44f 3300 mov.w r3, #131072 ; 0x20000 + 80046a6: f8c7 31d0 str.w r3, [r7, #464] ; 0x1d0 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80046aa: f8d7 31d0 ldr.w r3, [r7, #464] ; 0x1d0 + 80046ae: fa93 f3a3 rbit r3, r3 + 80046b2: f8c7 31cc str.w r3, [r7, #460] ; 0x1cc + return result; + 80046b6: f8d7 31cc ldr.w r3, [r7, #460] ; 0x1cc + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80046ba: fab3 f383 clz r3, r3 + 80046be: b2db uxtb r3, r3 + 80046c0: 095b lsrs r3, r3, #5 + 80046c2: b2db uxtb r3, r3 + 80046c4: f043 0301 orr.w r3, r3, #1 + 80046c8: b2db uxtb r3, r3 + 80046ca: 2b01 cmp r3, #1 + 80046cc: d102 bne.n 80046d4 + 80046ce: 4b47 ldr r3, [pc, #284] ; (80047ec ) + 80046d0: 681b ldr r3, [r3, #0] + 80046d2: e015 b.n 8004700 + 80046d4: f44f 3300 mov.w r3, #131072 ; 0x20000 + 80046d8: f8c7 31c8 str.w r3, [r7, #456] ; 0x1c8 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80046dc: f8d7 31c8 ldr.w r3, [r7, #456] ; 0x1c8 + 80046e0: fa93 f3a3 rbit r3, r3 + 80046e4: f8c7 31c4 str.w r3, [r7, #452] ; 0x1c4 + 80046e8: f44f 3300 mov.w r3, #131072 ; 0x20000 + 80046ec: f8c7 31c0 str.w r3, [r7, #448] ; 0x1c0 + 80046f0: f8d7 31c0 ldr.w r3, [r7, #448] ; 0x1c0 + 80046f4: fa93 f3a3 rbit r3, r3 + 80046f8: f8c7 31bc str.w r3, [r7, #444] ; 0x1bc + 80046fc: 4b3b ldr r3, [pc, #236] ; (80047ec ) + 80046fe: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004700: f44f 3200 mov.w r2, #131072 ; 0x20000 + 8004704: f8c7 21b8 str.w r2, [r7, #440] ; 0x1b8 + 8004708: f8d7 21b8 ldr.w r2, [r7, #440] ; 0x1b8 + 800470c: fa92 f2a2 rbit r2, r2 + 8004710: f8c7 21b4 str.w r2, [r7, #436] ; 0x1b4 + return result; + 8004714: f8d7 21b4 ldr.w r2, [r7, #436] ; 0x1b4 + 8004718: fab2 f282 clz r2, r2 + 800471c: b2d2 uxtb r2, r2 + 800471e: f042 0220 orr.w r2, r2, #32 + 8004722: b2d2 uxtb r2, r2 + 8004724: f002 021f and.w r2, r2, #31 + 8004728: 2101 movs r1, #1 + 800472a: fa01 f202 lsl.w r2, r1, r2 + 800472e: 4013 ands r3, r2 + 8004730: 2b00 cmp r3, #0 + 8004732: d0ab beq.n 800468c + 8004734: e05d b.n 80047f2 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004736: f7fd fd95 bl 8002264 + 800473a: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 800473e: e00a b.n 8004756 + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8004740: f7fd fd90 bl 8002264 + 8004744: 4602 mov r2, r0 + 8004746: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 800474a: 1ad3 subs r3, r2, r3 + 800474c: 2b64 cmp r3, #100 ; 0x64 + 800474e: d902 bls.n 8004756 + { + return HAL_TIMEOUT; + 8004750: 2303 movs r3, #3 + 8004752: f000 bee9 b.w 8005528 + 8004756: f44f 3300 mov.w r3, #131072 ; 0x20000 + 800475a: f8c7 31b0 str.w r3, [r7, #432] ; 0x1b0 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 800475e: f8d7 31b0 ldr.w r3, [r7, #432] ; 0x1b0 + 8004762: fa93 f3a3 rbit r3, r3 + 8004766: f8c7 31ac str.w r3, [r7, #428] ; 0x1ac + return result; + 800476a: f8d7 31ac ldr.w r3, [r7, #428] ; 0x1ac + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 800476e: fab3 f383 clz r3, r3 + 8004772: b2db uxtb r3, r3 + 8004774: 095b lsrs r3, r3, #5 + 8004776: b2db uxtb r3, r3 + 8004778: f043 0301 orr.w r3, r3, #1 + 800477c: b2db uxtb r3, r3 + 800477e: 2b01 cmp r3, #1 + 8004780: d102 bne.n 8004788 + 8004782: 4b1a ldr r3, [pc, #104] ; (80047ec ) + 8004784: 681b ldr r3, [r3, #0] + 8004786: e015 b.n 80047b4 + 8004788: f44f 3300 mov.w r3, #131072 ; 0x20000 + 800478c: f8c7 31a8 str.w r3, [r7, #424] ; 0x1a8 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004790: f8d7 31a8 ldr.w r3, [r7, #424] ; 0x1a8 + 8004794: fa93 f3a3 rbit r3, r3 + 8004798: f8c7 31a4 str.w r3, [r7, #420] ; 0x1a4 + 800479c: f44f 3300 mov.w r3, #131072 ; 0x20000 + 80047a0: f8c7 31a0 str.w r3, [r7, #416] ; 0x1a0 + 80047a4: f8d7 31a0 ldr.w r3, [r7, #416] ; 0x1a0 + 80047a8: fa93 f3a3 rbit r3, r3 + 80047ac: f8c7 319c str.w r3, [r7, #412] ; 0x19c + 80047b0: 4b0e ldr r3, [pc, #56] ; (80047ec ) + 80047b2: 6a5b ldr r3, [r3, #36] ; 0x24 + 80047b4: f44f 3200 mov.w r2, #131072 ; 0x20000 + 80047b8: f8c7 2198 str.w r2, [r7, #408] ; 0x198 + 80047bc: f8d7 2198 ldr.w r2, [r7, #408] ; 0x198 + 80047c0: fa92 f2a2 rbit r2, r2 + 80047c4: f8c7 2194 str.w r2, [r7, #404] ; 0x194 + return result; + 80047c8: f8d7 2194 ldr.w r2, [r7, #404] ; 0x194 + 80047cc: fab2 f282 clz r2, r2 + 80047d0: b2d2 uxtb r2, r2 + 80047d2: f042 0220 orr.w r2, r2, #32 + 80047d6: b2d2 uxtb r2, r2 + 80047d8: f002 021f and.w r2, r2, #31 + 80047dc: 2101 movs r1, #1 + 80047de: fa01 f202 lsl.w r2, r1, r2 + 80047e2: 4013 ands r3, r2 + 80047e4: 2b00 cmp r3, #0 + 80047e6: d1ab bne.n 8004740 + 80047e8: e003 b.n 80047f2 + 80047ea: bf00 nop + 80047ec: 40021000 .word 0x40021000 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 80047f0: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 80047f2: f507 7300 add.w r3, r7, #512 ; 0x200 + 80047f6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80047fa: 681b ldr r3, [r3, #0] + 80047fc: 681b ldr r3, [r3, #0] + 80047fe: f003 0302 and.w r3, r3, #2 + 8004802: 2b00 cmp r3, #0 + 8004804: f000 817d beq.w 8004b02 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 8004808: 4ba6 ldr r3, [pc, #664] ; (8004aa4 ) + 800480a: 685b ldr r3, [r3, #4] + 800480c: f003 030c and.w r3, r3, #12 + 8004810: 2b00 cmp r3, #0 + 8004812: d00b beq.n 800482c + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + 8004814: 4ba3 ldr r3, [pc, #652] ; (8004aa4 ) + 8004816: 685b ldr r3, [r3, #4] + 8004818: f003 030c and.w r3, r3, #12 + 800481c: 2b08 cmp r3, #8 + 800481e: d172 bne.n 8004906 + 8004820: 4ba0 ldr r3, [pc, #640] ; (8004aa4 ) + 8004822: 685b ldr r3, [r3, #4] + 8004824: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8004828: 2b00 cmp r3, #0 + 800482a: d16c bne.n 8004906 + 800482c: 2302 movs r3, #2 + 800482e: f8c7 3190 str.w r3, [r7, #400] ; 0x190 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004832: f8d7 3190 ldr.w r3, [r7, #400] ; 0x190 + 8004836: fa93 f3a3 rbit r3, r3 + 800483a: f8c7 318c str.w r3, [r7, #396] ; 0x18c + return result; + 800483e: f8d7 318c ldr.w r3, [r7, #396] ; 0x18c + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8004842: fab3 f383 clz r3, r3 + 8004846: b2db uxtb r3, r3 + 8004848: 095b lsrs r3, r3, #5 + 800484a: b2db uxtb r3, r3 + 800484c: f043 0301 orr.w r3, r3, #1 + 8004850: b2db uxtb r3, r3 + 8004852: 2b01 cmp r3, #1 + 8004854: d102 bne.n 800485c + 8004856: 4b93 ldr r3, [pc, #588] ; (8004aa4 ) + 8004858: 681b ldr r3, [r3, #0] + 800485a: e013 b.n 8004884 + 800485c: 2302 movs r3, #2 + 800485e: f8c7 3188 str.w r3, [r7, #392] ; 0x188 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004862: f8d7 3188 ldr.w r3, [r7, #392] ; 0x188 + 8004866: fa93 f3a3 rbit r3, r3 + 800486a: f8c7 3184 str.w r3, [r7, #388] ; 0x184 + 800486e: 2302 movs r3, #2 + 8004870: f8c7 3180 str.w r3, [r7, #384] ; 0x180 + 8004874: f8d7 3180 ldr.w r3, [r7, #384] ; 0x180 + 8004878: fa93 f3a3 rbit r3, r3 + 800487c: f8c7 317c str.w r3, [r7, #380] ; 0x17c + 8004880: 4b88 ldr r3, [pc, #544] ; (8004aa4 ) + 8004882: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004884: 2202 movs r2, #2 + 8004886: f8c7 2178 str.w r2, [r7, #376] ; 0x178 + 800488a: f8d7 2178 ldr.w r2, [r7, #376] ; 0x178 + 800488e: fa92 f2a2 rbit r2, r2 + 8004892: f8c7 2174 str.w r2, [r7, #372] ; 0x174 + return result; + 8004896: f8d7 2174 ldr.w r2, [r7, #372] ; 0x174 + 800489a: fab2 f282 clz r2, r2 + 800489e: b2d2 uxtb r2, r2 + 80048a0: f042 0220 orr.w r2, r2, #32 + 80048a4: b2d2 uxtb r2, r2 + 80048a6: f002 021f and.w r2, r2, #31 + 80048aa: 2101 movs r1, #1 + 80048ac: fa01 f202 lsl.w r2, r1, r2 + 80048b0: 4013 ands r3, r2 + 80048b2: 2b00 cmp r3, #0 + 80048b4: d00a beq.n 80048cc + 80048b6: f507 7300 add.w r3, r7, #512 ; 0x200 + 80048ba: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80048be: 681b ldr r3, [r3, #0] + 80048c0: 691b ldr r3, [r3, #16] + 80048c2: 2b01 cmp r3, #1 + 80048c4: d002 beq.n 80048cc + { + return HAL_ERROR; + 80048c6: 2301 movs r3, #1 + 80048c8: f000 be2e b.w 8005528 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80048cc: 4b75 ldr r3, [pc, #468] ; (8004aa4 ) + 80048ce: 681b ldr r3, [r3, #0] + 80048d0: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 80048d4: f507 7300 add.w r3, r7, #512 ; 0x200 + 80048d8: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80048dc: 681b ldr r3, [r3, #0] + 80048de: 695b ldr r3, [r3, #20] + 80048e0: 21f8 movs r1, #248 ; 0xf8 + 80048e2: f8c7 1170 str.w r1, [r7, #368] ; 0x170 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80048e6: f8d7 1170 ldr.w r1, [r7, #368] ; 0x170 + 80048ea: fa91 f1a1 rbit r1, r1 + 80048ee: f8c7 116c str.w r1, [r7, #364] ; 0x16c + return result; + 80048f2: f8d7 116c ldr.w r1, [r7, #364] ; 0x16c + 80048f6: fab1 f181 clz r1, r1 + 80048fa: b2c9 uxtb r1, r1 + 80048fc: 408b lsls r3, r1 + 80048fe: 4969 ldr r1, [pc, #420] ; (8004aa4 ) + 8004900: 4313 orrs r3, r2 + 8004902: 600b str r3, [r1, #0] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8004904: e0fd b.n 8004b02 + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8004906: f507 7300 add.w r3, r7, #512 ; 0x200 + 800490a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 800490e: 681b ldr r3, [r3, #0] + 8004910: 691b ldr r3, [r3, #16] + 8004912: 2b00 cmp r3, #0 + 8004914: f000 8088 beq.w 8004a28 + 8004918: 2301 movs r3, #1 + 800491a: f8c7 3168 str.w r3, [r7, #360] ; 0x168 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 800491e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168 + 8004922: fa93 f3a3 rbit r3, r3 + 8004926: f8c7 3164 str.w r3, [r7, #356] ; 0x164 + return result; + 800492a: f8d7 3164 ldr.w r3, [r7, #356] ; 0x164 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 800492e: fab3 f383 clz r3, r3 + 8004932: b2db uxtb r3, r3 + 8004934: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 + 8004938: f503 1384 add.w r3, r3, #1081344 ; 0x108000 + 800493c: 009b lsls r3, r3, #2 + 800493e: 461a mov r2, r3 + 8004940: 2301 movs r3, #1 + 8004942: 6013 str r3, [r2, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004944: f7fd fc8e bl 8002264 + 8004948: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 800494c: e00a b.n 8004964 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 800494e: f7fd fc89 bl 8002264 + 8004952: 4602 mov r2, r0 + 8004954: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8004958: 1ad3 subs r3, r2, r3 + 800495a: 2b02 cmp r3, #2 + 800495c: d902 bls.n 8004964 + { + return HAL_TIMEOUT; + 800495e: 2303 movs r3, #3 + 8004960: f000 bde2 b.w 8005528 + 8004964: 2302 movs r3, #2 + 8004966: f8c7 3160 str.w r3, [r7, #352] ; 0x160 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 800496a: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160 + 800496e: fa93 f3a3 rbit r3, r3 + 8004972: f8c7 315c str.w r3, [r7, #348] ; 0x15c + return result; + 8004976: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 800497a: fab3 f383 clz r3, r3 + 800497e: b2db uxtb r3, r3 + 8004980: 095b lsrs r3, r3, #5 + 8004982: b2db uxtb r3, r3 + 8004984: f043 0301 orr.w r3, r3, #1 + 8004988: b2db uxtb r3, r3 + 800498a: 2b01 cmp r3, #1 + 800498c: d102 bne.n 8004994 + 800498e: 4b45 ldr r3, [pc, #276] ; (8004aa4 ) + 8004990: 681b ldr r3, [r3, #0] + 8004992: e013 b.n 80049bc + 8004994: 2302 movs r3, #2 + 8004996: f8c7 3158 str.w r3, [r7, #344] ; 0x158 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 800499a: f8d7 3158 ldr.w r3, [r7, #344] ; 0x158 + 800499e: fa93 f3a3 rbit r3, r3 + 80049a2: f8c7 3154 str.w r3, [r7, #340] ; 0x154 + 80049a6: 2302 movs r3, #2 + 80049a8: f8c7 3150 str.w r3, [r7, #336] ; 0x150 + 80049ac: f8d7 3150 ldr.w r3, [r7, #336] ; 0x150 + 80049b0: fa93 f3a3 rbit r3, r3 + 80049b4: f8c7 314c str.w r3, [r7, #332] ; 0x14c + 80049b8: 4b3a ldr r3, [pc, #232] ; (8004aa4 ) + 80049ba: 6a5b ldr r3, [r3, #36] ; 0x24 + 80049bc: 2202 movs r2, #2 + 80049be: f8c7 2148 str.w r2, [r7, #328] ; 0x148 + 80049c2: f8d7 2148 ldr.w r2, [r7, #328] ; 0x148 + 80049c6: fa92 f2a2 rbit r2, r2 + 80049ca: f8c7 2144 str.w r2, [r7, #324] ; 0x144 + return result; + 80049ce: f8d7 2144 ldr.w r2, [r7, #324] ; 0x144 + 80049d2: fab2 f282 clz r2, r2 + 80049d6: b2d2 uxtb r2, r2 + 80049d8: f042 0220 orr.w r2, r2, #32 + 80049dc: b2d2 uxtb r2, r2 + 80049de: f002 021f and.w r2, r2, #31 + 80049e2: 2101 movs r1, #1 + 80049e4: fa01 f202 lsl.w r2, r1, r2 + 80049e8: 4013 ands r3, r2 + 80049ea: 2b00 cmp r3, #0 + 80049ec: d0af beq.n 800494e + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80049ee: 4b2d ldr r3, [pc, #180] ; (8004aa4 ) + 80049f0: 681b ldr r3, [r3, #0] + 80049f2: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 80049f6: f507 7300 add.w r3, r7, #512 ; 0x200 + 80049fa: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80049fe: 681b ldr r3, [r3, #0] + 8004a00: 695b ldr r3, [r3, #20] + 8004a02: 21f8 movs r1, #248 ; 0xf8 + 8004a04: f8c7 1140 str.w r1, [r7, #320] ; 0x140 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004a08: f8d7 1140 ldr.w r1, [r7, #320] ; 0x140 + 8004a0c: fa91 f1a1 rbit r1, r1 + 8004a10: f8c7 113c str.w r1, [r7, #316] ; 0x13c + return result; + 8004a14: f8d7 113c ldr.w r1, [r7, #316] ; 0x13c + 8004a18: fab1 f181 clz r1, r1 + 8004a1c: b2c9 uxtb r1, r1 + 8004a1e: 408b lsls r3, r1 + 8004a20: 4920 ldr r1, [pc, #128] ; (8004aa4 ) + 8004a22: 4313 orrs r3, r2 + 8004a24: 600b str r3, [r1, #0] + 8004a26: e06c b.n 8004b02 + 8004a28: 2301 movs r3, #1 + 8004a2a: f8c7 3138 str.w r3, [r7, #312] ; 0x138 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004a2e: f8d7 3138 ldr.w r3, [r7, #312] ; 0x138 + 8004a32: fa93 f3a3 rbit r3, r3 + 8004a36: f8c7 3134 str.w r3, [r7, #308] ; 0x134 + return result; + 8004a3a: f8d7 3134 ldr.w r3, [r7, #308] ; 0x134 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8004a3e: fab3 f383 clz r3, r3 + 8004a42: b2db uxtb r3, r3 + 8004a44: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 + 8004a48: f503 1384 add.w r3, r3, #1081344 ; 0x108000 + 8004a4c: 009b lsls r3, r3, #2 + 8004a4e: 461a mov r2, r3 + 8004a50: 2300 movs r3, #0 + 8004a52: 6013 str r3, [r2, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004a54: f7fd fc06 bl 8002264 + 8004a58: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8004a5c: e00a b.n 8004a74 + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8004a5e: f7fd fc01 bl 8002264 + 8004a62: 4602 mov r2, r0 + 8004a64: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8004a68: 1ad3 subs r3, r2, r3 + 8004a6a: 2b02 cmp r3, #2 + 8004a6c: d902 bls.n 8004a74 + { + return HAL_TIMEOUT; + 8004a6e: 2303 movs r3, #3 + 8004a70: f000 bd5a b.w 8005528 + 8004a74: 2302 movs r3, #2 + 8004a76: f8c7 3130 str.w r3, [r7, #304] ; 0x130 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004a7a: f8d7 3130 ldr.w r3, [r7, #304] ; 0x130 + 8004a7e: fa93 f3a3 rbit r3, r3 + 8004a82: f8c7 312c str.w r3, [r7, #300] ; 0x12c + return result; + 8004a86: f8d7 312c ldr.w r3, [r7, #300] ; 0x12c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 8004a8a: fab3 f383 clz r3, r3 + 8004a8e: b2db uxtb r3, r3 + 8004a90: 095b lsrs r3, r3, #5 + 8004a92: b2db uxtb r3, r3 + 8004a94: f043 0301 orr.w r3, r3, #1 + 8004a98: b2db uxtb r3, r3 + 8004a9a: 2b01 cmp r3, #1 + 8004a9c: d104 bne.n 8004aa8 + 8004a9e: 4b01 ldr r3, [pc, #4] ; (8004aa4 ) + 8004aa0: 681b ldr r3, [r3, #0] + 8004aa2: e015 b.n 8004ad0 + 8004aa4: 40021000 .word 0x40021000 + 8004aa8: 2302 movs r3, #2 + 8004aaa: f8c7 3128 str.w r3, [r7, #296] ; 0x128 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004aae: f8d7 3128 ldr.w r3, [r7, #296] ; 0x128 + 8004ab2: fa93 f3a3 rbit r3, r3 + 8004ab6: f8c7 3124 str.w r3, [r7, #292] ; 0x124 + 8004aba: 2302 movs r3, #2 + 8004abc: f8c7 3120 str.w r3, [r7, #288] ; 0x120 + 8004ac0: f8d7 3120 ldr.w r3, [r7, #288] ; 0x120 + 8004ac4: fa93 f3a3 rbit r3, r3 + 8004ac8: f8c7 311c str.w r3, [r7, #284] ; 0x11c + 8004acc: 4bc8 ldr r3, [pc, #800] ; (8004df0 ) + 8004ace: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004ad0: 2202 movs r2, #2 + 8004ad2: f8c7 2118 str.w r2, [r7, #280] ; 0x118 + 8004ad6: f8d7 2118 ldr.w r2, [r7, #280] ; 0x118 + 8004ada: fa92 f2a2 rbit r2, r2 + 8004ade: f8c7 2114 str.w r2, [r7, #276] ; 0x114 + return result; + 8004ae2: f8d7 2114 ldr.w r2, [r7, #276] ; 0x114 + 8004ae6: fab2 f282 clz r2, r2 + 8004aea: b2d2 uxtb r2, r2 + 8004aec: f042 0220 orr.w r2, r2, #32 + 8004af0: b2d2 uxtb r2, r2 + 8004af2: f002 021f and.w r2, r2, #31 + 8004af6: 2101 movs r1, #1 + 8004af8: fa01 f202 lsl.w r2, r1, r2 + 8004afc: 4013 ands r3, r2 + 8004afe: 2b00 cmp r3, #0 + 8004b00: d1ad bne.n 8004a5e + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8004b02: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004b06: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8004b0a: 681b ldr r3, [r3, #0] + 8004b0c: 681b ldr r3, [r3, #0] + 8004b0e: f003 0308 and.w r3, r3, #8 + 8004b12: 2b00 cmp r3, #0 + 8004b14: f000 8110 beq.w 8004d38 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8004b18: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004b1c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8004b20: 681b ldr r3, [r3, #0] + 8004b22: 699b ldr r3, [r3, #24] + 8004b24: 2b00 cmp r3, #0 + 8004b26: d079 beq.n 8004c1c + 8004b28: 2301 movs r3, #1 + 8004b2a: f8c7 3110 str.w r3, [r7, #272] ; 0x110 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004b2e: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110 + 8004b32: fa93 f3a3 rbit r3, r3 + 8004b36: f8c7 310c str.w r3, [r7, #268] ; 0x10c + return result; + 8004b3a: f8d7 310c ldr.w r3, [r7, #268] ; 0x10c + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8004b3e: fab3 f383 clz r3, r3 + 8004b42: b2db uxtb r3, r3 + 8004b44: 461a mov r2, r3 + 8004b46: 4bab ldr r3, [pc, #684] ; (8004df4 ) + 8004b48: 4413 add r3, r2 + 8004b4a: 009b lsls r3, r3, #2 + 8004b4c: 461a mov r2, r3 + 8004b4e: 2301 movs r3, #1 + 8004b50: 6013 str r3, [r2, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004b52: f7fd fb87 bl 8002264 + 8004b56: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8004b5a: e00a b.n 8004b72 + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8004b5c: f7fd fb82 bl 8002264 + 8004b60: 4602 mov r2, r0 + 8004b62: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8004b66: 1ad3 subs r3, r2, r3 + 8004b68: 2b02 cmp r3, #2 + 8004b6a: d902 bls.n 8004b72 + { + return HAL_TIMEOUT; + 8004b6c: 2303 movs r3, #3 + 8004b6e: f000 bcdb b.w 8005528 + 8004b72: 2302 movs r3, #2 + 8004b74: f8c7 3108 str.w r3, [r7, #264] ; 0x108 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004b78: f8d7 3108 ldr.w r3, [r7, #264] ; 0x108 + 8004b7c: fa93 f3a3 rbit r3, r3 + 8004b80: f8c7 3104 str.w r3, [r7, #260] ; 0x104 + 8004b84: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004b88: f5a3 7380 sub.w r3, r3, #256 ; 0x100 + 8004b8c: 2202 movs r2, #2 + 8004b8e: 601a str r2, [r3, #0] + 8004b90: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004b94: f5a3 7380 sub.w r3, r3, #256 ; 0x100 + 8004b98: 681b ldr r3, [r3, #0] + 8004b9a: fa93 f2a3 rbit r2, r3 + 8004b9e: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004ba2: f5a3 7382 sub.w r3, r3, #260 ; 0x104 + 8004ba6: 601a str r2, [r3, #0] + 8004ba8: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004bac: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 8004bb0: 2202 movs r2, #2 + 8004bb2: 601a str r2, [r3, #0] + 8004bb4: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004bb8: f5a3 7384 sub.w r3, r3, #264 ; 0x108 + 8004bbc: 681b ldr r3, [r3, #0] + 8004bbe: fa93 f2a3 rbit r2, r3 + 8004bc2: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004bc6: f5a3 7386 sub.w r3, r3, #268 ; 0x10c + 8004bca: 601a str r2, [r3, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8004bcc: 4b88 ldr r3, [pc, #544] ; (8004df0 ) + 8004bce: 6a5a ldr r2, [r3, #36] ; 0x24 + 8004bd0: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004bd4: f5a3 7388 sub.w r3, r3, #272 ; 0x110 + 8004bd8: 2102 movs r1, #2 + 8004bda: 6019 str r1, [r3, #0] + 8004bdc: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004be0: f5a3 7388 sub.w r3, r3, #272 ; 0x110 + 8004be4: 681b ldr r3, [r3, #0] + 8004be6: fa93 f1a3 rbit r1, r3 + 8004bea: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004bee: f5a3 738a sub.w r3, r3, #276 ; 0x114 + 8004bf2: 6019 str r1, [r3, #0] + return result; + 8004bf4: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004bf8: f5a3 738a sub.w r3, r3, #276 ; 0x114 + 8004bfc: 681b ldr r3, [r3, #0] + 8004bfe: fab3 f383 clz r3, r3 + 8004c02: b2db uxtb r3, r3 + 8004c04: f043 0360 orr.w r3, r3, #96 ; 0x60 + 8004c08: b2db uxtb r3, r3 + 8004c0a: f003 031f and.w r3, r3, #31 + 8004c0e: 2101 movs r1, #1 + 8004c10: fa01 f303 lsl.w r3, r1, r3 + 8004c14: 4013 ands r3, r2 + 8004c16: 2b00 cmp r3, #0 + 8004c18: d0a0 beq.n 8004b5c + 8004c1a: e08d b.n 8004d38 + 8004c1c: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004c20: f5a3 738c sub.w r3, r3, #280 ; 0x118 + 8004c24: 2201 movs r2, #1 + 8004c26: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004c28: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004c2c: f5a3 738c sub.w r3, r3, #280 ; 0x118 + 8004c30: 681b ldr r3, [r3, #0] + 8004c32: fa93 f2a3 rbit r2, r3 + 8004c36: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004c3a: f5a3 738e sub.w r3, r3, #284 ; 0x11c + 8004c3e: 601a str r2, [r3, #0] + return result; + 8004c40: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004c44: f5a3 738e sub.w r3, r3, #284 ; 0x11c + 8004c48: 681b ldr r3, [r3, #0] + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8004c4a: fab3 f383 clz r3, r3 + 8004c4e: b2db uxtb r3, r3 + 8004c50: 461a mov r2, r3 + 8004c52: 4b68 ldr r3, [pc, #416] ; (8004df4 ) + 8004c54: 4413 add r3, r2 + 8004c56: 009b lsls r3, r3, #2 + 8004c58: 461a mov r2, r3 + 8004c5a: 2300 movs r3, #0 + 8004c5c: 6013 str r3, [r2, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004c5e: f7fd fb01 bl 8002264 + 8004c62: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8004c66: e00a b.n 8004c7e + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8004c68: f7fd fafc bl 8002264 + 8004c6c: 4602 mov r2, r0 + 8004c6e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8004c72: 1ad3 subs r3, r2, r3 + 8004c74: 2b02 cmp r3, #2 + 8004c76: d902 bls.n 8004c7e + { + return HAL_TIMEOUT; + 8004c78: 2303 movs r3, #3 + 8004c7a: f000 bc55 b.w 8005528 + 8004c7e: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004c82: f5a3 7390 sub.w r3, r3, #288 ; 0x120 + 8004c86: 2202 movs r2, #2 + 8004c88: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004c8a: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004c8e: f5a3 7390 sub.w r3, r3, #288 ; 0x120 + 8004c92: 681b ldr r3, [r3, #0] + 8004c94: fa93 f2a3 rbit r2, r3 + 8004c98: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004c9c: f5a3 7392 sub.w r3, r3, #292 ; 0x124 + 8004ca0: 601a str r2, [r3, #0] + 8004ca2: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004ca6: f5a3 7394 sub.w r3, r3, #296 ; 0x128 + 8004caa: 2202 movs r2, #2 + 8004cac: 601a str r2, [r3, #0] + 8004cae: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004cb2: f5a3 7394 sub.w r3, r3, #296 ; 0x128 + 8004cb6: 681b ldr r3, [r3, #0] + 8004cb8: fa93 f2a3 rbit r2, r3 + 8004cbc: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004cc0: f5a3 7396 sub.w r3, r3, #300 ; 0x12c + 8004cc4: 601a str r2, [r3, #0] + 8004cc6: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004cca: f5a3 7398 sub.w r3, r3, #304 ; 0x130 + 8004cce: 2202 movs r2, #2 + 8004cd0: 601a str r2, [r3, #0] + 8004cd2: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004cd6: f5a3 7398 sub.w r3, r3, #304 ; 0x130 + 8004cda: 681b ldr r3, [r3, #0] + 8004cdc: fa93 f2a3 rbit r2, r3 + 8004ce0: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004ce4: f5a3 739a sub.w r3, r3, #308 ; 0x134 + 8004ce8: 601a str r2, [r3, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8004cea: 4b41 ldr r3, [pc, #260] ; (8004df0 ) + 8004cec: 6a5a ldr r2, [r3, #36] ; 0x24 + 8004cee: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004cf2: f5a3 739c sub.w r3, r3, #312 ; 0x138 + 8004cf6: 2102 movs r1, #2 + 8004cf8: 6019 str r1, [r3, #0] + 8004cfa: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004cfe: f5a3 739c sub.w r3, r3, #312 ; 0x138 + 8004d02: 681b ldr r3, [r3, #0] + 8004d04: fa93 f1a3 rbit r1, r3 + 8004d08: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004d0c: f5a3 739e sub.w r3, r3, #316 ; 0x13c + 8004d10: 6019 str r1, [r3, #0] + return result; + 8004d12: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004d16: f5a3 739e sub.w r3, r3, #316 ; 0x13c + 8004d1a: 681b ldr r3, [r3, #0] + 8004d1c: fab3 f383 clz r3, r3 + 8004d20: b2db uxtb r3, r3 + 8004d22: f043 0360 orr.w r3, r3, #96 ; 0x60 + 8004d26: b2db uxtb r3, r3 + 8004d28: f003 031f and.w r3, r3, #31 + 8004d2c: 2101 movs r1, #1 + 8004d2e: fa01 f303 lsl.w r3, r1, r3 + 8004d32: 4013 ands r3, r2 + 8004d34: 2b00 cmp r3, #0 + 8004d36: d197 bne.n 8004c68 + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8004d38: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004d3c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8004d40: 681b ldr r3, [r3, #0] + 8004d42: 681b ldr r3, [r3, #0] + 8004d44: f003 0304 and.w r3, r3, #4 + 8004d48: 2b00 cmp r3, #0 + 8004d4a: f000 81a1 beq.w 8005090 + { + FlagStatus pwrclkchanged = RESET; + 8004d4e: 2300 movs r3, #0 + 8004d50: f887 31ff strb.w r3, [r7, #511] ; 0x1ff + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8004d54: 4b26 ldr r3, [pc, #152] ; (8004df0 ) + 8004d56: 69db ldr r3, [r3, #28] + 8004d58: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8004d5c: 2b00 cmp r3, #0 + 8004d5e: d116 bne.n 8004d8e + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8004d60: 4b23 ldr r3, [pc, #140] ; (8004df0 ) + 8004d62: 69db ldr r3, [r3, #28] + 8004d64: 4a22 ldr r2, [pc, #136] ; (8004df0 ) + 8004d66: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8004d6a: 61d3 str r3, [r2, #28] + 8004d6c: 4b20 ldr r3, [pc, #128] ; (8004df0 ) + 8004d6e: 69db ldr r3, [r3, #28] + 8004d70: f003 5280 and.w r2, r3, #268435456 ; 0x10000000 + 8004d74: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004d78: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8 + 8004d7c: 601a str r2, [r3, #0] + 8004d7e: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004d82: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8 + 8004d86: 681b ldr r3, [r3, #0] + pwrclkchanged = SET; + 8004d88: 2301 movs r3, #1 + 8004d8a: f887 31ff strb.w r3, [r7, #511] ; 0x1ff + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8004d8e: 4b1a ldr r3, [pc, #104] ; (8004df8 ) + 8004d90: 681b ldr r3, [r3, #0] + 8004d92: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004d96: 2b00 cmp r3, #0 + 8004d98: d11a bne.n 8004dd0 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8004d9a: 4b17 ldr r3, [pc, #92] ; (8004df8 ) + 8004d9c: 681b ldr r3, [r3, #0] + 8004d9e: 4a16 ldr r2, [pc, #88] ; (8004df8 ) + 8004da0: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8004da4: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8004da6: f7fd fa5d bl 8002264 + 8004daa: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8004dae: e009 b.n 8004dc4 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8004db0: f7fd fa58 bl 8002264 + 8004db4: 4602 mov r2, r0 + 8004db6: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8004dba: 1ad3 subs r3, r2, r3 + 8004dbc: 2b64 cmp r3, #100 ; 0x64 + 8004dbe: d901 bls.n 8004dc4 + { + return HAL_TIMEOUT; + 8004dc0: 2303 movs r3, #3 + 8004dc2: e3b1 b.n 8005528 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8004dc4: 4b0c ldr r3, [pc, #48] ; (8004df8 ) + 8004dc6: 681b ldr r3, [r3, #0] + 8004dc8: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004dcc: 2b00 cmp r3, #0 + 8004dce: d0ef beq.n 8004db0 + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8004dd0: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004dd4: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8004dd8: 681b ldr r3, [r3, #0] + 8004dda: 68db ldr r3, [r3, #12] + 8004ddc: 2b01 cmp r3, #1 + 8004dde: d10d bne.n 8004dfc + 8004de0: 4b03 ldr r3, [pc, #12] ; (8004df0 ) + 8004de2: 6a1b ldr r3, [r3, #32] + 8004de4: 4a02 ldr r2, [pc, #8] ; (8004df0 ) + 8004de6: f043 0301 orr.w r3, r3, #1 + 8004dea: 6213 str r3, [r2, #32] + 8004dec: e03c b.n 8004e68 + 8004dee: bf00 nop + 8004df0: 40021000 .word 0x40021000 + 8004df4: 10908120 .word 0x10908120 + 8004df8: 40007000 .word 0x40007000 + 8004dfc: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004e00: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8004e04: 681b ldr r3, [r3, #0] + 8004e06: 68db ldr r3, [r3, #12] + 8004e08: 2b00 cmp r3, #0 + 8004e0a: d10c bne.n 8004e26 + 8004e0c: 4bc1 ldr r3, [pc, #772] ; (8005114 ) + 8004e0e: 6a1b ldr r3, [r3, #32] + 8004e10: 4ac0 ldr r2, [pc, #768] ; (8005114 ) + 8004e12: f023 0301 bic.w r3, r3, #1 + 8004e16: 6213 str r3, [r2, #32] + 8004e18: 4bbe ldr r3, [pc, #760] ; (8005114 ) + 8004e1a: 6a1b ldr r3, [r3, #32] + 8004e1c: 4abd ldr r2, [pc, #756] ; (8005114 ) + 8004e1e: f023 0304 bic.w r3, r3, #4 + 8004e22: 6213 str r3, [r2, #32] + 8004e24: e020 b.n 8004e68 + 8004e26: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004e2a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8004e2e: 681b ldr r3, [r3, #0] + 8004e30: 68db ldr r3, [r3, #12] + 8004e32: 2b05 cmp r3, #5 + 8004e34: d10c bne.n 8004e50 + 8004e36: 4bb7 ldr r3, [pc, #732] ; (8005114 ) + 8004e38: 6a1b ldr r3, [r3, #32] + 8004e3a: 4ab6 ldr r2, [pc, #728] ; (8005114 ) + 8004e3c: f043 0304 orr.w r3, r3, #4 + 8004e40: 6213 str r3, [r2, #32] + 8004e42: 4bb4 ldr r3, [pc, #720] ; (8005114 ) + 8004e44: 6a1b ldr r3, [r3, #32] + 8004e46: 4ab3 ldr r2, [pc, #716] ; (8005114 ) + 8004e48: f043 0301 orr.w r3, r3, #1 + 8004e4c: 6213 str r3, [r2, #32] + 8004e4e: e00b b.n 8004e68 + 8004e50: 4bb0 ldr r3, [pc, #704] ; (8005114 ) + 8004e52: 6a1b ldr r3, [r3, #32] + 8004e54: 4aaf ldr r2, [pc, #700] ; (8005114 ) + 8004e56: f023 0301 bic.w r3, r3, #1 + 8004e5a: 6213 str r3, [r2, #32] + 8004e5c: 4bad ldr r3, [pc, #692] ; (8005114 ) + 8004e5e: 6a1b ldr r3, [r3, #32] + 8004e60: 4aac ldr r2, [pc, #688] ; (8005114 ) + 8004e62: f023 0304 bic.w r3, r3, #4 + 8004e66: 6213 str r3, [r2, #32] + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8004e68: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004e6c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8004e70: 681b ldr r3, [r3, #0] + 8004e72: 68db ldr r3, [r3, #12] + 8004e74: 2b00 cmp r3, #0 + 8004e76: f000 8081 beq.w 8004f7c + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004e7a: f7fd f9f3 bl 8002264 + 8004e7e: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8004e82: e00b b.n 8004e9c + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8004e84: f7fd f9ee bl 8002264 + 8004e88: 4602 mov r2, r0 + 8004e8a: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8004e8e: 1ad3 subs r3, r2, r3 + 8004e90: f241 3288 movw r2, #5000 ; 0x1388 + 8004e94: 4293 cmp r3, r2 + 8004e96: d901 bls.n 8004e9c + { + return HAL_TIMEOUT; + 8004e98: 2303 movs r3, #3 + 8004e9a: e345 b.n 8005528 + 8004e9c: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004ea0: f5a3 73a0 sub.w r3, r3, #320 ; 0x140 + 8004ea4: 2202 movs r2, #2 + 8004ea6: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004ea8: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004eac: f5a3 73a0 sub.w r3, r3, #320 ; 0x140 + 8004eb0: 681b ldr r3, [r3, #0] + 8004eb2: fa93 f2a3 rbit r2, r3 + 8004eb6: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004eba: f5a3 73a2 sub.w r3, r3, #324 ; 0x144 + 8004ebe: 601a str r2, [r3, #0] + 8004ec0: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004ec4: f5a3 73a4 sub.w r3, r3, #328 ; 0x148 + 8004ec8: 2202 movs r2, #2 + 8004eca: 601a str r2, [r3, #0] + 8004ecc: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004ed0: f5a3 73a4 sub.w r3, r3, #328 ; 0x148 + 8004ed4: 681b ldr r3, [r3, #0] + 8004ed6: fa93 f2a3 rbit r2, r3 + 8004eda: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004ede: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c + 8004ee2: 601a str r2, [r3, #0] + return result; + 8004ee4: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004ee8: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c + 8004eec: 681b ldr r3, [r3, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8004eee: fab3 f383 clz r3, r3 + 8004ef2: b2db uxtb r3, r3 + 8004ef4: 095b lsrs r3, r3, #5 + 8004ef6: b2db uxtb r3, r3 + 8004ef8: f043 0302 orr.w r3, r3, #2 + 8004efc: b2db uxtb r3, r3 + 8004efe: 2b02 cmp r3, #2 + 8004f00: d102 bne.n 8004f08 + 8004f02: 4b84 ldr r3, [pc, #528] ; (8005114 ) + 8004f04: 6a1b ldr r3, [r3, #32] + 8004f06: e013 b.n 8004f30 + 8004f08: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004f0c: f5a3 73a8 sub.w r3, r3, #336 ; 0x150 + 8004f10: 2202 movs r2, #2 + 8004f12: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004f14: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004f18: f5a3 73a8 sub.w r3, r3, #336 ; 0x150 + 8004f1c: 681b ldr r3, [r3, #0] + 8004f1e: fa93 f2a3 rbit r2, r3 + 8004f22: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004f26: f5a3 73aa sub.w r3, r3, #340 ; 0x154 + 8004f2a: 601a str r2, [r3, #0] + 8004f2c: 4b79 ldr r3, [pc, #484] ; (8005114 ) + 8004f2e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004f30: f507 7200 add.w r2, r7, #512 ; 0x200 + 8004f34: f5a2 72ac sub.w r2, r2, #344 ; 0x158 + 8004f38: 2102 movs r1, #2 + 8004f3a: 6011 str r1, [r2, #0] + 8004f3c: f507 7200 add.w r2, r7, #512 ; 0x200 + 8004f40: f5a2 72ac sub.w r2, r2, #344 ; 0x158 + 8004f44: 6812 ldr r2, [r2, #0] + 8004f46: fa92 f1a2 rbit r1, r2 + 8004f4a: f507 7200 add.w r2, r7, #512 ; 0x200 + 8004f4e: f5a2 72ae sub.w r2, r2, #348 ; 0x15c + 8004f52: 6011 str r1, [r2, #0] + return result; + 8004f54: f507 7200 add.w r2, r7, #512 ; 0x200 + 8004f58: f5a2 72ae sub.w r2, r2, #348 ; 0x15c + 8004f5c: 6812 ldr r2, [r2, #0] + 8004f5e: fab2 f282 clz r2, r2 + 8004f62: b2d2 uxtb r2, r2 + 8004f64: f042 0240 orr.w r2, r2, #64 ; 0x40 + 8004f68: b2d2 uxtb r2, r2 + 8004f6a: f002 021f and.w r2, r2, #31 + 8004f6e: 2101 movs r1, #1 + 8004f70: fa01 f202 lsl.w r2, r1, r2 + 8004f74: 4013 ands r3, r2 + 8004f76: 2b00 cmp r3, #0 + 8004f78: d084 beq.n 8004e84 + 8004f7a: e07f b.n 800507c + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004f7c: f7fd f972 bl 8002264 + 8004f80: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8004f84: e00b b.n 8004f9e + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8004f86: f7fd f96d bl 8002264 + 8004f8a: 4602 mov r2, r0 + 8004f8c: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8004f90: 1ad3 subs r3, r2, r3 + 8004f92: f241 3288 movw r2, #5000 ; 0x1388 + 8004f96: 4293 cmp r3, r2 + 8004f98: d901 bls.n 8004f9e + { + return HAL_TIMEOUT; + 8004f9a: 2303 movs r3, #3 + 8004f9c: e2c4 b.n 8005528 + 8004f9e: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004fa2: f5a3 73b0 sub.w r3, r3, #352 ; 0x160 + 8004fa6: 2202 movs r2, #2 + 8004fa8: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8004faa: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004fae: f5a3 73b0 sub.w r3, r3, #352 ; 0x160 + 8004fb2: 681b ldr r3, [r3, #0] + 8004fb4: fa93 f2a3 rbit r2, r3 + 8004fb8: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004fbc: f5a3 73b2 sub.w r3, r3, #356 ; 0x164 + 8004fc0: 601a str r2, [r3, #0] + 8004fc2: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004fc6: f5a3 73b4 sub.w r3, r3, #360 ; 0x168 + 8004fca: 2202 movs r2, #2 + 8004fcc: 601a str r2, [r3, #0] + 8004fce: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004fd2: f5a3 73b4 sub.w r3, r3, #360 ; 0x168 + 8004fd6: 681b ldr r3, [r3, #0] + 8004fd8: fa93 f2a3 rbit r2, r3 + 8004fdc: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004fe0: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c + 8004fe4: 601a str r2, [r3, #0] + return result; + 8004fe6: f507 7300 add.w r3, r7, #512 ; 0x200 + 8004fea: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c + 8004fee: 681b ldr r3, [r3, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8004ff0: fab3 f383 clz r3, r3 + 8004ff4: b2db uxtb r3, r3 + 8004ff6: 095b lsrs r3, r3, #5 + 8004ff8: b2db uxtb r3, r3 + 8004ffa: f043 0302 orr.w r3, r3, #2 + 8004ffe: b2db uxtb r3, r3 + 8005000: 2b02 cmp r3, #2 + 8005002: d102 bne.n 800500a + 8005004: 4b43 ldr r3, [pc, #268] ; (8005114 ) + 8005006: 6a1b ldr r3, [r3, #32] + 8005008: e013 b.n 8005032 + 800500a: f507 7300 add.w r3, r7, #512 ; 0x200 + 800500e: f5a3 73b8 sub.w r3, r3, #368 ; 0x170 + 8005012: 2202 movs r2, #2 + 8005014: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005016: f507 7300 add.w r3, r7, #512 ; 0x200 + 800501a: f5a3 73b8 sub.w r3, r3, #368 ; 0x170 + 800501e: 681b ldr r3, [r3, #0] + 8005020: fa93 f2a3 rbit r2, r3 + 8005024: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005028: f5a3 73ba sub.w r3, r3, #372 ; 0x174 + 800502c: 601a str r2, [r3, #0] + 800502e: 4b39 ldr r3, [pc, #228] ; (8005114 ) + 8005030: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005032: f507 7200 add.w r2, r7, #512 ; 0x200 + 8005036: f5a2 72bc sub.w r2, r2, #376 ; 0x178 + 800503a: 2102 movs r1, #2 + 800503c: 6011 str r1, [r2, #0] + 800503e: f507 7200 add.w r2, r7, #512 ; 0x200 + 8005042: f5a2 72bc sub.w r2, r2, #376 ; 0x178 + 8005046: 6812 ldr r2, [r2, #0] + 8005048: fa92 f1a2 rbit r1, r2 + 800504c: f507 7200 add.w r2, r7, #512 ; 0x200 + 8005050: f5a2 72be sub.w r2, r2, #380 ; 0x17c + 8005054: 6011 str r1, [r2, #0] + return result; + 8005056: f507 7200 add.w r2, r7, #512 ; 0x200 + 800505a: f5a2 72be sub.w r2, r2, #380 ; 0x17c + 800505e: 6812 ldr r2, [r2, #0] + 8005060: fab2 f282 clz r2, r2 + 8005064: b2d2 uxtb r2, r2 + 8005066: f042 0240 orr.w r2, r2, #64 ; 0x40 + 800506a: b2d2 uxtb r2, r2 + 800506c: f002 021f and.w r2, r2, #31 + 8005070: 2101 movs r1, #1 + 8005072: fa01 f202 lsl.w r2, r1, r2 + 8005076: 4013 ands r3, r2 + 8005078: 2b00 cmp r3, #0 + 800507a: d184 bne.n 8004f86 + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 800507c: f897 31ff ldrb.w r3, [r7, #511] ; 0x1ff + 8005080: 2b01 cmp r3, #1 + 8005082: d105 bne.n 8005090 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8005084: 4b23 ldr r3, [pc, #140] ; (8005114 ) + 8005086: 69db ldr r3, [r3, #28] + 8005088: 4a22 ldr r2, [pc, #136] ; (8005114 ) + 800508a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 800508e: 61d3 str r3, [r2, #28] + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8005090: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005094: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8005098: 681b ldr r3, [r3, #0] + 800509a: 69db ldr r3, [r3, #28] + 800509c: 2b00 cmp r3, #0 + 800509e: f000 8242 beq.w 8005526 + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 80050a2: 4b1c ldr r3, [pc, #112] ; (8005114 ) + 80050a4: 685b ldr r3, [r3, #4] + 80050a6: f003 030c and.w r3, r3, #12 + 80050aa: 2b08 cmp r3, #8 + 80050ac: f000 8213 beq.w 80054d6 + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 80050b0: f507 7300 add.w r3, r7, #512 ; 0x200 + 80050b4: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80050b8: 681b ldr r3, [r3, #0] + 80050ba: 69db ldr r3, [r3, #28] + 80050bc: 2b02 cmp r3, #2 + 80050be: f040 8162 bne.w 8005386 + 80050c2: f507 7300 add.w r3, r7, #512 ; 0x200 + 80050c6: f5a3 73c0 sub.w r3, r3, #384 ; 0x180 + 80050ca: f04f 7280 mov.w r2, #16777216 ; 0x1000000 + 80050ce: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80050d0: f507 7300 add.w r3, r7, #512 ; 0x200 + 80050d4: f5a3 73c0 sub.w r3, r3, #384 ; 0x180 + 80050d8: 681b ldr r3, [r3, #0] + 80050da: fa93 f2a3 rbit r2, r3 + 80050de: f507 7300 add.w r3, r7, #512 ; 0x200 + 80050e2: f5a3 73c2 sub.w r3, r3, #388 ; 0x184 + 80050e6: 601a str r2, [r3, #0] + return result; + 80050e8: f507 7300 add.w r3, r7, #512 ; 0x200 + 80050ec: f5a3 73c2 sub.w r3, r3, #388 ; 0x184 + 80050f0: 681b ldr r3, [r3, #0] +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80050f2: fab3 f383 clz r3, r3 + 80050f6: b2db uxtb r3, r3 + 80050f8: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 + 80050fc: f503 1384 add.w r3, r3, #1081344 ; 0x108000 + 8005100: 009b lsls r3, r3, #2 + 8005102: 461a mov r2, r3 + 8005104: 2300 movs r3, #0 + 8005106: 6013 str r3, [r2, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005108: f7fd f8ac bl 8002264 + 800510c: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8005110: e00c b.n 800512c + 8005112: bf00 nop + 8005114: 40021000 .word 0x40021000 + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8005118: f7fd f8a4 bl 8002264 + 800511c: 4602 mov r2, r0 + 800511e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8005122: 1ad3 subs r3, r2, r3 + 8005124: 2b02 cmp r3, #2 + 8005126: d901 bls.n 800512c + { + return HAL_TIMEOUT; + 8005128: 2303 movs r3, #3 + 800512a: e1fd b.n 8005528 + 800512c: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005130: f5a3 73c4 sub.w r3, r3, #392 ; 0x188 + 8005134: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 8005138: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 800513a: f507 7300 add.w r3, r7, #512 ; 0x200 + 800513e: f5a3 73c4 sub.w r3, r3, #392 ; 0x188 + 8005142: 681b ldr r3, [r3, #0] + 8005144: fa93 f2a3 rbit r2, r3 + 8005148: f507 7300 add.w r3, r7, #512 ; 0x200 + 800514c: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c + 8005150: 601a str r2, [r3, #0] + return result; + 8005152: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005156: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c + 800515a: 681b ldr r3, [r3, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 800515c: fab3 f383 clz r3, r3 + 8005160: b2db uxtb r3, r3 + 8005162: 095b lsrs r3, r3, #5 + 8005164: b2db uxtb r3, r3 + 8005166: f043 0301 orr.w r3, r3, #1 + 800516a: b2db uxtb r3, r3 + 800516c: 2b01 cmp r3, #1 + 800516e: d102 bne.n 8005176 + 8005170: 4bb0 ldr r3, [pc, #704] ; (8005434 ) + 8005172: 681b ldr r3, [r3, #0] + 8005174: e027 b.n 80051c6 + 8005176: f507 7300 add.w r3, r7, #512 ; 0x200 + 800517a: f5a3 73c8 sub.w r3, r3, #400 ; 0x190 + 800517e: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 8005182: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005184: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005188: f5a3 73c8 sub.w r3, r3, #400 ; 0x190 + 800518c: 681b ldr r3, [r3, #0] + 800518e: fa93 f2a3 rbit r2, r3 + 8005192: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005196: f5a3 73ca sub.w r3, r3, #404 ; 0x194 + 800519a: 601a str r2, [r3, #0] + 800519c: f507 7300 add.w r3, r7, #512 ; 0x200 + 80051a0: f5a3 73cc sub.w r3, r3, #408 ; 0x198 + 80051a4: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 80051a8: 601a str r2, [r3, #0] + 80051aa: f507 7300 add.w r3, r7, #512 ; 0x200 + 80051ae: f5a3 73cc sub.w r3, r3, #408 ; 0x198 + 80051b2: 681b ldr r3, [r3, #0] + 80051b4: fa93 f2a3 rbit r2, r3 + 80051b8: f507 7300 add.w r3, r7, #512 ; 0x200 + 80051bc: f5a3 73ce sub.w r3, r3, #412 ; 0x19c + 80051c0: 601a str r2, [r3, #0] + 80051c2: 4b9c ldr r3, [pc, #624] ; (8005434 ) + 80051c4: 6a5b ldr r3, [r3, #36] ; 0x24 + 80051c6: f507 7200 add.w r2, r7, #512 ; 0x200 + 80051ca: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0 + 80051ce: f04f 7100 mov.w r1, #33554432 ; 0x2000000 + 80051d2: 6011 str r1, [r2, #0] + 80051d4: f507 7200 add.w r2, r7, #512 ; 0x200 + 80051d8: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0 + 80051dc: 6812 ldr r2, [r2, #0] + 80051de: fa92 f1a2 rbit r1, r2 + 80051e2: f507 7200 add.w r2, r7, #512 ; 0x200 + 80051e6: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4 + 80051ea: 6011 str r1, [r2, #0] + return result; + 80051ec: f507 7200 add.w r2, r7, #512 ; 0x200 + 80051f0: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4 + 80051f4: 6812 ldr r2, [r2, #0] + 80051f6: fab2 f282 clz r2, r2 + 80051fa: b2d2 uxtb r2, r2 + 80051fc: f042 0220 orr.w r2, r2, #32 + 8005200: b2d2 uxtb r2, r2 + 8005202: f002 021f and.w r2, r2, #31 + 8005206: 2101 movs r1, #1 + 8005208: fa01 f202 lsl.w r2, r1, r2 + 800520c: 4013 ands r3, r2 + 800520e: 2b00 cmp r3, #0 + 8005210: d182 bne.n 8005118 + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PREDIV, + RCC_OscInitStruct->PLL.PLLMUL); +#else + /* Configure the main PLL clock source and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8005212: 4b88 ldr r3, [pc, #544] ; (8005434 ) + 8005214: 685b ldr r3, [r3, #4] + 8005216: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000 + 800521a: f507 7300 add.w r3, r7, #512 ; 0x200 + 800521e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8005222: 681b ldr r3, [r3, #0] + 8005224: 6a59 ldr r1, [r3, #36] ; 0x24 + 8005226: f507 7300 add.w r3, r7, #512 ; 0x200 + 800522a: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 800522e: 681b ldr r3, [r3, #0] + 8005230: 6a1b ldr r3, [r3, #32] + 8005232: 430b orrs r3, r1 + 8005234: 497f ldr r1, [pc, #508] ; (8005434 ) + 8005236: 4313 orrs r3, r2 + 8005238: 604b str r3, [r1, #4] + 800523a: f507 7300 add.w r3, r7, #512 ; 0x200 + 800523e: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8 + 8005242: f04f 7280 mov.w r2, #16777216 ; 0x1000000 + 8005246: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005248: f507 7300 add.w r3, r7, #512 ; 0x200 + 800524c: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8 + 8005250: 681b ldr r3, [r3, #0] + 8005252: fa93 f2a3 rbit r2, r3 + 8005256: f507 7300 add.w r3, r7, #512 ; 0x200 + 800525a: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac + 800525e: 601a str r2, [r3, #0] + return result; + 8005260: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005264: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac + 8005268: 681b ldr r3, [r3, #0] + RCC_OscInitStruct->PLL.PLLMUL); +#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 800526a: fab3 f383 clz r3, r3 + 800526e: b2db uxtb r3, r3 + 8005270: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 + 8005274: f503 1384 add.w r3, r3, #1081344 ; 0x108000 + 8005278: 009b lsls r3, r3, #2 + 800527a: 461a mov r2, r3 + 800527c: 2301 movs r3, #1 + 800527e: 6013 str r3, [r2, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005280: f7fc fff0 bl 8002264 + 8005284: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8005288: e009 b.n 800529e + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 800528a: f7fc ffeb bl 8002264 + 800528e: 4602 mov r2, r0 + 8005290: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 8005294: 1ad3 subs r3, r2, r3 + 8005296: 2b02 cmp r3, #2 + 8005298: d901 bls.n 800529e + { + return HAL_TIMEOUT; + 800529a: 2303 movs r3, #3 + 800529c: e144 b.n 8005528 + 800529e: f507 7300 add.w r3, r7, #512 ; 0x200 + 80052a2: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0 + 80052a6: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 80052aa: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80052ac: f507 7300 add.w r3, r7, #512 ; 0x200 + 80052b0: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0 + 80052b4: 681b ldr r3, [r3, #0] + 80052b6: fa93 f2a3 rbit r2, r3 + 80052ba: f507 7300 add.w r3, r7, #512 ; 0x200 + 80052be: f5a3 73da sub.w r3, r3, #436 ; 0x1b4 + 80052c2: 601a str r2, [r3, #0] + return result; + 80052c4: f507 7300 add.w r3, r7, #512 ; 0x200 + 80052c8: f5a3 73da sub.w r3, r3, #436 ; 0x1b4 + 80052cc: 681b ldr r3, [r3, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 80052ce: fab3 f383 clz r3, r3 + 80052d2: b2db uxtb r3, r3 + 80052d4: 095b lsrs r3, r3, #5 + 80052d6: b2db uxtb r3, r3 + 80052d8: f043 0301 orr.w r3, r3, #1 + 80052dc: b2db uxtb r3, r3 + 80052de: 2b01 cmp r3, #1 + 80052e0: d102 bne.n 80052e8 + 80052e2: 4b54 ldr r3, [pc, #336] ; (8005434 ) + 80052e4: 681b ldr r3, [r3, #0] + 80052e6: e027 b.n 8005338 + 80052e8: f507 7300 add.w r3, r7, #512 ; 0x200 + 80052ec: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8 + 80052f0: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 80052f4: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80052f6: f507 7300 add.w r3, r7, #512 ; 0x200 + 80052fa: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8 + 80052fe: 681b ldr r3, [r3, #0] + 8005300: fa93 f2a3 rbit r2, r3 + 8005304: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005308: f5a3 73de sub.w r3, r3, #444 ; 0x1bc + 800530c: 601a str r2, [r3, #0] + 800530e: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005312: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0 + 8005316: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 800531a: 601a str r2, [r3, #0] + 800531c: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005320: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0 + 8005324: 681b ldr r3, [r3, #0] + 8005326: fa93 f2a3 rbit r2, r3 + 800532a: f507 7300 add.w r3, r7, #512 ; 0x200 + 800532e: f5a3 73e2 sub.w r3, r3, #452 ; 0x1c4 + 8005332: 601a str r2, [r3, #0] + 8005334: 4b3f ldr r3, [pc, #252] ; (8005434 ) + 8005336: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005338: f507 7200 add.w r2, r7, #512 ; 0x200 + 800533c: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8 + 8005340: f04f 7100 mov.w r1, #33554432 ; 0x2000000 + 8005344: 6011 str r1, [r2, #0] + 8005346: f507 7200 add.w r2, r7, #512 ; 0x200 + 800534a: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8 + 800534e: 6812 ldr r2, [r2, #0] + 8005350: fa92 f1a2 rbit r1, r2 + 8005354: f507 7200 add.w r2, r7, #512 ; 0x200 + 8005358: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc + 800535c: 6011 str r1, [r2, #0] + return result; + 800535e: f507 7200 add.w r2, r7, #512 ; 0x200 + 8005362: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc + 8005366: 6812 ldr r2, [r2, #0] + 8005368: fab2 f282 clz r2, r2 + 800536c: b2d2 uxtb r2, r2 + 800536e: f042 0220 orr.w r2, r2, #32 + 8005372: b2d2 uxtb r2, r2 + 8005374: f002 021f and.w r2, r2, #31 + 8005378: 2101 movs r1, #1 + 800537a: fa01 f202 lsl.w r2, r1, r2 + 800537e: 4013 ands r3, r2 + 8005380: 2b00 cmp r3, #0 + 8005382: d082 beq.n 800528a + 8005384: e0cf b.n 8005526 + 8005386: f507 7300 add.w r3, r7, #512 ; 0x200 + 800538a: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0 + 800538e: f04f 7280 mov.w r2, #16777216 ; 0x1000000 + 8005392: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005394: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005398: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0 + 800539c: 681b ldr r3, [r3, #0] + 800539e: fa93 f2a3 rbit r2, r3 + 80053a2: f507 7300 add.w r3, r7, #512 ; 0x200 + 80053a6: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4 + 80053aa: 601a str r2, [r3, #0] + return result; + 80053ac: f507 7300 add.w r3, r7, #512 ; 0x200 + 80053b0: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4 + 80053b4: 681b ldr r3, [r3, #0] + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80053b6: fab3 f383 clz r3, r3 + 80053ba: b2db uxtb r3, r3 + 80053bc: f103 5384 add.w r3, r3, #276824064 ; 0x10800000 + 80053c0: f503 1384 add.w r3, r3, #1081344 ; 0x108000 + 80053c4: 009b lsls r3, r3, #2 + 80053c6: 461a mov r2, r3 + 80053c8: 2300 movs r3, #0 + 80053ca: 6013 str r3, [r2, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 80053cc: f7fc ff4a bl 8002264 + 80053d0: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8 + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80053d4: e009 b.n 80053ea + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 80053d6: f7fc ff45 bl 8002264 + 80053da: 4602 mov r2, r0 + 80053dc: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8 + 80053e0: 1ad3 subs r3, r2, r3 + 80053e2: 2b02 cmp r3, #2 + 80053e4: d901 bls.n 80053ea + { + return HAL_TIMEOUT; + 80053e6: 2303 movs r3, #3 + 80053e8: e09e b.n 8005528 + 80053ea: f507 7300 add.w r3, r7, #512 ; 0x200 + 80053ee: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8 + 80053f2: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 80053f6: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80053f8: f507 7300 add.w r3, r7, #512 ; 0x200 + 80053fc: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8 + 8005400: 681b ldr r3, [r3, #0] + 8005402: fa93 f2a3 rbit r2, r3 + 8005406: f507 7300 add.w r3, r7, #512 ; 0x200 + 800540a: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc + 800540e: 601a str r2, [r3, #0] + return result; + 8005410: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005414: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc + 8005418: 681b ldr r3, [r3, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 800541a: fab3 f383 clz r3, r3 + 800541e: b2db uxtb r3, r3 + 8005420: 095b lsrs r3, r3, #5 + 8005422: b2db uxtb r3, r3 + 8005424: f043 0301 orr.w r3, r3, #1 + 8005428: b2db uxtb r3, r3 + 800542a: 2b01 cmp r3, #1 + 800542c: d104 bne.n 8005438 + 800542e: 4b01 ldr r3, [pc, #4] ; (8005434 ) + 8005430: 681b ldr r3, [r3, #0] + 8005432: e029 b.n 8005488 + 8005434: 40021000 .word 0x40021000 + 8005438: f507 7300 add.w r3, r7, #512 ; 0x200 + 800543c: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0 + 8005440: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 8005444: 601a str r2, [r3, #0] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005446: f507 7300 add.w r3, r7, #512 ; 0x200 + 800544a: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0 + 800544e: 681b ldr r3, [r3, #0] + 8005450: fa93 f2a3 rbit r2, r3 + 8005454: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005458: f5a3 73f2 sub.w r3, r3, #484 ; 0x1e4 + 800545c: 601a str r2, [r3, #0] + 800545e: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005462: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8 + 8005466: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 800546a: 601a str r2, [r3, #0] + 800546c: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005470: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8 + 8005474: 681b ldr r3, [r3, #0] + 8005476: fa93 f2a3 rbit r2, r3 + 800547a: f507 7300 add.w r3, r7, #512 ; 0x200 + 800547e: f5a3 73f6 sub.w r3, r3, #492 ; 0x1ec + 8005482: 601a str r2, [r3, #0] + 8005484: 4b2b ldr r3, [pc, #172] ; (8005534 ) + 8005486: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005488: f507 7200 add.w r2, r7, #512 ; 0x200 + 800548c: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0 + 8005490: f04f 7100 mov.w r1, #33554432 ; 0x2000000 + 8005494: 6011 str r1, [r2, #0] + 8005496: f507 7200 add.w r2, r7, #512 ; 0x200 + 800549a: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0 + 800549e: 6812 ldr r2, [r2, #0] + 80054a0: fa92 f1a2 rbit r1, r2 + 80054a4: f507 7200 add.w r2, r7, #512 ; 0x200 + 80054a8: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4 + 80054ac: 6011 str r1, [r2, #0] + return result; + 80054ae: f507 7200 add.w r2, r7, #512 ; 0x200 + 80054b2: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4 + 80054b6: 6812 ldr r2, [r2, #0] + 80054b8: fab2 f282 clz r2, r2 + 80054bc: b2d2 uxtb r2, r2 + 80054be: f042 0220 orr.w r2, r2, #32 + 80054c2: b2d2 uxtb r2, r2 + 80054c4: f002 021f and.w r2, r2, #31 + 80054c8: 2101 movs r1, #1 + 80054ca: fa01 f202 lsl.w r2, r1, r2 + 80054ce: 4013 ands r3, r2 + 80054d0: 2b00 cmp r3, #0 + 80054d2: d180 bne.n 80053d6 + 80054d4: e027 b.n 8005526 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 80054d6: f507 7300 add.w r3, r7, #512 ; 0x200 + 80054da: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 80054de: 681b ldr r3, [r3, #0] + 80054e0: 69db ldr r3, [r3, #28] + 80054e2: 2b01 cmp r3, #1 + 80054e4: d101 bne.n 80054ea + { + return HAL_ERROR; + 80054e6: 2301 movs r3, #1 + 80054e8: e01e b.n 8005528 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; + 80054ea: 4b12 ldr r3, [pc, #72] ; (8005534 ) + 80054ec: 685b ldr r3, [r3, #4] + 80054ee: f8c7 31f4 str.w r3, [r7, #500] ; 0x1f4 + pll_config2 = RCC->CFGR2; + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) +#else + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 80054f2: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4 + 80054f6: f403 3280 and.w r2, r3, #65536 ; 0x10000 + 80054fa: f507 7300 add.w r3, r7, #512 ; 0x200 + 80054fe: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 8005502: 681b ldr r3, [r3, #0] + 8005504: 6a1b ldr r3, [r3, #32] + 8005506: 429a cmp r2, r3 + 8005508: d10b bne.n 8005522 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 800550a: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4 + 800550e: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 + 8005512: f507 7300 add.w r3, r7, #512 ; 0x200 + 8005516: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc + 800551a: 681b ldr r3, [r3, #0] + 800551c: 6a5b ldr r3, [r3, #36] ; 0x24 + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 800551e: 429a cmp r2, r3 + 8005520: d001 beq.n 8005526 +#endif + { + return HAL_ERROR; + 8005522: 2301 movs r3, #1 + 8005524: e000 b.n 8005528 + } + } + } + } + + return HAL_OK; + 8005526: 2300 movs r3, #0 +} + 8005528: 4618 mov r0, r3 + 800552a: f507 7700 add.w r7, r7, #512 ; 0x200 + 800552e: 46bd mov sp, r7 + 8005530: bd80 pop {r7, pc} + 8005532: bf00 nop + 8005534: 40021000 .word 0x40021000 + +08005538 : + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8005538: b580 push {r7, lr} + 800553a: b09e sub sp, #120 ; 0x78 + 800553c: af00 add r7, sp, #0 + 800553e: 6078 str r0, [r7, #4] + 8005540: 6039 str r1, [r7, #0] + uint32_t tickstart = 0U; + 8005542: 2300 movs r3, #0 + 8005544: 677b str r3, [r7, #116] ; 0x74 + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + 8005546: 687b ldr r3, [r7, #4] + 8005548: 2b00 cmp r3, #0 + 800554a: d101 bne.n 8005550 + { + return HAL_ERROR; + 800554c: 2301 movs r3, #1 + 800554e: e162 b.n 8005816 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8005550: 4b90 ldr r3, [pc, #576] ; (8005794 ) + 8005552: 681b ldr r3, [r3, #0] + 8005554: f003 0307 and.w r3, r3, #7 + 8005558: 683a ldr r2, [r7, #0] + 800555a: 429a cmp r2, r3 + 800555c: d910 bls.n 8005580 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800555e: 4b8d ldr r3, [pc, #564] ; (8005794 ) + 8005560: 681b ldr r3, [r3, #0] + 8005562: f023 0207 bic.w r2, r3, #7 + 8005566: 498b ldr r1, [pc, #556] ; (8005794 ) + 8005568: 683b ldr r3, [r7, #0] + 800556a: 4313 orrs r3, r2 + 800556c: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 800556e: 4b89 ldr r3, [pc, #548] ; (8005794 ) + 8005570: 681b ldr r3, [r3, #0] + 8005572: f003 0307 and.w r3, r3, #7 + 8005576: 683a ldr r2, [r7, #0] + 8005578: 429a cmp r2, r3 + 800557a: d001 beq.n 8005580 + { + return HAL_ERROR; + 800557c: 2301 movs r3, #1 + 800557e: e14a b.n 8005816 + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8005580: 687b ldr r3, [r7, #4] + 8005582: 681b ldr r3, [r3, #0] + 8005584: f003 0302 and.w r3, r3, #2 + 8005588: 2b00 cmp r3, #0 + 800558a: d008 beq.n 800559e + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 800558c: 4b82 ldr r3, [pc, #520] ; (8005798 ) + 800558e: 685b ldr r3, [r3, #4] + 8005590: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8005594: 687b ldr r3, [r7, #4] + 8005596: 689b ldr r3, [r3, #8] + 8005598: 497f ldr r1, [pc, #508] ; (8005798 ) + 800559a: 4313 orrs r3, r2 + 800559c: 604b str r3, [r1, #4] + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 800559e: 687b ldr r3, [r7, #4] + 80055a0: 681b ldr r3, [r3, #0] + 80055a2: f003 0301 and.w r3, r3, #1 + 80055a6: 2b00 cmp r3, #0 + 80055a8: f000 80dc beq.w 8005764 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80055ac: 687b ldr r3, [r7, #4] + 80055ae: 685b ldr r3, [r3, #4] + 80055b0: 2b01 cmp r3, #1 + 80055b2: d13c bne.n 800562e + 80055b4: f44f 3300 mov.w r3, #131072 ; 0x20000 + 80055b8: 673b str r3, [r7, #112] ; 0x70 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80055ba: 6f3b ldr r3, [r7, #112] ; 0x70 + 80055bc: fa93 f3a3 rbit r3, r3 + 80055c0: 66fb str r3, [r7, #108] ; 0x6c + return result; + 80055c2: 6efb ldr r3, [r7, #108] ; 0x6c + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80055c4: fab3 f383 clz r3, r3 + 80055c8: b2db uxtb r3, r3 + 80055ca: 095b lsrs r3, r3, #5 + 80055cc: b2db uxtb r3, r3 + 80055ce: f043 0301 orr.w r3, r3, #1 + 80055d2: b2db uxtb r3, r3 + 80055d4: 2b01 cmp r3, #1 + 80055d6: d102 bne.n 80055de + 80055d8: 4b6f ldr r3, [pc, #444] ; (8005798 ) + 80055da: 681b ldr r3, [r3, #0] + 80055dc: e00f b.n 80055fe + 80055de: f44f 3300 mov.w r3, #131072 ; 0x20000 + 80055e2: 66bb str r3, [r7, #104] ; 0x68 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80055e4: 6ebb ldr r3, [r7, #104] ; 0x68 + 80055e6: fa93 f3a3 rbit r3, r3 + 80055ea: 667b str r3, [r7, #100] ; 0x64 + 80055ec: f44f 3300 mov.w r3, #131072 ; 0x20000 + 80055f0: 663b str r3, [r7, #96] ; 0x60 + 80055f2: 6e3b ldr r3, [r7, #96] ; 0x60 + 80055f4: fa93 f3a3 rbit r3, r3 + 80055f8: 65fb str r3, [r7, #92] ; 0x5c + 80055fa: 4b67 ldr r3, [pc, #412] ; (8005798 ) + 80055fc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80055fe: f44f 3200 mov.w r2, #131072 ; 0x20000 + 8005602: 65ba str r2, [r7, #88] ; 0x58 + 8005604: 6dba ldr r2, [r7, #88] ; 0x58 + 8005606: fa92 f2a2 rbit r2, r2 + 800560a: 657a str r2, [r7, #84] ; 0x54 + return result; + 800560c: 6d7a ldr r2, [r7, #84] ; 0x54 + 800560e: fab2 f282 clz r2, r2 + 8005612: b2d2 uxtb r2, r2 + 8005614: f042 0220 orr.w r2, r2, #32 + 8005618: b2d2 uxtb r2, r2 + 800561a: f002 021f and.w r2, r2, #31 + 800561e: 2101 movs r1, #1 + 8005620: fa01 f202 lsl.w r2, r1, r2 + 8005624: 4013 ands r3, r2 + 8005626: 2b00 cmp r3, #0 + 8005628: d17b bne.n 8005722 + { + return HAL_ERROR; + 800562a: 2301 movs r3, #1 + 800562c: e0f3 b.n 8005816 + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800562e: 687b ldr r3, [r7, #4] + 8005630: 685b ldr r3, [r3, #4] + 8005632: 2b02 cmp r3, #2 + 8005634: d13c bne.n 80056b0 + 8005636: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 800563a: 653b str r3, [r7, #80] ; 0x50 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 800563c: 6d3b ldr r3, [r7, #80] ; 0x50 + 800563e: fa93 f3a3 rbit r3, r3 + 8005642: 64fb str r3, [r7, #76] ; 0x4c + return result; + 8005644: 6cfb ldr r3, [r7, #76] ; 0x4c + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8005646: fab3 f383 clz r3, r3 + 800564a: b2db uxtb r3, r3 + 800564c: 095b lsrs r3, r3, #5 + 800564e: b2db uxtb r3, r3 + 8005650: f043 0301 orr.w r3, r3, #1 + 8005654: b2db uxtb r3, r3 + 8005656: 2b01 cmp r3, #1 + 8005658: d102 bne.n 8005660 + 800565a: 4b4f ldr r3, [pc, #316] ; (8005798 ) + 800565c: 681b ldr r3, [r3, #0] + 800565e: e00f b.n 8005680 + 8005660: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8005664: 64bb str r3, [r7, #72] ; 0x48 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005666: 6cbb ldr r3, [r7, #72] ; 0x48 + 8005668: fa93 f3a3 rbit r3, r3 + 800566c: 647b str r3, [r7, #68] ; 0x44 + 800566e: f04f 7300 mov.w r3, #33554432 ; 0x2000000 + 8005672: 643b str r3, [r7, #64] ; 0x40 + 8005674: 6c3b ldr r3, [r7, #64] ; 0x40 + 8005676: fa93 f3a3 rbit r3, r3 + 800567a: 63fb str r3, [r7, #60] ; 0x3c + 800567c: 4b46 ldr r3, [pc, #280] ; (8005798 ) + 800567e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005680: f04f 7200 mov.w r2, #33554432 ; 0x2000000 + 8005684: 63ba str r2, [r7, #56] ; 0x38 + 8005686: 6bba ldr r2, [r7, #56] ; 0x38 + 8005688: fa92 f2a2 rbit r2, r2 + 800568c: 637a str r2, [r7, #52] ; 0x34 + return result; + 800568e: 6b7a ldr r2, [r7, #52] ; 0x34 + 8005690: fab2 f282 clz r2, r2 + 8005694: b2d2 uxtb r2, r2 + 8005696: f042 0220 orr.w r2, r2, #32 + 800569a: b2d2 uxtb r2, r2 + 800569c: f002 021f and.w r2, r2, #31 + 80056a0: 2101 movs r1, #1 + 80056a2: fa01 f202 lsl.w r2, r1, r2 + 80056a6: 4013 ands r3, r2 + 80056a8: 2b00 cmp r3, #0 + 80056aa: d13a bne.n 8005722 + { + return HAL_ERROR; + 80056ac: 2301 movs r3, #1 + 80056ae: e0b2 b.n 8005816 + 80056b0: 2302 movs r3, #2 + 80056b2: 633b str r3, [r7, #48] ; 0x30 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80056b4: 6b3b ldr r3, [r7, #48] ; 0x30 + 80056b6: fa93 f3a3 rbit r3, r3 + 80056ba: 62fb str r3, [r7, #44] ; 0x2c + return result; + 80056bc: 6afb ldr r3, [r7, #44] ; 0x2c + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80056be: fab3 f383 clz r3, r3 + 80056c2: b2db uxtb r3, r3 + 80056c4: 095b lsrs r3, r3, #5 + 80056c6: b2db uxtb r3, r3 + 80056c8: f043 0301 orr.w r3, r3, #1 + 80056cc: b2db uxtb r3, r3 + 80056ce: 2b01 cmp r3, #1 + 80056d0: d102 bne.n 80056d8 + 80056d2: 4b31 ldr r3, [pc, #196] ; (8005798 ) + 80056d4: 681b ldr r3, [r3, #0] + 80056d6: e00d b.n 80056f4 + 80056d8: 2302 movs r3, #2 + 80056da: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80056dc: 6abb ldr r3, [r7, #40] ; 0x28 + 80056de: fa93 f3a3 rbit r3, r3 + 80056e2: 627b str r3, [r7, #36] ; 0x24 + 80056e4: 2302 movs r3, #2 + 80056e6: 623b str r3, [r7, #32] + 80056e8: 6a3b ldr r3, [r7, #32] + 80056ea: fa93 f3a3 rbit r3, r3 + 80056ee: 61fb str r3, [r7, #28] + 80056f0: 4b29 ldr r3, [pc, #164] ; (8005798 ) + 80056f2: 6a5b ldr r3, [r3, #36] ; 0x24 + 80056f4: 2202 movs r2, #2 + 80056f6: 61ba str r2, [r7, #24] + 80056f8: 69ba ldr r2, [r7, #24] + 80056fa: fa92 f2a2 rbit r2, r2 + 80056fe: 617a str r2, [r7, #20] + return result; + 8005700: 697a ldr r2, [r7, #20] + 8005702: fab2 f282 clz r2, r2 + 8005706: b2d2 uxtb r2, r2 + 8005708: f042 0220 orr.w r2, r2, #32 + 800570c: b2d2 uxtb r2, r2 + 800570e: f002 021f and.w r2, r2, #31 + 8005712: 2101 movs r1, #1 + 8005714: fa01 f202 lsl.w r2, r1, r2 + 8005718: 4013 ands r3, r2 + 800571a: 2b00 cmp r3, #0 + 800571c: d101 bne.n 8005722 + { + return HAL_ERROR; + 800571e: 2301 movs r3, #1 + 8005720: e079 b.n 8005816 + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8005722: 4b1d ldr r3, [pc, #116] ; (8005798 ) + 8005724: 685b ldr r3, [r3, #4] + 8005726: f023 0203 bic.w r2, r3, #3 + 800572a: 687b ldr r3, [r7, #4] + 800572c: 685b ldr r3, [r3, #4] + 800572e: 491a ldr r1, [pc, #104] ; (8005798 ) + 8005730: 4313 orrs r3, r2 + 8005732: 604b str r3, [r1, #4] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005734: f7fc fd96 bl 8002264 + 8005738: 6778 str r0, [r7, #116] ; 0x74 + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 800573a: e00a b.n 8005752 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 800573c: f7fc fd92 bl 8002264 + 8005740: 4602 mov r2, r0 + 8005742: 6f7b ldr r3, [r7, #116] ; 0x74 + 8005744: 1ad3 subs r3, r2, r3 + 8005746: f241 3288 movw r2, #5000 ; 0x1388 + 800574a: 4293 cmp r3, r2 + 800574c: d901 bls.n 8005752 + { + return HAL_TIMEOUT; + 800574e: 2303 movs r3, #3 + 8005750: e061 b.n 8005816 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8005752: 4b11 ldr r3, [pc, #68] ; (8005798 ) + 8005754: 685b ldr r3, [r3, #4] + 8005756: f003 020c and.w r2, r3, #12 + 800575a: 687b ldr r3, [r7, #4] + 800575c: 685b ldr r3, [r3, #4] + 800575e: 009b lsls r3, r3, #2 + 8005760: 429a cmp r2, r3 + 8005762: d1eb bne.n 800573c + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8005764: 4b0b ldr r3, [pc, #44] ; (8005794 ) + 8005766: 681b ldr r3, [r3, #0] + 8005768: f003 0307 and.w r3, r3, #7 + 800576c: 683a ldr r2, [r7, #0] + 800576e: 429a cmp r2, r3 + 8005770: d214 bcs.n 800579c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8005772: 4b08 ldr r3, [pc, #32] ; (8005794 ) + 8005774: 681b ldr r3, [r3, #0] + 8005776: f023 0207 bic.w r2, r3, #7 + 800577a: 4906 ldr r1, [pc, #24] ; (8005794 ) + 800577c: 683b ldr r3, [r7, #0] + 800577e: 4313 orrs r3, r2 + 8005780: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + 8005782: 4b04 ldr r3, [pc, #16] ; (8005794 ) + 8005784: 681b ldr r3, [r3, #0] + 8005786: f003 0307 and.w r3, r3, #7 + 800578a: 683a ldr r2, [r7, #0] + 800578c: 429a cmp r2, r3 + 800578e: d005 beq.n 800579c + { + return HAL_ERROR; + 8005790: 2301 movs r3, #1 + 8005792: e040 b.n 8005816 + 8005794: 40022000 .word 0x40022000 + 8005798: 40021000 .word 0x40021000 + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 800579c: 687b ldr r3, [r7, #4] + 800579e: 681b ldr r3, [r3, #0] + 80057a0: f003 0304 and.w r3, r3, #4 + 80057a4: 2b00 cmp r3, #0 + 80057a6: d008 beq.n 80057ba + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 80057a8: 4b1d ldr r3, [pc, #116] ; (8005820 ) + 80057aa: 685b ldr r3, [r3, #4] + 80057ac: f423 62e0 bic.w r2, r3, #1792 ; 0x700 + 80057b0: 687b ldr r3, [r7, #4] + 80057b2: 68db ldr r3, [r3, #12] + 80057b4: 491a ldr r1, [pc, #104] ; (8005820 ) + 80057b6: 4313 orrs r3, r2 + 80057b8: 604b str r3, [r1, #4] + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 80057ba: 687b ldr r3, [r7, #4] + 80057bc: 681b ldr r3, [r3, #0] + 80057be: f003 0308 and.w r3, r3, #8 + 80057c2: 2b00 cmp r3, #0 + 80057c4: d009 beq.n 80057da + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 80057c6: 4b16 ldr r3, [pc, #88] ; (8005820 ) + 80057c8: 685b ldr r3, [r3, #4] + 80057ca: f423 5260 bic.w r2, r3, #14336 ; 0x3800 + 80057ce: 687b ldr r3, [r7, #4] + 80057d0: 691b ldr r3, [r3, #16] + 80057d2: 00db lsls r3, r3, #3 + 80057d4: 4912 ldr r1, [pc, #72] ; (8005820 ) + 80057d6: 4313 orrs r3, r2 + 80057d8: 604b str r3, [r1, #4] + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + 80057da: f000 f829 bl 8005830 + 80057de: 4601 mov r1, r0 + 80057e0: 4b0f ldr r3, [pc, #60] ; (8005820 ) + 80057e2: 685b ldr r3, [r3, #4] + 80057e4: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 80057e8: 22f0 movs r2, #240 ; 0xf0 + 80057ea: 613a str r2, [r7, #16] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80057ec: 693a ldr r2, [r7, #16] + 80057ee: fa92 f2a2 rbit r2, r2 + 80057f2: 60fa str r2, [r7, #12] + return result; + 80057f4: 68fa ldr r2, [r7, #12] + 80057f6: fab2 f282 clz r2, r2 + 80057fa: b2d2 uxtb r2, r2 + 80057fc: 40d3 lsrs r3, r2 + 80057fe: 4a09 ldr r2, [pc, #36] ; (8005824 ) + 8005800: 5cd3 ldrb r3, [r2, r3] + 8005802: fa21 f303 lsr.w r3, r1, r3 + 8005806: 4a08 ldr r2, [pc, #32] ; (8005828 ) + 8005808: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (uwTickPrio); + 800580a: 4b08 ldr r3, [pc, #32] ; (800582c ) + 800580c: 681b ldr r3, [r3, #0] + 800580e: 4618 mov r0, r3 + 8005810: f7fc fce4 bl 80021dc + + return HAL_OK; + 8005814: 2300 movs r3, #0 +} + 8005816: 4618 mov r0, r3 + 8005818: 3778 adds r7, #120 ; 0x78 + 800581a: 46bd mov sp, r7 + 800581c: bd80 pop {r7, pc} + 800581e: bf00 nop + 8005820: 40021000 .word 0x40021000 + 8005824: 080064e0 .word 0x080064e0 + 8005828: 20000008 .word 0x20000008 + 800582c: 2000000c .word 0x2000000c + +08005830 : + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8005830: b480 push {r7} + 8005832: b08b sub sp, #44 ; 0x2c + 8005834: af00 add r7, sp, #0 + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + 8005836: 2300 movs r3, #0 + 8005838: 61fb str r3, [r7, #28] + 800583a: 2300 movs r3, #0 + 800583c: 61bb str r3, [r7, #24] + 800583e: 2300 movs r3, #0 + 8005840: 627b str r3, [r7, #36] ; 0x24 + 8005842: 2300 movs r3, #0 + 8005844: 617b str r3, [r7, #20] + uint32_t sysclockfreq = 0U; + 8005846: 2300 movs r3, #0 + 8005848: 623b str r3, [r7, #32] + + tmpreg = RCC->CFGR; + 800584a: 4b29 ldr r3, [pc, #164] ; (80058f0 ) + 800584c: 685b ldr r3, [r3, #4] + 800584e: 61fb str r3, [r7, #28] + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8005850: 69fb ldr r3, [r7, #28] + 8005852: f003 030c and.w r3, r3, #12 + 8005856: 2b04 cmp r3, #4 + 8005858: d002 beq.n 8005860 + 800585a: 2b08 cmp r3, #8 + 800585c: d003 beq.n 8005866 + 800585e: e03c b.n 80058da + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + 8005860: 4b24 ldr r3, [pc, #144] ; (80058f4 ) + 8005862: 623b str r3, [r7, #32] + break; + 8005864: e03c b.n 80058e0 + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; + 8005866: 69fb ldr r3, [r7, #28] + 8005868: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 + 800586c: f44f 1270 mov.w r2, #3932160 ; 0x3c0000 + 8005870: 60ba str r2, [r7, #8] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005872: 68ba ldr r2, [r7, #8] + 8005874: fa92 f2a2 rbit r2, r2 + 8005878: 607a str r2, [r7, #4] + return result; + 800587a: 687a ldr r2, [r7, #4] + 800587c: fab2 f282 clz r2, r2 + 8005880: b2d2 uxtb r2, r2 + 8005882: 40d3 lsrs r3, r2 + 8005884: 4a1c ldr r2, [pc, #112] ; (80058f8 ) + 8005886: 5cd3 ldrb r3, [r2, r3] + 8005888: 617b str r3, [r7, #20] + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)]; + 800588a: 4b19 ldr r3, [pc, #100] ; (80058f0 ) + 800588c: 6adb ldr r3, [r3, #44] ; 0x2c + 800588e: f003 030f and.w r3, r3, #15 + 8005892: 220f movs r2, #15 + 8005894: 613a str r2, [r7, #16] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005896: 693a ldr r2, [r7, #16] + 8005898: fa92 f2a2 rbit r2, r2 + 800589c: 60fa str r2, [r7, #12] + return result; + 800589e: 68fa ldr r2, [r7, #12] + 80058a0: fab2 f282 clz r2, r2 + 80058a4: b2d2 uxtb r2, r2 + 80058a6: 40d3 lsrs r3, r2 + 80058a8: 4a14 ldr r2, [pc, #80] ; (80058fc ) + 80058aa: 5cd3 ldrb r3, [r2, r3] + 80058ac: 61bb str r3, [r7, #24] +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) + 80058ae: 69fb ldr r3, [r7, #28] + 80058b0: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80058b4: 2b00 cmp r3, #0 + 80058b6: d008 beq.n 80058ca + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + 80058b8: 4a0e ldr r2, [pc, #56] ; (80058f4 ) + 80058ba: 69bb ldr r3, [r7, #24] + 80058bc: fbb2 f2f3 udiv r2, r2, r3 + 80058c0: 697b ldr r3, [r7, #20] + 80058c2: fb02 f303 mul.w r3, r2, r3 + 80058c6: 627b str r3, [r7, #36] ; 0x24 + 80058c8: e004 b.n 80058d4 + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); + 80058ca: 697b ldr r3, [r7, #20] + 80058cc: 4a0c ldr r2, [pc, #48] ; (8005900 ) + 80058ce: fb02 f303 mul.w r3, r2, r3 + 80058d2: 627b str r3, [r7, #36] ; 0x24 + { + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + } +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + sysclockfreq = pllclk; + 80058d4: 6a7b ldr r3, [r7, #36] ; 0x24 + 80058d6: 623b str r3, [r7, #32] + break; + 80058d8: e002 b.n 80058e0 + } + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + 80058da: 4b0a ldr r3, [pc, #40] ; (8005904 ) + 80058dc: 623b str r3, [r7, #32] + break; + 80058de: bf00 nop + } + } + return sysclockfreq; + 80058e0: 6a3b ldr r3, [r7, #32] +} + 80058e2: 4618 mov r0, r3 + 80058e4: 372c adds r7, #44 ; 0x2c + 80058e6: 46bd mov sp, r7 + 80058e8: f85d 7b04 ldr.w r7, [sp], #4 + 80058ec: 4770 bx lr + 80058ee: bf00 nop + 80058f0: 40021000 .word 0x40021000 + 80058f4: 00f42400 .word 0x00f42400 + 80058f8: 080064f0 .word 0x080064f0 + 80058fc: 08006500 .word 0x08006500 + 8005900: 003d0900 .word 0x003d0900 + 8005904: 007a1200 .word 0x007a1200 + +08005908 : + * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 8005908: b580 push {r7, lr} + 800590a: b092 sub sp, #72 ; 0x48 + 800590c: af00 add r7, sp, #0 + 800590e: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8005910: 2300 movs r3, #0 + 8005912: 643b str r3, [r7, #64] ; 0x40 + uint32_t temp_reg = 0U; + 8005914: 2300 movs r3, #0 + 8005916: 63fb str r3, [r7, #60] ; 0x3c + FlagStatus pwrclkchanged = RESET; + 8005918: 2300 movs r3, #0 + 800591a: f887 3047 strb.w r3, [r7, #71] ; 0x47 + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 800591e: 687b ldr r3, [r7, #4] + 8005920: 681b ldr r3, [r3, #0] + 8005922: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8005926: 2b00 cmp r3, #0 + 8005928: f000 80d4 beq.w 8005ad4 + + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800592c: 4b4e ldr r3, [pc, #312] ; (8005a68 ) + 800592e: 69db ldr r3, [r3, #28] + 8005930: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005934: 2b00 cmp r3, #0 + 8005936: d10e bne.n 8005956 + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8005938: 4b4b ldr r3, [pc, #300] ; (8005a68 ) + 800593a: 69db ldr r3, [r3, #28] + 800593c: 4a4a ldr r2, [pc, #296] ; (8005a68 ) + 800593e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8005942: 61d3 str r3, [r2, #28] + 8005944: 4b48 ldr r3, [pc, #288] ; (8005a68 ) + 8005946: 69db ldr r3, [r3, #28] + 8005948: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800594c: 60bb str r3, [r7, #8] + 800594e: 68bb ldr r3, [r7, #8] + pwrclkchanged = SET; + 8005950: 2301 movs r3, #1 + 8005952: f887 3047 strb.w r3, [r7, #71] ; 0x47 + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8005956: 4b45 ldr r3, [pc, #276] ; (8005a6c ) + 8005958: 681b ldr r3, [r3, #0] + 800595a: f403 7380 and.w r3, r3, #256 ; 0x100 + 800595e: 2b00 cmp r3, #0 + 8005960: d118 bne.n 8005994 + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + 8005962: 4b42 ldr r3, [pc, #264] ; (8005a6c ) + 8005964: 681b ldr r3, [r3, #0] + 8005966: 4a41 ldr r2, [pc, #260] ; (8005a6c ) + 8005968: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800596c: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 800596e: f7fc fc79 bl 8002264 + 8005972: 6438 str r0, [r7, #64] ; 0x40 + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8005974: e008 b.n 8005988 + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8005976: f7fc fc75 bl 8002264 + 800597a: 4602 mov r2, r0 + 800597c: 6c3b ldr r3, [r7, #64] ; 0x40 + 800597e: 1ad3 subs r3, r2, r3 + 8005980: 2b64 cmp r3, #100 ; 0x64 + 8005982: d901 bls.n 8005988 + { + return HAL_TIMEOUT; + 8005984: 2303 movs r3, #3 + 8005986: e14b b.n 8005c20 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8005988: 4b38 ldr r3, [pc, #224] ; (8005a6c ) + 800598a: 681b ldr r3, [r3, #0] + 800598c: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005990: 2b00 cmp r3, #0 + 8005992: d0f0 beq.n 8005976 + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + 8005994: 4b34 ldr r3, [pc, #208] ; (8005a68 ) + 8005996: 6a1b ldr r3, [r3, #32] + 8005998: f403 7340 and.w r3, r3, #768 ; 0x300 + 800599c: 63fb str r3, [r7, #60] ; 0x3c + if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 800599e: 6bfb ldr r3, [r7, #60] ; 0x3c + 80059a0: 2b00 cmp r3, #0 + 80059a2: f000 8084 beq.w 8005aae + 80059a6: 687b ldr r3, [r7, #4] + 80059a8: 685b ldr r3, [r3, #4] + 80059aa: f403 7340 and.w r3, r3, #768 ; 0x300 + 80059ae: 6bfa ldr r2, [r7, #60] ; 0x3c + 80059b0: 429a cmp r2, r3 + 80059b2: d07c beq.n 8005aae + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 80059b4: 4b2c ldr r3, [pc, #176] ; (8005a68 ) + 80059b6: 6a1b ldr r3, [r3, #32] + 80059b8: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80059bc: 63fb str r3, [r7, #60] ; 0x3c + 80059be: f44f 3380 mov.w r3, #65536 ; 0x10000 + 80059c2: 633b str r3, [r7, #48] ; 0x30 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80059c4: 6b3b ldr r3, [r7, #48] ; 0x30 + 80059c6: fa93 f3a3 rbit r3, r3 + 80059ca: 62fb str r3, [r7, #44] ; 0x2c + return result; + 80059cc: 6afb ldr r3, [r7, #44] ; 0x2c + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 80059ce: fab3 f383 clz r3, r3 + 80059d2: b2db uxtb r3, r3 + 80059d4: 461a mov r2, r3 + 80059d6: 4b26 ldr r3, [pc, #152] ; (8005a70 ) + 80059d8: 4413 add r3, r2 + 80059da: 009b lsls r3, r3, #2 + 80059dc: 461a mov r2, r3 + 80059de: 2301 movs r3, #1 + 80059e0: 6013 str r3, [r2, #0] + 80059e2: f44f 3380 mov.w r3, #65536 ; 0x10000 + 80059e6: 63bb str r3, [r7, #56] ; 0x38 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 80059e8: 6bbb ldr r3, [r7, #56] ; 0x38 + 80059ea: fa93 f3a3 rbit r3, r3 + 80059ee: 637b str r3, [r7, #52] ; 0x34 + return result; + 80059f0: 6b7b ldr r3, [r7, #52] ; 0x34 + __HAL_RCC_BACKUPRESET_RELEASE(); + 80059f2: fab3 f383 clz r3, r3 + 80059f6: b2db uxtb r3, r3 + 80059f8: 461a mov r2, r3 + 80059fa: 4b1d ldr r3, [pc, #116] ; (8005a70 ) + 80059fc: 4413 add r3, r2 + 80059fe: 009b lsls r3, r3, #2 + 8005a00: 461a mov r2, r3 + 8005a02: 2300 movs r3, #0 + 8005a04: 6013 str r3, [r2, #0] + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + 8005a06: 4a18 ldr r2, [pc, #96] ; (8005a68 ) + 8005a08: 6bfb ldr r3, [r7, #60] ; 0x3c + 8005a0a: 6213 str r3, [r2, #32] + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + 8005a0c: 6bfb ldr r3, [r7, #60] ; 0x3c + 8005a0e: f003 0301 and.w r3, r3, #1 + 8005a12: 2b00 cmp r3, #0 + 8005a14: d04b beq.n 8005aae + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8005a16: f7fc fc25 bl 8002264 + 8005a1a: 6438 str r0, [r7, #64] ; 0x40 + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8005a1c: e00a b.n 8005a34 + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8005a1e: f7fc fc21 bl 8002264 + 8005a22: 4602 mov r2, r0 + 8005a24: 6c3b ldr r3, [r7, #64] ; 0x40 + 8005a26: 1ad3 subs r3, r2, r3 + 8005a28: f241 3288 movw r2, #5000 ; 0x1388 + 8005a2c: 4293 cmp r3, r2 + 8005a2e: d901 bls.n 8005a34 + { + return HAL_TIMEOUT; + 8005a30: 2303 movs r3, #3 + 8005a32: e0f5 b.n 8005c20 + 8005a34: 2302 movs r3, #2 + 8005a36: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005a38: 6abb ldr r3, [r7, #40] ; 0x28 + 8005a3a: fa93 f3a3 rbit r3, r3 + 8005a3e: 627b str r3, [r7, #36] ; 0x24 + 8005a40: 2302 movs r3, #2 + 8005a42: 623b str r3, [r7, #32] + 8005a44: 6a3b ldr r3, [r7, #32] + 8005a46: fa93 f3a3 rbit r3, r3 + 8005a4a: 61fb str r3, [r7, #28] + return result; + 8005a4c: 69fb ldr r3, [r7, #28] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8005a4e: fab3 f383 clz r3, r3 + 8005a52: b2db uxtb r3, r3 + 8005a54: 095b lsrs r3, r3, #5 + 8005a56: b2db uxtb r3, r3 + 8005a58: f043 0302 orr.w r3, r3, #2 + 8005a5c: b2db uxtb r3, r3 + 8005a5e: 2b02 cmp r3, #2 + 8005a60: d108 bne.n 8005a74 + 8005a62: 4b01 ldr r3, [pc, #4] ; (8005a68 ) + 8005a64: 6a1b ldr r3, [r3, #32] + 8005a66: e00d b.n 8005a84 + 8005a68: 40021000 .word 0x40021000 + 8005a6c: 40007000 .word 0x40007000 + 8005a70: 10908100 .word 0x10908100 + 8005a74: 2302 movs r3, #2 + 8005a76: 61bb str r3, [r7, #24] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8005a78: 69bb ldr r3, [r7, #24] + 8005a7a: fa93 f3a3 rbit r3, r3 + 8005a7e: 617b str r3, [r7, #20] + 8005a80: 4b69 ldr r3, [pc, #420] ; (8005c28 ) + 8005a82: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005a84: 2202 movs r2, #2 + 8005a86: 613a str r2, [r7, #16] + 8005a88: 693a ldr r2, [r7, #16] + 8005a8a: fa92 f2a2 rbit r2, r2 + 8005a8e: 60fa str r2, [r7, #12] + return result; + 8005a90: 68fa ldr r2, [r7, #12] + 8005a92: fab2 f282 clz r2, r2 + 8005a96: b2d2 uxtb r2, r2 + 8005a98: f042 0240 orr.w r2, r2, #64 ; 0x40 + 8005a9c: b2d2 uxtb r2, r2 + 8005a9e: f002 021f and.w r2, r2, #31 + 8005aa2: 2101 movs r1, #1 + 8005aa4: fa01 f202 lsl.w r2, r1, r2 + 8005aa8: 4013 ands r3, r2 + 8005aaa: 2b00 cmp r3, #0 + 8005aac: d0b7 beq.n 8005a1e + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8005aae: 4b5e ldr r3, [pc, #376] ; (8005c28 ) + 8005ab0: 6a1b ldr r3, [r3, #32] + 8005ab2: f423 7240 bic.w r2, r3, #768 ; 0x300 + 8005ab6: 687b ldr r3, [r7, #4] + 8005ab8: 685b ldr r3, [r3, #4] + 8005aba: 495b ldr r1, [pc, #364] ; (8005c28 ) + 8005abc: 4313 orrs r3, r2 + 8005abe: 620b str r3, [r1, #32] + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 8005ac0: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 + 8005ac4: 2b01 cmp r3, #1 + 8005ac6: d105 bne.n 8005ad4 + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8005ac8: 4b57 ldr r3, [pc, #348] ; (8005c28 ) + 8005aca: 69db ldr r3, [r3, #28] + 8005acc: 4a56 ldr r2, [pc, #344] ; (8005c28 ) + 8005ace: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8005ad2: 61d3 str r3, [r2, #28] + } + } + + /*------------------------------- USART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 8005ad4: 687b ldr r3, [r7, #4] + 8005ad6: 681b ldr r3, [r3, #0] + 8005ad8: f003 0301 and.w r3, r3, #1 + 8005adc: 2b00 cmp r3, #0 + 8005ade: d008 beq.n 8005af2 + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 8005ae0: 4b51 ldr r3, [pc, #324] ; (8005c28 ) + 8005ae2: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005ae4: f023 0203 bic.w r2, r3, #3 + 8005ae8: 687b ldr r3, [r7, #4] + 8005aea: 689b ldr r3, [r3, #8] + 8005aec: 494e ldr r1, [pc, #312] ; (8005c28 ) + 8005aee: 4313 orrs r3, r2 + 8005af0: 630b str r3, [r1, #48] ; 0x30 + } + +#if defined(RCC_CFGR3_USART2SW) + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 8005af2: 687b ldr r3, [r7, #4] + 8005af4: 681b ldr r3, [r3, #0] + 8005af6: f003 0302 and.w r3, r3, #2 + 8005afa: 2b00 cmp r3, #0 + 8005afc: d008 beq.n 8005b10 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 8005afe: 4b4a ldr r3, [pc, #296] ; (8005c28 ) + 8005b00: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005b02: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8005b06: 687b ldr r3, [r7, #4] + 8005b08: 68db ldr r3, [r3, #12] + 8005b0a: 4947 ldr r1, [pc, #284] ; (8005c28 ) + 8005b0c: 4313 orrs r3, r2 + 8005b0e: 630b str r3, [r1, #48] ; 0x30 + } +#endif /* RCC_CFGR3_USART2SW */ + +#if defined(RCC_CFGR3_USART3SW) + /*------------------------------ USART3 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 8005b10: 687b ldr r3, [r7, #4] + 8005b12: 681b ldr r3, [r3, #0] + 8005b14: f003 0304 and.w r3, r3, #4 + 8005b18: 2b00 cmp r3, #0 + 8005b1a: d008 beq.n 8005b2e + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 8005b1c: 4b42 ldr r3, [pc, #264] ; (8005c28 ) + 8005b1e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005b20: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 8005b24: 687b ldr r3, [r7, #4] + 8005b26: 691b ldr r3, [r3, #16] + 8005b28: 493f ldr r1, [pc, #252] ; (8005c28 ) + 8005b2a: 4313 orrs r3, r2 + 8005b2c: 630b str r3, [r1, #48] ; 0x30 + } +#endif /* RCC_CFGR3_USART3SW */ + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8005b2e: 687b ldr r3, [r7, #4] + 8005b30: 681b ldr r3, [r3, #0] + 8005b32: f003 0320 and.w r3, r3, #32 + 8005b36: 2b00 cmp r3, #0 + 8005b38: d008 beq.n 8005b4c + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 8005b3a: 4b3b ldr r3, [pc, #236] ; (8005c28 ) + 8005b3c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005b3e: f023 0210 bic.w r2, r3, #16 + 8005b42: 687b ldr r3, [r7, #4] + 8005b44: 69db ldr r3, [r3, #28] + 8005b46: 4938 ldr r1, [pc, #224] ; (8005c28 ) + 8005b48: 4313 orrs r3, r2 + 8005b4a: 630b str r3, [r1, #48] ; 0x30 +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) + /*------------------------------ USB Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + 8005b4c: 687b ldr r3, [r7, #4] + 8005b4e: 681b ldr r3, [r3, #0] + 8005b50: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8005b54: 2b00 cmp r3, #0 + 8005b56: d008 beq.n 8005b6a + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); + 8005b58: 4b33 ldr r3, [pc, #204] ; (8005c28 ) + 8005b5a: 685b ldr r3, [r3, #4] + 8005b5c: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 + 8005b60: 687b ldr r3, [r7, #4] + 8005b62: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005b64: 4930 ldr r1, [pc, #192] ; (8005c28 ) + 8005b66: 4313 orrs r3, r2 + 8005b68: 604b str r3, [r1, #4] + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) + + /*------------------------------ I2C2 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 8005b6a: 687b ldr r3, [r7, #4] + 8005b6c: 681b ldr r3, [r3, #0] + 8005b6e: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005b72: 2b00 cmp r3, #0 + 8005b74: d008 beq.n 8005b88 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 8005b76: 4b2c ldr r3, [pc, #176] ; (8005c28 ) + 8005b78: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005b7a: f023 0220 bic.w r2, r3, #32 + 8005b7e: 687b ldr r3, [r7, #4] + 8005b80: 6a1b ldr r3, [r3, #32] + 8005b82: 4929 ldr r1, [pc, #164] ; (8005c28 ) + 8005b84: 4313 orrs r3, r2 + 8005b86: 630b str r3, [r1, #48] ; 0x30 + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) + + /*------------------------------ UART4 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 8005b88: 687b ldr r3, [r7, #4] + 8005b8a: 681b ldr r3, [r3, #0] + 8005b8c: f003 0308 and.w r3, r3, #8 + 8005b90: 2b00 cmp r3, #0 + 8005b92: d008 beq.n 8005ba6 + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 8005b94: 4b24 ldr r3, [pc, #144] ; (8005c28 ) + 8005b96: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005b98: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8005b9c: 687b ldr r3, [r7, #4] + 8005b9e: 695b ldr r3, [r3, #20] + 8005ba0: 4921 ldr r1, [pc, #132] ; (8005c28 ) + 8005ba2: 4313 orrs r3, r2 + 8005ba4: 630b str r3, [r1, #48] ; 0x30 + } + + /*------------------------------ UART5 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 8005ba6: 687b ldr r3, [r7, #4] + 8005ba8: 681b ldr r3, [r3, #0] + 8005baa: f003 0310 and.w r3, r3, #16 + 8005bae: 2b00 cmp r3, #0 + 8005bb0: d008 beq.n 8005bc4 + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 8005bb2: 4b1d ldr r3, [pc, #116] ; (8005c28 ) + 8005bb4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005bb6: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8005bba: 687b ldr r3, [r7, #4] + 8005bbc: 699b ldr r3, [r3, #24] + 8005bbe: 491a ldr r1, [pc, #104] ; (8005c28 ) + 8005bc0: 4313 orrs r3, r2 + 8005bc2: 630b str r3, [r1, #48] ; 0x30 + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + /*------------------------------ I2S Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) + 8005bc4: 687b ldr r3, [r7, #4] + 8005bc6: 681b ldr r3, [r3, #0] + 8005bc8: f403 7300 and.w r3, r3, #512 ; 0x200 + 8005bcc: 2b00 cmp r3, #0 + 8005bce: d008 beq.n 8005be2 + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure the I2S clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 8005bd0: 4b15 ldr r3, [pc, #84] ; (8005c28 ) + 8005bd2: 685b ldr r3, [r3, #4] + 8005bd4: f423 0200 bic.w r2, r3, #8388608 ; 0x800000 + 8005bd8: 687b ldr r3, [r7, #4] + 8005bda: 6a9b ldr r3, [r3, #40] ; 0x28 + 8005bdc: 4912 ldr r1, [pc, #72] ; (8005c28 ) + 8005bde: 4313 orrs r3, r2 + 8005be0: 604b str r3, [r1, #4] +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) + + /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) + 8005be2: 687b ldr r3, [r7, #4] + 8005be4: 681b ldr r3, [r3, #0] + 8005be6: f003 0380 and.w r3, r3, #128 ; 0x80 + 8005bea: 2b00 cmp r3, #0 + 8005bec: d008 beq.n 8005c00 + { + /* Check the parameters */ + assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); + + /* Configure the ADC12 clock source */ + __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); + 8005bee: 4b0e ldr r3, [pc, #56] ; (8005c28 ) + 8005bf0: 6adb ldr r3, [r3, #44] ; 0x2c + 8005bf2: f423 72f8 bic.w r2, r3, #496 ; 0x1f0 + 8005bf6: 687b ldr r3, [r7, #4] + 8005bf8: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005bfa: 490b ldr r1, [pc, #44] ; (8005c28 ) + 8005bfc: 4313 orrs r3, r2 + 8005bfe: 62cb str r3, [r1, #44] ; 0x2c + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + /*------------------------------ TIM1 clock Configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) + 8005c00: 687b ldr r3, [r7, #4] + 8005c02: 681b ldr r3, [r3, #0] + 8005c04: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8005c08: 2b00 cmp r3, #0 + 8005c0a: d008 beq.n 8005c1e + { + /* Check the parameters */ + assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); + + /* Configure the TIM1 clock source */ + __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); + 8005c0c: 4b06 ldr r3, [pc, #24] ; (8005c28 ) + 8005c0e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8005c10: f423 7280 bic.w r2, r3, #256 ; 0x100 + 8005c14: 687b ldr r3, [r7, #4] + 8005c16: 6adb ldr r3, [r3, #44] ; 0x2c + 8005c18: 4903 ldr r1, [pc, #12] ; (8005c28 ) + 8005c1a: 4313 orrs r3, r2 + 8005c1c: 630b str r3, [r1, #48] ; 0x30 + __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); + } +#endif /* STM32F303xE || STM32F398xx */ + + + return HAL_OK; + 8005c1e: 2300 movs r3, #0 +} + 8005c20: 4618 mov r0, r3 + 8005c22: 3748 adds r7, #72 ; 0x48 + 8005c24: 46bd mov sp, r7 + 8005c26: bd80 pop {r7, pc} + 8005c28: 40021000 .word 0x40021000 + +08005c2c : + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + 8005c2c: b580 push {r7, lr} + 8005c2e: b084 sub sp, #16 + 8005c30: af00 add r7, sp, #0 + 8005c32: 6078 str r0, [r7, #4] + uint32_t frxth; + + /* Check the SPI handle allocation */ + if (hspi == NULL) + 8005c34: 687b ldr r3, [r7, #4] + 8005c36: 2b00 cmp r3, #0 + 8005c38: d101 bne.n 8005c3e + { + return HAL_ERROR; + 8005c3a: 2301 movs r3, #1 + 8005c3c: e09d b.n 8005d7a + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 8005c3e: 687b ldr r3, [r7, #4] + 8005c40: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005c42: 2b00 cmp r3, #0 + 8005c44: d108 bne.n 8005c58 + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + 8005c46: 687b ldr r3, [r7, #4] + 8005c48: 685b ldr r3, [r3, #4] + 8005c4a: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 8005c4e: d009 beq.n 8005c64 + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 8005c50: 687b ldr r3, [r7, #4] + 8005c52: 2200 movs r2, #0 + 8005c54: 61da str r2, [r3, #28] + 8005c56: e005 b.n 8005c64 + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 8005c58: 687b ldr r3, [r7, #4] + 8005c5a: 2200 movs r2, #0 + 8005c5c: 611a str r2, [r3, #16] + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 8005c5e: 687b ldr r3, [r7, #4] + 8005c60: 2200 movs r2, #0 + 8005c62: 615a str r2, [r3, #20] + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8005c64: 687b ldr r3, [r7, #4] + 8005c66: 2200 movs r2, #0 + 8005c68: 629a str r2, [r3, #40] ; 0x28 +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + 8005c6a: 687b ldr r3, [r7, #4] + 8005c6c: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 8005c70: b2db uxtb r3, r3 + 8005c72: 2b00 cmp r3, #0 + 8005c74: d106 bne.n 8005c84 + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + 8005c76: 687b ldr r3, [r7, #4] + 8005c78: 2200 movs r2, #0 + 8005c7a: f883 205c strb.w r2, [r3, #92] ; 0x5c + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + 8005c7e: 6878 ldr r0, [r7, #4] + 8005c80: f7fc f9e4 bl 800204c +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + 8005c84: 687b ldr r3, [r7, #4] + 8005c86: 2202 movs r2, #2 + 8005c88: f883 205d strb.w r2, [r3, #93] ; 0x5d + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8005c8c: 687b ldr r3, [r7, #4] + 8005c8e: 681b ldr r3, [r3, #0] + 8005c90: 681a ldr r2, [r3, #0] + 8005c92: 687b ldr r3, [r7, #4] + 8005c94: 681b ldr r3, [r3, #0] + 8005c96: f022 0240 bic.w r2, r2, #64 ; 0x40 + 8005c9a: 601a str r2, [r3, #0] + + /* Align by default the rs fifo threshold on the data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 8005c9c: 687b ldr r3, [r7, #4] + 8005c9e: 68db ldr r3, [r3, #12] + 8005ca0: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 8005ca4: d902 bls.n 8005cac + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + 8005ca6: 2300 movs r3, #0 + 8005ca8: 60fb str r3, [r7, #12] + 8005caa: e002 b.n 8005cb2 + } + else + { + frxth = SPI_RXFIFO_THRESHOLD_QF; + 8005cac: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8005cb0: 60fb str r3, [r7, #12] + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + 8005cb2: 687b ldr r3, [r7, #4] + 8005cb4: 68db ldr r3, [r3, #12] + 8005cb6: f5b3 6f70 cmp.w r3, #3840 ; 0xf00 + 8005cba: d007 beq.n 8005ccc + 8005cbc: 687b ldr r3, [r7, #4] + 8005cbe: 68db ldr r3, [r3, #12] + 8005cc0: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 8005cc4: d002 beq.n 8005ccc + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 8005cc6: 687b ldr r3, [r7, #4] + 8005cc8: 2200 movs r2, #0 + 8005cca: 629a str r2, [r3, #40] ; 0x28 + } + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 8005ccc: 687b ldr r3, [r7, #4] + 8005cce: 685b ldr r3, [r3, #4] + 8005cd0: f403 7282 and.w r2, r3, #260 ; 0x104 + 8005cd4: 687b ldr r3, [r7, #4] + 8005cd6: 689b ldr r3, [r3, #8] + 8005cd8: f403 4304 and.w r3, r3, #33792 ; 0x8400 + 8005cdc: 431a orrs r2, r3 + 8005cde: 687b ldr r3, [r7, #4] + 8005ce0: 691b ldr r3, [r3, #16] + 8005ce2: f003 0302 and.w r3, r3, #2 + 8005ce6: 431a orrs r2, r3 + 8005ce8: 687b ldr r3, [r7, #4] + 8005cea: 695b ldr r3, [r3, #20] + 8005cec: f003 0301 and.w r3, r3, #1 + 8005cf0: 431a orrs r2, r3 + 8005cf2: 687b ldr r3, [r7, #4] + 8005cf4: 699b ldr r3, [r3, #24] + 8005cf6: f403 7300 and.w r3, r3, #512 ; 0x200 + 8005cfa: 431a orrs r2, r3 + 8005cfc: 687b ldr r3, [r7, #4] + 8005cfe: 69db ldr r3, [r3, #28] + 8005d00: f003 0338 and.w r3, r3, #56 ; 0x38 + 8005d04: 431a orrs r2, r3 + 8005d06: 687b ldr r3, [r7, #4] + 8005d08: 6a1b ldr r3, [r3, #32] + 8005d0a: f003 0380 and.w r3, r3, #128 ; 0x80 + 8005d0e: ea42 0103 orr.w r1, r2, r3 + 8005d12: 687b ldr r3, [r7, #4] + 8005d14: 6a9b ldr r3, [r3, #40] ; 0x28 + 8005d16: f403 5200 and.w r2, r3, #8192 ; 0x2000 + 8005d1a: 687b ldr r3, [r7, #4] + 8005d1c: 681b ldr r3, [r3, #0] + 8005d1e: 430a orrs r2, r1 + 8005d20: 601a str r2, [r3, #0] + } + } +#endif /* USE_SPI_CRC */ + + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + 8005d22: 687b ldr r3, [r7, #4] + 8005d24: 699b ldr r3, [r3, #24] + 8005d26: 0c1b lsrs r3, r3, #16 + 8005d28: f003 0204 and.w r2, r3, #4 + 8005d2c: 687b ldr r3, [r7, #4] + 8005d2e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005d30: f003 0310 and.w r3, r3, #16 + 8005d34: 431a orrs r2, r3 + 8005d36: 687b ldr r3, [r7, #4] + 8005d38: 6b5b ldr r3, [r3, #52] ; 0x34 + 8005d3a: f003 0308 and.w r3, r3, #8 + 8005d3e: 431a orrs r2, r3 + 8005d40: 687b ldr r3, [r7, #4] + 8005d42: 68db ldr r3, [r3, #12] + 8005d44: f403 6370 and.w r3, r3, #3840 ; 0xf00 + 8005d48: ea42 0103 orr.w r1, r2, r3 + 8005d4c: 68fb ldr r3, [r7, #12] + 8005d4e: f403 5280 and.w r2, r3, #4096 ; 0x1000 + 8005d52: 687b ldr r3, [r7, #4] + 8005d54: 681b ldr r3, [r3, #0] + 8005d56: 430a orrs r2, r1 + 8005d58: 605a str r2, [r3, #4] + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 8005d5a: 687b ldr r3, [r7, #4] + 8005d5c: 681b ldr r3, [r3, #0] + 8005d5e: 69da ldr r2, [r3, #28] + 8005d60: 687b ldr r3, [r7, #4] + 8005d62: 681b ldr r3, [r3, #0] + 8005d64: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 8005d68: 61da str r2, [r3, #28] +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8005d6a: 687b ldr r3, [r7, #4] + 8005d6c: 2200 movs r2, #0 + 8005d6e: 661a str r2, [r3, #96] ; 0x60 + hspi->State = HAL_SPI_STATE_READY; + 8005d70: 687b ldr r3, [r7, #4] + 8005d72: 2201 movs r2, #1 + 8005d74: f883 205d strb.w r2, [r3, #93] ; 0x5d + + return HAL_OK; + 8005d78: 2300 movs r3, #0 +} + 8005d7a: 4618 mov r0, r3 + 8005d7c: 3710 adds r7, #16 + 8005d7e: 46bd mov sp, r7 + 8005d80: bd80 pop {r7, pc} + +08005d82 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout) +{ + 8005d82: b580 push {r7, lr} + 8005d84: b08a sub sp, #40 ; 0x28 + 8005d86: af00 add r7, sp, #0 + 8005d88: 60f8 str r0, [r7, #12] + 8005d8a: 60b9 str r1, [r7, #8] + 8005d8c: 607a str r2, [r7, #4] + 8005d8e: 807b strh r3, [r7, #2] + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + 8005d90: 2301 movs r3, #1 + 8005d92: 627b str r3, [r7, #36] ; 0x24 + HAL_StatusTypeDef errorcode = HAL_OK; + 8005d94: 2300 movs r3, #0 + 8005d96: f887 3023 strb.w r3, [r7, #35] ; 0x23 + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + 8005d9a: 68fb ldr r3, [r7, #12] + 8005d9c: f893 305c ldrb.w r3, [r3, #92] ; 0x5c + 8005da0: 2b01 cmp r3, #1 + 8005da2: d101 bne.n 8005da8 + 8005da4: 2302 movs r3, #2 + 8005da6: e1fb b.n 80061a0 + 8005da8: 68fb ldr r3, [r7, #12] + 8005daa: 2201 movs r2, #1 + 8005dac: f883 205c strb.w r2, [r3, #92] ; 0x5c + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + 8005db0: f7fc fa58 bl 8002264 + 8005db4: 61f8 str r0, [r7, #28] + + /* Init temporary variables */ + tmp_state = hspi->State; + 8005db6: 68fb ldr r3, [r7, #12] + 8005db8: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 8005dbc: 76fb strb r3, [r7, #27] + tmp_mode = hspi->Init.Mode; + 8005dbe: 68fb ldr r3, [r7, #12] + 8005dc0: 685b ldr r3, [r3, #4] + 8005dc2: 617b str r3, [r7, #20] + initial_TxXferCount = Size; + 8005dc4: 887b ldrh r3, [r7, #2] + 8005dc6: 827b strh r3, [r7, #18] + initial_RxXferCount = Size; + 8005dc8: 887b ldrh r3, [r7, #2] + 8005dca: 823b strh r3, [r7, #16] +#if (USE_SPI_CRC != 0U) + spi_cr1 = READ_REG(hspi->Instance->CR1); + spi_cr2 = READ_REG(hspi->Instance->CR2); +#endif /* USE_SPI_CRC */ + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + 8005dcc: 7efb ldrb r3, [r7, #27] + 8005dce: 2b01 cmp r3, #1 + 8005dd0: d00e beq.n 8005df0 + 8005dd2: 697b ldr r3, [r7, #20] + 8005dd4: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 8005dd8: d106 bne.n 8005de8 + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + 8005dda: 68fb ldr r3, [r7, #12] + 8005ddc: 689b ldr r3, [r3, #8] + 8005dde: 2b00 cmp r3, #0 + 8005de0: d102 bne.n 8005de8 + 8005de2: 7efb ldrb r3, [r7, #27] + 8005de4: 2b04 cmp r3, #4 + 8005de6: d003 beq.n 8005df0 + { + errorcode = HAL_BUSY; + 8005de8: 2302 movs r3, #2 + 8005dea: f887 3023 strb.w r3, [r7, #35] ; 0x23 + goto error; + 8005dee: e1cd b.n 800618c + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + 8005df0: 68bb ldr r3, [r7, #8] + 8005df2: 2b00 cmp r3, #0 + 8005df4: d005 beq.n 8005e02 + 8005df6: 687b ldr r3, [r7, #4] + 8005df8: 2b00 cmp r3, #0 + 8005dfa: d002 beq.n 8005e02 + 8005dfc: 887b ldrh r3, [r7, #2] + 8005dfe: 2b00 cmp r3, #0 + 8005e00: d103 bne.n 8005e0a + { + errorcode = HAL_ERROR; + 8005e02: 2301 movs r3, #1 + 8005e04: f887 3023 strb.w r3, [r7, #35] ; 0x23 + goto error; + 8005e08: e1c0 b.n 800618c + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + 8005e0a: 68fb ldr r3, [r7, #12] + 8005e0c: f893 305d ldrb.w r3, [r3, #93] ; 0x5d + 8005e10: b2db uxtb r3, r3 + 8005e12: 2b04 cmp r3, #4 + 8005e14: d003 beq.n 8005e1e + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + 8005e16: 68fb ldr r3, [r7, #12] + 8005e18: 2205 movs r2, #5 + 8005e1a: f883 205d strb.w r2, [r3, #93] ; 0x5d + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 8005e1e: 68fb ldr r3, [r7, #12] + 8005e20: 2200 movs r2, #0 + 8005e22: 661a str r2, [r3, #96] ; 0x60 + hspi->pRxBuffPtr = (uint8_t *)pRxData; + 8005e24: 68fb ldr r3, [r7, #12] + 8005e26: 687a ldr r2, [r7, #4] + 8005e28: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount = Size; + 8005e2a: 68fb ldr r3, [r7, #12] + 8005e2c: 887a ldrh r2, [r7, #2] + 8005e2e: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + hspi->RxXferSize = Size; + 8005e32: 68fb ldr r3, [r7, #12] + 8005e34: 887a ldrh r2, [r7, #2] + 8005e36: f8a3 2044 strh.w r2, [r3, #68] ; 0x44 + hspi->pTxBuffPtr = (uint8_t *)pTxData; + 8005e3a: 68fb ldr r3, [r7, #12] + 8005e3c: 68ba ldr r2, [r7, #8] + 8005e3e: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount = Size; + 8005e40: 68fb ldr r3, [r7, #12] + 8005e42: 887a ldrh r2, [r7, #2] + 8005e44: 87da strh r2, [r3, #62] ; 0x3e + hspi->TxXferSize = Size; + 8005e46: 68fb ldr r3, [r7, #12] + 8005e48: 887a ldrh r2, [r7, #2] + 8005e4a: 879a strh r2, [r3, #60] ; 0x3c + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + 8005e4c: 68fb ldr r3, [r7, #12] + 8005e4e: 2200 movs r2, #0 + 8005e50: 64da str r2, [r3, #76] ; 0x4c + hspi->TxISR = NULL; + 8005e52: 68fb ldr r3, [r7, #12] + 8005e54: 2200 movs r2, #0 + 8005e56: 651a str r2, [r3, #80] ; 0x50 + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + 8005e58: 68fb ldr r3, [r7, #12] + 8005e5a: 68db ldr r3, [r3, #12] + 8005e5c: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 8005e60: d802 bhi.n 8005e68 + 8005e62: 8a3b ldrh r3, [r7, #16] + 8005e64: 2b01 cmp r3, #1 + 8005e66: d908 bls.n 8005e7a + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 8005e68: 68fb ldr r3, [r7, #12] + 8005e6a: 681b ldr r3, [r3, #0] + 8005e6c: 685a ldr r2, [r3, #4] + 8005e6e: 68fb ldr r3, [r7, #12] + 8005e70: 681b ldr r3, [r3, #0] + 8005e72: f422 5280 bic.w r2, r2, #4096 ; 0x1000 + 8005e76: 605a str r2, [r3, #4] + 8005e78: e007 b.n 8005e8a + } + else + { + /* Set fiforxthreshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 8005e7a: 68fb ldr r3, [r7, #12] + 8005e7c: 681b ldr r3, [r3, #0] + 8005e7e: 685a ldr r2, [r3, #4] + 8005e80: 68fb ldr r3, [r7, #12] + 8005e82: 681b ldr r3, [r3, #0] + 8005e84: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 8005e88: 605a str r2, [r3, #4] + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 8005e8a: 68fb ldr r3, [r7, #12] + 8005e8c: 681b ldr r3, [r3, #0] + 8005e8e: 681b ldr r3, [r3, #0] + 8005e90: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005e94: 2b40 cmp r3, #64 ; 0x40 + 8005e96: d007 beq.n 8005ea8 + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + 8005e98: 68fb ldr r3, [r7, #12] + 8005e9a: 681b ldr r3, [r3, #0] + 8005e9c: 681a ldr r2, [r3, #0] + 8005e9e: 68fb ldr r3, [r7, #12] + 8005ea0: 681b ldr r3, [r3, #0] + 8005ea2: f042 0240 orr.w r2, r2, #64 ; 0x40 + 8005ea6: 601a str r2, [r3, #0] + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 8005ea8: 68fb ldr r3, [r7, #12] + 8005eaa: 68db ldr r3, [r3, #12] + 8005eac: f5b3 6fe0 cmp.w r3, #1792 ; 0x700 + 8005eb0: d97c bls.n 8005fac + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8005eb2: 68fb ldr r3, [r7, #12] + 8005eb4: 685b ldr r3, [r3, #4] + 8005eb6: 2b00 cmp r3, #0 + 8005eb8: d002 beq.n 8005ec0 + 8005eba: 8a7b ldrh r3, [r7, #18] + 8005ebc: 2b01 cmp r3, #1 + 8005ebe: d169 bne.n 8005f94 + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 8005ec0: 68fb ldr r3, [r7, #12] + 8005ec2: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005ec4: 881a ldrh r2, [r3, #0] + 8005ec6: 68fb ldr r3, [r7, #12] + 8005ec8: 681b ldr r3, [r3, #0] + 8005eca: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8005ecc: 68fb ldr r3, [r7, #12] + 8005ece: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005ed0: 1c9a adds r2, r3, #2 + 8005ed2: 68fb ldr r3, [r7, #12] + 8005ed4: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 8005ed6: 68fb ldr r3, [r7, #12] + 8005ed8: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8005eda: b29b uxth r3, r3 + 8005edc: 3b01 subs r3, #1 + 8005ede: b29a uxth r2, r3 + 8005ee0: 68fb ldr r3, [r7, #12] + 8005ee2: 87da strh r2, [r3, #62] ; 0x3e + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 8005ee4: e056 b.n 8005f94 + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + 8005ee6: 68fb ldr r3, [r7, #12] + 8005ee8: 681b ldr r3, [r3, #0] + 8005eea: 689b ldr r3, [r3, #8] + 8005eec: f003 0302 and.w r3, r3, #2 + 8005ef0: 2b02 cmp r3, #2 + 8005ef2: d11b bne.n 8005f2c + 8005ef4: 68fb ldr r3, [r7, #12] + 8005ef6: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8005ef8: b29b uxth r3, r3 + 8005efa: 2b00 cmp r3, #0 + 8005efc: d016 beq.n 8005f2c + 8005efe: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005f00: 2b01 cmp r3, #1 + 8005f02: d113 bne.n 8005f2c + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 8005f04: 68fb ldr r3, [r7, #12] + 8005f06: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005f08: 881a ldrh r2, [r3, #0] + 8005f0a: 68fb ldr r3, [r7, #12] + 8005f0c: 681b ldr r3, [r3, #0] + 8005f0e: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8005f10: 68fb ldr r3, [r7, #12] + 8005f12: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005f14: 1c9a adds r2, r3, #2 + 8005f16: 68fb ldr r3, [r7, #12] + 8005f18: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 8005f1a: 68fb ldr r3, [r7, #12] + 8005f1c: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8005f1e: b29b uxth r3, r3 + 8005f20: 3b01 subs r3, #1 + 8005f22: b29a uxth r2, r3 + 8005f24: 68fb ldr r3, [r7, #12] + 8005f26: 87da strh r2, [r3, #62] ; 0x3e + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + 8005f28: 2300 movs r3, #0 + 8005f2a: 627b str r3, [r7, #36] ; 0x24 + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + 8005f2c: 68fb ldr r3, [r7, #12] + 8005f2e: 681b ldr r3, [r3, #0] + 8005f30: 689b ldr r3, [r3, #8] + 8005f32: f003 0301 and.w r3, r3, #1 + 8005f36: 2b01 cmp r3, #1 + 8005f38: d11c bne.n 8005f74 + 8005f3a: 68fb ldr r3, [r7, #12] + 8005f3c: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 8005f40: b29b uxth r3, r3 + 8005f42: 2b00 cmp r3, #0 + 8005f44: d016 beq.n 8005f74 + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + 8005f46: 68fb ldr r3, [r7, #12] + 8005f48: 681b ldr r3, [r3, #0] + 8005f4a: 68da ldr r2, [r3, #12] + 8005f4c: 68fb ldr r3, [r7, #12] + 8005f4e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005f50: b292 uxth r2, r2 + 8005f52: 801a strh r2, [r3, #0] + hspi->pRxBuffPtr += sizeof(uint16_t); + 8005f54: 68fb ldr r3, [r7, #12] + 8005f56: 6c1b ldr r3, [r3, #64] ; 0x40 + 8005f58: 1c9a adds r2, r3, #2 + 8005f5a: 68fb ldr r3, [r7, #12] + 8005f5c: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount--; + 8005f5e: 68fb ldr r3, [r7, #12] + 8005f60: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 8005f64: b29b uxth r3, r3 + 8005f66: 3b01 subs r3, #1 + 8005f68: b29a uxth r2, r3 + 8005f6a: 68fb ldr r3, [r7, #12] + 8005f6c: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + 8005f70: 2301 movs r3, #1 + 8005f72: 627b str r3, [r7, #36] ; 0x24 + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + 8005f74: f7fc f976 bl 8002264 + 8005f78: 4602 mov r2, r0 + 8005f7a: 69fb ldr r3, [r7, #28] + 8005f7c: 1ad3 subs r3, r2, r3 + 8005f7e: 6b3a ldr r2, [r7, #48] ; 0x30 + 8005f80: 429a cmp r2, r3 + 8005f82: d807 bhi.n 8005f94 + 8005f84: 6b3b ldr r3, [r7, #48] ; 0x30 + 8005f86: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8005f8a: d003 beq.n 8005f94 + { + errorcode = HAL_TIMEOUT; + 8005f8c: 2303 movs r3, #3 + 8005f8e: f887 3023 strb.w r3, [r7, #35] ; 0x23 + goto error; + 8005f92: e0fb b.n 800618c + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 8005f94: 68fb ldr r3, [r7, #12] + 8005f96: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8005f98: b29b uxth r3, r3 + 8005f9a: 2b00 cmp r3, #0 + 8005f9c: d1a3 bne.n 8005ee6 + 8005f9e: 68fb ldr r3, [r7, #12] + 8005fa0: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 8005fa4: b29b uxth r3, r3 + 8005fa6: 2b00 cmp r3, #0 + 8005fa8: d19d bne.n 8005ee6 + 8005faa: e0df b.n 800616c + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 8005fac: 68fb ldr r3, [r7, #12] + 8005fae: 685b ldr r3, [r3, #4] + 8005fb0: 2b00 cmp r3, #0 + 8005fb2: d003 beq.n 8005fbc + 8005fb4: 8a7b ldrh r3, [r7, #18] + 8005fb6: 2b01 cmp r3, #1 + 8005fb8: f040 80cb bne.w 8006152 + { + if (hspi->TxXferCount > 1U) + 8005fbc: 68fb ldr r3, [r7, #12] + 8005fbe: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8005fc0: b29b uxth r3, r3 + 8005fc2: 2b01 cmp r3, #1 + 8005fc4: d912 bls.n 8005fec + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 8005fc6: 68fb ldr r3, [r7, #12] + 8005fc8: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005fca: 881a ldrh r2, [r3, #0] + 8005fcc: 68fb ldr r3, [r7, #12] + 8005fce: 681b ldr r3, [r3, #0] + 8005fd0: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8005fd2: 68fb ldr r3, [r7, #12] + 8005fd4: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005fd6: 1c9a adds r2, r3, #2 + 8005fd8: 68fb ldr r3, [r7, #12] + 8005fda: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount -= 2U; + 8005fdc: 68fb ldr r3, [r7, #12] + 8005fde: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8005fe0: b29b uxth r3, r3 + 8005fe2: 3b02 subs r3, #2 + 8005fe4: b29a uxth r2, r3 + 8005fe6: 68fb ldr r3, [r7, #12] + 8005fe8: 87da strh r2, [r3, #62] ; 0x3e + 8005fea: e0b2 b.n 8006152 + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 8005fec: 68fb ldr r3, [r7, #12] + 8005fee: 6b9a ldr r2, [r3, #56] ; 0x38 + 8005ff0: 68fb ldr r3, [r7, #12] + 8005ff2: 681b ldr r3, [r3, #0] + 8005ff4: 330c adds r3, #12 + 8005ff6: 7812 ldrb r2, [r2, #0] + 8005ff8: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr++; + 8005ffa: 68fb ldr r3, [r7, #12] + 8005ffc: 6b9b ldr r3, [r3, #56] ; 0x38 + 8005ffe: 1c5a adds r2, r3, #1 + 8006000: 68fb ldr r3, [r7, #12] + 8006002: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 8006004: 68fb ldr r3, [r7, #12] + 8006006: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8006008: b29b uxth r3, r3 + 800600a: 3b01 subs r3, #1 + 800600c: b29a uxth r2, r3 + 800600e: 68fb ldr r3, [r7, #12] + 8006010: 87da strh r2, [r3, #62] ; 0x3e + } + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 8006012: e09e b.n 8006152 + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + 8006014: 68fb ldr r3, [r7, #12] + 8006016: 681b ldr r3, [r3, #0] + 8006018: 689b ldr r3, [r3, #8] + 800601a: f003 0302 and.w r3, r3, #2 + 800601e: 2b02 cmp r3, #2 + 8006020: d134 bne.n 800608c + 8006022: 68fb ldr r3, [r7, #12] + 8006024: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8006026: b29b uxth r3, r3 + 8006028: 2b00 cmp r3, #0 + 800602a: d02f beq.n 800608c + 800602c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800602e: 2b01 cmp r3, #1 + 8006030: d12c bne.n 800608c + { + if (hspi->TxXferCount > 1U) + 8006032: 68fb ldr r3, [r7, #12] + 8006034: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8006036: b29b uxth r3, r3 + 8006038: 2b01 cmp r3, #1 + 800603a: d912 bls.n 8006062 + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 800603c: 68fb ldr r3, [r7, #12] + 800603e: 6b9b ldr r3, [r3, #56] ; 0x38 + 8006040: 881a ldrh r2, [r3, #0] + 8006042: 68fb ldr r3, [r7, #12] + 8006044: 681b ldr r3, [r3, #0] + 8006046: 60da str r2, [r3, #12] + hspi->pTxBuffPtr += sizeof(uint16_t); + 8006048: 68fb ldr r3, [r7, #12] + 800604a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800604c: 1c9a adds r2, r3, #2 + 800604e: 68fb ldr r3, [r7, #12] + 8006050: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount -= 2U; + 8006052: 68fb ldr r3, [r7, #12] + 8006054: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8006056: b29b uxth r3, r3 + 8006058: 3b02 subs r3, #2 + 800605a: b29a uxth r2, r3 + 800605c: 68fb ldr r3, [r7, #12] + 800605e: 87da strh r2, [r3, #62] ; 0x3e + 8006060: e012 b.n 8006088 + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 8006062: 68fb ldr r3, [r7, #12] + 8006064: 6b9a ldr r2, [r3, #56] ; 0x38 + 8006066: 68fb ldr r3, [r7, #12] + 8006068: 681b ldr r3, [r3, #0] + 800606a: 330c adds r3, #12 + 800606c: 7812 ldrb r2, [r2, #0] + 800606e: 701a strb r2, [r3, #0] + hspi->pTxBuffPtr++; + 8006070: 68fb ldr r3, [r7, #12] + 8006072: 6b9b ldr r3, [r3, #56] ; 0x38 + 8006074: 1c5a adds r2, r3, #1 + 8006076: 68fb ldr r3, [r7, #12] + 8006078: 639a str r2, [r3, #56] ; 0x38 + hspi->TxXferCount--; + 800607a: 68fb ldr r3, [r7, #12] + 800607c: 8fdb ldrh r3, [r3, #62] ; 0x3e + 800607e: b29b uxth r3, r3 + 8006080: 3b01 subs r3, #1 + 8006082: b29a uxth r2, r3 + 8006084: 68fb ldr r3, [r7, #12] + 8006086: 87da strh r2, [r3, #62] ; 0x3e + } + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + 8006088: 2300 movs r3, #0 + 800608a: 627b str r3, [r7, #36] ; 0x24 + } +#endif /* USE_SPI_CRC */ + } + + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + 800608c: 68fb ldr r3, [r7, #12] + 800608e: 681b ldr r3, [r3, #0] + 8006090: 689b ldr r3, [r3, #8] + 8006092: f003 0301 and.w r3, r3, #1 + 8006096: 2b01 cmp r3, #1 + 8006098: d148 bne.n 800612c + 800609a: 68fb ldr r3, [r7, #12] + 800609c: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 80060a0: b29b uxth r3, r3 + 80060a2: 2b00 cmp r3, #0 + 80060a4: d042 beq.n 800612c + { + if (hspi->RxXferCount > 1U) + 80060a6: 68fb ldr r3, [r7, #12] + 80060a8: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 80060ac: b29b uxth r3, r3 + 80060ae: 2b01 cmp r3, #1 + 80060b0: d923 bls.n 80060fa + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + 80060b2: 68fb ldr r3, [r7, #12] + 80060b4: 681b ldr r3, [r3, #0] + 80060b6: 68da ldr r2, [r3, #12] + 80060b8: 68fb ldr r3, [r7, #12] + 80060ba: 6c1b ldr r3, [r3, #64] ; 0x40 + 80060bc: b292 uxth r2, r2 + 80060be: 801a strh r2, [r3, #0] + hspi->pRxBuffPtr += sizeof(uint16_t); + 80060c0: 68fb ldr r3, [r7, #12] + 80060c2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80060c4: 1c9a adds r2, r3, #2 + 80060c6: 68fb ldr r3, [r7, #12] + 80060c8: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount -= 2U; + 80060ca: 68fb ldr r3, [r7, #12] + 80060cc: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 80060d0: b29b uxth r3, r3 + 80060d2: 3b02 subs r3, #2 + 80060d4: b29a uxth r2, r3 + 80060d6: 68fb ldr r3, [r7, #12] + 80060d8: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + if (hspi->RxXferCount <= 1U) + 80060dc: 68fb ldr r3, [r7, #12] + 80060de: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 80060e2: b29b uxth r3, r3 + 80060e4: 2b01 cmp r3, #1 + 80060e6: d81f bhi.n 8006128 + { + /* Set RX Fifo threshold before to switch on 8 bit data size */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 80060e8: 68fb ldr r3, [r7, #12] + 80060ea: 681b ldr r3, [r3, #0] + 80060ec: 685a ldr r2, [r3, #4] + 80060ee: 68fb ldr r3, [r7, #12] + 80060f0: 681b ldr r3, [r3, #0] + 80060f2: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 80060f6: 605a str r2, [r3, #4] + 80060f8: e016 b.n 8006128 + } + } + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + 80060fa: 68fb ldr r3, [r7, #12] + 80060fc: 681b ldr r3, [r3, #0] + 80060fe: f103 020c add.w r2, r3, #12 + 8006102: 68fb ldr r3, [r7, #12] + 8006104: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006106: 7812 ldrb r2, [r2, #0] + 8006108: b2d2 uxtb r2, r2 + 800610a: 701a strb r2, [r3, #0] + hspi->pRxBuffPtr++; + 800610c: 68fb ldr r3, [r7, #12] + 800610e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8006110: 1c5a adds r2, r3, #1 + 8006112: 68fb ldr r3, [r7, #12] + 8006114: 641a str r2, [r3, #64] ; 0x40 + hspi->RxXferCount--; + 8006116: 68fb ldr r3, [r7, #12] + 8006118: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 800611c: b29b uxth r3, r3 + 800611e: 3b01 subs r3, #1 + 8006120: b29a uxth r2, r3 + 8006122: 68fb ldr r3, [r7, #12] + 8006124: f8a3 2046 strh.w r2, [r3, #70] ; 0x46 + } + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + 8006128: 2301 movs r3, #1 + 800612a: 627b str r3, [r7, #36] ; 0x24 + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + 800612c: f7fc f89a bl 8002264 + 8006130: 4602 mov r2, r0 + 8006132: 69fb ldr r3, [r7, #28] + 8006134: 1ad3 subs r3, r2, r3 + 8006136: 6b3a ldr r2, [r7, #48] ; 0x30 + 8006138: 429a cmp r2, r3 + 800613a: d803 bhi.n 8006144 + 800613c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800613e: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8006142: d102 bne.n 800614a + 8006144: 6b3b ldr r3, [r7, #48] ; 0x30 + 8006146: 2b00 cmp r3, #0 + 8006148: d103 bne.n 8006152 + { + errorcode = HAL_TIMEOUT; + 800614a: 2303 movs r3, #3 + 800614c: f887 3023 strb.w r3, [r7, #35] ; 0x23 + goto error; + 8006150: e01c b.n 800618c + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 8006152: 68fb ldr r3, [r7, #12] + 8006154: 8fdb ldrh r3, [r3, #62] ; 0x3e + 8006156: b29b uxth r3, r3 + 8006158: 2b00 cmp r3, #0 + 800615a: f47f af5b bne.w 8006014 + 800615e: 68fb ldr r3, [r7, #12] + 8006160: f8b3 3046 ldrh.w r3, [r3, #70] ; 0x46 + 8006164: b29b uxth r3, r3 + 8006166: 2b00 cmp r3, #0 + 8006168: f47f af54 bne.w 8006014 + errorcode = HAL_ERROR; + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 800616c: 69fa ldr r2, [r7, #28] + 800616e: 6b39 ldr r1, [r7, #48] ; 0x30 + 8006170: 68f8 ldr r0, [r7, #12] + 8006172: f000 f937 bl 80063e4 + 8006176: 4603 mov r3, r0 + 8006178: 2b00 cmp r3, #0 + 800617a: d006 beq.n 800618a + { + errorcode = HAL_ERROR; + 800617c: 2301 movs r3, #1 + 800617e: f887 3023 strb.w r3, [r7, #35] ; 0x23 + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 8006182: 68fb ldr r3, [r7, #12] + 8006184: 2220 movs r2, #32 + 8006186: 661a str r2, [r3, #96] ; 0x60 + 8006188: e000 b.n 800618c + } + +error : + 800618a: bf00 nop + hspi->State = HAL_SPI_STATE_READY; + 800618c: 68fb ldr r3, [r7, #12] + 800618e: 2201 movs r2, #1 + 8006190: f883 205d strb.w r2, [r3, #93] ; 0x5d + __HAL_UNLOCK(hspi); + 8006194: 68fb ldr r3, [r7, #12] + 8006196: 2200 movs r2, #0 + 8006198: f883 205c strb.w r2, [r3, #92] ; 0x5c + return errorcode; + 800619c: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 +} + 80061a0: 4618 mov r0, r3 + 80061a2: 3728 adds r7, #40 ; 0x28 + 80061a4: 46bd mov sp, r7 + 80061a6: bd80 pop {r7, pc} + +080061a8 : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + 80061a8: b580 push {r7, lr} + 80061aa: b088 sub sp, #32 + 80061ac: af00 add r7, sp, #0 + 80061ae: 60f8 str r0, [r7, #12] + 80061b0: 60b9 str r1, [r7, #8] + 80061b2: 603b str r3, [r7, #0] + 80061b4: 4613 mov r3, r2 + 80061b6: 71fb strb r3, [r7, #7] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 80061b8: f7fc f854 bl 8002264 + 80061bc: 4602 mov r2, r0 + 80061be: 6abb ldr r3, [r7, #40] ; 0x28 + 80061c0: 1a9b subs r3, r3, r2 + 80061c2: 683a ldr r2, [r7, #0] + 80061c4: 4413 add r3, r2 + 80061c6: 61fb str r3, [r7, #28] + tmp_tickstart = HAL_GetTick(); + 80061c8: f7fc f84c bl 8002264 + 80061cc: 61b8 str r0, [r7, #24] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 80061ce: 4b39 ldr r3, [pc, #228] ; (80062b4 ) + 80061d0: 681b ldr r3, [r3, #0] + 80061d2: 015b lsls r3, r3, #5 + 80061d4: 0d1b lsrs r3, r3, #20 + 80061d6: 69fa ldr r2, [r7, #28] + 80061d8: fb02 f303 mul.w r3, r2, r3 + 80061dc: 617b str r3, [r7, #20] + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 80061de: e054 b.n 800628a + { + if (Timeout != HAL_MAX_DELAY) + 80061e0: 683b ldr r3, [r7, #0] + 80061e2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 80061e6: d050 beq.n 800628a + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 80061e8: f7fc f83c bl 8002264 + 80061ec: 4602 mov r2, r0 + 80061ee: 69bb ldr r3, [r7, #24] + 80061f0: 1ad3 subs r3, r2, r3 + 80061f2: 69fa ldr r2, [r7, #28] + 80061f4: 429a cmp r2, r3 + 80061f6: d902 bls.n 80061fe + 80061f8: 69fb ldr r3, [r7, #28] + 80061fa: 2b00 cmp r3, #0 + 80061fc: d13d bne.n 800627a + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 80061fe: 68fb ldr r3, [r7, #12] + 8006200: 681b ldr r3, [r3, #0] + 8006202: 685a ldr r2, [r3, #4] + 8006204: 68fb ldr r3, [r7, #12] + 8006206: 681b ldr r3, [r3, #0] + 8006208: f022 02e0 bic.w r2, r2, #224 ; 0xe0 + 800620c: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 800620e: 68fb ldr r3, [r7, #12] + 8006210: 685b ldr r3, [r3, #4] + 8006212: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 8006216: d111 bne.n 800623c + 8006218: 68fb ldr r3, [r7, #12] + 800621a: 689b ldr r3, [r3, #8] + 800621c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8006220: d004 beq.n 800622c + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 8006222: 68fb ldr r3, [r7, #12] + 8006224: 689b ldr r3, [r3, #8] + 8006226: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 800622a: d107 bne.n 800623c + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 800622c: 68fb ldr r3, [r7, #12] + 800622e: 681b ldr r3, [r3, #0] + 8006230: 681a ldr r2, [r3, #0] + 8006232: 68fb ldr r3, [r7, #12] + 8006234: 681b ldr r3, [r3, #0] + 8006236: f022 0240 bic.w r2, r2, #64 ; 0x40 + 800623a: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 800623c: 68fb ldr r3, [r7, #12] + 800623e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006240: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8006244: d10f bne.n 8006266 + { + SPI_RESET_CRC(hspi); + 8006246: 68fb ldr r3, [r7, #12] + 8006248: 681b ldr r3, [r3, #0] + 800624a: 681a ldr r2, [r3, #0] + 800624c: 68fb ldr r3, [r7, #12] + 800624e: 681b ldr r3, [r3, #0] + 8006250: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 8006254: 601a str r2, [r3, #0] + 8006256: 68fb ldr r3, [r7, #12] + 8006258: 681b ldr r3, [r3, #0] + 800625a: 681a ldr r2, [r3, #0] + 800625c: 68fb ldr r3, [r7, #12] + 800625e: 681b ldr r3, [r3, #0] + 8006260: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 8006264: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 8006266: 68fb ldr r3, [r7, #12] + 8006268: 2201 movs r2, #1 + 800626a: f883 205d strb.w r2, [r3, #93] ; 0x5d + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 800626e: 68fb ldr r3, [r7, #12] + 8006270: 2200 movs r2, #0 + 8006272: f883 205c strb.w r2, [r3, #92] ; 0x5c + + return HAL_TIMEOUT; + 8006276: 2303 movs r3, #3 + 8006278: e017 b.n 80062aa + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + 800627a: 697b ldr r3, [r7, #20] + 800627c: 2b00 cmp r3, #0 + 800627e: d101 bne.n 8006284 + { + tmp_timeout = 0U; + 8006280: 2300 movs r3, #0 + 8006282: 61fb str r3, [r7, #28] + } + count--; + 8006284: 697b ldr r3, [r7, #20] + 8006286: 3b01 subs r3, #1 + 8006288: 617b str r3, [r7, #20] + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 800628a: 68fb ldr r3, [r7, #12] + 800628c: 681b ldr r3, [r3, #0] + 800628e: 689a ldr r2, [r3, #8] + 8006290: 68bb ldr r3, [r7, #8] + 8006292: 4013 ands r3, r2 + 8006294: 68ba ldr r2, [r7, #8] + 8006296: 429a cmp r2, r3 + 8006298: bf0c ite eq + 800629a: 2301 moveq r3, #1 + 800629c: 2300 movne r3, #0 + 800629e: b2db uxtb r3, r3 + 80062a0: 461a mov r2, r3 + 80062a2: 79fb ldrb r3, [r7, #7] + 80062a4: 429a cmp r2, r3 + 80062a6: d19b bne.n 80061e0 + } + } + + return HAL_OK; + 80062a8: 2300 movs r3, #0 +} + 80062aa: 4618 mov r0, r3 + 80062ac: 3720 adds r7, #32 + 80062ae: 46bd mov sp, r7 + 80062b0: bd80 pop {r7, pc} + 80062b2: bf00 nop + 80062b4: 20000008 .word 0x20000008 + +080062b8 : + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + 80062b8: b580 push {r7, lr} + 80062ba: b08a sub sp, #40 ; 0x28 + 80062bc: af00 add r7, sp, #0 + 80062be: 60f8 str r0, [r7, #12] + 80062c0: 60b9 str r1, [r7, #8] + 80062c2: 607a str r2, [r7, #4] + 80062c4: 603b str r3, [r7, #0] + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + 80062c6: 2300 movs r3, #0 + 80062c8: 75fb strb r3, [r7, #23] + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 80062ca: f7fb ffcb bl 8002264 + 80062ce: 4602 mov r2, r0 + 80062d0: 6b3b ldr r3, [r7, #48] ; 0x30 + 80062d2: 1a9b subs r3, r3, r2 + 80062d4: 683a ldr r2, [r7, #0] + 80062d6: 4413 add r3, r2 + 80062d8: 627b str r3, [r7, #36] ; 0x24 + tmp_tickstart = HAL_GetTick(); + 80062da: f7fb ffc3 bl 8002264 + 80062de: 6238 str r0, [r7, #32] + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + 80062e0: 68fb ldr r3, [r7, #12] + 80062e2: 681b ldr r3, [r3, #0] + 80062e4: 330c adds r3, #12 + 80062e6: 61fb str r3, [r7, #28] + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + 80062e8: 4b3d ldr r3, [pc, #244] ; (80063e0 ) + 80062ea: 681a ldr r2, [r3, #0] + 80062ec: 4613 mov r3, r2 + 80062ee: 009b lsls r3, r3, #2 + 80062f0: 4413 add r3, r2 + 80062f2: 00da lsls r2, r3, #3 + 80062f4: 1ad3 subs r3, r2, r3 + 80062f6: 0d1b lsrs r3, r3, #20 + 80062f8: 6a7a ldr r2, [r7, #36] ; 0x24 + 80062fa: fb02 f303 mul.w r3, r2, r3 + 80062fe: 61bb str r3, [r7, #24] + + while ((hspi->Instance->SR & Fifo) != State) + 8006300: e060 b.n 80063c4 + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + 8006302: 68bb ldr r3, [r7, #8] + 8006304: f5b3 6fc0 cmp.w r3, #1536 ; 0x600 + 8006308: d107 bne.n 800631a + 800630a: 687b ldr r3, [r7, #4] + 800630c: 2b00 cmp r3, #0 + 800630e: d104 bne.n 800631a + { + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + 8006310: 69fb ldr r3, [r7, #28] + 8006312: 781b ldrb r3, [r3, #0] + 8006314: b2db uxtb r3, r3 + 8006316: 75fb strb r3, [r7, #23] + /* To avoid GCC warning */ + UNUSED(tmpreg8); + 8006318: 7dfb ldrb r3, [r7, #23] + } + + if (Timeout != HAL_MAX_DELAY) + 800631a: 683b ldr r3, [r7, #0] + 800631c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff + 8006320: d050 beq.n 80063c4 + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 8006322: f7fb ff9f bl 8002264 + 8006326: 4602 mov r2, r0 + 8006328: 6a3b ldr r3, [r7, #32] + 800632a: 1ad3 subs r3, r2, r3 + 800632c: 6a7a ldr r2, [r7, #36] ; 0x24 + 800632e: 429a cmp r2, r3 + 8006330: d902 bls.n 8006338 + 8006332: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006334: 2b00 cmp r3, #0 + 8006336: d13d bne.n 80063b4 + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 8006338: 68fb ldr r3, [r7, #12] + 800633a: 681b ldr r3, [r3, #0] + 800633c: 685a ldr r2, [r3, #4] + 800633e: 68fb ldr r3, [r7, #12] + 8006340: 681b ldr r3, [r3, #0] + 8006342: f022 02e0 bic.w r2, r2, #224 ; 0xe0 + 8006346: 605a str r2, [r3, #4] + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 8006348: 68fb ldr r3, [r7, #12] + 800634a: 685b ldr r3, [r3, #4] + 800634c: f5b3 7f82 cmp.w r3, #260 ; 0x104 + 8006350: d111 bne.n 8006376 + 8006352: 68fb ldr r3, [r7, #12] + 8006354: 689b ldr r3, [r3, #8] + 8006356: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800635a: d004 beq.n 8006366 + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + 800635c: 68fb ldr r3, [r7, #12] + 800635e: 689b ldr r3, [r3, #8] + 8006360: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8006364: d107 bne.n 8006376 + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + 8006366: 68fb ldr r3, [r7, #12] + 8006368: 681b ldr r3, [r3, #0] + 800636a: 681a ldr r2, [r3, #0] + 800636c: 68fb ldr r3, [r7, #12] + 800636e: 681b ldr r3, [r3, #0] + 8006370: f022 0240 bic.w r2, r2, #64 ; 0x40 + 8006374: 601a str r2, [r3, #0] + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 8006376: 68fb ldr r3, [r7, #12] + 8006378: 6a9b ldr r3, [r3, #40] ; 0x28 + 800637a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800637e: d10f bne.n 80063a0 + { + SPI_RESET_CRC(hspi); + 8006380: 68fb ldr r3, [r7, #12] + 8006382: 681b ldr r3, [r3, #0] + 8006384: 681a ldr r2, [r3, #0] + 8006386: 68fb ldr r3, [r7, #12] + 8006388: 681b ldr r3, [r3, #0] + 800638a: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 800638e: 601a str r2, [r3, #0] + 8006390: 68fb ldr r3, [r7, #12] + 8006392: 681b ldr r3, [r3, #0] + 8006394: 681a ldr r2, [r3, #0] + 8006396: 68fb ldr r3, [r7, #12] + 8006398: 681b ldr r3, [r3, #0] + 800639a: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 800639e: 601a str r2, [r3, #0] + } + + hspi->State = HAL_SPI_STATE_READY; + 80063a0: 68fb ldr r3, [r7, #12] + 80063a2: 2201 movs r2, #1 + 80063a4: f883 205d strb.w r2, [r3, #93] ; 0x5d + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + 80063a8: 68fb ldr r3, [r7, #12] + 80063aa: 2200 movs r2, #0 + 80063ac: f883 205c strb.w r2, [r3, #92] ; 0x5c + + return HAL_TIMEOUT; + 80063b0: 2303 movs r3, #3 + 80063b2: e010 b.n 80063d6 + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + 80063b4: 69bb ldr r3, [r7, #24] + 80063b6: 2b00 cmp r3, #0 + 80063b8: d101 bne.n 80063be + { + tmp_timeout = 0U; + 80063ba: 2300 movs r3, #0 + 80063bc: 627b str r3, [r7, #36] ; 0x24 + } + count--; + 80063be: 69bb ldr r3, [r7, #24] + 80063c0: 3b01 subs r3, #1 + 80063c2: 61bb str r3, [r7, #24] + while ((hspi->Instance->SR & Fifo) != State) + 80063c4: 68fb ldr r3, [r7, #12] + 80063c6: 681b ldr r3, [r3, #0] + 80063c8: 689a ldr r2, [r3, #8] + 80063ca: 68bb ldr r3, [r7, #8] + 80063cc: 4013 ands r3, r2 + 80063ce: 687a ldr r2, [r7, #4] + 80063d0: 429a cmp r2, r3 + 80063d2: d196 bne.n 8006302 + } + } + + return HAL_OK; + 80063d4: 2300 movs r3, #0 +} + 80063d6: 4618 mov r0, r3 + 80063d8: 3728 adds r7, #40 ; 0x28 + 80063da: 46bd mov sp, r7 + 80063dc: bd80 pop {r7, pc} + 80063de: bf00 nop + 80063e0: 20000008 .word 0x20000008 + +080063e4 : + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + 80063e4: b580 push {r7, lr} + 80063e6: b086 sub sp, #24 + 80063e8: af02 add r7, sp, #8 + 80063ea: 60f8 str r0, [r7, #12] + 80063ec: 60b9 str r1, [r7, #8] + 80063ee: 607a str r2, [r7, #4] + /* Control if the TX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + 80063f0: 687b ldr r3, [r7, #4] + 80063f2: 9300 str r3, [sp, #0] + 80063f4: 68bb ldr r3, [r7, #8] + 80063f6: 2200 movs r2, #0 + 80063f8: f44f 51c0 mov.w r1, #6144 ; 0x1800 + 80063fc: 68f8 ldr r0, [r7, #12] + 80063fe: f7ff ff5b bl 80062b8 + 8006402: 4603 mov r3, r0 + 8006404: 2b00 cmp r3, #0 + 8006406: d007 beq.n 8006418 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8006408: 68fb ldr r3, [r7, #12] + 800640a: 6e1b ldr r3, [r3, #96] ; 0x60 + 800640c: f043 0220 orr.w r2, r3, #32 + 8006410: 68fb ldr r3, [r7, #12] + 8006412: 661a str r2, [r3, #96] ; 0x60 + return HAL_TIMEOUT; + 8006414: 2303 movs r3, #3 + 8006416: e027 b.n 8006468 + } + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 8006418: 687b ldr r3, [r7, #4] + 800641a: 9300 str r3, [sp, #0] + 800641c: 68bb ldr r3, [r7, #8] + 800641e: 2200 movs r2, #0 + 8006420: 2180 movs r1, #128 ; 0x80 + 8006422: 68f8 ldr r0, [r7, #12] + 8006424: f7ff fec0 bl 80061a8 + 8006428: 4603 mov r3, r0 + 800642a: 2b00 cmp r3, #0 + 800642c: d007 beq.n 800643e + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 800642e: 68fb ldr r3, [r7, #12] + 8006430: 6e1b ldr r3, [r3, #96] ; 0x60 + 8006432: f043 0220 orr.w r2, r3, #32 + 8006436: 68fb ldr r3, [r7, #12] + 8006438: 661a str r2, [r3, #96] ; 0x60 + return HAL_TIMEOUT; + 800643a: 2303 movs r3, #3 + 800643c: e014 b.n 8006468 + } + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + 800643e: 687b ldr r3, [r7, #4] + 8006440: 9300 str r3, [sp, #0] + 8006442: 68bb ldr r3, [r7, #8] + 8006444: 2200 movs r2, #0 + 8006446: f44f 61c0 mov.w r1, #1536 ; 0x600 + 800644a: 68f8 ldr r0, [r7, #12] + 800644c: f7ff ff34 bl 80062b8 + 8006450: 4603 mov r3, r0 + 8006452: 2b00 cmp r3, #0 + 8006454: d007 beq.n 8006466 + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8006456: 68fb ldr r3, [r7, #12] + 8006458: 6e1b ldr r3, [r3, #96] ; 0x60 + 800645a: f043 0220 orr.w r2, r3, #32 + 800645e: 68fb ldr r3, [r7, #12] + 8006460: 661a str r2, [r3, #96] ; 0x60 + return HAL_TIMEOUT; + 8006462: 2303 movs r3, #3 + 8006464: e000 b.n 8006468 + } + + return HAL_OK; + 8006466: 2300 movs r3, #0 +} + 8006468: 4618 mov r0, r3 + 800646a: 3710 adds r7, #16 + 800646c: 46bd mov sp, r7 + 800646e: bd80 pop {r7, pc} + +08006470 <__libc_init_array>: + 8006470: b570 push {r4, r5, r6, lr} + 8006472: 4d0d ldr r5, [pc, #52] ; (80064a8 <__libc_init_array+0x38>) + 8006474: 4c0d ldr r4, [pc, #52] ; (80064ac <__libc_init_array+0x3c>) + 8006476: 1b64 subs r4, r4, r5 + 8006478: 10a4 asrs r4, r4, #2 + 800647a: 2600 movs r6, #0 + 800647c: 42a6 cmp r6, r4 + 800647e: d109 bne.n 8006494 <__libc_init_array+0x24> + 8006480: 4d0b ldr r5, [pc, #44] ; (80064b0 <__libc_init_array+0x40>) + 8006482: 4c0c ldr r4, [pc, #48] ; (80064b4 <__libc_init_array+0x44>) + 8006484: f000 f820 bl 80064c8 <_init> + 8006488: 1b64 subs r4, r4, r5 + 800648a: 10a4 asrs r4, r4, #2 + 800648c: 2600 movs r6, #0 + 800648e: 42a6 cmp r6, r4 + 8006490: d105 bne.n 800649e <__libc_init_array+0x2e> + 8006492: bd70 pop {r4, r5, r6, pc} + 8006494: f855 3b04 ldr.w r3, [r5], #4 + 8006498: 4798 blx r3 + 800649a: 3601 adds r6, #1 + 800649c: e7ee b.n 800647c <__libc_init_array+0xc> + 800649e: f855 3b04 ldr.w r3, [r5], #4 + 80064a2: 4798 blx r3 + 80064a4: 3601 adds r6, #1 + 80064a6: e7f2 b.n 800648e <__libc_init_array+0x1e> + 80064a8: 08006510 .word 0x08006510 + 80064ac: 08006510 .word 0x08006510 + 80064b0: 08006510 .word 0x08006510 + 80064b4: 08006514 .word 0x08006514 + +080064b8 : + 80064b8: 4402 add r2, r0 + 80064ba: 4603 mov r3, r0 + 80064bc: 4293 cmp r3, r2 + 80064be: d100 bne.n 80064c2 + 80064c0: 4770 bx lr + 80064c2: f803 1b01 strb.w r1, [r3], #1 + 80064c6: e7f9 b.n 80064bc + +080064c8 <_init>: + 80064c8: b5f8 push {r3, r4, r5, r6, r7, lr} + 80064ca: bf00 nop + 80064cc: bcf8 pop {r3, r4, r5, r6, r7} + 80064ce: bc08 pop {r3} + 80064d0: 469e mov lr, r3 + 80064d2: 4770 bx lr + +080064d4 <_fini>: + 80064d4: b5f8 push {r3, r4, r5, r6, r7, lr} + 80064d6: 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0x000000000000a000 xrw +FLASH 0x0000000008000000 0x0000000000040000 xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crti.o +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +LOAD ./Core/Src/ADBMS_Abstraction.o +LOAD ./Core/Src/ADBMS_LL_Driver.o +LOAD ./Core/Src/AMS_CAN.o +LOAD ./Core/Src/AMS_HighLevel.o +LOAD ./Core/Src/Testbench.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/stm32f3xx_hal_msp.o +LOAD ./Core/Src/stm32f3xx_it.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32f3xx.o +LOAD ./Core/Startup/startup_stm32f302cctx.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o +LOAD ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o +START GROUP +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +END GROUP +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtend.o +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x000000002000a000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0x188 + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0x188 ./Core/Startup/startup_stm32f302cctx.o + 0x0000000008000000 g_pfnVectors + 0x0000000008000188 . = ALIGN (0x4) + +.text 0x0000000008000188 0x6358 + 0x0000000008000188 . = ALIGN (0x4) + *(.text) + .text 0x0000000008000188 0x40 /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + *(.text*) + .text.initAMS 0x00000000080001c8 0x54 ./Core/Src/ADBMS_Abstraction.o + 0x00000000080001c8 initAMS + .text.amsWakeUp + 0x000000000800021c 0x1c ./Core/Src/ADBMS_Abstraction.o + 0x000000000800021c amsWakeUp + .text.amsCellMeasurement + 0x0000000008000238 0x2e ./Core/Src/ADBMS_Abstraction.o + 0x0000000008000238 amsCellMeasurement + .text.amsAuxMeasurement + 0x0000000008000266 0x12a ./Core/Src/ADBMS_Abstraction.o + 0x0000000008000266 amsAuxMeasurement + .text.amsInternalStatusMeasurement + 0x0000000008000390 0x94 ./Core/Src/ADBMS_Abstraction.o + 0x0000000008000390 amsInternalStatusMeasurement + .text.amsConfigAuxMeasurement + 0x0000000008000424 0x60 ./Core/Src/ADBMS_Abstraction.o + 0x0000000008000424 amsConfigAuxMeasurement + .text.amsConfigBalancing + 0x0000000008000484 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0x0000000008006510 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x0000000008006510 PROVIDE (__preinit_array_end = .) + 0x0000000008006510 . = ALIGN (0x4) + +.init_array 0x0000000008006510 0x4 + 0x0000000008006510 . = ALIGN (0x4) + 0x0000000008006510 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x0000000008006510 0x4 /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x0000000008006514 PROVIDE (__init_array_end = .) + 0x0000000008006514 . = ALIGN (0x4) + +.fini_array 0x0000000008006514 0x4 + 0x0000000008006514 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0000000008006514 0x4 /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x0000000008006518 . = ALIGN (0x4) + 0x0000000008006518 _sidata = LOADADDR (.data) + +.data 0x0000000020000000 0x14 load address 0x0000000008006518 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _sdata = . + *(.data) + *(.data*) + .data.numberofCells + 0x0000000020000000 0x1 ./Core/Src/AMS_HighLevel.o + 0x0000000020000000 numberofCells + *fill* 0x0000000020000001 0x3 + .data.channelstobalance.0 + 0x0000000020000004 0x4 ./Core/Src/AMS_HighLevel.o + .data.SystemCoreClock + 0x0000000020000008 0x4 ./Core/Src/system_stm32f3xx.o + 0x0000000020000008 SystemCoreClock + .data.uwTickPrio + 0x000000002000000c 0x4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x000000002000000c uwTickPrio + .data.uwTickFreq + 0x0000000020000010 0x1 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x0000000020000010 uwTickFreq + *(.RamFunc) + *(.RamFunc*) + 0x0000000020000014 . = ALIGN (0x4) + *fill* 0x0000000020000011 0x3 + 0x0000000020000014 _edata = . + +.igot.plt 0x0000000020000014 0x0 load address 0x000000000800652c + .igot.plt 0x0000000020000014 0x0 /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x0000000020000014 . = ALIGN (0x4) + +.bss 0x0000000020000018 0x258 load address 0x000000000800652c + 0x0000000020000018 _sbss = . + 0x0000000020000018 __bss_start__ = _sbss + *(.bss) + .bss 0x0000000020000018 0x1c /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + *(.bss*) + .bss.numberofcells + 0x0000000020000034 0x1 ./Core/Src/ADBMS_Abstraction.o + 0x0000000020000034 numberofcells + .bss.numberofauxchannels + 0x0000000020000035 0x1 ./Core/Src/ADBMS_Abstraction.o + 0x0000000020000035 numberofauxchannels + *fill* 0x0000000020000036 0x2 + .bss.adbmsspi 0x0000000020000038 0x4 ./Core/Src/ADBMS_LL_Driver.o + 0x0000000020000038 adbmsspi + .bss.err_cnt.0 + 0x000000002000003c 0x4 ./Core/Src/ADBMS_LL_Driver.o + .bss.PENDING_MESSAGE_HANDLE + 0x0000000020000040 0x4 ./Core/Src/AMS_CAN.o + 0x0000000020000040 PENDING_MESSAGE_HANDLE + .bss.canTestData + 0x0000000020000044 0x8 ./Core/Src/AMS_CAN.o + 0x0000000020000044 canTestData + .bss.ams_can_handle + 0x000000002000004c 0x4 ./Core/Src/AMS_CAN.o + 0x000000002000004c ams_can_handle + .bss.cb_triggered + 0x0000000020000050 0x4 ./Core/Src/AMS_CAN.o + .bss.header.3 0x0000000020000054 0x1c ./Core/Src/AMS_CAN.o + .bss.data.2 0x0000000020000070 0x8 ./Core/Src/AMS_CAN.o + .bss.header.1 0x0000000020000078 0x18 ./Core/Src/AMS_CAN.o + .bss.data.0 0x0000000020000090 0x8 ./Core/Src/AMS_CAN.o + .bss.module 0x0000000020000098 0x60 ./Core/Src/AMS_HighLevel.o + 0x0000000020000098 module + .bss.currentintegrator + 0x00000000200000f8 0x8 ./Core/Src/AMS_HighLevel.o + 0x00000000200000f8 currentintegrator + .bss.lastticks + 0x0000000020000100 0x4 ./Core/Src/AMS_HighLevel.o + 0x0000000020000100 lastticks + .bss.currenttick + 0x0000000020000104 0x4 ./Core/Src/AMS_HighLevel.o + 0x0000000020000104 currenttick + .bss.eepromconfigured + 0x0000000020000108 0x1 ./Core/Src/AMS_HighLevel.o + 0x0000000020000108 eepromconfigured + *fill* 0x0000000020000109 0x1 + .bss.amsuv 0x000000002000010a 0x2 ./Core/Src/AMS_HighLevel.o + 0x000000002000010a amsuv + .bss.amsov 0x000000002000010c 0x2 ./Core/Src/AMS_HighLevel.o + 0x000000002000010c amsov + .bss.amserrorcode + 0x000000002000010e 0x1 ./Core/Src/AMS_HighLevel.o + 0x000000002000010e amserrorcode + .bss.numberofAux + 0x000000002000010f 0x1 ./Core/Src/AMS_HighLevel.o + 0x000000002000010f numberofAux + .bss.currentAMSState + 0x0000000020000110 0x1 ./Core/Src/AMS_HighLevel.o + 0x0000000020000110 currentAMSState + .bss.lastAMSState + 0x0000000020000111 0x1 ./Core/Src/AMS_HighLevel.o + 0x0000000020000111 lastAMSState + *fill* 0x0000000020000112 0x2 + .bss.header.1 0x0000000020000114 0x18 ./Core/Src/Testbench.o + .bss.header.0 0x000000002000012c 0x18 ./Core/Src/Testbench.o + .bss.hcan 0x0000000020000144 0x28 ./Core/Src/main.o + 0x0000000020000144 hcan + .bss.hi2c1 0x000000002000016c 0x4c ./Core/Src/main.o + 0x000000002000016c hi2c1 + .bss.hi2c2 0x00000000200001b8 0x4c ./Core/Src/main.o + 0x00000000200001b8 hi2c2 + .bss.hspi1 0x0000000020000204 0x64 ./Core/Src/main.o + 0x0000000020000204 hspi1 + .bss.last_error + 0x0000000020000268 0x4 ./Core/Src/main.o + .bss.uwTick 0x000000002000026c 0x4 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + 0x000000002000026c uwTick + *(COMMON) + 0x0000000020000270 . = ALIGN (0x4) + 0x0000000020000270 _ebss = . + 0x0000000020000270 __bss_end__ = _ebss + +._user_heap_stack + 0x0000000020000270 0x600 load address 0x000000000800652c + 0x0000000020000270 . = ALIGN (0x8) + [!provide] PROVIDE (end = .) + 0x0000000020000270 PROVIDE (_end = .) + 0x0000000020000470 . = (. + _Min_Heap_Size) + *fill* 0x0000000020000270 0x200 + 0x0000000020000870 . = (. + _Min_Stack_Size) + *fill* 0x0000000020000470 0x400 + 0x0000000020000870 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x30 + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x1e /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crti.o + .ARM.attributes + 0x000000000000001e 0x34 /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .ARM.attributes + 0x0000000000000052 0x34 ./Core/Src/ADBMS_Abstraction.o + .ARM.attributes + 0x0000000000000086 0x34 ./Core/Src/ADBMS_LL_Driver.o + .ARM.attributes + 0x00000000000000ba 0x34 ./Core/Src/AMS_CAN.o + .ARM.attributes + 0x00000000000000ee 0x34 ./Core/Src/AMS_HighLevel.o + .ARM.attributes + 0x0000000000000122 0x34 ./Core/Src/Testbench.o + .ARM.attributes + 0x0000000000000156 0x34 ./Core/Src/main.o + .ARM.attributes + 0x000000000000018a 0x34 ./Core/Src/stm32f3xx_hal_msp.o + .ARM.attributes + 0x00000000000001be 0x34 ./Core/Src/stm32f3xx_it.o + .ARM.attributes + 0x00000000000001f2 0x34 ./Core/Src/system_stm32f3xx.o + .ARM.attributes + 0x0000000000000226 0x21 ./Core/Startup/startup_stm32f302cctx.o + .ARM.attributes + 0x0000000000000247 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .ARM.attributes + 0x000000000000027b 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .ARM.attributes + 0x00000000000002af 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .ARM.attributes + 0x00000000000002e3 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .ARM.attributes + 0x0000000000000317 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o + .ARM.attributes + 0x000000000000034b 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o + .ARM.attributes + 0x000000000000037f 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .ARM.attributes + 0x00000000000003b3 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .ARM.attributes + 0x00000000000003e7 0x34 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.o + .ARM.attributes + 0x000000000000041b 0x34 /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x000000000000044f 0x34 /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x0000000000000483 0x1e /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/crtn.o +OUTPUT(BMS_Software.elf elf32-littlearm) +LOAD linker stubs +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc.a +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +LOAD /opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/thumb/v7e-m+fp/hard/libgcc.a + +.debug_info 0x0000000000000000 0xf54c + .debug_info 0x0000000000000000 0xcee ./Core/Src/ADBMS_Abstraction.o + .debug_info 0x0000000000000cee 0xc8d ./Core/Src/ADBMS_LL_Driver.o + .debug_info 0x000000000000197b 0xa39 ./Core/Src/AMS_CAN.o + .debug_info 0x00000000000023b4 0xc1a ./Core/Src/AMS_HighLevel.o + .debug_info 0x0000000000002fce 0xa96 ./Core/Src/Testbench.o + .debug_info 0x0000000000003a64 0x1635 ./Core/Src/main.o + .debug_info 0x0000000000005099 0x12f6 ./Core/Src/stm32f3xx_hal_msp.o + .debug_info 0x000000000000638f 0x549 ./Core/Src/stm32f3xx_it.o + .debug_info 0x00000000000068d8 0x416 ./Core/Src/system_stm32f3xx.o + .debug_info 0x0000000000006cee 0x22 ./Core/Startup/startup_stm32f302cctx.o + .debug_info 0x0000000000006d10 0x7d7 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_info 0x00000000000074e7 0xfbb ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_info 0x00000000000084a2 0xd55 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_info 0x00000000000091f7 0x68a ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_info 0x0000000000009881 0x214e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o + .debug_info 0x000000000000b9cf 0x891 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o + .debug_info 0x000000000000c260 0x1586 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_info 0x000000000000d7e6 0x5da ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_info 0x000000000000ddc0 0x178c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.o + +.debug_abbrev 0x0000000000000000 0x2965 + .debug_abbrev 0x0000000000000000 0x2db ./Core/Src/ADBMS_Abstraction.o + .debug_abbrev 0x00000000000002db 0x259 ./Core/Src/ADBMS_LL_Driver.o + .debug_abbrev 0x0000000000000534 0x259 ./Core/Src/AMS_CAN.o + .debug_abbrev 0x000000000000078d 0x2b8 ./Core/Src/AMS_HighLevel.o + .debug_abbrev 0x0000000000000a45 0x268 ./Core/Src/Testbench.o + .debug_abbrev 0x0000000000000cad 0x370 ./Core/Src/main.o + .debug_abbrev 0x000000000000101d 0x228 ./Core/Src/stm32f3xx_hal_msp.o + .debug_abbrev 0x0000000000001245 0x183 ./Core/Src/stm32f3xx_it.o + .debug_abbrev 0x00000000000013c8 0x116 ./Core/Src/system_stm32f3xx.o + .debug_abbrev 0x00000000000014de 0x12 ./Core/Startup/startup_stm32f302cctx.o + .debug_abbrev 0x00000000000014f0 0x20e ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_abbrev 0x00000000000016fe 0x21d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_abbrev 0x000000000000191b 0x316 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_abbrev 0x0000000000001c31 0x1bb ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_abbrev 0x0000000000001dec 0x243 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o + .debug_abbrev 0x000000000000202f 0x1b0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o + .debug_abbrev 0x00000000000021df 0x30c ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o + .debug_abbrev 0x00000000000024eb 0x226 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o + .debug_abbrev 0x0000000000002711 0x254 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.o + +.debug_aranges 0x0000000000000000 0xcc8 + .debug_aranges + 0x0000000000000000 0xe8 ./Core/Src/ADBMS_Abstraction.o + .debug_aranges + 0x00000000000000e8 0x78 ./Core/Src/ADBMS_LL_Driver.o + .debug_aranges + 0x0000000000000160 0x40 ./Core/Src/AMS_CAN.o + .debug_aranges + 0x00000000000001a0 0x70 ./Core/Src/AMS_HighLevel.o + .debug_aranges + 0x0000000000000210 0x40 ./Core/Src/Testbench.o + .debug_aranges + 0x0000000000000250 0x78 ./Core/Src/main.o + .debug_aranges + 0x00000000000002c8 0x50 ./Core/Src/stm32f3xx_hal_msp.o + .debug_aranges + 0x0000000000000318 0x68 ./Core/Src/stm32f3xx_it.o + .debug_aranges + 0x0000000000000380 0x28 ./Core/Src/system_stm32f3xx.o + .debug_aranges + 0x00000000000003a8 0x28 ./Core/Startup/startup_stm32f302cctx.o + .debug_aranges + 0x00000000000003d0 0xe0 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o + .debug_aranges + 0x00000000000004b0 0x138 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.o + .debug_aranges + 0x00000000000005e8 0x118 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o + .debug_aranges + 0x0000000000000700 0x58 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o + .debug_aranges + 0x0000000000000758 0x290 ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o + .debug_aranges + 0x00000000000009e8 0x48 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/opt/st/stm32cubeide_1.10.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.10.3-2021.10.linux64_1.0.0.202111181127/tools/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(lib_a-memset.o) diff --git a/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/ADBMS_Abstraction.d b/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/ADBMS_Abstraction.d new file mode 100644 index 0000000..c5caccc --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/ADBMS_Abstraction.d @@ -0,0 +1,65 @@ +Core/Src/ADBMS_Abstraction.o: ../Core/Src/ADBMS_Abstraction.c \ + ../Core/Inc/ADBMS_Abstraction.h ../Core/Inc/ADBMS_LL_Driver.h \ + ../Core/Inc/main.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + ../Core/Inc/stm32f3xx_hal_conf.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + 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+../Core/Src/stm32f3xx_hal_msp.c:155:6:HAL_I2C_MspInit 56 static +../Core/Src/stm32f3xx_hal_msp.c:223:6:HAL_I2C_MspDeInit 16 static +../Core/Src/stm32f3xx_hal_msp.c:274:6:HAL_SPI_MspInit 48 static +../Core/Src/stm32f3xx_hal_msp.c:311:6:HAL_SPI_MspDeInit 16 static diff --git a/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/stm32f3xx_it.d b/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/stm32f3xx_it.d new file mode 100644 index 0000000..c75aeef --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/stm32f3xx_it.d @@ -0,0 +1,62 @@ +Core/Src/stm32f3xx_it.o: ../Core/Src/stm32f3xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + ../Core/Inc/stm32f3xx_hal_conf.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + ../Core/Inc/stm32f3xx_it.h +../Core/Inc/main.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +../Core/Inc/stm32f3xx_hal_conf.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: 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+../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:199:19:HAL_DMA_DeInit 16 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:281:19:HAL_DMA_Start 32 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:328:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:384:19:HAL_DMA_Abort 16 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:422:19:HAL_DMA_Abort_IT 24 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:468:19:HAL_DMA_PollForTransfer 32 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:569:6:HAL_DMA_IRQHandler 24 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:661:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:712:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:788:22:HAL_DMA_GetState 16 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:799:10:HAL_DMA_GetError 16 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:825:13:DMA_SetConfig 24 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c:859:13:DMA_CalcBaseAndBitshift 16 static diff --git a/BMS_Testbench/BMS_Software_V1/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.d b/BMS_Testbench/BMS_Software_V1/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.d new file mode 100644 index 0000000..d8bdd5e --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.d @@ -0,0 +1,60 @@ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o: \ + ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + ../Core/Inc/stm32f3xx_hal_conf.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +../Core/Inc/stm32f3xx_hal_conf.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: 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static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:448:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:488:6:HAL_EXTI_IRQHandler 32 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:525:10:HAL_EXTI_GetPending 40 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:559:6:HAL_EXTI_ClearPending 32 static +../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c:586:6:HAL_EXTI_GenerateSWI 32 static diff --git a/BMS_Testbench/BMS_Software_V1/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.d b/BMS_Testbench/BMS_Software_V1/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.d new file mode 100644 index 0000000..419d2db --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.d @@ -0,0 +1,60 @@ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o: \ + ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + ../Core/Inc/stm32f3xx_hal_conf.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +../Core/Inc/stm32f3xx_hal_conf.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: 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    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_HAL_GPIO_H +#define __STM32F3xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */ +/** + * @} + */ + + /** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/** @addtogroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + ((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32f3xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_HAL_GPIO_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h new file mode 100644 index 0000000..f3b308c --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h @@ -0,0 +1,1522 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_HAL_GPIO_EX_H +#define __STM32F3xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +#if defined (STM32F302xC) +/*---------------------------------- STM32F302xC ------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ +#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ +#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ +#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ + +#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F302xC */ + +#if defined (STM32F303xC) +/*---------------------------------- STM32F303xC ------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ +#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ +#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ +#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */ +#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */ +#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */ +#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ +#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */ +#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ + +#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F303xC */ + +#if defined (STM32F303xE) +/*---------------------------------- STM32F303xE ------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ +#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ +#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ +#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ +#define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */ +#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */ +#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */ +#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ +#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */ +#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F303xE */ + +#if defined (STM32F302xE) +/*---------------------------------- STM32F302xE ------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ +#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ +#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ +#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F302xE */ + +#if defined (STM32F398xx) +/*---------------------------------- STM32F398xx ------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ +#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ +#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ +#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ +#define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */ +#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */ +#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */ +#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ +#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */ +#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F398xx */ + +#if defined (STM32F358xx) +/*---------------------------------- STM32F358xx -------------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ +#define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ +#define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +#define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ +#define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */ +#define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */ +#define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ +#define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */ +#define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ +#define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */ +#define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F358xx */ + +#if defined (STM32F373xC) +/*---------------------------------- STM32F373xC--------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ +#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ +#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */ + + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F373xC */ + + +#if defined (STM32F378xx) +/*---------------------------------------- STM32F378xx--------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ +#define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ +#define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ +#define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ +#define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F378xx */ + +#if defined (STM32F303x8) +/*---------------------------------- STM32F303x8--------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F303x8 */ + +#if defined (STM32F334x8) || defined (STM32F328xx) +/*---------------------------------- STM32F334x8/STM32F328xx -------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_HRTIM1 ((uint8_t)0x03U) /* HRTIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_HRTIM1 ((uint8_t)0x0CU) /* HRTIM1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */ +#define GPIO_AF13_HRTIM1 ((uint8_t)0x0DU) /* HRTIM1 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F334x8 || STM32F328xx */ + +#if defined (STM32F301x8) || defined (STM32F318xx) +/*---------------------------------- STM32F301x8 / STM32F318xx ------------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F301x8 || STM32F318xx */ + +#if defined (STM32F302x8) +/*---------------------------------- STM32F302x8------------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ +#define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ +#define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */ +#define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ +#define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ +#define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ +#define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU)) +/*------------------------------------------------------------------------------------------*/ +#endif /* STM32F302x8 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index +* @{ + */ +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ + defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 5U) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ + defined(STM32F373xC) || defined(STM32F378xx) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U : 7U) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h new file mode 100644 index 0000000..5a4500e --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h @@ -0,0 +1,838 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F3xx_HAL_I2C_H +#define STM32F3xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32f3xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ + (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f3xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F3xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h new file mode 100644 index 0000000..c6fcfc6 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h @@ -0,0 +1,180 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F3xx_HAL_I2C_EX_H +#define STM32F3xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#if defined(SYSCFG_CFGR1_I2C2_FMP) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif /* SYSCFG_CFGR1_I2C2_FMP */ +#if defined(SYSCFG_CFGR1_I2C3_FMP) +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif /* SYSCFG_CFGR1_I2C3_FMP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F3xx_HAL_I2C_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h new file mode 100644 index 0000000..5f6d606 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h @@ -0,0 +1,219 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_HAL_PWR_H +#define __STM32F3xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins + * @{ + */ + +#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */ +#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */ +#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */ +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */ +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */ +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */ +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */ +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */ +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF /*!< Wakeup event from wakeup pin or RTC alarm */ +#define PWR_FLAG_SB PWR_CSR_SBF /*!< Standby flag */ +#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Power Voltage Detector output flag */ +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF /*!< VREFINT reference voltage ready */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A + * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference + * voltage VREFINT is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32f3xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F3xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h new file mode 100644 index 0000000..9f5b45d --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h @@ -0,0 +1,322 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_HAL_PWR_EX_H +#define __STM32F3xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ +#if defined(STM32F302xE) || defined(STM32F303xE) || \ + defined(STM32F302xC) || defined(STM32F303xC) || \ + defined(STM32F303x8) || defined(STM32F334x8) || \ + defined(STM32F301x8) || defined(STM32F302x8) || \ + defined(STM32F373xC) +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level + This parameter can be a value of @ref PWREx_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVD_Mode */ +}PWR_PVDTypeDef; +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F303x8 || STM32F334x8 || */ + /* STM32F301x8 || STM32F302x8 || */ + /* STM32F373xC */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || \ + defined(STM32F302xC) || defined(STM32F303xC) || \ + defined(STM32F303x8) || defined(STM32F334x8) || \ + defined(STM32F301x8) || defined(STM32F302x8) || \ + defined(STM32F373xC) + +/** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */ +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */ +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */ +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */ +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */ +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */ +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */ +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */ +/** + * @} + */ + +/** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +#define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F303x8 || STM32F334x8 || */ + /* STM32F301x8 || STM32F302x8 || */ + /* STM32F373xC */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +/** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx + * @{ + */ +#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */ +#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */ +#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */ +/** + * @} + */ +#endif /* STM32F373xC || STM32F378xx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros + * @{ + */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || \ + defined(STM32F302xC) || defined(STM32F303xC) || \ + defined(STM32F303x8) || defined(STM32F334x8) || \ + defined(STM32F301x8) || defined(STM32F302x8) || \ + defined(STM32F373xC) + +/** + * @brief Enable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F303x8 || STM32F334x8 || */ + /* STM32F301x8 || STM32F302x8 || */ + /* STM32F373xC */ + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || \ + defined(STM32F302xC) || defined(STM32F303xC) || \ + defined(STM32F303x8) || defined(STM32F334x8) || \ + defined(STM32F301x8) || defined(STM32F302x8) || \ + defined(STM32F373xC) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F303x8 || STM32F334x8 || */ + /* STM32F301x8 || STM32F302x8 || */ + /* STM32F373xC */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \ + ((SDADC) == PWR_SDADC_ANALOG2) || \ + ((SDADC) == PWR_SDADC_ANALOG3)) +#endif /* STM32F373xC || STM32F378xx */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions + * @{ + */ +/* Peripheral Extended control functions **************************************/ +#if defined(STM32F302xE) || defined(STM32F303xE) || \ + defined(STM32F302xC) || defined(STM32F303xC) || \ + defined(STM32F303x8) || defined(STM32F334x8) || \ + defined(STM32F301x8) || defined(STM32F302x8) || \ + defined(STM32F373xC) +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F303x8 || STM32F334x8 || */ + /* STM32F301x8 || STM32F302x8 || */ + /* STM32F373xC */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +void HAL_PWREx_EnableSDADC(uint32_t Analogx); +void HAL_PWREx_DisableSDADC(uint32_t Analogx); +#endif /* STM32F373xC || STM32F378xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h new file mode 100644 index 0000000..b101ef0 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h @@ -0,0 +1,1740 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_HAL_RCC_H +#define __STM32F3xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00 +#define RCC_CFGR_OFFSET 0x04 +#define RCC_CIR_OFFSET 0x08 +#define RCC_BDCR_OFFSET 0x20 +#define RCC_CSR_OFFSET 0x24 + +/** + * @} + */ + +/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) +#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) +#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) +#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) +#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) +#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) +/* Alias word address of HSEON bit */ +#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) +#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) +#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) +#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) +#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) + +/* Alias word address of RMVF bit */ +#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) +#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) + +/* --- BDCR Registers ---*/ +/* Alias word address of LSEON bit */ +#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON) +#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP) +#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) + +/* Alias word address of RTCEN bit */ +#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN) +#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) + +/* Alias word address of BDRST bit */ +#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST) +#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1U) +#define BDCR_REG_INDEX ((uint8_t)2U) +#define CSR_REG_INDEX ((uint8_t)3U) +#define CFGR_REG_INDEX ((uint8_t)4U) + +#define RCC_FLAG_MASK ((uint8_t)0x1FU) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) +#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ + ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ + ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ + ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ + ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ + ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ + ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ + ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) +#else +#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ + ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) +#endif +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) +#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \ + ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \ + ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \ + ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \ + ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \ + ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \ + ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \ + ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16)) +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ + ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ + ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ + ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ + ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ + ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ + ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ + ((__MUL__) == RCC_PLL_MUL16)) +#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) +#if defined(RCC_CFGR3_USART2SW) +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) +#endif /* RCC_CFGR3_USART3SW */ +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< PLLState: The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ + +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock + This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ + +#endif +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + uint32_t HSEPredivValue; /*!< The HSE predivision factor value. + This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */ + +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ + +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */ +#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) +#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ +#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ + +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE (0x00000000U) +#define RCC_OSCILLATORTYPE_HSE (0x00000001U) +#define RCC_OSCILLATORTYPE_HSI (0x00000002U) +#define RCC_OSCILLATORTYPE_LSE (0x00000004U) +#define RCC_OSCILLATORTYPE_LSI (0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ + +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ + +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ + +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ +#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ +#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ + +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor + * @{ + */ +#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 +#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 +#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 +#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 +#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 +#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 +#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 +#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 +#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 +#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 +#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 +#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 +#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 +#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 +#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 + +/** + * @} + */ + +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) +/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor + * @{ + */ + +#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 +#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 +#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 +#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 +#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 +#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 +#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 +#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 +#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 +#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 +#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 +#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 +#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 +#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 +#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 +#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 + +/** + * @} + */ + +#endif +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) +/** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor + * @{ + */ + +#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 +#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 +#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 +#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 +#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 +#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 +#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 +#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 +#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 +#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 +#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 +#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 +#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 +#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 +#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 +#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 + +/** + * @} + */ +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + +#if defined(RCC_CFGR3_USART2SW) +/** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK +#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE +#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI + +/** + * @} + */ +#endif /* RCC_CFGR3_USART2SW */ + +#if defined(RCC_CFGR3_USART3SW) +/** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK +#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE +#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI + +/** + * @} + */ +#endif /* RCC_CFGR3_USART3SW */ + +/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK + +/** + * @} + */ +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 (0x00000000U) +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ + +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ +#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * - 100: CFGR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ +#if defined(RCC_CSR_V18PWRRSTF) +#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF))) +#endif +#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */ +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */ + +/* Flags in the CFGR register */ +#if defined(RCC_CFGR_MCOF) +#define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */ +#endif /* RCC_CFGR_MCOF */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TSC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) +#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) +#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) +#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) +#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) +#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) +#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) +#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief EGet the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) +#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) + +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) +#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ + (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) + +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macro to enable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) + +/** @brief Macro to disable the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON turn ON the HSE oscillator + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do{ \ + if ((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if ((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if ((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + }while(0U) + +/** + * @} + */ + +/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config + * @{ + */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * @param __USART1CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + @if STM32F302xC + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F303xC + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F358xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F302xE + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F303xE + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F398xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F373xC + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F378xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F301x8 + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F302x8 + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F318xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F303x8 + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F334x8 + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F328xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + @if STM32F302xC + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F303xC + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F358xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F302xE + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F303xE + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F398xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F373xC + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F378xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock + @endif + @if STM32F301x8 + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F302x8 + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F318xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F303x8 + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F334x8 + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + @if STM32F328xx + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + @endif + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) + +#if defined(RCC_CFGR3_USART2SW) +/** @brief Macro to configure the USART2 clock (USART2CLK). + * @param __USART2CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) +#endif /* RCC_CFGR3_USART2SW */ + +#if defined(RCC_CFGR3_USART3SW) +/** @brief Macro to configure the USART3 clock (USART3CLK). + * @param __USART3CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) +#endif /* RCC_CFGR3_USART2SW */ +/** + * @} + */ + +/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config + * @{ + */ + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macro to enable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) + +/** @brief Macro to disable the main PLL. + * @note The main PLL can not be disabled if it is used as system clock source + */ +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + + +/** @brief Get oscillator clock selected as PLL input clock + * @retval The clock source used for PLL entry. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) + +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) + +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 + * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 + * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 + */ +#else +/** @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source + */ +#endif +#if defined(RCC_CFGR_MCOPRE) +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) +#else + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) + +#endif + +/** + * @} + */ + + /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macro to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, + * the RTC cannot be used in STOP and STANDBY modes. + * @note The system must always be configured so as to get a PCLK frequency greater than or + * equal to the RTCCLK frequency for a proper operation of the RTC. + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** @brief Macro to enable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) + +/** @brief Macro to disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) + +/** @brief Macro to force the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) + +/** @brief Macros to release the Backup domain reset. + */ +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_CSS Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. + * @arg @ref RCC_IT_LSERDY LSE ready interrupt. + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. + * @arg @ref RCC_IT_HSERDY HSE ready interrupt. + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. + * @arg @ref RCC_IT_CSS Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. + * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset + * @arg @ref RCC_FLAG_PINRST Pin reset. + * @arg @ref RCC_FLAG_PORRST POR/PDR reset. + * @arg @ref RCC_FLAG_SFTRST Software reset. + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. + * @arg @ref RCC_FLAG_LPWRRST Low Power reset. + @if defined(STM32F301x8) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + @if defined(STM32F302x8) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + @if defined(STM32F302xC) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output + @endif + @if defined(STM32F302xE) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + @if defined(STM32F303x8) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + @if defined(STM32F303xC) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output + @endif + @if defined(STM32F303xE) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + @if defined(STM32F334x8) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + @if defined(STM32F358xx) + * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output + @endif + @if defined(STM32F373xC) + * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain + @endif + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ + (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ + (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \ + RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f3xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h new file mode 100644 index 0000000..37c9ced --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h @@ -0,0 +1,3827 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_HAL_RCC_EX_H +#define __STM32F3xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/** @addtogroup RCCEx_Private_Macros + * @{ + */ + +#if defined(RCC_CFGR_PLLNODIV) +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2)) +#else +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2)) +#endif /* RCC_CFGR_PLLNODIV */ + +#if defined(STM32F301x8) || defined(STM32F318xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \ + RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ + RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC)) +#endif /* STM32F301x8 || STM32F318xx */ +#if defined(STM32F302x8) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ + RCC_PERIPHCLK_TIM17)) +#endif /* STM32F302x8 */ +#if defined(STM32F302xC) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \ + RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB)) +#endif /* STM32F302xC */ +#if defined(STM32F303xC) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ + RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ + RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB)) +#endif /* STM32F303xC */ +#if defined(STM32F302xE) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \ + RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \ + RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ + RCC_PERIPHCLK_TIM17)) +#endif /* STM32F302xE */ +#if defined(STM32F303xE) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ + RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ + RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \ + RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ + RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20)) +#endif /* STM32F303xE */ +#if defined(STM32F398xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ + RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ + RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \ + RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \ + RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \ + RCC_PERIPHCLK_TIM20)) +#endif /* STM32F398xx */ +#if defined(STM32F358xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ + RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ + RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC)) +#endif /* STM32F358xx */ +#if defined(STM32F303x8) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ + RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC)) +#endif /* STM32F303x8 */ +#if defined(STM32F334x8) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ + RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \ + RCC_PERIPHCLK_RTC)) +#endif /* STM32F334x8 */ +#if defined(STM32F328xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ + RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC)) +#endif /* STM32F328xx */ +#if defined(STM32F373xC) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB)) +#endif /* STM32F373xC */ +#if defined(STM32F378xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) +#endif /* STM32F378xx */ + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) +#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)) +#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \ + ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \ + ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \ + ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \ + ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \ + ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \ + ((ADCCLK) == RCC_ADC1PLLCLK_DIV256)) +#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) +#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ + ((SOURCE) == RCC_TIM1CLK_PLLCLK)) +#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \ + ((SOURCE) == RCC_TIM15CLK_PLLCLK)) +#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \ + ((SOURCE) == RCC_TIM16CLK_PLLCLK)) +#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \ + ((SOURCE) == RCC_TIM17CLK_PLLCLK)) +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ +#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) +#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) +#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) +#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ + ((SOURCE) == RCC_TIM1CLK_PLLCLK)) +#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) +#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) +#endif /* STM32F302xC || STM32F303xC || STM32F358xx */ +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) +#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)) +#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) +#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) +#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ + ((SOURCE) == RCC_TIM1CLK_PLLCLK)) +#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \ + ((SOURCE) == RCC_TIM2CLK_PLLCLK)) +#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \ + ((SOURCE) == RCC_TIM34CLK_PLLCLK)) +#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \ + ((SOURCE) == RCC_TIM15CLK_PLLCLK)) +#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \ + ((SOURCE) == RCC_TIM16CLK_PLLCLK)) +#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \ + ((SOURCE) == RCC_TIM17CLK_PLLCLK)) +#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) +#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ +#if defined(STM32F303xE) || defined(STM32F398xx) +#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \ + ((SOURCE) == RCC_TIM20CLK_PLLCLK)) +#endif /* STM32F303xE || STM32F398xx */ +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) +#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \ + ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \ + ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \ + ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \ + ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \ + ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \ + ((ADCCLK) == RCC_ADC34PLLCLK_DIV256)) +#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \ + ((SOURCE) == RCC_TIM8CLK_PLLCLK)) +#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ + ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) +#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ + ((SOURCE) == RCC_TIM1CLK_PLLCLK)) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ +#if defined(STM32F334x8) +#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \ + ((SOURCE) == RCC_HRTIM1CLK_PLLCLK)) +#endif /* STM32F334x8 */ +#if defined(STM32F373xC) || defined(STM32F378xx) +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) +#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \ + ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8)) +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \ + ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \ + ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \ + ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \ + ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \ + ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \ + ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \ + ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \ + ((DIV) == RCC_SDADCSYSCLK_DIV48)) +#endif /* STM32F373xC || STM32F378xx */ +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5)) +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F302x8 || */ + /* STM32F373xC */ +#if defined(RCC_CFGR_MCOPRE) +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ + ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ + ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) +#else +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) +#endif /* RCC_CFGR_MCOPRE */ + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +#if defined(STM32F301x8) || defined(STM32F318xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t Adc1ClockSelection; /*!< ADC1 clock source + This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ + + uint32_t I2sClockSelection; /*!< I2S clock source + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t Tim15ClockSelection; /*!< TIM15 clock source + This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ + + uint32_t Tim16ClockSelection; /*!< TIM16 clock source + This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ + + uint32_t Tim17ClockSelection; /*!< TIM17 clock source + This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F301x8 || STM32F318xx */ + +#if defined(STM32F302x8) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t Adc1ClockSelection; /*!< ADC1 clock source + This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ + + uint32_t I2sClockSelection; /*!< I2S clock source + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t Tim15ClockSelection; /*!< TIM15 clock source + This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ + + uint32_t Tim16ClockSelection; /*!< TIM16 clock source + This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ + + uint32_t Tim17ClockSelection; /*!< TIM17 clock source + This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ + + uint32_t USBClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F302x8 */ + +#if defined(STM32F302xC) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCC_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCC_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t I2sClockSelection; /*!< I2S clock source + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t USBClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F302xC */ + +#if defined(STM32F303xC) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCC_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCC_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source + This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ + + uint32_t I2sClockSelection; /*!< I2S clock source + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t Tim8ClockSelection; /*!< TIM8 clock source + This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ + + uint32_t USBClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F303xC */ + +#if defined(STM32F302xE) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCC_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCC_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t I2sClockSelection; /*!< I2S clock source + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t Tim2ClockSelection; /*!< TIM2 clock source + This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ + + uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source + This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ + + uint32_t Tim15ClockSelection; /*!< TIM15 clock source + This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ + + uint32_t Tim16ClockSelection; /*!< TIM16 clock source + This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ + + uint32_t Tim17ClockSelection; /*!< TIM17 clock source + This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ + + uint32_t USBClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F302xE */ + +#if defined(STM32F303xE) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCC_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCC_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source + This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ + + uint32_t I2sClockSelection; /*!< I2S clock source + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t Tim2ClockSelection; /*!< TIM2 clock source + This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ + + uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source + This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ + + uint32_t Tim8ClockSelection; /*!< TIM8 clock source + This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ + + uint32_t Tim15ClockSelection; /*!< TIM15 clock source + This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ + + uint32_t Tim16ClockSelection; /*!< TIM16 clock source + This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ + + uint32_t Tim17ClockSelection; /*!< TIM17 clock source + This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ + + uint32_t Tim20ClockSelection; /*!< TIM20 clock source + This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */ + + uint32_t USBClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F303xE */ + +#if defined(STM32F398xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCC_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCC_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source + This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ + + uint32_t I2sClockSelection; /*!< I2S clock source + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t Tim2ClockSelection; /*!< TIM2 clock source + This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ + + uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source + This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ + + uint32_t Tim8ClockSelection; /*!< TIM8 clock source + This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ + + uint32_t Tim15ClockSelection; /*!< TIM15 clock source + This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ + + uint32_t Tim16ClockSelection; /*!< TIM16 clock source + This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ + + uint32_t Tim17ClockSelection; /*!< TIM17 clock source + This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ + + uint32_t Tim20ClockSelection; /*!< TIM20 clock source + This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F398xx */ + +#if defined(STM32F358xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCC_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCC_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source + This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ + + uint32_t I2sClockSelection; /*!< I2S clock source + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t Tim8ClockSelection; /*!< TIM8 clock source + This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F358xx */ + +#if defined(STM32F303x8) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F303x8 */ + +#if defined(STM32F334x8) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + + uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source + This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F334x8 */ + +#if defined(STM32F328xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source + This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ + + uint32_t Tim1ClockSelection; /*!< TIM1 clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F328xx */ + +#if defined(STM32F373xC) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCC_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCC_USART3_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t Adc1ClockSelection; /*!< ADC1 clock source + This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ + + uint32_t SdadcClockSelection; /*!< SDADC clock prescaler + This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t USBClockSelection; /*!< USB clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F373xC */ + +#if defined(STM32F378xx) +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCC_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCC_USART3_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCC_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t Adc1ClockSelection; /*!< ADC1 clock source + This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ + + uint32_t SdadcClockSelection; /*!< SDADC clock prescaler + This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */ + + uint32_t CecClockSelection; /*!< HDMI CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + +}RCC_PeriphCLKInitTypeDef; +#endif /* STM32F378xx */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants + * @{ + */ +/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK +#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK +#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE +#if defined(RCC_CFGR_PLLNODIV) +#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL) +#endif /* RCC_CFGR_PLLNODIV */ +#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection + * @{ + */ +#if defined(STM32F301x8) || defined(STM32F318xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC1 (0x00000080U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_I2C3 (0x00008000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_TIM15 (0x00040000U) +#define RCC_PERIPHCLK_TIM16 (0x00080000U) +#define RCC_PERIPHCLK_TIM17 (0x00100000U) + +#endif /* STM32F301x8 || STM32F318xx */ + +#if defined(STM32F302x8) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC1 (0x00000080U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_I2C3 (0x00008000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) +#define RCC_PERIPHCLK_TIM15 (0x00040000U) +#define RCC_PERIPHCLK_TIM16 (0x00080000U) +#define RCC_PERIPHCLK_TIM17 (0x00100000U) + + +#endif /* STM32F302x8 */ + +#if defined(STM32F302xC) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F302xC */ + +#if defined(STM32F303xC) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_ADC34 (0x00000100U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_TIM8 (0x00002000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F303xC */ + +#if defined(STM32F302xE) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) +#define RCC_PERIPHCLK_I2C3 (0x00040000U) +#define RCC_PERIPHCLK_TIM2 (0x00100000U) +#define RCC_PERIPHCLK_TIM34 (0x00200000U) +#define RCC_PERIPHCLK_TIM15 (0x00400000U) +#define RCC_PERIPHCLK_TIM16 (0x00800000U) +#define RCC_PERIPHCLK_TIM17 (0x01000000U) + +#endif /* STM32F302xE */ + +#if defined(STM32F303xE) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_ADC34 (0x00000100U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_TIM8 (0x00002000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) +#define RCC_PERIPHCLK_I2C3 (0x00040000U) +#define RCC_PERIPHCLK_TIM2 (0x00100000U) +#define RCC_PERIPHCLK_TIM34 (0x00200000U) +#define RCC_PERIPHCLK_TIM15 (0x00400000U) +#define RCC_PERIPHCLK_TIM16 (0x00800000U) +#define RCC_PERIPHCLK_TIM17 (0x01000000U) +#define RCC_PERIPHCLK_TIM20 (0x02000000U) + +#endif /* STM32F303xE */ + +#if defined(STM32F398xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_ADC34 (0x00000100U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_TIM8 (0x00002000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_I2C3 (0x00040000U) +#define RCC_PERIPHCLK_TIM2 (0x00100000U) +#define RCC_PERIPHCLK_TIM34 (0x00200000U) +#define RCC_PERIPHCLK_TIM15 (0x00400000U) +#define RCC_PERIPHCLK_TIM16 (0x00800000U) +#define RCC_PERIPHCLK_TIM17 (0x01000000U) +#define RCC_PERIPHCLK_TIM20 (0x02000000U) + + +#endif /* STM32F398xx */ + +#if defined(STM32F358xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_UART4 (0x00000008U) +#define RCC_PERIPHCLK_UART5 (0x00000010U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_ADC34 (0x00000100U) +#define RCC_PERIPHCLK_I2S (0x00000200U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_TIM8 (0x00002000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F358xx */ + +#if defined(STM32F303x8) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F303x8 */ + +#if defined(STM32F334x8) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_HRTIM1 (0x00004000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + + +#endif /* STM32F334x8 */ + +#if defined(STM32F328xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_ADC12 (0x00000080U) +#define RCC_PERIPHCLK_TIM1 (0x00001000U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F328xx */ + +#if defined(STM32F373xC) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC1 (0x00000080U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_SDADC (0x00000800U) +#define RCC_PERIPHCLK_RTC (0x00010000U) +#define RCC_PERIPHCLK_USB (0x00020000U) + +#endif /* STM32F373xC */ + +#if defined(STM32F378xx) +#define RCC_PERIPHCLK_USART1 (0x00000001U) +#define RCC_PERIPHCLK_USART2 (0x00000002U) +#define RCC_PERIPHCLK_USART3 (0x00000004U) +#define RCC_PERIPHCLK_I2C1 (0x00000020U) +#define RCC_PERIPHCLK_I2C2 (0x00000040U) +#define RCC_PERIPHCLK_ADC1 (0x00000080U) +#define RCC_PERIPHCLK_CEC (0x00000400U) +#define RCC_PERIPHCLK_SDADC (0x00000800U) +#define RCC_PERIPHCLK_RTC (0x00010000U) + +#endif /* STM32F378xx */ +/** + * @} + */ + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + +/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1 +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK + +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK + +/** + * @} + */ + +/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source + * @{ + */ +#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO +#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1 +#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2 +#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4 +#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6 +#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8 +#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10 +#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12 +#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16 +#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32 +#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64 +#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128 +#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256 + +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT + +/** + * @} + */ + +/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source + * @{ + */ +#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK +#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source + * @{ + */ +#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK +#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source + * @{ + */ +#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK +#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source + * @{ + */ +#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK +#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL + +/** + * @} + */ + +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) + +/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK + +/** + * @} + */ + +/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source + * @{ + */ + +/* ADC1 & ADC2 */ +#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO +#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 +#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 +#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 +#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 +#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 +#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 +#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 +#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 +#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 +#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 +#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 +#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 + +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT + +/** + * @} + */ +/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source + * @{ + */ +#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK +#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source + * @{ + */ +#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK +#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK +#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE +#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI + +/** + * @} + */ + +/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source + * @{ + */ +#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK +#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK +#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE +#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI + +/** + * @} + */ + +#endif /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) + +/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK + +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK + +/** + * @} + */ + +/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source + * @{ + */ + +/* ADC1 & ADC2 */ +#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO +#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 +#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 +#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 +#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 +#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 +#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 +#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 +#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 +#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 +#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 +#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 +#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 + +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT + +/** + * @} + */ + +/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source + * @{ + */ +#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK +#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source + * @{ + */ +#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK +#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source + * @{ + */ +#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK +#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source + * @{ + */ +#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK +#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source + * @{ + */ +#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK +#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source + * @{ + */ +#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK +#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL + +/** + * @} + */ + +/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source + * @{ + */ +#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK +#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK +#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE +#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI + +/** + * @} + */ + +/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source + * @{ + */ +#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK +#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK +#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE +#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI + +/** + * @} + */ + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx) +/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source + * @{ + */ +#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK +#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL + +/** + * @} + */ +#endif /* STM32F303xE || STM32F398xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) + +/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source + * @{ + */ + +/* ADC3 & ADC4 */ +#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO +#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1 +#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2 +#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4 +#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6 +#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8 +#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10 +#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12 +#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16 +#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32 +#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64 +#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128 +#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256 + +/** + * @} + */ + +/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source + * @{ + */ +#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK +#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL + +/** + * @} + */ + +#endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) + +/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1 +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +/** + * @} + */ + +/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source + * @{ + */ +/* ADC1 & ADC2 */ +#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO +#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 +#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 +#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 +#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 +#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 +#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 +#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 +#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 +#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 +#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 +#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 +#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 + +/** + * @} + */ + +/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source + * @{ + */ +#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK +#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL + +/** + * @} + */ + +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F334x8) + +/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source + * @{ + */ +#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK +#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL + +/** + * @} + */ + +#endif /* STM32F334x8 */ + +#if defined(STM32F373xC) || defined(STM32F378xx) + +/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK +#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE +#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI + +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK + +/** + * @} + */ + +/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source + * @{ + */ + +/* ADC1 */ +#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 +#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 +#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 +#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 + +/** + * @} + */ + +/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 +#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE + +/** + * @} + */ + +/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler + * @{ + */ +#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1 +#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2 +#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4 +#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6 +#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8 +#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10 +#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12 +#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14 +#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16 +#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20 +#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24 +#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28 +#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32 +#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36 +#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40 +#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44 +#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48 + +/** + * @} + */ + +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) +/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source + * @{ + */ + +#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 +#define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5 + +/** + * @} + */ + +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F302x8 || */ + /* STM32F373xC */ + + +/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler + * @{ + */ +#if defined(RCC_CFGR_MCOPRE) + +#define RCC_MCODIV_1 (0x00000000U) +#define RCC_MCODIV_2 (0x10000000U) +#define RCC_MCODIV_4 (0x20000000U) +#define RCC_MCODIV_8 (0x30000000U) +#define RCC_MCODIV_16 (0x40000000U) +#define RCC_MCODIV_32 (0x50000000U) +#define RCC_MCODIV_64 (0x60000000U) +#define RCC_MCODIV_128 (0x70000000U) + +#else + +#define RCC_MCODIV_1 (0x00000000U) + +#endif /* RCC_CFGR_MCOPRE */ + +/** + * @} + */ + +/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration + * @{ + */ + +#define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros + * @{ + */ + +/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration + * @{ + */ +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +/** @brief Macro to configure the PLL clock source, multiplication and division factors. + * @note This macro must be used only when the PLL is disabled. + * + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock + * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock + * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \ + do { \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ + } while(0U) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + +#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) +/** @brief Macro to configure the PLL clock source and multiplication factor. + * @note This macro must be used only when the PLL is disabled. + * + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock + * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))) +#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + /* STM32F373xC || STM32F378xx */ +/** + * @} + */ + +#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) +/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. + * @note Predivision factor can not be changed if PLL is used as system clock + * In this case, you have to select another source of the system clock, disable the PLL and + * then change the HSE predivision factor. + * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. + * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. + */ +#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) + +/** + * @brief Macro to get prediv1 factor for PLL. + */ +#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV) + +/** + * @} + */ +#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + /* STM32F373xC || STM32F378xx */ + +/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN)) +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0U) +/* Aliases for STM32 F3 compatibility */ +#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() +#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) +#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN)) +/* Aliases for STM32 F3 compatibility */ +#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() +#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_ADC34_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN)) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0U) +/* Aliases for STM32 F3 compatibility */ +#define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() +#define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() + +#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN)) +/* Aliases for STM32 F3 compatibility */ +#define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() +#define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM18_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx) \ + || defined(STM32F303xC) || defined(STM32F358xx) \ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F302x8 || */ + /* STM32F373xC */ + +#if !defined(STM32F301x8) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) +#endif /* STM32F301x8*/ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F334x8) +#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN)) +#endif /* STM32F334x8 */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM19_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN)) +#define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN)) +#define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN)) +#define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN)) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_TIM20_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN)) +#endif /* STM32F303xE || STM32F398xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET) + +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET) +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET) + +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET) + +#define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET) + +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) + +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET) + +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) + +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) + +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET) + +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) + +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx) \ + || defined(STM32F303xC) || defined(STM32F358xx) \ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) + +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) +#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) + +#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F302x8 || */ + /* STM32F373xC */ + +#if !defined(STM32F301x8) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET) + +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET) +#endif /* STM32F301x8*/ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) + +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) + +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) + +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) + +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F334x8) +#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET) + +#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET) +#endif /* STM32F334x8 */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET) +#define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET) +#define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET) +#define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET) + +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET) +#define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET) +#define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET) +#define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) + +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET) + +#define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET) +#endif /* STM32F303xE || STM32F398xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset + * @brief Force or release AHB peripheral reset. + * @{ + */ +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST)) + +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST)) +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) +#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST)) +/* Aliases for STM32 F3 compatibility */ +#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() +#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) +#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST)) +/* Aliases for STM32 F3 compatibility */ +#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() +#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST)) + +#define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST)) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST)) +/* Aliases for STM32 F3 compatibility */ +#define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() +#define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() + +#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST)) +/* Aliases for STM32 F3 compatibility */ +#define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() +#define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) + +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) + +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST)) + +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST)) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) + +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) + +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F302x8 || */ + /* STM32F373xC */ + +#if !defined(STM32F301x8) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) + +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) +#endif /* STM32F301x8*/ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) + +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) + +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) + +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F334x8) +#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST)) + +#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST)) +#endif /* STM32F334x8 */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST)) +#define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST)) +#define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST)) +#define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST)) + +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST)) +#define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST)) +#define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST)) +#define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST)) +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) + +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) + +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx) +#define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST)) + +#define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST)) +#endif /* STM32F303xE || STM32F398xx */ + +/** + * @} + */ + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) +/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config + * @{ + */ + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * @param __I2C2CLKSource__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) + +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * @param __I2C3CLKSource__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__)) + +/** @brief Macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW))) + +/** + * @} + */ + +/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config + * @{ + */ +/** @brief Macro to configure the TIM1 clock (TIM1CLK). + * @param __TIM1CLKSource__ specifies the TIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock + * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock + */ +#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) + +/** @brief Macro to get the TIM1 clock (TIM1CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock + * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock + */ +#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) + +/** @brief Macro to configure the TIM15 clock (TIM15CLK). + * @param __TIM15CLKSource__ specifies the TIM15 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock + * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock + */ +#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__)) + +/** @brief Macro to get the TIM15 clock (TIM15CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock + * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock + */ +#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW))) + +/** @brief Macro to configure the TIM16 clock (TIM16CLK). + * @param __TIM16CLKSource__ specifies the TIM16 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock + * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock + */ +#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__)) + +/** @brief Macro to get the TIM16 clock (TIM16CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock + * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock + */ +#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW))) + +/** @brief Macro to configure the TIM17 clock (TIM17CLK). + * @param __TIM17CLKSource__ specifies the TIM17 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock + * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock + */ +#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__)) + +/** @brief Macro to get the TIM17 clock (TIM17CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock + * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock + */ +#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW))) + +/** + * @} + */ + +/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config + * @{ + */ +/** @brief Macro to configure the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param __I2SCLKSource__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source + * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin + * used as I2S clock source + */ +#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__)) + +/** @brief Macro to get the I2S clock source (I2SCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source + * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin + * used as I2S clock source + */ +#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) +/** + * @} + */ + +/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config + * @{ + */ + +/** @brief Macro to configure the ADC1 clock (ADC1CLK). + * @param __ADC1CLKSource__ specifies the ADC1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock + * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock + */ +#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__)) + +/** @brief Macro to get the ADC1 clock + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock + * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock + * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock + */ +#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES))) +/** + * @} + */ + +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) +/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config + * @{ + */ + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * @param __I2C2CLKSource__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) +/** + * @} + */ + +/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config + * @{ + */ + +/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK). + * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock + * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock + */ +#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__)) + +/** @brief Macro to get the ADC1 & ADC2 clock + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock + * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock + */ +#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12))) +/** + * @} + */ + +/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config + * @{ + */ + +/** @brief Macro to configure the TIM1 clock (TIM1CLK). + * @param __TIM1CLKSource__ specifies the TIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock + * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock + */ +#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) + +/** @brief Macro to get the TIM1 clock (TIM1CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock + * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock + */ +#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) +/** + * @} + */ + +/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config + * @{ + */ + +/** @brief Macro to configure the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param __I2SCLKSource__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source + * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin + * used as I2S clock source + */ +#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__)) + +/** @brief Macro to get the I2S clock source (I2SCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source + * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin + * used as I2S clock source + */ +#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) +/** + * @} + */ + +/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config + * @{ + */ + +/** @brief Macro to configure the UART4 clock (UART4CLK). + * @param __UART4CLKSource__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + */ +#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__)) + +/** @brief Macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock + * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW))) + +/** @brief Macro to configure the UART5 clock (UART5CLK). + * @param __UART5CLKSource__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + */ +#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__)) + +/** @brief Macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock + * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW))) +/** + * @} + */ +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) +/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config + * @{ + */ + +/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK). + * @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock + * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock + */ +#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__)) + +/** @brief Macro to get the ADC3 & ADC4 clock + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock + * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock + * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock + */ +#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34))) +/** + * @} + */ + +/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config + * @{ + */ + +/** @brief Macro to configure the TIM8 clock (TIM8CLK). + * @param __TIM8CLKSource__ specifies the TIM8 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock + * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock + */ +#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__)) + +/** @brief Macro to get the TIM8 clock (TIM8CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock + * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock + */ +#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW))) + +/** + * @} + */ +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config + * @{ + */ + +/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK). + * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock + * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock + */ +#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__)) + +/** @brief Macro to get the ADC1 & ADC2 clock + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock + * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock + * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock + */ +#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12))) +/** + * @} + */ + +/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config + * @{ + */ +/** @brief Macro to configure the TIM1 clock (TIM1CLK). + * @param __TIM1CLKSource__ specifies the TIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock + * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock + */ +#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) + +/** @brief Macro to get the TIM1 clock (TIM1CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock + * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock + */ +#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) +/** + * @} + */ +#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F334x8) +/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config + * @{ + */ +/** @brief Macro to configure the HRTIM1 clock. + * @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock + * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock + */ +#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__)) + +/** @brief Macro to get the HRTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock + * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock + */ +#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW))) +/** + * @} + */ +#endif /* STM32F334x8 */ + +#if defined(STM32F373xC) || defined(STM32F378xx) +/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config + * @{ + */ +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * @param __I2C2CLKSource__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) +/** + * @} + */ + +/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config + * @{ + */ +/** @brief Macro to configure the ADC1 clock (ADC1CLK). + * @param __ADC1CLKSource__ specifies the ADC1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock + * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock + * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock + * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock + */ +#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__)) + +/** @brief Macro to get the ADC1 clock (ADC1CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock + * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock + * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock + * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock + */ +#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) +/** + * @} + */ + +/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config + * @{ + */ +/** @brief Macro to configure the SDADCx clock (SDADCxCLK). + * @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock + */ +#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__)) + +/** @brief Macro to get the SDADCx clock prescaler. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock + * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock + */ +#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE))) +/** + * @} + */ + +/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config + * @{ + */ +/** @brief Macro to configure the CEC clock. + * @param __CECCLKSource__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__)) + +/** @brief Macro to get the HDMI CEC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) +/** + * @} + */ + +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) + +/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config + * @{ + */ +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSource__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock + */ +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) +/** + * @} + */ + +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F302x8 || */ + /* STM32F373xC */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) + +/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config + * @{ + */ +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * @param __I2C3CLKSource__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__)) + +/** @brief Macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW))) +/** + * @} + */ + +/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config + * @{ + */ +/** @brief Macro to configure the TIM2 clock (TIM2CLK). + * @param __TIM2CLKSource__ specifies the TIM2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock + * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock + */ +#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__)) + +/** @brief Macro to get the TIM2 clock (TIM2CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock + * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock + */ +#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW))) + +/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK). + * @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock + * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock + */ +#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__)) + +/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock + * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock + */ +#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW))) + +/** @brief Macro to configure the TIM15 clock (TIM15CLK). + * @param __TIM15CLKSource__ specifies the TIM15 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock + * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock + */ +#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__)) + +/** @brief Macro to get the TIM15 clock (TIM15CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock + * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock + */ +#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW))) + +/** @brief Macro to configure the TIM16 clock (TIM16CLK). + * @param __TIM16CLKSource__ specifies the TIM16 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock + * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock + */ +#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__)) + +/** @brief Macro to get the TIM16 clock (TIM16CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock + * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock + */ +#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW))) + +/** @brief Macro to configure the TIM17 clock (TIM17CLK). + * @param __TIM17CLKSource__ specifies the TIM17 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock + * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock + */ +#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__)) + +/** @brief Macro to get the TIM17 clock (TIM17CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock + * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock + */ +#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW))) + +/** + * @} + */ + +#endif /* STM32f302xE || STM32f303xE || STM32F398xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx) +/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config + * @{ + */ +/** @brief Macro to configure the TIM20 clock (TIM20CLK). + * @param __TIM20CLKSource__ specifies the TIM20 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock + * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock + */ +#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__)) + +/** @brief Macro to get the TIM20 clock (TIM20CLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock + * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock + */ +#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW))) + +/** + * @} + */ +#endif /* STM32f303xE || STM32F398xx */ + +/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ + RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h new file mode 100644 index 0000000..149cc17 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h @@ -0,0 +1,852 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F3xx_HAL_SPI_H +#define STM32F3xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + CRC Length is only used with Data8 and Data16, not other data size + This parameter can be a value of @ref SPI_CRC_length */ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This parameter can be a value of @ref SPI_NSSP_Mode + This mode is activated by the NSSP bit in the SPIx_CR2 register and + it takes effect only if the SPI interface is configured as Motorola SPI + master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, + CPOL setting is ignored).. */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Code SPI Error Code + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000U) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000U) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_4BIT (0x00000300U) +#define SPI_DATASIZE_5BIT (0x00000400U) +#define SPI_DATASIZE_6BIT (0x00000500U) +#define SPI_DATASIZE_7BIT (0x00000600U) +#define SPI_DATASIZE_8BIT (0x00000700U) +#define SPI_DATASIZE_9BIT (0x00000800U) +#define SPI_DATASIZE_10BIT (0x00000900U) +#define SPI_DATASIZE_11BIT (0x00000A00U) +#define SPI_DATASIZE_12BIT (0x00000B00U) +#define SPI_DATASIZE_13BIT (0x00000C00U) +#define SPI_DATASIZE_14BIT (0x00000D00U) +#define SPI_DATASIZE_15BIT (0x00000E00U) +#define SPI_DATASIZE_16BIT (0x00000F00U) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000U) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000U) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT (0x00000000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) +/** + * @} + */ + +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode + * @{ + */ +#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP +#define SPI_NSS_PULSE_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000U) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000U) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000U) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC Length + * @{ + * This parameter can be one of the following values: + * SPI_CRC_LENGTH_DATASIZE: aligned with the data size + * SPI_CRC_LENGTH_8BIT : CRC 8bit + * SPI_CRC_LENGTH_16BIT : CRC 16bit + */ +#define SPI_CRC_LENGTH_DATASIZE (0x00000000U) +#define SPI_CRC_LENGTH_8BIT (0x00000001U) +#define SPI_CRC_LENGTH_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold + * @{ + * This parameter can be one of the following values: + * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : + * RXNE event is generated if the FIFO + * level is greater or equal to 1/4(8-bits). + * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO + * level is greater or equal to 1/2(16 bits). */ +#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ +#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ +#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ + | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) +/** + * @} + */ + +/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level + * @{ + */ +#define SPI_FTLVL_EMPTY (0x00000000U) +#define SPI_FTLVL_QUARTER_FULL (0x00000800U) +#define SPI_FTLVL_HALF_FULL (0x00001000U) +#define SPI_FTLVL_FULL (0x00001800U) + +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level + * @{ + */ +#define SPI_FRLVL_EMPTY (0x00000000U) +#define SPI_FRLVL_QUARTER_FULL (0x00000200U) +#define SPI_FRLVL_HALF_FULL (0x00000400U) +#define SPI_FRLVL_FULL (0x00000600U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ + }while(0U) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR register. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 register. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_4BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Select management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI NSS Pulse parameter is in allowed range. + * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. + * This parameter can be a value of @ref SPI_NSSP_Mode + * @retval None + */ +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI CRC length is in allowed range. + * @param __LENGTH__ specifies the SPI CRC length. + * This parameter can be a value of @ref SPI_CRC_length + * @retval None + */ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) + +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +/** + * @} + */ + +/* Include SPI HAL Extended module */ +#include "stm32f3xx_hal_spi_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F3xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h new file mode 100644 index 0000000..8f72788 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F3xx_HAL_SPI_EX_H +#define STM32F3xx_HAL_SPI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPIEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/** @addtogroup SPIEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F3xx_HAL_SPI_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h new file mode 100644 index 0000000..aa6a7ea --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h @@ -0,0 +1,2533 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F3xx_HAL_TIM_H +#define STM32F3xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ +#if defined(TIM_CR2_MMS2) + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ +#endif /* TIM_CR2_MMS2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BK2E) + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#endif /*TIM_BDTR_BK2E */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ +#if defined(TIM_CCER_CC5E) + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ +#endif /* TIM_CCER_CC6E */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#if defined(TIM_BDTR_BK2E) + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +#if defined(TIM_BDTR_BK2E) + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +#endif /* TIM_BDTR_BK2E */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +#if defined(TIM_SMCR_OCCS) +#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ +#endif /* TIM_SMCR_OCCS */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_OR 0x00000014U +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#if defined(TIM_EGR_B2G) +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +#endif /* TIM_EGR_B2G */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +#if defined(TIM_CR1_UIFREMAP) +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +#endif /* TIM_CR1_UIFREMAP */ +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#if defined(TIM_SR_CC5IF) +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#endif /* TIM_SR_CC5IF */ +#if defined(TIM_SR_CC6IF) +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#endif /* TIM_SR_CC6IF */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#if defined(TIM_SR_B2IF) +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#endif /* TIM_SR_B2IF */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#if defined(TIM_CCER_CC5E) +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#endif /* TIM_CCER_CC6E */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +#if defined(TIM_BDTR_BK2E) +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ +#endif /* TIM_BDTR_BK2E */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +#if defined(TIM_CCR5_CCR5) +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ +#endif /* TIM_CCR5_CCR5 */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +#if defined(TIM_CR2_MMS2) +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ +#endif /* TIM_CR2_MMS2 */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#if defined (TIM_SMCR_SMS_3) +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +#endif /* TIM_SMCR_SMS_3 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#if defined(TIM_CCMR1_OC1M_3) +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#endif /* TIM_CCMR1_OC1M_3 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) + * @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*) + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * (*) Value not defined for all devices + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) + * @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*) + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * (*) Value not defined for all devices + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +#if defined(TIM_CR1_UIFREMAP) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) +#endif /* TIM_CR1_UIFREMAP */ + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) +#else +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value (*) + * @arg TIM_CHANNEL_6: get capture/compare 6 register value (*) + * (*) Value not defined for all devices + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) +#else +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @retval None + */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) +#else +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @retval None + */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) +#else +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) +#else +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) +#else +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#if defined(TIM_SMCR_OCCS) +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) +#endif /* TIM_SMCR_OCCS */ + +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_OR)) +#else +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR)) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +#if defined(TIM_EGR_B2G) +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) +#else +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) +#endif /* TIM_EGR_B2G */ + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#if defined(TIM_CR1_UIFREMAP) +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + +#endif /* TIM_CR1_UIFREMAP */ +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) +#else +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) +#endif /* TIM_CCER_CC5E &&TIM_CCER_CC6E */ + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#if defined(TIM_BDTR_BK2E) +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) +#endif /* TIM_BDTR_BK2E */ + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#if defined(TIM_CCR5_CCR5) +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) +#endif /* TIM_CCR5_CCR5 */ + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#if defined(TIM_CR2_MMS2) +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) +#endif /* TIM_CR2_MMS2 */ + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#if defined (TIM_SMCR_SMS_3) +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) +#else +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) +#endif /* TIM_SMCR_SMS_3 */ + +#if defined(TIM_CCMR1_OC1M_3) +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) +#else +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) +#endif /* TIM_CCMR1_OC1M_3 */ + +#if defined(TIM_CCMR1_OC1M_3) +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) +#else +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) +#endif /* TIM_CCMR1_OC1M_3 */ + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#if defined (TIM_SMCR_SMS_3) +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) +#else +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) +#endif /* TIM_SMCR_SMS_3 */ + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) +#else +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + } while(0) +#endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f3xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F3xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h new file mode 100644 index 0000000..80c2df1 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h @@ -0,0 +1,343 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F3xx_HAL_TIM_EX_H +#define STM32F3xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal_def.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#if defined(TIM1) +#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ + +#if defined(ADC4) +#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */ +#elif defined(ADC2) +#define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ +#define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */ +#endif /* ADC4 */ +#endif /* TIM1 */ + +#if defined(TIM8) +#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */ + +#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */ +#endif /* TIM8 */ + +#if defined(TIM14) +#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */ +#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */ +#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */ +#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */ +#endif /* TIM14 */ + +#if defined(TIM16) +#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ +#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32 */ +#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ +#endif /* TIM16 */ + +#if defined(TIM20) +#define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ +#define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */ +#endif /* TIM20 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#if defined(TIM1) && defined(TIM8) && defined(TIM20) && defined(TIM16) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM20) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) +#elif defined(TIM1) && defined(TIM8) && defined(TIM16) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) +#elif defined(TIM1) && defined(TIM16) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ + || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) +#elif defined(TIM14) +#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ + (((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)) +#endif /* TIM1 && TIM8 && TIM20 && TIM16 */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined(TIM_CCR5_CCR5) +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +#endif /* TIM_CCR5_CCR5 */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +#if defined(TIM_BDTR_BK2E) +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +#endif /* TIM_BDTR_BK2E */ +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F3xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h new file mode 100644 index 0000000..c0058c4 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h @@ -0,0 +1,1063 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_BUS_H +#define __STM32F3xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN +#if defined(DMA2) +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN +#endif /*DMA2*/ +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN +#if defined(FMC_Bank1) +#define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN +#endif /*FMC_Bank1*/ +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +#if defined(GPIOH) +#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN +#endif /*GPIOH*/ +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN +#if defined(GPIOE) +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN +#endif /*GPIOE*/ +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN +#if defined(GPIOG) +#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN +#endif /*GPIOH*/ +#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN +#if defined(RCC_AHBENR_ADC1EN) +#define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN +#endif /*RCC_AHBENR_ADC1EN*/ +#if defined(ADC1_2_COMMON) +#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN +#endif /*ADC1_2_COMMON*/ +#if defined(ADC3_4_COMMON) +#define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN +#endif /*ADC3_4_COMMON*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#endif /*TIM3*/ +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#endif /*TIM4*/ +#if defined(TIM5) +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#endif /*TIM5*/ +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /*TIM7*/ +#if defined(TIM12) +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN +#endif /*TIM12*/ +#if defined(TIM13) +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN +#endif /*TIM13*/ +#if defined(TIM14) +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#endif /*TIM14*/ +#if defined(TIM18) +#define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN +#endif /*TIM18*/ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /*SPI2*/ +#if defined(SPI3) +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#endif /*SPI3*/ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#endif /*UART4*/ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#endif /*UART5*/ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#endif /*I2C2*/ +#if defined(USB) +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN +#endif /*USB*/ +#if defined(CAN) +#define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN +#endif /*CAN*/ +#if defined(DAC2) +#define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN +#endif /*DAC2*/ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /*CEC*/ +#if defined(I2C3) +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN +#endif /*I2C3*/ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#if defined(RCC_APB2ENR_ADC1EN) +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#endif /*RCC_APB2ENR_ADC1EN*/ +#if defined(TIM1) +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#endif /*TIM1*/ +#if defined(SPI1) +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#endif /*SPI1*/ +#if defined(TIM8) +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#endif /*TIM8*/ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(SPI4) +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#endif /*SPI4*/ +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#if defined(TIM19) +#define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN +#endif /*TIM19*/ +#if defined(TIM20) +#define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN +#endif /*TIM20*/ +#if defined(HRTIM1) +#define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN +#endif /*HRTIM1*/ +#if defined(SDADC1) +#define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN +#endif /*SDADC1*/ +#if defined(SDADC2) +#define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN +#endif /*SDADC2*/ +#if defined(SDADC3) +#define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN +#endif /*SDADC3*/ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n + * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n + * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n + * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n + * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n + * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n + * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_BUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h new file mode 100644 index 0000000..33d6af6 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h @@ -0,0 +1,640 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (MPU services provided only on some devices) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_CORTEX_H +#define __STM32F3xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M4 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC24 for Cortex-M4 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h new file mode 100644 index 0000000..7a21e12 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h @@ -0,0 +1,1996 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_DMA_H +#define __STM32F3xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA2) +#if defined (DMA2_Channel6) && defined (DMA2_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); +} + +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); +} + +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); +} + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); +} + +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); +} + +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); +} + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); +} + +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); +} + +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); +} + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); +} + +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); +} + +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); +} + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +/** + * @brief Clear Channel 6 global interrupt flag. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} + +/** + * @brief Clear Channel 7 global interrupt flag. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} + +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} + +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} + +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h new file mode 100644 index 0000000..6d09d63 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h @@ -0,0 +1,1383 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_EXTI_H +#define __STM32F3xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ +#if defined(EXTI_32_63_SUPPORT) + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ +#endif + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + +#if defined(EXTI_32_63_SUPPORT) +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#if defined(EXTI_IMR2_IM33) +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#endif +#if defined(EXTI_IMR2_IM34) +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#endif +#if defined(EXTI_IMR2_IM35) +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#endif +#if defined(EXTI_IMR2_IM36) +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#endif +#if defined(EXTI_IMR2_IM37) +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#endif +#if defined(EXTI_IMR2_IM38) +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#endif +#if defined(EXTI_IMR2_IM39) +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#endif +#if defined(EXTI_IMR2_IM40) +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#endif +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ + +#endif + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} +#endif + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} +#endif + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines from 32 to 34, line + * 39) is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} +#endif + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} +#endif + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} +#endif + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} +#endif + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} +#endif + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} +#endif + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)); +} +#endif + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + +#if defined(EXTI_32_63_SUPPORT) + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); +} +#endif + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + +#if defined(EXTI_32_63_SUPPORT) +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR2, ExtiLine); +} +#endif + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h new file mode 100644 index 0000000..80edfc4 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h @@ -0,0 +1,980 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_GPIO_H +#define __STM32F3xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, + (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, + (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h new file mode 100644 index 0000000..4d164cc --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h @@ -0,0 +1,2275 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F3xx_LL_I2C_H +#define STM32F3xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. + + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WriteReg function + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + * CR1 DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); +} + +/** + * @brief Enable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when Digital Filter is disabled. + * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Disable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Check if Wakeup from STOP is enabled or disabled. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + * @param I2Cx I2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + * @param I2Cx I2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) +{ + WRITE_REG(I2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + * CR1 SMBDEN LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + * CR1 SMBDEN LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +{ + WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize + * @param I2Cx I2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest + * @param I2Cx I2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr + * @param I2Cx I2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n + * CR2 ADD10 LL_I2C_HandleTransfer\n + * CR2 RD_WRN LL_I2C_HandleTransfer\n + * CR2 START LL_I2C_HandleTransfer\n + * CR2 STOP LL_I2C_HandleTransfer\n + * CR2 RELOAD LL_I2C_HandleTransfer\n + * CR2 NBYTES LL_I2C_HandleTransfer\n + * CR2 AUTOEND LL_I2C_HandleTransfer\n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param I2Cx I2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll PECR PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + WRITE_REG(I2Cx->TXDR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F3xx_LL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h new file mode 100644 index 0000000..9f900d6 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h @@ -0,0 +1,554 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_PWR_H +#define __STM32F3xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#if defined(PWR_PVD_SUPPORT) +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) +#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ +#endif /* PWR_CSR_VREFINTRDYF */ +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ +#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +#if defined(PWR_CR_LPDS) +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ +#endif /* PWR_CR_LPDS */ + +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ +/** + * @} + */ +#endif /* PWR_PVD_SUPPORT */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx + * @{ + */ +#if defined(SDADC1) +#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */ +#endif /* SDADC1 */ +#if defined(SDADC2) +#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */ +#endif /* SDADC2 */ +#if defined(SDADC3) +#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */ +#endif /* SDADC3 */ +/** + * @} + */ +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enables the SDADC peripheral functionality + * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n + * CR ENSD2 LL_PWR_EnableSDADC\n + * CR ENSD3 LL_PWR_EnableSDADC + * @param Analogx This parameter can be a combination of the following values: + * @arg @ref LL_PWR_SDADC_ANALOG1 + * @arg @ref LL_PWR_SDADC_ANALOG2 + * @arg @ref LL_PWR_SDADC_ANALOG3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx) +{ + SET_BIT(PWR->CR, Analogx); +} + +/** + * @brief Disables the SDADC peripheral functionality + * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n + * CR ENSD2 LL_PWR_EnableSDADC\n + * CR ENSD3 LL_PWR_EnableSDADC + * @param Analogx This parameter can be a combination of the following values: + * @arg @ref LL_PWR_SDADC_ANALOG1 + * @arg @ref LL_PWR_SDADC_ANALOG2 + * @arg @ref LL_PWR_SDADC_ANALOG3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx) +{ + CLEAR_BIT(PWR->CR, Analogx); +} + +/** + * @brief Check if SDADCx has been enabled or not + * @rmtoll CR ENSD1 LL_PWR_IsEnabledSDADC\n + * CR ENSD2 LL_PWR_IsEnabledSDADC\n + * CR ENSD3 LL_PWR_IsEnabledSDADC + * @param Analogx This parameter can be a combination of the following values: + * @arg @ref LL_PWR_SDADC_ANALOG1 + * @arg @ref LL_PWR_SDADC_ANALOG2 + * @arg @ref LL_PWR_SDADC_ANALOG3 + * @retval None + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx) +{ + return (READ_BIT(PWR->CR, Analogx) == (Analogx)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} + +#if defined(PWR_CR_LPDS) +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} +#endif /* PWR_CR_LPDS */ + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} +#endif /* PWR_PVD_SUPPORT */ + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_CSR_VREFINTRDYF) +/** + * @brief Get Internal Reference VrefInt Flag + * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); +} +#endif /* PWR_CSR_VREFINTRDYF */ +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h new file mode 100644 index 0000000..6426832 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h @@ -0,0 +1,2842 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_RCC_H +#define __STM32F3xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Defines used for the bit position in the register and perform offsets*/ +#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */ +#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */ +#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */ +#define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#if defined(RCC_CSR_V18PWRRSTF) +#define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ +#endif /* RCC_CSR_V18PWRRSTF */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ +#if defined(RCC_CFGR_PLLNODIV) +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ +#endif /* RCC_CFGR_PLLNODIV */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ +#if defined(RCC_CFGR_MCOPRE) +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ +#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ +#define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ +#define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ +#define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ +#endif /* RCC_CFGR_MCOPRE */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#if defined(RCC_CFGR3_USART1SW_PCLK1) +#define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */ +#else +#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */ +#endif /*RCC_CFGR3_USART1SW_PCLK1*/ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ +#if defined(RCC_CFGR3_USART2SW) +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ +#endif /* RCC_CFGR3_USART3SW */ +/** + * @} + */ + +#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) +/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */ +#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */ +/** + * @} + */ + +#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ + +/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */ +#if defined(RCC_CFGR3_I2C2SW) +#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */ +#endif /*RCC_CFGR3_I2C2SW*/ +#if defined(RCC_CFGR3_I2C3SW) +#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */ +#endif /*RCC_CFGR3_I2C3SW*/ +/** + * @} + */ + +#if defined(RCC_CFGR_I2SSRC) +/** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */ +#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */ +/** + * @} + */ + +#endif /* RCC_CFGR_I2SSRC */ + +#if defined(RCC_CFGR3_TIMSW) +/** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection + * @{ + */ +#define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */ +#define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */ +#if defined(RCC_CFGR3_TIM8SW) +#define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */ +#define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */ +#endif /*RCC_CFGR3_TIM8SW*/ +#if defined(RCC_CFGR3_TIM15SW) +#define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */ +#define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */ +#endif /*RCC_CFGR3_TIM15SW*/ +#if defined(RCC_CFGR3_TIM16SW) +#define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */ +#define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */ +#endif /*RCC_CFGR3_TIM16SW*/ +#if defined(RCC_CFGR3_TIM17SW) +#define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */ +#define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */ +#endif /*RCC_CFGR3_TIM17SW*/ +#if defined(RCC_CFGR3_TIM20SW) +#define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */ +#define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */ +#endif /*RCC_CFGR3_TIM20SW*/ +#if defined(RCC_CFGR3_TIM2SW) +#define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */ +#define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */ +#endif /*RCC_CFGR3_TIM2SW*/ +#if defined(RCC_CFGR3_TIM34SW) +#define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */ +#define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */ +#endif /*RCC_CFGR3_TIM34SW*/ +/** + * @} + */ + +#endif /* RCC_CFGR3_TIMSW */ + +#if defined(HRTIM1) +/** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection + * @{ + */ +#define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */ +#define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */ +/** + * @} + */ + +#endif /* HRTIM1 */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ +#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ +/** + * @} + */ + +#endif /* CEC */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */ +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */ +/** + * @} + */ + +#endif /* USB */ + +#if defined(RCC_CFGR_ADCPRE) +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */ +/** + * @} + */ + +#elif defined(RCC_CFGR2_ADC1PRES) +/** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */ +#define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */ +/** + * @} + */ + +#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) +#if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34) +/** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection + * @{ + */ +#define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection + * @{ + */ +#define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */ +#define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */ +/** + * @} + */ + +#else +/** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */ +#define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */ +/** + * @} + */ + +#endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */ + +#endif /* RCC_CFGR_ADCPRE */ + +#if defined(RCC_CFGR_SDPRE) +/** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection + * @{ + */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */ +#define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */ +/** + * @} + */ + +#endif /* RCC_CFGR_SDPRE */ + +/** @defgroup RCC_LL_EC_USART Peripheral USART get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ +#if defined(RCC_CFGR3_USART2SW) +#define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) +#define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ +#endif /* RCC_CFGR3_USART3SW */ +/** + * @} + */ + +#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) +/** @defgroup RCC_LL_EC_UART Peripheral UART get clock source + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */ +#define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ + +/** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ +#if defined(RCC_CFGR3_I2C2SW) +#define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */ +#endif /*RCC_CFGR3_I2C2SW*/ +#if defined(RCC_CFGR3_I2C3SW) +#define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */ +#endif /*RCC_CFGR3_I2C3SW*/ +/** + * @} + */ + +#if defined(RCC_CFGR_I2SSRC) +/** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source + * @{ + */ +#define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CFGR_I2SSRC */ + +#if defined(RCC_CFGR3_TIMSW) +/** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source + * @{ + */ +#define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */ +#if defined(RCC_CFGR3_TIM2SW) +#define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */ +#endif /*RCC_CFGR3_TIM2SW*/ +#if defined(RCC_CFGR3_TIM8SW) +#define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */ +#endif /*RCC_CFGR3_TIM8SW*/ +#if defined(RCC_CFGR3_TIM15SW) +#define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */ +#endif /*RCC_CFGR3_TIM15SW*/ +#if defined(RCC_CFGR3_TIM16SW) +#define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */ +#endif /*RCC_CFGR3_TIM16SW*/ +#if defined(RCC_CFGR3_TIM17SW) +#define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */ +#endif /*RCC_CFGR3_TIM17SW*/ +#if defined(RCC_CFGR3_TIM20SW) +#define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */ +#endif /*RCC_CFGR3_TIM20SW*/ +#if defined(RCC_CFGR3_TIM34SW) +#define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */ +#endif /*RCC_CFGR3_TIM34SW*/ +/** + * @} + */ + +#endif /* RCC_CFGR3_TIMSW */ + +#if defined(HRTIM1) +/** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source + * @{ + */ +#define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */ +/** + * @} + */ + +#endif /* HRTIM1 */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ +/** + * @} + */ + +#endif /* CEC */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */ +/** + * @} + */ + +#endif /* USB */ + +#if defined(RCC_CFGR_ADCPRE) +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CFGR_ADCPRE */ + +#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) +/** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source + * @{ + */ +#if defined(RCC_CFGR2_ADC1PRES) +#define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */ +#else +#define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */ +#if defined(RCC_CFGR2_ADCPRE34) +#define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */ +#endif /*RCC_CFGR2_ADCPRE34*/ +#endif /*RCC_CFGR2_ADC1PRES*/ +/** + * @} + */ + +#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ + +#if defined(RCC_CFGR_SDPRE) +/** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source + * @{ + */ +#define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CFGR_SDPRE */ + + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + * @{ + */ +#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ +#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ +#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ +#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ +#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ +#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ +#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ +#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ +#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ +#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ +#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ +#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ +#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ +#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ +#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + * @{ + */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as main PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ +#else +#define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + * @{ + */ +#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ +#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ +#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ +#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ +#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ +#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ +#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ +#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ +#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ +#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ +#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ +#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ +#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ +#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ +#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() + * , @ref LL_RCC_PLL_GetPrediv()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @param __PLLPREDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ + (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) + +#else +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +/** + * @brief Helper macro to calculate the HCLK frequency + * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__: This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler + * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__: This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disable the Clock Security System. + * @note Cannot be disabled in HSE is ready (only by hardware) + * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO\n + * CFGR PLLNODIV LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 + * + * (*) value not defined in all devices + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 (*) + * @arg @ref LL_RCC_MCO1_DIV_4 (*) + * @arg @ref LL_RCC_MCO1_DIV_8 (*) + * @arg @ref LL_RCC_MCO1_DIV_16 (*) + * @arg @ref LL_RCC_MCO1_DIV_32 (*) + * @arg @ref LL_RCC_MCO1_DIV_64 (*) + * @arg @ref LL_RCC_MCO1_DIV_128 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ +#if defined(RCC_CFGR_MCOPRE) +#if defined(RCC_CFGR_PLLNODIV) + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); +#else + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +#endif /* RCC_CFGR_PLLNODIV */ +#else + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); +#endif /* RCC_CFGR_MCOPRE */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n + * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n + * CFGR3 USART3SW LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); +} + +#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) +/** + * @brief Configure UARTx clock source + * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n + * CFGR3 UART5SW LL_RCC_SetUARTClockSource + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) +{ + MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW))); +} +#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ + +/** + * @brief Configure I2Cx clock source + * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n + * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n + * CFGR3 I2C3SW LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU)); +} + +#if defined(RCC_CFGR_I2SSRC) +/** + * @brief Configure I2Sx clock source + * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource); +} +#endif /* RCC_CFGR_I2SSRC */ + +#if defined(RCC_CFGR3_TIMSW) +/** + * @brief Configure TIMx clock source + * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n + * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n + * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n + * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n + * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n + * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n + * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n + * CFGR3 TIM34SW LL_RCC_SetTIMClockSource + * @param TIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource) +{ + MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU)); +} +#endif /* RCC_CFGR3_TIMSW */ + +#if defined(HRTIM1) +/** + * @brief Configure HRTIMx clock source + * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource + * @param HRTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource); +} +#endif /* HRTIM1 */ + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); +} +#endif /* CEC */ + +#if defined(USB) +/** + * @brief Configure USB clock source + * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); +} +#endif /* USB */ + +#if defined(RCC_CFGR_ADCPRE) +/** + * @brief Configure ADC clock source + * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); +} + +#elif defined(RCC_CFGR2_ADC1PRES) +/** + * @brief Configure ADC clock source + * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource); +} + +#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) +/** + * @brief Configure ADC clock source + * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n + * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256 + * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ +#if defined(RCC_CFGR2_ADCPRE34) + MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU)); +#else + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource); +#endif /* RCC_CFGR2_ADCPRE34 */ +} +#endif /* RCC_CFGR_ADCPRE */ + +#if defined(RCC_CFGR_SDPRE) +/** + * @brief Configure SDADCx clock source + * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource + * @param SDADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource); +} +#endif /* RCC_CFGR_SDPRE */ + +/** + * @brief Get USARTx clock source + * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n + * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n + * CFGR3 USART3SW LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); +} + +#if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) +/** + * @brief Get UARTx clock source + * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n + * CFGR3 UART5SW LL_RCC_GetUARTClockSource + * @param UARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U)); +} +#endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ + +/** + * @brief Get I2Cx clock source + * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n + * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n + * CFGR3 I2C3SW LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U)); +} + +#if defined(RCC_CFGR_I2SSRC) +/** + * @brief Get I2Sx clock source + * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); +} +#endif /* RCC_CFGR_I2SSRC */ + +#if defined(RCC_CFGR3_TIMSW) +/** + * @brief Get TIMx clock source + * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n + * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n + * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n + * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n + * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n + * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n + * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n + * CFGR3 TIM34SW LL_RCC_GetTIMClockSource + * @param TIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE + * @arg @ref LL_RCC_TIM2_CLKSOURCE (*) + * @arg @ref LL_RCC_TIM8_CLKSOURCE (*) + * @arg @ref LL_RCC_TIM15_CLKSOURCE (*) + * @arg @ref LL_RCC_TIM16_CLKSOURCE (*) + * @arg @ref LL_RCC_TIM17_CLKSOURCE (*) + * @arg @ref LL_RCC_TIM20_CLKSOURCE (*) + * @arg @ref LL_RCC_TIM34_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U)); +} +#endif /* RCC_CFGR3_TIMSW */ + +#if defined(HRTIM1) +/** + * @brief Get HRTIMx clock source + * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource + * @param HRTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_HRTIM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx)); +} +#endif /* HRTIM1 */ + +#if defined(CEC) +/** + * @brief Get CEC clock source + * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); +} +#endif /* CEC */ + +#if defined(USB) +/** + * @brief Get USBx clock source + * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); +} +#endif /* USB */ + +#if defined(RCC_CFGR_ADCPRE) +/** + * @brief Get ADCx clock source + * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); +} + +#elif defined(RCC_CFGR2_ADC1PRES) +/** + * @brief Get ADCx clock source + * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128 + * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256 + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); +} + +#elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) +/** + * @brief Get ADCx clock source + * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n + * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC12_CLKSOURCE + * @arg @ref LL_RCC_ADC34_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128 + * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256 + * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*) + * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ +#if defined(RCC_CFGR2_ADCPRE34) + return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U)); +#else + return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); +#endif /*RCC_CFGR2_ADCPRE34*/ +} +#endif /* RCC_CFGR_ADCPRE */ + +#if defined(RCC_CFGR_SDPRE) +/** + * @brief Get SDADCx clock source + * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource + * @param SDADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44 + * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx)); +} +#endif /* RCC_CFGR_SDPRE */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed any more unless + * the Backup domain is reset. The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @param PLLDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); +} + +#else + +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); +} +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ + +/** + * @brief Configure PLL clock source + * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI (*) + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI (*) + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +} + +/** + * @brief Get PLL multiplication Factor + * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); +} + +/** + * @brief Get PREDIV division factor for the main PLL + * @note They can be written only when the PLL is disabled + * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 + * @arg @ref LL_RCC_PREDIV_DIV_4 + * @arg @ref LL_RCC_PREDIV_DIV_5 + * @arg @ref LL_RCC_PREDIV_DIV_6 + * @arg @ref LL_RCC_PREDIV_DIV_7 + * @arg @ref LL_RCC_PREDIV_DIV_8 + * @arg @ref LL_RCC_PREDIV_DIV_9 + * @arg @ref LL_RCC_PREDIV_DIV_10 + * @arg @ref LL_RCC_PREDIV_DIV_11 + * @arg @ref LL_RCC_PREDIV_DIV_12 + * @arg @ref LL_RCC_PREDIV_DIV_13 + * @arg @ref LL_RCC_PREDIV_DIV_14 + * @arg @ref LL_RCC_PREDIV_DIV_15 + * @arg @ref LL_RCC_PREDIV_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +#if defined(RCC_CFGR_MCOF) +/** + * @brief Check if switch to new MCO source is effective or not + * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void) +{ + return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF)); +} +#endif /* RCC_CFGR_MCOF */ + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +#if defined(RCC_CSR_V18PWRRSTF) +/** + * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. + * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); +} +#endif /* RCC_CSR_V18PWRRSTF */ + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +#if defined(UART4) || defined(UART5) +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); +#endif /* UART4 || UART5 */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +#if defined(RCC_CFGR_I2SSRC) +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#endif /* RCC_CFGR_I2SSRC */ +#if defined(USB_OTG_FS) || defined(USB) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB */ +#if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)) +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +#endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ +#if defined(RCC_CFGR_SDPRE) +uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource); +#endif /*RCC_CFGR_SDPRE */ +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +#if defined(RCC_CFGR3_TIMSW) +uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource); +#endif /*RCC_CFGR3_TIMSW*/ +uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h new file mode 100644 index 0000000..d47644d --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h @@ -0,0 +1,1724 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_SYSTEM_H +#define __STM32F3xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */ +#define SYSCFG_OFFSET_CFGR1 0x00000000U +#define SYSCFG_OFFSET_CFGR3 0x00000050U + +/* Mask used for TIM breaks functions */ +#if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) +#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK) +#elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) +#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK) +#elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) +#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK) +#else +#define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK) +#endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP + * @{ + */ +#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */ +#if defined(FMC_BANK1) +#define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @arg @ref LL_SYSCFG_REMAP_FMC (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); +} + +#if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP) +/** + * @brief Set DMA request remapping bits for SPI + * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n + * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 + * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 + * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 + * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 + * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 + * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF)); +} +#endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */ + +#if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP) +/** + * @brief Set DMA request remapping bits for I2C + * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n + * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 + * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 + * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 + * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 + * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 + * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF)); +} +#endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */ + +#if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP) +/** + * @brief Set DMA request remapping bits for ADC + * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n + * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*) + * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*) + * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*) + * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*) + * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U)); + MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU)); +} +#endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */ + +/** + * @brief Set DMA request remapping bits for DAC + * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n + * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 + * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 + * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*) + * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*) + * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*) + * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*) + * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U)); +} + +/** + * @brief Set DMA request remapping bits for TIM + * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n + * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM + * @param Remap This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 + * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 + * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3 + * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*) + * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U)); +} + +#if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE) +/** + * @brief Set Timer input remap + * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n + * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*) + * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*) + * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*) + * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*) + * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*) + * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU)); +} +#endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */ + +#if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP) +/** + * @brief Set ADC Trigger remap + * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n + * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 + * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO + * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 + * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 + * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 + * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 + * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO + * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 + * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 + * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 + * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 + * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO + * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 + * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 + * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 + * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 + * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 + * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO + * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 + * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 + * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 + * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 + * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 + * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO + * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 + * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 + * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO + * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap) +{ + MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU)); +} +#endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */ + +#if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP) +/** + * @brief Set DAC Trigger remap + * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n + * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n + * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC + * @param Remap This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*) + * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*) + * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*) + * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*) + * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*) + * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*) + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U)); + MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U)); +} +#endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */ + +#if defined(SYSCFG_CFGR1_USB_IT_RMP) +/** + * @brief Enable USB interrupt remap + * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76 + * respectively + * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP); +} + +/** + * @brief Disable USB interrupt remap + * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP); +} +#endif /* SYSCFG_CFGR1_USB_IT_RMP */ + +#if defined(SYSCFG_CFGR1_VBAT) +/** + * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input) + * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT); +} + +/** + * @brief Disable VBAT monitoring + * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT); +} +#endif /* SYSCFG_CFGR1_VBAT */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); +} + +/** + * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); +} + +/** + * @brief Enable Floating Point Unit Underflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); +} + +/** + * @brief Enable Floating Point Unit Overflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); +} + +/** + * @brief Enable Floating Point Unit Input denormal Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); +} + +/** + * @brief Enable Floating Point Unit Inexact Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); +} + +/** + * @brief Disable Floating Point Unit Invalid operation Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); +} + +/** + * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); +} + +/** + * @brief Disable Floating Point Unit Underflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); +} + +/** + * @brief Disable Floating Point Unit Overflow Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); +} + +/** + * @brief Disable Floating Point Unit Input denormal Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); +} + +/** + * @brief Disable Floating Point Unit Inexact Interrupt + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); +} + +/** + * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)); +} + +/** + * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)); +} + +/** + * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)); +} + +/** + * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)); +} + +/** + * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)); +} + +/** + * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) +{ + return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH (*) + * + * (*) value not defined in all devices. + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); +} + +/** + * @brief Set connections to TIMx Break inputs + * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*) + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break); +} + +/** + * @brief Get connections to TIMx Break inputs + * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*) + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK)); +} + +#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR) +/** + * @brief Disable RAM Parity Check Disable + * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void) +{ + SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR); +} +#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */ + +#if defined(SYSCFG_CFGR2_SRAM_PE) +/** + * @brief Check if SRAM parity error detected + * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) +{ + return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE)); +} + +/** + * @brief Clear SRAM parity error flag + * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) +{ + SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE); +} +#endif /* SYSCFG_CFGR2_SRAM_PE */ + +#if defined(SYSCFG_RCR_PAGE0) +/** + * @brief Enable CCM SRAM page write protection + * @note Write protection is cleared only by a system reset + * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n + * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP + * @param PageWRP This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0 + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1 + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2 + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3 + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*) + * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP) +{ + SET_BIT(SYSCFG->RCR, PageWRP); +} +#endif /* SYSCFG_RCR_PAGE0 */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422 + * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432 + * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438. + * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439 + * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE ); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE ); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); +} + +#if defined(FLASH_ACR_HLFCYA) +/** + * @brief Enable Flash Half Cycle Access + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); +} + +/** + * @brief Disable Flash Half Cycle Access + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); +} + +/** + * @brief Check if Flash Half Cycle Access is enabled or not + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); +} +#endif /* FLASH_ACR_HLFCYA */ + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_SYSTEM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h new file mode 100644 index 0000000..0c18159 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h @@ -0,0 +1,282 @@ +/** + ****************************************************************************** + * @file stm32f3xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F3xx_LL_UTILS_H +#define __STM32F3xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx.h" + +/** @addtogroup STM32F3xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +#else + uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +#if defined(FLASH_ACR_LATENCY) +ErrorStatus LL_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F3xx_LL_UTILS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/License.md b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/License.md new file mode 100644 index 0000000..d12cc8e --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/License.md @@ -0,0 +1,3 @@ +# Copyright (c) 2016 STMicroelectronics + +This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c new file mode 100644 index 0000000..56980b0 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c @@ -0,0 +1,531 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs categories: + (+) HAL Initialization and de-initialization functions + (+) HAL Control functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HAL_Private Constants + * @{ + */ +/** + * @brief STM32F3xx HAL Driver version number V1.5.6 + */ +#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ +#define __STM32F3xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ +#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32F3xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK (0x00000FFFU) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface, the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) de-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __Weak + to make override possible in case of other implementations in user file. + +@endverbatim + * @{ + */ + +/** + * @brief This function configures the Flash prefetch, + * Configures time base source, NVIC and Low level hardware + * @note This function is called at the beginning of program after reset and before + * the clock configuration + * + * @note The Systick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset and the NVIC configuration is set to Priority group 4 + * + * @note The time base configuration is based on MSI clock when exting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation,Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __Weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Povides a tick value in millisecond. + * @note The function is declared as __Weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * The function is declared as __Weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) + +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * The function is declared as __Weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + +} + +/** + * @brief This function returns the HAL revision + * @retval version 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F3xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c new file mode 100644 index 0000000..6fba113 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c @@ -0,0 +1,2420 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be triggered by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. + + Function HAL_CAN_RegisterCallback() allows to register following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + + By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + example HAL_CAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() + or HAL_CAN_Init() function. + + When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +#if defined(CAN) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcan->MspInitCallback == NULL) + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + } +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Stop the CAN module */ + (void)HAL_CAN_Stop(hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->MspDeInitCallback == NULL) + { + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hcan->MspDeInitCallback(hcan); + +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspDeInit(hcan); +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CAN CallBack. + * To be used instead of the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = pCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = pCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = pCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = pCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a CAN CallBack. + * CAN callabck is redirected to the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = HAL_CAN_SleepCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = HAL_CAN_ErrorCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip = hcan->Instance; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + + /* CAN is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_LISTENING) + { + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Increment counter */ + count++; + + /* Check if timeout is reached */ + if (count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Check transmit mailbox value */ + if (transmitmailbox > 2U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; + + return HAL_ERROR; + } + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + { + /* Transmission Mailbox 0 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + { + /* Transmission Mailbox 1 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + { + /* Transmission Mailbox 2 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + { + /* Receive FIFO 0 message pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + { + /* Receive FIFO 1 message pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Call Error callback function */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } + } + + /* Return CAN state */ + return state; +} + +/** + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +{ + /* Return CAN error code */ + return hcan->ErrorCode; +} + +/** + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Reset CAN error code */ + hcan->ErrorCode = 0U; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; + } + + /* Return the status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CAN_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CAN */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c new file mode 100644 index 0000000..641711d --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c @@ -0,0 +1,513 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0FU). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f3xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* + Additional Tables: CORTEX_NVIC_Priority_Table + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ========================================================================================================================== + +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @param PreemptPriority The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1U) + +/** + * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation) + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU->CTRL = 0U; +} + +/** + * @brief Enables the MPU + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +} + + /** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != RESET) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Return 1 if pending else 0U */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0U */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c new file mode 100644 index 0000000..cb6a091 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c @@ -0,0 +1,900 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Channel, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + using HAL_DMA_Init() function. + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + + /* Check the DMA handle allocation */ + if(NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Get the CR register value */ + tmp = hdma->Instance->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR)); + + /* Prepare the DMA Channel configuration */ + tmp |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* Write to DMA Channel CR register */ + hdma->Instance->CCR = tmp; + + /* Initialize DmaBaseAddress and ChannelIndex parameters used + by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + DMA_CalcBaseAndBitshift(hdma); + + /* Initialise the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if(NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + hdma->Instance->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + hdma->Instance->CPAR = 0U; + + /* Reset DMA Channel memory address register */ + hdma->Instance->CMAR = 0U; + + /* Get DMA Base Address */ + DMA_CalcBaseAndBitshift(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief I/O operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete, & transfer error interrupts */ + /* Half transfer interrupt is optional: enable it only if associated callback is available */ + if(NULL != hdma->XferHalfCpltCallback ) + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + } + else + { + hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Enable the Peripheral */ + hdma->Instance->CCR |= DMA_CCR_EN; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + } + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Abort the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + + /* Disable DMA IT */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Disable the channel */ + hdma->Instance->CCR &= ~DMA_CCR_EN; + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << hdma->ChannelIndex; + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << hdma->ChannelIndex; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + { + if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CCR &= ~DMA_IT_HT; + } + + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + + /* DMA peripheral state is not updated in Half Transfer */ + /* State is updated only in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete & transfer error interrupts */ + /* if the DMA mode is not CIRCULAR */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Clear the transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management ***************************************/ + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Then, disable all DMA interrupts */ + hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameters. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @brief Set the DMA base address and channel index depending on DMA instance + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ +#if defined (DMA2) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + /* calculation of the channel index */ + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; +#endif +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + + /** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c new file mode 100644 index 0000000..3120041 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c @@ -0,0 +1,621 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ + regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Get pending bit */ + regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + + /* Clear Pending bit */ + *regaddr = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (&EXTI->SWIER + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c new file mode 100644 index 0000000..6da1eca --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c @@ -0,0 +1,695 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) Option Bytes programming + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F3xx devices. + + (#) FLASH Memory I/O Programming functions: this group includes all needed + functions to erase and program the main memory: + (++) Lock and Unlock the FLASH interface + (++) Erase function: Erase page, erase all pages + (++) Program functions: half word, word and doubleword + (#) FLASH Option Bytes Programming functions: this group includes all needed + functions to manage the Option Bytes: + (++) Lock and Unlock the Option Bytes + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Launch the Option Bytes loader + (++) Erase Option Bytes + (++) Program the data Option Bytes + (++) Get the Write protection. + (++) Get the user option bytes. + + (#) Interrupts and flags management functions : this group + includes all needed functions to: + (++) Handle FLASH interrupts + (++) Wait for last FLASH operation according to its status + (++) Get error flag status + + [..] In addition to these function, this driver includes a set of macros allowing + to handle the following operations: + + (+) Set/Get the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the half cycle access + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macro ---------------------------- ---------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim +@endverbatim + * @{ + */ + +/** + * @brief Program halfword, word or double word at a specified address + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @note FLASH should be previously erased before new programming (only exception to this + * is when 0x0000 is programmed) + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint8_t index = 0U; + uint8_t nbiterations = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /* Program halfword (16-bit) at a specified address. */ + nbiterations = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /* Program word (32-bit = 2*16-bit) at a specified address. */ + nbiterations = 2U; + } + else + { + /* Program double word (64-bit = 4*16-bit) at a specified address. */ + nbiterations = 4U; + } + + for (index = 0U; index < nbiterations; index++) + { + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + /* In case of error, stop programming procedure */ + if (status != HAL_OK) + { + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program halfword, word or double word at a specified address with interrupt enabled. + * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifie the address to be programmed. + * @param Data Specifie the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + pFlash.Address = Address; + pFlash.Data = Data; + + if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + /* Program halfword (16-bit) at a specified address. */ + pFlash.DataRemaining = 1U; + } + else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + /* Program word (32-bit : 2*16-bit) at a specified address. */ + pFlash.DataRemaining = 2U; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + /* Program double word (64-bit : 4*16-bit) at a specified address. */ + pFlash.DataRemaining = 4U; + } + + /* Program halfword (16-bit) at a specified address. */ + FLASH_Program_HalfWord(Address, (uint16_t)Data); + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /* Return the faulty address */ + addresstmp = pFlash.Address; + /* Reset address */ + pFlash.Address = 0xFFFFFFFFU; + + /* Save the Error code */ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + /* Process can continue only if no error detected */ + if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of pages to erased can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still pages to erase */ + if(pFlash.DataRemaining != 0U) + { + addresstmp = pFlash.Address; + /*Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + pFlash.Address = addresstmp; + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + FLASH_PageErase(addresstmp); + } + else + { + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Address = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* Operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0U); + + /* Stop Mass Erase procedure*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + else + { + /* Nb of 16-bit data to program can be decreased */ + pFlash.DataRemaining--; + + /* Check if there are still 16-bit data to program */ + if(pFlash.DataRemaining != 0U) + { + /* Increment address to 16-bit */ + pFlash.Address += 2U; + addresstmp = pFlash.Address; + + /* Shift to have next 16-bit data */ + pFlash.Data = (pFlash.Data >> 16U); + + /* Operation is completed, disable the PG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + } + else + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + } + else + { + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + } + + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + } + + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PG, PER and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + + /* Disable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Mass Erase: No return value expected + * - Pages Erase: Address of the page which returned an error + * - Program: Address which was selected for data program + * @retval none + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @note This function will reset automatically the MCU. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OBL_Launch bit to launch the option byte loading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be: + * @ref FLASH_Error_Codes + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to program the new data */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Write data in the address */ + *(__IO uint16_t*)Address = Data; +} + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + { + if (Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* There is no error flag set */ + return HAL_OK; +} + + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + uint32_t flags = 0U; + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + flags |= FLASH_FLAG_WRPERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + flags |= FLASH_FLAG_PGERR; + } + /* Clear FLASH error pending bits */ + __HAL_FLASH_CLEAR_FLAG(flags); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c new file mode 100644 index 0000000..4364751 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c @@ -0,0 +1,983 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * + Extended Initialization/de-initialization functions + * + Extended I/O operation functions + * + Extended Peripheral Control functions + * + @verbatim + ============================================================================== + ##### Flash peripheral extended features ##### + ============================================================================== + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F3xxx devices. It includes + + (++) Set/Reset the write protection + (++) Program the user Option Bytes + (++) Get the Read protection Level + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH + * @{ + */ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variables used for Erase pages under interruption*/ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW) +#define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0) +#define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +/* Erase operations */ +static void FLASH_MassErase(void); +void FLASH_PageErase(uint32_t PageAddress); + +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); +static uint32_t FLASH_OB_GetWRP(void); +static uint32_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetUser(void); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) HAL_FLASHEx_Erase: return only when erase has been done + (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback + is called with parameter 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). + +@endverbatim + * @{ + */ + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError pointer to variable that + * contains the configuration information on faulty page in case of error + * (0xFFFFFFFF means that all the pages have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t address = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass Erase requested for Bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Mass erase to be done*/ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the MER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + } + } + else + { + /* Page Erase is requested */ + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + /* Page Erase requested on address located on bank1 */ + /* Wait for last operation to be completed */ + if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + /* Erase page by page to be done*/ + for(address = pEraseInit->PageAddress; + address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + address += FLASH_PAGE_SIZE) + { + FLASH_PageErase(address); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the PER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = address; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + * must be called before. + * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* If procedure already ongoing, reject the next one */ + if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation and Error source interrupts */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + FLASH_MassErase(); + } + else + { + /* Erase by page to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + + pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + pFlash.DataRemaining = pEraseInit->NbPages; + pFlash.Address = pEraseInit->PageAddress; + + /*Erase 1st page and wait for IT*/ + FLASH_PageErase(pEraseInit->PageAddress); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @brief Option Bytes Programming functions + * +@verbatim + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + option bytes operations. + +@endverbatim + * @{ + */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) +{ + uint8_t rdptmp = OB_RDP_LEVEL_0; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Get the actual read protection Option Byte value */ + rdptmp = FLASH_OB_GetRDP(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Restore the last read protection Option Byte value */ + status = FLASH_OB_RDP_LevelConfig(rdptmp); + } + } + + /* Return the erase status */ + return status; +} + +/** + * @brief Program option bytes + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /* Enable of Write protection on the selected page */ + status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + } + else + { + /* Disable of Write protection on the selected page */ + status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + } + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* DATA configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + { + status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + return status; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + + /*Get WRP*/ + pOBInit->WRPPage = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); +} + +/** + * @brief Get the Option byte user data + * @param DATAAdress Address of the option byte DATA + * This parameter can be one of the following values: + * @arg @ref OB_DATA_ADDRESS_DATA0 + * @arg @ref OB_DATA_ADDRESS_DATA1 + * @retval Value programmed in USER data + */ +uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) +{ + uint32_t value = 0U; + + if (DATAAdress == OB_DATA_ADDRESS_DATA0) + { + /* Get value programmed in OB USER Data0 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + } + else + { + /* Get value programmed in OB USER Data1 */ + value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + } + + return value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Full erase of FLASH memory Bank + * + * @retval None + */ +static void FLASH_MassErase(void) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Only bank1 will be erased*/ + SET_BIT(FLASH->CR, FLASH_CR_MER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @brief Enable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write protected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFFU; +#if defined(OB_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFFU; +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFFU; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFFU; +#endif /* OB_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be protected ******/ + WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO255MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); +#endif /* OB_WRP_PAGES48TO63MASK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + /* Enable write protection */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 &= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ + +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 &= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ + +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 &= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 &= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Disable the write protection of the desired pages + * @note An option byte erase is done automatically in this function. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash page i if + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WriteProtectPage specifies the page(s) to be write unprotected. + * The value of this parameter depend on device used within the same series + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) +{ + HAL_StatusTypeDef status = HAL_OK; + uint16_t WRP0_Data = 0xFFFFU; +#if defined(OB_WRP1_WRP1) + uint16_t WRP1_Data = 0xFFFFU; +#endif /* OB_WRP1_WRP1 */ +#if defined(OB_WRP2_WRP2) + uint16_t WRP2_Data = 0xFFFFU; +#endif /* OB_WRP2_WRP2 */ +#if defined(OB_WRP3_WRP3) + uint16_t WRP3_Data = 0xFFFFU; +#endif /* OB_WRP3_WRP3 */ + + /* Check the parameters */ + assert_param(IS_OB_WRP(WriteProtectPage)); + + /* Get current write protected pages and the new pages to be unprotected ******/ + WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + +#if defined(OB_WRP_PAGES0TO15MASK) + WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); +#endif /* OB_WRP_PAGES0TO31MASK */ + +#if defined(OB_WRP_PAGES16TO31MASK) + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); +#endif /* OB_WRP_PAGES32TO63MASK */ + +#if defined(OB_WRP_PAGES32TO47MASK) + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); +#endif /* OB_WRP_PAGES32TO47MASK */ + +#if defined(OB_WRP_PAGES48TO127MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); +#elif defined(OB_WRP_PAGES48TO255MASK) + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); +#endif /* OB_WRP_PAGES48TO63MASK */ + + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* To be able to write again option byte, need to perform a option byte erase */ + status = HAL_FLASHEx_OBErase(); + if (status == HAL_OK) + { + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(OB_WRP0_WRP0) + if(WRP0_Data != 0xFFU) + { + OB->WRP0 |= WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP0_WRP0 */ + +#if defined(OB_WRP1_WRP1) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + { + OB->WRP1 |= WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP1_WRP1 */ + +#if defined(OB_WRP2_WRP2) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + { + OB->WRP2 |= WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP2_WRP2 */ + +#if defined(OB_WRP3_WRP3) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + { + OB->WRP3 |= WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } +#endif /* OB_WRP3_WRP3 */ + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + return status; +} + +/** + * @brief Set the read protection level. + * @param ReadProtectLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* If the previous operation is completed, proceed to erase the option bytes */ + SET_BIT(FLASH->CR, FLASH_CR_OPTER); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the OPTER Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + + if(status == HAL_OK) + { + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + + WRITE_REG(OB->RDP, ReadProtectLevel); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte. + * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); + assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); + assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); + assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); +#if defined(FLASH_OBR_SDADC12_VDD_MONITOR) + assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET))); +#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enable the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + +#if defined(FLASH_OBR_SDADC12_VDD_MONITOR) + OB->USER = (UserConfig | 0x08U); +#else + OB->USER = (UserConfig | 0x88U); +#endif + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes + * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes + * (system reset will occur) + * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + * @param Address specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data specifies the data to be programmed. + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Enables the Option Bytes Programming operation */ + SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the OPTPG Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval The FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(READ_REG(FLASH->WRPR)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH RDP level + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t tmp_reg = 0U; + + /* Read RDP level bits */ +#if defined(FLASH_OBR_RDPRT) + tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); +#elif defined(FLASH_OBR_LEVEL1_PROT) + tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT)); +#endif /* FLASH_OBR_RDPRT */ + +#if defined(FLASH_OBR_RDPRT) + if (tmp_reg == FLASH_OBR_RDPRT_2) +#elif defined(FLASH_OBR_LEVEL1_PROT) + if (tmp_reg == FLASH_OBR_LEVEL2_PROT) +#endif /* FLASH_OBR_RDPRT */ + { + return OB_RDP_LEVEL_2; + } + else if (tmp_reg == 0U) + { + return OB_RDP_LEVEL_0; + } + else + { + return OB_RDP_LEVEL_1; + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), + * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Erase the specified FLASH memory page + * @param PageAddress FLASH page to erase + * The value of this parameter depend on device used within the same series + * + * @retval None + */ +void FLASH_PageErase(uint32_t PageAddress) +{ + /* Clean the error context */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Proceed to erase the page */ + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, PageAddress); + SET_BIT(FLASH->CR, FLASH_CR_STRT); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c new file mode 100644 index 0000000..e1f91fe --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c @@ -0,0 +1,542 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants + * @{ + */ +#define GPIO_NUMBER (16U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + temp |= (GPIO_Init->Speed << (position * 2u)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + temp |= ((GPIO_Init->Pull) << (position * 2u)); + GPIOx->PUPDR = temp; + } + + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2u]; + temp &= ~(0x0FuL << (4u * (position & 0x03u))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + SYSCFG->EXTICR[position >> 2u] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~(iocurrent); + if((GPIO_Init->Mode & EXTI_IT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + + temp = EXTI->EMR; + temp &= ~(iocurrent); + if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~(iocurrent); + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~(iocurrent); + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2u]; + tmp &= (0x0FuL << (4u * (position & 0x03u))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~((uint32_t)iocurrent); + EXTI->FTSR &= ~((uint32_t)iocurrent); + + /* Configure the External Interrupt or event for the current IO */ + tmp = 0x0FuL << (4u * (position & 0x03u)); + SYSCFG->EXTICR[position >> 2u] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + * @param GPIO_Pin specifies the pin to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Ouput Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** +* @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c new file mode 100644 index 0000000..af58c50 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c @@ -0,0 +1,6794 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + return HAL_ERROR; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* In case of Soft End condition, generate the STOP condition */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c new file mode 100644 index 0000000..c36afb6 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c @@ -0,0 +1,367 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F3xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c new file mode 100644 index 0000000..3ad97c3 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c @@ -0,0 +1,461 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + @verbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + forced in input pull down configuration and is active on rising edges. + (+) There are up to three WakeUp pins: + (++)WakeUp Pin 1 on PA.00. + (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only). + (++)WakeUp Pin 3 on PE.06. + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + + Refer to the datasheets for more details. + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices). + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + (+) Exit: + (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode to minimize the consumption. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) + function with: + (++) Main regulator ON or + (++) Low Power regulator ON. + (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or + (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + (+) Exit: + (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, + when programmed in wakeup mode (the peripheral must be + programmed in wakeup mode and the corresponding interrupt vector + must be enabled in the NVIC). + + *** Standby mode *** + ==================== + [..] + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. + The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + The voltage regulator is OFF. + + (+) Entry: + (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (+) Exit: + (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event, a time-stamp event, or a comparator event, + without depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. + + (+) Comparator auto-wakeup (AWU) from the Stop mode + + (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: + (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U) + to be sensitive to to the selected edges (falling, rising or falling + and rising) (Interrupt or Event modes) using the EXTI_Init() function. + (+++) Configure the comparator to generate the event. +@endverbatim + * @{ + */ + +/** + * @brief Enables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + * This parameter can be value of : + * @ref PWR_WakeUp_Pins + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Enable the EWUPx pin */ + SET_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be values of : + * @ref PWR_WakeUp_Pins + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + /* Disable the EWUPx pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param Regulator Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @note This parameter has no effect in F3 family and is just maintained to + * offer full portability of other STM32 families softwares. + * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. + * When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STOP mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); + + /* Set LPDS bit according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available), + * - RTC alternate function pins if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out, + * - WKUP pins if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c new file mode 100644 index 0000000..69e35e9 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c @@ -0,0 +1,272 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWREx HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWR Extended Private Constants + * @{ + */ +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions + * @brief Extended Peripheral Control functions + * +@verbatim + + =============================================================================== + ##### Peripheral Extended control functions ##### + =============================================================================== + *** PVD configuration (present on all other devices than STM32F3x8 devices) *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro + (+) The PVD is stopped in Standby mode. + -@- PVD is not available on STM32F3x8 Product Line + + + *** Voltage regulator *** + ========================= + [..] + (+) The voltage regulator is always enabled after Reset. It works in three different + modes. + In Run mode, the regulator supplies full power to the 1.8V domain (core, memories + and digital peripherals). + In Stop mode, the regulator supplies low power to the 1.8V domain, preserving + contents of registers and SRAM. + In Stop mode, the regulator is powered off. The contents of the registers and SRAM + are lost except for the Standby circuitry and the Backup Domain. + Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the + microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage. + + + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro + (+) The PVD is stopped in Standby mode. + + + *** SDADC power configuration *** + ================================ + [..] + (+) On STM32F373xC/STM32F378xx devices, there are up to + 3 SDADC instances that can be enabled/disabled. + +@endverbatim + * @{ + */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || \ + defined(STM32F302xC) || defined(STM32F303xC) || \ + defined(STM32F303x8) || defined(STM32F334x8) || \ + defined(STM32F301x8) || defined(STM32F302x8) || \ + defined(STM32F373xC) + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F303x8 || STM32F334x8 || */ + /* STM32F301x8 || STM32F302x8 || */ + /* STM32F373xC */ + +#if defined(STM32F373xC) || defined(STM32F378xx) + +/** + * @brief Enables the SDADC peripheral functionaliy + * @param Analogx specifies the SDADC peripheral instance. + * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3. + * @retval None + */ +void HAL_PWREx_EnableSDADC(uint32_t Analogx) +{ + /* Check the parameters */ + assert_param(IS_PWR_SDADC_ANALOG(Analogx)); + + /* Enable PWR clock interface for SDADC use */ + __HAL_RCC_PWR_CLK_ENABLE(); + + PWR->CR |= Analogx; +} + +/** + * @brief Disables the SDADC peripheral functionaliy + * @param Analogx specifies the SDADC peripheral instance. + * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3. + * @retval None + */ +void HAL_PWREx_DisableSDADC(uint32_t Analogx) +{ + /* Check the parameters */ + assert_param(IS_PWR_SDADC_ANALOG(Analogx)); + + PWR->CR &= ~Analogx; +} + +#endif /* STM32F373xC || STM32F378xx */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c new file mode 100644 index 0000000..007ff2e --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c @@ -0,0 +1,1224 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + and all peripherals are off except internal SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + [..] Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals whose clocks are not + derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC +* @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +/* Bits position in in the CFGR register */ +#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE) +#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1) +#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, + 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; +const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, + 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + The HSI clock can be used also to clock the USART and I2C peripherals. + + (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring different output clocks: + (++) The first output is used to generate the high speed system clock (up to 72 MHz) + (++) The second output is used to generate the clock for the USB FS (48 MHz) + (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz) + (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz) + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M4 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL + clock (divided by 2) output on pin (such as PA8 pin). + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: + (++) The FLASH program/erase clock which is always HSI 8MHz clock. + (++) The USB 48 MHz clock which is derived from the PLL VCO clock. + (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. + (++) The I2C clock which can be derived as well from HSI 8MHz clock. + (++) The ADC clock which is derived from PLL output. + (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC + (HSE divided by a programmable prescaler). The System clock (SYSCLK) + frequency must be higher or equal to the RTC clock frequency. + (++) IWDG clock which is always the LSI clock. + + (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz, + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + + (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + prefetch is disabled. + @endverbatim + * @{ + */ + +/* + Additional consideration on the SYSCLK based on Latency settings: + +-----------------------------------------------+ + | Latency | SYSCLK clock frequency (MHz) | + |---------------|-------------------------------| + |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + |---------------|-------------------------------| + |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + |---------------|-------------------------------| + |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | + +-----------------------------------------------+ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS and MCO1 OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart = 0; + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Insure HSIRDY bit is set before writing default HSITRIM value */ + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM default value */ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, RCC_CR_HSITRIM_4); + + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO); + + /* Insure HSI selected as system clock source */ + /* Get start tick */ + tickstart = HAL_GetTick(); + + /* Wait till system clock source is ready */ + while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + { + if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Update the SystemCoreClock global variable for HSI as system clock source */ + SystemCoreClock = HSI_VALUE; + + /* Configure the source of time base considering new system clock settings */ + if(HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Reset HSEON, CSSON, PLLON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Insure PLLRDY is reset */ + /* Get start tick */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Reset CFGR2 register */ + CLEAR_REG(RCC->CFGR2); + + /* Reset CFGR3 register */ + CLEAR_REG(RCC->CFGR3); + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIR); + + /* Reset all CSR flags */ + __HAL_RCC_CLEAR_RESET_FLAGS(); + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + uint32_t pll_config2; +#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) + { + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + /* Configure the HSE predivision factor --------------------------------*/ + __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + + /* Check the HSE State */ + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + /* Configure the main PLL clock source, predivider and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PREDIV, + RCC_OscInitStruct->PLL.PLLMUL); +#else + /* Configure the main PLL clock source and multiplication factor. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLMUL); +#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->CFGR; +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + pll_config2 = RCC->CFGR2; + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) +#else + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) +#endif + { + return HAL_ERROR; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * The value of this parameter depend on device used within the same series + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart = 0U; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if(FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if(__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick (uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + + @endverbatim + * @{ + */ + +#if defined(RCC_CFGR_MCOPRE) +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected + * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + * @retval None + */ +#else +/** + * @brief Selects the clock source to output on MCO pin. + * @note MCO pin should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + * @param RCC_MCODiv specifies the MCO DIV. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @retval None + */ +#endif +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef gpio; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* Configure the MCO1 pin in alternate function mode */ + gpio.Mode = GPIO_MODE_AF_PP; + gpio.Speed = GPIO_SPEED_FREQ_HIGH; + gpio.Pull = GPIO_NOPULL; + gpio.Pin = MCO1_PIN; + gpio.Alternate = GPIO_AF0_MCO; + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + + /* Configure the MCO clock source */ + __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) + * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. + * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + { + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)]; +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); + } +#else + if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + } +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + sysclockfreq = pllclk; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: /* HSI used as system clock */ + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + + /* Get the HSE configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); +#endif + + /* Get the HSI configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); + + /* Get the LSE configuration -----------------------------------------------*/ + if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + + /* Get the PLL configuration -----------------------------------------------*/ + if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); +#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); +#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * contains the current clock configuration. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != NULL); + assert_param(pFLatency != NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c new file mode 100644 index 0000000..cb44fb4 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c @@ -0,0 +1,1584 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/** @defgroup RCCEx RCCEx + * @brief RCC Extension HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \ + || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \ + || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \ + || defined(RCC_CFGR3_HRTIM1SW) +/** @defgroup RCCEx_Private_Functions RCCEx Private Functions + * @{ + */ +static uint32_t RCC_GetPLLCLKFreq(void); + +/** + * @} + */ +#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks + * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @note When the TIMx clock source is APB clock, so the TIMx clock is APB clock or + * APB clock x 2 depending on the APB prescaler. + * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t temp_reg = 0U; + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = temp_reg; + + /* Wait for LSERDY if LSE was enabled */ + if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------- USART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + +#if defined(RCC_CFGR3_USART2SW) + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } +#endif /* RCC_CFGR3_USART2SW */ + +#if defined(RCC_CFGR3_USART3SW) + /*------------------------------ USART3 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } +#endif /* RCC_CFGR3_USART3SW */ + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) + /*------------------------------ USB Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); + } + +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F302x8 || */ + /* STM32F373xC */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) + + /*------------------------------ I2C2 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + /*------------------------------ I2C3 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) + + /*------------------------------ UART4 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*------------------------------ UART5 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + /*------------------------------ I2S Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure the I2S clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + } + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + /*------------------------------ ADC1 clock Configuration ------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1) + { + /* Check the parameters */ + assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection)); + + /* Configure the ADC1 clock source */ + __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection); + } + +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) + + /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) + { + /* Check the parameters */ + assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); + + /* Configure the ADC12 clock source */ + __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); + } + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) + + /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34) + { + /* Check the parameters */ + assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection)); + + /* Configure the ADC34 clock source */ + __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection); + } + +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F373xC) || defined(STM32F378xx) + + /*------------------------------ ADC1 clock Configuration ------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1) + { + /* Check the parameters */ + assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection)); + + /* Configure the ADC1 clock source */ + __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection); + } + +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + /*------------------------------ TIM1 clock Configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); + + /* Configure the TIM1 clock source */ + __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); + } + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) + + /*------------------------------ TIM8 clock Configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection)); + + /* Configure the TIM8 clock source */ + __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection); + } + +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + /*------------------------------ TIM15 clock Configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + + /* Configure the TIM15 clock source */ + __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + } + + /*------------------------------ TIM16 clock Configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection)); + + /* Configure the TIM16 clock source */ + __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection); + } + + /*------------------------------ TIM17 clock Configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection)); + + /* Configure the TIM17 clock source */ + __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection); + } + +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F334x8) + + /*------------------------------ HRTIM1 clock Configuration ----------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); + + /* Configure the HRTIM1 clock source */ + __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); + } + +#endif /* STM32F334x8 */ + +#if defined(STM32F373xC) || defined(STM32F378xx) + + /*------------------------------ SDADC clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC) + { + /* Check the parameters */ + assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection)); + + /* Configure the SDADC clock prescaler */ + __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection); + } + + /*------------------------------ CEC clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) + + /*------------------------------ TIM2 clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection); + } + + /*------------------------------ TIM3 clock Configuration -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection); + } + + /*------------------------------ TIM15 clock Configuration ------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + } + + /*------------------------------ TIM16 clock Configuration ------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection); + } + + /*------------------------------ TIM17 clock Configuration ------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection); + } + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx) + /*------------------------------ TIM20 clock Configuration ------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); + } +#endif /* STM32F303xE || STM32F398xx */ + + + return HAL_OK; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks + * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks). + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + /* Common part first */ +#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; +#else + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; +#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ + + /* Get the RTC configuration --------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USART1 clock configuration --------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); +#if defined(RCC_CFGR3_USART2SW) + /* Get the USART2 clock configuration -----------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) + /* Get the USART3 clock configuration -----------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); +#endif /* RCC_CFGR3_USART3SW */ + /* Get the I2C1 clock configuration -----------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + +#if defined(STM32F302xE) || defined(STM32F303xE)\ + || defined(STM32F302xC) || defined(STM32F303xC)\ + || defined(STM32F302x8) \ + || defined(STM32F373xC) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + /* Get the USB clock configuration -----------------------------------------*/ + PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE(); + +#endif /* STM32F302xE || STM32F303xE || */ + /* STM32F302xC || STM32F303xC || */ + /* STM32F302x8 || */ + /* STM32F373xC */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2; + /* Get the I2C2 clock configuration -----------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3; + /* Get the I2C3 clock configuration -----------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) + + PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5); + /* Get the UART4 clock configuration -----------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + /* Get the UART5 clock configuration -----------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S; + /* Get the I2S clock configuration -----------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + || defined(STM32F373xC) || defined(STM32F378xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1; + /* Get the ADC1 clock configuration -----------------------------------------*/ + PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE(); + +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12; + /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/ + PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE(); + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34; + /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/ + PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE(); + +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1; + /* Get the TIM1 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE(); + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + /* STM32F302xC || STM32F303xC || STM32F358xx || */ + /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F303xE) || defined(STM32F398xx)\ + || defined(STM32F303xC) || defined(STM32F358xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8; + /* Get the TIM8 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE(); + +#endif /* STM32F303xE || STM32F398xx || */ + /* STM32F303xC || STM32F358xx */ + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + + PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17); + /* Get the TIM15 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); + /* Get the TIM16 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE(); + /* Get the TIM17 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE(); + +#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + +#if defined(STM32F334x8) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; + /* Get the HRTIM1 clock configuration -----------------------------------------*/ + PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); + +#endif /* STM32F334x8 */ + +#if defined(STM32F373xC) || defined(STM32F378xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC; + /* Get the SDADC clock configuration -----------------------------------------*/ + PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE(); + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; + /* Get the CEC clock configuration -----------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2; + /* Get the TIM2 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE(); + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34; + /* Get the TIM3 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE(); + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15; + /* Get the TIM15 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16; + /* Get the TIM16 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE(); + + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17; + /* Get the TIM17 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE(); + +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + +#if defined (STM32F303xE) || defined(STM32F398xx) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20; + /* Get the TIM20 clock configuration -----------------------------------------*/ + PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE(); +#endif /* STM32F303xE || STM32F398xx */ +} + +/** + * @brief Returns the peripheral clock frequency + * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable. + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + @if STM32F301x8 + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + @endif + @if STM32F302x8 + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + @endif + @if STM32F302xC + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + @endif + @if STM32F302xE + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + @endif + @if STM32F303x8 + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + @endif + @if STM32F303xC + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + @endif + @if STM32F303xE + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + @endif + @if STM32F318xx + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + @endif + @if STM32F328xx + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + @endif + @if STM32F334x8 + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock + @endif + @if STM32F358xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + @endif + @if STM32F373xC + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F378xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + @endif + @if STM32F398xx + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock + * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + @endif + * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* frequency == 0 : means that no available frequency for the peripheral */ + uint32_t frequency = 0U; + + uint32_t srcclk = 0U; +#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) + uint16_t adc_pll_prediv_table[16] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U}; +#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ +#if defined(RCC_CFGR_SDPRE) + uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U}; +#endif /* RCC_CFGR_SDPRE */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_RTC: + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + { + frequency = HSE_VALUE / 32U; + } + break; + } + case RCC_PERIPHCLK_USART1: + { + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + /* Check if USART1 clock selection is PCLK1 */ +#if defined(RCC_USART1CLKSOURCE_PCLK2) + if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } +#else + if (srcclk == RCC_USART1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } +#endif /* RCC_USART1CLKSOURCE_PCLK2 */ + /* Check if HSI is ready and if USART1 clock selection is HSI */ + else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART1 clock selection is SYSCLK */ + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART1 clock selection is LSE */ + else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#if defined(RCC_CFGR3_USART2SW) + case RCC_PERIPHCLK_USART2: + { + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + /* Check if USART2 clock selection is PCLK1 */ + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART2 clock selection is HSI */ + else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART2 clock selection is SYSCLK */ + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART2 clock selection is LSE */ + else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_USART2SW */ +#if defined(RCC_CFGR3_USART3SW) + case RCC_PERIPHCLK_USART3: + { + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + /* Check if USART3 clock selection is PCLK1 */ + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if USART3 clock selection is HSI */ + else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if USART3 clock selection is SYSCLK */ + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if USART3 clock selection is LSE */ + else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_USART3SW */ +#if defined(RCC_CFGR3_UART4SW) + case RCC_PERIPHCLK_UART4: + { + /* Get the current UART4 source */ + srcclk = __HAL_RCC_GET_UART4_SOURCE(); + + /* Check if UART4 clock selection is PCLK1 */ + if (srcclk == RCC_UART4CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if UART4 clock selection is HSI */ + else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if UART4 clock selection is SYSCLK */ + else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if UART4 clock selection is LSE */ + else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_UART4SW */ +#if defined(RCC_CFGR3_UART5SW) + case RCC_PERIPHCLK_UART5: + { + /* Get the current UART5 source */ + srcclk = __HAL_RCC_GET_UART5_SOURCE(); + + /* Check if UART5 clock selection is PCLK1 */ + if (srcclk == RCC_UART5CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if HSI is ready and if UART5 clock selection is HSI */ + else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if UART5 clock selection is SYSCLK */ + else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + /* Check if LSE is ready and if UART5 clock selection is LSE */ + else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_UART5SW */ + case RCC_PERIPHCLK_I2C1: + { + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Check if HSI is ready and if I2C1 clock selection is HSI */ + if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if I2C1 clock selection is SYSCLK */ + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + break; + } +#if defined(RCC_CFGR3_I2C2SW) + case RCC_PERIPHCLK_I2C2: + { + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Check if HSI is ready and if I2C2 clock selection is HSI */ + if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if I2C2 clock selection is SYSCLK */ + else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + break; + } +#endif /* RCC_CFGR3_I2C2SW */ +#if defined(RCC_CFGR3_I2C3SW) + case RCC_PERIPHCLK_I2C3: + { + /* Get the current I2C3 source */ + srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Check if HSI is ready and if I2C3 clock selection is HSI */ + if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if I2C3 clock selection is SYSCLK */ + else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + break; + } +#endif /* RCC_CFGR3_I2C3SW */ +#if defined(RCC_CFGR_I2SSRC) + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */ + if (srcclk == RCC_I2SCLKSOURCE_EXT) + { + /* External clock used. Frequency cannot be returned.*/ + frequency = 0xDEADDEADU; + } + /* Check if I2S clock selection is SYSCLK */ + else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + break; + } +#endif /* RCC_CFGR_I2SSRC */ +#if defined(RCC_CFGR_USBPRE) + case RCC_PERIPHCLK_USB: + { + /* Check if PLL is ready */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) + { + /* Get the current USB source */ + srcclk = __HAL_RCC_GET_USB_SOURCE(); + + /* Check if USB clock selection is not divided */ + if (srcclk == RCC_USBCLKSOURCE_PLL) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if USB clock selection is divided by 1.5 */ + else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */ + { + frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U; + } + } + break; + } +#endif /* RCC_CFGR_USBPRE */ +#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE) + case RCC_PERIPHCLK_ADC1: + { + /* Get the current ADC1 source */ + srcclk = __HAL_RCC_GET_ADC1_SOURCE(); +#if defined(RCC_CFGR2_ADC1PRES) + /* Check if ADC1 clock selection is AHB */ + if (srcclk == RCC_ADC1PLLCLK_OFF) + { + frequency = SystemCoreClock; + } + /* PLL clock has been selected */ + else + { + /* Check if PLL is ready */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) + { + /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */ + frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU]; + } + } +#else /* RCC_CFGR_ADCPRE */ + /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */ + frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U); +#endif /* RCC_CFGR2_ADC1PRES */ + break; + } +#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */ +#if defined(RCC_CFGR2_ADCPRE12) + case RCC_PERIPHCLK_ADC12: + { + /* Get the current ADC12 source */ + srcclk = __HAL_RCC_GET_ADC12_SOURCE(); + /* Check if ADC12 clock selection is AHB */ + if (srcclk == RCC_ADC12PLLCLK_OFF) + { + frequency = SystemCoreClock; + } + /* PLL clock has been selected */ + else + { + /* Check if PLL is ready */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) + { + /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */ + frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF]; + } + } + break; + } +#endif /* RCC_CFGR2_ADCPRE12 */ +#if defined(RCC_CFGR2_ADCPRE34) + case RCC_PERIPHCLK_ADC34: + { + /* Get the current ADC34 source */ + srcclk = __HAL_RCC_GET_ADC34_SOURCE(); + /* Check if ADC34 clock selection is AHB */ + if (srcclk == RCC_ADC34PLLCLK_OFF) + { + frequency = SystemCoreClock; + } + /* PLL clock has been selected */ + else + { + /* Check if PLL is ready */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) + { + /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */ + frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF]; + } + } + break; + } +#endif /* RCC_CFGR2_ADCPRE34 */ +#if defined(RCC_CFGR3_TIM1SW) + case RCC_PERIPHCLK_TIM1: + { + /* Get the current TIM1 source */ + srcclk = __HAL_RCC_GET_TIM1_SOURCE(); + + /* Check if PLL is ready and if TIM1 clock selection is PLL */ + if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if TIM1 clock selection is SYSCLK */ + else if (srcclk == RCC_TIM1CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_TIM1SW */ +#if defined(RCC_CFGR3_TIM2SW) + case RCC_PERIPHCLK_TIM2: + { + /* Get the current TIM2 source */ + srcclk = __HAL_RCC_GET_TIM2_SOURCE(); + + /* Check if PLL is ready and if TIM2 clock selection is PLL */ + if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if TIM2 clock selection is SYSCLK */ + else if (srcclk == RCC_TIM2CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_TIM2SW */ +#if defined(RCC_CFGR3_TIM8SW) + case RCC_PERIPHCLK_TIM8: + { + /* Get the current TIM8 source */ + srcclk = __HAL_RCC_GET_TIM8_SOURCE(); + + /* Check if PLL is ready and if TIM8 clock selection is PLL */ + if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if TIM8 clock selection is SYSCLK */ + else if (srcclk == RCC_TIM8CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_TIM8SW */ +#if defined(RCC_CFGR3_TIM15SW) + case RCC_PERIPHCLK_TIM15: + { + /* Get the current TIM15 source */ + srcclk = __HAL_RCC_GET_TIM15_SOURCE(); + + /* Check if PLL is ready and if TIM15 clock selection is PLL */ + if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if TIM15 clock selection is SYSCLK */ + else if (srcclk == RCC_TIM15CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_TIM15SW */ +#if defined(RCC_CFGR3_TIM16SW) + case RCC_PERIPHCLK_TIM16: + { + /* Get the current TIM16 source */ + srcclk = __HAL_RCC_GET_TIM16_SOURCE(); + + /* Check if PLL is ready and if TIM16 clock selection is PLL */ + if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if TIM16 clock selection is SYSCLK */ + else if (srcclk == RCC_TIM16CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_TIM16SW */ +#if defined(RCC_CFGR3_TIM17SW) + case RCC_PERIPHCLK_TIM17: + { + /* Get the current TIM17 source */ + srcclk = __HAL_RCC_GET_TIM17_SOURCE(); + + /* Check if PLL is ready and if TIM17 clock selection is PLL */ + if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if TIM17 clock selection is SYSCLK */ + else if (srcclk == RCC_TIM17CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_TIM17SW */ +#if defined(RCC_CFGR3_TIM20SW) + case RCC_PERIPHCLK_TIM20: + { + /* Get the current TIM20 source */ + srcclk = __HAL_RCC_GET_TIM20_SOURCE(); + + /* Check if PLL is ready and if TIM20 clock selection is PLL */ + if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if TIM20 clock selection is SYSCLK */ + else if (srcclk == RCC_TIM20CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_TIM20SW */ +#if defined(RCC_CFGR3_TIM34SW) + case RCC_PERIPHCLK_TIM34: + { + /* Get the current TIM34 source */ + srcclk = __HAL_RCC_GET_TIM34_SOURCE(); + + /* Check if PLL is ready and if TIM34 clock selection is PLL */ + if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if TIM34 clock selection is SYSCLK */ + else if (srcclk == RCC_TIM34CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_TIM34SW */ +#if defined(RCC_CFGR3_HRTIM1SW) + case RCC_PERIPHCLK_HRTIM1: + { + /* Get the current HRTIM1 source */ + srcclk = __HAL_RCC_GET_HRTIM1_SOURCE(); + + /* Check if PLL is ready and if HRTIM1 clock selection is PLL */ + if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) + { + frequency = RCC_GetPLLCLKFreq(); + } + /* Check if HRTIM1 clock selection is SYSCLK */ + else if (srcclk == RCC_HRTIM1CLK_HCLK) + { + frequency = SystemCoreClock; + } + break; + } +#endif /* RCC_CFGR3_HRTIM1SW */ +#if defined(RCC_CFGR_SDPRE) + case RCC_PERIPHCLK_SDADC: + { + /* Get the current SDADC source */ + srcclk = __HAL_RCC_GET_SDADC_SOURCE(); + /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */ + frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF]; + break; + } +#endif /* RCC_CFGR_SDPRE */ +#if defined(RCC_CFGR3_CECSW) + case RCC_PERIPHCLK_CEC: + { + /* Get the current CEC source */ + srcclk = __HAL_RCC_GET_CEC_SOURCE(); + + /* Check if HSI is ready and if CEC clock selection is HSI */ + if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) + { + frequency = HSI_VALUE; + } + /* Check if LSE is ready and if CEC clock selection is LSE */ + else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + { + frequency = LSE_VALUE; + } + break; + } +#endif /* RCC_CFGR3_CECSW */ + default: + { + break; + } + } + return(frequency); +} + +/** + * @} + */ + +/** + * @} + */ + + +#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \ + || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \ + || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \ + || defined(RCC_CFGR3_HRTIM1SW) + +/** @addtogroup RCCEx_Private_Functions + * @{ + */ +static uint32_t RCC_GetPLLCLKFreq(void) +{ + uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U; + + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + pllmul = ( pllmul >> 18U) + 2U; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; +#if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + if (pllsource != RCC_PLLSOURCE_HSI) + { + prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (HSE_VALUE/prediv) * pllmul; + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */ + pllclk = (HSI_VALUE >> 1U) * pllmul; + } +#else + prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + pllclk = (HSE_VALUE/prediv) * pllmul; + } + else + { + /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ + pllclk = (HSI_VALUE/prediv) * pllmul; + } +#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + + return pllclk; +} +/** + * @} + */ + +#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c new file mode 100644 index 0000000..5d270f8 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c @@ -0,0 +1,4458 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + + [..] + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + + @endverbatim + + Additional table : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Transfer mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Transfer mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + uint32_t frxth; + + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + } +#if (USE_SPI_CRC != 0U) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Align by default the rs fifo threshold on the data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + } + else + { + frxth = SPI_RXFIFO_THRESHOLD_QF; + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + } + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCL Configuration -------------------*/ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + } + } +#endif /* USE_SPI_CRC */ + + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + (hspi->Init.TIMode & SPI_CR2_FRF) | + (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + (frxth & SPI_CR2_FRXTH))); + +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + uint16_t initial_TxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + initial_TxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr ++; + hspi->TxXferCount--; + } + } + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error: + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + uint32_t tickstart; + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + /* this is done to handle the CRCNEXT before the latest data */ + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + /* read the received data */ + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + + /* Read the latest data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* the latest data has not been received */ + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Receive last data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Read CRC to Flush DR and RXNE flag */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, + uint32_t Timeout) +{ + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + uint32_t spi_cr1; + uint32_t spi_cr2; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + initial_RxXferCount = Size; +#if (USE_SPI_CRC != 0U) + spi_cr1 = READ_REG(hspi->Instance->CR1); + spi_cr2 = READ_REG(hspi->Instance->CR2); +#endif /* USE_SPI_CRC */ + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set fiforxthreshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + if (hspi->RxXferCount > 1U) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount <= 1U) + { + /* Set RX Fifo threshold before to switch on 8 bit data size */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + } + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + { + errorcode = HAL_TIMEOUT; + goto error; + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Read CRC from DR to close CRC calculation process */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read CRC */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } + } + + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + /* Clear CRC Flag */ + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + + errorcode = HAL_ERROR; + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; + + /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + /* Set RX Fifo threshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } + SPI_RESET_CRC(hspi); + } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } + SPI_RESET_CRC(hspi); + } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ + + /* Check if packing mode is enabled and if there is more than 2 data to receive */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) + { + /* Set RX Fifo threshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + /* Packing mode is enabled only if the DMA setting is HALWORD */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Check the even/odd of the data size + crc if enabled */ + if ((hspi->TxXferCount & 0x1U) == 0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U); + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + +#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx) + /* Packing mode management is enabled by the DMA settings */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Restriction the DMA data received is not allowed in this mode */ + errorcode = HAL_ERROR; + goto error; + } +#endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */ + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + +error: + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + +#if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx) || defined (STM32F378xx) + /* Packing mode management is enabled by the DMA settings */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Restriction the DMA data received is not allowed in this mode */ + errorcode = HAL_ERROR; + goto error; + } +#endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */ + + /* Reset the threshold bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); + + /* The packing mode management is enabled by the DMA settings according the spi data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + if ((hspi->TxXferSize & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = hspi->TxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } + } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + + hspi->State = HAL_SPI_STATE_READY; + goto error; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + hspi->State = HAL_SPI_STATE_READY; + return errorcode; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + + /* SPI in mode Receiver ----------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + { + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + return; + } + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->TxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) + { + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + else + { + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Stop the disable DMA transfer on SPI side */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in packing mode */ + if (hspi->RxXferCount > 1U) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount == 1U) + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + /* Receive data in 8 Bit mode */ + else + { + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + } + + /* Check end of the reception */ + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + hspi->CRCSize--; + + /* Check end of the reception */ + if (hspi->CRCSize == 0U) + { + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in packing Bit mode */ + if (hspi->TxXferCount >= 2U) + { + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + /* Transmit data in 8 Bit mode */ + else + { + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + + /* Check the end of the transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + hspi->CRCSize--; + + if (hspi->CRCSize == 0U) + { + SPI_CloseRx_ISR(hspi); + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; + } + } + + return HAL_OK; +} + +/** + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + + while ((hspi->Instance->SR & Fifo) != State) + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + { + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; + } + } + + return HAL_OK; +} + +/** + * @brief Handle the check of the RX transaction complete. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + /* Control if the TX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the RX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle abort a Rx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count; + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count; + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + + /* Check TXEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c new file mode 100644 index 0000000..71f3181 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_spi_ex.c + * @author MCD Application Team + * @brief Extended SPI HAL module driver. + * This file provides firmware functions to manage the following + * SPI peripheral extended functionalities : + * + IO operation functions + * + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup SPIEx SPIEx + * @brief SPI Extended HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPIEx_Private_Constants SPIEx Private Constants + * @{ + */ +#define SPI_FIFO_SIZE 4UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + * @{ + */ + +/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of extended functions to manage the SPI + data transfers. + + (#) Rx data flush function: + (++) HAL_SPIEx_FlushRxFifo() + +@endverbatim + * @{ + */ + +/** + * @brief Flush the RX fifo. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg; + uint8_t count = 0U; + while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) + { + count++; + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* To avoid GCC warning */ + if (count == SPI_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c new file mode 100644 index 0000000..9bab4be --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c @@ -0,0 +1,7942 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback (when supported). + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +#if defined(TIM_CCER_CC5E) +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +#endif /* TIM_CCER_CC6E */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +#if defined(TIM_BDTR_BK2E) + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +#endif /* TIM_BDTR_BK2E */ + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + +#if defined(TIM_CCER_CC5E) + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } +#endif /* TIM_CCER_CC5E */ + +#if defined(TIM_CCER_CC6E) + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } +#endif /* TIM_CCER_CC6E */ + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + * (*) Value not defined for all devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + +#if defined(TIM_CCER_CC5E) + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } +#endif /* TIM_CCER_CC5E */ + +#if defined(TIM_CCER_CC6E) + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } +#endif /* TIM_CCER_CC6E */ + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 (*) + * @arg TIM_DMABASE_CCR5 (*) + * @arg TIM_DMABASE_CCR6 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + } + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 (*) + * @arg TIM_DMABASE_CCR5 (*) + * @arg TIM_DMABASE_CCR6 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 (*) + * @arg TIM_DMABASE_CCR5 (*) + * @arg TIM_DMABASE_CCR6 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + } + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 (*) + * @arg TIM_DMABASE_CCR5 (*) + * @arg TIM_DMABASE_CCR6 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances + * supporting a break input. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 (*) + * @arg TIM_CHANNEL_6: TIM Channel 6 (*) + * (*) Value not defined for all devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ +#if defined(TIM_SMCR_OCCS) + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); +#else + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); +#endif /* TIM_SMCR_OCCS */ + break; + } +#if defined(TIM_SMCR_OCCS) + case TIM_CLEARINPUTSOURCE_OCREFCLR: + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + } + break; +#endif /* TIM_SMCR_OCCS */ + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); +#if defined(TIM_SMCR_OCCS) + + /* Set the OCREF clear selection bit */ + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); +#endif /* TIM_SMCR_OCCS */ + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } +#if defined(TIM_CCER_CC5E) + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } +#endif /* TIM_CCER_CC5E */ +#if defined(TIM_CCER_CC6E) + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } +#endif /* TIM_CCER_CC6E */ + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID +#if defined(TIM_BDTR_BK2E) + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID +#endif + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; +#if defined(TIM_BDTR_BK2E) + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; +#endif /* TIM_BDTR_BK2E */ + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID +#if defined(TIM_BDTR_BK2E) + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID +#endif + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; +#if defined(TIM_BDTR_BK2E) + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; +#endif /* TIM_BDTR_BK2E */ + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; +#if defined(TIM_CR2_OIS2N) + tmpcr2 &= ~TIM_CR2_OIS2N; +#endif /* TIM_CR2_OIS2N */ + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + +#if defined(TIM_CR2_OIS3) + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } +#endif /* TIM_CR2_OIS3 */ + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + +#if defined(TIM_CR2_OIS4) + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } +#endif /* TIM_CR2_OIS4 */ + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +#if defined(TIM_CCER_CC5E) +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} +#endif /* TIM_CCER_CC5E */ + +#if defined(TIM_CCER_CC6E) +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} +#endif /* TIM_CCER_CC6E */ + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; +#if defined(TIM_BDTR_BK2E) + htim->Break2Callback = HAL_TIMEx_Break2Callback; +#endif /* TIM_BDTR_BK2E */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c new file mode 100644 index 0000000..37e7c57 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c @@ -0,0 +1,2554 @@ +/** + ****************************************************************************** + * @file stm32f3xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Time OCRef clear configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f3xx_hal.h" + +/** @addtogroup STM32F3xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + +#if defined(TIM_CR2_MMS2) + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } +#endif /* TIM_CR2_MMS2 */ + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); +#if defined(TIM_BDTR_BKF) + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); +#endif /* TIM_BDTR_BKF */ + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); +#if defined(TIM_BDTR_BKF) + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); +#endif /* TIM_BDTR_BKF */ + +#if defined(TIM_BDTR_BK2E) + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + } +#endif /* TIM_BDTR_BK2E */ + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + @if STM32F301x8 + * For TIM1, the parameter can have the following values: + * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 + @elseif STM32F303xE + * For TIM1, the parameter is a combination of 2 fields (field1 | field2): + * + * field1 can have the following values: + * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 + * + * field2 can have the following values: + * @arg TIM_TIM1_ADC4_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1 + * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2 + * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3 + @elseif STM32F334x8 + * For TIM1, the parameter is a combination of 2 fields (field1 | field2): + * + * field1 can have the following values: + * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 + * + * field2 can have the following values: + * @arg TIM_TIM1_ADC2_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 + * @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 + * @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3 + @endif + @if STM32F303xE + * For TIM8, the parameter is a combination of 2 fields (field1 | field2): + * + * field1 can have the following values: + * @arg TIM_TIM8_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM8_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 + * @arg TIM_TIM8_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 + * @arg TIM_TIM8_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD2 + * + * field2 can have the following values: + * @arg TIM_TIM8_ADC3_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM8_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 + * @arg TIM_TIM8_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 + * @arg TIM_TIM8_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 + @endif + @if STM32F373xC + * For TIM14, the parameter can have the following values: + * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock + * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 + * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO + @else + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock + * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32 + * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO + @endif + @if STM32F303xE + * For TIM20, the parameter is a combination of 2 fields (field1 | field2): + * + * field1 can have the following values: + * @arg TIM_TIM20_ADC3_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM20_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 + * @arg TIM_TIM20_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 + * @arg TIM_TIM20_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD2 + * + * field2 can have the following values: + * @arg TIM_TIM20_ADC4_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) + * @arg TIM_TIM20_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1 + * @arg TIM_TIM20_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2 + * @arg TIM_TIM20_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3 + @endif + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + __HAL_LOCK(htim); + + /* Check parameters */ + assert_param(IS_TIM_REMAP(htim->Instance, Remap)); + + /* Set the Timer remapping configuration */ + WRITE_REG(htim->Instance->OR, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +#if defined(TIM_CCR5_CCR5) +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#endif /* TIM_CCR5_CCR5 */ + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +#if defined(TIM_BDTR_BK2E) +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +#endif /* TIM_BDTR_BK2E */ +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/BMS_Testbench/BMS_Software_V1/Makefile b/BMS_Testbench/BMS_Software_V1/Makefile new file mode 100644 index 0000000..4f9ac55 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Makefile @@ -0,0 +1,193 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.19.2] date: [Sat Apr 15 20:04:42 CEST 2023] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = ams-slave-23 + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +Core/Src/main.c \ +Core/Src/stm32f3xx_it.c \ +Core/Src/stm32f3xx_hal_msp.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c \ +Core/Src/system_stm32f3xx.c + +# ASM sources +ASM_SOURCES = \ +startup_stm32f302xc.s + + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m4 + +# fpu +FPU = -mfpu=fpv4-sp-d16 + +# float-abi +FLOAT-ABI = -mfloat-abi=hard + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DUSE_HAL_DRIVER \ +-DSTM32F302xC + + +# AS includes +AS_INCLUDES = + +# C includes +C_INCLUDES = \ +-ICore/Inc \ +-IDrivers/STM32F3xx_HAL_Driver/Inc \ +-IDrivers/STM32F3xx_HAL_Driver/Inc/Legacy \ +-IDrivers/CMSIS/Device/ST/STM32F3xx/Include \ +-IDrivers/CMSIS/Include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS += $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = STM32F302CCTx_FLASH.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/STM32-for-VSCode.config.yaml b/BMS_Testbench/BMS_Software_V1/STM32-for-VSCode.config.yaml new file mode 100644 index 0000000..898440f --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/STM32-for-VSCode.config.yaml @@ -0,0 +1,107 @@ +# Configuration file for the STM32 for VSCode extension +# Arrays can be inputted in two ways. One is: [entry_1, entry_2, ..., entry_final] +# or by adding an indented list below the variable name e.g.: +# VARIABLE: +# - entry_1 +# - entry_2 + +# The project name +target: ams-slave-23 +# Can be C or C++ +language: C + +optimization: Og + +# MCU settings +targetMCU: stm32f3x +cpu: cortex-m4 # type of cpu e.g. cortex-m4 +fpu: fpv4-sp-d16 # Defines how floating points are defined. Can be left empty. +floatAbi: -mfloat-abi=hard +ldscript: STM32F302CCTx_FLASH.ld # linker script + +# Compiler definitions. The -D prefix for the compiler will be automatically added. +cDefinitions: [] +cxxDefinitions: [] +asDefinitions: [] + +# Compiler definition files. you can add a single files or an array of files for different definitions. +# The file is expected to have a definition each new line. +# This allows to include for example a .definition file which can be ignored in git and can contain +# This can be convenient for passing along secrets at compile time, or generating a file for per device setup. +cDefinitionsFile: +cxxDefinitionsFile: +asDefinitionsFile: + +# Compiler flags +cFlags: + - -Wall + - -fdata-sections + - -ffunction-sections + +cxxFlags: [] +assemblyFlags: + - -Wall + - -fdata-sections + - -ffunction-sections + +linkerFlags: [] + +# libraries to be included. The -l prefix to the library will be automatically added. +libraries: + - c + - m + +# Library directories. Folders can be added here that contain custom libraries. +libraryDirectories: [] + +# Files or folders that will be excluded from compilation. +# Glob patterns (https://www.wikiwand.com/en/Glob_(programming)) can be used. +# Do mind that double stars are reserved in yaml +# these should be escaped with a: \ or the name should be in double quotes e.g. "**.test.**" +excludes: + - "**/Examples/**" + - "**/examples/**" + - "**/Example/**" + - "**/example/**" + - "**_template.*" + + +# Include directories (directories containing .h or .hpp files) +# If a CubeMX makefile is present it will automatically include the include directories from that makefile. +includeDirectories: + - Inc/** + - Core/Inc/** + - Core/Lib/** + - Src/** + - Core/Src/** + - Core/Lib/** + + +# Files that should be included in the compilation. +# If a CubeMX makefile is present it will automatically include the c and cpp/cxx files from that makefile. +# Glob patterns (https://www.wikiwand.com/en/Glob_(programming)) can be used. +# Do mind that double stars are reserved in yaml +# these should be escaped with a: \ or the name should be in double quotes e.g. "HARDWARE_DRIVER*.c" +sourceFiles: + - Src/** + - Core/Src/** + - Core/Lib/** + + +# When no makefile is present it will show a warning pop-up. +# However when compilation without the CubeMX Makefile is desired, this can be turned of. +suppressMakefileWarning: false + +# Custom makefile rules +# Here custom makefile rules can be added to the STM32Make.make file +# an example of how this can be used is commented out below. +customMakefileRules: +# - command: sayhello +# rule: echo "hello" +# dependsOn: $(BUILD_DIR)/$(TARGET).elf # can be left out + +# Additional flags which will be used when invoking the make command +makeFlags: +# - -O # use this option when the output of make is mixed up only works for make version 4.0 and upwards +# - --silent # use this option to silence the output of the build + \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/STM32F102xx.svd b/BMS_Testbench/BMS_Software_V1/STM32F102xx.svd new file mode 100644 index 0000000..9b0b41f --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/STM32F102xx.svd @@ -0,0 +1,9041 @@ + + + STM32F102xx + 1.1 + STM32F102xx + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD_IRQ + PVD through EXTI line detection + interrupt + 1 + + + + CR + CR + Power control register + (PWR_CR) + 0x0 + 0x20 + read-write + 0x00000000 + + + LPDS + Low Power Deep Sleep + 0 + 1 + + + PDDS + Power Down Deep Sleep + 1 + 1 + + + CWUF + Clear Wake-up Flag + 2 + 1 + + + CSBF + Clear STANDBY Flag + 3 + 1 + + + PVDE + Power Voltage Detector + Enable + 4 + 1 + + + PLS + PVD Level Selection + 5 + 3 + + + DBP + Disable Backup Domain write + protection + 8 + 1 + + + + + CSR + CSR + Power control register + (PWR_CR) + 0x4 + 0x20 + 0x00000000 + + + WUF + Wake-Up Flag + 0 + 1 + read-only + + + SBF + STANDBY Flag + 1 + 1 + read-only + + + PVDO + PVD Output + 2 + 1 + read-only + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC_IRQ + RCC global interrupt + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HSION + Internal High Speed clock + enable + 0 + 1 + read-write + + + HSIRDY + Internal High Speed clock ready + flag + 1 + 1 + read-only + + + HSITRIM + Internal High Speed clock + trimming + 3 + 5 + read-write + + + HSICAL + Internal High Speed clock + Calibration + 8 + 8 + read-only + + + HSEON + External High Speed clock + enable + 16 + 1 + read-write + + + HSERDY + External High Speed clock ready + flag + 17 + 1 + read-only + + + HSEBYP + External High Speed clock + Bypass + 18 + 1 + read-write + + + CSSON + Clock Security System + enable + 19 + 1 + read-write + + + PLLON + PLL enable + 24 + 1 + read-write + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + + + CFGR + CFGR + Clock configuration register + (RCC_CFGR) + 0x4 + 0x20 + 0x00000000 + + + SW + System clock Switch + 0 + 2 + read-write + + + SWS + System Clock Switch Status + 2 + 2 + read-only + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + PPRE1 + APB Low speed prescaler + (APB1) + 8 + 3 + read-write + + + PPRE2 + APB High speed prescaler + (APB2) + 11 + 3 + read-write + + + ADCPRE + ADC prescaler + 14 + 2 + read-write + + + PLLSRC + PLL entry clock source + 16 + 1 + read-write + + + PLLXTPRE + HSE divider for PLL entry + 17 + 1 + read-write + + + PLLMUL + PLL Multiplication Factor + 18 + 4 + read-write + + + MCO + Microcontroller clock + output + 24 + 3 + read-write + + + + + CIR + CIR + Clock interrupt register + (RCC_CIR) + 0x8 + 0x20 + 0x00000000 + + + LSIRDYF + LSI Ready Interrupt flag + 0 + 1 + read-only + + + LSERDYF + LSE Ready Interrupt flag + 1 + 1 + read-only + + + HSIRDYF + HSI Ready Interrupt flag + 2 + 1 + read-only + + + HSERDYF + HSE Ready Interrupt flag + 3 + 1 + read-only + + + PLLRDYF + PLL Ready Interrupt flag + 4 + 1 + read-only + + + CSSF + Clock Security System Interrupt + flag + 7 + 1 + read-only + + + LSIRDYIE + LSI Ready Interrupt Enable + 8 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable + 9 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable + 10 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable + 11 + 1 + read-write + + + PLLRDYIE + PLL Ready Interrupt Enable + 12 + 1 + read-write + + + LSIRDYC + LSI Ready Interrupt Clear + 16 + 1 + write-only + + + LSERDYC + LSE Ready Interrupt Clear + 17 + 1 + write-only + + + HSIRDYC + HSI Ready Interrupt Clear + 18 + 1 + write-only + + + HSERDYC + HSE Ready Interrupt Clear + 19 + 1 + write-only + + + PLLRDYC + PLL Ready Interrupt Clear + 20 + 1 + write-only + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + (RCC_APB2RSTR) + 0xC + 0x20 + read-write + 0x000000000 + + + AFIORST + Alternate function I/O + reset + 0 + 1 + + + IOPARST + IO port A reset + 2 + 1 + + + IOPBRST + IO port B reset + 3 + 1 + + + IOPCRST + IO port C reset + 4 + 1 + + + IOPDRST + IO port D reset + 5 + 1 + + + ADC1RST + ADC 1 interface reset + 9 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + (RCC_APB1RSTR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIM2RST + Timer 2 reset + 0 + 1 + + + TIM3RST + Timer 3 reset + 1 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + BKPRST + Backup interface reset + 27 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + + + AHBENR + AHBENR + AHB Peripheral Clock enable register + (RCC_AHBENR) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLITFEN + FLITF clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable register + (RCC_APB2ENR) + 0x18 + 0x20 + read-write + 0x00000000 + + + AFIOEN + Alternate function I/O clock + enable + 0 + 1 + + + IOPAEN + I/O port A clock enable + 2 + 1 + + + IOPBEN + I/O port B clock enable + 3 + 1 + + + IOPCEN + I/O port C clock enable + 4 + 1 + + + IOPDEN + I/O port D clock enable + 5 + 1 + + + ADC1EN + ADC 1 interface clock + enable + 9 + 1 + + + SPI1EN + SPI 1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable register + (RCC_APB1ENR) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM2EN + Timer 2 clock enable + 0 + 1 + + + TIM3EN + Timer 3 clock enable + 1 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + I2C1EN + I2C 1 clock enable + 21 + 1 + + + BKPEN + Backup interface clock + enable + 27 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + + + BDCR + BDCR + Backup domain control register + (RCC_BDCR) + 0x20 + 0x20 + 0x00000000 + + + LSEON + External Low Speed oscillator + enable + 0 + 1 + read-write + + + LSERDY + External Low Speed oscillator + ready + 1 + 1 + read-only + + + LSEBYP + External Low Speed oscillator + bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + + + CSR + CSR + Control/status register + (RCC_CSR) + 0x24 + 0x20 + 0x0C000000 + + + LSION + Internal low speed oscillator + enable + 0 + 1 + read-write + + + LSIRDY + Internal low speed oscillator + ready + 1 + 1 + read-only + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + + + GPIOA + General purpose I/O + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CRL + CRL + Port configuration register low + (GPIOn_CRL) + 0x0 + 0x20 + read-write + 0x44444444 + + + MODE0 + Port n.0 mode bits + 0 + 2 + + + CNF0 + Port n.0 configuration + bits + 2 + 2 + + + MODE1 + Port n.1 mode bits + 4 + 2 + + + CNF1 + Port n.1 configuration + bits + 6 + 2 + + + MODE2 + Port n.2 mode bits + 8 + 2 + + + CNF2 + Port n.2 configuration + bits + 10 + 2 + + + MODE3 + Port n.3 mode bits + 12 + 2 + + + CNF3 + Port n.3 configuration + bits + 14 + 2 + + + MODE4 + Port n.4 mode bits + 16 + 2 + + + CNF4 + Port n.4 configuration + bits + 18 + 2 + + + MODE5 + Port n.5 mode bits + 20 + 2 + + + CNF5 + Port n.5 configuration + bits + 22 + 2 + + + MODE6 + Port n.6 mode bits + 24 + 2 + + + CNF6 + Port n.6 configuration + bits + 26 + 2 + + + MODE7 + Port n.7 mode bits + 28 + 2 + + + CNF7 + Port n.7 configuration + bits + 30 + 2 + + + + + CRH + CRH + Port configuration register high + (GPIOn_CRL) + 0x4 + 0x20 + read-write + 0x44444444 + + + MODE8 + Port n.8 mode bits + 0 + 2 + + + CNF8 + Port n.8 configuration + bits + 2 + 2 + + + MODE9 + Port n.9 mode bits + 4 + 2 + + + CNF9 + Port n.9 configuration + bits + 6 + 2 + + + MODE10 + Port n.10 mode bits + 8 + 2 + + + CNF10 + Port n.10 configuration + bits + 10 + 2 + + + MODE11 + Port n.11 mode bits + 12 + 2 + + + CNF11 + Port n.11 configuration + bits + 14 + 2 + + + MODE12 + Port n.12 mode bits + 16 + 2 + + + CNF12 + Port n.12 configuration + bits + 18 + 2 + + + MODE13 + Port n.13 mode bits + 20 + 2 + + + CNF13 + Port n.13 configuration + bits + 22 + 2 + + + MODE14 + Port n.14 mode bits + 24 + 2 + + + CNF14 + Port n.14 configuration + bits + 26 + 2 + + + MODE15 + Port n.15 mode bits + 28 + 2 + + + CNF15 + Port n.15 configuration + bits + 30 + 2 + + + + + IDR + IDR + Port input data register + (GPIOn_IDR) + 0x8 + 0x20 + read-only + 0x00000000 + + + IDR0 + Port input data + 0 + 1 + + + IDR1 + Port input data + 1 + 1 + + + IDR2 + Port input data + 2 + 1 + + + IDR3 + Port input data + 3 + 1 + + + IDR4 + Port input data + 4 + 1 + + + IDR5 + Port input data + 5 + 1 + + + IDR6 + Port input data + 6 + 1 + + + IDR7 + Port input data + 7 + 1 + + + IDR8 + Port input data + 8 + 1 + + + IDR9 + Port input data + 9 + 1 + + + IDR10 + Port input data + 10 + 1 + + + IDR11 + Port input data + 11 + 1 + + + IDR12 + Port input data + 12 + 1 + + + IDR13 + Port input data + 13 + 1 + + + IDR14 + Port input data + 14 + 1 + + + IDR15 + Port input data + 15 + 1 + + + + + ODR + ODR + Port output data register + (GPIOn_ODR) + 0xC + 0x20 + read-write + 0x00000000 + + + ODR0 + Port output data + 0 + 1 + + + ODR1 + Port output data + 1 + 1 + + + ODR2 + Port output data + 2 + 1 + + + ODR3 + Port output data + 3 + 1 + + + ODR4 + Port output data + 4 + 1 + + + ODR5 + Port output data + 5 + 1 + + + ODR6 + Port output data + 6 + 1 + + + ODR7 + Port output data + 7 + 1 + + + ODR8 + Port output data + 8 + 1 + + + ODR9 + Port output data + 9 + 1 + + + ODR10 + Port output data + 10 + 1 + + + ODR11 + Port output data + 11 + 1 + + + ODR12 + Port output data + 12 + 1 + + + ODR13 + Port output data + 13 + 1 + + + ODR14 + Port output data + 14 + 1 + + + ODR15 + Port output data + 15 + 1 + + + + + BSRR + BSRR + Port bit set/reset register + (GPIOn_BSRR) + 0x10 + 0x20 + write-only + 0x00000000 + + + BS0 + Set bit 0 + 0 + 1 + + + BS1 + Set bit 1 + 1 + 1 + + + BS2 + Set bit 1 + 2 + 1 + + + BS3 + Set bit 3 + 3 + 1 + + + BS4 + Set bit 4 + 4 + 1 + + + BS5 + Set bit 5 + 5 + 1 + + + BS6 + Set bit 6 + 6 + 1 + + + BS7 + Set bit 7 + 7 + 1 + + + BS8 + Set bit 8 + 8 + 1 + + + BS9 + Set bit 9 + 9 + 1 + + + BS10 + Set bit 10 + 10 + 1 + + + BS11 + Set bit 11 + 11 + 1 + + + BS12 + Set bit 12 + 12 + 1 + + + BS13 + Set bit 13 + 13 + 1 + + + BS14 + Set bit 14 + 14 + 1 + + + BS15 + Set bit 15 + 15 + 1 + + + BR0 + Reset bit 0 + 16 + 1 + + + BR1 + Reset bit 1 + 17 + 1 + + + BR2 + Reset bit 2 + 18 + 1 + + + BR3 + Reset bit 3 + 19 + 1 + + + BR4 + Reset bit 4 + 20 + 1 + + + BR5 + Reset bit 5 + 21 + 1 + + + BR6 + Reset bit 6 + 22 + 1 + + + BR7 + Reset bit 7 + 23 + 1 + + + BR8 + Reset bit 8 + 24 + 1 + + + BR9 + Reset bit 9 + 25 + 1 + + + BR10 + Reset bit 10 + 26 + 1 + + + BR11 + Reset bit 11 + 27 + 1 + + + BR12 + Reset bit 12 + 28 + 1 + + + BR13 + Reset bit 13 + 29 + 1 + + + BR14 + Reset bit 14 + 30 + 1 + + + BR15 + Reset bit 15 + 31 + 1 + + + + + BRR + BRR + Port bit reset register + (GPIOn_BRR) + 0x14 + 0x20 + write-only + 0x00000000 + + + BR0 + Reset bit 0 + 0 + 1 + + + BR1 + Reset bit 1 + 1 + 1 + + + BR2 + Reset bit 1 + 2 + 1 + + + BR3 + Reset bit 3 + 3 + 1 + + + BR4 + Reset bit 4 + 4 + 1 + + + BR5 + Reset bit 5 + 5 + 1 + + + BR6 + Reset bit 6 + 6 + 1 + + + BR7 + Reset bit 7 + 7 + 1 + + + BR8 + Reset bit 8 + 8 + 1 + + + BR9 + Reset bit 9 + 9 + 1 + + + BR10 + Reset bit 10 + 10 + 1 + + + BR11 + Reset bit 11 + 11 + 1 + + + BR12 + Reset bit 12 + 12 + 1 + + + BR13 + Reset bit 13 + 13 + 1 + + + BR14 + Reset bit 14 + 14 + 1 + + + BR15 + Reset bit 15 + 15 + 1 + + + + + LCKR + LCKR + Port configuration lock + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LCK0 + Port A Lock bit 0 + 0 + 1 + + + LCK1 + Port A Lock bit 1 + 1 + 1 + + + LCK2 + Port A Lock bit 2 + 2 + 1 + + + LCK3 + Port A Lock bit 3 + 3 + 1 + + + LCK4 + Port A Lock bit 4 + 4 + 1 + + + LCK5 + Port A Lock bit 5 + 5 + 1 + + + LCK6 + Port A Lock bit 6 + 6 + 1 + + + LCK7 + Port A Lock bit 7 + 7 + 1 + + + LCK8 + Port A Lock bit 8 + 8 + 1 + + + LCK9 + Port A Lock bit 9 + 9 + 1 + + + LCK10 + Port A Lock bit 10 + 10 + 1 + + + LCK11 + Port A Lock bit 11 + 11 + 1 + + + LCK12 + Port A Lock bit 12 + 12 + 1 + + + LCK13 + Port A Lock bit 13 + 13 + 1 + + + LCK14 + Port A Lock bit 14 + 14 + 1 + + + LCK15 + Port A Lock bit 15 + 15 + 1 + + + LCKK + Lock key + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + AFIO + Alternate function I/O + AFIO + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVCR + EVCR + Event Control Register + (AFIO_EVCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + PIN + Pin selection + 0 + 4 + + + PORT + Port selection + 4 + 3 + + + EVOE + Event Output Enable + 7 + 1 + + + + + MAPR + MAPR + AF remap and debug I/O configuration + register (AFIO_MAPR) + 0x4 + 0x20 + 0x00000000 + + + SPI1_REMAP + SPI1 remapping + 0 + 1 + read-write + + + I2C1_REMAP + I2C1 remapping + 1 + 1 + read-write + + + USART1_REMAP + USART1 remapping + 2 + 1 + read-write + + + USART2_REMAP + USART2 remapping + 3 + 1 + read-write + + + USART3_REMAP + USART3 remapping + 4 + 2 + read-write + + + TIM1_REMAP + TIM1 remapping + 6 + 2 + read-write + + + TIM2_REMAP + TIM2 remapping + 8 + 2 + read-write + + + TIM3_REMAP + TIM3 remapping + 10 + 2 + read-write + + + TIM4_REMAP + TIM4 remapping + 12 + 1 + read-write + + + CAN_REMAP + CAN1 remapping + 13 + 2 + read-write + + + PD01_REMAP + Port D0/Port D1 mapping on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TIM5CH4_IREMAP + Set and cleared by + software + 16 + 1 + read-write + + + ADC1_ETRGINJ_REMAP + ADC 1 External trigger injected + conversion remapping + 17 + 1 + read-write + + + ADC1_ETRGREG_REMAP + ADC 1 external trigger regular + conversion remapping + 18 + 1 + read-write + + + ADC2_ETRGINJ_REMAP + ADC 2 external trigger injected + conversion remapping + 19 + 1 + read-write + + + ADC2_ETRGREG_REMAP + ADC 2 external trigger regular + conversion remapping + 20 + 1 + read-write + + + SWJ_CFG + Serial wire JTAG + configuration + 24 + 3 + write-only + + + + + EXTICR1 + EXTICR1 + External interrupt configuration register 1 + (AFIO_EXTICR1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXTI0 + EXTI0 configuration + 0 + 4 + + + EXTI1 + EXTI1 configuration + 4 + 4 + + + EXTI2 + EXTI2 configuration + 8 + 4 + + + EXTI3 + EXTI3 configuration + 12 + 4 + + + + + EXTICR2 + EXTICR2 + External interrupt configuration register 2 + (AFIO_EXTICR2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXTI4 + EXTI4 configuration + 0 + 4 + + + EXTI5 + EXTI5 configuration + 4 + 4 + + + EXTI6 + EXTI6 configuration + 8 + 4 + + + EXTI7 + EXTI7 configuration + 12 + 4 + + + + + EXTICR3 + EXTICR3 + External interrupt configuration register 3 + (AFIO_EXTICR3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI8 + EXTI8 configuration + 0 + 4 + + + EXTI9 + EXTI9 configuration + 4 + 4 + + + EXTI10 + EXTI10 configuration + 8 + 4 + + + EXTI11 + EXTI11 configuration + 12 + 4 + + + + + EXTICR4 + EXTICR4 + External interrupt configuration register 4 + (AFIO_EXTICR4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI12 + EXTI12 configuration + 0 + 4 + + + EXTI13 + EXTI13 configuration + 4 + 4 + + + EXTI14 + EXTI14 configuration + 8 + 4 + + + EXTI15 + EXTI15 configuration + 12 + 4 + + + + + MAPR2 + MAPR2 + AF remap and debug I/O configuration + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM9_REMAP + TIM9 remapping + 5 + 1 + + + TIM10_REMAP + TIM10 remapping + 6 + 1 + + + TIM11_REMAP + TIM11 remapping + 7 + 1 + + + TIM13_REMAP + TIM13 remapping + 8 + 1 + + + TIM14_REMAP + TIM14 remapping + 9 + 1 + + + FSMC_NADV + NADV connect/disconnect + 10 + 1 + + + + + + + EXTI + EXTI + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER_IRQ + Tamper interrupt + 2 + + + EXTI0_IRQ + EXTI Line0 interrupt + 6 + + + EXTI1_IRQ + EXTI Line1 interrupt + 7 + + + EXTI2_IRQ + EXTI Line2 interrupt + 8 + + + EXTI3_IRQ + EXTI Line3 interrupt + 9 + + + EXTI4_IRQ + EXTI Line4 interrupt + 10 + + + EXTI9_5_IRQ + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10_IRQ + EXTI Line[15:10] interrupts + 40 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Rising trigger event configuration of + line 18 + 18 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Falling trigger event configuration of + line 18 + 18 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER18 + Software Interrupt on line + 18 + 18 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + + + PR1 + Pending bit 1 + 1 + 1 + + + PR2 + Pending bit 2 + 2 + 1 + + + PR3 + Pending bit 3 + 3 + 1 + + + PR4 + Pending bit 4 + 4 + 1 + + + PR5 + Pending bit 5 + 5 + 1 + + + PR6 + Pending bit 6 + 6 + 1 + + + PR7 + Pending bit 7 + 7 + 1 + + + PR8 + Pending bit 8 + 8 + 1 + + + PR9 + Pending bit 9 + 9 + 1 + + + PR10 + Pending bit 10 + 10 + 1 + + + PR11 + Pending bit 11 + 11 + 1 + + + PR12 + Pending bit 12 + 12 + 1 + + + PR13 + Pending bit 13 + 13 + 1 + + + PR14 + Pending bit 14 + 14 + 1 + + + PR15 + Pending bit 15 + 15 + 1 + + + PR16 + Pending bit 16 + 16 + 1 + + + PR17 + Pending bit 17 + 17 + 1 + + + PR18 + Pending bit 18 + 18 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1_IRQ + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2_IRQ + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3_IRQ + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4_IRQ + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5_IRQ + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6_IRQ + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7_IRQ + DMA1 Channel7 global interrupt + 17 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer Complete + flag + 17 + 1 + + + HTIF5 + Channel 5 Half Transfer Complete + flag + 18 + 1 + + + TEIF5 + Channel 5 Transfer Error + flag + 19 + 1 + + + GIF6 + Channel 6 Global interrupt + flag + 20 + 1 + + + TCIF6 + Channel 6 Transfer Complete + flag + 21 + 1 + + + HTIF6 + Channel 6 Half Transfer Complete + flag + 22 + 1 + + + TEIF6 + Channel 6 Transfer Error + flag + 23 + 1 + + + GIF7 + Channel 7 Global interrupt + flag + 24 + 1 + + + TCIF7 + Channel 7 Transfer Complete + flag + 25 + 1 + + + HTIF7 + Channel 7 Half Transfer Complete + flag + 26 + 1 + + + TEIF7 + Channel 7 Transfer Error + flag + 27 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + (DMA_IFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CGIF4 + Channel 4 Global interrupt + clear + 12 + 1 + + + CGIF5 + Channel 5 Global interrupt + clear + 16 + 1 + + + CGIF6 + Channel 6 Global interrupt + clear + 20 + 1 + + + CGIF7 + Channel 7 Global interrupt + clear + 24 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CTCIF4 + Channel 4 Transfer Complete + clear + 13 + 1 + + + CTCIF5 + Channel 5 Transfer Complete + clear + 17 + 1 + + + CTCIF6 + Channel 6 Transfer Complete + clear + 21 + 1 + + + CTCIF7 + Channel 7 Transfer Complete + clear + 25 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CHTIF4 + Channel 4 Half Transfer + clear + 14 + 1 + + + CHTIF5 + Channel 5 Half Transfer + clear + 18 + 1 + + + CHTIF6 + Channel 6 Half Transfer + clear + 22 + 1 + + + CHTIF7 + Channel 7 Half Transfer + clear + 26 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CTEIF4 + Channel 4 Transfer Error + clear + 15 + 1 + + + CTEIF5 + Channel 5 Transfer Error + clear + 19 + 1 + + + CTEIF6 + Channel 6 Transfer Error + clear + 23 + 1 + + + CTEIF7 + Channel 7 Transfer Error + clear + 27 + 1 + + + + + CCR1 + CCR1 + DMA channel configuration register + (DMA_CCR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel configuration register + (DMA_CCR) + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel configuration register + (DMA_CCR) + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR4 + CCR4 + DMA channel configuration register + (DMA_CCR) + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR4 + CNDTR4 + DMA channel 4 number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR4 + CPAR4 + DMA channel 4 peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR4 + CMAR4 + DMA channel 4 memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR5 + CCR5 + DMA channel configuration register + (DMA_CCR) + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR5 + CNDTR5 + DMA channel 5 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR5 + CPAR5 + DMA channel 5 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR5 + CMAR5 + DMA channel 5 memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR6 + CCR6 + DMA channel configuration register + (DMA_CCR) + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR6 + CNDTR6 + DMA channel 6 number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR6 + CPAR6 + DMA channel 6 peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR6 + CMAR6 + DMA channel 6 memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR7 + CCR7 + DMA channel configuration register + (DMA_CCR) + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR7 + CNDTR7 + DMA channel 7 number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR7 + CPAR7 + DMA channel 7 peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR7 + CMAR7 + DMA channel 7 memory address + register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1_IRQ + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2_IRQ + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3_IRQ + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5_IRQ + DMA2 Channel4 and DMA2 Channel5 global + interrupt + 59 + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_IRQ + RTC global interrupt + 3 + + + RTCAlarm_IRQ + RTC Alarms through EXTI line + interrupt + 41 + + + + CRH + CRH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + SECIE + Second interrupt Enable + 0 + 1 + + + ALRIE + Alarm interrupt Enable + 1 + 1 + + + OWIE + Overflow interrupt Enable + 2 + 1 + + + + + CRL + CRL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + SECF + Second Flag + 0 + 1 + read-write + + + ALRF + Alarm Flag + 1 + 1 + read-write + + + OWF + Overflow Flag + 2 + 1 + read-write + + + RSF + Registers Synchronized + Flag + 3 + 1 + read-write + + + CNF + Configuration Flag + 4 + 1 + read-write + + + RTOFF + RTC operation OFF + 5 + 1 + read-only + + + + + PRLH + PRLH + RTC Prescaler Load Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + PRLH + RTC Prescaler Load Register + High + 0 + 4 + + + + + PRLL + PRLL + RTC Prescaler Load Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + PRLL + RTC Prescaler Divider Register + Low + 0 + 16 + + + + + DIVH + DIVH + RTC Prescaler Divider Register + High + 0x10 + 0x20 + read-only + 0x00000000 + + + DIVH + RTC prescaler divider register + high + 0 + 4 + + + + + DIVL + DIVL + RTC Prescaler Divider Register + Low + 0x14 + 0x20 + read-only + 0x8000 + + + DIVL + RTC prescaler divider register + Low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNTH + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNTL + RTC counter register Low + 0 + 16 + + + + + ALRH + ALRH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + ALRH + RTC alarm register high + 0 + 16 + + + + + ALRL + ALRL + RTC Alarm Register Low + 0x24 + 0x20 + write-only + 0xFFFF + + + ALRL + RTC alarm register low + 0 + 16 + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register (IWDG_KR) + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + + + PR + PR + Prescaler register (IWDG_PR) + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register (IWDG_RLR) + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register (IWDG_SR) + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG_IRQ + Window Watchdog interrupt + 0 + + + + CR + CR + Control register (WWDG_CR) + 0x0 + 0x20 + read-write + 0x0000007F + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + WDGA + Activation bit + 7 + 1 + + + + + CFR + CFR + Configuration register + (WWDG_CFR) + 0x4 + 0x20 + read-write + 0x0000007F + + + W + 7-bit window value + 0 + 7 + + + WDGTB + Timer Base + 7 + 2 + + + EWI + Early Wakeup Interrupt + 9 + 1 + + + + + SR + SR + Status register (WWDG_SR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EWI + Early Wakeup Interrupt + 0 + 1 + + + + + + + TIM2 + General purpose timer + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2_IRQ + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + 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Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 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3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + + + TIM3 + 0x40000400 + + TIM3_IRQ + TIM3 global interrupt + 29 + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C_EV_IRQ + I2C event interrupt + 31 + + + I2C_ER_IRQ + I2C errot interrupt + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + ALERT + SMBus alert + 13 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + ENARP + ARP enable + 4 + 1 + + + SMBTYPE + SMBus type + 3 + 1 + + + SMBUS + SMBus mode + 1 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDMODE + Addressing mode (slave + mode) + 15 + 1 + + + ADD10 + Interface address + 8 + 2 + + + ADD7 + Interface address + 1 + 7 + + + ADD0 + Interface address + 0 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADD2 + Interface address + 1 + 7 + + + ENDUAL + Dual addressing mode + enable + 0 + 1 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + SMBALERT + SMBus alert + 15 + 1 + read-write + + + TIMEOUT + Timeout or Tlow error + 14 + 1 + read-write + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADD10 + 10-bit header sent (Master + mode) + 3 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + SMBHOST + SMBus host header (Slave + mode) + 6 + 1 + + + SMBDEFAULT + SMBus device default address (Slave + mode) + 5 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI_IRQ + SPI global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + UDR + Underrun flag + 3 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1_IRQ + USART1 global interrupt + 37 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C0 + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2_IRQ + USART2 global interrupt + 38 + + + + ADC1 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_IRQ + ADC1 global interrupt + 18 + + + + SR + SR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CR1 + CR1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DUALMOD + Dual mode selection + 16 + 4 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CR2 + CR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + SWSTART + Start conversion of regular + channels + 22 + 1 + + + JSWSTART + Start conversion of injected + channels + 21 + 1 + + + EXTTRIG + External trigger conversion mode for + regular channels + 20 + 1 + + + EXTSEL + External event select for regular + group + 17 + 3 + + + JEXTTRIG + External trigger conversion mode for + injected channels + 15 + 1 + + + JEXTSEL + External event select for injected + group + 12 + 3 + + + ALIGN + Data alignment + 11 + 1 + + + DMA + Direct memory access mode + 8 + 1 + + + RSTCAL + Reset calibration + 3 + 1 + + + CAL + A/D calibration + 2 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D converter ON / OFF + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + JOFR1 + JOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR2 + JOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR3 + JOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR4 + JOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + HTR + HTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + LTR + LTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1 + 1st conversion in regular + sequence + 0 + 5 + + + + + JSQR + JSQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + JDR1 + JDR1 + injected data register x + 0x3C + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR2 + JDR2 + injected data register x + 0x40 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR3 + JDR3 + injected data register x + 0x44 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR4 + JDR4 + injected data register x + 0x48 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + DR + DR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA + Regular data + 0 + 16 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + FLASH + FLASH + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH_IRQ + Flash global interrupt + 4 + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000030 + + + LATENCY + Latency + 0 + 3 + read-write + + + HLFCYA + Flash half cycle access + enable + 3 + 1 + read-write + + + PRFTBE + Prefetch buffer enable + 4 + 1 + read-write + + + PRFTBS + Prefetch buffer status + 5 + 1 + read-only + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEY + FPEC key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRTERR + Write protection error + 4 + 1 + read-write + + + PGERR + Programming error + 2 + 1 + read-write + + + BSY + Busy + 0 + 1 + read-only + + + + + CR + CR + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + PG + Programming + 0 + 1 + + + PER + Page Erase + 1 + 1 + + + MER + Mass Erase + 2 + 1 + + + OPTPG + Option byte programming + 4 + 1 + + + OPTER + Option byte erase + 5 + 1 + + + STRT + Start + 6 + 1 + + + LOCK + Lock + 7 + 1 + + + OPTWRE + Option bytes write enable + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + + + AR + AR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash Address + 0 + 32 + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + OPTERR + Option byte error + 0 + 1 + + + RDPRT + Read protection + 1 + 1 + + + WDG_SW + WDG_SW + 2 + 1 + + + nRST_STOP + nRST_STOP + 3 + 1 + + + nRST_STDBY + nRST_STDBY + 4 + 1 + + + Data0 + Data0 + 10 + 8 + + + Data1 + Data1 + 18 + 8 + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + WRP + Write protect + 0 + 32 + + + + + + + DBG + Debug support + DBG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DBGMCU_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + DEV_ID + 0 + 12 + + + REV_ID + REV_ID + 16 + 16 + + + + + CR + CR + DBGMCU_CR + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + DBG_IWDG_STOP + DBG_IWDG_STOP + 8 + 1 + + + DBG_WWDG_STOP + DBG_WWDG_STOP + 9 + 1 + + + DBG_TIM2_STOP + DBG_TIM2_STOP + 11 + 1 + + + DBG_TIM3_STOP + DBG_TIM3_STOP + 12 + 1 + + + DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT + 15 + 1 + + + + + + + BKP + Backup registers + BKP + 0x40006C04 + + 0x0 + 0x400 + registers + + + + DR1 + DR1 + Backup data register (BKP_DR) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1 + Backup data + 0 + 16 + + + + + DR2 + DR2 + Backup data register (BKP_DR) + 0x4 + 0x20 + read-write + 0x00000000 + + + D2 + Backup data + 0 + 16 + + + + + DR3 + DR3 + Backup data register (BKP_DR) + 0x8 + 0x20 + read-write + 0x00000000 + + + D3 + Backup data + 0 + 16 + + + + + DR4 + DR4 + Backup data register (BKP_DR) + 0xC + 0x20 + read-write + 0x00000000 + + + D4 + Backup data + 0 + 16 + + + + + DR5 + DR5 + Backup data register (BKP_DR) + 0x10 + 0x20 + read-write + 0x00000000 + + + D5 + Backup data + 0 + 16 + + + + + DR6 + DR6 + Backup data register (BKP_DR) + 0x14 + 0x20 + read-write + 0x00000000 + + + D6 + Backup data + 0 + 16 + + + + + DR7 + DR7 + Backup data register (BKP_DR) + 0x18 + 0x20 + read-write + 0x00000000 + + + D7 + Backup data + 0 + 16 + + + + + DR8 + DR8 + Backup data register (BKP_DR) + 0x1C + 0x20 + read-write + 0x00000000 + + + D8 + Backup data + 0 + 16 + + + + + DR9 + DR9 + Backup data register (BKP_DR) + 0x20 + 0x20 + read-write + 0x00000000 + + + D9 + Backup data + 0 + 16 + + + + + DR10 + DR10 + Backup data register (BKP_DR) + 0x24 + 0x20 + read-write + 0x00000000 + + + D10 + Backup data + 0 + 16 + + + + + DR11 + DR11 + Backup data register (BKP_DR) + 0x3C + 0x20 + read-write + 0x00000000 + + + DR11 + Backup data + 0 + 16 + + + + + DR12 + DR12 + Backup data register (BKP_DR) + 0x40 + 0x20 + read-write + 0x00000000 + + + DR12 + Backup data + 0 + 16 + + + + + DR13 + DR13 + Backup data register (BKP_DR) + 0x44 + 0x20 + read-write + 0x00000000 + + + DR13 + Backup data + 0 + 16 + + + + + DR14 + DR14 + Backup data register (BKP_DR) + 0x48 + 0x20 + read-write + 0x00000000 + + + D14 + Backup data + 0 + 16 + + + + + DR15 + DR15 + Backup data register (BKP_DR) + 0x4C + 0x20 + read-write + 0x00000000 + + + D15 + Backup data + 0 + 16 + + + + + DR16 + DR16 + Backup data register (BKP_DR) + 0x50 + 0x20 + read-write + 0x00000000 + + + D16 + Backup data + 0 + 16 + + + + + DR17 + DR17 + Backup data register (BKP_DR) + 0x54 + 0x20 + read-write + 0x00000000 + + + D17 + Backup data + 0 + 16 + + + + + DR18 + DR18 + Backup data register (BKP_DR) + 0x58 + 0x20 + read-write + 0x00000000 + + + D18 + Backup data + 0 + 16 + + + + + DR19 + DR19 + Backup data register (BKP_DR) + 0x5C + 0x20 + read-write + 0x00000000 + + + D19 + Backup data + 0 + 16 + + + + + DR20 + DR20 + Backup data register (BKP_DR) + 0x60 + 0x20 + read-write + 0x00000000 + + + D20 + Backup data + 0 + 16 + + + + + DR21 + DR21 + Backup data register (BKP_DR) + 0x64 + 0x20 + read-write + 0x00000000 + + + D21 + Backup data + 0 + 16 + + + + + DR22 + DR22 + Backup data register (BKP_DR) + 0x68 + 0x20 + read-write + 0x00000000 + + + D22 + Backup data + 0 + 16 + + + + + DR23 + DR23 + Backup data register (BKP_DR) + 0x6C + 0x20 + read-write + 0x00000000 + + + D23 + Backup data + 0 + 16 + + + + + DR24 + DR24 + Backup data register (BKP_DR) + 0x70 + 0x20 + read-write + 0x00000000 + + + D24 + Backup data + 0 + 16 + + + + + DR25 + DR25 + Backup data register (BKP_DR) + 0x74 + 0x20 + read-write + 0x00000000 + + + D25 + Backup data + 0 + 16 + + + + + DR26 + DR26 + Backup data register (BKP_DR) + 0x78 + 0x20 + read-write + 0x00000000 + + + D26 + Backup data + 0 + 16 + + + + + DR27 + DR27 + Backup data register (BKP_DR) + 0x7C + 0x20 + read-write + 0x00000000 + + + D27 + Backup data + 0 + 16 + + + + + DR28 + DR28 + Backup data register (BKP_DR) + 0x80 + 0x20 + read-write + 0x00000000 + + + D28 + Backup data + 0 + 16 + + + + + DR29 + DR29 + Backup data register (BKP_DR) + 0x84 + 0x20 + read-write + 0x00000000 + + + D29 + Backup data + 0 + 16 + + + + + DR30 + DR30 + Backup data register (BKP_DR) + 0x88 + 0x20 + read-write + 0x00000000 + + + D30 + Backup data + 0 + 16 + + + + + DR31 + DR31 + Backup data register (BKP_DR) + 0x8C + 0x20 + read-write + 0x00000000 + + + D31 + Backup data + 0 + 16 + + + + + DR32 + DR32 + Backup data register (BKP_DR) + 0x90 + 0x20 + read-write + 0x00000000 + + + D32 + Backup data + 0 + 16 + + + + + DR33 + DR33 + Backup data register (BKP_DR) + 0x94 + 0x20 + read-write + 0x00000000 + + + D33 + Backup data + 0 + 16 + + + + + DR34 + DR34 + Backup data register (BKP_DR) + 0x98 + 0x20 + read-write + 0x00000000 + + + D34 + Backup data + 0 + 16 + + + + + DR35 + DR35 + Backup data register (BKP_DR) + 0x9C + 0x20 + read-write + 0x00000000 + + + D35 + Backup data + 0 + 16 + + + + + DR36 + DR36 + Backup data register (BKP_DR) + 0xA0 + 0x20 + read-write + 0x00000000 + + + D36 + Backup data + 0 + 16 + + + + + DR37 + DR37 + Backup data register (BKP_DR) + 0xA4 + 0x20 + read-write + 0x00000000 + + + D37 + Backup data + 0 + 16 + + + + + DR38 + DR38 + Backup data register (BKP_DR) + 0xA8 + 0x20 + read-write + 0x00000000 + + + D38 + Backup data + 0 + 16 + + + + + DR39 + DR39 + Backup data register (BKP_DR) + 0xAC + 0x20 + read-write + 0x00000000 + + + D39 + Backup data + 0 + 16 + + + + + DR40 + DR40 + Backup data register (BKP_DR) + 0xB0 + 0x20 + read-write + 0x00000000 + + + D40 + Backup data + 0 + 16 + + + + + DR41 + DR41 + Backup data register (BKP_DR) + 0xB4 + 0x20 + read-write + 0x00000000 + + + D41 + Backup data + 0 + 16 + + + + + DR42 + DR42 + Backup data register (BKP_DR) + 0xB8 + 0x20 + read-write + 0x00000000 + + + D42 + Backup data + 0 + 16 + + + + + RTCCR + RTCCR + RTC clock calibration register + (BKP_RTCCR) + 0x28 + 0x20 + read-write + 0x00000000 + + + CAL + Calibration value + 0 + 7 + + + CCO + Calibration Clock Output + 7 + 1 + + + ASOE + Alarm or second output + enable + 8 + 1 + + + ASOS + Alarm or second output + selection + 9 + 1 + + + + + CR + CR + Backup control register + (BKP_CR) + 0x2C + 0x20 + read-write + 0x00000000 + + + TPE + Tamper pin enable + 0 + 1 + + + TPAL + Tamper pin active level + 1 + 1 + + + + + CSR + CSR + BKP_CSR control/status register + (BKP_CSR) + 0x30 + 0x20 + 0x00000000 + + + CTE + Clear Tamper event + 0 + 1 + write-only + + + CTI + Clear Tamper Interrupt + 1 + 1 + write-only + + + TPIE + Tamper Pin interrupt + enable + 2 + 1 + read-write + + + TEF + Tamper Event Flag + 8 + 1 + read-only + + + TIF + Tamper Interrupt Flag + 9 + 1 + read-only + + + + + + NVIC Nested Vectored Interrupt Controller NVIC 0xE000E000 0x0 0x1001 registers 0x1001 0xFFFFF3FF reserved ICTR ICTR Interrupt Controller Type Register 0x4 0x20 read-only 0x00000000 INTLINESNUM Total number of interrupt lines in groups 0 4 STIR STIR Software Triggered Interrupt Register 0xF00 0x20 write-only 0x00000000 INTID interrupt to be triggered 0 9 ISER0 ISER0 Interrupt Set-Enable Register 0x100 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x104 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x180 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x184 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x200 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x204 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x280 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x284 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x300 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x304 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x400 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x404 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x408 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x40C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x410 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x414 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x418 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x41C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x420 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x424 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x428 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x42C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x430 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x434 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x438 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 + diff --git a/BMS_Testbench/BMS_Software_V1/STM32F302.svd b/BMS_Testbench/BMS_Software_V1/STM32F302.svd new file mode 100644 index 0000000..bf83bfd --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/STM32F302.svd @@ -0,0 +1,39943 @@ + + + STM32F302 + 1.7 + STM32F302 + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x28000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x24000000 + + + PUPDR15 + Port x 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Lok Key + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + Port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port x Reset bit y + 0 + 1 + + + BR1 + Port x Reset bit y + 1 + 1 + + + BR2 + Port x Reset bit y + 2 + 1 + + + BR3 + Port x Reset bit y + 3 + 1 + + + BR4 + Port x Reset bit y + 4 + 1 + + + BR5 + Port x Reset bit y + 5 + 1 + + + BR6 + Port x Reset bit y + 6 + 1 + + + BR7 + Port x Reset bit y + 7 + 1 + + + BR8 + Port x Reset bit y + 8 + 1 + + + BR9 + Port x Reset bit y + 9 + 1 + + + BR10 + Port x Reset bit y + 10 + 1 + + + BR11 + Port x Reset bit y + 11 + 1 + + + BR12 + Port x Reset bit y + 12 + 1 + + + BR13 + Port x Reset bit y + 13 + 1 + + + BR14 + Port x Reset bit y + 14 + 1 + + + BR15 + Port x Reset bit y + 15 + 1 + + + + + + + GPIOC + 0x48000800 + + + GPIOD + 0x48000C00 + + + GPIOE + 0x48001000 + + + GPIOF + 0x48001400 + + + GPIOG + 0x48001800 + + + GPIOH + 0x48001C00 + + + TSC + Touch sensing controller + TSC + 0x40024000 + + 0x0 + 0x400 + registers + + + EXTI2_TSC + EXTI Line2 and Touch sensing + interrupts + 8 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTPH + Charge transfer pulse high + 28 + 4 + + + CTPL + Charge transfer pulse low + 24 + 4 + + + SSD + Spread spectrum deviation + 17 + 7 + + + SSE + Spread spectrum enable + 16 + 1 + + + SSPSC + Spread spectrum prescaler + 15 + 1 + + + PGPSC + pulse generator prescaler + 12 + 3 + + + MCV + Max count value + 5 + 3 + + + IODEF + I/O Default mode + 4 + 1 + + + SYNCPOL + Synchronization pin + polarity + 3 + 1 + + + AM + Acquisition mode + 2 + 1 + + + START + Start a new acquisition + 1 + 1 + + + TSCE + Touch sensing controller + enable + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + MCEIE + Max count error interrupt + enable + 1 + 1 + + + EOAIE + End of acquisition interrupt + enable + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x8 + 0x20 + read-write + 0x00000000 + + + MCEIC + Max count error interrupt + clear + 1 + 1 + + + EOAIC + End of acquisition interrupt + clear + 0 + 1 + + + + + ISR + ISR + interrupt status register + 0xC + 0x20 + read-write + 0x00000000 + + + MCEF + Max count error flag + 1 + 1 + + + EOAF + End of acquisition flag + 0 + 1 + + + + + IOHCR + IOHCR + I/O hysteresis control + register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + G1_IO1 + G1_IO1 Schmitt trigger hysteresis + mode + 0 + 1 + + + G1_IO2 + G1_IO2 Schmitt trigger hysteresis + mode + 1 + 1 + + + G1_IO3 + G1_IO3 Schmitt trigger hysteresis + mode + 2 + 1 + + + G1_IO4 + G1_IO4 Schmitt trigger hysteresis + mode + 3 + 1 + + + G2_IO1 + G2_IO1 Schmitt trigger hysteresis + mode + 4 + 1 + + + G2_IO2 + G2_IO2 Schmitt trigger hysteresis + mode + 5 + 1 + + + G2_IO3 + G2_IO3 Schmitt trigger hysteresis + mode + 6 + 1 + + + G2_IO4 + G2_IO4 Schmitt trigger hysteresis + mode + 7 + 1 + + + G3_IO1 + G3_IO1 Schmitt trigger hysteresis + mode + 8 + 1 + + + G3_IO2 + G3_IO2 Schmitt trigger hysteresis + mode + 9 + 1 + + + G3_IO3 + G3_IO3 Schmitt trigger hysteresis + mode + 10 + 1 + + + G3_IO4 + G3_IO4 Schmitt trigger hysteresis + mode + 11 + 1 + + + G4_IO1 + G4_IO1 Schmitt trigger hysteresis + mode + 12 + 1 + + + G4_IO2 + G4_IO2 Schmitt trigger hysteresis + mode + 13 + 1 + + + G4_IO3 + G4_IO3 Schmitt trigger hysteresis + mode + 14 + 1 + + + G4_IO4 + G4_IO4 Schmitt trigger hysteresis + mode + 15 + 1 + + + G5_IO1 + G5_IO1 Schmitt trigger hysteresis + mode + 16 + 1 + + + G5_IO2 + G5_IO2 Schmitt trigger hysteresis + mode + 17 + 1 + + + G5_IO3 + G5_IO3 Schmitt trigger hysteresis + mode + 18 + 1 + + + G5_IO4 + G5_IO4 Schmitt trigger hysteresis + mode + 19 + 1 + + + G6_IO1 + G6_IO1 Schmitt trigger hysteresis + mode + 20 + 1 + + + G6_IO2 + G6_IO2 Schmitt trigger hysteresis + mode + 21 + 1 + + + G6_IO3 + G6_IO3 Schmitt trigger hysteresis + mode + 22 + 1 + + + G6_IO4 + G6_IO4 Schmitt trigger hysteresis + mode + 23 + 1 + + + G7_IO1 + G7_IO1 Schmitt trigger hysteresis + mode + 24 + 1 + + + G7_IO2 + G7_IO2 Schmitt trigger hysteresis + mode + 25 + 1 + + + G7_IO3 + G7_IO3 Schmitt trigger hysteresis + mode + 26 + 1 + + + G7_IO4 + G7_IO4 Schmitt trigger hysteresis + mode + 27 + 1 + + + G8_IO1 + G8_IO1 Schmitt trigger hysteresis + mode + 28 + 1 + + + G8_IO2 + G8_IO2 Schmitt trigger hysteresis + mode + 29 + 1 + + + G8_IO3 + G8_IO3 Schmitt trigger hysteresis + mode + 30 + 1 + + + G8_IO4 + G8_IO4 Schmitt trigger hysteresis + mode + 31 + 1 + + + + + IOASCR + IOASCR + I/O analog switch control + register + 0x18 + 0x20 + read-write + 0x00000000 + + + G1_IO1 + G1_IO1 analog switch + enable + 0 + 1 + + + G1_IO2 + G1_IO2 analog switch + enable + 1 + 1 + + + G1_IO3 + G1_IO3 analog switch + enable + 2 + 1 + + + G1_IO4 + G1_IO4 analog switch + enable + 3 + 1 + + + G2_IO1 + G2_IO1 analog switch + enable + 4 + 1 + + + G2_IO2 + G2_IO2 analog switch + enable + 5 + 1 + + + G2_IO3 + G2_IO3 analog switch + enable + 6 + 1 + + + G2_IO4 + G2_IO4 analog switch + enable + 7 + 1 + + + G3_IO1 + G3_IO1 analog switch + enable + 8 + 1 + + + G3_IO2 + G3_IO2 analog switch + enable + 9 + 1 + + + G3_IO3 + G3_IO3 analog switch + enable + 10 + 1 + + + G3_IO4 + G3_IO4 analog switch + enable + 11 + 1 + + + G4_IO1 + G4_IO1 analog switch + enable + 12 + 1 + + + G4_IO2 + G4_IO2 analog switch + enable + 13 + 1 + + + G4_IO3 + G4_IO3 analog switch + enable + 14 + 1 + + + G4_IO4 + G4_IO4 analog switch + enable + 15 + 1 + + + G5_IO1 + G5_IO1 analog switch + enable + 16 + 1 + + + G5_IO2 + G5_IO2 analog switch + enable + 17 + 1 + + + G5_IO3 + G5_IO3 analog switch + enable + 18 + 1 + + + G5_IO4 + G5_IO4 analog switch + enable + 19 + 1 + + + G6_IO1 + G6_IO1 analog switch + enable + 20 + 1 + + + G6_IO2 + G6_IO2 analog switch + enable + 21 + 1 + + + G6_IO3 + G6_IO3 analog switch + enable + 22 + 1 + + + G6_IO4 + G6_IO4 analog switch + enable + 23 + 1 + + + G7_IO1 + G7_IO1 analog switch + enable + 24 + 1 + + + G7_IO2 + G7_IO2 analog switch + enable + 25 + 1 + + + G7_IO3 + G7_IO3 analog switch + enable + 26 + 1 + + + G7_IO4 + G7_IO4 analog switch + enable + 27 + 1 + + + G8_IO1 + G8_IO1 analog switch + enable + 28 + 1 + + + G8_IO2 + G8_IO2 analog switch + enable + 29 + 1 + + + G8_IO3 + G8_IO3 analog switch + enable + 30 + 1 + + + G8_IO4 + G8_IO4 analog switch + enable + 31 + 1 + + + + + IOSCR + IOSCR + I/O sampling control register + 0x20 + 0x20 + read-write + 0x00000000 + + + G1_IO1 + G1_IO1 sampling mode + 0 + 1 + + + G1_IO2 + G1_IO2 sampling mode + 1 + 1 + + + G1_IO3 + G1_IO3 sampling mode + 2 + 1 + + + G1_IO4 + G1_IO4 sampling mode + 3 + 1 + + + G2_IO1 + G2_IO1 sampling mode + 4 + 1 + + + G2_IO2 + G2_IO2 sampling mode + 5 + 1 + + + G2_IO3 + G2_IO3 sampling mode + 6 + 1 + + + G2_IO4 + G2_IO4 sampling mode + 7 + 1 + + + G3_IO1 + G3_IO1 sampling mode + 8 + 1 + + + G3_IO2 + G3_IO2 sampling mode + 9 + 1 + + + G3_IO3 + G3_IO3 sampling mode + 10 + 1 + + + G3_IO4 + G3_IO4 sampling mode + 11 + 1 + + + G4_IO1 + G4_IO1 sampling mode + 12 + 1 + + + G4_IO2 + G4_IO2 sampling mode + 13 + 1 + + + G4_IO3 + G4_IO3 sampling mode + 14 + 1 + + + G4_IO4 + G4_IO4 sampling mode + 15 + 1 + + + G5_IO1 + G5_IO1 sampling mode + 16 + 1 + + + G5_IO2 + G5_IO2 sampling mode + 17 + 1 + + + G5_IO3 + G5_IO3 sampling mode + 18 + 1 + + + G5_IO4 + G5_IO4 sampling mode + 19 + 1 + + + G6_IO1 + G6_IO1 sampling mode + 20 + 1 + + + G6_IO2 + G6_IO2 sampling mode + 21 + 1 + + + G6_IO3 + G6_IO3 sampling mode + 22 + 1 + + + G6_IO4 + G6_IO4 sampling mode + 23 + 1 + + + G7_IO1 + G7_IO1 sampling mode + 24 + 1 + + + G7_IO2 + G7_IO2 sampling mode + 25 + 1 + + + G7_IO3 + G7_IO3 sampling mode + 26 + 1 + + + G7_IO4 + G7_IO4 sampling mode + 27 + 1 + + + G8_IO1 + G8_IO1 sampling mode + 28 + 1 + + + G8_IO2 + G8_IO2 sampling mode + 29 + 1 + + + G8_IO3 + G8_IO3 sampling mode + 30 + 1 + + + G8_IO4 + G8_IO4 sampling mode + 31 + 1 + + + + + IOCCR + IOCCR + I/O channel control register + 0x28 + 0x20 + read-write + 0x00000000 + + + G1_IO1 + G1_IO1 channel mode + 0 + 1 + + + G1_IO2 + G1_IO2 channel mode + 1 + 1 + + + G1_IO3 + G1_IO3 channel mode + 2 + 1 + + + G1_IO4 + G1_IO4 channel mode + 3 + 1 + + + G2_IO1 + G2_IO1 channel mode + 4 + 1 + + + G2_IO2 + G2_IO2 channel mode + 5 + 1 + + + G2_IO3 + G2_IO3 channel mode + 6 + 1 + + + G2_IO4 + G2_IO4 channel mode + 7 + 1 + + + G3_IO1 + G3_IO1 channel mode + 8 + 1 + + + G3_IO2 + G3_IO2 channel mode + 9 + 1 + + + G3_IO3 + G3_IO3 channel mode + 10 + 1 + + + G3_IO4 + G3_IO4 channel mode + 11 + 1 + + + G4_IO1 + G4_IO1 channel mode + 12 + 1 + + + G4_IO2 + G4_IO2 channel mode + 13 + 1 + + + G4_IO3 + G4_IO3 channel mode + 14 + 1 + + + G4_IO4 + G4_IO4 channel mode + 15 + 1 + + + G5_IO1 + G5_IO1 channel mode + 16 + 1 + + + G5_IO2 + G5_IO2 channel mode + 17 + 1 + + + G5_IO3 + G5_IO3 channel mode + 18 + 1 + + + G5_IO4 + G5_IO4 channel mode + 19 + 1 + + + G6_IO1 + G6_IO1 channel mode + 20 + 1 + + + G6_IO2 + G6_IO2 channel mode + 21 + 1 + + + G6_IO3 + G6_IO3 channel mode + 22 + 1 + + + G6_IO4 + G6_IO4 channel mode + 23 + 1 + + + G7_IO1 + G7_IO1 channel mode + 24 + 1 + + + G7_IO2 + G7_IO2 channel mode + 25 + 1 + + + G7_IO3 + G7_IO3 channel mode + 26 + 1 + + + G7_IO4 + G7_IO4 channel mode + 27 + 1 + + + G8_IO1 + G8_IO1 channel mode + 28 + 1 + + + G8_IO2 + G8_IO2 channel mode + 29 + 1 + + + G8_IO3 + G8_IO3 channel mode + 30 + 1 + + + G8_IO4 + G8_IO4 channel mode + 31 + 1 + + + + + IOGCSR + IOGCSR + I/O group control status + register + 0x30 + 0x20 + 0x00000000 + + + G8S + Analog I/O group x status + 23 + 1 + read-write + + + G7S + Analog I/O group x status + 22 + 1 + read-write + + + G6S + Analog I/O group x status + 21 + 1 + read-only + + + G5S + Analog I/O group x status + 20 + 1 + read-only + + + G4S + Analog I/O group x status + 19 + 1 + read-only + + + G3S + Analog I/O group x status + 18 + 1 + read-only + + + G2S + Analog I/O group x status + 17 + 1 + read-only + + + G1S + Analog I/O group x status + 16 + 1 + read-only + + + G8E + Analog I/O group x enable + 7 + 1 + read-write + + + G7E + Analog I/O group x enable + 6 + 1 + read-write + + + G6E + Analog I/O group x enable + 5 + 1 + read-write + + + G5E + Analog I/O group x enable + 4 + 1 + read-write + + + G4E + Analog I/O group x enable + 3 + 1 + read-write + + + G3E + Analog I/O group x enable + 2 + 1 + read-write + + + G2E + Analog I/O group x enable + 1 + 1 + read-write + + + G1E + Analog I/O group x enable + 0 + 1 + read-write + + + + + IOG1CR + IOG1CR + I/O group x counter register + 0x34 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG2CR + IOG2CR + I/O group x counter register + 0x38 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG3CR + IOG3CR + I/O group x counter register + 0x3C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG4CR + IOG4CR + I/O group x counter register + 0x40 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG5CR + IOG5CR + I/O group x counter register + 0x44 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG6CR + IOG6CR + I/O group x counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG7CR + IOG7CR + I/O group x counter register + 0x4C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + IOG8CR + IOG8CR + I/O group x counter register + 0x50 + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 14 + + + + + + + CRC + cyclic redundancy check calculation + unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register + bits + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RESET + reset bit + 0 + 1 + + + POLYSIZE + Polynomial size + 3 + 2 + + + REV_IN + Reverse input data + 5 + 2 + + + REV_OUT + Reverse output data + 7 + 1 + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + INIT + Programmable initial CRC + value + 0 + 32 + + + + + POL + POL + CRC polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + Flash + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000030 + + + LATENCY + LATENCY + 0 + 3 + read-write + + + PRFTBE + PRFTBE + 4 + 1 + read-write + + + PRFTBS + PRFTBS + 5 + 1 + read-only + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + FKEYR + Flash Key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Flash status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRT + Write protection error + 4 + 1 + read-write + + + PGERR + Programming error + 2 + 1 + read-write + + + BSY + Busy + 0 + 1 + read-only + + + + + CR + CR + Flash control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FORCE_OPTLOAD + Force option byte loading + 13 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + OPTWRE + Option bytes write enable + 9 + 1 + + + LOCK + Lock + 7 + 1 + + + STRT + Start + 6 + 1 + + + OPTER + Option byte erase + 5 + 1 + + + OPTPG + Option byte programming + 4 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + AR + AR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash address + 0 + 32 + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0xFFFFFF02 + + + OPTERR + Option byte error + 0 + 1 + + + LEVEL1_PROT + Level 1 protection status + 1 + 1 + + + LEVEL2_PROT + Level 2 protection status + 2 + 1 + + + WDG_SW + WDG_SW + 8 + 1 + + + nRST_STOP + nRST_STOP + 9 + 1 + + + nRST_STDBY + nRST_STDBY + 10 + 1 + + + BOOT1 + BOOT1 + 12 + 1 + + + VDDA_MONITOR + VDDA_MONITOR + 13 + 1 + + + SRAM_PARITY_CHECK + SRAM_PARITY_CHECK + 14 + 1 + + + Data0 + Data0 + 16 + 8 + + + Data1 + Data1 + 24 + 8 + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + WRP + Write protect + 0 + 32 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HSION + Internal High Speed clock + enable + 0 + 1 + read-write + + + HSIRDY + Internal High Speed clock ready + flag + 1 + 1 + read-only + + + HSITRIM + Internal High Speed clock + trimming + 3 + 5 + read-write + + + HSICAL + Internal High Speed clock + Calibration + 8 + 8 + read-only + + + HSEON + External High Speed clock + enable + 16 + 1 + read-write + + + HSERDY + External High Speed clock ready + flag + 17 + 1 + read-only + + + HSEBYP + External High Speed clock + Bypass + 18 + 1 + read-write + + + CSSON + Clock Security System + enable + 19 + 1 + read-write + + + PLLON + PLL enable + 24 + 1 + read-write + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + + + CFGR + CFGR + Clock configuration register + (RCC_CFGR) + 0x4 + 0x20 + 0x00000000 + + + SW + System clock Switch + 0 + 2 + read-write + + + SWS + System Clock Switch Status + 2 + 2 + read-only + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + PPRE1 + APB Low speed prescaler + (APB1) + 8 + 3 + read-write + + + PPRE2 + APB high speed prescaler + (APB2) + 11 + 3 + read-write + + + PLLSRC + PLL entry clock source + 15 + 2 + read-write + + + PLLXTPRE + HSE divider for PLL entry + 17 + 1 + read-write + + + PLLMUL + PLL Multiplication Factor + 18 + 4 + read-write + + + USBPRES + USB prescaler + 22 + 1 + read-write + + + MCO + Microcontroller clock + output + 24 + 3 + read-write + + + MCOF + Microcontroller Clock Output + Flag + 28 + 1 + read-only + + + I2SSRC + I2S external clock source + selection + 23 + 1 + read-write + + + + + CIR + CIR + Clock interrupt register + (RCC_CIR) + 0x8 + 0x20 + 0x00000000 + + + LSIRDYF + LSI Ready Interrupt flag + 0 + 1 + read-only + + + LSERDYF + LSE Ready Interrupt flag + 1 + 1 + read-only + + + HSIRDYF + HSI Ready Interrupt flag + 2 + 1 + read-only + + + HSERDYF + HSE Ready Interrupt flag + 3 + 1 + read-only + + + PLLRDYF + PLL Ready Interrupt flag + 4 + 1 + read-only + + + CSSF + Clock Security System Interrupt + flag + 7 + 1 + read-only + + + LSIRDYIE + LSI Ready Interrupt Enable + 8 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable + 9 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable + 10 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable + 11 + 1 + read-write + + + PLLRDYIE + PLL Ready Interrupt Enable + 12 + 1 + read-write + + + LSIRDYC + LSI Ready Interrupt Clear + 16 + 1 + write-only + + + LSERDYC + LSE Ready Interrupt Clear + 17 + 1 + write-only + + + HSIRDYC + HSI Ready Interrupt Clear + 18 + 1 + write-only + + + HSERDYC + HSE Ready Interrupt Clear + 19 + 1 + write-only + + + PLLRDYC + PLL Ready Interrupt Clear + 20 + 1 + write-only + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + (RCC_APB2RSTR) + 0xC + 0x20 + read-write + 0x00000000 + + + SYSCFGRST + SYSCFG and COMP reset + 0 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + TIM8RST + TIM8 timer reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TIM15RST + TIM15 timer reset + 16 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + (RCC_APB1RSTR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIM2RST + Timer 2 reset + 0 + 1 + + + TIM3RST + Timer 3 reset + 1 + 1 + + + TIM4RST + Timer 14 reset + 2 + 1 + + + TIM6RST + Timer 6 reset + 4 + 1 + + + TIM7RST + Timer 7 reset + 5 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBRST + USB reset + 23 + 1 + + + CANRST + CAN reset + 25 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DACRST + DAC interface reset + 29 + 1 + + + + + AHBENR + AHBENR + AHB Peripheral Clock enable register + (RCC_AHBENR) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMAEN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLITFEN + FLITF clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + IOPAEN + I/O port A clock enable + 17 + 1 + + + IOPBEN + I/O port B clock enable + 18 + 1 + + + IOPCEN + I/O port C clock enable + 19 + 1 + + + IOPDEN + I/O port D clock enable + 20 + 1 + + + IOPEEN + I/O port E clock enable + 21 + 1 + + + IOPFEN + I/O port F clock enable + 22 + 1 + + + TSCEN + Touch sensing controller clock + enable + 24 + 1 + + + ADC12EN + ADC1 and ADC2 clock enable + 28 + 1 + + + ADC34EN + ADC3 and ADC4 clock enable + 29 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable register + (RCC_APB2ENR) + 0x18 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG clock enable + 0 + 1 + + + TIM1EN + TIM1 Timer clock enable + 11 + 1 + + + SPI1EN + SPI 1 clock enable + 12 + 1 + + + TIM8EN + TIM8 Timer clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TIM15EN + TIM15 timer clock enable + 16 + 1 + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + TIM17EN + TIM17 timer clock enable + 18 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable register + (RCC_APB1ENR) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM2EN + Timer 2 clock enable + 0 + 1 + + + TIM3EN + Timer 3 clock enable + 1 + 1 + + + TIM4EN + Timer 4 clock enable + 2 + 1 + + + TIM6EN + Timer 6 clock enable + 4 + 1 + + + TIM7EN + Timer 7 clock enable + 5 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + SPI2EN + SPI 2 clock enable + 14 + 1 + + + SPI3EN + SPI 3 clock enable + 15 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + I2C1EN + I2C 1 clock enable + 21 + 1 + + + I2C2EN + I2C 2 clock enable + 22 + 1 + + + USBEN + USB clock enable + 23 + 1 + + + CANEN + CAN clock enable + 25 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DACEN + DAC interface clock enable + 29 + 1 + + + + + BDCR + BDCR + Backup domain control register + (RCC_BDCR) + 0x20 + 0x20 + 0x00000000 + + + LSEON + External Low Speed oscillator + enable + 0 + 1 + read-write + + + LSERDY + External Low Speed oscillator + ready + 1 + 1 + read-only + + + LSEBYP + External Low Speed oscillator + bypass + 2 + 1 + read-write + + + LSEDRV + LSE oscillator drive + capability + 3 + 2 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + + + CSR + CSR + Control/status register + (RCC_CSR) + 0x24 + 0x20 + 0x0C000000 + + + LSION + Internal low speed oscillator + enable + 0 + 1 + read-write + + + LSIRDY + Internal low speed oscillator + ready + 1 + 1 + read-only + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + IOPARST + I/O port A reset + 17 + 1 + + + IOPBRST + I/O port B reset + 18 + 1 + + + IOPCRST + I/O port C reset + 19 + 1 + + + IOPDRST + I/O port D reset + 20 + 1 + + + IOPERST + I/O port E reset + 21 + 1 + + + IOPFRST + I/O port F reset + 22 + 1 + + + TSCRST + Touch sensing controller + reset + 24 + 1 + + + ADC12RST + ADC1 and ADC2 reset + 28 + 1 + + + ADC34RST + ADC3 and ADC4 reset + 29 + 1 + + + + + CFGR2 + CFGR2 + Clock configuration register 2 + 0x2C + 0x20 + read-write + 0x00000000 + + + PREDIV + PREDIV division factor + 0 + 4 + + + ADC12PRES + ADC1 and ADC2 prescaler + 4 + 5 + + + ADC34PRES + ADC3 and ADC4 prescaler + 9 + 5 + + + + + CFGR3 + CFGR3 + Clock configuration register 3 + 0x30 + 0x20 + read-write + 0x00000000 + + + USART1SW + USART1 clock source + selection + 0 + 2 + + + I2C1SW + I2C1 clock source + selection + 4 + 1 + + + I2C2SW + I2C2 clock source + selection + 5 + 1 + + + USART2SW + USART2 clock source + selection + 16 + 2 + + + USART3SW + USART3 clock source + selection + 18 + 2 + + + TIM1SW + Timer1 clock source + selection + 8 + 1 + + + TIM8SW + Timer8 clock source + selection + 9 + 1 + + + UART4SW + UART4 clock source + selection + 20 + 2 + + + UART5SW + UART5 clock source + selection + 22 + 2 + + + + + + + DMA1 + DMA controller 1 + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 channel 1 interrupt + 11 + + + DMA1_CH2 + DMA1 channel 2 interrupt + 12 + + + DMA1_CH3 + DMA1 channel 3 interrupt + 13 + + + DMA1_CH4 + DMA1 channel 4 interrupt + 14 + + + DMA1_CH5 + DMA1 channel 5 interrupt + 15 + + + DMA1_CH6 + DMA1 channel 6 interrupt + 16 + + + DMA1_CH7 + DMA1 channel 7interrupt + 17 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer Complete + flag + 17 + 1 + + + HTIF5 + Channel 5 Half Transfer Complete + flag + 18 + 1 + + + TEIF5 + Channel 5 Transfer Error + flag + 19 + 1 + + + GIF6 + Channel 6 Global interrupt + flag + 20 + 1 + + + TCIF6 + Channel 6 Transfer Complete + flag + 21 + 1 + + + HTIF6 + Channel 6 Half Transfer Complete + flag + 22 + 1 + + + TEIF6 + Channel 6 Transfer Error + flag + 23 + 1 + + + GIF7 + Channel 7 Global interrupt + flag + 24 + 1 + + + TCIF7 + Channel 7 Transfer Complete + flag + 25 + 1 + + + HTIF7 + Channel 7 Half Transfer Complete + flag + 26 + 1 + + + TEIF7 + Channel 7 Transfer Error + flag + 27 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + (DMA_IFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CGIF4 + Channel 4 Global interrupt + clear + 12 + 1 + + + CTCIF4 + Channel 4 Transfer Complete + clear + 13 + 1 + + + CHTIF4 + Channel 4 Half Transfer + clear + 14 + 1 + + + CTEIF4 + Channel 4 Transfer Error + clear + 15 + 1 + + + CGIF5 + Channel 5 Global interrupt + clear + 16 + 1 + + + CTCIF5 + Channel 5 Transfer Complete + clear + 17 + 1 + + + CHTIF5 + Channel 5 Half Transfer + clear + 18 + 1 + + + CTEIF5 + Channel 5 Transfer Error + clear + 19 + 1 + + + CGIF6 + Channel 6 Global interrupt + clear + 20 + 1 + + + CTCIF6 + Channel 6 Transfer Complete + clear + 21 + 1 + + + CHTIF6 + Channel 6 Half Transfer + clear + 22 + 1 + + + CTEIF6 + Channel 6 Transfer Error + clear + 23 + 1 + + + CGIF7 + Channel 7 Global interrupt + clear + 24 + 1 + + + CTCIF7 + Channel 7 Transfer Complete + clear + 25 + 1 + + + CHTIF7 + Channel 7 Half Transfer + clear + 26 + 1 + + + CTEIF7 + Channel 7 Transfer Error + clear + 27 + 1 + + + + + CCR1 + CCR1 + DMA channel configuration register + (DMA_CCR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel configuration register + (DMA_CCR) + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel configuration register + (DMA_CCR) + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR4 + CCR4 + DMA channel configuration register + (DMA_CCR) + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR4 + CNDTR4 + DMA channel 4 number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR4 + CPAR4 + DMA channel 4 peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR4 + CMAR4 + DMA channel 4 memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR5 + CCR5 + DMA channel configuration register + (DMA_CCR) + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR5 + CNDTR5 + DMA channel 5 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR5 + CPAR5 + DMA channel 5 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR5 + CMAR5 + DMA channel 5 memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR6 + CCR6 + DMA channel configuration register + (DMA_CCR) + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR6 + CNDTR6 + DMA channel 6 number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR6 + CPAR6 + DMA channel 6 peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR6 + CMAR6 + DMA channel 6 memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR7 + CCR7 + DMA channel configuration register + (DMA_CCR) + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + CNDTR7 + CNDTR7 + DMA channel 7 number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR7 + CPAR7 + DMA channel 7 peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR7 + CMAR7 + DMA channel 7 memory address + register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + DMA2 + 0x40020400 + + DMA2_CH1 + DMA2 channel1 global interrupt + 56 + + + DMA2_CH2 + DMA2 channel2 global interrupt + 57 + + + DMA2_CH3 + DMA2 channel3 global interrupt + 58 + + + DMA2_CH4 + DMA2 channel4 global interrupt + 59 + + + DMA2_CH5 + DMA2 channel5 global interrupt + 60 + + + + TIM2 + General purpose timer + TIMs + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + TS + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + ETF + External trigger filter + 8 + 4 + + + ETPS + External trigger prescaler + 12 + 2 + + + ECE + External clock enable + 14 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + SMS_3 + Slave mode selection bit3 + 16 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2M + Output compare 2 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read-write + + + SETUP + Setup transaction + completed + 11 + 1 + read-only + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + read-write + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + read-write + + + CTR_RX + Correct transfer for + reception + 15 + 1 + read-write + + + + + USB_EP1R + USB_EP1R + endpoint 1 register + 0x4 + 0x20 + 0x00000000 + + + EA + Endpoint address + 0 + 4 + read-write + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + read-write + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + read-write + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + read-write + + + EP_KIND + Endpoint kind + 8 + 1 + read-write + + + EP_TYPE + Endpoint type + 9 + 2 + read-write + + + SETUP + Setup transaction + completed + 11 + 1 + read-only + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + read-write + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + read-write + + + CTR_RX + Correct transfer for + reception + 15 + 1 + read-write + + + + + USB_EP2R + USB_EP2R + endpoint 2 register + 0x8 + 0x20 + 0x00000000 + + + EA + Endpoint address + 0 + 4 + read-write + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + read-write + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + read-write + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + read-write + + + EP_KIND + Endpoint kind + 8 + 1 + read-write + + + EP_TYPE + Endpoint type + 9 + 2 + read-write + + + SETUP + Setup transaction + completed + 11 + 1 + read-only + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + read-write + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + read-write + + + CTR_RX + Correct transfer for + reception + 15 + 1 + read-write + + + + + USB_EP3R + USB_EP3R + endpoint 3 register + 0xC + 0x20 + 0x00000000 + + + EA + Endpoint address + 0 + 4 + read-write + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + read-write + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + read-write + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + read-write + + + EP_KIND + Endpoint kind + 8 + 1 + read-write + + + EP_TYPE + Endpoint type + 9 + 2 + read-write + + + SETUP + Setup transaction + completed + 11 + 1 + read-only + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + read-write + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + read-write + + + CTR_RX + Correct transfer for + reception + 15 + 1 + read-write + + + + + USB_EP4R + USB_EP4R + endpoint 4 register + 0x10 + 0x20 + 0x00000000 + + + EA + Endpoint address + 0 + 4 + read-write + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + read-write + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + read-write + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + read-write + + + EP_KIND + Endpoint kind + 8 + 1 + read-write + + + EP_TYPE + Endpoint type + 9 + 2 + read-write + + + SETUP + Setup transaction + completed + 11 + 1 + read-only + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + read-write + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + read-write + + + CTR_RX + Correct transfer for + reception + 15 + 1 + read-write + + + + + USB_EP5R + USB_EP5R + endpoint 5 register + 0x14 + 0x20 + 0x00000000 + + + EA + Endpoint address + 0 + 4 + read-write + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + read-write + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + read-write + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + read-write + + + EP_KIND + Endpoint kind + 8 + 1 + read-write + + + EP_TYPE + Endpoint type + 9 + 2 + read-write + + + SETUP + Setup transaction + completed + 11 + 1 + read-only + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + read-write + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + read-write + + + CTR_RX + Correct transfer for + reception + 15 + 1 + read-write + + + + + USB_EP6R + USB_EP6R + endpoint 6 register + 0x18 + 0x20 + 0x00000000 + + + EA + Endpoint address + 0 + 4 + read-write + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + read-write + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + read-write + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + read-write + + + EP_KIND + Endpoint kind + 8 + 1 + read-write + + + EP_TYPE + Endpoint type + 9 + 2 + read-write + + + SETUP + Setup transaction + completed + 11 + 1 + read-only + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + read-write + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + read-write + + + CTR_RX + Correct transfer for + reception + 15 + 1 + read-write + + + + + USB_EP7R + USB_EP7R + endpoint 7 register + 0x1C + 0x20 + 0x00000000 + + + EA + Endpoint address + 0 + 4 + read-write + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + read-write + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + read-write + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + read-write + + + EP_KIND + Endpoint kind + 8 + 1 + read-write + + + EP_TYPE + Endpoint type + 9 + 2 + read-write + + + SETUP + Setup transaction + completed + 11 + 1 + read-only + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + read-write + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + read-write + + + CTR_RX + Correct transfer for + reception + 15 + 1 + read-write + + + + + USB_CNTR + USB_CNTR + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + FRES + Force USB Reset + 0 + 1 + + + PDWN + Power down + 1 + 1 + + + LPMODE + Low-power mode + 2 + 1 + + + FSUSP + Force suspend + 3 + 1 + + + RESUME + Resume request + 4 + 1 + + + ESOFM + Expected start of frame interrupt + mask + 8 + 1 + + + SOFM + Start of frame interrupt + mask + 9 + 1 + + + RESETM + USB reset interrupt mask + 10 + 1 + + + SUSPM + Suspend mode interrupt + mask + 11 + 1 + + + WKUPM + Wakeup interrupt mask + 12 + 1 + + + ERRM + Error interrupt mask + 13 + 1 + + + PMAOVRM + Packet memory area over / underrun + interrupt mask + 14 + 1 + + + CTRM + Correct transfer interrupt + mask + 15 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x20 + 0x00000000 + + + EP_ID + Endpoint Identifier + 0 + 4 + read-only + + + DIR + Direction of transaction + 4 + 1 + read-only + + + ESOF + Expected start frame + 8 + 1 + read-write + + + SOF + start of frame + 9 + 1 + read-write + + + RESET + reset request + 10 + 1 + read-write + + + SUSP + Suspend mode request + 11 + 1 + read-write + + + WKUP + Wakeup + 12 + 1 + read-write + + + ERR + Error + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / + underrun + 14 + 1 + read-write + + + CTR + Correct transfer + 15 + 1 + read-only + + + + + FNR + FNR + frame number register + 0x48 + 0x20 + read-only + 0x0000 + + + FN + Frame number + 0 + 11 + + + LSOF + Lost SOF + 11 + 2 + + + LCK + Locked + 13 + 1 + + + RXDM + Receive data - line status + 14 + 1 + + + RXDP + Receive data + line status + 15 + 1 + + + + + DADDR + DADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADD + Device address + 0 + 1 + + + ADD1 + Device address + 1 + 1 + + + ADD2 + Device address + 2 + 1 + + + ADD3 + Device address + 3 + 1 + + + ADD4 + Device address + 4 + 1 + + + ADD5 + Device address + 5 + 1 + + + ADD6 + Device address + 6 + 1 + + + EF + Enable function + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTABLE + Buffer table + 3 + 13 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_ER + I2C1 error interrupt + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + read-write + + + TXIE + TX Interrupt enable + 1 + 1 + read-write + + + RXIE + RX Interrupt enable + 2 + 1 + read-write + + + ADDRIE + Address match interrupt enable (slave + only) + 3 + 1 + read-write + + + NACKIE + Not acknowledge received interrupt + enable + 4 + 1 + read-write + + + STOPIE + STOP detection Interrupt + enable + 5 + 1 + read-write + + + TCIE + Transfer Complete interrupt + enable + 6 + 1 + read-write + + + ERRIE + Error interrupts enable + 7 + 1 + read-write + + + DNF + Digital noise filter + 8 + 4 + read-write + + + ANFOFF + Analog noise filter OFF + 12 + 1 + read-write + + + SWRST + Software reset + 13 + 1 + write-only + + + TXDMAEN + DMA transmission requests + enable + 14 + 1 + read-write + + + RXDMAEN + DMA reception requests + enable + 15 + 1 + read-write + + + SBC + Slave byte control + 16 + 1 + read-write + + + NOSTRETCH + Clock stretching disable + 17 + 1 + read-write + + + WUPEN + Wakeup from STOP enable + 18 + 1 + read-write + + + GCEN + General call enable + 19 + 1 + read-write + + + SMBHEN + SMBus Host address enable + 20 + 1 + read-write + + + SMBDEN + SMBus Device Default address + enable + 21 + 1 + read-write + + + ALERTEN + SMBUS alert enable + 22 + 1 + read-write + + + PECEN + PEC enable + 23 + 1 + read-write + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master + mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave + mode) + 15 + 1 + + + STOP + Stop generation (master + mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read + direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master + mode) + 11 + 1 + + + RD_WRN + Transfer direction (master + mode) + 10 + 1 + + + SADD8 + Slave address bit 9:8 (master + mode) + 8 + 2 + + + SADD1 + Slave address bit 7:1 (master + mode) + 1 + 7 + + + SADD0 + Slave address bit 0 (master + mode) + 0 + 1 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1_0 + Interface address + 0 + 1 + + + OA1_1 + Interface address + 1 + 7 + + + OA1_8 + Interface address + 8 + 2 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master + mode) + 0 + 8 + + + SCLH + SCL high period (master + mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout + detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout + enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave + mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave + mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection + flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave + mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master + mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received + flag + 4 + 1 + read-only + + + ADDR + Address matched (slave + mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty + (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status + (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty + (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag + clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag + clear + 10 + 1 + + + ARLOCF + Arbitration lost flag + clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking + register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C3 + 0x40007800 + + I2C2_EV_EXTI24 + I2C2 event interrupt & EXTI Line24 + interrupt + 33 + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + WVU + Watchdog counter window value + update + 2 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window + value + 0 + 12 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + T + 7-bit counter + 0 + 7 + + + WDGA + Activation bit + 7 + 1 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB + Timer base + 7 + 2 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_WKUP + RTC Wakeup interrupt through the EXTI + line + 3 + + + RTCAlarm + RTC alarm interrupt + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + + + REFCKON + Reference clock detection enable (50 or + 60 Hz) + 4 + 1 + + + BYPSHAD + Bypass the shadow + registers + 5 + 1 + + + FMT + Hour format + 6 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + + + BKP + Backup + 18 + 1 + + + COSEL + Calibration output + selection + 19 + 1 + + + POL + Output polarity + 20 + 1 + + + OSEL + Output selection + 21 + 2 + + + COE + Calibration output enable + 23 + 1 + + + + + ISR + ISR + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + + + TAMP2F + RTC_TAMP2 detection flag + 14 + 1 + read-write + + + TAMP3F + RTC_TAMP3 detection flag + 15 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBR + ALRMBR + alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAFCR + TAFCR + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP3E + Tamper 3 detection enable + 5 + 1 + + + TAMP3TRG + Active level for tamper 3 + 6 + 1 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + PC13VALUE + PC13 value + 18 + 1 + + + PC13MODE + PC13 mode + 19 + 1 + + + PC14VALUE + PC14 value + 20 + 1 + + + PC14MODE + PC 14 mode + 21 + 1 + + + PC15VALUE + PC15 value + 22 + 1 + + + PC15MODE + PC15 mode + 23 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + backup register + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + backup register + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + backup register + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + backup register + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + backup register + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + backup register + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + backup register + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + backup register + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + backup register + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + backup register + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + backup register + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + backup register + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + backup register + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + backup register + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + backup register + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP20R + BKP20R + backup register + 0xA0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP21R + BKP21R + backup register + 0xA4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP22R + BKP22R + backup register + 0xA8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP23R + BKP23R + backup register + 0xAC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP24R + BKP24R + backup register + 0xB0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP25R + BKP25R + backup register + 0xB4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP26R + BKP26R + backup register + 0xB8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP27R + BKP27R + backup register + 0xBC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP28R + BKP28R + backup register + 0xC0 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP29R + BKP29R + backup register + 0xC4 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP30R + BKP30R + backup register + 0xC8 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP31R + BKP31R + backup register + 0xCC + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + TIM6 + Basic timers + TIMs + 0x40001000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + Low counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + TIM6_DACUNDER + TIM6 global and DAC12 underrun + interrupts + 54 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable + 29 + 1 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + EN1 + DAC channel1 enable + 0 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR2 + DAC channel2 DMA underrun + flag + 29 + 1 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + + + + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 12 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment + control + 5 + 1 + + + TRACE_MODE + Trace pin assignment + control + 6 + 2 + + + + + APB1FZ + APB1FZ + APB Low Freeze Register + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIM2_STOP + Debug Timer 2 stopped when Core is + halted + 0 + 1 + + + DBG_TIM3_STOP + Debug Timer 3 stopped when Core is + halted + 1 + 1 + + + DBG_TIM4_STOP + Debug Timer 4 stopped when Core is + halted + 2 + 1 + + + DBG_TIM5_STOP + Debug Timer 5 stopped when Core is + halted + 3 + 1 + + + DBG_TIM6_STOP + Debug Timer 6 stopped when Core is + halted + 4 + 1 + + + DBG_TIM7_STOP + Debug Timer 7 stopped when Core is + halted + 5 + 1 + + + DBG_TIM12_STOP + Debug Timer 12 stopped when Core is + halted + 6 + 1 + + + DBG_TIM13_STOP + Debug Timer 13 stopped when Core is + halted + 7 + 1 + + + DBG_TIMER14_STOP + Debug Timer 14 stopped when Core is + halted + 8 + 1 + + + DBG_TIM18_STOP + Debug Timer 18 stopped when Core is + halted + 9 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + I2C1_SMBUS_TIMEOUT + SMBUS timeout mode stopped when Core is + halted + 21 + 1 + + + I2C2_SMBUS_TIMEOUT + SMBUS timeout mode stopped when Core is + halted + 22 + 1 + + + DBG_CAN_STOP + Debug CAN stopped when core is + halted + 25 + 1 + + + + + APB2FZ + APB2FZ + APB High Freeze Register + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIM15_STOP + Debug Timer 15 stopped when Core is + halted + 2 + 1 + + + DBG_TIM16_STOP + Debug Timer 16 stopped when Core is + halted + 3 + 1 + + + DBG_TIM17_STO + Debug Timer 17 stopped when Core is + halted + 4 + 1 + + + DBG_TIM19_STOP + Debug Timer 19 stopped when Core is + halted + 5 + 1 + + + + + + + TIM1 + Advanced timer + TIMs + 0x40012C00 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + DIR + Direction + 4 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + MMS + Master mode selection + 4 + 3 + + + TI1S + TI1 selection + 7 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS5 + Output Idle state 5 + 16 + 1 + + + OIS6 + Output Idle state 6 + 18 + 1 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + SMS + Slave mode selection + 0 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + TS + Trigger selection + 4 + 3 + + + MSM + Master/Slave mode + 7 + 1 + + + ETF + External trigger filter + 8 + 4 + + + ETPS + External trigger prescaler + 12 + 2 + + + ECE + External clock enable + 14 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + SMS3 + Slave mode selection bit 3 + 16 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + C5IF + Capture/Compare 5 interrupt + flag + 16 + 1 + + + C6IF + Capture/Compare 6 interrupt + flag + 17 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + TG + Trigger generation + 6 + 1 + + + BG + Break generation + 7 + 1 + + + B2G + Break 2 generation + 8 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + OC1M_3 + Output Compare 1 mode bit + 3 + 16 + 1 + + + OC2M_3 + Output Compare 2 mode bit + 3 + 24 + 1 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + OC3M_3 + Output Compare 3 mode bit + 3 + 16 + 1 + + + OC4M_3 + Output Compare 4 mode bit + 3 + 24 + 1 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC5E + Capture/Compare 5 output + enable + 16 + 1 + + + CC5P + Capture/Compare 5 output + Polarity + 17 + 1 + + + CC6E + Capture/Compare 6 output + enable + 20 + 1 + + + CC6P + Capture/Compare 6 output + Polarity + 21 + 1 + + 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OFFSET2_CH + 26 + 5 + + + OFFSET2 + OFFSET2 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET3_EN + OFFSET3_EN + 31 + 1 + + + OFFSET3_CH + OFFSET3_CH + 26 + 5 + + + OFFSET3 + OFFSET3 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET4_EN + OFFSET4_EN + 31 + 1 + + + OFFSET4_CH + OFFSET4_CH + 26 + 5 + + + OFFSET4 + OFFSET4 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration + Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 1 + 18 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration + Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 1 + 18 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register + 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_1_15 + Differential mode for channels 15 to + 1 + 1 + 15 + read-write + + + DIFSEL_16_18 + Differential mode for channels 18 to + 16 + 16 + 3 + read-only + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + + + ADC2 + 0x50000100 + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + ADC3 + 0x50000400 + + ADC3 + ADC3 global interrupt + 47 + + + + ADC4 + 0x50000500 + + ADC4 + ADC4 global interrupt + 61 + + + + ADC1_2 + Analog-to-Digital Converter + ADC + 0x50000300 + + 0x0 + 0x11 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave + ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the + slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave + ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the + slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the + slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave + ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave + ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave + ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of + the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + MULT + Multi ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + DMACFG + DMA configuration (for multi-ADC + mode) + 13 + 1 + + + MDMA + Direct memory access mode for multi ADC + mode + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + VREFEN + VREFINT enable + 22 + 1 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VBATEN + VBAT enable + 24 + 1 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave + ADC + 16 + 16 + + + RDATA_MST + Regular data of the master + ADC + 0 + 16 + + + + + + + ADC3_4 + 0x50000700 + + + FMC + Flexible memory controller + FMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + FMC + FSMC global interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CCLKEN + CCLKEN + 20 + 1 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + PCR2 + PCR2 + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR2 + SR2 + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM2 + PMEM2 + Common memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT2 + PATT2 + Attribute memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR2 + ECCR2 + ECC result register 2 + 0x74 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR3 + PCR3 + PC Card/NAND Flash control register + 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR3 + SR3 + FIFO status and interrupt register + 3 + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM3 + PMEM3 + Common memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT3 + PATT3 + Attribute memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR3 + ECCR3 + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR4 + PCR4 + PC Card/NAND Flash control register + 4 + 0xA0 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR4 + SR4 + FIFO status and interrupt register + 4 + 0xA4 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM4 + PMEM4 + Common memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT4 + PATT4 + Attribute memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + PIO4 + PIO4 + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IOHIZx + IOHIZx + 24 + 8 + + + IOHOLDx + IOHOLDx + 16 + 8 + + + IOWAITx + IOWAITx + 8 + 8 + + + IOSETx + IOSETx + 0 + 8 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + Bus turnaround phase + duration + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + Bus turnaround phase + duration + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers + 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + Bus turnaround phase + duration + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + Bus turnaround phase + duration + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + + + SYSCFG_COMP_OPAMP + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + SYSCFG_CFGR1 + SYSCFG_CFGR1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + + + USB_IT_RMP + USB interrupt remap + 5 + 1 + + + TIM1_ITR_RMP + Timer 1 ITR3 selection + 6 + 1 + + + DAC_TRIG_RMP + DAC trigger remap (when TSEL = + 001) + 7 + 1 + + + ADC24_DMA_RMP + ADC24 DMA remapping bit + 8 + 1 + + + TIM16_DMA_RMP + TIM16 DMA request remapping + bit + 11 + 1 + + + TIM17_DMA_RMP + TIM17 DMA request remapping + bit + 12 + 1 + + + TIM6_DAC1_DMA_RMP + TIM6 and DAC1 DMA request remapping + bit + 13 + 1 + + + TIM7_DAC2_DMA_RMP + TIM7 and DAC2 DMA request remapping + bit + 14 + 1 + + + I2C_PB6_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 16 + 1 + + + I2C_PB7_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 17 + 1 + + + I2C_PB8_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 18 + 1 + + + I2C_PB9_FM + Fast Mode Plus (FM+) driving capability + activation bits. + 19 + 1 + + + I2C1_FM + I2C1 Fast Mode Plus + 20 + 1 + + + I2C2_FM + I2C2 Fast Mode Plus + 21 + 1 + + + ENCODER_MODE + Encoder mode + 22 + 2 + + + FPU_IT + Interrupt enable bits from + FPU + 26 + 6 + + + + + SYSCFG_EXTICR1 + SYSCFG_EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI 3 configuration bits + 12 + 4 + + + EXTI2 + EXTI 2 configuration bits + 8 + 4 + + + EXTI1 + EXTI 1 configuration bits + 4 + 4 + + + EXTI0 + EXTI 0 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR2 + SYSCFG_EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI 7 configuration bits + 12 + 4 + + + EXTI6 + EXTI 6 configuration bits + 8 + 4 + + + EXTI5 + EXTI 5 configuration bits + 4 + 4 + + + EXTI4 + EXTI 4 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR3 + SYSCFG_EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI 11 configuration bits + 12 + 4 + + + EXTI10 + EXTI 10 configuration bits + 8 + 4 + + + EXTI9 + EXTI 9 configuration bits + 4 + 4 + + + EXTI8 + EXTI 8 configuration bits + 0 + 4 + + + + + SYSCFG_EXTICR4 + SYSCFG_EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI 15 configuration bits + 12 + 4 + + + EXTI14 + EXTI 14 configuration bits + 8 + 4 + + + EXTI13 + EXTI 13 configuration bits + 4 + 4 + + + EXTI12 + EXTI 12 configuration bits + 0 + 4 + + + + + SYSCFG_CFGR2 + SYSCFG_CFGR2 + configuration register 2 + 0x18 + 0x20 + read-write + 0x0000 + + + LOCUP_LOCK + Cortex-M0 LOCKUP bit enable + bit + 0 + 1 + + + SRAM_PARITY_LOCK + SRAM parity lock bit + 1 + 1 + + + PVD_LOCK + PVD lock enable bit + 2 + 1 + + + BYP_ADD_PAR + Bypass address bit 29 in parity + calculation + 4 + 1 + + + SRAM_PEF + SRAM parity flag + 8 + 1 + + + + + SYSCFG_RCR + SYSCFG_RCR + CCM SRAM protection register + 0x4 + 0x20 + read-write + 0x0000 + + + PAGE0_WP + CCM SRAM page write protection + bit + 0 + 1 + + + PAGE1_WP + CCM SRAM page write protection + bit + 1 + 1 + + + PAGE2_WP + CCM SRAM page write protection + bit + 2 + 1 + + + PAGE3_WP + CCM SRAM page write protection + bit + 3 + 1 + + + PAGE4_WP + CCM SRAM page write protection + bit + 4 + 1 + + + PAGE5_WP + CCM SRAM page write protection + bit + 5 + 1 + + + PAGE6_WP + CCM SRAM page write protection + bit + 6 + 1 + + + PAGE7_WP + CCM SRAM page write protection + bit + 7 + 1 + + + + + SYSCFG_CFGR3 + SYSCFG_CFGR3 + configuration register 3 + 0x50 + 0x20 + read-write + 0x0000 + + + DAC1_TRIG5_RMP + DAC1_CH1 / DAC1_CH2 Trigger + remap + 17 + 1 + + + DAC1_TRIG3_RMP + DAC1_CH1 / DAC1_CH2 Trigger + remap + 16 + 1 + + + ADC2_DMA_RMP_1 + ADC2 DMA controller remapping + bit + 9 + 1 + + + ADC2_DMA_RMP_0 + ADC2 DMA channel remapping + bit + 6 + 2 + + + I2C1_RX_DMA_RMP + I2C1_RX DMA remapping bit + 4 + 2 + + + SPI1_TX_DMA_RMP + SPI1_TX DMA remapping bit + 2 + 2 + + + SPI1_RX_DMA_RMP + SPI1_RX DMA remapping bit + 0 + 2 + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control register + 0x3C + 0x20 + 0x00000000 + + + OPAMP2EN + OPAMP2 enable + 0 + 1 + read-write + + + FORCE_VP + FORCE_VP + 1 + 1 + read-write + + + VP_SEL + OPAMP2 Non inverting input + selection + 2 + 2 + read-write + + + VM_SEL + OPAMP2 inverting input + selection + 5 + 2 + read-write + + + TCM_EN + Timer controlled Mux mode + enable + 7 + 1 + read-write + + + VMS_SEL + OPAMP2 inverting input secondary + selection + 8 + 1 + read-write + + + VPS_SEL + OPAMP2 Non inverting input secondary + selection + 9 + 2 + read-write + + + CALON + Calibration mode enable + 11 + 1 + read-write + + + CAL_SEL + Calibration selection + 12 + 2 + read-write + + + PGA_GAIN + Gain in PGA mode + 14 + 4 + read-write + + + USER_TRIM + User trimming enable + 18 + 1 + read-write + + + TRIMOFFSETP + Offset trimming value + (PMOS) + 19 + 5 + read-write + + + TRIMOFFSETN + Offset trimming value + (NMOS) + 24 + 5 + read-write + + + TSTREF + TSTREF + 29 + 1 + read-write + + + OUTCAL + OPAMP 2 ouput status flag + 30 + 1 + read-only + + + LOCK + OPAMP 2 lock + 31 + 1 + read-write + + + + + COMP2_CSR + COMP2_CSR + control and status register + 0x20 + 0x20 + 0x00000000 + + + COMP2EN + Comparator 2 enable + 0 + 1 + read-write + + + COMP2MODE + Comparator 2 mode + 2 + 2 + read-write + + + COMP2INSEL + Comparator 2 inverting input + selection + 4 + 3 + read-write + + + COMP2INPSEL + Comparator 2 non inverted input + selection + 7 + 1 + read-write + + + COMP2INMSEL + Comparator 1inverting input + selection + 9 + 1 + read-write + + + COMP2_OUT_SEL + Comparator 2 output + selection + 10 + 4 + read-write + + + COMP2POL + Comparator 2 output + polarity + 15 + 1 + read-write + + + COMP2HYST + Comparator 2 hysteresis + 16 + 2 + read-write + + + COMP2_BLANKING + Comparator 2 blanking + source + 18 + 3 + read-write + + + COMP2OUT + Comparator 2 output + 30 + 1 + read-only + + + COMP2LOCK + Comparator 2 lock + 31 + 1 + read-write + + + + + COMP4_CSR + COMP4_CSR + control and status register + 0x28 + 0x20 + 0x00000000 + + + COMP4EN + Comparator 4 enable + 0 + 1 + read-write + + + COMP4MODE + Comparator 4 mode + 2 + 2 + read-write + + + COMP4INSEL + Comparator 4 inverting input + selection + 4 + 3 + read-write + + + COMP4INPSEL + Comparator 4 non inverted input + selection + 7 + 1 + read-write + + + COM4WINMODE + Comparator 4 window mode + 9 + 1 + read-write + + + COMP4_OUT_SEL + Comparator 4 output + selection + 10 + 4 + read-write + + + COMP4POL + Comparator 4 output + polarity + 15 + 1 + read-write + + + COMP4HYST + Comparator 4 hysteresis + 16 + 2 + read-write + + + COMP4_BLANKING + Comparator 4 blanking + source + 18 + 3 + read-write + + + COMP4OUT + Comparator 4 output + 30 + 1 + read-only + + + COMP4LOCK + Comparator 4 lock + 31 + 1 + read-write + + + + + COMP6_CSR + COMP6_CSR + control and status register + 0x30 + 0x20 + 0x00000000 + + + COMP6EN + Comparator 6 enable + 0 + 1 + read-write + + + COMP6MODE + Comparator 6 mode + 2 + 2 + read-write + + + COMP6INSEL + Comparator 6 inverting input + selection + 4 + 3 + read-write + + + COMP6INPSEL + Comparator 6 non inverted input + selection + 7 + 1 + read-write + + + COM6WINMODE + Comparator 6 window mode + 9 + 1 + read-write + + + COMP6_OUT_SEL + Comparator 6 output + selection + 10 + 4 + read-write + + + COMP6POL + Comparator 6 output + polarity + 15 + 1 + read-write + + + COMP6HYST + Comparator 6 hysteresis + 16 + 2 + read-write + + + COMP6_BLANKING + Comparator 6 blanking + source + 18 + 3 + read-write + + + COMP6OUT + Comparator 6 output + 30 + 1 + read-only + + + COMP6LOCK + Comparator 6 lock + 31 + 1 + read-write + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x355 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending + Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address + register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated + floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception + bit + 0 + 1 + + + DZC + Division by zero cumulative exception + bit. + 1 + 1 + + + OFC + Overflow cumulative exception + bit + 2 + 1 + + + UFC + Underflow cumulative exception + bit + 3 + 1 + + + IXC + Inexact cumulative exception + bit + 4 + 1 + + + IDC + Input denormal cumulative exception + bit. + 7 + 1 + + + RMode + Rounding Mode control + field + 22 + 2 + + + FZ + Flush-to-zero mode control + bit: + 24 + 1 + + + DN + Default NaN mode control + bit + 25 + 1 + + + AHP + Alternative half-precision control + bit + 26 + 1 + + + V + Overflow condition code + flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code + flag + 31 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-only + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CTRL + CTRL + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + LOAD + LOAD + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + VAL + VAL + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR1 + SHPR1 + System handler priority + registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler + 4 + 0 + 8 + + + PRI_5 + Priority of system handler + 5 + 8 + 8 + + + PRI_6 + Priority of system handler + 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + SHCSR + SHCSR + System handler control and state + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active + bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active + bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active + bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active + bit + 10 + 1 + + + SYSTICKACT + SysTick exception active + bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending + bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception + pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending + bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable + bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status + register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + Instruction access violation + flag + 1 + 1 + + + MUNSTKERR + Memory manager fault on unstacking for a + return from exception + 3 + 1 + + + MSTKERR + Memory manager fault on stacking for + exception entry. + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + Memory Management Fault Address Register + (MMAR) valid flag + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return + from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception + entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state + preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid + flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage + fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage + fault + 18 + 1 + + + NOCP + No coprocessor usage + fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage + fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + MMFAR + Memory management fault + address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + BFAR + Bus fault address + 0 + 32 + + + + + AFSR + AFSR + Auxiliary fault status + register + 0x3C + 0x20 + read-write + 0x00000000 + + + IMPDEF + Implementation defined + 0 + 32 + + + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control + register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISMCYCINT + DISMCYCINT + 0 + 1 + + + DISDEFWBUF + DISDEFWBUF + 1 + 1 + + + DISFOLD + DISFOLD + 2 + 1 + + + DISFPCA + DISFPCA + 8 + 1 + + + DISOOFP + DISOOFP + 9 + 1 + + + + + + + diff --git a/BMS_Testbench/BMS_Software_V1/STM32F302CCTX_FLASH.ld b/BMS_Testbench/BMS_Software_V1/STM32F302CCTX_FLASH.ld new file mode 100644 index 0000000..bef8c8f --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/STM32F302CCTX_FLASH.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32F302CCTx Device from STM32F3 series +** 256Kbytes FLASH +** 40Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 40K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/BMS_Testbench/BMS_Software_V1/STM32F302CCTx_FLASH.ld b/BMS_Testbench/BMS_Software_V1/STM32F302CCTx_FLASH.ld new file mode 100644 index 0000000..4bddf4d --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/STM32F302CCTx_FLASH.ld @@ -0,0 +1,189 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : STM32CubeMX +** +** Abstract : Linker script for STM32F302CCTx series +** 256Kbytes FLASH and 40Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,†without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

    © COPYRIGHT(c) 2019 STMicroelectronics

    +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 40K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/BMS_Testbench/BMS_Software_V1/STM32Make.make b/BMS_Testbench/BMS_Software_V1/STM32Make.make new file mode 100644 index 0000000..d0d120a --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/STM32Make.make @@ -0,0 +1,265 @@ +########################################################################################################################## +# File automatically-generated by STM32forVSCode +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = ams-slave-23 + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +Core/Src/ADBMS_Abstraction.c \ +Core/Src/ADBMS_LL_Driver.c \ +Core/Src/AMS_CAN.c \ +Core/Src/AMS_HighLevel.c \ +Core/Src/Testbench.c \ +Core/Src/main.c \ +Core/Src/stm32f3xx_hal_msp.c \ +Core/Src/stm32f3xx_it.c \ +Core/Src/syscalls.c \ +Core/Src/sysmem.c \ +Core/Src/system_stm32f3xx.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c + + +CPP_SOURCES = \ + + +# ASM sources +ASM_SOURCES = \ +startup_stm32f302xc.s + + + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +POSTFIX = " +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +GCC_PATH="/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin +ifdef GCC_PATH +CXX = $(GCC_PATH)/$(PREFIX)g++$(POSTFIX) +CC = $(GCC_PATH)/$(PREFIX)gcc$(POSTFIX) +AS = $(GCC_PATH)/$(PREFIX)gcc$(POSTFIX) -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy$(POSTFIX) +SZ = $(GCC_PATH)/$(PREFIX)size$(POSTFIX) +else +CXX = $(PREFIX)g++ +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m4 + +# fpu +FPU = -mfpu=fpv4-sp-d16 + +# float-abi +FLOAT-ABI = -mfloat-abi=hard + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DSTM32F302xC \ +-DUSE_HAL_DRIVER + + +# CXX defines +CXX_DEFS = \ +-DSTM32F302xC \ +-DUSE_HAL_DRIVER + + +# AS includes +AS_INCLUDES = \ + +# C includes +C_INCLUDES = \ +-ICore/Inc \ +-IDrivers/CMSIS/Device/ST/STM32F3xx/Include \ +-IDrivers/CMSIS/Include \ +-IDrivers/STM32F3xx_HAL_Driver/Inc \ +-IDrivers/STM32F3xx_HAL_Driver/Inc/Legacy + + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CXXFLAGS = $(MCU) $(CXX_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections -feliminate-unused-debug-types + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf -ggdb +CXXFLAGS += -g -gdwarf -ggdb +endif + +# Add additional flags +CFLAGS += -Wall -fdata-sections -ffunction-sections +ASFLAGS += -Wall -fdata-sections -ffunction-sections +CXXFLAGS += + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" +CXXFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = STM32F302CCTx_FLASH.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = \ + + +# Additional LD Flags from config file +ADDITIONALLDFLAGS = -specs=nano.specs + +LDFLAGS = $(MCU) $(ADDITIONALLDFLAGS) -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of cpp program objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(CPP_SOURCES:.cpp=.o))) +vpath %.cpp $(sort $(dir $(CPP_SOURCES))) + +# list of C objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) + +# list of ASM program objects +# list of ASM program objects +UPPER_CASE_ASM_SOURCES = $(filter %.S,$(ASM_SOURCES)) +LOWER_CASE_ASM_SOURCES = $(filter %.s,$(ASM_SOURCES)) + +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(UPPER_CASE_ASM_SOURCES:.S=.o))) +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(LOWER_CASE_ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.cpp STM32Make.make | $(BUILD_DIR) + $(CXX) -c $(CXXFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.cpp=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.cxx STM32Make.make | $(BUILD_DIR) + $(CXX) -c $(CXXFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.cxx=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.c STM32Make.make | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s STM32Make.make | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S STM32Make.make | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) STM32Make.make + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# flash +####################################### +flash: $(BUILD_DIR)/$(TARGET).elf + "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/openocd/0.12.0-1.1/.content/bin/openocd" -f ./openocd.cfg -c "program $(BUILD_DIR)/$(TARGET).elf verify reset exit" + +####################################### +# erase +####################################### +erase: $(BUILD_DIR)/$(TARGET).elf + "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/openocd/0.12.0-1.1/.content/bin/openocd" -f ./openocd.cfg -c "init; reset halt; stm32f3x mass_erase 0; exit" + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# custom makefile rules +####################################### + + + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** \ No newline at end of file diff --git a/BMS_Testbench/BMS_Software_V1/ams-slave-23 Debug.launch b/BMS_Testbench/BMS_Software_V1/ams-slave-23 Debug.launch new file mode 100644 index 0000000..18bbbbf --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/ams-slave-23 Debug.launch @@ -0,0 +1,77 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/BMS_Testbench/BMS_Software_V1/ams-slave-23.ioc b/BMS_Testbench/BMS_Software_V1/ams-slave-23.ioc new file mode 100644 index 0000000..47e2279 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/ams-slave-23.ioc @@ -0,0 +1,199 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +CAN.ABOM=ENABLE +CAN.BS1=CAN_BS1_13TQ +CAN.BS2=CAN_BS2_2TQ +CAN.CalculateBaudRate=500000 +CAN.CalculateTimeBit=2000 +CAN.CalculateTimeQuantum=125.0 +CAN.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2,Prescaler,NART,ABOM +CAN.NART=ENABLE +CAN.Prescaler=2 +File.Version=6 +KeepUserPlacement=false +Mcu.CPN=STM32F302CCT6 +Mcu.Family=STM32F3 +Mcu.IP0=CAN +Mcu.IP1=I2C1 +Mcu.IP2=I2C2 +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=SPI1 +Mcu.IP6=SYS +Mcu.IPNb=7 +Mcu.Name=STM32F302C(B-C)Tx +Mcu.Package=LQFP48 +Mcu.Pin0=PF0-OSC_IN +Mcu.Pin1=PF1-OSC_OUT +Mcu.Pin10=PA9 +Mcu.Pin11=PA10 +Mcu.Pin12=PA11 +Mcu.Pin13=PA12 +Mcu.Pin14=PA13 +Mcu.Pin15=PA14 +Mcu.Pin16=PA15 +Mcu.Pin17=PB3 +Mcu.Pin18=PB7 +Mcu.Pin2=PA4 +Mcu.Pin3=PA5 +Mcu.Pin4=PA6 +Mcu.Pin5=PA7 +Mcu.Pin6=PB13 +Mcu.Pin7=PB14 +Mcu.Pin8=PB15 +Mcu.Pin9=PA8 +Mcu.PinsNb=19 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F302CCTx +MxCube.Version=6.7.0 +MxDb.Version=DB.6.0.70 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.USB_LP_CAN_RX0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA10.Locked=true +PA10.Mode=I2C +PA10.Signal=I2C2_SDA +PA11.Locked=true +PA11.Mode=CAN_Activate +PA11.Signal=CAN_RX +PA12.Locked=true +PA12.Mode=CAN_Activate +PA12.Signal=CAN_TX +PA13.Locked=true +PA13.Mode=Trace_Asynchronous_SW +PA13.Signal=SYS_JTMS-SWDIO +PA14.Locked=true +PA14.Mode=Trace_Asynchronous_SW +PA14.Signal=SYS_JTCK-SWCLK +PA15.GPIOParameters=GPIO_Label +PA15.GPIO_Label=TMP_SCL +PA15.Locked=true +PA15.Mode=I2C +PA15.Signal=I2C1_SCL +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=CSB +PA4.Locked=true +PA4.Signal=GPIO_Output +PA5.Locked=true +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Locked=true +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Locked=true +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI +PA8.GPIOParameters=GPIO_Label +PA8.GPIO_Label=Status_3 +PA8.Locked=true +PA8.Signal=GPIO_Output +PA9.Locked=true +PA9.Mode=I2C +PA9.Signal=I2C2_SCL +PB13.GPIOParameters=GPIO_Label +PB13.GPIO_Label=Status_0 +PB13.Locked=true +PB13.Signal=GPIO_Output +PB14.GPIOParameters=GPIO_Label +PB14.GPIO_Label=Status_1 +PB14.Locked=true +PB14.Signal=GPIO_Output +PB15.GPIOParameters=GPIO_Label +PB15.GPIO_Label=Status_2 +PB15.Locked=true +PB15.Signal=GPIO_Output +PB3.Mode=Trace_Asynchronous_SW +PB3.Signal=SYS_JTDO-TRACESWO +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=TMP_SDA +PB7.Locked=true +PB7.Mode=I2C +PB7.Signal=I2C1_SDA +PF0-OSC_IN.Mode=HSE-External-Oscillator +PF0-OSC_IN.Signal=RCC_OSC_IN +PF1-OSC_OUT.Mode=HSE-External-Oscillator +PF1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F302CCTx +ProjectManager.FirmwarePackage=STM32Cube FW_F3 V1.11.3 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain=STM32CubeIDE +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=ams-slave-23.ioc +ProjectManager.ProjectName=ams-slave-23 +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_CAN_Init-CAN-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_I2C2_Init-I2C2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true +RCC.ADC12outputFreq_Value=32000000 +RCC.AHBFreq_Value=16000000 +RCC.APB1Freq_Value=16000000 +RCC.APB1TimFreq_Value=16000000 +RCC.APB2Freq_Value=16000000 +RCC.APB2TimFreq_Value=16000000 +RCC.CortexFreq_Value=16000000 +RCC.FCLKCortexFreq_Value=16000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=16000000 +RCC.HSEPLLFreq_Value=16000000 +RCC.HSE_VALUE=16000000 +RCC.HSIPLLFreq_Value=4000000 +RCC.HSI_VALUE=8000000 +RCC.I2C1Freq_Value=8000000 +RCC.I2C2Freq_Value=8000000 +RCC.IPParameters=ADC12outputFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSEPLLFreq_Value,HSE_VALUE,HSIPLLFreq_Value,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,LSE_VALUE,LSI_VALUE,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSourceVirtual,TIM1Freq_Value,TIM2Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOOutput2Freq_Value +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=40000 +RCC.MCOFreq_Value=16000000 +RCC.PLLCLKFreq_Value=32000000 +RCC.PLLMCOFreq_Value=16000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RTCFreq_Value=40000 +RCC.RTCHSEDivFreq_Value=500000 +RCC.SYSCLKFreq_VALUE=16000000 +RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_HSE +RCC.TIM1Freq_Value=16000000 +RCC.TIM2Freq_Value=16000000 +RCC.USART1Freq_Value=16000000 +RCC.USART2Freq_Value=16000000 +RCC.USART3Freq_Value=16000000 +RCC.USBFreq_Value=32000000 +RCC.VCOOutput2Freq_Value=16000000 +SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_32 +SPI1.CalculateBaudRate=500.0 KBits/s +SPI1.DataSize=SPI_DATASIZE_8BIT +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +board=custom diff --git a/BMS_Testbench/BMS_Software_V1/build/ADBMS_Abstraction.d b/BMS_Testbench/BMS_Software_V1/build/ADBMS_Abstraction.d new file mode 100644 index 0000000..2806c08 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/ADBMS_Abstraction.d @@ -0,0 +1,63 @@ +build/ADBMS_Abstraction.o: Core/Src/ADBMS_Abstraction.c \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Core/Inc/ADBMS_CMD_MAKROS.h +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Core/Inc/ADBMS_CMD_MAKROS.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/ADBMS_Abstraction.lst b/BMS_Testbench/BMS_Software_V1/build/ADBMS_Abstraction.lst new file mode 100644 index 0000000..150da99 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/ADBMS_Abstraction.lst @@ -0,0 +1,2389 @@ +ARM GAS /tmp/ccKQpHxH.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "ADBMS_Abstraction.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/ADBMS_Abstraction.c" + 20 .section .text.amsWakeUp,"ax",%progbits + 21 .align 1 + 22 .global amsWakeUp + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 amsWakeUp: + 28 .LFB131: + 1:Core/Src/ADBMS_Abstraction.c **** /* + 2:Core/Src/ADBMS_Abstraction.c **** * ADBMS_Abstraction.c + 3:Core/Src/ADBMS_Abstraction.c **** * + 4:Core/Src/ADBMS_Abstraction.c **** * Created on: 14.07.2022 + 5:Core/Src/ADBMS_Abstraction.c **** * Author: max + 6:Core/Src/ADBMS_Abstraction.c **** */ + 7:Core/Src/ADBMS_Abstraction.c **** + 8:Core/Src/ADBMS_Abstraction.c **** #include "ADBMS_Abstraction.h" + 9:Core/Src/ADBMS_Abstraction.c **** + 10:Core/Src/ADBMS_Abstraction.c **** + 11:Core/Src/ADBMS_Abstraction.c **** + 12:Core/Src/ADBMS_Abstraction.c **** uint8 numberofcells; + 13:Core/Src/ADBMS_Abstraction.c **** uint8 numberofauxchannels; + 14:Core/Src/ADBMS_Abstraction.c **** + 15:Core/Src/ADBMS_Abstraction.c **** uint8 initAMS(SPI_HandleTypeDef* hspi, uint8 numofcells, uint8 numofaux) + 16:Core/Src/ADBMS_Abstraction.c **** { + 17:Core/Src/ADBMS_Abstraction.c **** adbmsDriverInit(hspi); + 18:Core/Src/ADBMS_Abstraction.c **** numberofcells = numofcells; + 19:Core/Src/ADBMS_Abstraction.c **** numberofauxchannels = numofaux; + 20:Core/Src/ADBMS_Abstraction.c **** + 21:Core/Src/ADBMS_Abstraction.c **** + 22:Core/Src/ADBMS_Abstraction.c **** amsWakeUp(); + 23:Core/Src/ADBMS_Abstraction.c **** amsStopBalancing(); + 24:Core/Src/ADBMS_Abstraction.c **** amsConfigOverVoltage(DEFAULT_OV); + 25:Core/Src/ADBMS_Abstraction.c **** amsConfigUnderVoltage(DEFAULT_UV); + 26:Core/Src/ADBMS_Abstraction.c **** amsConfigAuxMeasurement(0xFFFF); + 27:Core/Src/ADBMS_Abstraction.c **** + 28:Core/Src/ADBMS_Abstraction.c **** return 0; + 29:Core/Src/ADBMS_Abstraction.c **** } + 30:Core/Src/ADBMS_Abstraction.c **** + ARM GAS /tmp/ccKQpHxH.s page 2 + + + 31:Core/Src/ADBMS_Abstraction.c **** uint8 amsWakeUp() + 32:Core/Src/ADBMS_Abstraction.c **** { + 29 .loc 1 32 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 0000 00B5 push {lr} + 34 .cfi_def_cfa_offset 4 + 35 .cfi_offset 14, -4 + 36 0002 83B0 sub sp, sp, #12 + 37 .cfi_def_cfa_offset 16 + 33:Core/Src/ADBMS_Abstraction.c **** uint8 buf[6]; + 38 .loc 1 33 2 view .LVU1 + 34:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGA, buf, 6); + 39 .loc 1 34 2 view .LVU2 + 40 0004 0622 movs r2, #6 + 41 0006 6946 mov r1, sp + 42 0008 0220 movs r0, #2 + 43 000a FFF7FEFF bl readCMD + 44 .LVL0: + 35:Core/Src/ADBMS_Abstraction.c **** return 0; + 45 .loc 1 35 2 view .LVU3 + 36:Core/Src/ADBMS_Abstraction.c **** } + 46 .loc 1 36 1 is_stmt 0 view .LVU4 + 47 000e 0020 movs r0, #0 + 48 0010 03B0 add sp, sp, #12 + 49 .cfi_def_cfa_offset 4 + 50 @ sp needed + 51 0012 5DF804FB ldr pc, [sp], #4 + 52 .cfi_endproc + 53 .LFE131: + 55 .section .text.amsConfigCellMeasurement,"ax",%progbits + 56 .align 1 + 57 .global amsConfigCellMeasurement + 58 .syntax unified + 59 .thumb + 60 .thumb_func + 62 amsConfigCellMeasurement: + 63 .LVL1: + 64 .LFB133: + 37:Core/Src/ADBMS_Abstraction.c **** + 38:Core/Src/ADBMS_Abstraction.c **** uint8 amsCellMeasurement(Cell_Module *module) + 39:Core/Src/ADBMS_Abstraction.c **** { + 40:Core/Src/ADBMS_Abstraction.c **** uint8_t rxbuffer[CV_GROUP_A_SIZE]; + 41:Core/Src/ADBMS_Abstraction.c **** writeCMD((ADCV | CH000 | MD10), rxbuffer, 0); + 42:Core/Src/ADBMS_Abstraction.c **** mcuDelay(5); + 43:Core/Src/ADBMS_Abstraction.c **** amsReadCellVoltages(module); + 44:Core/Src/ADBMS_Abstraction.c **** return 0; + 45:Core/Src/ADBMS_Abstraction.c **** } + 46:Core/Src/ADBMS_Abstraction.c **** + 47:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigCellMeasurement(uint8 numberofChannels) + 48:Core/Src/ADBMS_Abstraction.c **** { + 65 .loc 1 48 1 is_stmt 1 view -0 + 66 .cfi_startproc + 67 @ args = 0, pretend = 0, frame = 0 + 68 @ frame_needed = 0, uses_anonymous_args = 0 + 69 @ link register save eliminated. + ARM GAS /tmp/ccKQpHxH.s page 3 + + + 49:Core/Src/ADBMS_Abstraction.c **** numberofcells = numberofChannels; + 70 .loc 1 49 2 view .LVU6 + 71 .loc 1 49 16 is_stmt 0 view .LVU7 + 72 0000 014B ldr r3, .L4 + 73 0002 1870 strb r0, [r3] + 50:Core/Src/ADBMS_Abstraction.c **** return 0; + 74 .loc 1 50 2 is_stmt 1 view .LVU8 + 51:Core/Src/ADBMS_Abstraction.c **** } + 75 .loc 1 51 1 is_stmt 0 view .LVU9 + 76 0004 0020 movs r0, #0 + 77 .LVL2: + 78 .loc 1 51 1 view .LVU10 + 79 0006 7047 bx lr + 80 .L5: + 81 .align 2 + 82 .L4: + 83 0008 00000000 .word numberofcells + 84 .cfi_endproc + 85 .LFE133: + 87 .section .text.amsAuxMeasurement,"ax",%progbits + 88 .align 1 + 89 .global amsAuxMeasurement + 90 .syntax unified + 91 .thumb + 92 .thumb_func + 94 amsAuxMeasurement: + 95 .LVL3: + 96 .LFB134: + 52:Core/Src/ADBMS_Abstraction.c **** + 53:Core/Src/ADBMS_Abstraction.c **** uint8 amsAuxMeasurement(Cell_Module *module) + 54:Core/Src/ADBMS_Abstraction.c **** { + 97 .loc 1 54 1 is_stmt 1 view -0 + 98 .cfi_startproc + 99 @ args = 0, pretend = 0, frame = 8 + 100 @ frame_needed = 0, uses_anonymous_args = 0 + 101 .loc 1 54 1 is_stmt 0 view .LVU12 + 102 0000 10B5 push {r4, lr} + 103 .cfi_def_cfa_offset 8 + 104 .cfi_offset 4, -8 + 105 .cfi_offset 14, -4 + 106 0002 82B0 sub sp, sp, #8 + 107 .cfi_def_cfa_offset 16 + 108 0004 0446 mov r4, r0 + 55:Core/Src/ADBMS_Abstraction.c **** uint8 args; + 109 .loc 1 55 2 is_stmt 1 view .LVU13 + 56:Core/Src/ADBMS_Abstraction.c **** uint8 rxbuf[AUX_GROUP_A_SIZE]; + 110 .loc 1 56 2 view .LVU14 + 57:Core/Src/ADBMS_Abstraction.c **** writeCMD(ADAX | MD01 | CHG000, &args, 0); + 111 .loc 1 57 2 view .LVU15 + 112 0006 0022 movs r2, #0 + 113 0008 0DF10701 add r1, sp, #7 + 114 000c 4FF49C60 mov r0, #1248 + 115 .LVL4: + 116 .loc 1 57 2 is_stmt 0 view .LVU16 + 117 0010 FFF7FEFF bl writeCMD + 118 .LVL5: + 58:Core/Src/ADBMS_Abstraction.c **** + ARM GAS /tmp/ccKQpHxH.s page 4 + + + 59:Core/Src/ADBMS_Abstraction.c **** mcuDelay(5); + 119 .loc 1 59 2 is_stmt 1 view .LVU17 + 120 0014 0520 movs r0, #5 + 121 0016 FFF7FEFF bl mcuDelay + 122 .LVL6: + 60:Core/Src/ADBMS_Abstraction.c **** + 61:Core/Src/ADBMS_Abstraction.c **** readCMD(RDAUXA, rxbuf, AUX_GROUP_A_SIZE); + 123 .loc 1 61 2 view .LVU18 + 124 001a 0622 movs r2, #6 + 125 001c 6946 mov r1, sp + 126 001e 0C20 movs r0, #12 + 127 0020 FFF7FEFF bl readCMD + 128 .LVL7: + 62:Core/Src/ADBMS_Abstraction.c **** + 63:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[0] = rxbuf[0] | (rxbuf[1]<<8); + 129 .loc 1 63 2 view .LVU19 + 130 .loc 1 63 32 is_stmt 0 view .LVU20 + 131 0024 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 132 .loc 1 63 44 view .LVU21 + 133 0028 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 134 .loc 1 63 36 view .LVU22 + 135 002c 43EA0223 orr r3, r3, r2, lsl #8 + 136 .loc 1 63 25 view .LVU23 + 137 0030 A384 strh r3, [r4, #36] @ movhi + 64:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[1] = rxbuf[2] | (rxbuf[3]<<8); + 138 .loc 1 64 2 is_stmt 1 view .LVU24 + 139 .loc 1 64 32 is_stmt 0 view .LVU25 + 140 0032 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 141 .loc 1 64 44 view .LVU26 + 142 0036 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 143 .loc 1 64 36 view .LVU27 + 144 003a 43EA0223 orr r3, r3, r2, lsl #8 + 145 .loc 1 64 25 view .LVU28 + 146 003e E384 strh r3, [r4, #38] @ movhi + 65:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[2] = rxbuf[4] | (rxbuf[5]<<8); + 147 .loc 1 65 2 is_stmt 1 view .LVU29 + 148 .loc 1 65 32 is_stmt 0 view .LVU30 + 149 0040 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 150 .loc 1 65 44 view .LVU31 + 151 0044 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 152 .loc 1 65 36 view .LVU32 + 153 0048 43EA0223 orr r3, r3, r2, lsl #8 + 154 .loc 1 65 25 view .LVU33 + 155 004c 2385 strh r3, [r4, #40] @ movhi + 66:Core/Src/ADBMS_Abstraction.c **** + 67:Core/Src/ADBMS_Abstraction.c **** readCMD(RDAUXB, rxbuf, AUX_GROUP_A_SIZE); + 156 .loc 1 67 2 is_stmt 1 view .LVU34 + 157 004e 0622 movs r2, #6 + 158 0050 6946 mov r1, sp + 159 0052 0E20 movs r0, #14 + 160 0054 FFF7FEFF bl readCMD + 161 .LVL8: + 68:Core/Src/ADBMS_Abstraction.c **** + 69:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[3] = rxbuf[0] | (rxbuf[1]<<8); + 162 .loc 1 69 2 view .LVU35 + 163 .loc 1 69 32 is_stmt 0 view .LVU36 + 164 0058 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + ARM GAS /tmp/ccKQpHxH.s page 5 + + + 165 .loc 1 69 44 view .LVU37 + 166 005c 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 167 .loc 1 69 36 view .LVU38 + 168 0060 43EA0223 orr r3, r3, r2, lsl #8 + 169 .loc 1 69 25 view .LVU39 + 170 0064 6385 strh r3, [r4, #42] @ movhi + 70:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[4] = rxbuf[2] | (rxbuf[3]<<8); + 171 .loc 1 70 2 is_stmt 1 view .LVU40 + 172 .loc 1 70 32 is_stmt 0 view .LVU41 + 173 0066 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 174 .loc 1 70 44 view .LVU42 + 175 006a 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 176 .loc 1 70 36 view .LVU43 + 177 006e 43EA0223 orr r3, r3, r2, lsl #8 + 178 .loc 1 70 25 view .LVU44 + 179 0072 A385 strh r3, [r4, #44] @ movhi + 71:Core/Src/ADBMS_Abstraction.c **** module->refVoltage = rxbuf[4] | (rxbuf[5]<<8); + 180 .loc 1 71 2 is_stmt 1 view .LVU45 + 181 .loc 1 71 28 is_stmt 0 view .LVU46 + 182 0074 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 183 .loc 1 71 40 view .LVU47 + 184 0078 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 185 .loc 1 71 32 view .LVU48 + 186 007c 43EA0223 orr r3, r3, r2, lsl #8 + 187 .loc 1 71 21 view .LVU49 + 188 0080 A4F84030 strh r3, [r4, #64] @ movhi + 72:Core/Src/ADBMS_Abstraction.c **** + 73:Core/Src/ADBMS_Abstraction.c **** readCMD(RDAUXC, rxbuf, AUX_GROUP_A_SIZE); + 189 .loc 1 73 2 is_stmt 1 view .LVU50 + 190 0084 0622 movs r2, #6 + 191 0086 6946 mov r1, sp + 192 0088 0D20 movs r0, #13 + 193 008a FFF7FEFF bl readCMD + 194 .LVL9: + 74:Core/Src/ADBMS_Abstraction.c **** + 75:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[5] = rxbuf[0] | (rxbuf[1]<<8); + 195 .loc 1 75 2 view .LVU51 + 196 .loc 1 75 32 is_stmt 0 view .LVU52 + 197 008e 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 198 .loc 1 75 44 view .LVU53 + 199 0092 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 200 .loc 1 75 36 view .LVU54 + 201 0096 43EA0223 orr r3, r3, r2, lsl #8 + 202 .loc 1 75 25 view .LVU55 + 203 009a E385 strh r3, [r4, #46] @ movhi + 76:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[6] = rxbuf[2] | (rxbuf[3]<<8); + 204 .loc 1 76 2 is_stmt 1 view .LVU56 + 205 .loc 1 76 32 is_stmt 0 view .LVU57 + 206 009c 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 207 .loc 1 76 44 view .LVU58 + 208 00a0 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 209 .loc 1 76 36 view .LVU59 + 210 00a4 43EA0223 orr r3, r3, r2, lsl #8 + 211 .loc 1 76 25 view .LVU60 + 212 00a8 2386 strh r3, [r4, #48] @ movhi + 77:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[7] = rxbuf[4] | (rxbuf[5]<<8); + 213 .loc 1 77 2 is_stmt 1 view .LVU61 + ARM GAS /tmp/ccKQpHxH.s page 6 + + + 214 .loc 1 77 32 is_stmt 0 view .LVU62 + 215 00aa 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 216 .loc 1 77 44 view .LVU63 + 217 00ae 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 218 .loc 1 77 36 view .LVU64 + 219 00b2 43EA0223 orr r3, r3, r2, lsl #8 + 220 .loc 1 77 25 view .LVU65 + 221 00b6 6386 strh r3, [r4, #50] @ movhi + 78:Core/Src/ADBMS_Abstraction.c **** + 79:Core/Src/ADBMS_Abstraction.c **** readCMD(RDAUXD, rxbuf, AUX_GROUP_A_SIZE); + 222 .loc 1 79 2 is_stmt 1 view .LVU66 + 223 00b8 0622 movs r2, #6 + 224 00ba 6946 mov r1, sp + 225 00bc 0F20 movs r0, #15 + 226 00be FFF7FEFF bl readCMD + 227 .LVL10: + 80:Core/Src/ADBMS_Abstraction.c **** + 81:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[8] = rxbuf[0] | (rxbuf[1]<<8); + 228 .loc 1 81 2 view .LVU67 + 229 .loc 1 81 32 is_stmt 0 view .LVU68 + 230 00c2 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 231 .loc 1 81 44 view .LVU69 + 232 00c6 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 233 .loc 1 81 36 view .LVU70 + 234 00ca 43EA0223 orr r3, r3, r2, lsl #8 + 235 .loc 1 81 25 view .LVU71 + 236 00ce A386 strh r3, [r4, #52] @ movhi + 82:Core/Src/ADBMS_Abstraction.c **** + 83:Core/Src/ADBMS_Abstraction.c **** return 0; + 237 .loc 1 83 2 is_stmt 1 view .LVU72 + 84:Core/Src/ADBMS_Abstraction.c **** } + 238 .loc 1 84 1 is_stmt 0 view .LVU73 + 239 00d0 0020 movs r0, #0 + 240 00d2 02B0 add sp, sp, #8 + 241 .cfi_def_cfa_offset 8 + 242 @ sp needed + 243 00d4 10BD pop {r4, pc} + 244 .loc 1 84 1 view .LVU74 + 245 .cfi_endproc + 246 .LFE134: + 248 .section .text.amsInternalStatusMeasurement,"ax",%progbits + 249 .align 1 + 250 .global amsInternalStatusMeasurement + 251 .syntax unified + 252 .thumb + 253 .thumb_func + 255 amsInternalStatusMeasurement: + 256 .LVL11: + 257 .LFB135: + 85:Core/Src/ADBMS_Abstraction.c **** + 86:Core/Src/ADBMS_Abstraction.c **** uint8 amsInternalStatusMeasurement(Cell_Module *module) + 87:Core/Src/ADBMS_Abstraction.c **** { + 258 .loc 1 87 1 is_stmt 1 view -0 + 259 .cfi_startproc + 260 @ args = 0, pretend = 0, frame = 8 + 261 @ frame_needed = 0, uses_anonymous_args = 0 + 262 .loc 1 87 1 is_stmt 0 view .LVU76 + ARM GAS /tmp/ccKQpHxH.s page 7 + + + 263 0000 10B5 push {r4, lr} + 264 .cfi_def_cfa_offset 8 + 265 .cfi_offset 4, -8 + 266 .cfi_offset 14, -4 + 267 0002 82B0 sub sp, sp, #8 + 268 .cfi_def_cfa_offset 16 + 269 0004 0446 mov r4, r0 + 88:Core/Src/ADBMS_Abstraction.c **** uint8 rxbuffer[STATUS_GROUP_A_SIZE]; + 270 .loc 1 88 2 is_stmt 1 view .LVU77 + 89:Core/Src/ADBMS_Abstraction.c **** writeCMD(ADSTAT | MD01 | CHST000, rxbuffer, STATUS_GROUP_A_SIZE); + 271 .loc 1 89 2 view .LVU78 + 272 0006 0622 movs r2, #6 + 273 0008 6946 mov r1, sp + 274 000a 4FF49D60 mov r0, #1256 + 275 .LVL12: + 276 .loc 1 89 2 is_stmt 0 view .LVU79 + 277 000e FFF7FEFF bl writeCMD + 278 .LVL13: + 90:Core/Src/ADBMS_Abstraction.c **** mcuDelay(5); + 279 .loc 1 90 2 is_stmt 1 view .LVU80 + 280 0012 0520 movs r0, #5 + 281 0014 FFF7FEFF bl mcuDelay + 282 .LVL14: + 91:Core/Src/ADBMS_Abstraction.c **** + 92:Core/Src/ADBMS_Abstraction.c **** readCMD(RDSTATA, rxbuffer, STATUS_GROUP_A_SIZE); + 283 .loc 1 92 2 view .LVU81 + 284 0018 0622 movs r2, #6 + 285 001a 6946 mov r1, sp + 286 001c 1020 movs r0, #16 + 287 001e FFF7FEFF bl readCMD + 288 .LVL15: + 93:Core/Src/ADBMS_Abstraction.c **** + 94:Core/Src/ADBMS_Abstraction.c **** module->sumOfCellMeasurements = rxbuffer[0] | (rxbuffer[1]<<8); + 289 .loc 1 94 2 view .LVU82 + 290 .loc 1 94 42 is_stmt 0 view .LVU83 + 291 0022 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 292 .loc 1 94 57 view .LVU84 + 293 0026 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 294 .loc 1 94 46 view .LVU85 + 295 002a 43EA0223 orr r3, r3, r2, lsl #8 + 296 .loc 1 94 32 view .LVU86 + 297 002e E387 strh r3, [r4, #62] @ movhi + 95:Core/Src/ADBMS_Abstraction.c **** module->internalDieTemp = rxbuffer[2] | (rxbuffer[3]<<8); + 298 .loc 1 95 2 is_stmt 1 view .LVU87 + 299 .loc 1 95 39 is_stmt 0 view .LVU88 + 300 0030 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 301 .loc 1 95 54 view .LVU89 + 302 0034 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 303 .loc 1 95 43 view .LVU90 + 304 0038 43EA0223 orr r3, r3, r2, lsl #8 + 305 .loc 1 95 29 view .LVU91 + 306 003c 2387 strh r3, [r4, #56] @ movhi + 96:Core/Src/ADBMS_Abstraction.c **** module->analogSupplyVoltage = rxbuffer[4] | (rxbuffer[5]<<8); + 307 .loc 1 96 2 is_stmt 1 view .LVU92 + 308 .loc 1 96 42 is_stmt 0 view .LVU93 + 309 003e 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 310 .loc 1 96 57 view .LVU94 + ARM GAS /tmp/ccKQpHxH.s page 8 + + + 311 0042 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 312 .loc 1 96 46 view .LVU95 + 313 0046 43EA0223 orr r3, r3, r2, lsl #8 + 314 .loc 1 96 32 view .LVU96 + 315 004a 6387 strh r3, [r4, #58] @ movhi + 97:Core/Src/ADBMS_Abstraction.c **** + 98:Core/Src/ADBMS_Abstraction.c **** readCMD(RDSTATB, rxbuffer, STATUS_GROUP_B_SIZE); + 316 .loc 1 98 2 is_stmt 1 view .LVU97 + 317 004c 0622 movs r2, #6 + 318 004e 6946 mov r1, sp + 319 0050 1220 movs r0, #18 + 320 0052 FFF7FEFF bl readCMD + 321 .LVL16: + 99:Core/Src/ADBMS_Abstraction.c **** module->digitalSupplyVoltage = rxbuffer[0] | (rxbuffer[1]<<8); + 322 .loc 1 99 2 view .LVU98 + 323 .loc 1 99 41 is_stmt 0 view .LVU99 + 324 0056 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 325 .loc 1 99 56 view .LVU100 + 326 005a 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 327 .loc 1 99 45 view .LVU101 + 328 005e 43EA0223 orr r3, r3, r2, lsl #8 + 329 .loc 1 99 31 view .LVU102 + 330 0062 A387 strh r3, [r4, #60] @ movhi + 100:Core/Src/ADBMS_Abstraction.c **** + 101:Core/Src/ADBMS_Abstraction.c **** + 102:Core/Src/ADBMS_Abstraction.c **** return 0; + 331 .loc 1 102 2 is_stmt 1 view .LVU103 + 103:Core/Src/ADBMS_Abstraction.c **** } + 332 .loc 1 103 1 is_stmt 0 view .LVU104 + 333 0064 0020 movs r0, #0 + 334 0066 02B0 add sp, sp, #8 + 335 .cfi_def_cfa_offset 8 + 336 @ sp needed + 337 0068 10BD pop {r4, pc} + 338 .loc 1 103 1 view .LVU105 + 339 .cfi_endproc + 340 .LFE135: + 342 .section .text.amsConfigAuxMeasurement,"ax",%progbits + 343 .align 1 + 344 .global amsConfigAuxMeasurement + 345 .syntax unified + 346 .thumb + 347 .thumb_func + 349 amsConfigAuxMeasurement: + 350 .LVL17: + 351 .LFB136: + 104:Core/Src/ADBMS_Abstraction.c **** + 105:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigAuxMeasurement(uint16 Channels) + 106:Core/Src/ADBMS_Abstraction.c **** { + 352 .loc 1 106 1 is_stmt 1 view -0 + 353 .cfi_startproc + 354 @ args = 0, pretend = 0, frame = 8 + 355 @ frame_needed = 0, uses_anonymous_args = 0 + 356 .loc 1 106 1 is_stmt 0 view .LVU107 + 357 0000 00B5 push {lr} + 358 .cfi_def_cfa_offset 4 + 359 .cfi_offset 14, -4 + ARM GAS /tmp/ccKQpHxH.s page 9 + + + 360 0002 83B0 sub sp, sp, #12 + 361 .cfi_def_cfa_offset 16 + 107:Core/Src/ADBMS_Abstraction.c **** uint8 buf[CFG_GROUP_A_SIZE]; + 362 .loc 1 107 2 is_stmt 1 view .LVU108 + 108:Core/Src/ADBMS_Abstraction.c **** + 109:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGA, buf, CFG_GROUP_A_SIZE); + 363 .loc 1 109 2 view .LVU109 + 364 0004 0622 movs r2, #6 + 365 0006 6946 mov r1, sp + 366 0008 0220 movs r0, #2 + 367 .LVL18: + 368 .loc 1 109 2 is_stmt 0 view .LVU110 + 369 000a FFF7FEFF bl readCMD + 370 .LVL19: + 110:Core/Src/ADBMS_Abstraction.c **** buf[0] |= 0xF8; + 371 .loc 1 110 2 is_stmt 1 view .LVU111 + 372 .loc 1 110 5 is_stmt 0 view .LVU112 + 373 000e 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 374 .loc 1 110 9 view .LVU113 + 375 0012 63F00703 orn r3, r3, #7 + 376 0016 8DF80030 strb r3, [sp] + 111:Core/Src/ADBMS_Abstraction.c **** writeCMD(WRCFGA, buf, CFG_GROUP_A_SIZE); + 377 .loc 1 111 2 is_stmt 1 view .LVU114 + 378 001a 0622 movs r2, #6 + 379 001c 6946 mov r1, sp + 380 001e 0120 movs r0, #1 + 381 0020 FFF7FEFF bl writeCMD + 382 .LVL20: + 112:Core/Src/ADBMS_Abstraction.c **** + 113:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGB, buf, CFG_GROUP_B_SIZE); + 383 .loc 1 113 2 view .LVU115 + 384 0024 0622 movs r2, #6 + 385 0026 6946 mov r1, sp + 386 0028 2620 movs r0, #38 + 387 002a FFF7FEFF bl readCMD + 388 .LVL21: + 114:Core/Src/ADBMS_Abstraction.c **** buf[0] |= 0x0F; + 389 .loc 1 114 2 view .LVU116 + 390 .loc 1 114 5 is_stmt 0 view .LVU117 + 391 002e 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 392 .loc 1 114 9 view .LVU118 + 393 0032 43F00F03 orr r3, r3, #15 + 394 0036 8DF80030 strb r3, [sp] + 115:Core/Src/ADBMS_Abstraction.c **** writeCMD(WRCFGB, buf, CFG_GROUP_B_SIZE); + 395 .loc 1 115 2 is_stmt 1 view .LVU119 + 396 003a 0622 movs r2, #6 + 397 003c 6946 mov r1, sp + 398 003e 2420 movs r0, #36 + 399 0040 FFF7FEFF bl writeCMD + 400 .LVL22: + 116:Core/Src/ADBMS_Abstraction.c **** return 0; + 401 .loc 1 116 2 view .LVU120 + 117:Core/Src/ADBMS_Abstraction.c **** } + 402 .loc 1 117 1 is_stmt 0 view .LVU121 + 403 0044 0020 movs r0, #0 + 404 0046 03B0 add sp, sp, #12 + 405 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccKQpHxH.s page 10 + + + 406 @ sp needed + 407 0048 5DF804FB ldr pc, [sp], #4 + 408 .cfi_endproc + 409 .LFE136: + 411 .section .text.amsConfigGPIO,"ax",%progbits + 412 .align 1 + 413 .global amsConfigGPIO + 414 .syntax unified + 415 .thumb + 416 .thumb_func + 418 amsConfigGPIO: + 419 .LVL23: + 420 .LFB137: + 118:Core/Src/ADBMS_Abstraction.c **** + 119:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigGPIO(uint16 gpios) + 120:Core/Src/ADBMS_Abstraction.c **** { + 421 .loc 1 120 1 is_stmt 1 view -0 + 422 .cfi_startproc + 423 @ args = 0, pretend = 0, frame = 0 + 424 @ frame_needed = 0, uses_anonymous_args = 0 + 425 @ link register save eliminated. + 121:Core/Src/ADBMS_Abstraction.c **** return 0; + 426 .loc 1 121 2 view .LVU123 + 122:Core/Src/ADBMS_Abstraction.c **** } + 427 .loc 1 122 1 is_stmt 0 view .LVU124 + 428 0000 0020 movs r0, #0 + 429 .LVL24: + 430 .loc 1 122 1 view .LVU125 + 431 0002 7047 bx lr + 432 .cfi_endproc + 433 .LFE137: + 435 .section .text.amsSetGPIO,"ax",%progbits + 436 .align 1 + 437 .global amsSetGPIO + 438 .syntax unified + 439 .thumb + 440 .thumb_func + 442 amsSetGPIO: + 443 .LVL25: + 444 .LFB138: + 123:Core/Src/ADBMS_Abstraction.c **** + 124:Core/Src/ADBMS_Abstraction.c **** uint8 amsSetGPIO(uint16 gpios) + 125:Core/Src/ADBMS_Abstraction.c **** { + 445 .loc 1 125 1 is_stmt 1 view -0 + 446 .cfi_startproc + 447 @ args = 0, pretend = 0, frame = 0 + 448 @ frame_needed = 0, uses_anonymous_args = 0 + 449 @ link register save eliminated. + 126:Core/Src/ADBMS_Abstraction.c **** return 0; + 450 .loc 1 126 2 view .LVU127 + 127:Core/Src/ADBMS_Abstraction.c **** } + 451 .loc 1 127 1 is_stmt 0 view .LVU128 + 452 0000 0020 movs r0, #0 + 453 .LVL26: + 454 .loc 1 127 1 view .LVU129 + 455 0002 7047 bx lr + 456 .cfi_endproc + ARM GAS /tmp/ccKQpHxH.s page 11 + + + 457 .LFE138: + 459 .section .text.readGPIO,"ax",%progbits + 460 .align 1 + 461 .global readGPIO + 462 .syntax unified + 463 .thumb + 464 .thumb_func + 466 readGPIO: + 467 .LVL27: + 468 .LFB139: + 128:Core/Src/ADBMS_Abstraction.c **** + 129:Core/Src/ADBMS_Abstraction.c **** uint8 readGPIO(Cell_Module* module) + 130:Core/Src/ADBMS_Abstraction.c **** { + 469 .loc 1 130 1 is_stmt 1 view -0 + 470 .cfi_startproc + 471 @ args = 0, pretend = 0, frame = 0 + 472 @ frame_needed = 0, uses_anonymous_args = 0 + 473 @ link register save eliminated. + 131:Core/Src/ADBMS_Abstraction.c **** return 0; + 474 .loc 1 131 2 view .LVU131 + 132:Core/Src/ADBMS_Abstraction.c **** } + 475 .loc 1 132 1 is_stmt 0 view .LVU132 + 476 0000 0020 movs r0, #0 + 477 .LVL28: + 478 .loc 1 132 1 view .LVU133 + 479 0002 7047 bx lr + 480 .cfi_endproc + 481 .LFE139: + 483 .section .text.amsConfigBalancing,"ax",%progbits + 484 .align 1 + 485 .global amsConfigBalancing + 486 .syntax unified + 487 .thumb + 488 .thumb_func + 490 amsConfigBalancing: + 491 .LVL29: + 492 .LFB140: + 133:Core/Src/ADBMS_Abstraction.c **** + 134:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigBalancing(uint32 Channels) + 135:Core/Src/ADBMS_Abstraction.c **** { + 493 .loc 1 135 1 is_stmt 1 view -0 + 494 .cfi_startproc + 495 @ args = 0, pretend = 0, frame = 8 + 496 @ frame_needed = 0, uses_anonymous_args = 0 + 497 .loc 1 135 1 is_stmt 0 view .LVU135 + 498 0000 30B5 push {r4, r5, lr} + 499 .cfi_def_cfa_offset 12 + 500 .cfi_offset 4, -12 + 501 .cfi_offset 5, -8 + 502 .cfi_offset 14, -4 + 503 0002 83B0 sub sp, sp, #12 + 504 .cfi_def_cfa_offset 24 + 505 0004 0446 mov r4, r0 + 136:Core/Src/ADBMS_Abstraction.c **** + 137:Core/Src/ADBMS_Abstraction.c **** uint8 regbuffer[CFG_GROUP_A_SIZE]; + 506 .loc 1 137 2 is_stmt 1 view .LVU136 + 138:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGA, regbuffer, CFG_GROUP_A_SIZE); + ARM GAS /tmp/ccKQpHxH.s page 12 + + + 507 .loc 1 138 2 view .LVU137 + 508 0006 0622 movs r2, #6 + 509 0008 6946 mov r1, sp + 510 000a 0220 movs r0, #2 + 511 .LVL30: + 512 .loc 1 138 2 is_stmt 0 view .LVU138 + 513 000c FFF7FEFF bl readCMD + 514 .LVL31: + 139:Core/Src/ADBMS_Abstraction.c **** + 140:Core/Src/ADBMS_Abstraction.c **** regbuffer[4] = Channels & 0xFF; + 515 .loc 1 140 2 is_stmt 1 view .LVU139 + 516 .loc 1 140 15 is_stmt 0 view .LVU140 + 517 0010 8DF80440 strb r4, [sp, #4] + 141:Core/Src/ADBMS_Abstraction.c **** regbuffer[5] &= 0xF0; + 518 .loc 1 141 2 is_stmt 1 view .LVU141 + 519 .loc 1 141 11 is_stmt 0 view .LVU142 + 520 0014 9DF80530 ldrb r3, [sp, #5] @ zero_extendqisi2 + 521 .loc 1 141 15 view .LVU143 + 522 0018 03F0F003 and r3, r3, #240 + 523 001c 8DF80530 strb r3, [sp, #5] + 142:Core/Src/ADBMS_Abstraction.c **** regbuffer[5] |= (Channels>>8) & 0x0F; + 524 .loc 1 142 2 is_stmt 1 view .LVU144 + 525 .loc 1 142 32 is_stmt 0 view .LVU145 + 526 0020 C4F30725 ubfx r5, r4, #8, #8 + 527 0024 C4F30322 ubfx r2, r4, #8, #4 + 528 .loc 1 142 15 view .LVU146 + 529 0028 1343 orrs r3, r3, r2 + 530 002a 8DF80530 strb r3, [sp, #5] + 143:Core/Src/ADBMS_Abstraction.c **** writeCMD(WRCFGA, regbuffer, CFG_GROUP_A_SIZE); + 531 .loc 1 143 2 is_stmt 1 view .LVU147 + 532 002e 0622 movs r2, #6 + 533 0030 6946 mov r1, sp + 534 0032 0120 movs r0, #1 + 535 0034 FFF7FEFF bl writeCMD + 536 .LVL32: + 144:Core/Src/ADBMS_Abstraction.c **** + 145:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGB, regbuffer, CFG_GROUP_B_SIZE); + 537 .loc 1 145 2 view .LVU148 + 538 0038 0622 movs r2, #6 + 539 003a 6946 mov r1, sp + 540 003c 2620 movs r0, #38 + 541 003e FFF7FEFF bl readCMD + 542 .LVL33: + 146:Core/Src/ADBMS_Abstraction.c **** regbuffer[0] &= 0x0F; + 543 .loc 1 146 2 view .LVU149 + 544 .loc 1 146 11 is_stmt 0 view .LVU150 + 545 0042 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 546 .loc 1 146 15 view .LVU151 + 547 0046 03F00F03 and r3, r3, #15 + 548 004a 8DF80030 strb r3, [sp] + 147:Core/Src/ADBMS_Abstraction.c **** regbuffer[0] |= (Channels>>8) & 0xF0; + 549 .loc 1 147 2 is_stmt 1 view .LVU152 + 550 .loc 1 147 32 is_stmt 0 view .LVU153 + 551 004e 05F0F005 and r5, r5, #240 + 552 .loc 1 147 15 view .LVU154 + 553 0052 2B43 orrs r3, r3, r5 + 554 0054 8DF80030 strb r3, [sp] + ARM GAS /tmp/ccKQpHxH.s page 13 + + + 148:Core/Src/ADBMS_Abstraction.c **** regbuffer[1] &= 0xFC; + 555 .loc 1 148 2 is_stmt 1 view .LVU155 + 556 .loc 1 148 11 is_stmt 0 view .LVU156 + 557 0058 9DF80130 ldrb r3, [sp, #1] @ zero_extendqisi2 + 558 .loc 1 148 15 view .LVU157 + 559 005c 03F0FC03 and r3, r3, #252 + 560 0060 8DF80130 strb r3, [sp, #1] + 149:Core/Src/ADBMS_Abstraction.c **** regbuffer[1] |= 0x03 & (Channels>>16); + 561 .loc 1 149 2 is_stmt 1 view .LVU158 + 562 .loc 1 149 23 is_stmt 0 view .LVU159 + 563 0064 C4F30144 ubfx r4, r4, #16, #2 + 564 .LVL34: + 565 .loc 1 149 15 view .LVU160 + 566 0068 2343 orrs r3, r3, r4 + 567 006a 8DF80130 strb r3, [sp, #1] + 150:Core/Src/ADBMS_Abstraction.c **** writeCMD(WRCFGB, regbuffer, CFG_GROUP_B_SIZE); + 568 .loc 1 150 2 is_stmt 1 view .LVU161 + 569 006e 0622 movs r2, #6 + 570 0070 6946 mov r1, sp + 571 0072 2420 movs r0, #36 + 572 0074 FFF7FEFF bl writeCMD + 573 .LVL35: + 151:Core/Src/ADBMS_Abstraction.c **** + 152:Core/Src/ADBMS_Abstraction.c **** return 0; + 574 .loc 1 152 2 view .LVU162 + 153:Core/Src/ADBMS_Abstraction.c **** } + 575 .loc 1 153 1 is_stmt 0 view .LVU163 + 576 0078 0020 movs r0, #0 + 577 007a 03B0 add sp, sp, #12 + 578 .cfi_def_cfa_offset 12 + 579 @ sp needed + 580 007c 30BD pop {r4, r5, pc} + 581 .cfi_endproc + 582 .LFE140: + 584 .section .text.amsStartBalancing,"ax",%progbits + 585 .align 1 + 586 .global amsStartBalancing + 587 .syntax unified + 588 .thumb + 589 .thumb_func + 591 amsStartBalancing: + 592 .LVL36: + 593 .LFB141: + 154:Core/Src/ADBMS_Abstraction.c **** + 155:Core/Src/ADBMS_Abstraction.c **** uint8 amsStartBalancing(uint8 dutyCycle) + 156:Core/Src/ADBMS_Abstraction.c **** { + 594 .loc 1 156 1 is_stmt 1 view -0 + 595 .cfi_startproc + 596 @ args = 0, pretend = 0, frame = 0 + 597 @ frame_needed = 0, uses_anonymous_args = 0 + 598 .loc 1 156 1 is_stmt 0 view .LVU165 + 599 0000 08B5 push {r3, lr} + 600 .cfi_def_cfa_offset 8 + 601 .cfi_offset 3, -8 + 602 .cfi_offset 14, -4 + 157:Core/Src/ADBMS_Abstraction.c **** writeCMD(UNMUTE, NULL, 0); + 603 .loc 1 157 2 is_stmt 1 view .LVU166 + ARM GAS /tmp/ccKQpHxH.s page 14 + + + 604 0002 0022 movs r2, #0 + 605 0004 1146 mov r1, r2 + 606 0006 2920 movs r0, #41 + 607 .LVL37: + 608 .loc 1 157 2 is_stmt 0 view .LVU167 + 609 0008 FFF7FEFF bl writeCMD + 610 .LVL38: + 158:Core/Src/ADBMS_Abstraction.c **** return 0; + 611 .loc 1 158 2 is_stmt 1 view .LVU168 + 159:Core/Src/ADBMS_Abstraction.c **** } + 612 .loc 1 159 1 is_stmt 0 view .LVU169 + 613 000c 0020 movs r0, #0 + 614 000e 08BD pop {r3, pc} + 615 .cfi_endproc + 616 .LFE141: + 618 .section .text.amsStopBalancing,"ax",%progbits + 619 .align 1 + 620 .global amsStopBalancing + 621 .syntax unified + 622 .thumb + 623 .thumb_func + 625 amsStopBalancing: + 626 .LFB142: + 160:Core/Src/ADBMS_Abstraction.c **** + 161:Core/Src/ADBMS_Abstraction.c **** uint8 amsStopBalancing() + 162:Core/Src/ADBMS_Abstraction.c **** { + 627 .loc 1 162 1 is_stmt 1 view -0 + 628 .cfi_startproc + 629 @ args = 0, pretend = 0, frame = 0 + 630 @ frame_needed = 0, uses_anonymous_args = 0 + 631 0000 08B5 push {r3, lr} + 632 .cfi_def_cfa_offset 8 + 633 .cfi_offset 3, -8 + 634 .cfi_offset 14, -4 + 163:Core/Src/ADBMS_Abstraction.c **** writeCMD(MUTE, NULL, 0); + 635 .loc 1 163 2 view .LVU171 + 636 0002 0022 movs r2, #0 + 637 0004 1146 mov r1, r2 + 638 0006 2820 movs r0, #40 + 639 0008 FFF7FEFF bl writeCMD + 640 .LVL39: + 164:Core/Src/ADBMS_Abstraction.c **** return 0; + 641 .loc 1 164 2 view .LVU172 + 165:Core/Src/ADBMS_Abstraction.c **** } + 642 .loc 1 165 1 is_stmt 0 view .LVU173 + 643 000c 0020 movs r0, #0 + 644 000e 08BD pop {r3, pc} + 645 .cfi_endproc + 646 .LFE142: + 648 .section .text.amsSelfTest,"ax",%progbits + 649 .align 1 + 650 .global amsSelfTest + 651 .syntax unified + 652 .thumb + 653 .thumb_func + 655 amsSelfTest: + 656 .LFB143: + ARM GAS /tmp/ccKQpHxH.s page 15 + + + 166:Core/Src/ADBMS_Abstraction.c **** + 167:Core/Src/ADBMS_Abstraction.c **** uint8 amsSelfTest() + 168:Core/Src/ADBMS_Abstraction.c **** { + 657 .loc 1 168 1 is_stmt 1 view -0 + 658 .cfi_startproc + 659 @ args = 0, pretend = 0, frame = 0 + 660 @ frame_needed = 0, uses_anonymous_args = 0 + 661 @ link register save eliminated. + 169:Core/Src/ADBMS_Abstraction.c **** return 0; + 662 .loc 1 169 2 view .LVU175 + 170:Core/Src/ADBMS_Abstraction.c **** } + 663 .loc 1 170 1 is_stmt 0 view .LVU176 + 664 0000 0020 movs r0, #0 + 665 0002 7047 bx lr + 666 .cfi_endproc + 667 .LFE143: + 669 .section .text.amsConfigUnderVoltage,"ax",%progbits + 670 .align 1 + 671 .global amsConfigUnderVoltage + 672 .syntax unified + 673 .thumb + 674 .thumb_func + 676 amsConfigUnderVoltage: + 677 .LVL40: + 678 .LFB144: + 171:Core/Src/ADBMS_Abstraction.c **** + 172:Core/Src/ADBMS_Abstraction.c **** + 173:Core/Src/ADBMS_Abstraction.c **** + 174:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigUnderVoltage(uint16 underVoltage) + 175:Core/Src/ADBMS_Abstraction.c **** { + 679 .loc 1 175 1 is_stmt 1 view -0 + 680 .cfi_startproc + 681 @ args = 0, pretend = 0, frame = 8 + 682 @ frame_needed = 0, uses_anonymous_args = 0 + 683 .loc 1 175 1 is_stmt 0 view .LVU178 + 684 0000 10B5 push {r4, lr} + 685 .cfi_def_cfa_offset 8 + 686 .cfi_offset 4, -8 + 687 .cfi_offset 14, -4 + 688 0002 82B0 sub sp, sp, #8 + 689 .cfi_def_cfa_offset 16 + 690 0004 0446 mov r4, r0 + 176:Core/Src/ADBMS_Abstraction.c **** uint8 buffer[CFG_GROUP_A_SIZE]; + 691 .loc 1 176 2 is_stmt 1 view .LVU179 + 177:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); + 692 .loc 1 177 2 view .LVU180 + 693 0006 0622 movs r2, #6 + 694 0008 6946 mov r1, sp + 695 000a 0220 movs r0, #2 + 696 .LVL41: + 697 .loc 1 177 2 is_stmt 0 view .LVU181 + 698 000c FFF7FEFF bl readCMD + 699 .LVL42: + 178:Core/Src/ADBMS_Abstraction.c **** + 179:Core/Src/ADBMS_Abstraction.c **** buffer[1] = (uint8) underVoltage & 0xFF; + 700 .loc 1 179 2 is_stmt 1 view .LVU182 + 701 .loc 1 179 12 is_stmt 0 view .LVU183 + ARM GAS /tmp/ccKQpHxH.s page 16 + + + 702 0010 8DF80140 strb r4, [sp, #1] + 180:Core/Src/ADBMS_Abstraction.c **** uint8 ovuv = buffer[2] & 0xF0; + 703 .loc 1 180 2 is_stmt 1 view .LVU184 + 704 .loc 1 180 21 is_stmt 0 view .LVU185 + 705 0014 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 706 .loc 1 180 8 view .LVU186 + 707 0018 03F0F003 and r3, r3, #240 + 708 .LVL43: + 181:Core/Src/ADBMS_Abstraction.c **** ovuv |= (uint8) (underVoltage >> 8) & 0x0F; + 709 .loc 1 181 2 is_stmt 1 view .LVU187 + 710 .loc 1 181 38 is_stmt 0 view .LVU188 + 711 001c C4F30324 ubfx r4, r4, #8, #4 + 712 .loc 1 181 7 view .LVU189 + 713 0020 2343 orrs r3, r3, r4 + 714 .LVL44: + 182:Core/Src/ADBMS_Abstraction.c **** buffer[2] = ovuv; + 715 .loc 1 182 2 is_stmt 1 view .LVU190 + 716 .loc 1 182 12 is_stmt 0 view .LVU191 + 717 0022 8DF80230 strb r3, [sp, #2] + 183:Core/Src/ADBMS_Abstraction.c **** + 184:Core/Src/ADBMS_Abstraction.c **** writeCMD(WRCFGA, buffer, CFG_GROUP_A_SIZE); + 718 .loc 1 184 2 is_stmt 1 view .LVU192 + 719 0026 0622 movs r2, #6 + 720 0028 6946 mov r1, sp + 721 002a 0120 movs r0, #1 + 722 002c FFF7FEFF bl writeCMD + 723 .LVL45: + 185:Core/Src/ADBMS_Abstraction.c **** + 186:Core/Src/ADBMS_Abstraction.c **** return 0; + 724 .loc 1 186 2 view .LVU193 + 187:Core/Src/ADBMS_Abstraction.c **** } + 725 .loc 1 187 1 is_stmt 0 view .LVU194 + 726 0030 0020 movs r0, #0 + 727 0032 02B0 add sp, sp, #8 + 728 .cfi_def_cfa_offset 8 + 729 @ sp needed + 730 0034 10BD pop {r4, pc} + 731 .cfi_endproc + 732 .LFE144: + 734 .section .text.amsCheckUnderOverVoltage,"ax",%progbits + 735 .align 1 + 736 .global amsCheckUnderOverVoltage + 737 .syntax unified + 738 .thumb + 739 .thumb_func + 741 amsCheckUnderOverVoltage: + 742 .LVL46: + 743 .LFB145: + 188:Core/Src/ADBMS_Abstraction.c **** + 189:Core/Src/ADBMS_Abstraction.c **** uint8 amsCheckUnderOverVoltage(Cell_Module *module) + 190:Core/Src/ADBMS_Abstraction.c **** { + 744 .loc 1 190 1 is_stmt 1 view -0 + 745 .cfi_startproc + 746 @ args = 0, pretend = 0, frame = 8 + 747 @ frame_needed = 0, uses_anonymous_args = 0 + 748 .loc 1 190 1 is_stmt 0 view .LVU196 + 749 0000 10B5 push {r4, lr} + ARM GAS /tmp/ccKQpHxH.s page 17 + + + 750 .cfi_def_cfa_offset 8 + 751 .cfi_offset 4, -8 + 752 .cfi_offset 14, -4 + 753 0002 82B0 sub sp, sp, #8 + 754 .cfi_def_cfa_offset 16 + 755 0004 0446 mov r4, r0 + 191:Core/Src/ADBMS_Abstraction.c **** uint8 regbuffer[STATUS_GROUP_B_SIZE]; + 756 .loc 1 191 2 is_stmt 1 view .LVU197 + 192:Core/Src/ADBMS_Abstraction.c **** uint32 overundervoltages = 0; + 757 .loc 1 192 2 view .LVU198 + 758 .LVL47: + 193:Core/Src/ADBMS_Abstraction.c **** readCMD(RDSTATB, regbuffer, STATUS_GROUP_B_SIZE); + 759 .loc 1 193 2 view .LVU199 + 760 0006 0622 movs r2, #6 + 761 0008 6946 mov r1, sp + 762 000a 1220 movs r0, #18 + 763 .LVL48: + 764 .loc 1 193 2 is_stmt 0 view .LVU200 + 765 000c FFF7FEFF bl readCMD + 766 .LVL49: + 194:Core/Src/ADBMS_Abstraction.c **** overundervoltages = regbuffer[2] | (regbuffer[3]<<8) | (regbuffer[4]<<16); + 767 .loc 1 194 2 is_stmt 1 view .LVU201 + 768 .loc 1 194 31 is_stmt 0 view .LVU202 + 769 0010 9DF802C0 ldrb ip, [sp, #2] @ zero_extendqisi2 + 770 .loc 1 194 47 view .LVU203 + 771 0014 9DF80330 ldrb r3, [sp, #3] @ zero_extendqisi2 + 772 .loc 1 194 35 view .LVU204 + 773 0018 4CEA032C orr ip, ip, r3, lsl #8 + 774 .loc 1 194 67 view .LVU205 + 775 001c 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 776 .loc 1 194 55 view .LVU206 + 777 0020 4CEA034C orr ip, ip, r3, lsl #16 + 778 .LVL50: + 195:Core/Src/ADBMS_Abstraction.c **** module->overVoltage = 0; + 779 .loc 1 195 2 is_stmt 1 view .LVU207 + 780 .loc 1 195 22 is_stmt 0 view .LVU208 + 781 0024 0022 movs r2, #0 + 782 0026 A265 str r2, [r4, #88] + 196:Core/Src/ADBMS_Abstraction.c **** module->underVoltage = 0; + 783 .loc 1 196 2 is_stmt 1 view .LVU209 + 784 .loc 1 196 23 is_stmt 0 view .LVU210 + 785 0028 E265 str r2, [r4, #92] + 197:Core/Src/ADBMS_Abstraction.c **** for(uint8 n = 0; n < 12; n++) + 786 .loc 1 197 2 is_stmt 1 view .LVU211 + 787 .LBB2: + 788 .loc 1 197 6 view .LVU212 + 789 .LVL51: + 790 .loc 1 197 2 is_stmt 0 view .LVU213 + 791 002a 13E0 b .L25 + 792 .LVL52: + 793 .L26: + 794 .LBB3: + 198:Core/Src/ADBMS_Abstraction.c **** { + 199:Core/Src/ADBMS_Abstraction.c **** uint8 overvolt = (overundervoltages>>(2*n+1)) & 0x01; + 795 .loc 1 199 3 is_stmt 1 discriminator 3 view .LVU214 + 796 .loc 1 199 42 is_stmt 0 discriminator 3 view .LVU215 + 797 002c 5300 lsls r3, r2, #1 + ARM GAS /tmp/ccKQpHxH.s page 18 + + + 798 .loc 1 199 44 discriminator 3 view .LVU216 + 799 002e 591C adds r1, r3, #1 + 800 .loc 1 199 38 discriminator 3 view .LVU217 + 801 0030 2CFA01F1 lsr r1, ip, r1 + 802 .loc 1 199 9 discriminator 3 view .LVU218 + 803 0034 01F00101 and r1, r1, #1 + 804 .LVL53: + 200:Core/Src/ADBMS_Abstraction.c **** uint8 undervolt = (overundervoltages>>(2*n))&0x01; + 805 .loc 1 200 3 is_stmt 1 discriminator 3 view .LVU219 + 806 .loc 1 200 39 is_stmt 0 discriminator 3 view .LVU220 + 807 0038 2CFA03F3 lsr r3, ip, r3 + 808 .loc 1 200 9 discriminator 3 view .LVU221 + 809 003c 03F00103 and r3, r3, #1 + 810 .LVL54: + 201:Core/Src/ADBMS_Abstraction.c **** + 202:Core/Src/ADBMS_Abstraction.c **** module->overVoltage |= overvolt<underVoltage |= undervolt<>(2*n+1)) & 0x01; + 869 .loc 1 212 3 discriminator 3 view .LVU244 + 870 .loc 1 212 42 is_stmt 0 discriminator 3 view .LVU245 + 871 0074 4B00 lsls r3, r1, #1 + 872 .loc 1 212 44 discriminator 3 view .LVU246 + 873 0076 5A1C adds r2, r3, #1 + 874 .loc 1 212 38 discriminator 3 view .LVU247 + 875 0078 2CFA02F2 lsr r2, ip, r2 + 876 .loc 1 212 9 discriminator 3 view .LVU248 + 877 007c 02F00102 and r2, r2, #1 + 878 .LVL63: + 213:Core/Src/ADBMS_Abstraction.c **** uint8 undervolt = (overundervoltages>>(2*n))&0x01; + 879 .loc 1 213 3 is_stmt 1 discriminator 3 view .LVU249 + 880 .loc 1 213 39 is_stmt 0 discriminator 3 view .LVU250 + 881 0080 2CFA03F3 lsr r3, ip, r3 + 882 .loc 1 213 9 discriminator 3 view .LVU251 + 883 0084 03F00103 and r3, r3, #1 + 884 .LVL64: + 214:Core/Src/ADBMS_Abstraction.c **** + 215:Core/Src/ADBMS_Abstraction.c **** module->overVoltage |= (uint32) overvolt<<(n+12); + 885 .loc 1 215 3 is_stmt 1 discriminator 3 view .LVU252 + 886 .loc 1 215 9 is_stmt 0 discriminator 3 view .LVU253 + 887 0088 A06D ldr r0, [r4, #88] + 888 .loc 1 215 47 discriminator 3 view .LVU254 + 889 008a 01F10C0E add lr, r1, #12 + 890 .loc 1 215 43 discriminator 3 view .LVU255 + 891 008e 02FA0EF2 lsl r2, r2, lr + 892 .LVL65: + ARM GAS /tmp/ccKQpHxH.s page 20 + + + 893 .loc 1 215 23 discriminator 3 view .LVU256 + 894 0092 1043 orrs r0, r0, r2 + 895 0094 A065 str r0, [r4, #88] + 216:Core/Src/ADBMS_Abstraction.c **** module->underVoltage |= (uint32) undervolt<<(n+12); + 896 .loc 1 216 3 is_stmt 1 discriminator 3 view .LVU257 + 897 .loc 1 216 9 is_stmt 0 discriminator 3 view .LVU258 + 898 0096 E26D ldr r2, [r4, #92] + 899 .loc 1 216 45 discriminator 3 view .LVU259 + 900 0098 03FA0EF3 lsl r3, r3, lr + 901 .LVL66: + 902 .loc 1 216 24 discriminator 3 view .LVU260 + 903 009c 1A43 orrs r2, r2, r3 + 904 009e E265 str r2, [r4, #92] + 905 .LBE5: + 210:Core/Src/ADBMS_Abstraction.c **** { + 906 .loc 1 210 27 is_stmt 1 discriminator 3 view .LVU261 + 907 00a0 0131 adds r1, r1, #1 + 908 .LVL67: + 210:Core/Src/ADBMS_Abstraction.c **** { + 909 .loc 1 210 27 is_stmt 0 discriminator 3 view .LVU262 + 910 00a2 C9B2 uxtb r1, r1 + 911 .LVL68: + 210:Core/Src/ADBMS_Abstraction.c **** { + 912 .loc 1 210 27 discriminator 3 view .LVU263 + 913 00a4 E4E7 b .L27 + 914 .LVL69: + 915 .L30: + 210:Core/Src/ADBMS_Abstraction.c **** { + 916 .loc 1 210 27 discriminator 3 view .LVU264 + 917 .LBE4: + 217:Core/Src/ADBMS_Abstraction.c **** } + 218:Core/Src/ADBMS_Abstraction.c **** + 219:Core/Src/ADBMS_Abstraction.c **** + 220:Core/Src/ADBMS_Abstraction.c **** return 0; + 918 .loc 1 220 2 is_stmt 1 view .LVU265 + 221:Core/Src/ADBMS_Abstraction.c **** } + 919 .loc 1 221 1 is_stmt 0 view .LVU266 + 920 00a6 0020 movs r0, #0 + 921 00a8 02B0 add sp, sp, #8 + 922 .cfi_def_cfa_offset 8 + 923 @ sp needed + 924 00aa 10BD pop {r4, pc} + 925 .loc 1 221 1 view .LVU267 + 926 .cfi_endproc + 927 .LFE145: + 929 .section .text.amsConfigOverVoltage,"ax",%progbits + 930 .align 1 + 931 .global amsConfigOverVoltage + 932 .syntax unified + 933 .thumb + 934 .thumb_func + 936 amsConfigOverVoltage: + 937 .LVL70: + 938 .LFB146: + 222:Core/Src/ADBMS_Abstraction.c **** + 223:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigOverVoltage(uint16 overVoltage) + 224:Core/Src/ADBMS_Abstraction.c **** { + ARM GAS /tmp/ccKQpHxH.s page 21 + + + 939 .loc 1 224 1 is_stmt 1 view -0 + 940 .cfi_startproc + 941 @ args = 0, pretend = 0, frame = 8 + 942 @ frame_needed = 0, uses_anonymous_args = 0 + 943 .loc 1 224 1 is_stmt 0 view .LVU269 + 944 0000 10B5 push {r4, lr} + 945 .cfi_def_cfa_offset 8 + 946 .cfi_offset 4, -8 + 947 .cfi_offset 14, -4 + 948 0002 82B0 sub sp, sp, #8 + 949 .cfi_def_cfa_offset 16 + 950 0004 0446 mov r4, r0 + 225:Core/Src/ADBMS_Abstraction.c **** uint8 buffer[CFG_GROUP_B_SIZE]; + 951 .loc 1 225 2 is_stmt 1 view .LVU270 + 226:Core/Src/ADBMS_Abstraction.c **** + 227:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); + 952 .loc 1 227 2 view .LVU271 + 953 0006 0622 movs r2, #6 + 954 0008 6946 mov r1, sp + 955 000a 0220 movs r0, #2 + 956 .LVL71: + 957 .loc 1 227 2 is_stmt 0 view .LVU272 + 958 000c FFF7FEFF bl readCMD + 959 .LVL72: + 228:Core/Src/ADBMS_Abstraction.c **** buffer[2] &= 0x0F; + 960 .loc 1 228 2 is_stmt 1 view .LVU273 + 961 .loc 1 228 8 is_stmt 0 view .LVU274 + 962 0010 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 963 .loc 1 228 12 view .LVU275 + 964 0014 03F00F03 and r3, r3, #15 + 965 0018 8DF80230 strb r3, [sp, #2] + 229:Core/Src/ADBMS_Abstraction.c **** buffer[2] |= (uint8) overVoltage << 4; + 966 .loc 1 229 2 is_stmt 1 view .LVU276 + 967 .loc 1 229 15 is_stmt 0 view .LVU277 + 968 001c E2B2 uxtb r2, r4 + 969 .loc 1 229 12 view .LVU278 + 970 001e 43EA0213 orr r3, r3, r2, lsl #4 + 971 0022 8DF80230 strb r3, [sp, #2] + 230:Core/Src/ADBMS_Abstraction.c **** buffer[3] = (uint8)(overVoltage>>4); + 972 .loc 1 230 2 is_stmt 1 view .LVU279 + 973 .loc 1 230 14 is_stmt 0 view .LVU280 + 974 0026 C4F30714 ubfx r4, r4, #4, #8 + 975 .loc 1 230 12 view .LVU281 + 976 002a 8DF80340 strb r4, [sp, #3] + 231:Core/Src/ADBMS_Abstraction.c **** + 232:Core/Src/ADBMS_Abstraction.c **** writeCMD(WRCFGA, buffer, CFG_GROUP_A_SIZE); + 977 .loc 1 232 2 is_stmt 1 view .LVU282 + 978 002e 0622 movs r2, #6 + 979 0030 6946 mov r1, sp + 980 0032 0120 movs r0, #1 + 981 0034 FFF7FEFF bl writeCMD + 982 .LVL73: + 233:Core/Src/ADBMS_Abstraction.c **** + 234:Core/Src/ADBMS_Abstraction.c **** return 0; + 983 .loc 1 234 2 view .LVU283 + 235:Core/Src/ADBMS_Abstraction.c **** } + 984 .loc 1 235 1 is_stmt 0 view .LVU284 + ARM GAS /tmp/ccKQpHxH.s page 22 + + + 985 0038 0020 movs r0, #0 + 986 003a 02B0 add sp, sp, #8 + 987 .cfi_def_cfa_offset 8 + 988 @ sp needed + 989 003c 10BD pop {r4, pc} + 990 .cfi_endproc + 991 .LFE146: + 993 .section .text.initAMS,"ax",%progbits + 994 .align 1 + 995 .global initAMS + 996 .syntax unified + 997 .thumb + 998 .thumb_func + 1000 initAMS: + 1001 .LVL74: + 1002 .LFB130: + 16:Core/Src/ADBMS_Abstraction.c **** adbmsDriverInit(hspi); + 1003 .loc 1 16 1 is_stmt 1 view -0 + 1004 .cfi_startproc + 1005 @ args = 0, pretend = 0, frame = 0 + 1006 @ frame_needed = 0, uses_anonymous_args = 0 + 16:Core/Src/ADBMS_Abstraction.c **** adbmsDriverInit(hspi); + 1007 .loc 1 16 1 is_stmt 0 view .LVU286 + 1008 0000 38B5 push {r3, r4, r5, lr} + 1009 .cfi_def_cfa_offset 16 + 1010 .cfi_offset 3, -16 + 1011 .cfi_offset 4, -12 + 1012 .cfi_offset 5, -8 + 1013 .cfi_offset 14, -4 + 1014 0002 0D46 mov r5, r1 + 1015 0004 1446 mov r4, r2 + 17:Core/Src/ADBMS_Abstraction.c **** numberofcells = numofcells; + 1016 .loc 1 17 2 is_stmt 1 view .LVU287 + 1017 0006 FFF7FEFF bl adbmsDriverInit + 1018 .LVL75: + 18:Core/Src/ADBMS_Abstraction.c **** numberofauxchannels = numofaux; + 1019 .loc 1 18 2 view .LVU288 + 18:Core/Src/ADBMS_Abstraction.c **** numberofauxchannels = numofaux; + 1020 .loc 1 18 16 is_stmt 0 view .LVU289 + 1021 000a 0B4B ldr r3, .L35 + 1022 000c 1D70 strb r5, [r3] + 19:Core/Src/ADBMS_Abstraction.c **** + 1023 .loc 1 19 2 is_stmt 1 view .LVU290 + 19:Core/Src/ADBMS_Abstraction.c **** + 1024 .loc 1 19 22 is_stmt 0 view .LVU291 + 1025 000e 0B4B ldr r3, .L35+4 + 1026 0010 1C70 strb r4, [r3] + 22:Core/Src/ADBMS_Abstraction.c **** amsStopBalancing(); + 1027 .loc 1 22 2 is_stmt 1 view .LVU292 + 1028 0012 FFF7FEFF bl amsWakeUp + 1029 .LVL76: + 23:Core/Src/ADBMS_Abstraction.c **** amsConfigOverVoltage(DEFAULT_OV); + 1030 .loc 1 23 2 view .LVU293 + 1031 0016 FFF7FEFF bl amsStopBalancing + 1032 .LVL77: + 24:Core/Src/ADBMS_Abstraction.c **** amsConfigUnderVoltage(DEFAULT_UV); + 1033 .loc 1 24 2 view .LVU294 + ARM GAS /tmp/ccKQpHxH.s page 23 + + + 1034 001a 40F64120 movw r0, #2625 + 1035 001e FFF7FEFF bl amsConfigOverVoltage + 1036 .LVL78: + 25:Core/Src/ADBMS_Abstraction.c **** amsConfigAuxMeasurement(0xFFFF); + 1037 .loc 1 25 2 view .LVU295 + 1038 0022 40F21A60 movw r0, #1562 + 1039 0026 FFF7FEFF bl amsConfigUnderVoltage + 1040 .LVL79: + 26:Core/Src/ADBMS_Abstraction.c **** + 1041 .loc 1 26 2 view .LVU296 + 1042 002a 4FF6FF70 movw r0, #65535 + 1043 002e FFF7FEFF bl amsConfigAuxMeasurement + 1044 .LVL80: + 28:Core/Src/ADBMS_Abstraction.c **** } + 1045 .loc 1 28 2 view .LVU297 + 29:Core/Src/ADBMS_Abstraction.c **** + 1046 .loc 1 29 1 is_stmt 0 view .LVU298 + 1047 0032 0020 movs r0, #0 + 1048 0034 38BD pop {r3, r4, r5, pc} + 1049 .L36: + 1050 0036 00BF .align 2 + 1051 .L35: + 1052 0038 00000000 .word numberofcells + 1053 003c 00000000 .word numberofauxchannels + 1054 .cfi_endproc + 1055 .LFE130: + 1057 .section .text.amsClearStatus,"ax",%progbits + 1058 .align 1 + 1059 .global amsClearStatus + 1060 .syntax unified + 1061 .thumb + 1062 .thumb_func + 1064 amsClearStatus: + 1065 .LFB147: + 236:Core/Src/ADBMS_Abstraction.c **** + 237:Core/Src/ADBMS_Abstraction.c **** /* + 238:Core/Src/ADBMS_Abstraction.c **** void dumpRegister(UART_HandleTypeDef *huart, uint8 RegID, uint8* buffer) + 239:Core/Src/ADBMS_Abstraction.c **** { + 240:Core/Src/ADBMS_Abstraction.c **** switch(RegID) + 241:Core/Src/ADBMS_Abstraction.c **** { + 242:Core/Src/ADBMS_Abstraction.c **** case CFG_GROUP_A_ID: + 243:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGA, buffer, CFG_GROUP_A_SIZE); + 244:Core/Src/ADBMS_Abstraction.c **** break; + 245:Core/Src/ADBMS_Abstraction.c **** case CFG_GROUP_B_ID: + 246:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCFGB, buffer, CFG_GROUP_A_SIZE); + 247:Core/Src/ADBMS_Abstraction.c **** break; + 248:Core/Src/ADBMS_Abstraction.c **** case CV_GROUP_A_ID: + 249:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVA, buffer, CFG_GROUP_A_SIZE); + 250:Core/Src/ADBMS_Abstraction.c **** break; + 251:Core/Src/ADBMS_Abstraction.c **** case CV_GROUP_B_ID: + 252:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVB, buffer, CFG_GROUP_A_SIZE); + 253:Core/Src/ADBMS_Abstraction.c **** break; + 254:Core/Src/ADBMS_Abstraction.c **** case CV_GROUP_C_ID: + 255:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVC, buffer, CFG_GROUP_A_SIZE); + 256:Core/Src/ADBMS_Abstraction.c **** break; + 257:Core/Src/ADBMS_Abstraction.c **** case CV_GROUP_D_ID: + 258:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVD, buffer, CFG_GROUP_A_SIZE); + ARM GAS /tmp/ccKQpHxH.s page 24 + + + 259:Core/Src/ADBMS_Abstraction.c **** break; + 260:Core/Src/ADBMS_Abstraction.c **** case CV_GROUP_E_ID: + 261:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVE, buffer, CFG_GROUP_A_SIZE); + 262:Core/Src/ADBMS_Abstraction.c **** break; + 263:Core/Src/ADBMS_Abstraction.c **** case CV_GROUP_F_ID: + 264:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVF, buffer, CFG_GROUP_A_SIZE); + 265:Core/Src/ADBMS_Abstraction.c **** break; + 266:Core/Src/ADBMS_Abstraction.c **** case AUX_GROUP_A_ID: + 267:Core/Src/ADBMS_Abstraction.c **** readCMD(RDAUXA, buffer, CFG_GROUP_A_SIZE); + 268:Core/Src/ADBMS_Abstraction.c **** break; + 269:Core/Src/ADBMS_Abstraction.c **** case AUX_GROUP_B_ID: + 270:Core/Src/ADBMS_Abstraction.c **** readCMD(RDAUXB, buffer, CFG_GROUP_A_SIZE); + 271:Core/Src/ADBMS_Abstraction.c **** break; + 272:Core/Src/ADBMS_Abstraction.c **** case AUX_GROUP_C_ID: + 273:Core/Src/ADBMS_Abstraction.c **** readCMD(RDAUXC, buffer, CFG_GROUP_A_SIZE); + 274:Core/Src/ADBMS_Abstraction.c **** break; + 275:Core/Src/ADBMS_Abstraction.c **** case AUX_GROUP_D_ID: + 276:Core/Src/ADBMS_Abstraction.c **** readCMD(RDAUXD, buffer, CFG_GROUP_A_SIZE); + 277:Core/Src/ADBMS_Abstraction.c **** break; + 278:Core/Src/ADBMS_Abstraction.c **** case STATUS_GROUP_A_ID: + 279:Core/Src/ADBMS_Abstraction.c **** readCMD(RDSTATA, buffer, CFG_GROUP_A_SIZE); + 280:Core/Src/ADBMS_Abstraction.c **** break; + 281:Core/Src/ADBMS_Abstraction.c **** case STATUS_GROUP_B_ID: + 282:Core/Src/ADBMS_Abstraction.c **** readCMD(RDSTATB, buffer, CFG_GROUP_A_SIZE); + 283:Core/Src/ADBMS_Abstraction.c **** break; + 284:Core/Src/ADBMS_Abstraction.c **** case COMM_GROUP_ID: + 285:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCOMM, buffer, CFG_GROUP_A_SIZE); + 286:Core/Src/ADBMS_Abstraction.c **** break; + 287:Core/Src/ADBMS_Abstraction.c **** case S_CONTROL_GROUP_ID: + 288:Core/Src/ADBMS_Abstraction.c **** readCMD(RDSCTRL, buffer, CFG_GROUP_A_SIZE); + 289:Core/Src/ADBMS_Abstraction.c **** break; + 290:Core/Src/ADBMS_Abstraction.c **** case PWM_GROUP_ID: + 291:Core/Src/ADBMS_Abstraction.c **** readCMD(RDPWM, buffer, CFG_GROUP_A_SIZE); + 292:Core/Src/ADBMS_Abstraction.c **** break; + 293:Core/Src/ADBMS_Abstraction.c **** case PWM_S_CONTROL_GROUP_B_ID: + 294:Core/Src/ADBMS_Abstraction.c **** readCMD(RDPSB, buffer, CFG_GROUP_A_SIZE); + 295:Core/Src/ADBMS_Abstraction.c **** break; + 296:Core/Src/ADBMS_Abstraction.c **** } + 297:Core/Src/ADBMS_Abstraction.c **** } + 298:Core/Src/ADBMS_Abstraction.c **** */ + 299:Core/Src/ADBMS_Abstraction.c **** + 300:Core/Src/ADBMS_Abstraction.c **** uint8 amsClearStatus() + 301:Core/Src/ADBMS_Abstraction.c **** { + 1066 .loc 1 301 1 is_stmt 1 view -0 + 1067 .cfi_startproc + 1068 @ args = 0, pretend = 0, frame = 8 + 1069 @ frame_needed = 0, uses_anonymous_args = 0 + 1070 0000 00B5 push {lr} + 1071 .cfi_def_cfa_offset 4 + 1072 .cfi_offset 14, -4 + 1073 0002 83B0 sub sp, sp, #12 + 1074 .cfi_def_cfa_offset 16 + 302:Core/Src/ADBMS_Abstraction.c **** uint8 buffer[6]; + 1075 .loc 1 302 2 view .LVU300 + 303:Core/Src/ADBMS_Abstraction.c **** writeCMD(CLRSTAT, buffer, 0); + 1076 .loc 1 303 2 view .LVU301 + 1077 0004 0022 movs r2, #0 + ARM GAS /tmp/ccKQpHxH.s page 25 + + + 1078 0006 6946 mov r1, sp + 1079 0008 40F21370 movw r0, #1811 + 1080 000c FFF7FEFF bl writeCMD + 1081 .LVL81: + 304:Core/Src/ADBMS_Abstraction.c **** return 0; + 1082 .loc 1 304 2 view .LVU302 + 305:Core/Src/ADBMS_Abstraction.c **** } + 1083 .loc 1 305 1 is_stmt 0 view .LVU303 + 1084 0010 0020 movs r0, #0 + 1085 0012 03B0 add sp, sp, #12 + 1086 .cfi_def_cfa_offset 4 + 1087 @ sp needed + 1088 0014 5DF804FB ldr pc, [sp], #4 + 1089 .cfi_endproc + 1090 .LFE147: + 1092 .section .text.amsClearAux,"ax",%progbits + 1093 .align 1 + 1094 .global amsClearAux + 1095 .syntax unified + 1096 .thumb + 1097 .thumb_func + 1099 amsClearAux: + 1100 .LFB148: + 306:Core/Src/ADBMS_Abstraction.c **** uint8 amsClearAux() + 307:Core/Src/ADBMS_Abstraction.c **** { + 1101 .loc 1 307 1 is_stmt 1 view -0 + 1102 .cfi_startproc + 1103 @ args = 0, pretend = 0, frame = 8 + 1104 @ frame_needed = 0, uses_anonymous_args = 0 + 1105 0000 00B5 push {lr} + 1106 .cfi_def_cfa_offset 4 + 1107 .cfi_offset 14, -4 + 1108 0002 83B0 sub sp, sp, #12 + 1109 .cfi_def_cfa_offset 16 + 308:Core/Src/ADBMS_Abstraction.c **** uint8 buffer[6]; + 1110 .loc 1 308 2 view .LVU305 + 309:Core/Src/ADBMS_Abstraction.c **** writeCMD(CLRAUX, buffer, 0); + 1111 .loc 1 309 2 view .LVU306 + 1112 0004 0022 movs r2, #0 + 1113 0006 6946 mov r1, sp + 1114 0008 40F21270 movw r0, #1810 + 1115 000c FFF7FEFF bl writeCMD + 1116 .LVL82: + 310:Core/Src/ADBMS_Abstraction.c **** return 0; + 1117 .loc 1 310 2 view .LVU307 + 311:Core/Src/ADBMS_Abstraction.c **** } + 1118 .loc 1 311 1 is_stmt 0 view .LVU308 + 1119 0010 0020 movs r0, #0 + 1120 0012 03B0 add sp, sp, #12 + 1121 .cfi_def_cfa_offset 4 + 1122 @ sp needed + 1123 0014 5DF804FB ldr pc, [sp], #4 + 1124 .cfi_endproc + 1125 .LFE148: + 1127 .section .text.amsClearCells,"ax",%progbits + 1128 .align 1 + 1129 .global amsClearCells + ARM GAS /tmp/ccKQpHxH.s page 26 + + + 1130 .syntax unified + 1131 .thumb + 1132 .thumb_func + 1134 amsClearCells: + 1135 .LFB149: + 312:Core/Src/ADBMS_Abstraction.c **** uint8 amsClearCells() + 313:Core/Src/ADBMS_Abstraction.c **** { + 1136 .loc 1 313 1 is_stmt 1 view -0 + 1137 .cfi_startproc + 1138 @ args = 0, pretend = 0, frame = 8 + 1139 @ frame_needed = 0, uses_anonymous_args = 0 + 1140 0000 00B5 push {lr} + 1141 .cfi_def_cfa_offset 4 + 1142 .cfi_offset 14, -4 + 1143 0002 83B0 sub sp, sp, #12 + 1144 .cfi_def_cfa_offset 16 + 314:Core/Src/ADBMS_Abstraction.c **** uint8 buffer[6]; + 1145 .loc 1 314 2 view .LVU310 + 315:Core/Src/ADBMS_Abstraction.c **** writeCMD(CLRCELL, buffer, 0); + 1146 .loc 1 315 2 view .LVU311 + 1147 0004 0022 movs r2, #0 + 1148 0006 6946 mov r1, sp + 1149 0008 40F21170 movw r0, #1809 + 1150 000c FFF7FEFF bl writeCMD + 1151 .LVL83: + 316:Core/Src/ADBMS_Abstraction.c **** return 0; + 1152 .loc 1 316 2 view .LVU312 + 317:Core/Src/ADBMS_Abstraction.c **** } + 1153 .loc 1 317 1 is_stmt 0 view .LVU313 + 1154 0010 0020 movs r0, #0 + 1155 0012 03B0 add sp, sp, #12 + 1156 .cfi_def_cfa_offset 4 + 1157 @ sp needed + 1158 0014 5DF804FB ldr pc, [sp], #4 + 1159 .cfi_endproc + 1160 .LFE149: + 1162 .section .text.amsSendWarning,"ax",%progbits + 1163 .align 1 + 1164 .global amsSendWarning + 1165 .syntax unified + 1166 .thumb + 1167 .thumb_func + 1169 amsSendWarning: + 1170 .LFB150: + 318:Core/Src/ADBMS_Abstraction.c **** + 319:Core/Src/ADBMS_Abstraction.c **** uint8 amsSendWarning() + 320:Core/Src/ADBMS_Abstraction.c **** { + 1171 .loc 1 320 1 is_stmt 1 view -0 + 1172 .cfi_startproc + 1173 @ args = 0, pretend = 0, frame = 0 + 1174 @ frame_needed = 0, uses_anonymous_args = 0 + 1175 @ link register save eliminated. + 321:Core/Src/ADBMS_Abstraction.c **** //HAL_GPIO_WritePin(AMS_Warning_GPIO_Port, AMS_Warning_Pin, GPIO_PIN_SET); + 322:Core/Src/ADBMS_Abstraction.c **** return 0; + 1176 .loc 1 322 2 view .LVU315 + 323:Core/Src/ADBMS_Abstraction.c **** } + 1177 .loc 1 323 1 is_stmt 0 view .LVU316 + ARM GAS /tmp/ccKQpHxH.s page 27 + + + 1178 0000 0020 movs r0, #0 + 1179 0002 7047 bx lr + 1180 .cfi_endproc + 1181 .LFE150: + 1183 .section .text.amsSendError,"ax",%progbits + 1184 .align 1 + 1185 .global amsSendError + 1186 .syntax unified + 1187 .thumb + 1188 .thumb_func + 1190 amsSendError: + 1191 .LFB151: + 324:Core/Src/ADBMS_Abstraction.c **** + 325:Core/Src/ADBMS_Abstraction.c **** uint8 amsSendError() + 326:Core/Src/ADBMS_Abstraction.c **** { + 1192 .loc 1 326 1 is_stmt 1 view -0 + 1193 .cfi_startproc + 1194 @ args = 0, pretend = 0, frame = 0 + 1195 @ frame_needed = 0, uses_anonymous_args = 0 + 1196 @ link register save eliminated. + 327:Core/Src/ADBMS_Abstraction.c **** //HAL_GPIO_WritePin(AMS_Error_GPIO_Port, AMS_Error_Pin, GPIO_PIN_SET); + 328:Core/Src/ADBMS_Abstraction.c **** return 0; + 1197 .loc 1 328 2 view .LVU318 + 329:Core/Src/ADBMS_Abstraction.c **** } + 1198 .loc 1 329 1 is_stmt 0 view .LVU319 + 1199 0000 0020 movs r0, #0 + 1200 0002 7047 bx lr + 1201 .cfi_endproc + 1202 .LFE151: + 1204 .section .text.amsClearWarning,"ax",%progbits + 1205 .align 1 + 1206 .global amsClearWarning + 1207 .syntax unified + 1208 .thumb + 1209 .thumb_func + 1211 amsClearWarning: + 1212 .LFB152: + 330:Core/Src/ADBMS_Abstraction.c **** + 331:Core/Src/ADBMS_Abstraction.c **** uint8 amsClearWarning() + 332:Core/Src/ADBMS_Abstraction.c **** { + 1213 .loc 1 332 1 is_stmt 1 view -0 + 1214 .cfi_startproc + 1215 @ args = 0, pretend = 0, frame = 0 + 1216 @ frame_needed = 0, uses_anonymous_args = 0 + 1217 @ link register save eliminated. + 333:Core/Src/ADBMS_Abstraction.c **** //HAL_GPIO_WritePin(AMS_Warning_GPIO_Port, AMS_Warning_Pin, GPIO_PIN_RESET); + 334:Core/Src/ADBMS_Abstraction.c **** return 0; + 1218 .loc 1 334 2 view .LVU321 + 335:Core/Src/ADBMS_Abstraction.c **** } + 1219 .loc 1 335 1 is_stmt 0 view .LVU322 + 1220 0000 0020 movs r0, #0 + 1221 0002 7047 bx lr + 1222 .cfi_endproc + 1223 .LFE152: + 1225 .section .text.amsClearError,"ax",%progbits + 1226 .align 1 + 1227 .global amsClearError + ARM GAS /tmp/ccKQpHxH.s page 28 + + + 1228 .syntax unified + 1229 .thumb + 1230 .thumb_func + 1232 amsClearError: + 1233 .LFB153: + 336:Core/Src/ADBMS_Abstraction.c **** + 337:Core/Src/ADBMS_Abstraction.c **** uint8 amsClearError() + 338:Core/Src/ADBMS_Abstraction.c **** { + 1234 .loc 1 338 1 is_stmt 1 view -0 + 1235 .cfi_startproc + 1236 @ args = 0, pretend = 0, frame = 0 + 1237 @ frame_needed = 0, uses_anonymous_args = 0 + 1238 @ link register save eliminated. + 339:Core/Src/ADBMS_Abstraction.c **** //HAL_GPIO_WritePin(AMS_Error_GPIO_Port, AMS_Error_Pin, GPIO_PIN_RESET); + 340:Core/Src/ADBMS_Abstraction.c **** return 0; + 1239 .loc 1 340 2 view .LVU324 + 341:Core/Src/ADBMS_Abstraction.c **** } + 1240 .loc 1 341 1 is_stmt 0 view .LVU325 + 1241 0000 0020 movs r0, #0 + 1242 0002 7047 bx lr + 1243 .cfi_endproc + 1244 .LFE153: + 1246 .section .text.amsReadCellVoltages,"ax",%progbits + 1247 .align 1 + 1248 .global amsReadCellVoltages + 1249 .syntax unified + 1250 .thumb + 1251 .thumb_func + 1253 amsReadCellVoltages: + 1254 .LVL84: + 1255 .LFB155: + 342:Core/Src/ADBMS_Abstraction.c **** + 343:Core/Src/ADBMS_Abstraction.c **** uint8 amscheckOpenCellWire(Cell_Module *module) + 344:Core/Src/ADBMS_Abstraction.c **** { + 345:Core/Src/ADBMS_Abstraction.c **** uint8 args; + 346:Core/Src/ADBMS_Abstraction.c **** uint16 cellspu[18]; + 347:Core/Src/ADBMS_Abstraction.c **** + 348:Core/Src/ADBMS_Abstraction.c **** writeCMD(ADOW |MD01|CH000|PUP , &args, 0); //run Pull Up at least Twice + 349:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 350:Core/Src/ADBMS_Abstraction.c **** writeCMD(ADOW |MD01|CH000|PUP , &args, 0); //run Pull Up at least Twice + 351:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 352:Core/Src/ADBMS_Abstraction.c **** + 353:Core/Src/ADBMS_Abstraction.c **** amsReadCellVoltages(module); + 354:Core/Src/ADBMS_Abstraction.c **** + 355:Core/Src/ADBMS_Abstraction.c **** for(uint8_t n = 0; n cellVoltages[n]; + 358:Core/Src/ADBMS_Abstraction.c **** } + 359:Core/Src/ADBMS_Abstraction.c **** + 360:Core/Src/ADBMS_Abstraction.c **** + 361:Core/Src/ADBMS_Abstraction.c **** writeCMD(ADOW |MD01|CH000, &args, 0); //run Pull Up at least Twice + 362:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 363:Core/Src/ADBMS_Abstraction.c **** writeCMD(ADOW |MD01|CH000, &args, 0); //run Pull Up at least Twice + 364:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 365:Core/Src/ADBMS_Abstraction.c **** + 366:Core/Src/ADBMS_Abstraction.c **** amsReadCellVoltages(module); + 367:Core/Src/ADBMS_Abstraction.c **** + ARM GAS /tmp/ccKQpHxH.s page 29 + + + 368:Core/Src/ADBMS_Abstraction.c **** for(uint8 n = 1; n < numberofcells; n++) + 369:Core/Src/ADBMS_Abstraction.c **** { + 370:Core/Src/ADBMS_Abstraction.c **** int dv = cellspu[n]-module->cellVoltages[n]; + 371:Core/Src/ADBMS_Abstraction.c **** if(dv < -4000) + 372:Core/Src/ADBMS_Abstraction.c **** { + 373:Core/Src/ADBMS_Abstraction.c **** return (1+n); + 374:Core/Src/ADBMS_Abstraction.c **** } + 375:Core/Src/ADBMS_Abstraction.c **** } + 376:Core/Src/ADBMS_Abstraction.c **** if((cellspu[0] == 0) || (cellspu[0] == 0xFFFF)) + 377:Core/Src/ADBMS_Abstraction.c **** { + 378:Core/Src/ADBMS_Abstraction.c **** return 1; + 379:Core/Src/ADBMS_Abstraction.c **** } + 380:Core/Src/ADBMS_Abstraction.c **** if(module->cellVoltages[numberofcells-1] == 0) + 381:Core/Src/ADBMS_Abstraction.c **** { + 382:Core/Src/ADBMS_Abstraction.c **** return 19; + 383:Core/Src/ADBMS_Abstraction.c **** } + 384:Core/Src/ADBMS_Abstraction.c **** + 385:Core/Src/ADBMS_Abstraction.c **** return 0; + 386:Core/Src/ADBMS_Abstraction.c **** } + 387:Core/Src/ADBMS_Abstraction.c **** + 388:Core/Src/ADBMS_Abstraction.c **** uint8 amsReadCellVoltages(Cell_Module *module) + 389:Core/Src/ADBMS_Abstraction.c **** { + 1256 .loc 1 389 1 is_stmt 1 view -0 + 1257 .cfi_startproc + 1258 @ args = 0, pretend = 0, frame = 8 + 1259 @ frame_needed = 0, uses_anonymous_args = 0 + 1260 .loc 1 389 1 is_stmt 0 view .LVU327 + 1261 0000 10B5 push {r4, lr} + 1262 .cfi_def_cfa_offset 8 + 1263 .cfi_offset 4, -8 + 1264 .cfi_offset 14, -4 + 1265 0002 82B0 sub sp, sp, #8 + 1266 .cfi_def_cfa_offset 16 + 1267 0004 0446 mov r4, r0 + 390:Core/Src/ADBMS_Abstraction.c **** uint8 rxbuffer[CV_GROUP_A_SIZE]; + 1268 .loc 1 390 2 is_stmt 1 view .LVU328 + 391:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVA, rxbuffer, CV_GROUP_A_SIZE); + 1269 .loc 1 391 2 view .LVU329 + 1270 0006 0622 movs r2, #6 + 1271 0008 6946 mov r1, sp + 1272 000a 0420 movs r0, #4 + 1273 .LVL85: + 1274 .loc 1 391 2 is_stmt 0 view .LVU330 + 1275 000c FFF7FEFF bl readCMD + 1276 .LVL86: + 392:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[0] = rxbuffer[0] | (rxbuffer[1]<<8); + 1277 .loc 1 392 2 is_stmt 1 view .LVU331 + 1278 .loc 1 392 36 is_stmt 0 view .LVU332 + 1279 0010 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 1280 .loc 1 392 51 view .LVU333 + 1281 0014 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 1282 .loc 1 392 40 view .LVU334 + 1283 0018 43EA0223 orr r3, r3, r2, lsl #8 + 1284 .loc 1 392 26 view .LVU335 + 1285 001c 2380 strh r3, [r4] @ movhi + 393:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[1] = rxbuffer[2] | (rxbuffer[3]<<8); + 1286 .loc 1 393 2 is_stmt 1 view .LVU336 + ARM GAS /tmp/ccKQpHxH.s page 30 + + + 1287 .loc 1 393 36 is_stmt 0 view .LVU337 + 1288 001e 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 1289 .loc 1 393 51 view .LVU338 + 1290 0022 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 1291 .loc 1 393 40 view .LVU339 + 1292 0026 43EA0223 orr r3, r3, r2, lsl #8 + 1293 .loc 1 393 26 view .LVU340 + 1294 002a 6380 strh r3, [r4, #2] @ movhi + 394:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[2] = rxbuffer[4] | (rxbuffer[5]<<8); + 1295 .loc 1 394 2 is_stmt 1 view .LVU341 + 1296 .loc 1 394 36 is_stmt 0 view .LVU342 + 1297 002c 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 1298 .loc 1 394 51 view .LVU343 + 1299 0030 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 1300 .loc 1 394 40 view .LVU344 + 1301 0034 43EA0223 orr r3, r3, r2, lsl #8 + 1302 .loc 1 394 26 view .LVU345 + 1303 0038 A380 strh r3, [r4, #4] @ movhi + 395:Core/Src/ADBMS_Abstraction.c **** + 396:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVB, rxbuffer, CV_GROUP_A_SIZE); + 1304 .loc 1 396 2 is_stmt 1 view .LVU346 + 1305 003a 0622 movs r2, #6 + 1306 003c 6946 mov r1, sp + 1307 003e 1046 mov r0, r2 + 1308 0040 FFF7FEFF bl readCMD + 1309 .LVL87: + 397:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[3] = rxbuffer[0] | (rxbuffer[1]<<8); + 1310 .loc 1 397 2 view .LVU347 + 1311 .loc 1 397 36 is_stmt 0 view .LVU348 + 1312 0044 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 1313 .loc 1 397 51 view .LVU349 + 1314 0048 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 1315 .loc 1 397 40 view .LVU350 + 1316 004c 43EA0223 orr r3, r3, r2, lsl #8 + 1317 .loc 1 397 26 view .LVU351 + 1318 0050 E380 strh r3, [r4, #6] @ movhi + 398:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[4] = rxbuffer[2] | (rxbuffer[3]<<8); + 1319 .loc 1 398 2 is_stmt 1 view .LVU352 + 1320 .loc 1 398 36 is_stmt 0 view .LVU353 + 1321 0052 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 1322 .loc 1 398 51 view .LVU354 + 1323 0056 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 1324 .loc 1 398 40 view .LVU355 + 1325 005a 43EA0223 orr r3, r3, r2, lsl #8 + 1326 .loc 1 398 26 view .LVU356 + 1327 005e 2381 strh r3, [r4, #8] @ movhi + 399:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[5] = rxbuffer[4] | (rxbuffer[5]<<8); + 1328 .loc 1 399 2 is_stmt 1 view .LVU357 + 1329 .loc 1 399 36 is_stmt 0 view .LVU358 + 1330 0060 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 1331 .loc 1 399 51 view .LVU359 + 1332 0064 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 1333 .loc 1 399 40 view .LVU360 + 1334 0068 43EA0223 orr r3, r3, r2, lsl #8 + 1335 .loc 1 399 26 view .LVU361 + 1336 006c 6381 strh r3, [r4, #10] @ movhi + 400:Core/Src/ADBMS_Abstraction.c **** + ARM GAS /tmp/ccKQpHxH.s page 31 + + + 401:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVC, rxbuffer, CV_GROUP_A_SIZE); + 1337 .loc 1 401 2 is_stmt 1 view .LVU362 + 1338 006e 0622 movs r2, #6 + 1339 0070 6946 mov r1, sp + 1340 0072 0820 movs r0, #8 + 1341 0074 FFF7FEFF bl readCMD + 1342 .LVL88: + 402:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[6] = rxbuffer[0] | (rxbuffer[1]<<8); + 1343 .loc 1 402 2 view .LVU363 + 1344 .loc 1 402 36 is_stmt 0 view .LVU364 + 1345 0078 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 1346 .loc 1 402 51 view .LVU365 + 1347 007c 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 1348 .loc 1 402 40 view .LVU366 + 1349 0080 43EA0223 orr r3, r3, r2, lsl #8 + 1350 .loc 1 402 26 view .LVU367 + 1351 0084 A381 strh r3, [r4, #12] @ movhi + 403:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[7] = rxbuffer[2] | (rxbuffer[3]<<8); + 1352 .loc 1 403 2 is_stmt 1 view .LVU368 + 1353 .loc 1 403 36 is_stmt 0 view .LVU369 + 1354 0086 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 1355 .loc 1 403 51 view .LVU370 + 1356 008a 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 1357 .loc 1 403 40 view .LVU371 + 1358 008e 43EA0223 orr r3, r3, r2, lsl #8 + 1359 .loc 1 403 26 view .LVU372 + 1360 0092 E381 strh r3, [r4, #14] @ movhi + 404:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[8] = rxbuffer[4] | (rxbuffer[5]<<8); + 1361 .loc 1 404 2 is_stmt 1 view .LVU373 + 1362 .loc 1 404 36 is_stmt 0 view .LVU374 + 1363 0094 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 1364 .loc 1 404 51 view .LVU375 + 1365 0098 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 1366 .loc 1 404 40 view .LVU376 + 1367 009c 43EA0223 orr r3, r3, r2, lsl #8 + 1368 .loc 1 404 26 view .LVU377 + 1369 00a0 2382 strh r3, [r4, #16] @ movhi + 405:Core/Src/ADBMS_Abstraction.c **** + 406:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVD, rxbuffer, CV_GROUP_A_SIZE); + 1370 .loc 1 406 2 is_stmt 1 view .LVU378 + 1371 00a2 0622 movs r2, #6 + 1372 00a4 6946 mov r1, sp + 1373 00a6 0A20 movs r0, #10 + 1374 00a8 FFF7FEFF bl readCMD + 1375 .LVL89: + 407:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[9] = rxbuffer[0] | (rxbuffer[1]<<8); + 1376 .loc 1 407 2 view .LVU379 + 1377 .loc 1 407 36 is_stmt 0 view .LVU380 + 1378 00ac 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 1379 .loc 1 407 51 view .LVU381 + 1380 00b0 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 1381 .loc 1 407 40 view .LVU382 + 1382 00b4 43EA0223 orr r3, r3, r2, lsl #8 + 1383 .loc 1 407 26 view .LVU383 + 1384 00b8 6382 strh r3, [r4, #18] @ movhi + 408:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[10] = rxbuffer[2] | (rxbuffer[3]<<8); + 1385 .loc 1 408 2 is_stmt 1 view .LVU384 + ARM GAS /tmp/ccKQpHxH.s page 32 + + + 1386 .loc 1 408 37 is_stmt 0 view .LVU385 + 1387 00ba 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 1388 .loc 1 408 52 view .LVU386 + 1389 00be 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 1390 .loc 1 408 41 view .LVU387 + 1391 00c2 43EA0223 orr r3, r3, r2, lsl #8 + 1392 .loc 1 408 27 view .LVU388 + 1393 00c6 A382 strh r3, [r4, #20] @ movhi + 409:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[11] = rxbuffer[4] | (rxbuffer[5]<<8); + 1394 .loc 1 409 2 is_stmt 1 view .LVU389 + 1395 .loc 1 409 37 is_stmt 0 view .LVU390 + 1396 00c8 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 1397 .loc 1 409 52 view .LVU391 + 1398 00cc 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 1399 .loc 1 409 41 view .LVU392 + 1400 00d0 43EA0223 orr r3, r3, r2, lsl #8 + 1401 .loc 1 409 27 view .LVU393 + 1402 00d4 E382 strh r3, [r4, #22] @ movhi + 410:Core/Src/ADBMS_Abstraction.c **** + 411:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVE, rxbuffer, CV_GROUP_A_SIZE); + 1403 .loc 1 411 2 is_stmt 1 view .LVU394 + 1404 00d6 0622 movs r2, #6 + 1405 00d8 6946 mov r1, sp + 1406 00da 0920 movs r0, #9 + 1407 00dc FFF7FEFF bl readCMD + 1408 .LVL90: + 412:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[12] = rxbuffer[0] | (rxbuffer[1]<<8); + 1409 .loc 1 412 2 view .LVU395 + 1410 .loc 1 412 37 is_stmt 0 view .LVU396 + 1411 00e0 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 1412 .loc 1 412 52 view .LVU397 + 1413 00e4 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 1414 .loc 1 412 41 view .LVU398 + 1415 00e8 43EA0223 orr r3, r3, r2, lsl #8 + 1416 .loc 1 412 27 view .LVU399 + 1417 00ec 2383 strh r3, [r4, #24] @ movhi + 413:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[13] = rxbuffer[2] | (rxbuffer[3]<<8); + 1418 .loc 1 413 2 is_stmt 1 view .LVU400 + 1419 .loc 1 413 37 is_stmt 0 view .LVU401 + 1420 00ee 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 1421 .loc 1 413 52 view .LVU402 + 1422 00f2 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 1423 .loc 1 413 41 view .LVU403 + 1424 00f6 43EA0223 orr r3, r3, r2, lsl #8 + 1425 .loc 1 413 27 view .LVU404 + 1426 00fa 6383 strh r3, [r4, #26] @ movhi + 414:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[14] = rxbuffer[4] | (rxbuffer[5]<<8); + 1427 .loc 1 414 2 is_stmt 1 view .LVU405 + 1428 .loc 1 414 37 is_stmt 0 view .LVU406 + 1429 00fc 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 1430 .loc 1 414 52 view .LVU407 + 1431 0100 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 1432 .loc 1 414 41 view .LVU408 + 1433 0104 43EA0223 orr r3, r3, r2, lsl #8 + 1434 .loc 1 414 27 view .LVU409 + 1435 0108 A383 strh r3, [r4, #28] @ movhi + 415:Core/Src/ADBMS_Abstraction.c **** + ARM GAS /tmp/ccKQpHxH.s page 33 + + + 416:Core/Src/ADBMS_Abstraction.c **** readCMD(RDCVF, rxbuffer, CV_GROUP_A_SIZE); + 1436 .loc 1 416 2 is_stmt 1 view .LVU410 + 1437 010a 0622 movs r2, #6 + 1438 010c 6946 mov r1, sp + 1439 010e 0B20 movs r0, #11 + 1440 0110 FFF7FEFF bl readCMD + 1441 .LVL91: + 417:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[15] = rxbuffer[0] | (rxbuffer[1]<<8); + 1442 .loc 1 417 2 view .LVU411 + 1443 .loc 1 417 37 is_stmt 0 view .LVU412 + 1444 0114 9DF80030 ldrb r3, [sp] @ zero_extendqisi2 + 1445 .loc 1 417 52 view .LVU413 + 1446 0118 9DF80120 ldrb r2, [sp, #1] @ zero_extendqisi2 + 1447 .loc 1 417 41 view .LVU414 + 1448 011c 43EA0223 orr r3, r3, r2, lsl #8 + 1449 .loc 1 417 27 view .LVU415 + 1450 0120 E383 strh r3, [r4, #30] @ movhi + 418:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[16] = rxbuffer[2] | (rxbuffer[3]<<8); + 1451 .loc 1 418 2 is_stmt 1 view .LVU416 + 1452 .loc 1 418 37 is_stmt 0 view .LVU417 + 1453 0122 9DF80230 ldrb r3, [sp, #2] @ zero_extendqisi2 + 1454 .loc 1 418 52 view .LVU418 + 1455 0126 9DF80320 ldrb r2, [sp, #3] @ zero_extendqisi2 + 1456 .loc 1 418 41 view .LVU419 + 1457 012a 43EA0223 orr r3, r3, r2, lsl #8 + 1458 .loc 1 418 27 view .LVU420 + 1459 012e 2384 strh r3, [r4, #32] @ movhi + 419:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[17] = rxbuffer[4] | (rxbuffer[5]<<8); + 1460 .loc 1 419 2 is_stmt 1 view .LVU421 + 1461 .loc 1 419 37 is_stmt 0 view .LVU422 + 1462 0130 9DF80430 ldrb r3, [sp, #4] @ zero_extendqisi2 + 1463 .loc 1 419 52 view .LVU423 + 1464 0134 9DF80520 ldrb r2, [sp, #5] @ zero_extendqisi2 + 1465 .loc 1 419 41 view .LVU424 + 1466 0138 43EA0223 orr r3, r3, r2, lsl #8 + 1467 .loc 1 419 27 view .LVU425 + 1468 013c 6384 strh r3, [r4, #34] @ movhi + 420:Core/Src/ADBMS_Abstraction.c **** + 421:Core/Src/ADBMS_Abstraction.c **** return 0; + 1469 .loc 1 421 2 is_stmt 1 view .LVU426 + 422:Core/Src/ADBMS_Abstraction.c **** } + 1470 .loc 1 422 1 is_stmt 0 view .LVU427 + 1471 013e 0020 movs r0, #0 + 1472 0140 02B0 add sp, sp, #8 + 1473 .cfi_def_cfa_offset 8 + 1474 @ sp needed + 1475 0142 10BD pop {r4, pc} + 1476 .loc 1 422 1 view .LVU428 + 1477 .cfi_endproc + 1478 .LFE155: + 1480 .section .text.amsCellMeasurement,"ax",%progbits + 1481 .align 1 + 1482 .global amsCellMeasurement + 1483 .syntax unified + 1484 .thumb + 1485 .thumb_func + 1487 amsCellMeasurement: + ARM GAS /tmp/ccKQpHxH.s page 34 + + + 1488 .LVL92: + 1489 .LFB132: + 39:Core/Src/ADBMS_Abstraction.c **** uint8_t rxbuffer[CV_GROUP_A_SIZE]; + 1490 .loc 1 39 1 is_stmt 1 view -0 + 1491 .cfi_startproc + 1492 @ args = 0, pretend = 0, frame = 8 + 1493 @ frame_needed = 0, uses_anonymous_args = 0 + 39:Core/Src/ADBMS_Abstraction.c **** uint8_t rxbuffer[CV_GROUP_A_SIZE]; + 1494 .loc 1 39 1 is_stmt 0 view .LVU430 + 1495 0000 10B5 push {r4, lr} + 1496 .cfi_def_cfa_offset 8 + 1497 .cfi_offset 4, -8 + 1498 .cfi_offset 14, -4 + 1499 0002 82B0 sub sp, sp, #8 + 1500 .cfi_def_cfa_offset 16 + 1501 0004 0446 mov r4, r0 + 40:Core/Src/ADBMS_Abstraction.c **** writeCMD((ADCV | CH000 | MD10), rxbuffer, 0); + 1502 .loc 1 40 2 is_stmt 1 view .LVU431 + 41:Core/Src/ADBMS_Abstraction.c **** mcuDelay(5); + 1503 .loc 1 41 2 view .LVU432 + 1504 0006 0022 movs r2, #0 + 1505 0008 6946 mov r1, sp + 1506 000a 4FF45870 mov r0, #864 + 1507 .LVL93: + 41:Core/Src/ADBMS_Abstraction.c **** mcuDelay(5); + 1508 .loc 1 41 2 is_stmt 0 view .LVU433 + 1509 000e FFF7FEFF bl writeCMD + 1510 .LVL94: + 42:Core/Src/ADBMS_Abstraction.c **** amsReadCellVoltages(module); + 1511 .loc 1 42 2 is_stmt 1 view .LVU434 + 1512 0012 0520 movs r0, #5 + 1513 0014 FFF7FEFF bl mcuDelay + 1514 .LVL95: + 43:Core/Src/ADBMS_Abstraction.c **** return 0; + 1515 .loc 1 43 2 view .LVU435 + 1516 0018 2046 mov r0, r4 + 1517 001a FFF7FEFF bl amsReadCellVoltages + 1518 .LVL96: + 44:Core/Src/ADBMS_Abstraction.c **** } + 1519 .loc 1 44 2 view .LVU436 + 45:Core/Src/ADBMS_Abstraction.c **** + 1520 .loc 1 45 1 is_stmt 0 view .LVU437 + 1521 001e 0020 movs r0, #0 + 1522 0020 02B0 add sp, sp, #8 + 1523 .cfi_def_cfa_offset 8 + 1524 @ sp needed + 1525 0022 10BD pop {r4, pc} + 45:Core/Src/ADBMS_Abstraction.c **** + 1526 .loc 1 45 1 view .LVU438 + 1527 .cfi_endproc + 1528 .LFE132: + 1530 .section .text.amscheckOpenCellWire,"ax",%progbits + 1531 .align 1 + 1532 .global amscheckOpenCellWire + 1533 .syntax unified + 1534 .thumb + 1535 .thumb_func + ARM GAS /tmp/ccKQpHxH.s page 35 + + + 1537 amscheckOpenCellWire: + 1538 .LVL97: + 1539 .LFB154: + 344:Core/Src/ADBMS_Abstraction.c **** uint8 args; + 1540 .loc 1 344 1 is_stmt 1 view -0 + 1541 .cfi_startproc + 1542 @ args = 0, pretend = 0, frame = 40 + 1543 @ frame_needed = 0, uses_anonymous_args = 0 + 344:Core/Src/ADBMS_Abstraction.c **** uint8 args; + 1544 .loc 1 344 1 is_stmt 0 view .LVU440 + 1545 0000 10B5 push {r4, lr} + 1546 .cfi_def_cfa_offset 8 + 1547 .cfi_offset 4, -8 + 1548 .cfi_offset 14, -4 + 1549 0002 8AB0 sub sp, sp, #40 + 1550 .cfi_def_cfa_offset 48 + 1551 0004 0446 mov r4, r0 + 345:Core/Src/ADBMS_Abstraction.c **** uint16 cellspu[18]; + 1552 .loc 1 345 2 is_stmt 1 view .LVU441 + 346:Core/Src/ADBMS_Abstraction.c **** + 1553 .loc 1 346 2 view .LVU442 + 348:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 1554 .loc 1 348 2 view .LVU443 + 1555 0006 0022 movs r2, #0 + 1556 0008 0DF12701 add r1, sp, #39 + 1557 000c 4FF43A70 mov r0, #744 + 1558 .LVL98: + 348:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 1559 .loc 1 348 2 is_stmt 0 view .LVU444 + 1560 0010 FFF7FEFF bl writeCMD + 1561 .LVL99: + 349:Core/Src/ADBMS_Abstraction.c **** writeCMD(ADOW |MD01|CH000|PUP , &args, 0); //run Pull Up at least Twice + 1562 .loc 1 349 2 is_stmt 1 view .LVU445 + 1563 0014 0520 movs r0, #5 + 1564 0016 FFF7FEFF bl HAL_Delay + 1565 .LVL100: + 350:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 1566 .loc 1 350 2 view .LVU446 + 1567 001a 0022 movs r2, #0 + 1568 001c 0DF12701 add r1, sp, #39 + 1569 0020 4FF43A70 mov r0, #744 + 1570 0024 FFF7FEFF bl writeCMD + 1571 .LVL101: + 351:Core/Src/ADBMS_Abstraction.c **** + 1572 .loc 1 351 2 view .LVU447 + 1573 0028 0520 movs r0, #5 + 1574 002a FFF7FEFF bl HAL_Delay + 1575 .LVL102: + 353:Core/Src/ADBMS_Abstraction.c **** + 1576 .loc 1 353 2 view .LVU448 + 1577 002e 2046 mov r0, r4 + 1578 0030 FFF7FEFF bl amsReadCellVoltages + 1579 .LVL103: + 355:Core/Src/ADBMS_Abstraction.c **** { + 1580 .loc 1 355 2 view .LVU449 + 1581 .LBB6: + 355:Core/Src/ADBMS_Abstraction.c **** { + ARM GAS /tmp/ccKQpHxH.s page 36 + + + 1582 .loc 1 355 6 view .LVU450 + 355:Core/Src/ADBMS_Abstraction.c **** { + 1583 .loc 1 355 14 is_stmt 0 view .LVU451 + 1584 0034 0023 movs r3, #0 + 355:Core/Src/ADBMS_Abstraction.c **** { + 1585 .loc 1 355 2 view .LVU452 + 1586 0036 08E0 b .L52 + 1587 .LVL104: + 1588 .L53: + 357:Core/Src/ADBMS_Abstraction.c **** } + 1589 .loc 1 357 3 is_stmt 1 discriminator 3 view .LVU453 + 357:Core/Src/ADBMS_Abstraction.c **** } + 1590 .loc 1 357 36 is_stmt 0 discriminator 3 view .LVU454 + 1591 0038 34F81310 ldrh r1, [r4, r3, lsl #1] + 357:Core/Src/ADBMS_Abstraction.c **** } + 1592 .loc 1 357 14 discriminator 3 view .LVU455 + 1593 003c 0AAA add r2, sp, #40 + 1594 003e 02EB4302 add r2, r2, r3, lsl #1 + 1595 0042 22F8281C strh r1, [r2, #-40] @ movhi + 355:Core/Src/ADBMS_Abstraction.c **** { + 1596 .loc 1 355 40 is_stmt 1 discriminator 3 view .LVU456 + 1597 0046 0133 adds r3, r3, #1 + 1598 .LVL105: + 355:Core/Src/ADBMS_Abstraction.c **** { + 1599 .loc 1 355 40 is_stmt 0 discriminator 3 view .LVU457 + 1600 0048 DBB2 uxtb r3, r3 + 1601 .LVL106: + 1602 .L52: + 355:Core/Src/ADBMS_Abstraction.c **** { + 1603 .loc 1 355 23 is_stmt 1 discriminator 1 view .LVU458 + 1604 004a 224A ldr r2, .L62 + 1605 004c 1278 ldrb r2, [r2] @ zero_extendqisi2 + 1606 004e 9A42 cmp r2, r3 + 1607 0050 F2D8 bhi .L53 + 1608 .LBE6: + 361:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 1609 .loc 1 361 2 view .LVU459 + 1610 0052 0022 movs r2, #0 + 1611 0054 0DF12701 add r1, sp, #39 + 1612 0058 4FF42A70 mov r0, #680 + 1613 005c FFF7FEFF bl writeCMD + 1614 .LVL107: + 362:Core/Src/ADBMS_Abstraction.c **** writeCMD(ADOW |MD01|CH000, &args, 0); //run Pull Up at least Twice + 1615 .loc 1 362 2 view .LVU460 + 1616 0060 0520 movs r0, #5 + 1617 0062 FFF7FEFF bl HAL_Delay + 1618 .LVL108: + 363:Core/Src/ADBMS_Abstraction.c **** HAL_Delay(5); + 1619 .loc 1 363 2 view .LVU461 + 1620 0066 0022 movs r2, #0 + 1621 0068 0DF12701 add r1, sp, #39 + 1622 006c 4FF42A70 mov r0, #680 + 1623 0070 FFF7FEFF bl writeCMD + 1624 .LVL109: + 364:Core/Src/ADBMS_Abstraction.c **** + 1625 .loc 1 364 2 view .LVU462 + 1626 0074 0520 movs r0, #5 + ARM GAS /tmp/ccKQpHxH.s page 37 + + + 1627 0076 FFF7FEFF bl HAL_Delay + 1628 .LVL110: + 366:Core/Src/ADBMS_Abstraction.c **** + 1629 .loc 1 366 2 view .LVU463 + 1630 007a 2046 mov r0, r4 + 1631 007c FFF7FEFF bl amsReadCellVoltages + 1632 .LVL111: + 368:Core/Src/ADBMS_Abstraction.c **** { + 1633 .loc 1 368 2 view .LVU464 + 1634 .LBB7: + 368:Core/Src/ADBMS_Abstraction.c **** { + 1635 .loc 1 368 6 view .LVU465 + 368:Core/Src/ADBMS_Abstraction.c **** { + 1636 .loc 1 368 12 is_stmt 0 view .LVU466 + 1637 0080 0123 movs r3, #1 + 368:Core/Src/ADBMS_Abstraction.c **** { + 1638 .loc 1 368 2 view .LVU467 + 1639 0082 01E0 b .L54 + 1640 .LVL112: + 1641 .L55: + 368:Core/Src/ADBMS_Abstraction.c **** { + 1642 .loc 1 368 39 is_stmt 1 discriminator 2 view .LVU468 + 1643 0084 0133 adds r3, r3, #1 + 1644 .LVL113: + 368:Core/Src/ADBMS_Abstraction.c **** { + 1645 .loc 1 368 39 is_stmt 0 discriminator 2 view .LVU469 + 1646 0086 DBB2 uxtb r3, r3 + 1647 .LVL114: + 1648 .L54: + 368:Core/Src/ADBMS_Abstraction.c **** { + 1649 .loc 1 368 21 is_stmt 1 discriminator 1 view .LVU470 + 1650 0088 124A ldr r2, .L62 + 1651 008a 1278 ldrb r2, [r2] @ zero_extendqisi2 + 1652 008c 9A42 cmp r2, r3 + 1653 008e 0ED9 bls .L61 + 1654 .LBB8: + 370:Core/Src/ADBMS_Abstraction.c **** if(dv < -4000) + 1655 .loc 1 370 3 view .LVU471 + 370:Core/Src/ADBMS_Abstraction.c **** if(dv < -4000) + 1656 .loc 1 370 19 is_stmt 0 view .LVU472 + 1657 0090 0AAA add r2, sp, #40 + 1658 0092 02EB4302 add r2, r2, r3, lsl #1 + 1659 0096 32F8282C ldrh r2, [r2, #-40] + 370:Core/Src/ADBMS_Abstraction.c **** if(dv < -4000) + 1660 .loc 1 370 43 view .LVU473 + 1661 009a 34F81310 ldrh r1, [r4, r3, lsl #1] + 370:Core/Src/ADBMS_Abstraction.c **** if(dv < -4000) + 1662 .loc 1 370 7 view .LVU474 + 1663 009e 521A subs r2, r2, r1 + 1664 .LVL115: + 371:Core/Src/ADBMS_Abstraction.c **** { + 1665 .loc 1 371 3 is_stmt 1 view .LVU475 + 371:Core/Src/ADBMS_Abstraction.c **** { + 1666 .loc 1 371 5 is_stmt 0 view .LVU476 + 1667 00a0 12F57A6F cmn r2, #4000 + 1668 00a4 EEDA bge .L55 + 373:Core/Src/ADBMS_Abstraction.c **** } + ARM GAS /tmp/ccKQpHxH.s page 38 + + + 1669 .loc 1 373 4 is_stmt 1 view .LVU477 + 373:Core/Src/ADBMS_Abstraction.c **** } + 1670 .loc 1 373 13 is_stmt 0 view .LVU478 + 1671 00a6 0133 adds r3, r3, #1 + 1672 .LVL116: + 373:Core/Src/ADBMS_Abstraction.c **** } + 1673 .loc 1 373 13 view .LVU479 + 1674 00a8 D8B2 uxtb r0, r3 + 1675 .LVL117: + 1676 .L56: + 373:Core/Src/ADBMS_Abstraction.c **** } + 1677 .loc 1 373 13 view .LVU480 + 1678 .LBE8: + 1679 .LBE7: + 386:Core/Src/ADBMS_Abstraction.c **** + 1680 .loc 1 386 1 view .LVU481 + 1681 00aa 0AB0 add sp, sp, #40 + 1682 .cfi_remember_state + 1683 .cfi_def_cfa_offset 8 + 1684 @ sp needed + 1685 00ac 10BD pop {r4, pc} + 1686 .LVL118: + 1687 .L61: + 1688 .cfi_restore_state + 376:Core/Src/ADBMS_Abstraction.c **** { + 1689 .loc 1 376 2 is_stmt 1 view .LVU482 + 376:Core/Src/ADBMS_Abstraction.c **** { + 1690 .loc 1 376 13 is_stmt 0 view .LVU483 + 1691 00ae BDF80030 ldrh r3, [sp] + 1692 .LVL119: + 376:Core/Src/ADBMS_Abstraction.c **** { + 1693 .loc 1 376 23 view .LVU484 + 1694 00b2 013B subs r3, r3, #1 + 1695 00b4 9BB2 uxth r3, r3 + 376:Core/Src/ADBMS_Abstraction.c **** { + 1696 .loc 1 376 4 view .LVU485 + 1697 00b6 4FF6FD71 movw r1, #65533 + 1698 00ba 8B42 cmp r3, r1 + 1699 00bc 05D8 bhi .L58 + 380:Core/Src/ADBMS_Abstraction.c **** { + 1700 .loc 1 380 2 is_stmt 1 view .LVU486 + 380:Core/Src/ADBMS_Abstraction.c **** { + 1701 .loc 1 380 39 is_stmt 0 view .LVU487 + 1702 00be 013A subs r2, r2, #1 + 380:Core/Src/ADBMS_Abstraction.c **** { + 1703 .loc 1 380 25 view .LVU488 + 1704 00c0 34F81230 ldrh r3, [r4, r2, lsl #1] + 380:Core/Src/ADBMS_Abstraction.c **** { + 1705 .loc 1 380 4 view .LVU489 + 1706 00c4 1BB1 cbz r3, .L59 + 385:Core/Src/ADBMS_Abstraction.c **** } + 1707 .loc 1 385 9 view .LVU490 + 1708 00c6 0020 movs r0, #0 + 1709 00c8 EFE7 b .L56 + 1710 .L58: + 378:Core/Src/ADBMS_Abstraction.c **** } + 1711 .loc 1 378 10 view .LVU491 + ARM GAS /tmp/ccKQpHxH.s page 39 + + + 1712 00ca 0120 movs r0, #1 + 1713 00cc EDE7 b .L56 + 1714 .L59: + 382:Core/Src/ADBMS_Abstraction.c **** } + 1715 .loc 1 382 10 view .LVU492 + 1716 00ce 1320 movs r0, #19 + 1717 00d0 EBE7 b .L56 + 1718 .L63: + 1719 00d2 00BF .align 2 + 1720 .L62: + 1721 00d4 00000000 .word numberofcells + 1722 .cfi_endproc + 1723 .LFE154: + 1725 .global numberofauxchannels + 1726 .section .bss.numberofauxchannels,"aw",%nobits + 1729 numberofauxchannels: + 1730 0000 00 .space 1 + 1731 .global numberofcells + 1732 .section .bss.numberofcells,"aw",%nobits + 1735 numberofcells: + 1736 0000 00 .space 1 + 1737 .text + 1738 .Letext0: + 1739 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1740 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1741 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1742 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1743 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 1744 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 1745 .file 8 "Core/Inc/ADBMS_LL_Driver.h" + 1746 .file 9 "Core/Inc/ADBMS_Abstraction.h" + 1747 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccKQpHxH.s page 40 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 ADBMS_Abstraction.c + /tmp/ccKQpHxH.s:21 .text.amsWakeUp:0000000000000000 $t + /tmp/ccKQpHxH.s:27 .text.amsWakeUp:0000000000000000 amsWakeUp + /tmp/ccKQpHxH.s:56 .text.amsConfigCellMeasurement:0000000000000000 $t + /tmp/ccKQpHxH.s:62 .text.amsConfigCellMeasurement:0000000000000000 amsConfigCellMeasurement + /tmp/ccKQpHxH.s:83 .text.amsConfigCellMeasurement:0000000000000008 $d + /tmp/ccKQpHxH.s:1735 .bss.numberofcells:0000000000000000 numberofcells + /tmp/ccKQpHxH.s:88 .text.amsAuxMeasurement:0000000000000000 $t + /tmp/ccKQpHxH.s:94 .text.amsAuxMeasurement:0000000000000000 amsAuxMeasurement + /tmp/ccKQpHxH.s:249 .text.amsInternalStatusMeasurement:0000000000000000 $t + /tmp/ccKQpHxH.s:255 .text.amsInternalStatusMeasurement:0000000000000000 amsInternalStatusMeasurement + /tmp/ccKQpHxH.s:343 .text.amsConfigAuxMeasurement:0000000000000000 $t + /tmp/ccKQpHxH.s:349 .text.amsConfigAuxMeasurement:0000000000000000 amsConfigAuxMeasurement + /tmp/ccKQpHxH.s:412 .text.amsConfigGPIO:0000000000000000 $t + /tmp/ccKQpHxH.s:418 .text.amsConfigGPIO:0000000000000000 amsConfigGPIO + /tmp/ccKQpHxH.s:436 .text.amsSetGPIO:0000000000000000 $t + /tmp/ccKQpHxH.s:442 .text.amsSetGPIO:0000000000000000 amsSetGPIO + /tmp/ccKQpHxH.s:460 .text.readGPIO:0000000000000000 $t + /tmp/ccKQpHxH.s:466 .text.readGPIO:0000000000000000 readGPIO + /tmp/ccKQpHxH.s:484 .text.amsConfigBalancing:0000000000000000 $t + /tmp/ccKQpHxH.s:490 .text.amsConfigBalancing:0000000000000000 amsConfigBalancing + /tmp/ccKQpHxH.s:585 .text.amsStartBalancing:0000000000000000 $t + /tmp/ccKQpHxH.s:591 .text.amsStartBalancing:0000000000000000 amsStartBalancing + /tmp/ccKQpHxH.s:619 .text.amsStopBalancing:0000000000000000 $t + /tmp/ccKQpHxH.s:625 .text.amsStopBalancing:0000000000000000 amsStopBalancing + /tmp/ccKQpHxH.s:649 .text.amsSelfTest:0000000000000000 $t + /tmp/ccKQpHxH.s:655 .text.amsSelfTest:0000000000000000 amsSelfTest + /tmp/ccKQpHxH.s:670 .text.amsConfigUnderVoltage:0000000000000000 $t + /tmp/ccKQpHxH.s:676 .text.amsConfigUnderVoltage:0000000000000000 amsConfigUnderVoltage + /tmp/ccKQpHxH.s:735 .text.amsCheckUnderOverVoltage:0000000000000000 $t + /tmp/ccKQpHxH.s:741 .text.amsCheckUnderOverVoltage:0000000000000000 amsCheckUnderOverVoltage + /tmp/ccKQpHxH.s:930 .text.amsConfigOverVoltage:0000000000000000 $t + /tmp/ccKQpHxH.s:936 .text.amsConfigOverVoltage:0000000000000000 amsConfigOverVoltage + /tmp/ccKQpHxH.s:994 .text.initAMS:0000000000000000 $t + /tmp/ccKQpHxH.s:1000 .text.initAMS:0000000000000000 initAMS + /tmp/ccKQpHxH.s:1052 .text.initAMS:0000000000000038 $d + /tmp/ccKQpHxH.s:1729 .bss.numberofauxchannels:0000000000000000 numberofauxchannels + /tmp/ccKQpHxH.s:1058 .text.amsClearStatus:0000000000000000 $t + /tmp/ccKQpHxH.s:1064 .text.amsClearStatus:0000000000000000 amsClearStatus + /tmp/ccKQpHxH.s:1093 .text.amsClearAux:0000000000000000 $t + /tmp/ccKQpHxH.s:1099 .text.amsClearAux:0000000000000000 amsClearAux + /tmp/ccKQpHxH.s:1128 .text.amsClearCells:0000000000000000 $t + /tmp/ccKQpHxH.s:1134 .text.amsClearCells:0000000000000000 amsClearCells + /tmp/ccKQpHxH.s:1163 .text.amsSendWarning:0000000000000000 $t + /tmp/ccKQpHxH.s:1169 .text.amsSendWarning:0000000000000000 amsSendWarning + /tmp/ccKQpHxH.s:1184 .text.amsSendError:0000000000000000 $t + /tmp/ccKQpHxH.s:1190 .text.amsSendError:0000000000000000 amsSendError + /tmp/ccKQpHxH.s:1205 .text.amsClearWarning:0000000000000000 $t + /tmp/ccKQpHxH.s:1211 .text.amsClearWarning:0000000000000000 amsClearWarning + /tmp/ccKQpHxH.s:1226 .text.amsClearError:0000000000000000 $t + /tmp/ccKQpHxH.s:1232 .text.amsClearError:0000000000000000 amsClearError + /tmp/ccKQpHxH.s:1247 .text.amsReadCellVoltages:0000000000000000 $t + /tmp/ccKQpHxH.s:1253 .text.amsReadCellVoltages:0000000000000000 amsReadCellVoltages + /tmp/ccKQpHxH.s:1481 .text.amsCellMeasurement:0000000000000000 $t + /tmp/ccKQpHxH.s:1487 .text.amsCellMeasurement:0000000000000000 amsCellMeasurement + /tmp/ccKQpHxH.s:1531 .text.amscheckOpenCellWire:0000000000000000 $t + ARM GAS /tmp/ccKQpHxH.s page 41 + + + /tmp/ccKQpHxH.s:1537 .text.amscheckOpenCellWire:0000000000000000 amscheckOpenCellWire + /tmp/ccKQpHxH.s:1721 .text.amscheckOpenCellWire:00000000000000d4 $d + /tmp/ccKQpHxH.s:1730 .bss.numberofauxchannels:0000000000000000 $d + /tmp/ccKQpHxH.s:1736 .bss.numberofcells:0000000000000000 $d + +UNDEFINED SYMBOLS +readCMD +writeCMD +mcuDelay +adbmsDriverInit +HAL_Delay diff --git a/BMS_Testbench/BMS_Software_V1/build/ADBMS_Abstraction.o b/BMS_Testbench/BMS_Software_V1/build/ADBMS_Abstraction.o new file mode 100644 index 0000000000000000000000000000000000000000..9afe59341c9eb481d5a12ec8f2d4a7c55a22f194 GIT binary patch literal 24584 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34:Core/Src/ADBMS_LL_Driver.c **** currentpec = updatePEC(currentpec, din); + 35:Core/Src/ADBMS_LL_Driver.c **** } + 36:Core/Src/ADBMS_LL_Driver.c **** } + 37:Core/Src/ADBMS_LL_Driver.c **** + 38:Core/Src/ADBMS_LL_Driver.c **** data[datalen-2] = (currentpec>>7) & 0xFF; + 39:Core/Src/ADBMS_LL_Driver.c **** data[datalen-1] = (currentpec<<1) & 0xFF; + 40:Core/Src/ADBMS_LL_Driver.c **** return 0; + 41:Core/Src/ADBMS_LL_Driver.c **** } + 42:Core/Src/ADBMS_LL_Driver.c **** + 43:Core/Src/ADBMS_LL_Driver.c **** else + 44:Core/Src/ADBMS_LL_Driver.c **** { + 45:Core/Src/ADBMS_LL_Driver.c **** return 1; + 46:Core/Src/ADBMS_LL_Driver.c **** } + 47:Core/Src/ADBMS_LL_Driver.c **** } + 48:Core/Src/ADBMS_LL_Driver.c **** + 49:Core/Src/ADBMS_LL_Driver.c **** uint8 checkPEC(uint8* data, uint8 datalen) + 50:Core/Src/ADBMS_LL_Driver.c **** { + 51:Core/Src/ADBMS_LL_Driver.c **** if(datalen <= 3) + 52:Core/Src/ADBMS_LL_Driver.c **** { + 53:Core/Src/ADBMS_LL_Driver.c **** return 255; + 54:Core/Src/ADBMS_LL_Driver.c **** } + 55:Core/Src/ADBMS_LL_Driver.c **** + 56:Core/Src/ADBMS_LL_Driver.c **** uint16 currentpec = INITAL_PEC; + 57:Core/Src/ADBMS_LL_Driver.c **** + 58:Core/Src/ADBMS_LL_Driver.c **** for(int i = 0; i < (datalen-2); i++) + 59:Core/Src/ADBMS_LL_Driver.c **** { + 60:Core/Src/ADBMS_LL_Driver.c **** for(int n = 0; n < 8;n++) + 61:Core/Src/ADBMS_LL_Driver.c **** { + 62:Core/Src/ADBMS_LL_Driver.c **** uint8 din = data[i] << (n); + 63:Core/Src/ADBMS_LL_Driver.c **** currentpec = updatePEC(currentpec, din); + 64:Core/Src/ADBMS_LL_Driver.c **** } + 65:Core/Src/ADBMS_LL_Driver.c **** } + 66:Core/Src/ADBMS_LL_Driver.c **** + 67:Core/Src/ADBMS_LL_Driver.c **** uint8 pechigh = (currentpec>>7) & 0xFF; + 68:Core/Src/ADBMS_LL_Driver.c **** uint8 peclow = (currentpec<<1) & 0xFF; + 69:Core/Src/ADBMS_LL_Driver.c **** + 70:Core/Src/ADBMS_LL_Driver.c **** if((pechigh == data[datalen-2]) && (peclow == data[datalen-1])) + 71:Core/Src/ADBMS_LL_Driver.c **** { + 72:Core/Src/ADBMS_LL_Driver.c **** return 0; + 73:Core/Src/ADBMS_LL_Driver.c **** } + 74:Core/Src/ADBMS_LL_Driver.c **** + 75:Core/Src/ADBMS_LL_Driver.c **** return 1; + 76:Core/Src/ADBMS_LL_Driver.c **** + 77:Core/Src/ADBMS_LL_Driver.c **** } + 78:Core/Src/ADBMS_LL_Driver.c **** + 79:Core/Src/ADBMS_LL_Driver.c **** uint16 updatePEC(uint16 currentPEC, uint8 din) + 80:Core/Src/ADBMS_LL_Driver.c **** { + 30 .loc 1 80 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 .loc 1 80 1 is_stmt 0 view .LVU1 + 35 0000 70B5 push {r4, r5, r6, lr} + ARM GAS /tmp/ccJRsTlY.s page 3 + + + 36 .cfi_def_cfa_offset 16 + 37 .cfi_offset 4, -16 + 38 .cfi_offset 5, -12 + 39 .cfi_offset 6, -8 + 40 .cfi_offset 14, -4 + 81:Core/Src/ADBMS_LL_Driver.c **** din = (din>>7) & 0x01; + 41 .loc 1 81 5 is_stmt 1 view .LVU2 + 42 .LVL1: + 82:Core/Src/ADBMS_LL_Driver.c **** uint8 in0 = din ^ ((currentPEC >> 14) &0x01); + 43 .loc 1 82 5 view .LVU3 + 44 .loc 1 82 43 is_stmt 0 view .LVU4 + 45 0002 C0F38032 ubfx r2, r0, #14, #1 + 46 .loc 1 82 21 view .LVU5 + 47 0006 82EAD113 eor r3, r2, r1, lsr #7 + 48 .loc 1 82 11 view .LVU6 + 49 000a 1946 mov r1, r3 + 50 .LVL2: + 83:Core/Src/ADBMS_LL_Driver.c **** uint8 in3 = in0 ^ ((currentPEC >> 2) &0x01); + 51 .loc 1 83 5 is_stmt 1 view .LVU7 + 52 .loc 1 83 42 is_stmt 0 view .LVU8 + 53 000c C0F38002 ubfx r2, r0, #2, #1 + 54 .loc 1 83 11 view .LVU9 + 55 0010 5A40 eors r2, r2, r3 + 56 .LVL3: + 84:Core/Src/ADBMS_LL_Driver.c **** uint8 in4 = in0 ^ ((currentPEC >> 3) &0x01); + 57 .loc 1 84 5 is_stmt 1 view .LVU10 + 58 .loc 1 84 42 is_stmt 0 view .LVU11 + 59 0012 C0F3C00C ubfx ip, r0, #3, #1 + 60 .loc 1 84 11 view .LVU12 + 61 0016 83EA0C0C eor ip, r3, ip + 62 .LVL4: + 85:Core/Src/ADBMS_LL_Driver.c **** uint8 in7 = in0 ^ ((currentPEC >> 6) &0x01); + 63 .loc 1 85 5 is_stmt 1 view .LVU13 + 64 .loc 1 85 42 is_stmt 0 view .LVU14 + 65 001a C0F3801E ubfx lr, r0, #6, #1 + 66 .loc 1 85 11 view .LVU15 + 67 001e 83EA0E0E eor lr, r3, lr + 68 .LVL5: + 86:Core/Src/ADBMS_LL_Driver.c **** uint8 in8 = in0 ^ ((currentPEC >> 7) &0x01); + 69 .loc 1 86 5 is_stmt 1 view .LVU16 + 70 .loc 1 86 42 is_stmt 0 view .LVU17 + 71 0022 C0F3C014 ubfx r4, r0, #7, #1 + 72 .loc 1 86 11 view .LVU18 + 73 0026 5C40 eors r4, r4, r3 + 74 .LVL6: + 87:Core/Src/ADBMS_LL_Driver.c **** uint8 in10 = in0 ^ ((currentPEC >> 9) &0x01); + 75 .loc 1 87 5 is_stmt 1 view .LVU19 + 76 .loc 1 87 43 is_stmt 0 view .LVU20 + 77 0028 C0F34025 ubfx r5, r0, #9, #1 + 78 .loc 1 87 11 view .LVU21 + 79 002c 5D40 eors r5, r5, r3 + 80 .LVL7: + 88:Core/Src/ADBMS_LL_Driver.c **** uint8 in14 = in0 ^ ((currentPEC >> 13) &0x01); + 81 .loc 1 88 5 is_stmt 1 view .LVU22 + 82 .loc 1 88 44 is_stmt 0 view .LVU23 + 83 002e C0F34036 ubfx r6, r0, #13, #1 + 84 .loc 1 88 11 view .LVU24 + ARM GAS /tmp/ccJRsTlY.s page 4 + + + 85 0032 5E40 eors r6, r6, r3 + 86 .LVL8: + 89:Core/Src/ADBMS_LL_Driver.c **** + 90:Core/Src/ADBMS_LL_Driver.c **** uint16 newPEC = 0; + 87 .loc 1 90 5 is_stmt 1 view .LVU25 + 91:Core/Src/ADBMS_LL_Driver.c **** + 92:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in14<<14; + 88 .loc 1 92 5 view .LVU26 + 93:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01<<12))<<1; + 89 .loc 1 93 5 view .LVU27 + 90 .loc 1 93 40 is_stmt 0 view .LVU28 + 91 0034 4000 lsls r0, r0, #1 + 92 .LVL9: + 93 .loc 1 93 40 view .LVU29 + 94 0036 00F40053 and r3, r0, #8192 + 95 .LVL10: + 96 .loc 1 93 12 view .LVU30 + 97 003a 43EA8633 orr r3, r3, r6, lsl #14 + 98 .LVL11: + 94:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01<<11))<<1; + 99 .loc 1 94 5 is_stmt 1 view .LVU31 + 100 .loc 1 94 40 is_stmt 0 view .LVU32 + 101 003e 00F48056 and r6, r0, #4096 + 102 .LVL12: + 103 .loc 1 94 12 view .LVU33 + 104 0042 3343 orrs r3, r3, r6 + 105 .LVL13: + 106 .loc 1 94 12 view .LVU34 + 107 0044 1BB2 sxth r3, r3 + 108 .LVL14: + 95:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01<<10))<<1; + 109 .loc 1 95 5 is_stmt 1 view .LVU35 + 110 .loc 1 95 40 is_stmt 0 view .LVU36 + 111 0046 00F40066 and r6, r0, #2048 + 112 .loc 1 95 12 view .LVU37 + 113 004a 3343 orrs r3, r3, r6 + 114 .LVL15: + 96:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in10<<10; + 115 .loc 1 96 5 is_stmt 1 view .LVU38 + 116 .loc 1 96 12 is_stmt 0 view .LVU39 + 117 004c 43EA8523 orr r3, r3, r5, lsl #10 + 118 .LVL16: + 97:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01<<8))<<1; + 119 .loc 1 97 5 is_stmt 1 view .LVU40 + 120 .loc 1 97 39 is_stmt 0 view .LVU41 + 121 0050 00F40075 and r5, r0, #512 + 122 .LVL17: + 123 .loc 1 97 12 view .LVU42 + 124 0054 2B43 orrs r3, r3, r5 + 125 .LVL18: + 126 .loc 1 97 12 view .LVU43 + 127 0056 1BB2 sxth r3, r3 + 128 .LVL19: + 98:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in8<<8; + 129 .loc 1 98 5 is_stmt 1 view .LVU44 + 130 .loc 1 98 12 is_stmt 0 view .LVU45 + 131 0058 43EA0423 orr r3, r3, r4, lsl #8 + ARM GAS /tmp/ccJRsTlY.s page 5 + + + 132 .LVL20: + 99:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in7<<7; + 133 .loc 1 99 5 is_stmt 1 view .LVU46 + 134 .loc 1 99 12 is_stmt 0 view .LVU47 + 135 005c 43EACE13 orr r3, r3, lr, lsl #7 + 136 .LVL21: + 100:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01<<5))<<1; + 137 .loc 1 100 5 is_stmt 1 view .LVU48 + 138 .loc 1 100 39 is_stmt 0 view .LVU49 + 139 0060 00F04004 and r4, r0, #64 + 140 .LVL22: + 141 .loc 1 100 12 view .LVU50 + 142 0064 2343 orrs r3, r3, r4 + 143 .LVL23: + 144 .loc 1 100 12 view .LVU51 + 145 0066 1BB2 sxth r3, r3 + 146 .LVL24: + 101:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01<<4))<<1; + 147 .loc 1 101 5 is_stmt 1 view .LVU52 + 148 .loc 1 101 39 is_stmt 0 view .LVU53 + 149 0068 00F02004 and r4, r0, #32 + 150 .loc 1 101 12 view .LVU54 + 151 006c 2343 orrs r3, r3, r4 + 152 .LVL25: + 102:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in4<<4; + 153 .loc 1 102 5 is_stmt 1 view .LVU55 + 154 .loc 1 102 12 is_stmt 0 view .LVU56 + 155 006e 43EA0C13 orr r3, r3, ip, lsl #4 + 156 .LVL26: + 103:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in3<<3; + 157 .loc 1 103 5 is_stmt 1 view .LVU57 + 158 .loc 1 103 12 is_stmt 0 view .LVU58 + 159 0072 43EAC203 orr r3, r3, r2, lsl #3 + 160 .LVL27: + 104:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01<<1))<<1; + 161 .loc 1 104 5 is_stmt 1 view .LVU59 + 162 .loc 1 104 39 is_stmt 0 view .LVU60 + 163 0076 00F00402 and r2, r0, #4 + 164 .LVL28: + 165 .loc 1 104 12 view .LVU61 + 166 007a 1343 orrs r3, r3, r2 + 167 .LVL29: + 168 .loc 1 104 12 view .LVU62 + 169 007c 1BB2 sxth r3, r3 + 170 .LVL30: + 105:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01))<<1; + 171 .loc 1 105 5 is_stmt 1 view .LVU63 + 172 .loc 1 105 36 is_stmt 0 view .LVU64 + 173 007e 00F00200 and r0, r0, #2 + 174 .loc 1 105 12 view .LVU65 + 175 0082 0343 orrs r3, r3, r0 + 176 .LVL31: + 177 .loc 1 105 12 view .LVU66 + 178 0084 9BB2 uxth r3, r3 + 179 .LVL32: + 106:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in0; + 180 .loc 1 106 5 is_stmt 1 view .LVU67 + ARM GAS /tmp/ccJRsTlY.s page 6 + + + 107:Core/Src/ADBMS_LL_Driver.c **** + 108:Core/Src/ADBMS_LL_Driver.c **** + 109:Core/Src/ADBMS_LL_Driver.c **** return newPEC; + 181 .loc 1 109 5 view .LVU68 + 110:Core/Src/ADBMS_LL_Driver.c **** } + 182 .loc 1 110 1 is_stmt 0 view .LVU69 + 183 0086 41EA0300 orr r0, r1, r3 + 184 .LVL33: + 185 .loc 1 110 1 view .LVU70 + 186 008a 70BD pop {r4, r5, r6, pc} + 187 .cfi_endproc + 188 .LFE133: + 190 .section .text.calculatePEC,"ax",%progbits + 191 .align 1 + 192 .global calculatePEC + 193 .syntax unified + 194 .thumb + 195 .thumb_func + 197 calculatePEC: + 198 .LVL34: + 199 .LFB131: + 25:Core/Src/ADBMS_LL_Driver.c **** uint16 currentpec = INITAL_PEC; + 200 .loc 1 25 1 is_stmt 1 view -0 + 201 .cfi_startproc + 202 @ args = 0, pretend = 0, frame = 0 + 203 @ frame_needed = 0, uses_anonymous_args = 0 + 26:Core/Src/ADBMS_LL_Driver.c **** if(datalen >= 3) + 204 .loc 1 26 5 view .LVU72 + 27:Core/Src/ADBMS_LL_Driver.c **** { + 205 .loc 1 27 5 view .LVU73 + 27:Core/Src/ADBMS_LL_Driver.c **** { + 206 .loc 1 27 7 is_stmt 0 view .LVU74 + 207 0000 0229 cmp r1, #2 + 208 0002 0FD8 bhi .L8 + 45:Core/Src/ADBMS_LL_Driver.c **** } + 209 .loc 1 45 16 view .LVU75 + 210 0004 0120 movs r0, #1 + 211 .LVL35: + 47:Core/Src/ADBMS_LL_Driver.c **** + 212 .loc 1 47 1 view .LVU76 + 213 0006 7047 bx lr + 214 .LVL36: + 215 .L6: + 216 .cfi_def_cfa_offset 24 + 217 .cfi_offset 3, -24 + 218 .cfi_offset 4, -20 + 219 .cfi_offset 5, -16 + 220 .cfi_offset 6, -12 + 221 .cfi_offset 7, -8 + 222 .cfi_offset 14, -4 + 223 .LBB2: + 224 .LBB3: + 225 .LBB4: + 33:Core/Src/ADBMS_LL_Driver.c **** currentpec = updatePEC(currentpec, din); + 226 .loc 1 33 17 is_stmt 1 discriminator 3 view .LVU77 + 33:Core/Src/ADBMS_LL_Driver.c **** currentpec = updatePEC(currentpec, din); + 227 .loc 1 33 33 is_stmt 0 discriminator 3 view .LVU78 + ARM GAS /tmp/ccJRsTlY.s page 7 + + + 228 0008 E95D ldrb r1, [r5, r7] @ zero_extendqisi2 + 33:Core/Src/ADBMS_LL_Driver.c **** currentpec = updatePEC(currentpec, din); + 229 .loc 1 33 37 discriminator 3 view .LVU79 + 230 000a A140 lsls r1, r1, r4 + 231 .LVL37: + 34:Core/Src/ADBMS_LL_Driver.c **** } + 232 .loc 1 34 17 is_stmt 1 discriminator 3 view .LVU80 + 34:Core/Src/ADBMS_LL_Driver.c **** } + 233 .loc 1 34 30 is_stmt 0 discriminator 3 view .LVU81 + 234 000c C9B2 uxtb r1, r1 + 34:Core/Src/ADBMS_LL_Driver.c **** } + 235 .loc 1 34 30 discriminator 3 view .LVU82 + 236 000e FFF7FEFF bl updatePEC + 237 .LVL38: + 34:Core/Src/ADBMS_LL_Driver.c **** } + 238 .loc 1 34 30 discriminator 3 view .LVU83 + 239 .LBE4: + 31:Core/Src/ADBMS_LL_Driver.c **** { + 240 .loc 1 31 35 is_stmt 1 discriminator 3 view .LVU84 + 241 0012 0134 adds r4, r4, #1 + 242 .LVL39: + 243 .L7: + 31:Core/Src/ADBMS_LL_Driver.c **** { + 244 .loc 1 31 30 discriminator 1 view .LVU85 + 245 0014 072C cmp r4, #7 + 246 0016 F7DD ble .L6 + 31:Core/Src/ADBMS_LL_Driver.c **** { + 247 .loc 1 31 30 is_stmt 0 discriminator 1 view .LVU86 + 248 .LBE3: + 29:Core/Src/ADBMS_LL_Driver.c **** { + 249 .loc 1 29 42 is_stmt 1 discriminator 2 view .LVU87 + 250 0018 0137 adds r7, r7, #1 + 251 .LVL40: + 252 .L4: + 29:Core/Src/ADBMS_LL_Driver.c **** { + 253 .loc 1 29 26 discriminator 1 view .LVU88 + 29:Core/Src/ADBMS_LL_Driver.c **** { + 254 .loc 1 29 36 is_stmt 0 discriminator 1 view .LVU89 + 255 001a B31E subs r3, r6, #2 + 29:Core/Src/ADBMS_LL_Driver.c **** { + 256 .loc 1 29 26 discriminator 1 view .LVU90 + 257 001c BB42 cmp r3, r7 + 258 001e 07DD ble .L13 + 259 .LBB5: + 31:Core/Src/ADBMS_LL_Driver.c **** { + 260 .loc 1 31 21 view .LVU91 + 261 0020 0024 movs r4, #0 + 262 0022 F7E7 b .L7 + 263 .LVL41: + 264 .L8: + 265 .cfi_def_cfa_offset 0 + 266 .cfi_restore 3 + 267 .cfi_restore 4 + 268 .cfi_restore 5 + 269 .cfi_restore 6 + 270 .cfi_restore 7 + 271 .cfi_restore 14 + ARM GAS /tmp/ccJRsTlY.s page 8 + + + 31:Core/Src/ADBMS_LL_Driver.c **** { + 272 .loc 1 31 21 view .LVU92 + 273 .LBE5: + 274 .LBE2: + 25:Core/Src/ADBMS_LL_Driver.c **** uint16 currentpec = INITAL_PEC; + 275 .loc 1 25 1 view .LVU93 + 276 0024 F8B5 push {r3, r4, r5, r6, r7, lr} + 277 .cfi_def_cfa_offset 24 + 278 .cfi_offset 3, -24 + 279 .cfi_offset 4, -20 + 280 .cfi_offset 5, -16 + 281 .cfi_offset 6, -12 + 282 .cfi_offset 7, -8 + 283 .cfi_offset 14, -4 + 284 0026 0546 mov r5, r0 + 285 0028 0E46 mov r6, r1 + 286 .LBB6: + 29:Core/Src/ADBMS_LL_Driver.c **** { + 287 .loc 1 29 17 view .LVU94 + 288 002a 0027 movs r7, #0 + 289 .LBE6: + 26:Core/Src/ADBMS_LL_Driver.c **** if(datalen >= 3) + 290 .loc 1 26 12 view .LVU95 + 291 002c 1020 movs r0, #16 + 292 .LVL42: + 26:Core/Src/ADBMS_LL_Driver.c **** if(datalen >= 3) + 293 .loc 1 26 12 view .LVU96 + 294 002e F4E7 b .L4 + 295 .LVL43: + 296 .L13: + 38:Core/Src/ADBMS_LL_Driver.c **** data[datalen-1] = (currentpec<<1) & 0xFF; + 297 .loc 1 38 9 is_stmt 1 view .LVU97 + 38:Core/Src/ADBMS_LL_Driver.c **** data[datalen-1] = (currentpec<<1) & 0xFF; + 298 .loc 1 38 25 is_stmt 0 view .LVU98 + 299 0030 C209 lsrs r2, r0, #7 + 300 0032 EA54 strb r2, [r5, r3] + 39:Core/Src/ADBMS_LL_Driver.c **** return 0; + 301 .loc 1 39 9 is_stmt 1 view .LVU99 + 39:Core/Src/ADBMS_LL_Driver.c **** return 0; + 302 .loc 1 39 38 is_stmt 0 view .LVU100 + 303 0034 4300 lsls r3, r0, #1 + 39:Core/Src/ADBMS_LL_Driver.c **** return 0; + 304 .loc 1 39 13 view .LVU101 + 305 0036 013E subs r6, r6, #1 + 39:Core/Src/ADBMS_LL_Driver.c **** return 0; + 306 .loc 1 39 25 view .LVU102 + 307 0038 AB55 strb r3, [r5, r6] + 40:Core/Src/ADBMS_LL_Driver.c **** } + 308 .loc 1 40 9 is_stmt 1 view .LVU103 + 40:Core/Src/ADBMS_LL_Driver.c **** } + 309 .loc 1 40 16 is_stmt 0 view .LVU104 + 310 003a 0020 movs r0, #0 + 311 .LVL44: + 47:Core/Src/ADBMS_LL_Driver.c **** + 312 .loc 1 47 1 view .LVU105 + 313 003c F8BD pop {r3, r4, r5, r6, r7, pc} + 47:Core/Src/ADBMS_LL_Driver.c **** + ARM GAS /tmp/ccJRsTlY.s page 9 + + + 314 .loc 1 47 1 view .LVU106 + 315 .cfi_endproc + 316 .LFE131: + 318 .section .text.checkPEC,"ax",%progbits + 319 .align 1 + 320 .global checkPEC + 321 .syntax unified + 322 .thumb + 323 .thumb_func + 325 checkPEC: + 326 .LVL45: + 327 .LFB132: + 50:Core/Src/ADBMS_LL_Driver.c **** if(datalen <= 3) + 328 .loc 1 50 1 is_stmt 1 view -0 + 329 .cfi_startproc + 330 @ args = 0, pretend = 0, frame = 0 + 331 @ frame_needed = 0, uses_anonymous_args = 0 + 51:Core/Src/ADBMS_LL_Driver.c **** { + 332 .loc 1 51 2 view .LVU108 + 51:Core/Src/ADBMS_LL_Driver.c **** { + 333 .loc 1 51 4 is_stmt 0 view .LVU109 + 334 0000 0329 cmp r1, #3 + 335 0002 25D9 bls .L19 + 50:Core/Src/ADBMS_LL_Driver.c **** if(datalen <= 3) + 336 .loc 1 50 1 view .LVU110 + 337 0004 F8B5 push {r3, r4, r5, r6, r7, lr} + 338 .cfi_def_cfa_offset 24 + 339 .cfi_offset 3, -24 + 340 .cfi_offset 4, -20 + 341 .cfi_offset 5, -16 + 342 .cfi_offset 6, -12 + 343 .cfi_offset 7, -8 + 344 .cfi_offset 14, -4 + 345 0006 0546 mov r5, r0 + 346 0008 0E46 mov r6, r1 + 347 .LBB7: + 58:Core/Src/ADBMS_LL_Driver.c **** { + 348 .loc 1 58 10 view .LVU111 + 349 000a 0027 movs r7, #0 + 350 .LBE7: + 56:Core/Src/ADBMS_LL_Driver.c **** + 351 .loc 1 56 9 view .LVU112 + 352 000c 1020 movs r0, #16 + 353 .LVL46: + 56:Core/Src/ADBMS_LL_Driver.c **** + 354 .loc 1 56 9 view .LVU113 + 355 000e 08E0 b .L16 + 356 .LVL47: + 357 .L17: + 358 .LBB11: + 359 .LBB8: + 360 .LBB9: + 62:Core/Src/ADBMS_LL_Driver.c **** currentpec = updatePEC(currentpec, din); + 361 .loc 1 62 10 is_stmt 1 discriminator 3 view .LVU114 + 62:Core/Src/ADBMS_LL_Driver.c **** currentpec = updatePEC(currentpec, din); + 362 .loc 1 62 26 is_stmt 0 discriminator 3 view .LVU115 + 363 0010 E95D ldrb r1, [r5, r7] @ zero_extendqisi2 + ARM GAS /tmp/ccJRsTlY.s page 10 + + + 62:Core/Src/ADBMS_LL_Driver.c **** currentpec = updatePEC(currentpec, din); + 364 .loc 1 62 30 discriminator 3 view .LVU116 + 365 0012 A140 lsls r1, r1, r4 + 366 .LVL48: + 63:Core/Src/ADBMS_LL_Driver.c **** } + 367 .loc 1 63 10 is_stmt 1 discriminator 3 view .LVU117 + 63:Core/Src/ADBMS_LL_Driver.c **** } + 368 .loc 1 63 23 is_stmt 0 discriminator 3 view .LVU118 + 369 0014 C9B2 uxtb r1, r1 + 63:Core/Src/ADBMS_LL_Driver.c **** } + 370 .loc 1 63 23 discriminator 3 view .LVU119 + 371 0016 FFF7FEFF bl updatePEC + 372 .LVL49: + 63:Core/Src/ADBMS_LL_Driver.c **** } + 373 .loc 1 63 23 discriminator 3 view .LVU120 + 374 .LBE9: + 60:Core/Src/ADBMS_LL_Driver.c **** { + 375 .loc 1 60 28 is_stmt 1 discriminator 3 view .LVU121 + 376 001a 0134 adds r4, r4, #1 + 377 .LVL50: + 378 .L18: + 60:Core/Src/ADBMS_LL_Driver.c **** { + 379 .loc 1 60 23 discriminator 1 view .LVU122 + 380 001c 072C cmp r4, #7 + 381 001e F7DD ble .L17 + 60:Core/Src/ADBMS_LL_Driver.c **** { + 382 .loc 1 60 23 is_stmt 0 discriminator 1 view .LVU123 + 383 .LBE8: + 58:Core/Src/ADBMS_LL_Driver.c **** { + 384 .loc 1 58 35 is_stmt 1 discriminator 2 view .LVU124 + 385 0020 0137 adds r7, r7, #1 + 386 .LVL51: + 387 .L16: + 58:Core/Src/ADBMS_LL_Driver.c **** { + 388 .loc 1 58 19 discriminator 1 view .LVU125 + 58:Core/Src/ADBMS_LL_Driver.c **** { + 389 .loc 1 58 29 is_stmt 0 discriminator 1 view .LVU126 + 390 0022 B31E subs r3, r6, #2 + 58:Core/Src/ADBMS_LL_Driver.c **** { + 391 .loc 1 58 19 discriminator 1 view .LVU127 + 392 0024 BB42 cmp r3, r7 + 393 0026 01DD ble .L27 + 394 .LBB10: + 60:Core/Src/ADBMS_LL_Driver.c **** { + 395 .loc 1 60 14 view .LVU128 + 396 0028 0024 movs r4, #0 + 397 002a F7E7 b .L18 + 398 .L27: + 399 .LBE10: + 400 .LBE11: + 67:Core/Src/ADBMS_LL_Driver.c **** uint8 peclow = (currentpec<<1) & 0xFF; + 401 .loc 1 67 2 is_stmt 1 view .LVU129 + 67:Core/Src/ADBMS_LL_Driver.c **** uint8 peclow = (currentpec<<1) & 0xFF; + 402 .loc 1 67 8 is_stmt 0 view .LVU130 + 403 002c C0F3C712 ubfx r2, r0, #7, #8 + 404 .LVL52: + 68:Core/Src/ADBMS_LL_Driver.c **** + ARM GAS /tmp/ccJRsTlY.s page 11 + + + 405 .loc 1 68 2 is_stmt 1 view .LVU131 + 68:Core/Src/ADBMS_LL_Driver.c **** + 406 .loc 1 68 28 is_stmt 0 view .LVU132 + 407 0030 4300 lsls r3, r0, #1 + 68:Core/Src/ADBMS_LL_Driver.c **** + 408 .loc 1 68 8 view .LVU133 + 409 0032 DBB2 uxtb r3, r3 + 410 .LVL53: + 70:Core/Src/ADBMS_LL_Driver.c **** { + 411 .loc 1 70 2 is_stmt 1 view .LVU134 + 70:Core/Src/ADBMS_LL_Driver.c **** { + 412 .loc 1 70 21 is_stmt 0 view .LVU135 + 413 0034 A919 adds r1, r5, r6 + 414 0036 11F8021C ldrb r1, [r1, #-2] @ zero_extendqisi2 + 70:Core/Src/ADBMS_LL_Driver.c **** { + 415 .loc 1 70 4 view .LVU136 + 416 003a 9142 cmp r1, r2 + 417 003c 01D0 beq .L28 + 75:Core/Src/ADBMS_LL_Driver.c **** + 418 .loc 1 75 9 view .LVU137 + 419 003e 0120 movs r0, #1 + 420 .LVL54: + 421 .L15: + 77:Core/Src/ADBMS_LL_Driver.c **** + 422 .loc 1 77 1 view .LVU138 + 423 0040 F8BD pop {r3, r4, r5, r6, r7, pc} + 424 .LVL55: + 425 .L28: + 70:Core/Src/ADBMS_LL_Driver.c **** { + 426 .loc 1 70 52 discriminator 1 view .LVU139 + 427 0042 3544 add r5, r5, r6 + 428 .LVL56: + 70:Core/Src/ADBMS_LL_Driver.c **** { + 429 .loc 1 70 52 discriminator 1 view .LVU140 + 430 0044 15F8012C ldrb r2, [r5, #-1] @ zero_extendqisi2 + 431 .LVL57: + 70:Core/Src/ADBMS_LL_Driver.c **** { + 432 .loc 1 70 34 discriminator 1 view .LVU141 + 433 0048 9A42 cmp r2, r3 + 434 004a 03D0 beq .L22 + 75:Core/Src/ADBMS_LL_Driver.c **** + 435 .loc 1 75 9 view .LVU142 + 436 004c 0120 movs r0, #1 + 437 .LVL58: + 75:Core/Src/ADBMS_LL_Driver.c **** + 438 .loc 1 75 9 view .LVU143 + 439 004e F7E7 b .L15 + 440 .LVL59: + 441 .L19: + 442 .cfi_def_cfa_offset 0 + 443 .cfi_restore 3 + 444 .cfi_restore 4 + 445 .cfi_restore 5 + 446 .cfi_restore 6 + 447 .cfi_restore 7 + 448 .cfi_restore 14 + 53:Core/Src/ADBMS_LL_Driver.c **** } + ARM GAS /tmp/ccJRsTlY.s page 12 + + + 449 .loc 1 53 10 view .LVU144 + 450 0050 FF20 movs r0, #255 + 451 .LVL60: + 77:Core/Src/ADBMS_LL_Driver.c **** + 452 .loc 1 77 1 view .LVU145 + 453 0052 7047 bx lr + 454 .LVL61: + 455 .L22: + 456 .cfi_def_cfa_offset 24 + 457 .cfi_offset 3, -24 + 458 .cfi_offset 4, -20 + 459 .cfi_offset 5, -16 + 460 .cfi_offset 6, -12 + 461 .cfi_offset 7, -8 + 462 .cfi_offset 14, -4 + 72:Core/Src/ADBMS_LL_Driver.c **** } + 463 .loc 1 72 10 view .LVU146 + 464 0054 0020 movs r0, #0 + 465 .LVL62: + 72:Core/Src/ADBMS_LL_Driver.c **** } + 466 .loc 1 72 10 view .LVU147 + 467 0056 F3E7 b .L15 + 468 .cfi_endproc + 469 .LFE132: + 471 .section .text.mcuAdbmsCSLow,"ax",%progbits + 472 .align 1 + 473 .global mcuAdbmsCSLow + 474 .syntax unified + 475 .thumb + 476 .thumb_func + 478 mcuAdbmsCSLow: + 479 .LFB136: + 111:Core/Src/ADBMS_LL_Driver.c **** + 112:Core/Src/ADBMS_LL_Driver.c **** uint8 writeCMD(uint16 command, uint8* args, uint8 arglen) + 113:Core/Src/ADBMS_LL_Driver.c **** { + 114:Core/Src/ADBMS_LL_Driver.c **** if(arglen > 0) + 115:Core/Src/ADBMS_LL_Driver.c **** { + 116:Core/Src/ADBMS_LL_Driver.c **** uint8 buffer[6+arglen]; + 117:Core/Src/ADBMS_LL_Driver.c **** buffer[0] = (command >> 8) & 0xFF; + 118:Core/Src/ADBMS_LL_Driver.c **** buffer[1] = (command) & 0xFF; + 119:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(buffer, 4); + 120:Core/Src/ADBMS_LL_Driver.c **** for(uint8 i = 0; i < arglen; i++) + 121:Core/Src/ADBMS_LL_Driver.c **** { + 122:Core/Src/ADBMS_LL_Driver.c **** buffer[4+i] = args[i]; + 123:Core/Src/ADBMS_LL_Driver.c **** } + 124:Core/Src/ADBMS_LL_Driver.c **** + 125:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(&buffer[4], arglen+2); //Calculate PEC of Data Part with offset of 4 Bytes for CMD an + 126:Core/Src/ADBMS_LL_Driver.c **** + 127:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 128:Core/Src/ADBMS_LL_Driver.c **** mcuSPITransmit(buffer, 6+arglen); + 129:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 130:Core/Src/ADBMS_LL_Driver.c **** + 131:Core/Src/ADBMS_LL_Driver.c **** } + 132:Core/Src/ADBMS_LL_Driver.c **** else + 133:Core/Src/ADBMS_LL_Driver.c **** { + 134:Core/Src/ADBMS_LL_Driver.c **** uint8 buffer[4]; + 135:Core/Src/ADBMS_LL_Driver.c **** buffer[0] = (command >> 8) & 0xFF; + ARM GAS /tmp/ccJRsTlY.s page 13 + + + 136:Core/Src/ADBMS_LL_Driver.c **** buffer[1] = (command) & 0xFF; + 137:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(buffer, 4); + 138:Core/Src/ADBMS_LL_Driver.c **** + 139:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 140:Core/Src/ADBMS_LL_Driver.c **** + 141:Core/Src/ADBMS_LL_Driver.c **** mcuSPITransmit(buffer, 4); + 142:Core/Src/ADBMS_LL_Driver.c **** + 143:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 144:Core/Src/ADBMS_LL_Driver.c **** } + 145:Core/Src/ADBMS_LL_Driver.c **** + 146:Core/Src/ADBMS_LL_Driver.c **** return 0; + 147:Core/Src/ADBMS_LL_Driver.c **** } + 148:Core/Src/ADBMS_LL_Driver.c **** + 149:Core/Src/ADBMS_LL_Driver.c **** uint8 readCMD(uint16 command, uint8* buffer, uint8 buflen) + 150:Core/Src/ADBMS_LL_Driver.c **** { + 151:Core/Src/ADBMS_LL_Driver.c **** //uint8* txbuffer = (uint8*) malloc(6+buflen); + 152:Core/Src/ADBMS_LL_Driver.c **** //uint8* rxbuffer = (uint8*) malloc(6+buflen); + 153:Core/Src/ADBMS_LL_Driver.c **** uint8 txbuffer[6+buflen]; + 154:Core/Src/ADBMS_LL_Driver.c **** uint8 rxbuffer[6+buflen]; + 155:Core/Src/ADBMS_LL_Driver.c **** + 156:Core/Src/ADBMS_LL_Driver.c **** txbuffer[0] = (command >> 8) & 0xFF; + 157:Core/Src/ADBMS_LL_Driver.c **** txbuffer[1] = (command) & 0xFF; + 158:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(txbuffer, 4); + 159:Core/Src/ADBMS_LL_Driver.c **** + 160:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 161:Core/Src/ADBMS_LL_Driver.c **** mcuSPITransmitReceive(rxbuffer, txbuffer, 6+buflen); + 162:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 163:Core/Src/ADBMS_LL_Driver.c **** + 164:Core/Src/ADBMS_LL_Driver.c **** + 165:Core/Src/ADBMS_LL_Driver.c **** for(uint8 i = 0; i 100) { + 181:Core/Src/ADBMS_LL_Driver.c **** Error_Handler(); + 182:Core/Src/ADBMS_LL_Driver.c **** } else { + 183:Core/Src/ADBMS_LL_Driver.c **** return 1; + 184:Core/Src/ADBMS_LL_Driver.c **** } + 185:Core/Src/ADBMS_LL_Driver.c **** } + 186:Core/Src/ADBMS_LL_Driver.c **** + 187:Core/Src/ADBMS_LL_Driver.c **** } + 188:Core/Src/ADBMS_LL_Driver.c **** + 189:Core/Src/ADBMS_LL_Driver.c **** void mcuAdbmsCSLow() + 190:Core/Src/ADBMS_LL_Driver.c **** { + 480 .loc 1 190 1 is_stmt 1 view -0 + 481 .cfi_startproc + ARM GAS /tmp/ccJRsTlY.s page 14 + + + 482 @ args = 0, pretend = 0, frame = 0 + 483 @ frame_needed = 0, uses_anonymous_args = 0 + 484 0000 08B5 push {r3, lr} + 485 .cfi_def_cfa_offset 8 + 486 .cfi_offset 3, -8 + 487 .cfi_offset 14, -4 + 191:Core/Src/ADBMS_LL_Driver.c **** HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_RESET); + 488 .loc 1 191 2 view .LVU149 + 489 0002 0022 movs r2, #0 + 490 0004 1021 movs r1, #16 + 491 0006 4FF09040 mov r0, #1207959552 + 492 000a FFF7FEFF bl HAL_GPIO_WritePin + 493 .LVL63: + 192:Core/Src/ADBMS_LL_Driver.c **** } + 494 .loc 1 192 1 is_stmt 0 view .LVU150 + 495 000e 08BD pop {r3, pc} + 496 .cfi_endproc + 497 .LFE136: + 499 .section .text.mcuAdbmsCSHigh,"ax",%progbits + 500 .align 1 + 501 .global mcuAdbmsCSHigh + 502 .syntax unified + 503 .thumb + 504 .thumb_func + 506 mcuAdbmsCSHigh: + 507 .LFB137: + 193:Core/Src/ADBMS_LL_Driver.c **** + 194:Core/Src/ADBMS_LL_Driver.c **** void mcuAdbmsCSHigh() + 195:Core/Src/ADBMS_LL_Driver.c **** { + 508 .loc 1 195 1 is_stmt 1 view -0 + 509 .cfi_startproc + 510 @ args = 0, pretend = 0, frame = 0 + 511 @ frame_needed = 0, uses_anonymous_args = 0 + 512 0000 08B5 push {r3, lr} + 513 .cfi_def_cfa_offset 8 + 514 .cfi_offset 3, -8 + 515 .cfi_offset 14, -4 + 196:Core/Src/ADBMS_LL_Driver.c **** HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_SET); + 516 .loc 1 196 2 view .LVU152 + 517 0002 0122 movs r2, #1 + 518 0004 1021 movs r1, #16 + 519 0006 4FF09040 mov r0, #1207959552 + 520 000a FFF7FEFF bl HAL_GPIO_WritePin + 521 .LVL64: + 197:Core/Src/ADBMS_LL_Driver.c **** } + 522 .loc 1 197 1 is_stmt 0 view .LVU153 + 523 000e 08BD pop {r3, pc} + 524 .cfi_endproc + 525 .LFE137: + 527 .section .text.adbmsDriverInit,"ax",%progbits + 528 .align 1 + 529 .global adbmsDriverInit + 530 .syntax unified + 531 .thumb + 532 .thumb_func + 534 adbmsDriverInit: + 535 .LVL65: + ARM GAS /tmp/ccJRsTlY.s page 15 + + + 536 .LFB130: + 16:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 537 .loc 1 16 1 is_stmt 1 view -0 + 538 .cfi_startproc + 539 @ args = 0, pretend = 0, frame = 0 + 540 @ frame_needed = 0, uses_anonymous_args = 0 + 16:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 541 .loc 1 16 1 is_stmt 0 view .LVU155 + 542 0000 10B5 push {r4, lr} + 543 .cfi_def_cfa_offset 8 + 544 .cfi_offset 4, -8 + 545 .cfi_offset 14, -4 + 546 0002 0446 mov r4, r0 + 17:Core/Src/ADBMS_LL_Driver.c **** HAL_Delay(1); + 547 .loc 1 17 2 is_stmt 1 view .LVU156 + 548 0004 FFF7FEFF bl mcuAdbmsCSLow + 549 .LVL66: + 18:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 550 .loc 1 18 2 view .LVU157 + 551 0008 0120 movs r0, #1 + 552 000a FFF7FEFF bl HAL_Delay + 553 .LVL67: + 19:Core/Src/ADBMS_LL_Driver.c **** adbmsspi = hspi; + 554 .loc 1 19 2 view .LVU158 + 555 000e FFF7FEFF bl mcuAdbmsCSHigh + 556 .LVL68: + 20:Core/Src/ADBMS_LL_Driver.c **** return 0; + 557 .loc 1 20 2 view .LVU159 + 20:Core/Src/ADBMS_LL_Driver.c **** return 0; + 558 .loc 1 20 11 is_stmt 0 view .LVU160 + 559 0012 024B ldr r3, .L35 + 560 0014 1C60 str r4, [r3] + 21:Core/Src/ADBMS_LL_Driver.c **** } + 561 .loc 1 21 2 is_stmt 1 view .LVU161 + 22:Core/Src/ADBMS_LL_Driver.c **** + 562 .loc 1 22 1 is_stmt 0 view .LVU162 + 563 0016 0020 movs r0, #0 + 564 0018 10BD pop {r4, pc} + 565 .LVL69: + 566 .L36: + 22:Core/Src/ADBMS_LL_Driver.c **** + 567 .loc 1 22 1 view .LVU163 + 568 001a 00BF .align 2 + 569 .L35: + 570 001c 00000000 .word adbmsspi + 571 .cfi_endproc + 572 .LFE130: + 574 .section .text.mcuSPITransmit,"ax",%progbits + 575 .align 1 + 576 .global mcuSPITransmit + 577 .syntax unified + 578 .thumb + 579 .thumb_func + 581 mcuSPITransmit: + 582 .LVL70: + 583 .LFB138: + 198:Core/Src/ADBMS_LL_Driver.c **** + ARM GAS /tmp/ccJRsTlY.s page 16 + + + 199:Core/Src/ADBMS_LL_Driver.c **** uint8 mcuSPITransmit(uint8* buffer, uint8 buffersize) + 200:Core/Src/ADBMS_LL_Driver.c **** { + 584 .loc 1 200 1 is_stmt 1 view -0 + 585 .cfi_startproc + 586 @ args = 0, pretend = 0, frame = 8 + 587 @ frame_needed = 1, uses_anonymous_args = 0 + 588 .loc 1 200 1 is_stmt 0 view .LVU165 + 589 0000 90B5 push {r4, r7, lr} + 590 .cfi_def_cfa_offset 12 + 591 .cfi_offset 4, -12 + 592 .cfi_offset 7, -8 + 593 .cfi_offset 14, -4 + 594 0002 85B0 sub sp, sp, #20 + 595 .cfi_def_cfa_offset 32 + 596 0004 02AF add r7, sp, #8 + 597 .cfi_def_cfa 7, 24 + 598 0006 0B46 mov r3, r1 + 201:Core/Src/ADBMS_LL_Driver.c **** HAL_StatusTypeDef status; + 599 .loc 1 201 2 is_stmt 1 view .LVU166 + 202:Core/Src/ADBMS_LL_Driver.c **** //status = HAL_SPI_Transmit(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOUT); + 203:Core/Src/ADBMS_LL_Driver.c **** //uint8 *rxbuf = (uint8*) malloc(buffersize); + 204:Core/Src/ADBMS_LL_Driver.c **** uint8 rxbuf[buffersize]; + 600 .loc 1 204 2 view .LVU167 + 601 .LVL71: + 602 .loc 1 204 8 is_stmt 0 view .LVU168 + 603 0008 CA1D adds r2, r1, #7 + 604 000a 02F4FC72 and r2, r2, #504 + 605 000e ADEB020D sub sp, sp, r2 + 606 0012 6A46 mov r2, sp + 607 .LVL72: + 205:Core/Src/ADBMS_LL_Driver.c **** status = HAL_SPI_TransmitReceive(adbmsspi, buffer, rxbuf, buffersize, ADBMS_SPI_TIMEOUT); + 608 .loc 1 205 2 is_stmt 1 view .LVU169 + 609 .loc 1 205 11 is_stmt 0 view .LVU170 + 610 0014 0A4C ldr r4, .L39 + 611 0016 4FF47A71 mov r1, #1000 + 612 .LVL73: + 613 .loc 1 205 11 view .LVU171 + 614 001a 42F8081B str r1, [r2], #8 + 615 .LVL74: + 616 .loc 1 205 11 view .LVU172 + 617 001e 0146 mov r1, r0 + 618 0020 2068 ldr r0, [r4] + 619 .LVL75: + 620 .loc 1 205 11 view .LVU173 + 621 0022 FFF7FEFF bl HAL_SPI_TransmitReceive + 622 .LVL76: + 206:Core/Src/ADBMS_LL_Driver.c **** __HAL_SPI_CLEAR_OVRFLAG(adbmsspi); + 623 .loc 1 206 2 is_stmt 1 view .LVU174 + 624 .LBB12: + 625 .loc 1 206 2 view .LVU175 + 626 0026 0023 movs r3, #0 + 627 0028 7B60 str r3, [r7, #4] + 628 .loc 1 206 2 view .LVU176 + 629 002a 2368 ldr r3, [r4] + 630 002c 1B68 ldr r3, [r3] + 631 002e DA68 ldr r2, [r3, #12] + 632 0030 7A60 str r2, [r7, #4] + ARM GAS /tmp/ccJRsTlY.s page 17 + + + 633 .loc 1 206 2 view .LVU177 + 634 0032 9B68 ldr r3, [r3, #8] + 635 0034 7B60 str r3, [r7, #4] + 636 .loc 1 206 2 view .LVU178 + 637 0036 7B68 ldr r3, [r7, #4] + 638 .LBE12: + 639 .loc 1 206 2 view .LVU179 + 207:Core/Src/ADBMS_LL_Driver.c **** //free(rxbuf); + 208:Core/Src/ADBMS_LL_Driver.c **** return status; + 640 .loc 1 208 2 view .LVU180 + 209:Core/Src/ADBMS_LL_Driver.c **** } + 641 .loc 1 209 1 is_stmt 0 view .LVU181 + 642 0038 0C37 adds r7, r7, #12 + 643 .cfi_def_cfa_offset 12 + 644 003a BD46 mov sp, r7 + 645 .cfi_def_cfa_register 13 + 646 .LVL77: + 647 .loc 1 209 1 view .LVU182 + 648 @ sp needed + 649 003c 90BD pop {r4, r7, pc} + 650 .L40: + 651 003e 00BF .align 2 + 652 .L39: + 653 0040 00000000 .word adbmsspi + 654 .cfi_endproc + 655 .LFE138: + 657 .section .text.writeCMD,"ax",%progbits + 658 .align 1 + 659 .global writeCMD + 660 .syntax unified + 661 .thumb + 662 .thumb_func + 664 writeCMD: + 665 .LVL78: + 666 .LFB134: + 113:Core/Src/ADBMS_LL_Driver.c **** if(arglen > 0) + 667 .loc 1 113 1 is_stmt 1 view -0 + 668 .cfi_startproc + 669 @ args = 0, pretend = 0, frame = 8 + 670 @ frame_needed = 1, uses_anonymous_args = 0 + 113:Core/Src/ADBMS_LL_Driver.c **** if(arglen > 0) + 671 .loc 1 113 1 is_stmt 0 view .LVU184 + 672 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 673 .cfi_def_cfa_offset 24 + 674 .cfi_offset 4, -24 + 675 .cfi_offset 5, -20 + 676 .cfi_offset 6, -16 + 677 .cfi_offset 7, -12 + 678 .cfi_offset 8, -8 + 679 .cfi_offset 14, -4 + 680 0004 82B0 sub sp, sp, #8 + 681 .cfi_def_cfa_offset 32 + 682 0006 00AF add r7, sp, #0 + 683 .cfi_def_cfa_register 7 + 114:Core/Src/ADBMS_LL_Driver.c **** { + 684 .loc 1 114 2 is_stmt 1 view .LVU185 + 114:Core/Src/ADBMS_LL_Driver.c **** { + ARM GAS /tmp/ccJRsTlY.s page 18 + + + 685 .loc 1 114 4 is_stmt 0 view .LVU186 + 686 0008 7AB3 cbz r2, .L42 + 687 000a 0D46 mov r5, r1 + 688 000c 1446 mov r4, r2 + 689 .LBB13: + 115:Core/Src/ADBMS_LL_Driver.c **** uint8 buffer[6+arglen]; + 690 .loc 1 115 2 view .LVU187 + 691 000e E846 mov r8, sp + 116:Core/Src/ADBMS_LL_Driver.c **** buffer[0] = (command >> 8) & 0xFF; + 692 .loc 1 116 2 is_stmt 1 view .LVU188 + 693 .LVL79: + 116:Core/Src/ADBMS_LL_Driver.c **** buffer[0] = (command >> 8) & 0xFF; + 694 .loc 1 116 8 is_stmt 0 view .LVU189 + 695 0010 02F10D03 add r3, r2, #13 + 696 0014 03F4FC73 and r3, r3, #504 + 697 0018 ADEB030D sub sp, sp, r3 + 698 001c 6E46 mov r6, sp + 699 .LVL80: + 117:Core/Src/ADBMS_LL_Driver.c **** buffer[1] = (command) & 0xFF; + 700 .loc 1 117 2 is_stmt 1 view .LVU190 + 117:Core/Src/ADBMS_LL_Driver.c **** buffer[1] = (command) & 0xFF; + 701 .loc 1 117 12 is_stmt 0 view .LVU191 + 702 001e 030A lsrs r3, r0, #8 + 703 0020 8DF80030 strb r3, [sp] + 118:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(buffer, 4); + 704 .loc 1 118 2 is_stmt 1 view .LVU192 + 118:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(buffer, 4); + 705 .loc 1 118 12 is_stmt 0 view .LVU193 + 706 0024 8DF80100 strb r0, [sp, #1] + 119:Core/Src/ADBMS_LL_Driver.c **** for(uint8 i = 0; i < arglen; i++) + 707 .loc 1 119 2 is_stmt 1 view .LVU194 + 708 0028 0421 movs r1, #4 + 709 .LVL81: + 119:Core/Src/ADBMS_LL_Driver.c **** for(uint8 i = 0; i < arglen; i++) + 710 .loc 1 119 2 is_stmt 0 view .LVU195 + 711 002a 6846 mov r0, sp + 712 .LVL82: + 119:Core/Src/ADBMS_LL_Driver.c **** for(uint8 i = 0; i < arglen; i++) + 713 .loc 1 119 2 view .LVU196 + 714 002c FFF7FEFF bl calculatePEC + 715 .LVL83: + 120:Core/Src/ADBMS_LL_Driver.c **** { + 716 .loc 1 120 2 is_stmt 1 view .LVU197 + 717 .LBB14: + 120:Core/Src/ADBMS_LL_Driver.c **** { + 718 .loc 1 120 6 view .LVU198 + 120:Core/Src/ADBMS_LL_Driver.c **** { + 719 .loc 1 120 12 is_stmt 0 view .LVU199 + 720 0030 0023 movs r3, #0 + 120:Core/Src/ADBMS_LL_Driver.c **** { + 721 .loc 1 120 2 view .LVU200 + 722 0032 04E0 b .L43 + 723 .LVL84: + 724 .L44: + 122:Core/Src/ADBMS_LL_Driver.c **** } + 725 .loc 1 122 3 is_stmt 1 discriminator 3 view .LVU201 + 122:Core/Src/ADBMS_LL_Driver.c **** } + ARM GAS /tmp/ccJRsTlY.s page 19 + + + 726 .loc 1 122 11 is_stmt 0 discriminator 3 view .LVU202 + 727 0034 1A1D adds r2, r3, #4 + 122:Core/Src/ADBMS_LL_Driver.c **** } + 728 .loc 1 122 21 discriminator 3 view .LVU203 + 729 0036 E95C ldrb r1, [r5, r3] @ zero_extendqisi2 + 122:Core/Src/ADBMS_LL_Driver.c **** } + 730 .loc 1 122 15 discriminator 3 view .LVU204 + 731 0038 B154 strb r1, [r6, r2] + 120:Core/Src/ADBMS_LL_Driver.c **** { + 732 .loc 1 120 32 is_stmt 1 discriminator 3 view .LVU205 + 733 003a 0133 adds r3, r3, #1 + 734 .LVL85: + 120:Core/Src/ADBMS_LL_Driver.c **** { + 735 .loc 1 120 32 is_stmt 0 discriminator 3 view .LVU206 + 736 003c DBB2 uxtb r3, r3 + 737 .LVL86: + 738 .L43: + 120:Core/Src/ADBMS_LL_Driver.c **** { + 739 .loc 1 120 21 is_stmt 1 discriminator 1 view .LVU207 + 740 003e A342 cmp r3, r4 + 741 0040 F8D3 bcc .L44 + 742 .LBE14: + 125:Core/Src/ADBMS_LL_Driver.c **** + 743 .loc 1 125 2 view .LVU208 + 744 0042 A11C adds r1, r4, #2 + 745 0044 C9B2 uxtb r1, r1 + 746 0046 301D adds r0, r6, #4 + 747 0048 FFF7FEFF bl calculatePEC + 748 .LVL87: + 127:Core/Src/ADBMS_LL_Driver.c **** mcuSPITransmit(buffer, 6+arglen); + 749 .loc 1 127 2 view .LVU209 + 750 004c FFF7FEFF bl mcuAdbmsCSLow + 751 .LVL88: + 128:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 752 .loc 1 128 2 view .LVU210 + 753 0050 A11D adds r1, r4, #6 + 754 0052 C9B2 uxtb r1, r1 + 755 0054 3046 mov r0, r6 + 756 0056 FFF7FEFF bl mcuSPITransmit + 757 .LVL89: + 129:Core/Src/ADBMS_LL_Driver.c **** + 758 .loc 1 129 2 view .LVU211 + 759 005a FFF7FEFF bl mcuAdbmsCSHigh + 760 .LVL90: + 761 005e C546 mov sp, r8 + 762 .LVL91: + 763 .L45: + 129:Core/Src/ADBMS_LL_Driver.c **** + 764 .loc 1 129 2 is_stmt 0 view .LVU212 + 765 .LBE13: + 146:Core/Src/ADBMS_LL_Driver.c **** } + 766 .loc 1 146 2 is_stmt 1 view .LVU213 + 147:Core/Src/ADBMS_LL_Driver.c **** + 767 .loc 1 147 1 is_stmt 0 view .LVU214 + 768 0060 0020 movs r0, #0 + 769 0062 0837 adds r7, r7, #8 + 770 .cfi_remember_state + ARM GAS /tmp/ccJRsTlY.s page 20 + + + 771 .cfi_def_cfa_offset 24 + 772 0064 BD46 mov sp, r7 + 773 .cfi_def_cfa_register 13 + 774 @ sp needed + 775 0066 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 776 .LVL92: + 777 .L42: + 778 .cfi_restore_state + 779 .LBB15: + 134:Core/Src/ADBMS_LL_Driver.c **** buffer[0] = (command >> 8) & 0xFF; + 780 .loc 1 134 2 is_stmt 1 view .LVU215 + 135:Core/Src/ADBMS_LL_Driver.c **** buffer[1] = (command) & 0xFF; + 781 .loc 1 135 2 view .LVU216 + 135:Core/Src/ADBMS_LL_Driver.c **** buffer[1] = (command) & 0xFF; + 782 .loc 1 135 12 is_stmt 0 view .LVU217 + 783 006a 030A lsrs r3, r0, #8 + 784 006c 3B71 strb r3, [r7, #4] + 136:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(buffer, 4); + 785 .loc 1 136 2 is_stmt 1 view .LVU218 + 136:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(buffer, 4); + 786 .loc 1 136 12 is_stmt 0 view .LVU219 + 787 006e 7871 strb r0, [r7, #5] + 137:Core/Src/ADBMS_LL_Driver.c **** + 788 .loc 1 137 2 is_stmt 1 view .LVU220 + 789 0070 0421 movs r1, #4 + 790 .LVL93: + 137:Core/Src/ADBMS_LL_Driver.c **** + 791 .loc 1 137 2 is_stmt 0 view .LVU221 + 792 0072 7818 adds r0, r7, r1 + 793 .LVL94: + 137:Core/Src/ADBMS_LL_Driver.c **** + 794 .loc 1 137 2 view .LVU222 + 795 0074 FFF7FEFF bl calculatePEC + 796 .LVL95: + 139:Core/Src/ADBMS_LL_Driver.c **** + 797 .loc 1 139 2 is_stmt 1 view .LVU223 + 798 0078 FFF7FEFF bl mcuAdbmsCSLow + 799 .LVL96: + 141:Core/Src/ADBMS_LL_Driver.c **** + 800 .loc 1 141 2 view .LVU224 + 801 007c 0421 movs r1, #4 + 802 007e 7818 adds r0, r7, r1 + 803 0080 FFF7FEFF bl mcuSPITransmit + 804 .LVL97: + 143:Core/Src/ADBMS_LL_Driver.c **** } + 805 .loc 1 143 2 view .LVU225 + 806 0084 FFF7FEFF bl mcuAdbmsCSHigh + 807 .LVL98: + 808 0088 EAE7 b .L45 + 809 .LBE15: + 810 .cfi_endproc + 811 .LFE134: + 813 .section .text.mcuSPIReceive,"ax",%progbits + 814 .align 1 + 815 .global mcuSPIReceive + 816 .syntax unified + 817 .thumb + ARM GAS /tmp/ccJRsTlY.s page 21 + + + 818 .thumb_func + 820 mcuSPIReceive: + 821 .LVL99: + 822 .LFB139: + 210:Core/Src/ADBMS_LL_Driver.c **** + 211:Core/Src/ADBMS_LL_Driver.c **** uint8 mcuSPIReceive(uint8* buffer, uint8 buffersize) + 212:Core/Src/ADBMS_LL_Driver.c **** { + 823 .loc 1 212 1 view -0 + 824 .cfi_startproc + 825 @ args = 0, pretend = 0, frame = 0 + 826 @ frame_needed = 0, uses_anonymous_args = 0 + 827 .loc 1 212 1 is_stmt 0 view .LVU227 + 828 0000 08B5 push {r3, lr} + 829 .cfi_def_cfa_offset 8 + 830 .cfi_offset 3, -8 + 831 .cfi_offset 14, -4 + 832 0002 0A46 mov r2, r1 + 213:Core/Src/ADBMS_LL_Driver.c **** HAL_StatusTypeDef status; + 833 .loc 1 213 2 is_stmt 1 view .LVU228 + 214:Core/Src/ADBMS_LL_Driver.c **** status = HAL_SPI_Receive(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOUT); + 834 .loc 1 214 2 view .LVU229 + 835 .loc 1 214 11 is_stmt 0 view .LVU230 + 836 0004 4FF47A73 mov r3, #1000 + 837 0008 0146 mov r1, r0 + 838 .LVL100: + 839 .loc 1 214 11 view .LVU231 + 840 000a 0248 ldr r0, .L49 + 841 .LVL101: + 842 .loc 1 214 11 view .LVU232 + 843 000c 0068 ldr r0, [r0] + 844 000e FFF7FEFF bl HAL_SPI_Receive + 845 .LVL102: + 215:Core/Src/ADBMS_LL_Driver.c **** return status; + 846 .loc 1 215 2 is_stmt 1 view .LVU233 + 216:Core/Src/ADBMS_LL_Driver.c **** } + 847 .loc 1 216 1 is_stmt 0 view .LVU234 + 848 0012 08BD pop {r3, pc} + 849 .L50: + 850 .align 2 + 851 .L49: + 852 0014 00000000 .word adbmsspi + 853 .cfi_endproc + 854 .LFE139: + 856 .section .text.mcuSPITransmitReceive,"ax",%progbits + 857 .align 1 + 858 .global mcuSPITransmitReceive + 859 .syntax unified + 860 .thumb + 861 .thumb_func + 863 mcuSPITransmitReceive: + 864 .LVL103: + 865 .LFB140: + 217:Core/Src/ADBMS_LL_Driver.c **** + 218:Core/Src/ADBMS_LL_Driver.c **** uint8 mcuSPITransmitReceive(uint8* rxbuffer, uint8* txbuffer, uint8 buffersize) + 219:Core/Src/ADBMS_LL_Driver.c **** { + 866 .loc 1 219 1 is_stmt 1 view -0 + 867 .cfi_startproc + ARM GAS /tmp/ccJRsTlY.s page 22 + + + 868 @ args = 0, pretend = 0, frame = 0 + 869 @ frame_needed = 0, uses_anonymous_args = 0 + 870 .loc 1 219 1 is_stmt 0 view .LVU236 + 871 0000 00B5 push {lr} + 872 .cfi_def_cfa_offset 4 + 873 .cfi_offset 14, -4 + 874 0002 83B0 sub sp, sp, #12 + 875 .cfi_def_cfa_offset 16 + 876 0004 1346 mov r3, r2 + 220:Core/Src/ADBMS_LL_Driver.c **** HAL_StatusTypeDef status; + 877 .loc 1 220 2 is_stmt 1 view .LVU237 + 221:Core/Src/ADBMS_LL_Driver.c **** status = HAL_SPI_TransmitReceive(adbmsspi, txbuffer, rxbuffer, buffersize, ADBMS_SPI_TIMEOUT); + 878 .loc 1 221 2 view .LVU238 + 879 .loc 1 221 11 is_stmt 0 view .LVU239 + 880 0006 4FF47A72 mov r2, #1000 + 881 .LVL104: + 882 .loc 1 221 11 view .LVU240 + 883 000a 0092 str r2, [sp] + 884 000c 0246 mov r2, r0 + 885 000e 0348 ldr r0, .L53 + 886 .LVL105: + 887 .loc 1 221 11 view .LVU241 + 888 0010 0068 ldr r0, [r0] + 889 0012 FFF7FEFF bl HAL_SPI_TransmitReceive + 890 .LVL106: + 222:Core/Src/ADBMS_LL_Driver.c **** return status; + 891 .loc 1 222 2 is_stmt 1 view .LVU242 + 223:Core/Src/ADBMS_LL_Driver.c **** } + 892 .loc 1 223 1 is_stmt 0 view .LVU243 + 893 0016 03B0 add sp, sp, #12 + 894 .cfi_def_cfa_offset 4 + 895 @ sp needed + 896 0018 5DF804FB ldr pc, [sp], #4 + 897 .L54: + 898 .align 2 + 899 .L53: + 900 001c 00000000 .word adbmsspi + 901 .cfi_endproc + 902 .LFE140: + 904 .section .text.readCMD,"ax",%progbits + 905 .align 1 + 906 .global readCMD + 907 .syntax unified + 908 .thumb + 909 .thumb_func + 911 readCMD: + 912 .LVL107: + 913 .LFB135: + 150:Core/Src/ADBMS_LL_Driver.c **** //uint8* txbuffer = (uint8*) malloc(6+buflen); + 914 .loc 1 150 1 is_stmt 1 view -0 + 915 .cfi_startproc + 916 @ args = 0, pretend = 0, frame = 0 + 917 @ frame_needed = 1, uses_anonymous_args = 0 + 150:Core/Src/ADBMS_LL_Driver.c **** //uint8* txbuffer = (uint8*) malloc(6+buflen); + 918 .loc 1 150 1 is_stmt 0 view .LVU245 + 919 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 920 .cfi_def_cfa_offset 32 + ARM GAS /tmp/ccJRsTlY.s page 23 + + + 921 .cfi_offset 3, -32 + 922 .cfi_offset 4, -28 + 923 .cfi_offset 5, -24 + 924 .cfi_offset 6, -20 + 925 .cfi_offset 7, -16 + 926 .cfi_offset 8, -12 + 927 .cfi_offset 9, -8 + 928 .cfi_offset 14, -4 + 929 0004 00AF add r7, sp, #0 + 930 .cfi_def_cfa_register 7 + 931 0006 0E46 mov r6, r1 + 932 0008 1446 mov r4, r2 + 153:Core/Src/ADBMS_LL_Driver.c **** uint8 rxbuffer[6+buflen]; + 933 .loc 1 153 2 is_stmt 1 view .LVU246 + 153:Core/Src/ADBMS_LL_Driver.c **** uint8 rxbuffer[6+buflen]; + 934 .loc 1 153 18 is_stmt 0 view .LVU247 + 935 000a 02F10609 add r9, r2, #6 + 936 .LVL108: + 153:Core/Src/ADBMS_LL_Driver.c **** uint8 rxbuffer[6+buflen]; + 937 .loc 1 153 8 view .LVU248 + 938 000e 02F10D03 add r3, r2, #13 + 939 0012 03F4FC73 and r3, r3, #504 + 940 0016 ADEB030D sub sp, sp, r3 + 941 001a E846 mov r8, sp + 942 .LVL109: + 154:Core/Src/ADBMS_LL_Driver.c **** + 943 .loc 1 154 2 is_stmt 1 view .LVU249 + 154:Core/Src/ADBMS_LL_Driver.c **** + 944 .loc 1 154 8 is_stmt 0 view .LVU250 + 945 001c ADEB030D sub sp, sp, r3 + 946 0020 6D46 mov r5, sp + 947 .LVL110: + 156:Core/Src/ADBMS_LL_Driver.c **** txbuffer[1] = (command) & 0xFF; + 948 .loc 1 156 2 is_stmt 1 view .LVU251 + 156:Core/Src/ADBMS_LL_Driver.c **** txbuffer[1] = (command) & 0xFF; + 949 .loc 1 156 14 is_stmt 0 view .LVU252 + 950 0022 030A lsrs r3, r0, #8 + 951 0024 88F80030 strb r3, [r8] + 157:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(txbuffer, 4); + 952 .loc 1 157 2 is_stmt 1 view .LVU253 + 157:Core/Src/ADBMS_LL_Driver.c **** calculatePEC(txbuffer, 4); + 953 .loc 1 157 14 is_stmt 0 view .LVU254 + 954 0028 88F80100 strb r0, [r8, #1] + 158:Core/Src/ADBMS_LL_Driver.c **** + 955 .loc 1 158 2 is_stmt 1 view .LVU255 + 956 002c 0421 movs r1, #4 + 957 .LVL111: + 158:Core/Src/ADBMS_LL_Driver.c **** + 958 .loc 1 158 2 is_stmt 0 view .LVU256 + 959 002e 4046 mov r0, r8 + 960 .LVL112: + 158:Core/Src/ADBMS_LL_Driver.c **** + 961 .loc 1 158 2 view .LVU257 + 962 0030 FFF7FEFF bl calculatePEC + 963 .LVL113: + 160:Core/Src/ADBMS_LL_Driver.c **** mcuSPITransmitReceive(rxbuffer, txbuffer, 6+buflen); + 964 .loc 1 160 2 is_stmt 1 view .LVU258 + ARM GAS /tmp/ccJRsTlY.s page 24 + + + 965 0034 FFF7FEFF bl mcuAdbmsCSLow + 966 .LVL114: + 161:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 967 .loc 1 161 2 view .LVU259 + 968 0038 5FFA89F2 uxtb r2, r9 + 969 003c 4146 mov r1, r8 + 970 003e 6846 mov r0, sp + 971 0040 FFF7FEFF bl mcuSPITransmitReceive + 972 .LVL115: + 162:Core/Src/ADBMS_LL_Driver.c **** + 973 .loc 1 162 2 view .LVU260 + 974 0044 FFF7FEFF bl mcuAdbmsCSHigh + 975 .LVL116: + 165:Core/Src/ADBMS_LL_Driver.c **** { + 976 .loc 1 165 2 view .LVU261 + 977 .LBB16: + 165:Core/Src/ADBMS_LL_Driver.c **** { + 978 .loc 1 165 6 view .LVU262 + 165:Core/Src/ADBMS_LL_Driver.c **** { + 979 .loc 1 165 12 is_stmt 0 view .LVU263 + 980 0048 0023 movs r3, #0 + 165:Core/Src/ADBMS_LL_Driver.c **** { + 981 .loc 1 165 2 view .LVU264 + 982 004a 04E0 b .L56 + 983 .LVL117: + 984 .L57: + 167:Core/Src/ADBMS_LL_Driver.c **** } + 985 .loc 1 167 3 is_stmt 1 discriminator 3 view .LVU265 + 167:Core/Src/ADBMS_LL_Driver.c **** } + 986 .loc 1 167 25 is_stmt 0 discriminator 3 view .LVU266 + 987 004c 1A1D adds r2, r3, #4 + 167:Core/Src/ADBMS_LL_Driver.c **** } + 988 .loc 1 167 23 discriminator 3 view .LVU267 + 989 004e AA5C ldrb r2, [r5, r2] @ zero_extendqisi2 + 167:Core/Src/ADBMS_LL_Driver.c **** } + 990 .loc 1 167 13 discriminator 3 view .LVU268 + 991 0050 F254 strb r2, [r6, r3] + 165:Core/Src/ADBMS_LL_Driver.c **** { + 992 .loc 1 165 30 is_stmt 1 discriminator 3 view .LVU269 + 993 0052 0133 adds r3, r3, #1 + 994 .LVL118: + 165:Core/Src/ADBMS_LL_Driver.c **** { + 995 .loc 1 165 30 is_stmt 0 discriminator 3 view .LVU270 + 996 0054 DBB2 uxtb r3, r3 + 997 .LVL119: + 998 .L56: + 165:Core/Src/ADBMS_LL_Driver.c **** { + 999 .loc 1 165 20 is_stmt 1 discriminator 1 view .LVU271 + 1000 0056 A342 cmp r3, r4 + 1001 0058 F8D3 bcc .L57 + 1002 .LBE16: + 170:Core/Src/ADBMS_LL_Driver.c **** + 1003 .loc 1 170 2 view .LVU272 + 170:Core/Src/ADBMS_LL_Driver.c **** + 1004 .loc 1 170 19 is_stmt 0 view .LVU273 + 1005 005a A11C adds r1, r4, #2 + 1006 005c C9B2 uxtb r1, r1 + ARM GAS /tmp/ccJRsTlY.s page 25 + + + 1007 005e 281D adds r0, r5, #4 + 1008 0060 FFF7FEFF bl checkPEC + 1009 .LVL120: + 175:Core/Src/ADBMS_LL_Driver.c **** return 0; + 1010 .loc 1 175 2 is_stmt 1 view .LVU274 + 175:Core/Src/ADBMS_LL_Driver.c **** return 0; + 1011 .loc 1 175 4 is_stmt 0 view .LVU275 + 1012 0064 30B1 cbz r0, .L55 + 1013 .LBB17: + 179:Core/Src/ADBMS_LL_Driver.c **** if (err_cnt++ > 100) { + 1014 .loc 1 179 3 is_stmt 1 view .LVU276 + 180:Core/Src/ADBMS_LL_Driver.c **** Error_Handler(); + 1015 .loc 1 180 3 view .LVU277 + 180:Core/Src/ADBMS_LL_Driver.c **** Error_Handler(); + 1016 .loc 1 180 14 is_stmt 0 view .LVU278 + 1017 0066 064A ldr r2, .L62 + 1018 0068 1368 ldr r3, [r2] + 1019 006a 591C adds r1, r3, #1 + 1020 006c 1160 str r1, [r2] + 180:Core/Src/ADBMS_LL_Driver.c **** Error_Handler(); + 1021 .loc 1 180 6 view .LVU279 + 1022 006e 642B cmp r3, #100 + 1023 0070 03DC bgt .L61 + 183:Core/Src/ADBMS_LL_Driver.c **** } + 1024 .loc 1 183 11 view .LVU280 + 1025 0072 0120 movs r0, #1 + 1026 .LVL121: + 1027 .L55: + 183:Core/Src/ADBMS_LL_Driver.c **** } + 1028 .loc 1 183 11 view .LVU281 + 1029 .LBE17: + 187:Core/Src/ADBMS_LL_Driver.c **** + 1030 .loc 1 187 1 view .LVU282 + 1031 0074 BD46 mov sp, r7 + 1032 .cfi_remember_state + 1033 .cfi_def_cfa_register 13 + 1034 @ sp needed + 1035 0076 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 1036 .LVL122: + 1037 .L61: + 1038 .cfi_restore_state + 1039 .LBB18: + 181:Core/Src/ADBMS_LL_Driver.c **** } else { + 1040 .loc 1 181 3 is_stmt 1 view .LVU283 + 1041 007a FFF7FEFF bl Error_Handler + 1042 .LVL123: + 181:Core/Src/ADBMS_LL_Driver.c **** } else { + 1043 .loc 1 181 3 is_stmt 0 view .LVU284 + 1044 .LBE18: + 187:Core/Src/ADBMS_LL_Driver.c **** + 1045 .loc 1 187 1 view .LVU285 + 1046 007e F9E7 b .L55 + 1047 .L63: + 1048 .align 2 + 1049 .L62: + 1050 0080 00000000 .word err_cnt.0 + 1051 .cfi_endproc + ARM GAS /tmp/ccJRsTlY.s page 26 + + + 1052 .LFE135: + 1054 .section .text.mcuDelay,"ax",%progbits + 1055 .align 1 + 1056 .global mcuDelay + 1057 .syntax unified + 1058 .thumb + 1059 .thumb_func + 1061 mcuDelay: + 1062 .LVL124: + 1063 .LFB141: + 224:Core/Src/ADBMS_LL_Driver.c **** + 225:Core/Src/ADBMS_LL_Driver.c **** inline void mcuDelay(uint16 delay) + 226:Core/Src/ADBMS_LL_Driver.c **** { + 1064 .loc 1 226 1 is_stmt 1 view -0 + 1065 .cfi_startproc + 1066 @ args = 0, pretend = 0, frame = 0 + 1067 @ frame_needed = 0, uses_anonymous_args = 0 + 1068 .loc 1 226 1 is_stmt 0 view .LVU287 + 1069 0000 08B5 push {r3, lr} + 1070 .cfi_def_cfa_offset 8 + 1071 .cfi_offset 3, -8 + 1072 .cfi_offset 14, -4 + 227:Core/Src/ADBMS_LL_Driver.c **** HAL_Delay(delay); + 1073 .loc 1 227 2 is_stmt 1 view .LVU288 + 1074 0002 FFF7FEFF bl HAL_Delay + 1075 .LVL125: + 228:Core/Src/ADBMS_LL_Driver.c **** } + 1076 .loc 1 228 1 is_stmt 0 view .LVU289 + 1077 0006 08BD pop {r3, pc} + 1078 .cfi_endproc + 1079 .LFE141: + 1081 .section .bss.err_cnt.0,"aw",%nobits + 1082 .align 2 + 1085 err_cnt.0: + 1086 0000 00000000 .space 4 + 1087 .global adbmsspi + 1088 .section .bss.adbmsspi,"aw",%nobits + 1089 .align 2 + 1092 adbmsspi: + 1093 0000 00000000 .space 4 + 1094 .text + 1095 .Letext0: + 1096 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1097 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1098 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1099 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1100 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 1101 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 1102 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 1103 .file 9 "Core/Inc/ADBMS_LL_Driver.h" + 1104 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 1105 .file 11 "Core/Inc/main.h" + ARM GAS /tmp/ccJRsTlY.s page 27 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 ADBMS_LL_Driver.c + /tmp/ccJRsTlY.s:21 .text.updatePEC:0000000000000000 $t + /tmp/ccJRsTlY.s:27 .text.updatePEC:0000000000000000 updatePEC + /tmp/ccJRsTlY.s:191 .text.calculatePEC:0000000000000000 $t + /tmp/ccJRsTlY.s:197 .text.calculatePEC:0000000000000000 calculatePEC + /tmp/ccJRsTlY.s:319 .text.checkPEC:0000000000000000 $t + /tmp/ccJRsTlY.s:325 .text.checkPEC:0000000000000000 checkPEC + /tmp/ccJRsTlY.s:472 .text.mcuAdbmsCSLow:0000000000000000 $t + /tmp/ccJRsTlY.s:478 .text.mcuAdbmsCSLow:0000000000000000 mcuAdbmsCSLow + /tmp/ccJRsTlY.s:500 .text.mcuAdbmsCSHigh:0000000000000000 $t + /tmp/ccJRsTlY.s:506 .text.mcuAdbmsCSHigh:0000000000000000 mcuAdbmsCSHigh + /tmp/ccJRsTlY.s:528 .text.adbmsDriverInit:0000000000000000 $t + /tmp/ccJRsTlY.s:534 .text.adbmsDriverInit:0000000000000000 adbmsDriverInit + /tmp/ccJRsTlY.s:570 .text.adbmsDriverInit:000000000000001c $d + /tmp/ccJRsTlY.s:1092 .bss.adbmsspi:0000000000000000 adbmsspi + /tmp/ccJRsTlY.s:575 .text.mcuSPITransmit:0000000000000000 $t + /tmp/ccJRsTlY.s:581 .text.mcuSPITransmit:0000000000000000 mcuSPITransmit + /tmp/ccJRsTlY.s:653 .text.mcuSPITransmit:0000000000000040 $d + /tmp/ccJRsTlY.s:658 .text.writeCMD:0000000000000000 $t + /tmp/ccJRsTlY.s:664 .text.writeCMD:0000000000000000 writeCMD + /tmp/ccJRsTlY.s:814 .text.mcuSPIReceive:0000000000000000 $t + /tmp/ccJRsTlY.s:820 .text.mcuSPIReceive:0000000000000000 mcuSPIReceive + /tmp/ccJRsTlY.s:852 .text.mcuSPIReceive:0000000000000014 $d + /tmp/ccJRsTlY.s:857 .text.mcuSPITransmitReceive:0000000000000000 $t + /tmp/ccJRsTlY.s:863 .text.mcuSPITransmitReceive:0000000000000000 mcuSPITransmitReceive + /tmp/ccJRsTlY.s:900 .text.mcuSPITransmitReceive:000000000000001c $d + /tmp/ccJRsTlY.s:905 .text.readCMD:0000000000000000 $t + /tmp/ccJRsTlY.s:911 .text.readCMD:0000000000000000 readCMD + /tmp/ccJRsTlY.s:1050 .text.readCMD:0000000000000080 $d + /tmp/ccJRsTlY.s:1085 .bss.err_cnt.0:0000000000000000 err_cnt.0 + /tmp/ccJRsTlY.s:1055 .text.mcuDelay:0000000000000000 $t + /tmp/ccJRsTlY.s:1061 .text.mcuDelay:0000000000000000 mcuDelay + /tmp/ccJRsTlY.s:1082 .bss.err_cnt.0:0000000000000000 $d + /tmp/ccJRsTlY.s:1089 .bss.adbmsspi:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_GPIO_WritePin +HAL_Delay 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Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_LL_Driver.h \ + Core/Inc/ADBMS_CMD_MAKROS.h Core/Inc/common_defs.h Core/Inc/main.h \ + Core/Inc/AMS_HighLevel.h Core/Inc/ADBMS_Abstraction.h +Core/Inc/AMS_CAN.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/common_defs.h: +Core/Inc/main.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/AMS_CAN.lst b/BMS_Testbench/BMS_Software_V1/build/AMS_CAN.lst new file mode 100644 index 0000000..ce50efe --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/AMS_CAN.lst @@ -0,0 +1,942 @@ +ARM GAS /tmp/ccf8kWw2.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "AMS_CAN.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/AMS_CAN.c" + 20 .section .text.ams_can_init,"ax",%progbits + 21 .align 1 + 22 .global ams_can_init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 ams_can_init: + 28 .LVL0: + 29 .LFB130: + 1:Core/Src/AMS_CAN.c **** /* + 2:Core/Src/AMS_CAN.c **** * AMS_CAN.c + 3:Core/Src/AMS_CAN.c **** * + 4:Core/Src/AMS_CAN.c **** * Created on: Mar 19, 2022 + 5:Core/Src/AMS_CAN.c **** * Author: jasper + 6:Core/Src/AMS_CAN.c **** */ + 7:Core/Src/AMS_CAN.c **** + 8:Core/Src/AMS_CAN.c **** #include "AMS_CAN.h" + 9:Core/Src/AMS_CAN.c **** + 10:Core/Src/AMS_CAN.c **** #include "ADBMS_Abstraction.h" + 11:Core/Src/AMS_CAN.c **** + 12:Core/Src/AMS_CAN.c **** + 13:Core/Src/AMS_CAN.c **** #include "common_defs.h" + 14:Core/Src/AMS_CAN.c **** #include "main.h" + 15:Core/Src/AMS_CAN.c **** #include "AMS_HighLevel.h" + 16:Core/Src/AMS_CAN.c **** #include "stm32f3xx.h" + 17:Core/Src/AMS_CAN.c **** #include "stm32f3xx_hal.h" + 18:Core/Src/AMS_CAN.c **** #include "stm32f3xx_hal_can.h" + 19:Core/Src/AMS_CAN.c **** + 20:Core/Src/AMS_CAN.c **** #include + 21:Core/Src/AMS_CAN.c **** + 22:Core/Src/AMS_CAN.c **** int PENDING_MESSAGE_HANDLE = 0; + 23:Core/Src/AMS_CAN.c **** uint8_t canTestData[8] = {0,0,0,0,0,0,0,0}; + 24:Core/Src/AMS_CAN.c **** + 25:Core/Src/AMS_CAN.c **** + 26:Core/Src/AMS_CAN.c **** CAN_HandleTypeDef* ams_can_handle; + 27:Core/Src/AMS_CAN.c **** + 28:Core/Src/AMS_CAN.c **** void ams_can_init(CAN_HandleTypeDef* ams_handle, + 29:Core/Src/AMS_CAN.c **** CAN_HandleTypeDef* car_handle) { + ARM GAS /tmp/ccf8kWw2.s page 2 + + + 30 .loc 1 29 50 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 40 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 .loc 1 29 50 is_stmt 0 view .LVU1 + 35 0000 10B5 push {r4, lr} + 36 .cfi_def_cfa_offset 8 + 37 .cfi_offset 4, -8 + 38 .cfi_offset 14, -4 + 39 0002 8AB0 sub sp, sp, #40 + 40 .cfi_def_cfa_offset 48 + 41 0004 0C46 mov r4, r1 + 30:Core/Src/AMS_CAN.c **** ams_can_handle = ams_handle; + 42 .loc 1 30 3 is_stmt 1 view .LVU2 + 43 .loc 1 30 18 is_stmt 0 view .LVU3 + 44 0006 204B ldr r3, .L11 + 45 0008 1860 str r0, [r3] + 31:Core/Src/AMS_CAN.c **** + 32:Core/Src/AMS_CAN.c **** // Start peripheral + 33:Core/Src/AMS_CAN.c **** if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { + 46 .loc 1 33 3 is_stmt 1 view .LVU4 + 47 .loc 1 33 7 is_stmt 0 view .LVU5 + 48 000a FFF7FEFF bl HAL_CAN_Start + 49 .LVL1: + 50 .loc 1 33 6 view .LVU6 + 51 000e 40BB cbnz r0, .L7 + 52 .L2: + 34:Core/Src/AMS_CAN.c **** ams_can_handle = car_handle; + 35:Core/Src/AMS_CAN.c **** if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { + 36:Core/Src/AMS_CAN.c **** Error_Handler(); + 37:Core/Src/AMS_CAN.c **** } + 38:Core/Src/AMS_CAN.c **** } + 39:Core/Src/AMS_CAN.c **** + 40:Core/Src/AMS_CAN.c **** // Config filter + 41:Core/Src/AMS_CAN.c **** CAN_FilterTypeDef can_filter; + 53 .loc 1 41 3 is_stmt 1 view .LVU7 + 42:Core/Src/AMS_CAN.c **** can_filter.FilterActivation = CAN_FILTER_ENABLE; + 54 .loc 1 42 3 view .LVU8 + 55 .loc 1 42 31 is_stmt 0 view .LVU9 + 56 0010 0122 movs r2, #1 + 57 0012 0892 str r2, [sp, #32] + 43:Core/Src/AMS_CAN.c **** can_filter.FilterBank = 0; + 58 .loc 1 43 3 is_stmt 1 view .LVU10 + 59 .loc 1 43 25 is_stmt 0 view .LVU11 + 60 0014 0023 movs r3, #0 + 61 0016 0593 str r3, [sp, #20] + 44:Core/Src/AMS_CAN.c **** can_filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; + 62 .loc 1 44 3 is_stmt 1 view .LVU12 + 63 .loc 1 44 35 is_stmt 0 view .LVU13 + 64 0018 0493 str r3, [sp, #16] + 45:Core/Src/AMS_CAN.c **** /* Message ID is in the MSBs of the FilterId register */ + 46:Core/Src/AMS_CAN.c **** can_filter.FilterIdHigh = CAN_ID_CLOCK_SYNC << (16 - 11); + 65 .loc 1 46 3 is_stmt 1 view .LVU14 + 66 .loc 1 46 27 is_stmt 0 view .LVU15 + 67 001a 4021 movs r1, #64 + 68 001c 0091 str r1, [sp] + 47:Core/Src/AMS_CAN.c **** can_filter.FilterIdLow = 0; + ARM GAS /tmp/ccf8kWw2.s page 3 + + + 69 .loc 1 47 3 is_stmt 1 view .LVU16 + 70 .loc 1 47 26 is_stmt 0 view .LVU17 + 71 001e 0193 str r3, [sp, #4] + 48:Core/Src/AMS_CAN.c **** /* Filter the 11 MSBs (i.e. a StdId) */ + 49:Core/Src/AMS_CAN.c **** + 50:Core/Src/AMS_CAN.c **** if(BMS_IN_TEST_MODE == 1){ + 72 .loc 1 50 3 is_stmt 1 view .LVU18 + 51:Core/Src/AMS_CAN.c **** can_filter.FilterMaskIdHigh = BMS_TEST_ID; // alleNachrichtenIds werden akzeptiert + 73 .loc 1 51 4 view .LVU19 + 74 .loc 1 51 32 is_stmt 0 view .LVU20 + 75 0020 0293 str r3, [sp, #8] + 52:Core/Src/AMS_CAN.c **** }else{ + 53:Core/Src/AMS_CAN.c **** can_filter.FilterMaskIdHigh = 0xFFE0; + 54:Core/Src/AMS_CAN.c **** } + 55:Core/Src/AMS_CAN.c **** + 56:Core/Src/AMS_CAN.c **** can_filter.FilterMaskIdLow = 0; + 76 .loc 1 56 3 is_stmt 1 view .LVU21 + 77 .loc 1 56 30 is_stmt 0 view .LVU22 + 78 0022 0393 str r3, [sp, #12] + 57:Core/Src/AMS_CAN.c **** can_filter.FilterMode = CAN_FILTERMODE_IDMASK; + 79 .loc 1 57 3 is_stmt 1 view .LVU23 + 80 .loc 1 57 25 is_stmt 0 view .LVU24 + 81 0024 0693 str r3, [sp, #24] + 58:Core/Src/AMS_CAN.c **** can_filter.FilterScale = CAN_FILTERSCALE_32BIT; + 82 .loc 1 58 3 is_stmt 1 view .LVU25 + 83 .loc 1 58 26 is_stmt 0 view .LVU26 + 84 0026 0792 str r2, [sp, #28] + 59:Core/Src/AMS_CAN.c **** can_filter.SlaveStartFilterBank = 0; + 85 .loc 1 59 3 is_stmt 1 view .LVU27 + 86 .loc 1 59 35 is_stmt 0 view .LVU28 + 87 0028 0993 str r3, [sp, #36] + 60:Core/Src/AMS_CAN.c **** if (HAL_CAN_ConfigFilter(ams_can_handle, &can_filter) != HAL_OK) { + 88 .loc 1 60 3 is_stmt 1 view .LVU29 + 89 .loc 1 60 7 is_stmt 0 view .LVU30 + 90 002a 6946 mov r1, sp + 91 002c 164B ldr r3, .L11 + 92 002e 1868 ldr r0, [r3] + 93 0030 FFF7FEFF bl HAL_CAN_ConfigFilter + 94 .LVL2: + 95 .loc 1 60 6 view .LVU31 + 96 0034 F8B9 cbnz r0, .L8 + 97 .L3: + 61:Core/Src/AMS_CAN.c **** Error_Handler(); + 62:Core/Src/AMS_CAN.c **** } + 63:Core/Src/AMS_CAN.c **** can_filter.FilterBank++; + 98 .loc 1 63 3 is_stmt 1 view .LVU32 + 99 .loc 1 63 13 is_stmt 0 view .LVU33 + 100 0036 059B ldr r3, [sp, #20] + 101 .loc 1 63 24 view .LVU34 + 102 0038 0133 adds r3, r3, #1 + 103 003a 0593 str r3, [sp, #20] + 64:Core/Src/AMS_CAN.c **** can_filter.FilterIdHigh = CAN_ID_MASTER_HEARTBEAT << (16 - 11); + 104 .loc 1 64 3 is_stmt 1 view .LVU35 + 105 .loc 1 64 27 is_stmt 0 view .LVU36 + 106 003c 4FF40073 mov r3, #512 + 107 0040 0093 str r3, [sp] + 65:Core/Src/AMS_CAN.c **** can_filter.FilterIdLow = 0; + ARM GAS /tmp/ccf8kWw2.s page 4 + + + 108 .loc 1 65 3 is_stmt 1 view .LVU37 + 109 .loc 1 65 26 is_stmt 0 view .LVU38 + 110 0042 0023 movs r3, #0 + 111 0044 0193 str r3, [sp, #4] + 66:Core/Src/AMS_CAN.c **** if (HAL_CAN_ConfigFilter(ams_can_handle, &can_filter) != HAL_OK) { + 112 .loc 1 66 3 is_stmt 1 view .LVU39 + 113 .loc 1 66 7 is_stmt 0 view .LVU40 + 114 0046 6946 mov r1, sp + 115 0048 0F4B ldr r3, .L11 + 116 004a 1868 ldr r0, [r3] + 117 004c FFF7FEFF bl HAL_CAN_ConfigFilter + 118 .LVL3: + 119 .loc 1 66 6 view .LVU41 + 120 0050 A0B9 cbnz r0, .L9 + 121 .L4: + 67:Core/Src/AMS_CAN.c **** Error_Handler(); + 68:Core/Src/AMS_CAN.c **** } + 69:Core/Src/AMS_CAN.c **** + 70:Core/Src/AMS_CAN.c **** // Activate RX notifications + 71:Core/Src/AMS_CAN.c **** if (HAL_CAN_ActivateNotification(ams_can_handle, + 122 .loc 1 71 3 is_stmt 1 view .LVU42 + 123 .loc 1 71 7 is_stmt 0 view .LVU43 + 124 0052 0221 movs r1, #2 + 125 0054 0C4B ldr r3, .L11 + 126 0056 1868 ldr r0, [r3] + 127 0058 FFF7FEFF bl HAL_CAN_ActivateNotification + 128 .LVL4: + 129 .loc 1 71 6 view .LVU44 + 130 005c 88B9 cbnz r0, .L10 + 131 .L1: + 72:Core/Src/AMS_CAN.c **** CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) { + 73:Core/Src/AMS_CAN.c **** Error_Handler(); + 74:Core/Src/AMS_CAN.c **** } + 75:Core/Src/AMS_CAN.c **** } + 132 .loc 1 75 1 view .LVU45 + 133 005e 0AB0 add sp, sp, #40 + 134 .cfi_remember_state + 135 .cfi_def_cfa_offset 8 + 136 @ sp needed + 137 0060 10BD pop {r4, pc} + 138 .LVL5: + 139 .L7: + 140 .cfi_restore_state + 34:Core/Src/AMS_CAN.c **** if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { + 141 .loc 1 34 5 is_stmt 1 view .LVU46 + 34:Core/Src/AMS_CAN.c **** if (HAL_CAN_Start(ams_can_handle) != HAL_OK) { + 142 .loc 1 34 20 is_stmt 0 view .LVU47 + 143 0062 094B ldr r3, .L11 + 144 0064 1C60 str r4, [r3] + 35:Core/Src/AMS_CAN.c **** Error_Handler(); + 145 .loc 1 35 5 is_stmt 1 view .LVU48 + 35:Core/Src/AMS_CAN.c **** Error_Handler(); + 146 .loc 1 35 9 is_stmt 0 view .LVU49 + 147 0066 2046 mov r0, r4 + 148 0068 FFF7FEFF bl HAL_CAN_Start + 149 .LVL6: + 35:Core/Src/AMS_CAN.c **** Error_Handler(); + ARM GAS /tmp/ccf8kWw2.s page 5 + + + 150 .loc 1 35 8 view .LVU50 + 151 006c 0028 cmp r0, #0 + 152 006e CFD0 beq .L2 + 36:Core/Src/AMS_CAN.c **** } + 153 .loc 1 36 7 is_stmt 1 view .LVU51 + 154 0070 FFF7FEFF bl Error_Handler + 155 .LVL7: + 156 0074 CCE7 b .L2 + 157 .L8: + 61:Core/Src/AMS_CAN.c **** } + 158 .loc 1 61 5 view .LVU52 + 159 0076 FFF7FEFF bl Error_Handler + 160 .LVL8: + 161 007a DCE7 b .L3 + 162 .L9: + 67:Core/Src/AMS_CAN.c **** } + 163 .loc 1 67 5 view .LVU53 + 164 007c FFF7FEFF bl Error_Handler + 165 .LVL9: + 166 0080 E7E7 b .L4 + 167 .L10: + 73:Core/Src/AMS_CAN.c **** } + 168 .loc 1 73 5 view .LVU54 + 169 0082 FFF7FEFF bl Error_Handler + 170 .LVL10: + 171 .loc 1 75 1 is_stmt 0 view .LVU55 + 172 0086 EAE7 b .L1 + 173 .L12: + 174 .align 2 + 175 .L11: + 176 0088 00000000 .word ams_can_handle + 177 .cfi_endproc + 178 .LFE130: + 180 .section .text.ams_can_handle_ams_msg,"ax",%progbits + 181 .align 1 + 182 .global ams_can_handle_ams_msg + 183 .syntax unified + 184 .thumb + 185 .thumb_func + 187 ams_can_handle_ams_msg: + 188 .LVL11: + 189 .LFB132: + 76:Core/Src/AMS_CAN.c **** + 77:Core/Src/AMS_CAN.c **** static int cb_triggered = 0; + 78:Core/Src/AMS_CAN.c **** + 79:Core/Src/AMS_CAN.c **** void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef* handle) { + 80:Core/Src/AMS_CAN.c **** static CAN_RxHeaderTypeDef header; + 81:Core/Src/AMS_CAN.c **** static uint8_t data[8]; + 82:Core/Src/AMS_CAN.c **** cb_triggered = 1; + 83:Core/Src/AMS_CAN.c **** + 84:Core/Src/AMS_CAN.c **** if (HAL_CAN_GetRxMessage(handle, CAN_RX_FIFO0, &header, data) != HAL_OK) { + 85:Core/Src/AMS_CAN.c **** Error_Handler(); + 86:Core/Src/AMS_CAN.c **** } + 87:Core/Src/AMS_CAN.c **** + 88:Core/Src/AMS_CAN.c **** if (handle == ams_can_handle) { + 89:Core/Src/AMS_CAN.c **** ams_can_handle_ams_msg(&header, data); + 90:Core/Src/AMS_CAN.c **** } else { + ARM GAS /tmp/ccf8kWw2.s page 6 + + + 91:Core/Src/AMS_CAN.c **** Error_Handler(); + 92:Core/Src/AMS_CAN.c **** } + 93:Core/Src/AMS_CAN.c **** } + 94:Core/Src/AMS_CAN.c **** + 95:Core/Src/AMS_CAN.c **** void ams_can_handle_ams_msg(CAN_RxHeaderTypeDef* header, uint8_t* data) { + 190 .loc 1 95 73 is_stmt 1 view -0 + 191 .cfi_startproc + 192 @ args = 0, pretend = 0, frame = 0 + 193 @ frame_needed = 0, uses_anonymous_args = 0 + 194 @ link register save eliminated. + 96:Core/Src/AMS_CAN.c **** + 97:Core/Src/AMS_CAN.c **** if(BMS_IN_TEST_MODE == 1){ + 195 .loc 1 97 3 view .LVU57 + 98:Core/Src/AMS_CAN.c **** PENDING_MESSAGE_HANDLE = 1; + 196 .loc 1 98 5 view .LVU58 + 197 .loc 1 98 28 is_stmt 0 view .LVU59 + 198 0000 054B ldr r3, .L16 + 199 0002 0122 movs r2, #1 + 200 0004 1A60 str r2, [r3] + 99:Core/Src/AMS_CAN.c **** for(int i = 0; i < 8; i++){ + 201 .loc 1 99 5 is_stmt 1 view .LVU60 + 202 .LBB2: + 203 .loc 1 99 9 view .LVU61 + 204 .LVL12: + 205 .loc 1 99 13 is_stmt 0 view .LVU62 + 206 0006 0023 movs r3, #0 + 207 .loc 1 99 5 view .LVU63 + 208 0008 03E0 b .L14 + 209 .LVL13: + 210 .L15: + 100:Core/Src/AMS_CAN.c **** canTestData[i] = data[i]; + 211 .loc 1 100 6 is_stmt 1 discriminator 3 view .LVU64 + 212 .loc 1 100 27 is_stmt 0 discriminator 3 view .LVU65 + 213 000a C85C ldrb r0, [r1, r3] @ zero_extendqisi2 + 214 .loc 1 100 21 discriminator 3 view .LVU66 + 215 000c 034A ldr r2, .L16+4 + 216 000e D054 strb r0, [r2, r3] + 99:Core/Src/AMS_CAN.c **** for(int i = 0; i < 8; i++){ + 217 .loc 1 99 28 is_stmt 1 discriminator 3 view .LVU67 + 218 0010 0133 adds r3, r3, #1 + 219 .LVL14: + 220 .L14: + 99:Core/Src/AMS_CAN.c **** for(int i = 0; i < 8; i++){ + 221 .loc 1 99 22 discriminator 1 view .LVU68 + 222 0012 072B cmp r3, #7 + 223 0014 F9DD ble .L15 + 224 .LBE2: + 101:Core/Src/AMS_CAN.c **** } + 102:Core/Src/AMS_CAN.c **** return; + 103:Core/Src/AMS_CAN.c **** } + 104:Core/Src/AMS_CAN.c **** + 105:Core/Src/AMS_CAN.c **** + 106:Core/Src/AMS_CAN.c **** if (header->IDE != CAN_ID_STD) { + 107:Core/Src/AMS_CAN.c **** return; + 108:Core/Src/AMS_CAN.c **** } + 109:Core/Src/AMS_CAN.c **** + 110:Core/Src/AMS_CAN.c **** switch (header->StdId) { + ARM GAS /tmp/ccf8kWw2.s page 7 + + + 111:Core/Src/AMS_CAN.c **** case CAN_ID_CLOCK_SYNC: + 112:Core/Src/AMS_CAN.c **** // clock_sync_handle_clock_sync_frame(data[0]); + 113:Core/Src/AMS_CAN.c **** break; + 114:Core/Src/AMS_CAN.c **** case CAN_ID_MASTER_HEARTBEAT: + 115:Core/Src/AMS_CAN.c **** // clock_sync_handle_master_heartbeat(); + 116:Core/Src/AMS_CAN.c **** break; + 117:Core/Src/AMS_CAN.c **** } + 118:Core/Src/AMS_CAN.c **** } + 225 .loc 1 118 1 is_stmt 0 view .LVU69 + 226 0016 7047 bx lr + 227 .L17: + 228 .align 2 + 229 .L16: + 230 0018 00000000 .word PENDING_MESSAGE_HANDLE + 231 001c 00000000 .word canTestData + 232 .cfi_endproc + 233 .LFE132: + 235 .section .text.HAL_CAN_RxFifo0MsgPendingCallback,"ax",%progbits + 236 .align 1 + 237 .global HAL_CAN_RxFifo0MsgPendingCallback + 238 .syntax unified + 239 .thumb + 240 .thumb_func + 242 HAL_CAN_RxFifo0MsgPendingCallback: + 243 .LVL15: + 244 .LFB131: + 79:Core/Src/AMS_CAN.c **** static CAN_RxHeaderTypeDef header; + 245 .loc 1 79 67 is_stmt 1 view -0 + 246 .cfi_startproc + 247 @ args = 0, pretend = 0, frame = 0 + 248 @ frame_needed = 0, uses_anonymous_args = 0 + 79:Core/Src/AMS_CAN.c **** static CAN_RxHeaderTypeDef header; + 249 .loc 1 79 67 is_stmt 0 view .LVU71 + 250 0000 10B5 push {r4, lr} + 251 .cfi_def_cfa_offset 8 + 252 .cfi_offset 4, -8 + 253 .cfi_offset 14, -4 + 254 0002 0446 mov r4, r0 + 80:Core/Src/AMS_CAN.c **** static uint8_t data[8]; + 255 .loc 1 80 3 is_stmt 1 view .LVU72 + 81:Core/Src/AMS_CAN.c **** cb_triggered = 1; + 256 .loc 1 81 3 view .LVU73 + 82:Core/Src/AMS_CAN.c **** + 257 .loc 1 82 3 view .LVU74 + 82:Core/Src/AMS_CAN.c **** + 258 .loc 1 82 16 is_stmt 0 view .LVU75 + 259 0004 0B4B ldr r3, .L25 + 260 0006 0122 movs r2, #1 + 261 0008 1A60 str r2, [r3] + 84:Core/Src/AMS_CAN.c **** Error_Handler(); + 262 .loc 1 84 3 is_stmt 1 view .LVU76 + 84:Core/Src/AMS_CAN.c **** Error_Handler(); + 263 .loc 1 84 7 is_stmt 0 view .LVU77 + 264 000a 0B4B ldr r3, .L25+4 + 265 000c 0B4A ldr r2, .L25+8 + 266 000e 0021 movs r1, #0 + 267 0010 FFF7FEFF bl HAL_CAN_GetRxMessage + ARM GAS /tmp/ccf8kWw2.s page 8 + + + 268 .LVL16: + 84:Core/Src/AMS_CAN.c **** Error_Handler(); + 269 .loc 1 84 6 view .LVU78 + 270 0014 30B9 cbnz r0, .L23 + 271 .L19: + 88:Core/Src/AMS_CAN.c **** ams_can_handle_ams_msg(&header, data); + 272 .loc 1 88 3 is_stmt 1 view .LVU79 + 88:Core/Src/AMS_CAN.c **** ams_can_handle_ams_msg(&header, data); + 273 .loc 1 88 14 is_stmt 0 view .LVU80 + 274 0016 0A4B ldr r3, .L25+12 + 275 0018 1B68 ldr r3, [r3] + 88:Core/Src/AMS_CAN.c **** ams_can_handle_ams_msg(&header, data); + 276 .loc 1 88 6 view .LVU81 + 277 001a A342 cmp r3, r4 + 278 001c 05D0 beq .L24 + 91:Core/Src/AMS_CAN.c **** } + 279 .loc 1 91 5 is_stmt 1 view .LVU82 + 280 001e FFF7FEFF bl Error_Handler + 281 .LVL17: + 282 .L18: + 93:Core/Src/AMS_CAN.c **** + 283 .loc 1 93 1 is_stmt 0 view .LVU83 + 284 0022 10BD pop {r4, pc} + 285 .LVL18: + 286 .L23: + 85:Core/Src/AMS_CAN.c **** } + 287 .loc 1 85 5 is_stmt 1 view .LVU84 + 288 0024 FFF7FEFF bl Error_Handler + 289 .LVL19: + 290 0028 F5E7 b .L19 + 291 .L24: + 89:Core/Src/AMS_CAN.c **** } else { + 292 .loc 1 89 5 view .LVU85 + 293 002a 0349 ldr r1, .L25+4 + 294 002c 0348 ldr r0, .L25+8 + 295 002e FFF7FEFF bl ams_can_handle_ams_msg + 296 .LVL20: + 297 0032 F6E7 b .L18 + 298 .L26: + 299 .align 2 + 300 .L25: + 301 0034 00000000 .word cb_triggered + 302 0038 00000000 .word data.2 + 303 003c 00000000 .word header.3 + 304 0040 00000000 .word ams_can_handle + 305 .cfi_endproc + 306 .LFE131: + 308 .section .text.ams_can_wait_for_free_mailboxes,"ax",%progbits + 309 .align 1 + 310 .global ams_can_wait_for_free_mailboxes + 311 .syntax unified + 312 .thumb + 313 .thumb_func + 315 ams_can_wait_for_free_mailboxes: + 316 .LVL21: + 317 .LFB134: + 119:Core/Src/AMS_CAN.c **** + ARM GAS /tmp/ccf8kWw2.s page 9 + + + 120:Core/Src/AMS_CAN.c **** void ams_can_send_heartbeat() { + 121:Core/Src/AMS_CAN.c **** static CAN_TxHeaderTypeDef header; + 122:Core/Src/AMS_CAN.c **** static uint8_t data[8]; + 123:Core/Src/AMS_CAN.c **** + 124:Core/Src/AMS_CAN.c **** header.IDE = CAN_ID_STD; + 125:Core/Src/AMS_CAN.c **** header.DLC = 8; + 126:Core/Src/AMS_CAN.c **** header.RTR = CAN_RTR_DATA; + 127:Core/Src/AMS_CAN.c **** header.TransmitGlobalTime = DISABLE; + 128:Core/Src/AMS_CAN.c **** + 129:Core/Src/AMS_CAN.c **** // Send voltages + 130:Core/Src/AMS_CAN.c **** for (int msg_id = 0; msg_id < 5; msg_id++) { + 131:Core/Src/AMS_CAN.c **** header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new fo + 132:Core/Src/AMS_CAN.c **** for (int i = 0; i < 4; i++) { + 133:Core/Src/AMS_CAN.c **** int cell = msg_id * 4 + i; + 134:Core/Src/AMS_CAN.c **** uint16_t v = (cell < N_CELLS) ? module.cellVoltages[cell] : 0; + 135:Core/Src/AMS_CAN.c **** data[2 * i + 0] = v & 0xFF; + 136:Core/Src/AMS_CAN.c **** data[2 * i + 1] = v >> 8; + 137:Core/Src/AMS_CAN.c **** } + 138:Core/Src/AMS_CAN.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, + 139:Core/Src/AMS_CAN.c **** CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 140:Core/Src/AMS_CAN.c **** uint32_t mailbox; + 141:Core/Src/AMS_CAN.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + 142:Core/Src/AMS_CAN.c **** } + 143:Core/Src/AMS_CAN.c **** } + 144:Core/Src/AMS_CAN.c **** + 145:Core/Src/AMS_CAN.c **** // Send temperatures + 146:Core/Src/AMS_CAN.c **** /*for (int temp_msg_id = 0; temp_msg_id < 8; temp_msg_id++) { + 147:Core/Src/AMS_CAN.c **** int msg_id = temp_msg_id + 3; + 148:Core/Src/AMS_CAN.c **** header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (slave_id << 4) | msg_id; + 149:Core/Src/AMS_CAN.c **** for (int i = 0; i < 4; i++) { + 150:Core/Src/AMS_CAN.c **** int sensor = temp_msg_id * 4 + i; + 151:Core/Src/AMS_CAN.c **** uint16_t temp = temperatures[sensor]; + 152:Core/Src/AMS_CAN.c **** data[2 * i + 0] = temp & 0xFF; + 153:Core/Src/AMS_CAN.c **** data[2 * i + 1] = temp >> 8; + 154:Core/Src/AMS_CAN.c **** } + 155:Core/Src/AMS_CAN.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, + 156:Core/Src/AMS_CAN.c **** CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 157:Core/Src/AMS_CAN.c **** uint32_t mailbox; + 158:Core/Src/AMS_CAN.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + 159:Core/Src/AMS_CAN.c **** } + 160:Core/Src/AMS_CAN.c **** }*/ + 161:Core/Src/AMS_CAN.c **** } + 162:Core/Src/AMS_CAN.c **** + 163:Core/Src/AMS_CAN.c **** /*void ams_can_send_error(AMS_ErrorCode error_code, + 164:Core/Src/AMS_CAN.c **** uint32_t transmission_timeout) { + 165:Core/Src/AMS_CAN.c **** static CAN_TxHeaderTypeDef header; + 166:Core/Src/AMS_CAN.c **** header.IDE = CAN_ID_STD; + 167:Core/Src/AMS_CAN.c **** header.DLC = 8; + 168:Core/Src/AMS_CAN.c **** header.RTR = CAN_RTR_DATA; + 169:Core/Src/AMS_CAN.c **** header.TransmitGlobalTime = DISABLE; + 170:Core/Src/AMS_CAN.c **** header.StdId = CAN_ID_SLAVE_ERROR; + 171:Core/Src/AMS_CAN.c **** + 172:Core/Src/AMS_CAN.c **** static uint8_t data[8]; + 173:Core/Src/AMS_CAN.c **** data[0] = slave_id; + 174:Core/Src/AMS_CAN.c **** data[1] = error_code; + 175:Core/Src/AMS_CAN.c **** + 176:Core/Src/AMS_CAN.c **** HAL_CAN_AbortTxRequest(ams_can_handle, + ARM GAS /tmp/ccf8kWw2.s page 10 + + + 177:Core/Src/AMS_CAN.c **** CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2); + 178:Core/Src/AMS_CAN.c **** uint32_t mailbox; + 179:Core/Src/AMS_CAN.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + 180:Core/Src/AMS_CAN.c **** ams_can_wait_for_free_mailboxes(ams_can_handle, 3, transmission_timeout); + 181:Core/Src/AMS_CAN.c **** }*/ + 182:Core/Src/AMS_CAN.c **** + 183:Core/Src/AMS_CAN.c **** HAL_StatusTypeDef ams_can_wait_for_free_mailboxes(CAN_HandleTypeDef* handle, + 184:Core/Src/AMS_CAN.c **** int num_mailboxes, + 185:Core/Src/AMS_CAN.c **** uint32_t timeout) { + 318 .loc 1 185 69 view -0 + 319 .cfi_startproc + 320 @ args = 0, pretend = 0, frame = 0 + 321 @ frame_needed = 0, uses_anonymous_args = 0 + 322 .loc 1 185 69 is_stmt 0 view .LVU87 + 323 0000 70B5 push {r4, r5, r6, lr} + 324 .cfi_def_cfa_offset 16 + 325 .cfi_offset 4, -16 + 326 .cfi_offset 5, -12 + 327 .cfi_offset 6, -8 + 328 .cfi_offset 14, -4 + 329 0002 0646 mov r6, r0 + 330 0004 0D46 mov r5, r1 + 331 0006 1446 mov r4, r2 + 186:Core/Src/AMS_CAN.c **** uint32_t end = HAL_GetTick() + timeout; + 332 .loc 1 186 3 is_stmt 1 view .LVU88 + 333 .loc 1 186 18 is_stmt 0 view .LVU89 + 334 0008 FFF7FEFF bl HAL_GetTick + 335 .LVL22: + 336 .loc 1 186 12 view .LVU90 + 337 000c 0444 add r4, r4, r0 + 338 .LVL23: + 187:Core/Src/AMS_CAN.c **** while (HAL_GetTick() < end) { + 339 .loc 1 187 3 is_stmt 1 view .LVU91 + 340 .L28: + 341 .loc 1 187 24 view .LVU92 + 342 .loc 1 187 10 is_stmt 0 view .LVU93 + 343 000e FFF7FEFF bl HAL_GetTick + 344 .LVL24: + 345 .loc 1 187 24 view .LVU94 + 346 0012 A042 cmp r0, r4 + 347 0014 06D2 bcs .L33 + 188:Core/Src/AMS_CAN.c **** if (HAL_CAN_GetTxMailboxesFreeLevel(handle) >= num_mailboxes) { + 348 .loc 1 188 5 is_stmt 1 view .LVU95 + 349 .loc 1 188 9 is_stmt 0 view .LVU96 + 350 0016 3046 mov r0, r6 + 351 0018 FFF7FEFF bl HAL_CAN_GetTxMailboxesFreeLevel + 352 .LVL25: + 353 .loc 1 188 8 view .LVU97 + 354 001c A842 cmp r0, r5 + 355 001e F6D3 bcc .L28 + 189:Core/Src/AMS_CAN.c **** return HAL_OK; + 356 .loc 1 189 14 view .LVU98 + 357 0020 0020 movs r0, #0 + 358 0022 00E0 b .L29 + 359 .L33: + 190:Core/Src/AMS_CAN.c **** } + 191:Core/Src/AMS_CAN.c **** } + ARM GAS /tmp/ccf8kWw2.s page 11 + + + 192:Core/Src/AMS_CAN.c **** return HAL_TIMEOUT; + 360 .loc 1 192 10 view .LVU99 + 361 0024 0320 movs r0, #3 + 362 .L29: + 193:Core/Src/AMS_CAN.c **** } + 363 .loc 1 193 1 view .LVU100 + 364 0026 70BD pop {r4, r5, r6, pc} + 365 .loc 1 193 1 view .LVU101 + 366 .cfi_endproc + 367 .LFE134: + 369 .section .text.ams_can_send_heartbeat,"ax",%progbits + 370 .align 1 + 371 .global ams_can_send_heartbeat + 372 .syntax unified + 373 .thumb + 374 .thumb_func + 376 ams_can_send_heartbeat: + 377 .LFB133: + 120:Core/Src/AMS_CAN.c **** static CAN_TxHeaderTypeDef header; + 378 .loc 1 120 31 is_stmt 1 view -0 + 379 .cfi_startproc + 380 @ args = 0, pretend = 0, frame = 8 + 381 @ frame_needed = 0, uses_anonymous_args = 0 + 382 0000 10B5 push {r4, lr} + 383 .cfi_def_cfa_offset 8 + 384 .cfi_offset 4, -8 + 385 .cfi_offset 14, -4 + 386 0002 82B0 sub sp, sp, #8 + 387 .cfi_def_cfa_offset 16 + 121:Core/Src/AMS_CAN.c **** static uint8_t data[8]; + 388 .loc 1 121 3 view .LVU103 + 122:Core/Src/AMS_CAN.c **** + 389 .loc 1 122 3 view .LVU104 + 124:Core/Src/AMS_CAN.c **** header.DLC = 8; + 390 .loc 1 124 3 view .LVU105 + 124:Core/Src/AMS_CAN.c **** header.DLC = 8; + 391 .loc 1 124 14 is_stmt 0 view .LVU106 + 392 0004 1A4B ldr r3, .L46 + 393 0006 0024 movs r4, #0 + 394 0008 9C60 str r4, [r3, #8] + 125:Core/Src/AMS_CAN.c **** header.RTR = CAN_RTR_DATA; + 395 .loc 1 125 3 is_stmt 1 view .LVU107 + 125:Core/Src/AMS_CAN.c **** header.RTR = CAN_RTR_DATA; + 396 .loc 1 125 14 is_stmt 0 view .LVU108 + 397 000a 0822 movs r2, #8 + 398 000c 1A61 str r2, [r3, #16] + 126:Core/Src/AMS_CAN.c **** header.TransmitGlobalTime = DISABLE; + 399 .loc 1 126 3 is_stmt 1 view .LVU109 + 126:Core/Src/AMS_CAN.c **** header.TransmitGlobalTime = DISABLE; + 400 .loc 1 126 14 is_stmt 0 view .LVU110 + 401 000e DC60 str r4, [r3, #12] + 127:Core/Src/AMS_CAN.c **** + 402 .loc 1 127 3 is_stmt 1 view .LVU111 + 127:Core/Src/AMS_CAN.c **** + 403 .loc 1 127 29 is_stmt 0 view .LVU112 + 404 0010 1C75 strb r4, [r3, #20] + 130:Core/Src/AMS_CAN.c **** header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new fo + ARM GAS /tmp/ccf8kWw2.s page 12 + + + 405 .loc 1 130 3 is_stmt 1 view .LVU113 + 406 .LBB3: + 130:Core/Src/AMS_CAN.c **** header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new fo + 407 .loc 1 130 8 view .LVU114 + 408 .LVL26: + 130:Core/Src/AMS_CAN.c **** header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new fo + 409 .loc 1 130 3 is_stmt 0 view .LVU115 + 410 0012 1AE0 b .L35 + 411 .LVL27: + 412 .L41: + 413 .LBB4: + 414 .LBB5: + 134:Core/Src/AMS_CAN.c **** data[2 * i + 0] = v & 0xFF; + 415 .loc 1 134 16 view .LVU116 + 416 0014 0022 movs r2, #0 + 417 .LVL28: + 418 .L37: + 135:Core/Src/AMS_CAN.c **** data[2 * i + 1] = v >> 8; + 419 .loc 1 135 7 is_stmt 1 discriminator 4 view .LVU117 + 135:Core/Src/AMS_CAN.c **** data[2 * i + 1] = v >> 8; + 420 .loc 1 135 18 is_stmt 0 discriminator 4 view .LVU118 + 421 0016 5900 lsls r1, r3, #1 + 135:Core/Src/AMS_CAN.c **** data[2 * i + 1] = v >> 8; + 422 .loc 1 135 23 discriminator 4 view .LVU119 + 423 0018 1648 ldr r0, .L46+4 + 424 001a 00F81320 strb r2, [r0, r3, lsl #1] + 136:Core/Src/AMS_CAN.c **** } + 425 .loc 1 136 7 is_stmt 1 discriminator 4 view .LVU120 + 136:Core/Src/AMS_CAN.c **** } + 426 .loc 1 136 18 is_stmt 0 discriminator 4 view .LVU121 + 427 001e 0131 adds r1, r1, #1 + 136:Core/Src/AMS_CAN.c **** } + 428 .loc 1 136 23 discriminator 4 view .LVU122 + 429 0020 120A lsrs r2, r2, #8 + 430 .LVL29: + 136:Core/Src/AMS_CAN.c **** } + 431 .loc 1 136 23 discriminator 4 view .LVU123 + 432 0022 4254 strb r2, [r0, r1] + 433 .LBE5: + 132:Core/Src/AMS_CAN.c **** int cell = msg_id * 4 + i; + 434 .loc 1 132 29 is_stmt 1 discriminator 4 view .LVU124 + 435 0024 0133 adds r3, r3, #1 + 436 .LVL30: + 437 .L36: + 132:Core/Src/AMS_CAN.c **** int cell = msg_id * 4 + i; + 438 .loc 1 132 23 discriminator 2 view .LVU125 + 439 0026 032B cmp r3, #3 + 440 0028 07DC bgt .L43 + 441 .LBB6: + 133:Core/Src/AMS_CAN.c **** uint16_t v = (cell < N_CELLS) ? module.cellVoltages[cell] : 0; + 442 .loc 1 133 7 view .LVU126 + 133:Core/Src/AMS_CAN.c **** uint16_t v = (cell < N_CELLS) ? module.cellVoltages[cell] : 0; + 443 .loc 1 133 11 is_stmt 0 view .LVU127 + 444 002a 03EB8402 add r2, r3, r4, lsl #2 + 445 .LVL31: + 134:Core/Src/AMS_CAN.c **** data[2 * i + 0] = v & 0xFF; + 446 .loc 1 134 7 is_stmt 1 view .LVU128 + ARM GAS /tmp/ccf8kWw2.s page 13 + + + 134:Core/Src/AMS_CAN.c **** data[2 * i + 0] = v & 0xFF; + 447 .loc 1 134 16 is_stmt 0 view .LVU129 + 448 002e 102A cmp r2, #16 + 449 0030 F0DC bgt .L41 + 134:Core/Src/AMS_CAN.c **** data[2 * i + 0] = v & 0xFF; + 450 .loc 1 134 16 discriminator 1 view .LVU130 + 451 0032 1149 ldr r1, .L46+8 + 452 0034 31F81220 ldrh r2, [r1, r2, lsl #1] + 453 .LVL32: + 134:Core/Src/AMS_CAN.c **** data[2 * i + 0] = v & 0xFF; + 454 .loc 1 134 16 discriminator 1 view .LVU131 + 455 0038 EDE7 b .L37 + 456 .LVL33: + 457 .L43: + 134:Core/Src/AMS_CAN.c **** data[2 * i + 0] = v & 0xFF; + 458 .loc 1 134 16 discriminator 1 view .LVU132 + 459 .LBE6: + 460 .LBE4: + 138:Core/Src/AMS_CAN.c **** CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 461 .loc 1 138 5 is_stmt 1 view .LVU133 + 138:Core/Src/AMS_CAN.c **** CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 462 .loc 1 138 9 is_stmt 0 view .LVU134 + 463 003a 0A22 movs r2, #10 + 464 003c 0121 movs r1, #1 + 465 003e 0F4B ldr r3, .L46+12 + 466 .LVL34: + 138:Core/Src/AMS_CAN.c **** CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 467 .loc 1 138 9 view .LVU135 + 468 0040 1868 ldr r0, [r3] + 469 0042 FFF7FEFF bl ams_can_wait_for_free_mailboxes + 470 .LVL35: + 138:Core/Src/AMS_CAN.c **** CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 471 .loc 1 138 8 view .LVU136 + 472 0046 40B1 cbz r0, .L44 + 473 .L39: + 130:Core/Src/AMS_CAN.c **** header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new fo + 474 .loc 1 130 42 is_stmt 1 discriminator 2 view .LVU137 + 475 0048 0134 adds r4, r4, #1 + 476 .LVL36: + 477 .L35: + 130:Core/Src/AMS_CAN.c **** header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (0 << 4) | msg_id; //TODO: Use slave_id/new fo + 478 .loc 1 130 31 discriminator 1 view .LVU138 + 479 004a 042C cmp r4, #4 + 480 004c 0DDC bgt .L45 + 131:Core/Src/AMS_CAN.c **** for (int i = 0; i < 4; i++) { + 481 .loc 1 131 5 view .LVU139 + 131:Core/Src/AMS_CAN.c **** for (int i = 0; i < 4; i++) { + 482 .loc 1 131 63 is_stmt 0 view .LVU140 + 483 004e 44F4C063 orr r3, r4, #1536 + 131:Core/Src/AMS_CAN.c **** for (int i = 0; i < 4; i++) { + 484 .loc 1 131 18 view .LVU141 + 485 0052 074A ldr r2, .L46 + 486 0054 1360 str r3, [r2] + 132:Core/Src/AMS_CAN.c **** int cell = msg_id * 4 + i; + 487 .loc 1 132 5 is_stmt 1 view .LVU142 + 488 .LBB7: + 132:Core/Src/AMS_CAN.c **** int cell = msg_id * 4 + i; + ARM GAS /tmp/ccf8kWw2.s page 14 + + + 489 .loc 1 132 10 view .LVU143 + 490 .LVL37: + 132:Core/Src/AMS_CAN.c **** int cell = msg_id * 4 + i; + 491 .loc 1 132 14 is_stmt 0 view .LVU144 + 492 0056 0023 movs r3, #0 + 132:Core/Src/AMS_CAN.c **** int cell = msg_id * 4 + i; + 493 .loc 1 132 5 view .LVU145 + 494 0058 E5E7 b .L36 + 495 .LVL38: + 496 .L44: + 132:Core/Src/AMS_CAN.c **** int cell = msg_id * 4 + i; + 497 .loc 1 132 5 view .LVU146 + 498 .LBE7: + 499 .LBB8: + 140:Core/Src/AMS_CAN.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + 500 .loc 1 140 7 is_stmt 1 view .LVU147 + 141:Core/Src/AMS_CAN.c **** } + 501 .loc 1 141 7 view .LVU148 + 502 005a 01AB add r3, sp, #4 + 503 005c 054A ldr r2, .L46+4 + 504 005e 0449 ldr r1, .L46 + 505 0060 0648 ldr r0, .L46+12 + 506 0062 0068 ldr r0, [r0] + 507 0064 FFF7FEFF bl HAL_CAN_AddTxMessage + 508 .LVL39: + 509 0068 EEE7 b .L39 + 510 .LVL40: + 511 .L45: + 141:Core/Src/AMS_CAN.c **** } + 512 .loc 1 141 7 is_stmt 0 view .LVU149 + 513 .LBE8: + 514 .LBE3: + 161:Core/Src/AMS_CAN.c **** + 515 .loc 1 161 1 view .LVU150 + 516 006a 02B0 add sp, sp, #8 + 517 .cfi_def_cfa_offset 8 + 518 @ sp needed + 519 006c 10BD pop {r4, pc} + 520 .LVL41: + 521 .L47: + 161:Core/Src/AMS_CAN.c **** + 522 .loc 1 161 1 view .LVU151 + 523 006e 00BF .align 2 + 524 .L46: + 525 0070 00000000 .word header.1 + 526 0074 00000000 .word data.0 + 527 0078 00000000 .word module + 528 007c 00000000 .word ams_can_handle + 529 .cfi_endproc + 530 .LFE133: + 532 .section .bss.data.0,"aw",%nobits + 533 .align 2 + 536 data.0: + 537 0000 00000000 .space 8 + 537 00000000 + 538 .section .bss.header.1,"aw",%nobits + 539 .align 2 + ARM GAS /tmp/ccf8kWw2.s page 15 + + + 542 header.1: + 543 0000 00000000 .space 24 + 543 00000000 + 543 00000000 + 543 00000000 + 543 00000000 + 544 .section .bss.data.2,"aw",%nobits + 545 .align 2 + 548 data.2: + 549 0000 00000000 .space 8 + 549 00000000 + 550 .section .bss.header.3,"aw",%nobits + 551 .align 2 + 554 header.3: + 555 0000 00000000 .space 28 + 555 00000000 + 555 00000000 + 555 00000000 + 555 00000000 + 556 .section .bss.cb_triggered,"aw",%nobits + 557 .align 2 + 560 cb_triggered: + 561 0000 00000000 .space 4 + 562 .global ams_can_handle + 563 .section .bss.ams_can_handle,"aw",%nobits + 564 .align 2 + 567 ams_can_handle: + 568 0000 00000000 .space 4 + 569 .global canTestData + 570 .section .bss.canTestData,"aw",%nobits + 571 .align 2 + 574 canTestData: + 575 0000 00000000 .space 8 + 575 00000000 + 576 .global PENDING_MESSAGE_HANDLE + 577 .section .bss.PENDING_MESSAGE_HANDLE,"aw",%nobits + 578 .align 2 + 581 PENDING_MESSAGE_HANDLE: + 582 0000 00000000 .space 4 + 583 .text + 584 .Letext0: + 585 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 586 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 587 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 588 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 589 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 590 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 591 .file 8 "Core/Inc/ADBMS_LL_Driver.h" + 592 .file 9 "Core/Inc/ADBMS_Abstraction.h" + 593 .file 10 "Core/Inc/AMS_CAN.h" + 594 .file 11 "Core/Inc/AMS_HighLevel.h" + 595 .file 12 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 596 .file 13 "Core/Inc/main.h" + ARM GAS /tmp/ccf8kWw2.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 AMS_CAN.c + /tmp/ccf8kWw2.s:21 .text.ams_can_init:0000000000000000 $t + /tmp/ccf8kWw2.s:27 .text.ams_can_init:0000000000000000 ams_can_init + /tmp/ccf8kWw2.s:176 .text.ams_can_init:0000000000000088 $d + /tmp/ccf8kWw2.s:567 .bss.ams_can_handle:0000000000000000 ams_can_handle + /tmp/ccf8kWw2.s:181 .text.ams_can_handle_ams_msg:0000000000000000 $t + /tmp/ccf8kWw2.s:187 .text.ams_can_handle_ams_msg:0000000000000000 ams_can_handle_ams_msg + /tmp/ccf8kWw2.s:230 .text.ams_can_handle_ams_msg:0000000000000018 $d + /tmp/ccf8kWw2.s:581 .bss.PENDING_MESSAGE_HANDLE:0000000000000000 PENDING_MESSAGE_HANDLE + /tmp/ccf8kWw2.s:574 .bss.canTestData:0000000000000000 canTestData + /tmp/ccf8kWw2.s:236 .text.HAL_CAN_RxFifo0MsgPendingCallback:0000000000000000 $t + /tmp/ccf8kWw2.s:242 .text.HAL_CAN_RxFifo0MsgPendingCallback:0000000000000000 HAL_CAN_RxFifo0MsgPendingCallback + /tmp/ccf8kWw2.s:301 .text.HAL_CAN_RxFifo0MsgPendingCallback:0000000000000034 $d + /tmp/ccf8kWw2.s:560 .bss.cb_triggered:0000000000000000 cb_triggered + /tmp/ccf8kWw2.s:548 .bss.data.2:0000000000000000 data.2 + /tmp/ccf8kWw2.s:554 .bss.header.3:0000000000000000 header.3 + /tmp/ccf8kWw2.s:309 .text.ams_can_wait_for_free_mailboxes:0000000000000000 $t + /tmp/ccf8kWw2.s:315 .text.ams_can_wait_for_free_mailboxes:0000000000000000 ams_can_wait_for_free_mailboxes + /tmp/ccf8kWw2.s:370 .text.ams_can_send_heartbeat:0000000000000000 $t + /tmp/ccf8kWw2.s:376 .text.ams_can_send_heartbeat:0000000000000000 ams_can_send_heartbeat + /tmp/ccf8kWw2.s:525 .text.ams_can_send_heartbeat:0000000000000070 $d + /tmp/ccf8kWw2.s:542 .bss.header.1:0000000000000000 header.1 + /tmp/ccf8kWw2.s:536 .bss.data.0:0000000000000000 data.0 + /tmp/ccf8kWw2.s:533 .bss.data.0:0000000000000000 $d + /tmp/ccf8kWw2.s:539 .bss.header.1:0000000000000000 $d + /tmp/ccf8kWw2.s:545 .bss.data.2:0000000000000000 $d + /tmp/ccf8kWw2.s:551 .bss.header.3:0000000000000000 $d + /tmp/ccf8kWw2.s:557 .bss.cb_triggered:0000000000000000 $d + /tmp/ccf8kWw2.s:564 .bss.ams_can_handle:0000000000000000 $d + /tmp/ccf8kWw2.s:571 .bss.canTestData:0000000000000000 $d + /tmp/ccf8kWw2.s:578 .bss.PENDING_MESSAGE_HANDLE:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_CAN_Start +HAL_CAN_ConfigFilter +HAL_CAN_ActivateNotification +Error_Handler +HAL_CAN_GetRxMessage +HAL_GetTick +HAL_CAN_GetTxMailboxesFreeLevel +HAL_CAN_AddTxMessage +module diff --git a/BMS_Testbench/BMS_Software_V1/build/AMS_CAN.o b/BMS_Testbench/BMS_Software_V1/build/AMS_CAN.o new file mode 100644 index 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zzHAtyC-8IhtoqED*KR5u!AH#2?$AhUB#Uo5lk@m4iV5(S6?!wol2Ge`TF|`9FPOfn z1aT)lOkY)s^+-l#9WG4Q|5K0FRk7b=;5h}$LKRwH*c!zSMG0{f3vUedwYW%!F7me% zSH8W+K?iU-#j)25M!vo8!=4X3vPXM@V{Zoae0$GwL@ z`w;5+_L@L6gXa_{&$oh+Z?6f4Xm28W*iv)$zKnXlyZk za5?e)H|i9xGrmv29??#5?41FlSdZd!ilg@`7{z+;WRL#*qF4`)rCf3B(O-QR>p3z~ zcIv^uP>adZ$sdmd2I66tJs$LKMz$%A zH1wP{WMds3K=(M41hgYNTBP?qeCld*gn4?0!OQpCgm=Cf$Y~zXGtKdPdy&1jusC)= z?i9!Lhl=bSgFRqPvptHP$~_o_%Djm{_UQUyk=`RXLtRJ>xHx*xv!26$ z1$wmhokD)8JPW=2@o2yqYz%ygZ#6C_KKf5WSd(*Lsd5v7&)<8=FBQVP=^?%Zy>=L( k{g}=sWY33-d^&3!Rq+y>(U?2MsUocfdI`jr@4(UfU-$%fu>b%7 literal 0 HcmV?d00001 diff --git a/BMS_Testbench/BMS_Software_V1/build/AMS_HighLevel.d b/BMS_Testbench/BMS_Software_V1/build/AMS_HighLevel.d new file mode 100644 index 0000000..690af56 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/AMS_HighLevel.d @@ -0,0 +1,64 @@ +build/AMS_HighLevel.o: Core/Src/AMS_HighLevel.c Core/Inc/AMS_HighLevel.h \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Core/Inc/ADBMS_CMD_MAKROS.h +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Core/Inc/ADBMS_CMD_MAKROS.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/AMS_HighLevel.lst b/BMS_Testbench/BMS_Software_V1/build/AMS_HighLevel.lst new file mode 100644 index 0000000..827dfa4 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/AMS_HighLevel.lst @@ -0,0 +1,1530 @@ +ARM GAS /tmp/ccaolay4.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "AMS_HighLevel.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/AMS_HighLevel.c" + 20 .section .text.AMS_Init,"ax",%progbits + 21 .align 1 + 22 .global AMS_Init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 AMS_Init: + 28 .LVL0: + 29 .LFB130: + 1:Core/Src/AMS_HighLevel.c **** /* + 2:Core/Src/AMS_HighLevel.c **** * AMS_HighLevel.c + 3:Core/Src/AMS_HighLevel.c **** * + 4:Core/Src/AMS_HighLevel.c **** * Created on: 20.07.2022 + 5:Core/Src/AMS_HighLevel.c **** * Author: max + 6:Core/Src/AMS_HighLevel.c **** */ + 7:Core/Src/AMS_HighLevel.c **** + 8:Core/Src/AMS_HighLevel.c **** + 9:Core/Src/AMS_HighLevel.c **** #include "AMS_HighLevel.h" + 10:Core/Src/AMS_HighLevel.c **** + 11:Core/Src/AMS_HighLevel.c **** Cell_Module module; + 12:Core/Src/AMS_HighLevel.c **** uint32_t balancedCells = 0; + 13:Core/Src/AMS_HighLevel.c **** uint8_t BalancingActive = 0; + 14:Core/Src/AMS_HighLevel.c **** uint8_t stateofcharge = 100; + 15:Core/Src/AMS_HighLevel.c **** int64_t currentintegrator = 0; + 16:Core/Src/AMS_HighLevel.c **** uint32_t lastticks = 0; + 17:Core/Src/AMS_HighLevel.c **** uint32_t currenttick = 0; + 18:Core/Src/AMS_HighLevel.c **** uint8_t eepromconfigured = 0; + 19:Core/Src/AMS_HighLevel.c **** + 20:Core/Src/AMS_HighLevel.c **** uint8_t internalbalancingalgo = 1; + 21:Core/Src/AMS_HighLevel.c **** uint16_t startbalancingthreshold = 41000; + 22:Core/Src/AMS_HighLevel.c **** uint16_t stopbalancingthreshold = 30000; + 23:Core/Src/AMS_HighLevel.c **** uint16_t balancingvoltagedelta = 10; + 24:Core/Src/AMS_HighLevel.c **** + 25:Core/Src/AMS_HighLevel.c **** + 26:Core/Src/AMS_HighLevel.c **** uint16_t amsuv = 0; + 27:Core/Src/AMS_HighLevel.c **** uint16_t amsov = 0; + 28:Core/Src/AMS_HighLevel.c **** + 29:Core/Src/AMS_HighLevel.c **** uint8_t amserrorcode = 0; + ARM GAS /tmp/ccaolay4.s page 2 + + + 30:Core/Src/AMS_HighLevel.c **** uint8_t amswarningcode = 0; + 31:Core/Src/AMS_HighLevel.c **** + 32:Core/Src/AMS_HighLevel.c **** uint8_t numberofCells = 17; + 33:Core/Src/AMS_HighLevel.c **** uint8_t numberofAux = 0; + 34:Core/Src/AMS_HighLevel.c **** + 35:Core/Src/AMS_HighLevel.c **** + 36:Core/Src/AMS_HighLevel.c **** amsState currentAMSState = AMSDEACTIVE; + 37:Core/Src/AMS_HighLevel.c **** amsState lastAMSState = AMSDEACTIVE; + 38:Core/Src/AMS_HighLevel.c **** + 39:Core/Src/AMS_HighLevel.c **** void AMS_Init(SPI_HandleTypeDef *hspi) + 40:Core/Src/AMS_HighLevel.c **** { + 30 .loc 1 40 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 .loc 1 40 1 is_stmt 0 view .LVU1 + 35 0000 08B5 push {r3, lr} + 36 .cfi_def_cfa_offset 8 + 37 .cfi_offset 3, -8 + 38 .cfi_offset 14, -4 + 41:Core/Src/AMS_HighLevel.c **** if(eepromconfigured == 1) + 39 .loc 1 41 2 is_stmt 1 view .LVU2 + 40 .loc 1 41 22 is_stmt 0 view .LVU3 + 41 0002 0F4B ldr r3, .L6 + 42 0004 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 43 .loc 1 41 4 view .LVU4 + 44 0006 012B cmp r3, #1 + 45 0008 11D0 beq .L5 + 42:Core/Src/AMS_HighLevel.c **** { + 43:Core/Src/AMS_HighLevel.c **** /*amsov = eepromcellovervoltage>>4; + 44:Core/Src/AMS_HighLevel.c **** amsuv = (eepromcellundervoltage-1)>>4; + 45:Core/Src/AMS_HighLevel.c **** numberofCells = eepromnumofcells; + 46:Core/Src/AMS_HighLevel.c **** numberofAux = eepromnumofaux; + 47:Core/Src/AMS_HighLevel.c **** initAMS(hspi, eepromnumofcells, eepromnumofaux);*/ + 48:Core/Src/AMS_HighLevel.c **** amsConfigOverVoltage(amsov); + 49:Core/Src/AMS_HighLevel.c **** amsConfigUnderVoltage(amsuv); + 50:Core/Src/AMS_HighLevel.c **** } + 51:Core/Src/AMS_HighLevel.c **** else + 52:Core/Src/AMS_HighLevel.c **** { + 53:Core/Src/AMS_HighLevel.c **** initAMS(hspi, numberofCells, numberofAux); + 46 .loc 1 53 3 is_stmt 1 view .LVU5 + 47 000a 0E4B ldr r3, .L6+4 + 48 000c 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 49 000e 0E4B ldr r3, .L6+8 + 50 0010 1978 ldrb r1, [r3] @ zero_extendqisi2 + 51 0012 FFF7FEFF bl initAMS + 52 .LVL1: + 54:Core/Src/AMS_HighLevel.c **** amsov = DEFAULT_OV; + 53 .loc 1 54 3 view .LVU6 + 54 .loc 1 54 9 is_stmt 0 view .LVU7 + 55 0016 0D4B ldr r3, .L6+12 + 56 0018 40F64122 movw r2, #2625 + 57 001c 1A80 strh r2, [r3] @ movhi + 55:Core/Src/AMS_HighLevel.c **** amsuv = DEFAULT_UV; + 58 .loc 1 55 3 is_stmt 1 view .LVU8 + 59 .loc 1 55 9 is_stmt 0 view .LVU9 + 60 001e 0C4B ldr r3, .L6+16 + ARM GAS /tmp/ccaolay4.s page 3 + + + 61 0020 40F21A62 movw r2, #1562 + 62 0024 1A80 strh r2, [r3] @ movhi + 63 .L3: + 56:Core/Src/AMS_HighLevel.c **** } + 57:Core/Src/AMS_HighLevel.c **** + 58:Core/Src/AMS_HighLevel.c **** + 59:Core/Src/AMS_HighLevel.c **** currentAMSState = AMSIDLE; + 64 .loc 1 59 2 is_stmt 1 view .LVU10 + 65 .loc 1 59 18 is_stmt 0 view .LVU11 + 66 0026 0B4B ldr r3, .L6+20 + 67 0028 0122 movs r2, #1 + 68 002a 1A70 strb r2, [r3] + 60:Core/Src/AMS_HighLevel.c **** + 61:Core/Src/AMS_HighLevel.c **** + 62:Core/Src/AMS_HighLevel.c **** } + 69 .loc 1 62 1 view .LVU12 + 70 002c 08BD pop {r3, pc} + 71 .LVL2: + 72 .L5: + 48:Core/Src/AMS_HighLevel.c **** amsConfigUnderVoltage(amsuv); + 73 .loc 1 48 3 is_stmt 1 view .LVU13 + 74 002e 074B ldr r3, .L6+12 + 75 0030 1888 ldrh r0, [r3] + 76 .LVL3: + 48:Core/Src/AMS_HighLevel.c **** amsConfigUnderVoltage(amsuv); + 77 .loc 1 48 3 is_stmt 0 view .LVU14 + 78 0032 FFF7FEFF bl amsConfigOverVoltage + 79 .LVL4: + 49:Core/Src/AMS_HighLevel.c **** } + 80 .loc 1 49 3 is_stmt 1 view .LVU15 + 81 0036 064B ldr r3, .L6+16 + 82 0038 1888 ldrh r0, [r3] + 83 003a FFF7FEFF bl amsConfigUnderVoltage + 84 .LVL5: + 85 003e F2E7 b .L3 + 86 .L7: + 87 .align 2 + 88 .L6: + 89 0040 00000000 .word eepromconfigured + 90 0044 00000000 .word numberofAux + 91 0048 00000000 .word numberofCells + 92 004c 00000000 .word amsov + 93 0050 00000000 .word amsuv + 94 0054 00000000 .word currentAMSState + 95 .cfi_endproc + 96 .LFE130: + 98 .section .text.AMS_Warning_Loop,"ax",%progbits + 99 .align 1 + 100 .global AMS_Warning_Loop + 101 .syntax unified + 102 .thumb + 103 .thumb_func + 105 AMS_Warning_Loop: + 106 .LFB133: + 63:Core/Src/AMS_HighLevel.c **** + 64:Core/Src/AMS_HighLevel.c **** void AMS_Loop() + 65:Core/Src/AMS_HighLevel.c **** { + ARM GAS /tmp/ccaolay4.s page 4 + + + 66:Core/Src/AMS_HighLevel.c **** + 67:Core/Src/AMS_HighLevel.c **** //On Transition Functions called ones if the State Changed + 68:Core/Src/AMS_HighLevel.c **** + 69:Core/Src/AMS_HighLevel.c **** if(currentAMSState != lastAMSState) + 70:Core/Src/AMS_HighLevel.c **** { + 71:Core/Src/AMS_HighLevel.c **** switch(currentAMSState) + 72:Core/Src/AMS_HighLevel.c **** { + 73:Core/Src/AMS_HighLevel.c **** case AMSIDLE: + 74:Core/Src/AMS_HighLevel.c **** break; + 75:Core/Src/AMS_HighLevel.c **** case AMSDEACTIVE: + 76:Core/Src/AMS_HighLevel.c **** break; + 77:Core/Src/AMS_HighLevel.c **** case AMSCHARGING: + 78:Core/Src/AMS_HighLevel.c **** break; + 79:Core/Src/AMS_HighLevel.c **** case AMSIDLEBALANCING: + 80:Core/Src/AMS_HighLevel.c **** break; + 81:Core/Src/AMS_HighLevel.c **** case AMSDISCHARGING: + 82:Core/Src/AMS_HighLevel.c **** break; + 83:Core/Src/AMS_HighLevel.c **** case AMSWARNING: + 84:Core/Src/AMS_HighLevel.c **** writeWarningLog(0x01); + 85:Core/Src/AMS_HighLevel.c **** break; + 86:Core/Src/AMS_HighLevel.c **** case AMSERROR: + 87:Core/Src/AMS_HighLevel.c **** writeErrorLog(amserrorcode); + 88:Core/Src/AMS_HighLevel.c **** break; + 89:Core/Src/AMS_HighLevel.c **** } + 90:Core/Src/AMS_HighLevel.c **** lastAMSState = currentAMSState; + 91:Core/Src/AMS_HighLevel.c **** } + 92:Core/Src/AMS_HighLevel.c **** + 93:Core/Src/AMS_HighLevel.c **** //Main Loops for different AMS States + 94:Core/Src/AMS_HighLevel.c **** + 95:Core/Src/AMS_HighLevel.c **** switch(currentAMSState) + 96:Core/Src/AMS_HighLevel.c **** { + 97:Core/Src/AMS_HighLevel.c **** case AMSIDLE: + 98:Core/Src/AMS_HighLevel.c **** AMS_Idle_Loop(); + 99:Core/Src/AMS_HighLevel.c **** break; + 100:Core/Src/AMS_HighLevel.c **** case AMSDEACTIVE: + 101:Core/Src/AMS_HighLevel.c **** break; + 102:Core/Src/AMS_HighLevel.c **** case AMSCHARGING: + 103:Core/Src/AMS_HighLevel.c **** break; + 104:Core/Src/AMS_HighLevel.c **** case AMSIDLEBALANCING: + 105:Core/Src/AMS_HighLevel.c **** AMS_Idle_Loop(); + 106:Core/Src/AMS_HighLevel.c **** break; + 107:Core/Src/AMS_HighLevel.c **** case AMSDISCHARGING: + 108:Core/Src/AMS_HighLevel.c **** break; + 109:Core/Src/AMS_HighLevel.c **** case AMSWARNING: + 110:Core/Src/AMS_HighLevel.c **** AMS_Warning_Loop(); + 111:Core/Src/AMS_HighLevel.c **** break; + 112:Core/Src/AMS_HighLevel.c **** case AMSERROR: + 113:Core/Src/AMS_HighLevel.c **** break; + 114:Core/Src/AMS_HighLevel.c **** } + 115:Core/Src/AMS_HighLevel.c **** } + 116:Core/Src/AMS_HighLevel.c **** + 117:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Idle_Loop() + 118:Core/Src/AMS_HighLevel.c **** { + 119:Core/Src/AMS_HighLevel.c **** amsWakeUp(); + 120:Core/Src/AMS_HighLevel.c **** amsConfigOverVoltage(amsov); + 121:Core/Src/AMS_HighLevel.c **** amsConfigUnderVoltage(amsuv); + 122:Core/Src/AMS_HighLevel.c **** amsConfigAuxMeasurement(0xFFFF); + ARM GAS /tmp/ccaolay4.s page 5 + + + 123:Core/Src/AMS_HighLevel.c **** amsClearAux(); + 124:Core/Src/AMS_HighLevel.c **** amsCellMeasurement(&module); + 125:Core/Src/AMS_HighLevel.c **** amsInternalStatusMeasurement(&module); + 126:Core/Src/AMS_HighLevel.c **** amsAuxMeasurement(&module); + 127:Core/Src/AMS_HighLevel.c **** amsCheckUnderOverVoltage(&module); + 128:Core/Src/AMS_HighLevel.c **** integrateCurrent(); + 129:Core/Src/AMS_HighLevel.c **** + 130:Core/Src/AMS_HighLevel.c **** static uint32_t channelstobalance = 1; + 131:Core/Src/AMS_HighLevel.c **** + 132:Core/Src/AMS_HighLevel.c **** channelstobalance = 0x1FFFF; + 133:Core/Src/AMS_HighLevel.c **** /* if(channelstobalance & 0x20000){ + 134:Core/Src/AMS_HighLevel.c **** channelstobalance = 1; + 135:Core/Src/AMS_HighLevel.c **** }*/ + 136:Core/Src/AMS_HighLevel.c **** + 137:Core/Src/AMS_HighLevel.c **** amsConfigBalancing(channelstobalance); + 138:Core/Src/AMS_HighLevel.c **** amsStartBalancing(100); + 139:Core/Src/AMS_HighLevel.c **** + 140:Core/Src/AMS_HighLevel.c **** if((module.overVoltage | module.underVoltage)) + 141:Core/Src/AMS_HighLevel.c **** { + 142:Core/Src/AMS_HighLevel.c **** //amsSendWarning(); + 143:Core/Src/AMS_HighLevel.c **** // currentAMSState = AMSWARNING; + 144:Core/Src/AMS_HighLevel.c **** } + 145:Core/Src/AMS_HighLevel.c **** + 146:Core/Src/AMS_HighLevel.c **** // AMS_Balancing_Loop(); + 147:Core/Src/AMS_HighLevel.c **** + 148:Core/Src/AMS_HighLevel.c **** /* if(BalancingActive) + 149:Core/Src/AMS_HighLevel.c **** { + 150:Core/Src/AMS_HighLevel.c **** amsStartBalancing(100); + 151:Core/Src/AMS_HighLevel.c **** } + 152:Core/Src/AMS_HighLevel.c **** else + 153:Core/Src/AMS_HighLevel.c **** { + 154:Core/Src/AMS_HighLevel.c **** amsStopBalancing(); + 155:Core/Src/AMS_HighLevel.c **** }*/ + 156:Core/Src/AMS_HighLevel.c **** //amsConfigBalancing(balancedCells); + 157:Core/Src/AMS_HighLevel.c **** //volatile amscheck = amscheckOpenCellWire(&module); + 158:Core/Src/AMS_HighLevel.c **** return 0; + 159:Core/Src/AMS_HighLevel.c **** } + 160:Core/Src/AMS_HighLevel.c **** + 161:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Warning_Loop() + 162:Core/Src/AMS_HighLevel.c **** { + 107 .loc 1 162 1 view -0 + 108 .cfi_startproc + 109 @ args = 0, pretend = 0, frame = 0 + 110 @ frame_needed = 0, uses_anonymous_args = 0 + 111 0000 10B5 push {r4, lr} + 112 .cfi_def_cfa_offset 8 + 113 .cfi_offset 4, -8 + 114 .cfi_offset 14, -4 + 163:Core/Src/AMS_HighLevel.c **** + 164:Core/Src/AMS_HighLevel.c **** amsWakeUp(); + 115 .loc 1 164 4 view .LVU17 + 116 0002 FFF7FEFF bl amsWakeUp + 117 .LVL6: + 165:Core/Src/AMS_HighLevel.c **** amsConfigOverVoltage(amsov); + 118 .loc 1 165 4 view .LVU18 + 119 0006 144B ldr r3, .L12 + 120 0008 1888 ldrh r0, [r3] + ARM GAS /tmp/ccaolay4.s page 6 + + + 121 000a FFF7FEFF bl amsConfigOverVoltage + 122 .LVL7: + 166:Core/Src/AMS_HighLevel.c **** amsConfigUnderVoltage(amsuv); + 123 .loc 1 166 4 view .LVU19 + 124 000e 134B ldr r3, .L12+4 + 125 0010 1888 ldrh r0, [r3] + 126 0012 FFF7FEFF bl amsConfigUnderVoltage + 127 .LVL8: + 167:Core/Src/AMS_HighLevel.c **** amsConfigAuxMeasurement(0xFFFF); + 128 .loc 1 167 4 view .LVU20 + 129 0016 4FF6FF70 movw r0, #65535 + 130 001a FFF7FEFF bl amsConfigAuxMeasurement + 131 .LVL9: + 168:Core/Src/AMS_HighLevel.c **** amsClearAux(); + 132 .loc 1 168 4 view .LVU21 + 133 001e FFF7FEFF bl amsClearAux + 134 .LVL10: + 169:Core/Src/AMS_HighLevel.c **** amsCellMeasurement(&module); + 135 .loc 1 169 4 view .LVU22 + 136 0022 0F4C ldr r4, .L12+8 + 137 0024 2046 mov r0, r4 + 138 0026 FFF7FEFF bl amsCellMeasurement + 139 .LVL11: + 170:Core/Src/AMS_HighLevel.c **** amsInternalStatusMeasurement(&module); + 140 .loc 1 170 4 view .LVU23 + 141 002a 2046 mov r0, r4 + 142 002c FFF7FEFF bl amsInternalStatusMeasurement + 143 .LVL12: + 171:Core/Src/AMS_HighLevel.c **** amsAuxMeasurement(&module); + 144 .loc 1 171 4 view .LVU24 + 145 0030 2046 mov r0, r4 + 146 0032 FFF7FEFF bl amsAuxMeasurement + 147 .LVL13: + 172:Core/Src/AMS_HighLevel.c **** amsCheckUnderOverVoltage(&module); + 148 .loc 1 172 4 view .LVU25 + 149 0036 2046 mov r0, r4 + 150 0038 FFF7FEFF bl amsCheckUnderOverVoltage + 151 .LVL14: + 173:Core/Src/AMS_HighLevel.c **** + 174:Core/Src/AMS_HighLevel.c **** if(!(module.overVoltage | module.underVoltage)) + 152 .loc 1 174 4 view .LVU26 + 153 .loc 1 174 15 is_stmt 0 view .LVU27 + 154 003c A36D ldr r3, [r4, #88] + 155 .loc 1 174 36 view .LVU28 + 156 003e E26D ldr r2, [r4, #92] + 157 .loc 1 174 6 view .LVU29 + 158 0040 1343 orrs r3, r3, r2 + 159 0042 03D0 beq .L11 + 160 .L9: + 175:Core/Src/AMS_HighLevel.c **** { + 176:Core/Src/AMS_HighLevel.c **** currentAMSState = AMSIDLE; + 177:Core/Src/AMS_HighLevel.c **** amsClearWarning(); + 178:Core/Src/AMS_HighLevel.c **** } + 179:Core/Src/AMS_HighLevel.c **** amsStopBalancing(); + 161 .loc 1 179 4 is_stmt 1 view .LVU30 + 162 0044 FFF7FEFF bl amsStopBalancing + 163 .LVL15: + ARM GAS /tmp/ccaolay4.s page 7 + + + 180:Core/Src/AMS_HighLevel.c **** + 181:Core/Src/AMS_HighLevel.c **** return 0; + 164 .loc 1 181 2 view .LVU31 + 182:Core/Src/AMS_HighLevel.c **** } + 165 .loc 1 182 1 is_stmt 0 view .LVU32 + 166 0048 0020 movs r0, #0 + 167 004a 10BD pop {r4, pc} + 168 .L11: + 176:Core/Src/AMS_HighLevel.c **** amsClearWarning(); + 169 .loc 1 176 5 is_stmt 1 view .LVU33 + 176:Core/Src/AMS_HighLevel.c **** amsClearWarning(); + 170 .loc 1 176 21 is_stmt 0 view .LVU34 + 171 004c 054B ldr r3, .L12+12 + 172 004e 0122 movs r2, #1 + 173 0050 1A70 strb r2, [r3] + 177:Core/Src/AMS_HighLevel.c **** } + 174 .loc 1 177 5 is_stmt 1 view .LVU35 + 175 0052 FFF7FEFF bl amsClearWarning + 176 .LVL16: + 177 0056 F5E7 b .L9 + 178 .L13: + 179 .align 2 + 180 .L12: + 181 0058 00000000 .word amsov + 182 005c 00000000 .word amsuv + 183 0060 00000000 .word module + 184 0064 00000000 .word currentAMSState + 185 .cfi_endproc + 186 .LFE133: + 188 .section .text.AMS_Error_Loop,"ax",%progbits + 189 .align 1 + 190 .global AMS_Error_Loop + 191 .syntax unified + 192 .thumb + 193 .thumb_func + 195 AMS_Error_Loop: + 196 .LFB134: + 183:Core/Src/AMS_HighLevel.c **** + 184:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Error_Loop() + 185:Core/Src/AMS_HighLevel.c **** { + 197 .loc 1 185 1 view -0 + 198 .cfi_startproc + 199 @ args = 0, pretend = 0, frame = 0 + 200 @ frame_needed = 0, uses_anonymous_args = 0 + 201 @ link register save eliminated. + 186:Core/Src/AMS_HighLevel.c **** return 0; + 202 .loc 1 186 2 view .LVU37 + 187:Core/Src/AMS_HighLevel.c **** } + 203 .loc 1 187 1 is_stmt 0 view .LVU38 + 204 0000 0020 movs r0, #0 + 205 0002 7047 bx lr + 206 .cfi_endproc + 207 .LFE134: + 209 .section .text.AMS_Charging_Loop,"ax",%progbits + 210 .align 1 + 211 .global AMS_Charging_Loop + 212 .syntax unified + ARM GAS /tmp/ccaolay4.s page 8 + + + 213 .thumb + 214 .thumb_func + 216 AMS_Charging_Loop: + 217 .LFB135: + 188:Core/Src/AMS_HighLevel.c **** + 189:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Charging_Loop() + 190:Core/Src/AMS_HighLevel.c **** { + 218 .loc 1 190 1 is_stmt 1 view -0 + 219 .cfi_startproc + 220 @ args = 0, pretend = 0, frame = 0 + 221 @ frame_needed = 0, uses_anonymous_args = 0 + 222 @ link register save eliminated. + 191:Core/Src/AMS_HighLevel.c **** return 0; + 223 .loc 1 191 2 view .LVU40 + 192:Core/Src/AMS_HighLevel.c **** } + 224 .loc 1 192 1 is_stmt 0 view .LVU41 + 225 0000 0020 movs r0, #0 + 226 0002 7047 bx lr + 227 .cfi_endproc + 228 .LFE135: + 230 .section .text.AMS_Discharging_Loop,"ax",%progbits + 231 .align 1 + 232 .global AMS_Discharging_Loop + 233 .syntax unified + 234 .thumb + 235 .thumb_func + 237 AMS_Discharging_Loop: + 238 .LFB136: + 193:Core/Src/AMS_HighLevel.c **** + 194:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Discharging_Loop() + 195:Core/Src/AMS_HighLevel.c **** { + 239 .loc 1 195 1 is_stmt 1 view -0 + 240 .cfi_startproc + 241 @ args = 0, pretend = 0, frame = 0 + 242 @ frame_needed = 0, uses_anonymous_args = 0 + 243 @ link register save eliminated. + 196:Core/Src/AMS_HighLevel.c **** return 0; + 244 .loc 1 196 2 view .LVU43 + 197:Core/Src/AMS_HighLevel.c **** } + 245 .loc 1 197 1 is_stmt 0 view .LVU44 + 246 0000 0020 movs r0, #0 + 247 0002 7047 bx lr + 248 .cfi_endproc + 249 .LFE136: + 251 .section .text.AMS_Balancing_Loop,"ax",%progbits + 252 .align 1 + 253 .global AMS_Balancing_Loop + 254 .syntax unified + 255 .thumb + 256 .thumb_func + 258 AMS_Balancing_Loop: + 259 .LFB137: + 198:Core/Src/AMS_HighLevel.c **** + 199:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Balancing_Loop() + 200:Core/Src/AMS_HighLevel.c **** { + 260 .loc 1 200 1 is_stmt 1 view -0 + 261 .cfi_startproc + ARM GAS /tmp/ccaolay4.s page 9 + + + 262 @ args = 0, pretend = 0, frame = 0 + 263 @ frame_needed = 0, uses_anonymous_args = 0 + 264 0000 70B5 push {r4, r5, r6, lr} + 265 .cfi_def_cfa_offset 16 + 266 .cfi_offset 4, -16 + 267 .cfi_offset 5, -12 + 268 .cfi_offset 6, -8 + 269 .cfi_offset 14, -4 + 201:Core/Src/AMS_HighLevel.c **** uint8_t balancingdone = 1; + 270 .loc 1 201 2 view .LVU46 + 271 .LVL17: + 202:Core/Src/AMS_HighLevel.c **** if((eepromconfigured == 1) && (internalbalancingalgo == 1) && (module.internalDieTemp<28000/*Therm + 272 .loc 1 202 2 view .LVU47 + 273 .loc 1 202 23 is_stmt 0 view .LVU48 + 274 0002 3E4B ldr r3, .L42 + 275 0004 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 276 .loc 1 202 4 view .LVU49 + 277 0006 012B cmp r3, #1 + 278 0008 03D1 bne .L18 + 279 .loc 1 202 55 discriminator 1 view .LVU50 + 280 000a 3D4B ldr r3, .L42+4 + 281 000c 1C78 ldrb r4, [r3] @ zero_extendqisi2 + 282 .loc 1 202 29 discriminator 1 view .LVU51 + 283 000e 012C cmp r4, #1 + 284 0010 04D0 beq .L37 + 285 .L18: + 203:Core/Src/AMS_HighLevel.c **** { + 204:Core/Src/AMS_HighLevel.c **** uint16_t highestcellvoltage = module.cellVoltages[0]; + 205:Core/Src/AMS_HighLevel.c **** uint16_t lowestcellvoltage = module.cellVoltages[0]; + 206:Core/Src/AMS_HighLevel.c **** uint8_t highestcell = 0; + 207:Core/Src/AMS_HighLevel.c **** uint8_t lowestcell = 0; + 208:Core/Src/AMS_HighLevel.c **** + 209:Core/Src/AMS_HighLevel.c **** for(uint8_t n = 0; n < numberofCells; n++) + 210:Core/Src/AMS_HighLevel.c **** { + 211:Core/Src/AMS_HighLevel.c **** if(module.cellVoltages[n] > highestcellvoltage) + 212:Core/Src/AMS_HighLevel.c **** { + 213:Core/Src/AMS_HighLevel.c **** highestcellvoltage = module.cellVoltages[n]; + 214:Core/Src/AMS_HighLevel.c **** highestcell = n; + 215:Core/Src/AMS_HighLevel.c **** } + 216:Core/Src/AMS_HighLevel.c **** if(module.cellVoltages[n] < lowestcellvoltage) + 217:Core/Src/AMS_HighLevel.c **** { + 218:Core/Src/AMS_HighLevel.c **** lowestcellvoltage = module.cellVoltages[n]; + 219:Core/Src/AMS_HighLevel.c **** lowestcell = n; + 220:Core/Src/AMS_HighLevel.c **** } + 221:Core/Src/AMS_HighLevel.c **** } + 222:Core/Src/AMS_HighLevel.c **** + 223:Core/Src/AMS_HighLevel.c **** if(currentAMSState == AMSCHARGING) //Balancing is only Active if the BMS is in Charging Mode + 224:Core/Src/AMS_HighLevel.c **** { + 225:Core/Src/AMS_HighLevel.c **** + 226:Core/Src/AMS_HighLevel.c **** uint32_t channelstobalance = 0; + 227:Core/Src/AMS_HighLevel.c **** + 228:Core/Src/AMS_HighLevel.c **** if(highestcellvoltage > startbalancingthreshold) + 229:Core/Src/AMS_HighLevel.c **** { + 230:Core/Src/AMS_HighLevel.c **** for(uint8_t n = 0; n < numberofCells; n++) + 231:Core/Src/AMS_HighLevel.c **** { + 232:Core/Src/AMS_HighLevel.c **** if(module.cellVoltages[n] > stopbalancingthreshold) + 233:Core/Src/AMS_HighLevel.c **** { + ARM GAS /tmp/ccaolay4.s page 10 + + + 234:Core/Src/AMS_HighLevel.c **** uint16_t dv = module.cellVoltages[n]-lowestcellvoltage; + 235:Core/Src/AMS_HighLevel.c **** if(dv > (balancingvoltagedelta*1000)) + 236:Core/Src/AMS_HighLevel.c **** { + 237:Core/Src/AMS_HighLevel.c **** balancingdone = 0; + 238:Core/Src/AMS_HighLevel.c **** channelstobalance |= 1< balancingvoltagedelta) + 264:Core/Src/AMS_HighLevel.c **** { + 265:Core/Src/AMS_HighLevel.c **** balancingdone = 0; + 266:Core/Src/AMS_HighLevel.c **** channelstobalance |= 1< (balancingvoltagedelta*1000)) + 449 .loc 1 234 7 is_stmt 1 view .LVU110 + 234:Core/Src/AMS_HighLevel.c **** if(dv > (balancingvoltagedelta*1000)) + 450 .loc 1 234 16 is_stmt 0 view .LVU111 + 451 009a ACEB010C sub ip, ip, r1 + 452 009e 1FFA8CFC uxth ip, ip + 453 .LVL38: + 235:Core/Src/AMS_HighLevel.c **** { + 454 .loc 1 235 7 is_stmt 1 view .LVU112 + 235:Core/Src/AMS_HighLevel.c **** { + 455 .loc 1 235 37 is_stmt 0 view .LVU113 + 456 00a2 1D4D ldr r5, .L42+28 + 457 00a4 2D88 ldrh r5, [r5] + 458 00a6 4FF47A7E mov lr, #1000 + 459 00aa 0EFB05F5 mul r5, lr, r5 + 235:Core/Src/AMS_HighLevel.c **** { + 460 .loc 1 235 9 view .LVU114 + 461 00ae AC45 cmp ip, r5 + 462 00b0 E7DD ble .L26 + 237:Core/Src/AMS_HighLevel.c **** channelstobalance |= 1< balancingvoltagedelta) + 512 .loc 1 262 7 view .LVU131 + 262:Core/Src/AMS_HighLevel.c **** if(dv > balancingvoltagedelta) + 513 .loc 1 262 40 is_stmt 0 view .LVU132 + 514 00d0 0C4D ldr r5, .L42+8 + 515 00d2 35F813C0 ldrh ip, [r5, r3, lsl #1] + 262:Core/Src/AMS_HighLevel.c **** if(dv > balancingvoltagedelta) + 516 .loc 1 262 16 view .LVU133 + 517 00d6 ACEB010C sub ip, ip, r1 + 518 00da 1FFA8CFC uxth ip, ip + 519 .LVL48: + 263:Core/Src/AMS_HighLevel.c **** { + 520 .loc 1 263 7 is_stmt 1 view .LVU134 + 263:Core/Src/AMS_HighLevel.c **** { + 521 .loc 1 263 13 is_stmt 0 view .LVU135 + 522 00de 0E4D ldr r5, .L42+28 + 523 00e0 2D88 ldrh r5, [r5] + 263:Core/Src/AMS_HighLevel.c **** { + 524 .loc 1 263 9 view .LVU136 + 525 00e2 6545 cmp r5, ip + 526 00e4 F0D2 bcs .L30 + 265:Core/Src/AMS_HighLevel.c **** channelstobalance |= 1<0>ed1+wbE({ z*onA>Eo!q0 z9beG3c+OZ|e4?ZTFp^RE3KkwX}Cq@15!| zJhfBFHFbQeu8Z%vEnU@f#u~r2VAO?oOg*}>tLl~=?+^Ch+4k-W>k*ByLoGL6HrBrM z_v?0-%-z|R^J4SvmJdtA*S4t_i+0@D_Q&Uocl_b?2<(}wLnnNzfBoE=uEjTep{?Ns zwY*|SBaBAVdO9U z%S|6I>1nuO@4JVuF8s)P@B7)yrH#i&tE*XUA!G4ZM5NdL3csV>apbq>8t+Wvaws+3ZKvI{K8E+U%aI1NR|4? z_orZI?%1xe=PS1TQK{U6yAG=GhDW{T?EZE7wd6GYTX@F)rRU(TP*;VH!L9-O+3n-x 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zM_c!2n25g8@gT+~(ij&Ti14$Gh&Xo<@!aW(;>8O7x)_x zTDJ@Q>iAK9jC}Y{i+qlVIBpgCb|Rd8Q|Nn$i0c8NA0#4(XM{dMM4Yb){W~J!RgvjK z6Y1y>FrBh-%*o*^fV7J6_j(l>!Y2rk6h0#)Gop8dJc7t(WgQ93Yr6K?^UUns_B{WT zJ$JT?%epz2{{+L{4`oqXk(zVq4YzN(XlB zgA>hk&RKXAqMJA3aO{&8t>oEIJG}W_wZp+7jg!SmjcxDrM+LU*45to`@bo{d+S1b> zV`%TE94u+B`&>aY=8qiQa;Hb|nOP2zv*Xa?VD;IaFp36HEkm*hOmw9bai9n+UiwYX!-##y?Zyn2)| zt-^(A=s(qKf)2~L{c?_Sl3y~M-|*_C=XaWEPL;Y44{+KE=f>szaN5jd{NQSyWXSs@fq~)_2|*K^9esh z8Qb4N-d&G}P>(6_SPxA5nR+~iygR;X1a!Lie&NyMzW#K2Z+Z0UpvV4jl2hj2z;MS` zj{#E;9^=EZlZlV#Q118=uy?wCFPD8nJ)V=f{f1$Ww3D3ttaM$D5l<{cpr6=BYOdQ?&tDDJeL( + 17:Core/Src/Testbench.c **** #include "ADBMS_Abstraction.h" + 18:Core/Src/Testbench.c **** #include "main.h" + 19:Core/Src/Testbench.c **** + 20:Core/Src/Testbench.c **** + 21:Core/Src/Testbench.c **** void canTestSendTemperatures(uint16_t* data){ + 30 .loc 1 21 45 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 40 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 .loc 1 21 45 is_stmt 0 view .LVU1 + 35 0000 00B5 push {lr} + 36 .cfi_def_cfa_offset 4 + 37 .cfi_offset 14, -4 + ARM GAS /tmp/ccSPu85t.s page 2 + + + 38 0002 8BB0 sub sp, sp, #44 + 39 .cfi_def_cfa_offset 48 + 22:Core/Src/Testbench.c **** static CAN_TxHeaderTypeDef header; + 40 .loc 1 22 2 is_stmt 1 view .LVU2 + 23:Core/Src/Testbench.c **** + 24:Core/Src/Testbench.c **** header.IDE = CAN_ID_STD; + 41 .loc 1 24 2 view .LVU3 + 42 .loc 1 24 13 is_stmt 0 view .LVU4 + 43 0004 3B4A ldr r2, .L17 + 44 0006 0023 movs r3, #0 + 45 0008 9360 str r3, [r2, #8] + 25:Core/Src/Testbench.c **** header.DLC = 8; + 46 .loc 1 25 2 is_stmt 1 view .LVU5 + 47 .loc 1 25 13 is_stmt 0 view .LVU6 + 48 000a 0821 movs r1, #8 + 49 000c 1161 str r1, [r2, #16] + 26:Core/Src/Testbench.c **** header.RTR = CAN_RTR_DATA; + 50 .loc 1 26 2 is_stmt 1 view .LVU7 + 51 .loc 1 26 13 is_stmt 0 view .LVU8 + 52 000e D360 str r3, [r2, #12] + 27:Core/Src/Testbench.c **** header.TransmitGlobalTime = DISABLE; + 53 .loc 1 27 2 is_stmt 1 view .LVU9 + 54 .loc 1 27 28 is_stmt 0 view .LVU10 + 55 0010 1375 strb r3, [r2, #20] + 28:Core/Src/Testbench.c **** uint8_t buffer[24]; + 56 .loc 1 28 2 is_stmt 1 view .LVU11 + 29:Core/Src/Testbench.c **** uint8_t tmp[8]; + 57 .loc 1 29 2 view .LVU12 + 30:Core/Src/Testbench.c **** + 31:Core/Src/Testbench.c **** for(int i = 0; i < 12; i++){ + 58 .loc 1 31 2 view .LVU13 + 59 .LBB2: + 60 .loc 1 31 6 view .LVU14 + 61 .LVL1: + 62 .loc 1 31 2 is_stmt 0 view .LVU15 + 63 0012 0EE0 b .L2 + 64 .LVL2: + 65 .L3: + 32:Core/Src/Testbench.c **** buffer[((i*2)+1)] = data[i] >> 8; + 66 .loc 1 32 3 is_stmt 1 discriminator 3 view .LVU16 + 67 .loc 1 32 27 is_stmt 0 discriminator 3 view .LVU17 + 68 0014 30F813C0 ldrh ip, [r0, r3, lsl #1] + 69 .loc 1 32 13 discriminator 3 view .LVU18 + 70 0018 5A00 lsls r2, r3, #1 + 71 .loc 1 32 21 discriminator 3 view .LVU19 + 72 001a 02F12901 add r1, r2, #41 + 73 001e 6944 add r1, sp, r1 + 74 0020 4FEA1C2E lsr lr, ip, #8 + 75 0024 01F818EC strb lr, [r1, #-24] + 33:Core/Src/Testbench.c **** buffer[(i*2)] = data[i]; + 76 .loc 1 33 3 is_stmt 1 discriminator 3 view .LVU20 + 77 .loc 1 33 17 is_stmt 0 discriminator 3 view .LVU21 + 78 0028 2832 adds r2, r2, #40 + 79 002a 6A44 add r2, sp, r2 + 80 002c 02F818CC strb ip, [r2, #-24] + 31:Core/Src/Testbench.c **** buffer[((i*2)+1)] = data[i] >> 8; + 81 .loc 1 31 26 is_stmt 1 discriminator 3 view .LVU22 + ARM GAS /tmp/ccSPu85t.s page 3 + + + 82 0030 0133 adds r3, r3, #1 + 83 .LVL3: + 84 .L2: + 31:Core/Src/Testbench.c **** buffer[((i*2)+1)] = data[i] >> 8; + 85 .loc 1 31 19 discriminator 1 view .LVU23 + 86 0032 0B2B cmp r3, #11 + 87 0034 EEDD ble .L3 + 88 .LBE2: + 89 .LBB3: + 34:Core/Src/Testbench.c **** } + 35:Core/Src/Testbench.c **** + 36:Core/Src/Testbench.c **** for(int i = 0; i < 8; i++){ + 90 .loc 1 36 10 is_stmt 0 view .LVU24 + 91 0036 0023 movs r3, #0 + 92 .LVL4: + 93 .loc 1 36 10 view .LVU25 + 94 0038 07E0 b .L4 + 95 .LVL5: + 96 .L5: + 37:Core/Src/Testbench.c **** tmp[i] = buffer[i]; + 97 .loc 1 37 3 is_stmt 1 discriminator 3 view .LVU26 + 98 .loc 1 37 18 is_stmt 0 discriminator 3 view .LVU27 + 99 003a 03F12802 add r2, r3, #40 + 100 003e 6A44 add r2, sp, r2 + 101 0040 12F8181C ldrb r1, [r2, #-24] @ zero_extendqisi2 + 102 .loc 1 37 10 discriminator 3 view .LVU28 + 103 0044 02F8201C strb r1, [r2, #-32] + 36:Core/Src/Testbench.c **** tmp[i] = buffer[i]; + 104 .loc 1 36 25 is_stmt 1 discriminator 3 view .LVU29 + 105 0048 0133 adds r3, r3, #1 + 106 .LVL6: + 107 .L4: + 36:Core/Src/Testbench.c **** tmp[i] = buffer[i]; + 108 .loc 1 36 19 discriminator 1 view .LVU30 + 109 004a 072B cmp r3, #7 + 110 004c F5DD ble .L5 + 111 .LBE3: + 38:Core/Src/Testbench.c **** } + 39:Core/Src/Testbench.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 112 .loc 1 39 2 view .LVU31 + 113 .loc 1 39 6 is_stmt 0 view .LVU32 + 114 004e 0A22 movs r2, #10 + 115 0050 0121 movs r1, #1 + 116 0052 294B ldr r3, .L17+4 + 117 .LVL7: + 118 .loc 1 39 6 view .LVU33 + 119 0054 1868 ldr r0, [r3] + 120 .LVL8: + 121 .loc 1 39 6 view .LVU34 + 122 0056 FFF7FEFF bl ams_can_wait_for_free_mailboxes + 123 .LVL9: + 124 .loc 1 39 5 view .LVU35 + 125 005a 10B1 cbz r0, .L14 + 126 .L6: + 127 .LBB4: + 36:Core/Src/Testbench.c **** tmp[i] = buffer[i]; + 128 .loc 1 36 10 discriminator 1 view .LVU36 + ARM GAS /tmp/ccSPu85t.s page 4 + + + 129 005c 0823 movs r3, #8 + 130 005e 0022 movs r2, #0 + 131 0060 13E0 b .L7 + 132 .L14: + 133 .LBE4: + 134 .LBB5: + 40:Core/Src/Testbench.c **** uint32_t mailbox; + 135 .loc 1 40 3 is_stmt 1 view .LVU37 + 41:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + 136 .loc 1 41 3 view .LVU38 + 137 0062 01AB add r3, sp, #4 + 138 0064 02AA add r2, sp, #8 + 139 0066 2349 ldr r1, .L17 + 140 0068 2348 ldr r0, .L17+4 + 141 006a 0068 ldr r0, [r0] + 142 006c FFF7FEFF bl HAL_CAN_AddTxMessage + 143 .LVL10: + 144 0070 F4E7 b .L6 + 145 .LVL11: + 146 .L8: + 147 .loc 1 41 3 is_stmt 0 view .LVU39 + 148 .LBE5: + 149 .LBB6: + 42:Core/Src/Testbench.c **** } + 43:Core/Src/Testbench.c **** + 44:Core/Src/Testbench.c **** int m = 0; + 45:Core/Src/Testbench.c **** for(int i = 8; i < 16; i++){ + 46:Core/Src/Testbench.c **** tmp[m] = buffer[i]; + 150 .loc 1 46 3 is_stmt 1 discriminator 3 view .LVU40 + 151 .loc 1 46 18 is_stmt 0 discriminator 3 view .LVU41 + 152 0072 03F12801 add r1, r3, #40 + 153 0076 6944 add r1, sp, r1 + 154 0078 11F8180C ldrb r0, [r1, #-24] @ zero_extendqisi2 + 155 .loc 1 46 10 discriminator 3 view .LVU42 + 156 007c 02F12801 add r1, r2, #40 + 157 0080 6944 add r1, sp, r1 + 158 0082 01F8200C strb r0, [r1, #-32] + 47:Core/Src/Testbench.c **** m++; + 159 .loc 1 47 3 is_stmt 1 discriminator 3 view .LVU43 + 160 .loc 1 47 4 is_stmt 0 discriminator 3 view .LVU44 + 161 0086 0132 adds r2, r2, #1 + 162 .LVL12: + 45:Core/Src/Testbench.c **** tmp[m] = buffer[i]; + 163 .loc 1 45 26 is_stmt 1 discriminator 3 view .LVU45 + 164 0088 0133 adds r3, r3, #1 + 165 .LVL13: + 166 .L7: + 45:Core/Src/Testbench.c **** tmp[m] = buffer[i]; + 167 .loc 1 45 19 discriminator 1 view .LVU46 + 168 008a 0F2B cmp r3, #15 + 169 008c F1DD ble .L8 + 170 .LBE6: + 48:Core/Src/Testbench.c **** } + 49:Core/Src/Testbench.c **** + 50:Core/Src/Testbench.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 171 .loc 1 50 2 view .LVU47 + 172 .loc 1 50 6 is_stmt 0 view .LVU48 + ARM GAS /tmp/ccSPu85t.s page 5 + + + 173 008e 0A22 movs r2, #10 + 174 .LVL14: + 175 .loc 1 50 6 view .LVU49 + 176 0090 0121 movs r1, #1 + 177 0092 194B ldr r3, .L17+4 + 178 .LVL15: + 179 .loc 1 50 6 view .LVU50 + 180 0094 1868 ldr r0, [r3] + 181 0096 FFF7FEFF bl ams_can_wait_for_free_mailboxes + 182 .LVL16: + 183 .loc 1 50 5 view .LVU51 + 184 009a 10B1 cbz r0, .L15 + 185 .L9: + 186 .LBB7: + 36:Core/Src/Testbench.c **** tmp[i] = buffer[i]; + 187 .loc 1 36 10 discriminator 1 view .LVU52 + 188 009c 1023 movs r3, #16 + 189 009e 0022 movs r2, #0 + 190 00a0 13E0 b .L10 + 191 .L15: + 192 .LBE7: + 193 .LBB8: + 51:Core/Src/Testbench.c **** uint32_t mailbox; + 194 .loc 1 51 3 is_stmt 1 view .LVU53 + 52:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + 195 .loc 1 52 3 view .LVU54 + 196 00a2 01AB add r3, sp, #4 + 197 00a4 02AA add r2, sp, #8 + 198 00a6 1349 ldr r1, .L17 + 199 00a8 1348 ldr r0, .L17+4 + 200 00aa 0068 ldr r0, [r0] + 201 00ac FFF7FEFF bl HAL_CAN_AddTxMessage + 202 .LVL17: + 203 00b0 F4E7 b .L9 + 204 .LVL18: + 205 .L11: + 206 .loc 1 52 3 is_stmt 0 view .LVU55 + 207 .LBE8: + 208 .LBB9: + 53:Core/Src/Testbench.c **** } + 54:Core/Src/Testbench.c **** m = 0; + 55:Core/Src/Testbench.c **** for(int i = 16; i < 24; i++){ + 56:Core/Src/Testbench.c **** tmp[m] = buffer[i]; + 209 .loc 1 56 3 is_stmt 1 discriminator 3 view .LVU56 + 210 .loc 1 56 18 is_stmt 0 discriminator 3 view .LVU57 + 211 00b2 03F12801 add r1, r3, #40 + 212 00b6 6944 add r1, sp, r1 + 213 00b8 11F8180C ldrb r0, [r1, #-24] @ zero_extendqisi2 + 214 .loc 1 56 10 discriminator 3 view .LVU58 + 215 00bc 02F12801 add r1, r2, #40 + 216 00c0 6944 add r1, sp, r1 + 217 00c2 01F8200C strb r0, [r1, #-32] + 57:Core/Src/Testbench.c **** m++; + 218 .loc 1 57 3 is_stmt 1 discriminator 3 view .LVU59 + 219 .loc 1 57 4 is_stmt 0 discriminator 3 view .LVU60 + 220 00c6 0132 adds r2, r2, #1 + 221 .LVL19: + ARM GAS /tmp/ccSPu85t.s page 6 + + + 55:Core/Src/Testbench.c **** tmp[m] = buffer[i]; + 222 .loc 1 55 27 is_stmt 1 discriminator 3 view .LVU61 + 223 00c8 0133 adds r3, r3, #1 + 224 .LVL20: + 225 .L10: + 55:Core/Src/Testbench.c **** tmp[m] = buffer[i]; + 226 .loc 1 55 20 discriminator 1 view .LVU62 + 227 00ca 172B cmp r3, #23 + 228 00cc F1DD ble .L11 + 229 .LBE9: + 58:Core/Src/Testbench.c **** } + 59:Core/Src/Testbench.c **** + 60:Core/Src/Testbench.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 230 .loc 1 60 2 view .LVU63 + 231 .loc 1 60 6 is_stmt 0 view .LVU64 + 232 00ce 0A22 movs r2, #10 + 233 .LVL21: + 234 .loc 1 60 6 view .LVU65 + 235 00d0 0121 movs r1, #1 + 236 00d2 094B ldr r3, .L17+4 + 237 .LVL22: + 238 .loc 1 60 6 view .LVU66 + 239 00d4 1868 ldr r0, [r3] + 240 00d6 FFF7FEFF bl ams_can_wait_for_free_mailboxes + 241 .LVL23: + 242 .loc 1 60 5 view .LVU67 + 243 00da 10B1 cbz r0, .L16 + 244 .L1: + 61:Core/Src/Testbench.c **** uint32_t mailbox; + 62:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, tmp, &mailbox); + 63:Core/Src/Testbench.c **** } + 64:Core/Src/Testbench.c **** } + 245 .loc 1 64 1 view .LVU68 + 246 00dc 0BB0 add sp, sp, #44 + 247 .cfi_remember_state + 248 .cfi_def_cfa_offset 4 + 249 @ sp needed + 250 00de 5DF804FB ldr pc, [sp], #4 + 251 .L16: + 252 .cfi_restore_state + 253 .LBB10: + 61:Core/Src/Testbench.c **** uint32_t mailbox; + 254 .loc 1 61 3 is_stmt 1 view .LVU69 + 62:Core/Src/Testbench.c **** } + 255 .loc 1 62 3 view .LVU70 + 256 00e2 01AB add r3, sp, #4 + 257 00e4 02AA add r2, sp, #8 + 258 00e6 0349 ldr r1, .L17 + 259 00e8 0348 ldr r0, .L17+4 + 260 00ea 0068 ldr r0, [r0] + 261 00ec FFF7FEFF bl HAL_CAN_AddTxMessage + 262 .LVL24: + 263 .LBE10: + 264 .loc 1 64 1 is_stmt 0 view .LVU71 + 265 00f0 F4E7 b .L1 + 266 .L18: + 267 00f2 00BF .align 2 + ARM GAS /tmp/ccSPu85t.s page 7 + + + 268 .L17: + 269 00f4 00000000 .word header.1 + 270 00f8 00000000 .word ams_can_handle + 271 .cfi_endproc + 272 .LFE130: + 274 .section .text.canTestSendAnswer,"ax",%progbits + 275 .align 1 + 276 .global canTestSendAnswer + 277 .syntax unified + 278 .thumb + 279 .thumb_func + 281 canTestSendAnswer: + 282 .LVL25: + 283 .LFB131: + 65:Core/Src/Testbench.c **** + 66:Core/Src/Testbench.c **** void canTestSendAnswer(uint8_t* data){ + 284 .loc 1 66 38 is_stmt 1 view -0 + 285 .cfi_startproc + 286 @ args = 0, pretend = 0, frame = 8 + 287 @ frame_needed = 0, uses_anonymous_args = 0 + 288 .loc 1 66 38 is_stmt 0 view .LVU73 + 289 0000 10B5 push {r4, lr} + 290 .cfi_def_cfa_offset 8 + 291 .cfi_offset 4, -8 + 292 .cfi_offset 14, -4 + 293 0002 82B0 sub sp, sp, #8 + 294 .cfi_def_cfa_offset 16 + 295 0004 0446 mov r4, r0 + 67:Core/Src/Testbench.c **** static CAN_TxHeaderTypeDef header; + 296 .loc 1 67 2 is_stmt 1 view .LVU74 + 68:Core/Src/Testbench.c **** + 69:Core/Src/Testbench.c **** header.IDE = CAN_ID_STD; + 297 .loc 1 69 2 view .LVU75 + 298 .loc 1 69 13 is_stmt 0 view .LVU76 + 299 0006 0C4B ldr r3, .L23 + 300 0008 0021 movs r1, #0 + 301 000a 9960 str r1, [r3, #8] + 70:Core/Src/Testbench.c **** header.DLC = 8; + 302 .loc 1 70 2 is_stmt 1 view .LVU77 + 303 .loc 1 70 13 is_stmt 0 view .LVU78 + 304 000c 0822 movs r2, #8 + 305 000e 1A61 str r2, [r3, #16] + 71:Core/Src/Testbench.c **** header.RTR = CAN_RTR_DATA; + 306 .loc 1 71 2 is_stmt 1 view .LVU79 + 307 .loc 1 71 13 is_stmt 0 view .LVU80 + 308 0010 D960 str r1, [r3, #12] + 72:Core/Src/Testbench.c **** header.TransmitGlobalTime = DISABLE; + 309 .loc 1 72 2 is_stmt 1 view .LVU81 + 310 .loc 1 72 28 is_stmt 0 view .LVU82 + 311 0012 1975 strb r1, [r3, #20] + 73:Core/Src/Testbench.c **** + 74:Core/Src/Testbench.c **** if (ams_can_wait_for_free_mailboxes(ams_can_handle, 1, + 312 .loc 1 74 4 is_stmt 1 view .LVU83 + 313 .loc 1 74 8 is_stmt 0 view .LVU84 + 314 0014 0A22 movs r2, #10 + 315 0016 0121 movs r1, #1 + 316 0018 084B ldr r3, .L23+4 + ARM GAS /tmp/ccSPu85t.s page 8 + + + 317 001a 1868 ldr r0, [r3] + 318 .LVL26: + 319 .loc 1 74 8 view .LVU85 + 320 001c FFF7FEFF bl ams_can_wait_for_free_mailboxes + 321 .LVL27: + 322 .loc 1 74 7 view .LVU86 + 323 0020 08B1 cbz r0, .L22 + 324 .L19: + 75:Core/Src/Testbench.c **** CAN_HEARTBEAT_TX_TIMEOUT) == HAL_OK) { + 76:Core/Src/Testbench.c **** uint32_t mailbox; + 77:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + 78:Core/Src/Testbench.c **** } + 79:Core/Src/Testbench.c **** } + 325 .loc 1 79 1 view .LVU87 + 326 0022 02B0 add sp, sp, #8 + 327 .cfi_remember_state + 328 .cfi_def_cfa_offset 8 + 329 @ sp needed + 330 0024 10BD pop {r4, pc} + 331 .LVL28: + 332 .L22: + 333 .cfi_restore_state + 334 .LBB11: + 76:Core/Src/Testbench.c **** HAL_CAN_AddTxMessage(ams_can_handle, &header, data, &mailbox); + 335 .loc 1 76 3 is_stmt 1 view .LVU88 + 77:Core/Src/Testbench.c **** } + 336 .loc 1 77 3 view .LVU89 + 337 0026 01AB add r3, sp, #4 + 338 0028 2246 mov r2, r4 + 339 002a 0349 ldr r1, .L23 + 340 002c 0348 ldr r0, .L23+4 + 341 002e 0068 ldr r0, [r0] + 342 0030 FFF7FEFF bl HAL_CAN_AddTxMessage + 343 .LVL29: + 344 .LBE11: + 345 .loc 1 79 1 is_stmt 0 view .LVU90 + 346 0034 F5E7 b .L19 + 347 .L24: + 348 0036 00BF .align 2 + 349 .L23: + 350 0038 00000000 .word header.0 + 351 003c 00000000 .word ams_can_handle + 352 .cfi_endproc + 353 .LFE131: + 355 .section .text.resetData,"ax",%progbits + 356 .align 1 + 357 .global resetData + 358 .syntax unified + 359 .thumb + 360 .thumb_func + 362 resetData: + 363 .LVL30: + 364 .LFB132: + 80:Core/Src/Testbench.c **** + 81:Core/Src/Testbench.c **** void resetData(uint8_t* data){ + 365 .loc 1 81 30 is_stmt 1 view -0 + 366 .cfi_startproc + ARM GAS /tmp/ccSPu85t.s page 9 + + + 367 @ args = 0, pretend = 0, frame = 0 + 368 @ frame_needed = 0, uses_anonymous_args = 0 + 369 @ link register save eliminated. + 82:Core/Src/Testbench.c **** for(int i = 0; i < 8; i++){ + 370 .loc 1 82 2 view .LVU92 + 371 .LBB12: + 372 .loc 1 82 6 view .LVU93 + 373 .loc 1 82 10 is_stmt 0 view .LVU94 + 374 0000 0023 movs r3, #0 + 375 .loc 1 82 2 view .LVU95 + 376 0002 02E0 b .L26 + 377 .LVL31: + 378 .L27: + 83:Core/Src/Testbench.c **** data[0] = 0; + 379 .loc 1 83 3 is_stmt 1 discriminator 3 view .LVU96 + 380 .loc 1 83 11 is_stmt 0 discriminator 3 view .LVU97 + 381 0004 0022 movs r2, #0 + 382 0006 0270 strb r2, [r0] + 82:Core/Src/Testbench.c **** for(int i = 0; i < 8; i++){ + 383 .loc 1 82 25 is_stmt 1 discriminator 3 view .LVU98 + 384 0008 0133 adds r3, r3, #1 + 385 .LVL32: + 386 .L26: + 82:Core/Src/Testbench.c **** for(int i = 0; i < 8; i++){ + 387 .loc 1 82 19 discriminator 1 view .LVU99 + 388 000a 072B cmp r3, #7 + 389 000c FADD ble .L27 + 390 .LBE12: + 84:Core/Src/Testbench.c **** } + 85:Core/Src/Testbench.c **** + 86:Core/Src/Testbench.c **** } + 391 .loc 1 86 1 is_stmt 0 view .LVU100 + 392 000e 7047 bx lr + 393 .cfi_endproc + 394 .LFE132: + 396 .section .text.readTemperatures,"ax",%progbits + 397 .align 1 + 398 .global readTemperatures + 399 .syntax unified + 400 .thumb + 401 .thumb_func + 403 readTemperatures: + 404 .LFB133: + 87:Core/Src/Testbench.c **** void readTemperatures(){ + 405 .loc 1 87 24 is_stmt 1 view -0 + 406 .cfi_startproc + 407 @ args = 0, pretend = 0, frame = 24 + 408 @ frame_needed = 0, uses_anonymous_args = 0 + 409 0000 10B5 push {r4, lr} + 410 .cfi_def_cfa_offset 8 + 411 .cfi_offset 4, -8 + 412 .cfi_offset 14, -4 + 413 0002 86B0 sub sp, sp, #24 + 414 .cfi_def_cfa_offset 32 + 88:Core/Src/Testbench.c **** uint8_t last_error = 0; + 415 .loc 1 88 2 view .LVU102 + 416 .LVL33: + ARM GAS /tmp/ccSPu85t.s page 10 + + + 89:Core/Src/Testbench.c **** int N_SENSORS = 12; + 417 .loc 1 89 2 view .LVU103 + 90:Core/Src/Testbench.c **** uint16_t temperatures[N_SENSORS]; + 418 .loc 1 90 2 view .LVU104 + 91:Core/Src/Testbench.c **** for (int i = 0; i < N_SENSORS; i++) { + 419 .loc 1 91 2 view .LVU105 + 420 .LBB13: + 421 .loc 1 91 7 view .LVU106 + 422 .loc 1 91 11 is_stmt 0 view .LVU107 + 423 0004 0024 movs r4, #0 + 424 .loc 1 91 2 view .LVU108 + 425 0006 00E0 b .L29 + 426 .LVL34: + 427 .L30: + 428 .loc 1 91 34 is_stmt 1 discriminator 2 view .LVU109 + 429 0008 0134 adds r4, r4, #1 + 430 .LVL35: + 431 .L29: + 432 .loc 1 91 20 discriminator 1 view .LVU110 + 433 000a 0B2C cmp r4, #11 + 434 000c 0CDC bgt .L33 + 92:Core/Src/Testbench.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 435 .loc 1 92 10 view .LVU111 + 436 .LBB14: + 437 .loc 1 92 14 is_stmt 0 view .LVU112 + 438 000e 0DEB4401 add r1, sp, r4, lsl #1 + 439 0012 2046 mov r0, r4 + 440 0014 FFF7FEFF bl sensor_read + 441 .LVL36: + 442 .loc 1 92 13 view .LVU113 + 443 0018 0028 cmp r0, #0 + 444 001a F5D0 beq .L30 + 445 .LBB15: + 93:Core/Src/Testbench.c **** sensor_init(i); + 446 .loc 1 93 12 is_stmt 1 view .LVU114 + 447 001c 2046 mov r0, r4 + 448 001e FFF7FEFF bl sensor_init + 449 .LVL37: + 94:Core/Src/Testbench.c **** last_error = HAL_GetTick(); + 450 .loc 1 94 12 view .LVU115 + 451 .loc 1 94 25 is_stmt 0 view .LVU116 + 452 0022 FFF7FEFF bl HAL_GetTick + 453 .LVL38: + 454 0026 EFE7 b .L30 + 455 .L33: + 456 .LBE15: + 457 .LBE14: + 458 .LBE13: + 95:Core/Src/Testbench.c **** } + 96:Core/Src/Testbench.c **** } + 97:Core/Src/Testbench.c **** canTestSendTemperatures(temperatures); + 459 .loc 1 97 2 is_stmt 1 view .LVU117 + 460 0028 6846 mov r0, sp + 461 002a FFF7FEFF bl canTestSendTemperatures + 462 .LVL39: + 98:Core/Src/Testbench.c **** } + 463 .loc 1 98 1 is_stmt 0 view .LVU118 + ARM GAS /tmp/ccSPu85t.s page 11 + + + 464 002e 06B0 add sp, sp, #24 + 465 .cfi_def_cfa_offset 8 + 466 .LVL40: + 467 .loc 1 98 1 view .LVU119 + 468 @ sp needed + 469 0030 10BD pop {r4, pc} + 470 .loc 1 98 1 view .LVU120 + 471 .cfi_endproc + 472 .LFE133: + 474 .section .text.testLoop,"ax",%progbits + 475 .align 1 + 476 .global testLoop + 477 .syntax unified + 478 .thumb + 479 .thumb_func + 481 testLoop: + 482 .LVL41: + 483 .LFB134: + 99:Core/Src/Testbench.c **** + 100:Core/Src/Testbench.c **** void testLoop(uint8_t* data){ + 484 .loc 1 100 29 is_stmt 1 view -0 + 485 .cfi_startproc + 486 @ args = 0, pretend = 0, frame = 0 + 487 @ frame_needed = 0, uses_anonymous_args = 0 + 488 .loc 1 100 29 is_stmt 0 view .LVU122 + 489 0000 38B5 push {r3, r4, r5, lr} + 490 .cfi_def_cfa_offset 16 + 491 .cfi_offset 3, -16 + 492 .cfi_offset 4, -12 + 493 .cfi_offset 5, -8 + 494 .cfi_offset 14, -4 + 495 0002 0546 mov r5, r0 + 101:Core/Src/Testbench.c **** uint8_t action = data[0]; + 496 .loc 1 101 2 is_stmt 1 view .LVU123 + 497 .loc 1 101 10 is_stmt 0 view .LVU124 + 498 0004 0378 ldrb r3, [r0] @ zero_extendqisi2 + 499 .LVL42: + 102:Core/Src/Testbench.c **** switch(action){ + 500 .loc 1 102 2 is_stmt 1 view .LVU125 + 501 0006 013B subs r3, r3, #1 + 502 0008 042B cmp r3, #4 + 503 000a 0AD8 bhi .L35 + 504 000c DFE803F0 tbb [pc, r3] + 505 .L37: + 506 0010 03 .byte (.L41-.L37)/2 + 507 0011 0D .byte (.L40-.L37)/2 + 508 0012 16 .byte (.L39-.L37)/2 + 509 0013 1D .byte (.L38-.L37)/2 + 510 0014 48 .byte (.L36-.L37)/2 + 511 0015 00 .p2align 1 + 512 .L41: + 103:Core/Src/Testbench.c **** case CAN_TEST: + 104:Core/Src/Testbench.c **** HAL_Delay(100); + 513 .loc 1 104 4 view .LVU126 + 514 0016 6420 movs r0, #100 + 515 .LVL43: + 516 .loc 1 104 4 is_stmt 0 view .LVU127 + ARM GAS /tmp/ccSPu85t.s page 12 + + + 517 0018 FFF7FEFF bl HAL_Delay + 518 .LVL44: + 105:Core/Src/Testbench.c **** canTestSendAnswer(data); + 519 .loc 1 105 4 is_stmt 1 view .LVU128 + 520 001c 2846 mov r0, r5 + 521 001e FFF7FEFF bl canTestSendAnswer + 522 .LVL45: + 106:Core/Src/Testbench.c **** break; + 523 .loc 1 106 4 view .LVU129 + 524 .L35: + 107:Core/Src/Testbench.c **** case VOLTAGE_TEST: + 108:Core/Src/Testbench.c **** HAL_Delay(100); + 109:Core/Src/Testbench.c **** amsReadCellVoltages(&module); + 110:Core/Src/Testbench.c **** ams_can_send_heartbeat(); + 111:Core/Src/Testbench.c **** break; + 112:Core/Src/Testbench.c **** case TEMP_TEST: + 113:Core/Src/Testbench.c **** HAL_Delay(1000); + 114:Core/Src/Testbench.c **** readTemperatures(); + 115:Core/Src/Testbench.c **** break; + 116:Core/Src/Testbench.c **** case EPROM_TEST: + 117:Core/Src/Testbench.c **** HAL_Delay(1000); + 118:Core/Src/Testbench.c **** for(uint16_t i = 1; i < 9; i++ ){ + 119:Core/Src/Testbench.c **** if(i == 4){ + 120:Core/Src/Testbench.c **** writeeeprom(i*3, 0x42); + 121:Core/Src/Testbench.c **** }else{ + 122:Core/Src/Testbench.c **** writeeeprom(i*3, 0x69); + 123:Core/Src/Testbench.c **** } + 124:Core/Src/Testbench.c **** } + 125:Core/Src/Testbench.c **** + 126:Core/Src/Testbench.c **** HAL_Delay(1000); + 127:Core/Src/Testbench.c **** for(uint16_t i = 1; i < 9; i++ ){ + 128:Core/Src/Testbench.c **** data[i-1] = readeeprom(i*3); + 129:Core/Src/Testbench.c **** } + 130:Core/Src/Testbench.c **** canTestSendAnswer(data); + 131:Core/Src/Testbench.c **** break; + 132:Core/Src/Testbench.c **** case BALANCING_TEST: + 133:Core/Src/Testbench.c **** HAL_Delay(1000); + 134:Core/Src/Testbench.c **** for(int i = 0; i < 17; i++){ + 135:Core/Src/Testbench.c **** amsConfigBalancing(0x00001<15_48JJ|^ z%%r4XO(`_Xekmk2RkNK60+mURx=X-8)~ZYLX`^Ua4=ruvhu@}pczq`trP z%;e_4y;mO*wc?mu?QbZ0dfv<3GSo|%5cO{!wQEHE@r5zP^}x3fYwtCC^=Y}mSXKDM zvoGqe>hsDMZxM+QY1S(}`@Z%;o7c33By_$0!p`HDOghxdc}muLj&)TVFLw))$<>GN z_BD8)FdB{@P3F08xU_u@z9$^*_>vc+WO4ijyVXbXdZN~UOondhAfJUQI;VBHI?(Xi zGY;id@y*sCo6m9HPM(zFgY$$ig*0d!mi$~3V)4JD_OvdQ%SnRz$b&e_?+3t@LSIM0-KEci!0$62 zgh;7+>dz-t3+{#YMsTHfE2^4z892Jo{~O?G)Yn2u>3f@RBz-J7x|3_~FswB1eB5>K zLCS~s+sM5s^tAx*T73)#Rb&;c^0s$ELF*^MnQHnAtqd)AyA)w)my)DM5kBogBKj0j zq-BZNu84qk5w*TENWCo6-cJr9ikPoa?!3DcQLdd!#2!T~(E8A__dG>ZXy2tyyiXC8 zLXRMJZ%qF(#aQ9J;V{Lxm()M0+7sG?)WnU7FwDO09^w6*B79~9lhJ#VB8trJ?VE)6 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/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-closer.o) +exit /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-exit.o) + /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +fflush /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fflush.o) +g_pfnVectors build/startup_stm32f302xc.o +hardware_init_hook /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +hcan build/main.o + build/stm32f3xx_it.o +hi2c1 build/main.o +hi2c2 build/main.o +hspi1 build/main.o +initAMS build/ADBMS_Abstraction.o + build/AMS_HighLevel.o +initialise_monitor_handles build/syscalls.o +integrateCurrent build/AMS_HighLevel.o +internalbalancingalgo build/AMS_HighLevel.o +lastAMSState build/AMS_HighLevel.o +lastticks build/AMS_HighLevel.o +main build/main.o + build/startup_stm32f302xc.o + /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +malloc /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-__atexit.o) +mcuAdbmsCSHigh build/ADBMS_LL_Driver.o +mcuAdbmsCSLow build/ADBMS_LL_Driver.o +mcuDelay build/ADBMS_LL_Driver.o + build/ADBMS_Abstraction.o +mcuSPIReceive build/ADBMS_LL_Driver.o +mcuSPITransmit build/ADBMS_LL_Driver.o +mcuSPITransmitReceive build/ADBMS_LL_Driver.o +memset /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) + build/main.o + /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +module build/AMS_HighLevel.o + build/Testbench.o + build/AMS_CAN.o +numberofAux build/AMS_HighLevel.o +numberofCells build/AMS_HighLevel.o +numberofauxchannels build/ADBMS_Abstraction.o +numberofcells build/ADBMS_Abstraction.o +pFlash build/stm32f3xx_hal_flash.o + build/stm32f3xx_hal_flash_ex.o +readCMD build/ADBMS_LL_Driver.o + build/ADBMS_Abstraction.o +readGPIO build/ADBMS_Abstraction.o +readTemperatures build/Testbench.o +readeeprom build/main.o + build/Testbench.o +resetData build/Testbench.o +sensor_init build/main.o + build/Testbench.o +sensor_read build/main.o + build/Testbench.o +software_init_hook /home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-eabi-gcc/12.2.1-1.2.1/.content/bin/../lib/gcc/arm-none-eabi/12.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +startbalancingthreshold build/AMS_HighLevel.o +stateofcharge build/AMS_HighLevel.o +stopbalancingthreshold build/AMS_HighLevel.o +testLoop build/Testbench.o + build/main.o +updatePEC build/ADBMS_LL_Driver.o +uwTick build/stm32f3xx_hal.o +uwTickFreq build/stm32f3xx_hal.o +uwTickPrio build/stm32f3xx_hal.o + build/stm32f3xx_hal_rcc.o +writeCMD build/ADBMS_LL_Driver.o + build/ADBMS_Abstraction.o +writeErrorLog build/AMS_HighLevel.o +writeWarningLog build/AMS_HighLevel.o +writeeeprom build/main.o + build/Testbench.o diff --git a/BMS_Testbench/BMS_Software_V1/build/main.d b/BMS_Testbench/BMS_Software_V1/build/main.d new file mode 100644 index 0000000..1e10e3c --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/main.d @@ -0,0 +1,73 @@ +build/main.o: Core/Src/main.c Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Core/Inc/ADBMS_CMD_MAKROS.h Core/Inc/ADBMS_CMD_MAKROS.h \ + Core/Inc/AMS_HighLevel.h Core/Inc/ADBMS_Abstraction.h Core/Inc/AMS_CAN.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Core/Inc/Testbench.h +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/AMS_CAN.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/Testbench.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/main.lst b/BMS_Testbench/BMS_Software_V1/build/main.lst new file mode 100644 index 0000000..ba586e2 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/main.lst @@ -0,0 +1,2091 @@ +ARM GAS /tmp/cctSQMH6.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "main.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/main.c" + 20 .section .text.MX_GPIO_Init,"ax",%progbits + 21 .align 1 + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 MX_GPIO_Init: + 27 .LFB136: + 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/main.c **** /** + 3:Core/Src/main.c **** ****************************************************************************** + 4:Core/Src/main.c **** * @file : main.c + 5:Core/Src/main.c **** * @brief : Main program body + 6:Core/Src/main.c **** ****************************************************************************** + 7:Core/Src/main.c **** * @attention + 8:Core/Src/main.c **** * + 9:Core/Src/main.c **** * Copyright (c) 2023 STMicroelectronics. + 10:Core/Src/main.c **** * All rights reserved. + 11:Core/Src/main.c **** * + 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Core/Src/main.c **** * in the root directory of this software component. + 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Core/Src/main.c **** * + 16:Core/Src/main.c **** ****************************************************************************** + 17:Core/Src/main.c **** */ + 18:Core/Src/main.c **** /* USER CODE END Header */ + 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ + 20:Core/Src/main.c **** #include "main.h" + 21:Core/Src/main.c **** + 22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ + 23:Core/Src/main.c **** /* USER CODE BEGIN Includes */ + 24:Core/Src/main.c **** #include "ADBMS_Abstraction.h" + 25:Core/Src/main.c **** #include "ADBMS_CMD_MAKROS.h" + 26:Core/Src/main.c **** #include "AMS_HighLevel.h" + 27:Core/Src/main.c **** #include "AMS_CAN.h" + 28:Core/Src/main.c **** #include "Testbench.h" + 29:Core/Src/main.c **** /* USER CODE END Includes */ + 30:Core/Src/main.c **** + 31:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ + ARM GAS /tmp/cctSQMH6.s page 2 + + + 32:Core/Src/main.c **** /* USER CODE BEGIN PTD */ + 33:Core/Src/main.c **** + 34:Core/Src/main.c **** /* USER CODE END PTD */ + 35:Core/Src/main.c **** + 36:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ + 37:Core/Src/main.c **** /* USER CODE BEGIN PD */ + 38:Core/Src/main.c **** #define N_SENSORS 12 + 39:Core/Src/main.c **** #define eAdress 0xAE + 40:Core/Src/main.c **** /* USER CODE END PD */ + 41:Core/Src/main.c **** + 42:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ + 43:Core/Src/main.c **** /* USER CODE BEGIN PM */ + 44:Core/Src/main.c **** + 45:Core/Src/main.c **** /* USER CODE END PM */ + 46:Core/Src/main.c **** + 47:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ + 48:Core/Src/main.c **** CAN_HandleTypeDef hcan; + 49:Core/Src/main.c **** + 50:Core/Src/main.c **** I2C_HandleTypeDef hi2c1; + 51:Core/Src/main.c **** I2C_HandleTypeDef hi2c2; + 52:Core/Src/main.c **** + 53:Core/Src/main.c **** SPI_HandleTypeDef hspi1; + 54:Core/Src/main.c **** + 55:Core/Src/main.c **** /* USER CODE BEGIN PV */ + 56:Core/Src/main.c **** static uint32_t last_error = 0; + 57:Core/Src/main.c **** extern uint8_t canTestData; + 58:Core/Src/main.c **** extern int PENDING_MESSAGE_HANDLE; + 59:Core/Src/main.c **** extern + 60:Core/Src/main.c **** /* USER CODE END PV */ + 61:Core/Src/main.c **** + 62:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ + 63:Core/Src/main.c **** void SystemClock_Config(void); + 64:Core/Src/main.c **** static void MX_GPIO_Init(void); + 65:Core/Src/main.c **** static void MX_CAN_Init(void); + 66:Core/Src/main.c **** static void MX_I2C1_Init(void); + 67:Core/Src/main.c **** static void MX_I2C2_Init(void); + 68:Core/Src/main.c **** static void MX_SPI1_Init(void); + 69:Core/Src/main.c **** /* USER CODE BEGIN PFP */ + 70:Core/Src/main.c **** void lowPowerLoop(void); + 71:Core/Src/main.c **** HAL_StatusTypeDef sensor_init(int); + 72:Core/Src/main.c **** HAL_StatusTypeDef sensor_read(int, uint16_t*); + 73:Core/Src/main.c **** uint8_t readeeprom(uint16_t address); + 74:Core/Src/main.c **** void writeeeprom(uint16_t address, uint8_t data); + 75:Core/Src/main.c **** + 76:Core/Src/main.c **** + 77:Core/Src/main.c **** /* USER CODE END PFP */ + 78:Core/Src/main.c **** + 79:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ + 80:Core/Src/main.c **** /* USER CODE BEGIN 0 */ + 81:Core/Src/main.c **** + 82:Core/Src/main.c **** /* USER CODE END 0 */ + 83:Core/Src/main.c **** + 84:Core/Src/main.c **** /** + 85:Core/Src/main.c **** * @brief The application entry point. + 86:Core/Src/main.c **** * @retval int + 87:Core/Src/main.c **** */ + 88:Core/Src/main.c **** int main(void) + ARM GAS /tmp/cctSQMH6.s page 3 + + + 89:Core/Src/main.c **** { + 90:Core/Src/main.c **** /* USER CODE BEGIN 1 */ + 91:Core/Src/main.c **** + 92:Core/Src/main.c **** /* USER CODE END 1 */ + 93:Core/Src/main.c **** + 94:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ + 95:Core/Src/main.c **** + 96:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + 97:Core/Src/main.c **** HAL_Init(); + 98:Core/Src/main.c **** + 99:Core/Src/main.c **** /* USER CODE BEGIN Init */ + 100:Core/Src/main.c **** + 101:Core/Src/main.c **** /* USER CODE END Init */ + 102:Core/Src/main.c **** + 103:Core/Src/main.c **** /* Configure the system clock */ + 104:Core/Src/main.c **** SystemClock_Config(); + 105:Core/Src/main.c **** + 106:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ + 107:Core/Src/main.c **** + 108:Core/Src/main.c **** /* USER CODE END SysInit */ + 109:Core/Src/main.c **** + 110:Core/Src/main.c **** /* Initialize all configured peripherals */ + 111:Core/Src/main.c **** MX_GPIO_Init(); + 112:Core/Src/main.c **** MX_CAN_Init(); + 113:Core/Src/main.c **** MX_I2C1_Init(); + 114:Core/Src/main.c **** MX_I2C2_Init(); + 115:Core/Src/main.c **** MX_SPI1_Init(); + 116:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + 117:Core/Src/main.c **** // eepromInitParameters(); + 118:Core/Src/main.c **** for (int i = 0; i < N_SENSORS; i++) { + 119:Core/Src/main.c **** if (sensor_init(i) != HAL_OK) { + 120:Core/Src/main.c **** last_error = HAL_GetTick(); + 121:Core/Src/main.c **** } + 122:Core/Src/main.c **** } + 123:Core/Src/main.c **** + 124:Core/Src/main.c **** AMS_Init(&hspi1); + 125:Core/Src/main.c **** ams_can_init(&hcan, &hcan); + 126:Core/Src/main.c **** //amsConfigAuxMeasurement(9); + 127:Core/Src/main.c **** + 128:Core/Src/main.c **** // startUARTConsole(&huart2, &module); + 129:Core/Src/main.c **** // htim2.Instance->CCR1 = 0x01FF; + 130:Core/Src/main.c **** // HAL_TIM_Base_Start(&htim2); + 131:Core/Src/main.c **** /* USER CODE END 2 */ + 132:Core/Src/main.c **** + 133:Core/Src/main.c **** /* Infinite loop */ + 134:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ + 135:Core/Src/main.c **** writeeeprom(1, 69); + 136:Core/Src/main.c **** uint16_t temperatures[N_SENSORS]; + 137:Core/Src/main.c **** AMS_Loop(); + 138:Core/Src/main.c **** while (1){ + 139:Core/Src/main.c **** if(BMS_IN_TEST_MODE == 1 ){ ////&& PENDING_MESSAGE_HANDLE == 1 + 140:Core/Src/main.c **** testLoop(&canTestData); + 141:Core/Src/main.c **** /* USER CODE END WHILE */ + 142:Core/Src/main.c **** /* USER CODE BEGIN 3 */ + 143:Core/Src/main.c **** + 144:Core/Src/main.c **** for (int i = 0; i < N_SENSORS; i++) { + 145:Core/Src/main.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { + ARM GAS /tmp/cctSQMH6.s page 4 + + + 146:Core/Src/main.c **** sensor_init(i); + 147:Core/Src/main.c **** last_error = HAL_GetTick(); + 148:Core/Src/main.c **** } + 149:Core/Src/main.c **** } + 150:Core/Src/main.c **** if(BMS_IN_TEST_MODE != 1){ + 151:Core/Src/main.c **** ams_can_send_heartbeat(); //for testing + 152:Core/Src/main.c **** } + 153:Core/Src/main.c **** } + 154:Core/Src/main.c **** } + 155:Core/Src/main.c **** + 156:Core/Src/main.c **** /* USER CODE END 3 */ + 157:Core/Src/main.c **** } + 158:Core/Src/main.c **** + 159:Core/Src/main.c **** /** + 160:Core/Src/main.c **** * @brief System Clock Configuration + 161:Core/Src/main.c **** * @retval None + 162:Core/Src/main.c **** */ + 163:Core/Src/main.c **** void SystemClock_Config(void) + 164:Core/Src/main.c **** { + 165:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 166:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 167:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 168:Core/Src/main.c **** + 169:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 170:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. + 171:Core/Src/main.c **** */ + 172:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE; + 173:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 174:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 175:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 177:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 178:Core/Src/main.c **** { + 179:Core/Src/main.c **** Error_Handler(); + 180:Core/Src/main.c **** } + 181:Core/Src/main.c **** + 182:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks + 183:Core/Src/main.c **** */ + 184:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 185:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 186:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; + 187:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 188:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 189:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 190:Core/Src/main.c **** + 191:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 192:Core/Src/main.c **** { + 193:Core/Src/main.c **** Error_Handler(); + 194:Core/Src/main.c **** } + 195:Core/Src/main.c **** PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C2; + 196:Core/Src/main.c **** PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; + 197:Core/Src/main.c **** PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_HSI; + 198:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 199:Core/Src/main.c **** { + 200:Core/Src/main.c **** Error_Handler(); + 201:Core/Src/main.c **** } + 202:Core/Src/main.c **** } + ARM GAS /tmp/cctSQMH6.s page 5 + + + 203:Core/Src/main.c **** + 204:Core/Src/main.c **** /** + 205:Core/Src/main.c **** * @brief CAN Initialization Function + 206:Core/Src/main.c **** * @param None + 207:Core/Src/main.c **** * @retval None + 208:Core/Src/main.c **** */ + 209:Core/Src/main.c **** static void MX_CAN_Init(void) + 210:Core/Src/main.c **** { + 211:Core/Src/main.c **** + 212:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 0 */ + 213:Core/Src/main.c **** + 214:Core/Src/main.c **** /* USER CODE END CAN_Init 0 */ + 215:Core/Src/main.c **** + 216:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 1 */ + 217:Core/Src/main.c **** + 218:Core/Src/main.c **** /* USER CODE END CAN_Init 1 */ + 219:Core/Src/main.c **** hcan.Instance = CAN; + 220:Core/Src/main.c **** hcan.Init.Prescaler = 2; + 221:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; + 222:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; + 223:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_13TQ; + 224:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_2TQ; + 225:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; + 226:Core/Src/main.c **** hcan.Init.AutoBusOff = ENABLE; + 227:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; + 228:Core/Src/main.c **** hcan.Init.AutoRetransmission = ENABLE; + 229:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; + 230:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; + 231:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) + 232:Core/Src/main.c **** { + 233:Core/Src/main.c **** Error_Handler(); + 234:Core/Src/main.c **** } + 235:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 2 */ + 236:Core/Src/main.c **** + 237:Core/Src/main.c **** /* USER CODE END CAN_Init 2 */ + 238:Core/Src/main.c **** + 239:Core/Src/main.c **** } + 240:Core/Src/main.c **** + 241:Core/Src/main.c **** /** + 242:Core/Src/main.c **** * @brief I2C1 Initialization Function + 243:Core/Src/main.c **** * @param None + 244:Core/Src/main.c **** * @retval None + 245:Core/Src/main.c **** */ + 246:Core/Src/main.c **** static void MX_I2C1_Init(void) + 247:Core/Src/main.c **** { + 248:Core/Src/main.c **** + 249:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 0 */ + 250:Core/Src/main.c **** + 251:Core/Src/main.c **** /* USER CODE END I2C1_Init 0 */ + 252:Core/Src/main.c **** + 253:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 1 */ + 254:Core/Src/main.c **** + 255:Core/Src/main.c **** /* USER CODE END I2C1_Init 1 */ + 256:Core/Src/main.c **** hi2c1.Instance = I2C1; + 257:Core/Src/main.c **** hi2c1.Init.Timing = 0x2000090E; + 258:Core/Src/main.c **** hi2c1.Init.OwnAddress1 = 0; + 259:Core/Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + ARM GAS /tmp/cctSQMH6.s page 6 + + + 260:Core/Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 261:Core/Src/main.c **** hi2c1.Init.OwnAddress2 = 0; + 262:Core/Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 263:Core/Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 264:Core/Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 265:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 266:Core/Src/main.c **** { + 267:Core/Src/main.c **** Error_Handler(); + 268:Core/Src/main.c **** } + 269:Core/Src/main.c **** + 270:Core/Src/main.c **** /** Configure Analogue filter + 271:Core/Src/main.c **** */ + 272:Core/Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 273:Core/Src/main.c **** { + 274:Core/Src/main.c **** Error_Handler(); + 275:Core/Src/main.c **** } + 276:Core/Src/main.c **** + 277:Core/Src/main.c **** /** Configure Digital filter + 278:Core/Src/main.c **** */ + 279:Core/Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 280:Core/Src/main.c **** { + 281:Core/Src/main.c **** Error_Handler(); + 282:Core/Src/main.c **** } + 283:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 2 */ + 284:Core/Src/main.c **** + 285:Core/Src/main.c **** /* USER CODE END I2C1_Init 2 */ + 286:Core/Src/main.c **** + 287:Core/Src/main.c **** } + 288:Core/Src/main.c **** + 289:Core/Src/main.c **** /** + 290:Core/Src/main.c **** * @brief I2C2 Initialization Function + 291:Core/Src/main.c **** * @param None + 292:Core/Src/main.c **** * @retval None + 293:Core/Src/main.c **** */ + 294:Core/Src/main.c **** static void MX_I2C2_Init(void) + 295:Core/Src/main.c **** { + 296:Core/Src/main.c **** + 297:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 0 */ + 298:Core/Src/main.c **** + 299:Core/Src/main.c **** /* USER CODE END I2C2_Init 0 */ + 300:Core/Src/main.c **** + 301:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 1 */ + 302:Core/Src/main.c **** + 303:Core/Src/main.c **** /* USER CODE END I2C2_Init 1 */ + 304:Core/Src/main.c **** hi2c2.Instance = I2C2; + 305:Core/Src/main.c **** hi2c2.Init.Timing = 0x2000090E; + 306:Core/Src/main.c **** hi2c2.Init.OwnAddress1 = 0; + 307:Core/Src/main.c **** hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 308:Core/Src/main.c **** hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 309:Core/Src/main.c **** hi2c2.Init.OwnAddress2 = 0; + 310:Core/Src/main.c **** hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 311:Core/Src/main.c **** hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 312:Core/Src/main.c **** hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 313:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c2) != HAL_OK) + 314:Core/Src/main.c **** { + 315:Core/Src/main.c **** Error_Handler(); + 316:Core/Src/main.c **** } + ARM GAS /tmp/cctSQMH6.s page 7 + + + 317:Core/Src/main.c **** + 318:Core/Src/main.c **** /** Configure Analogue filter + 319:Core/Src/main.c **** */ + 320:Core/Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 321:Core/Src/main.c **** { + 322:Core/Src/main.c **** Error_Handler(); + 323:Core/Src/main.c **** } + 324:Core/Src/main.c **** + 325:Core/Src/main.c **** /** Configure Digital filter + 326:Core/Src/main.c **** */ + 327:Core/Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) + 328:Core/Src/main.c **** { + 329:Core/Src/main.c **** Error_Handler(); + 330:Core/Src/main.c **** } + 331:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 2 */ + 332:Core/Src/main.c **** + 333:Core/Src/main.c **** /* USER CODE END I2C2_Init 2 */ + 334:Core/Src/main.c **** + 335:Core/Src/main.c **** } + 336:Core/Src/main.c **** + 337:Core/Src/main.c **** /** + 338:Core/Src/main.c **** * @brief SPI1 Initialization Function + 339:Core/Src/main.c **** * @param None + 340:Core/Src/main.c **** * @retval None + 341:Core/Src/main.c **** */ + 342:Core/Src/main.c **** static void MX_SPI1_Init(void) + 343:Core/Src/main.c **** { + 344:Core/Src/main.c **** + 345:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 0 */ + 346:Core/Src/main.c **** + 347:Core/Src/main.c **** /* USER CODE END SPI1_Init 0 */ + 348:Core/Src/main.c **** + 349:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 1 */ + 350:Core/Src/main.c **** + 351:Core/Src/main.c **** /* USER CODE END SPI1_Init 1 */ + 352:Core/Src/main.c **** /* SPI1 parameter configuration*/ + 353:Core/Src/main.c **** hspi1.Instance = SPI1; + 354:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; + 355:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 356:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 357:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 358:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 359:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_SOFT; + 360:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; + 361:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 362:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 363:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 364:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 7; + 365:Core/Src/main.c **** hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + 366:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + 367:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) + 368:Core/Src/main.c **** { + 369:Core/Src/main.c **** Error_Handler(); + 370:Core/Src/main.c **** } + 371:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 2 */ + 372:Core/Src/main.c **** + 373:Core/Src/main.c **** /* USER CODE END SPI1_Init 2 */ + ARM GAS /tmp/cctSQMH6.s page 8 + + + 374:Core/Src/main.c **** + 375:Core/Src/main.c **** } + 376:Core/Src/main.c **** + 377:Core/Src/main.c **** /** + 378:Core/Src/main.c **** * @brief GPIO Initialization Function + 379:Core/Src/main.c **** * @param None + 380:Core/Src/main.c **** * @retval None + 381:Core/Src/main.c **** */ + 382:Core/Src/main.c **** static void MX_GPIO_Init(void) + 383:Core/Src/main.c **** { + 28 .loc 1 383 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 32 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 0000 70B5 push {r4, r5, r6, lr} + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 4, -16 + 35 .cfi_offset 5, -12 + 36 .cfi_offset 6, -8 + 37 .cfi_offset 14, -4 + 38 0002 88B0 sub sp, sp, #32 + 39 .cfi_def_cfa_offset 48 + 384:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 40 .loc 1 384 3 view .LVU1 + 41 .loc 1 384 20 is_stmt 0 view .LVU2 + 42 0004 0024 movs r4, #0 + 43 0006 0394 str r4, [sp, #12] + 44 0008 0494 str r4, [sp, #16] + 45 000a 0594 str r4, [sp, #20] + 46 000c 0694 str r4, [sp, #24] + 47 000e 0794 str r4, [sp, #28] + 385:Core/Src/main.c **** + 386:Core/Src/main.c **** /* GPIO Ports Clock Enable */ + 387:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); + 48 .loc 1 387 3 is_stmt 1 view .LVU3 + 49 .LBB4: + 50 .loc 1 387 3 view .LVU4 + 51 .loc 1 387 3 view .LVU5 + 52 0010 204B ldr r3, .L3 + 53 0012 5A69 ldr r2, [r3, #20] + 54 0014 42F48002 orr r2, r2, #4194304 + 55 0018 5A61 str r2, [r3, #20] + 56 .loc 1 387 3 view .LVU6 + 57 001a 5A69 ldr r2, [r3, #20] + 58 001c 02F48002 and r2, r2, #4194304 + 59 0020 0092 str r2, [sp] + 60 .loc 1 387 3 view .LVU7 + 61 0022 009A ldr r2, [sp] + 62 .LBE4: + 63 .loc 1 387 3 view .LVU8 + 388:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 64 .loc 1 388 3 view .LVU9 + 65 .LBB5: + 66 .loc 1 388 3 view .LVU10 + 67 .loc 1 388 3 view .LVU11 + 68 0024 5A69 ldr r2, [r3, #20] + 69 0026 42F40032 orr r2, r2, #131072 + ARM GAS /tmp/cctSQMH6.s page 9 + + + 70 002a 5A61 str r2, [r3, #20] + 71 .loc 1 388 3 view .LVU12 + 72 002c 5A69 ldr r2, [r3, #20] + 73 002e 02F40032 and r2, r2, #131072 + 74 0032 0192 str r2, [sp, #4] + 75 .loc 1 388 3 view .LVU13 + 76 0034 019A ldr r2, [sp, #4] + 77 .LBE5: + 78 .loc 1 388 3 view .LVU14 + 389:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 79 .loc 1 389 3 view .LVU15 + 80 .LBB6: + 81 .loc 1 389 3 view .LVU16 + 82 .loc 1 389 3 view .LVU17 + 83 0036 5A69 ldr r2, [r3, #20] + 84 0038 42F48022 orr r2, r2, #262144 + 85 003c 5A61 str r2, [r3, #20] + 86 .loc 1 389 3 view .LVU18 + 87 003e 5B69 ldr r3, [r3, #20] + 88 0040 03F48023 and r3, r3, #262144 + 89 0044 0293 str r3, [sp, #8] + 90 .loc 1 389 3 view .LVU19 + 91 0046 029B ldr r3, [sp, #8] + 92 .LBE6: + 93 .loc 1 389 3 view .LVU20 + 390:Core/Src/main.c **** + 391:Core/Src/main.c **** /*Configure GPIO pin Output Level */ + 392:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, CSB_Pin|Status_3_Pin, GPIO_PIN_RESET); + 94 .loc 1 392 3 view .LVU21 + 95 0048 2246 mov r2, r4 + 96 004a 4FF48871 mov r1, #272 + 97 004e 4FF09040 mov r0, #1207959552 + 98 0052 FFF7FEFF bl HAL_GPIO_WritePin + 99 .LVL0: + 393:Core/Src/main.c **** + 394:Core/Src/main.c **** /*Configure GPIO pin Output Level */ + 395:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOB, Status_0_Pin|Status_1_Pin|Status_2_Pin, GPIO_PIN_RESET); + 100 .loc 1 395 3 view .LVU22 + 101 0056 104D ldr r5, .L3+4 + 102 0058 2246 mov r2, r4 + 103 005a 4FF46041 mov r1, #57344 + 104 005e 2846 mov r0, r5 + 105 0060 FFF7FEFF bl HAL_GPIO_WritePin + 106 .LVL1: + 396:Core/Src/main.c **** + 397:Core/Src/main.c **** /*Configure GPIO pins : CSB_Pin Status_3_Pin */ + 398:Core/Src/main.c **** GPIO_InitStruct.Pin = CSB_Pin|Status_3_Pin; + 107 .loc 1 398 3 view .LVU23 + 108 .loc 1 398 23 is_stmt 0 view .LVU24 + 109 0064 4FF48873 mov r3, #272 + 110 0068 0393 str r3, [sp, #12] + 399:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 111 .loc 1 399 3 is_stmt 1 view .LVU25 + 112 .loc 1 399 24 is_stmt 0 view .LVU26 + 113 006a 0126 movs r6, #1 + 114 006c 0496 str r6, [sp, #16] + 400:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + ARM GAS /tmp/cctSQMH6.s page 10 + + + 115 .loc 1 400 3 is_stmt 1 view .LVU27 + 116 .loc 1 400 24 is_stmt 0 view .LVU28 + 117 006e 0594 str r4, [sp, #20] + 401:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 118 .loc 1 401 3 is_stmt 1 view .LVU29 + 119 .loc 1 401 25 is_stmt 0 view .LVU30 + 120 0070 0694 str r4, [sp, #24] + 402:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 121 .loc 1 402 3 is_stmt 1 view .LVU31 + 122 0072 03A9 add r1, sp, #12 + 123 0074 4FF09040 mov r0, #1207959552 + 124 0078 FFF7FEFF bl HAL_GPIO_Init + 125 .LVL2: + 403:Core/Src/main.c **** + 404:Core/Src/main.c **** /*Configure GPIO pins : Status_0_Pin Status_1_Pin Status_2_Pin */ + 405:Core/Src/main.c **** GPIO_InitStruct.Pin = Status_0_Pin|Status_1_Pin|Status_2_Pin; + 126 .loc 1 405 3 view .LVU32 + 127 .loc 1 405 23 is_stmt 0 view .LVU33 + 128 007c 4FF46043 mov r3, #57344 + 129 0080 0393 str r3, [sp, #12] + 406:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 130 .loc 1 406 3 is_stmt 1 view .LVU34 + 131 .loc 1 406 24 is_stmt 0 view .LVU35 + 132 0082 0496 str r6, [sp, #16] + 407:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 133 .loc 1 407 3 is_stmt 1 view .LVU36 + 134 .loc 1 407 24 is_stmt 0 view .LVU37 + 135 0084 0594 str r4, [sp, #20] + 408:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 136 .loc 1 408 3 is_stmt 1 view .LVU38 + 137 .loc 1 408 25 is_stmt 0 view .LVU39 + 138 0086 0694 str r4, [sp, #24] + 409:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 139 .loc 1 409 3 is_stmt 1 view .LVU40 + 140 0088 03A9 add r1, sp, #12 + 141 008a 2846 mov r0, r5 + 142 008c FFF7FEFF bl HAL_GPIO_Init + 143 .LVL3: + 410:Core/Src/main.c **** + 411:Core/Src/main.c **** } + 144 .loc 1 411 1 is_stmt 0 view .LVU41 + 145 0090 08B0 add sp, sp, #32 + 146 .cfi_def_cfa_offset 16 + 147 @ sp needed + 148 0092 70BD pop {r4, r5, r6, pc} + 149 .L4: + 150 .align 2 + 151 .L3: + 152 0094 00100240 .word 1073876992 + 153 0098 00040048 .word 1207960576 + 154 .cfi_endproc + 155 .LFE136: + 157 .section .text.sensor_init,"ax",%progbits + 158 .align 1 + 159 .global sensor_init + 160 .syntax unified + 161 .thumb + ARM GAS /tmp/cctSQMH6.s page 11 + + + 162 .thumb_func + 164 sensor_init: + 165 .LVL4: + 166 .LFB137: + 412:Core/Src/main.c **** + 413:Core/Src/main.c **** /* USER CODE BEGIN 4 */ + 414:Core/Src/main.c **** HAL_StatusTypeDef sensor_init(int n) { + 167 .loc 1 414 38 is_stmt 1 view -0 + 168 .cfi_startproc + 169 @ args = 0, pretend = 0, frame = 8 + 170 @ frame_needed = 0, uses_anonymous_args = 0 + 171 .loc 1 414 38 is_stmt 0 view .LVU43 + 172 0000 00B5 push {lr} + 173 .cfi_def_cfa_offset 4 + 174 .cfi_offset 14, -4 + 175 0002 85B0 sub sp, sp, #20 + 176 .cfi_def_cfa_offset 24 + 415:Core/Src/main.c **** uint16_t addr = (0b1000000 | n) << 1; + 177 .loc 1 415 3 is_stmt 1 view .LVU44 + 178 .loc 1 415 35 is_stmt 0 view .LVU45 + 179 0004 4100 lsls r1, r0, #1 + 180 0006 41F08001 orr r1, r1, #128 + 181 000a 09B2 sxth r1, r1 + 182 .loc 1 415 12 view .LVU46 + 183 000c 89B2 uxth r1, r1 + 184 .LVL5: + 416:Core/Src/main.c **** uint8_t data[] = {0}; + 185 .loc 1 416 3 is_stmt 1 view .LVU47 + 186 .loc 1 416 11 is_stmt 0 view .LVU48 + 187 000e 0023 movs r3, #0 + 188 0010 8DF80C30 strb r3, [sp, #12] + 417:Core/Src/main.c **** return HAL_I2C_Master_Transmit(&hi2c1, addr, data, sizeof(data), 100); + 189 .loc 1 417 3 is_stmt 1 view .LVU49 + 190 .loc 1 417 10 is_stmt 0 view .LVU50 + 191 0014 6423 movs r3, #100 + 192 0016 0093 str r3, [sp] + 193 0018 0123 movs r3, #1 + 194 001a 03AA add r2, sp, #12 + 195 001c 0248 ldr r0, .L7 + 196 .LVL6: + 197 .loc 1 417 10 view .LVU51 + 198 001e FFF7FEFF bl HAL_I2C_Master_Transmit + 199 .LVL7: + 418:Core/Src/main.c **** } + 200 .loc 1 418 1 view .LVU52 + 201 0022 05B0 add sp, sp, #20 + 202 .cfi_def_cfa_offset 4 + 203 @ sp needed + 204 0024 5DF804FB ldr pc, [sp], #4 + 205 .L8: + 206 .align 2 + 207 .L7: + 208 0028 00000000 .word hi2c1 + 209 .cfi_endproc + 210 .LFE137: + 212 .section .text.sensor_read,"ax",%progbits + 213 .align 1 + ARM GAS /tmp/cctSQMH6.s page 12 + + + 214 .global sensor_read + 215 .syntax unified + 216 .thumb + 217 .thumb_func + 219 sensor_read: + 220 .LVL8: + 221 .LFB138: + 419:Core/Src/main.c **** + 420:Core/Src/main.c **** HAL_StatusTypeDef sensor_read(int n, uint16_t *res) { + 222 .loc 1 420 53 is_stmt 1 view -0 + 223 .cfi_startproc + 224 @ args = 0, pretend = 0, frame = 8 + 225 @ frame_needed = 0, uses_anonymous_args = 0 + 226 .loc 1 420 53 is_stmt 0 view .LVU54 + 227 0000 10B5 push {r4, lr} + 228 .cfi_def_cfa_offset 8 + 229 .cfi_offset 4, -8 + 230 .cfi_offset 14, -4 + 231 0002 84B0 sub sp, sp, #16 + 232 .cfi_def_cfa_offset 24 + 233 0004 0C46 mov r4, r1 + 421:Core/Src/main.c **** uint16_t addr = (0b1000000 | n) << 1; + 234 .loc 1 421 3 is_stmt 1 view .LVU55 + 235 .loc 1 421 35 is_stmt 0 view .LVU56 + 236 0006 4000 lsls r0, r0, #1 + 237 .LVL9: + 238 .loc 1 421 35 view .LVU57 + 239 0008 00B2 sxth r0, r0 + 240 .LVL10: + 422:Core/Src/main.c **** addr |= 1; // Read + 241 .loc 1 422 3 is_stmt 1 view .LVU58 + 242 .loc 1 422 8 is_stmt 0 view .LVU59 + 243 000a 40F08100 orr r0, r0, #129 + 244 .LVL11: + 423:Core/Src/main.c **** uint8_t result[2]; + 245 .loc 1 423 3 is_stmt 1 view .LVU60 + 424:Core/Src/main.c **** HAL_StatusTypeDef status = + 246 .loc 1 424 3 view .LVU61 + 425:Core/Src/main.c **** HAL_I2C_Master_Receive(&hi2c1, addr, result, sizeof(result), 100); + 247 .loc 1 425 7 is_stmt 0 view .LVU62 + 248 000e 6423 movs r3, #100 + 249 0010 0093 str r3, [sp] + 250 0012 0223 movs r3, #2 + 251 0014 03AA add r2, sp, #12 + 252 0016 81B2 uxth r1, r0 + 253 .LVL12: + 254 .loc 1 425 7 view .LVU63 + 255 0018 0648 ldr r0, .L12 + 256 .LVL13: + 257 .loc 1 425 7 view .LVU64 + 258 001a FFF7FEFF bl HAL_I2C_Master_Receive + 259 .LVL14: + 426:Core/Src/main.c **** if (status == HAL_OK) { + 260 .loc 1 426 3 is_stmt 1 view .LVU65 + 261 .loc 1 426 6 is_stmt 0 view .LVU66 + 262 001e 30B9 cbnz r0, .L10 + 427:Core/Src/main.c **** *res = (result[0] << 8) | result[1]; + ARM GAS /tmp/cctSQMH6.s page 13 + + + 263 .loc 1 427 5 is_stmt 1 view .LVU67 + 264 .loc 1 427 19 is_stmt 0 view .LVU68 + 265 0020 9DF80C20 ldrb r2, [sp, #12] @ zero_extendqisi2 + 266 .loc 1 427 37 view .LVU69 + 267 0024 9DF80D30 ldrb r3, [sp, #13] @ zero_extendqisi2 + 268 .loc 1 427 29 view .LVU70 + 269 0028 43EA0223 orr r3, r3, r2, lsl #8 + 270 .loc 1 427 10 view .LVU71 + 271 002c 2380 strh r3, [r4] @ movhi + 272 .L10: + 428:Core/Src/main.c **** } + 429:Core/Src/main.c **** return status; + 273 .loc 1 429 3 is_stmt 1 view .LVU72 + 430:Core/Src/main.c **** } + 274 .loc 1 430 1 is_stmt 0 view .LVU73 + 275 002e 04B0 add sp, sp, #16 + 276 .cfi_def_cfa_offset 8 + 277 @ sp needed + 278 0030 10BD pop {r4, pc} + 279 .LVL15: + 280 .L13: + 281 .loc 1 430 1 view .LVU74 + 282 0032 00BF .align 2 + 283 .L12: + 284 0034 00000000 .word hi2c1 + 285 .cfi_endproc + 286 .LFE138: + 288 .section .text.readeeprom,"ax",%progbits + 289 .align 1 + 290 .global readeeprom + 291 .syntax unified + 292 .thumb + 293 .thumb_func + 295 readeeprom: + 296 .LVL16: + 297 .LFB139: + 431:Core/Src/main.c **** + 432:Core/Src/main.c **** uint8_t readeeprom(uint16_t address){ + 298 .loc 1 432 37 is_stmt 1 view -0 + 299 .cfi_startproc + 300 @ args = 0, pretend = 0, frame = 8 + 301 @ frame_needed = 0, uses_anonymous_args = 0 + 302 .loc 1 432 37 is_stmt 0 view .LVU76 + 303 0000 00B5 push {lr} + 304 .cfi_def_cfa_offset 4 + 305 .cfi_offset 14, -4 + 306 0002 87B0 sub sp, sp, #28 + 307 .cfi_def_cfa_offset 32 + 308 0004 0246 mov r2, r0 + 433:Core/Src/main.c **** uint8_t data = 0; + 309 .loc 1 433 2 is_stmt 1 view .LVU77 + 310 .loc 1 433 10 is_stmt 0 view .LVU78 + 311 0006 0023 movs r3, #0 + 312 0008 8DF81730 strb r3, [sp, #23] + 434:Core/Src/main.c **** //uint8_t* address2 = (uint8_t*) &address; + 435:Core/Src/main.c **** //HAL_I2C_Master_Transmit(&hi2c2, 0xA0, address2, 2, 1000); + 436:Core/Src/main.c **** //HAL_I2C_Master_Receive(&hi2c2, 0xA0, &data, 1, 1000); + ARM GAS /tmp/cctSQMH6.s page 14 + + + 437:Core/Src/main.c **** HAL_I2C_Mem_Read(&hi2c2, 0xA0, address, 2, &data, 1 , 1000); + 313 .loc 1 437 2 is_stmt 1 view .LVU79 + 314 000c 4FF47A73 mov r3, #1000 + 315 0010 0293 str r3, [sp, #8] + 316 0012 0123 movs r3, #1 + 317 0014 0193 str r3, [sp, #4] + 318 0016 0DF11703 add r3, sp, #23 + 319 001a 0093 str r3, [sp] + 320 001c 0223 movs r3, #2 + 321 001e A021 movs r1, #160 + 322 0020 0348 ldr r0, .L16 + 323 .LVL17: + 324 .loc 1 437 2 is_stmt 0 view .LVU80 + 325 0022 FFF7FEFF bl HAL_I2C_Mem_Read + 326 .LVL18: + 438:Core/Src/main.c **** //HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + 439:Core/Src/main.c **** // uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t + 440:Core/Src/main.c **** return data; + 327 .loc 1 440 2 is_stmt 1 view .LVU81 + 441:Core/Src/main.c **** } + 328 .loc 1 441 1 is_stmt 0 view .LVU82 + 329 0026 9DF81700 ldrb r0, [sp, #23] @ zero_extendqisi2 + 330 002a 07B0 add sp, sp, #28 + 331 .cfi_def_cfa_offset 4 + 332 @ sp needed + 333 002c 5DF804FB ldr pc, [sp], #4 + 334 .L17: + 335 .align 2 + 336 .L16: + 337 0030 00000000 .word hi2c2 + 338 .cfi_endproc + 339 .LFE139: + 341 .section .text.writeeeprom,"ax",%progbits + 342 .align 1 + 343 .global writeeeprom + 344 .syntax unified + 345 .thumb + 346 .thumb_func + 348 writeeeprom: + 349 .LVL19: + 350 .LFB140: + 442:Core/Src/main.c **** + 443:Core/Src/main.c **** void writeeeprom(uint16_t address, uint8_t data){ + 351 .loc 1 443 49 is_stmt 1 view -0 + 352 .cfi_startproc + 353 @ args = 0, pretend = 0, frame = 8 + 354 @ frame_needed = 0, uses_anonymous_args = 0 + 355 .loc 1 443 49 is_stmt 0 view .LVU84 + 356 0000 00B5 push {lr} + 357 .cfi_def_cfa_offset 4 + 358 .cfi_offset 14, -4 + 359 0002 87B0 sub sp, sp, #28 + 360 .cfi_def_cfa_offset 32 + 361 0004 0246 mov r2, r0 + 362 0006 8DF81710 strb r1, [sp, #23] + 444:Core/Src/main.c **** HAL_I2C_Mem_Write(&hi2c2, 0xA0, address, 2, &data, 1, 1000); + 363 .loc 1 444 2 is_stmt 1 view .LVU85 + ARM GAS /tmp/cctSQMH6.s page 15 + + + 364 000a 4FF47A73 mov r3, #1000 + 365 000e 0293 str r3, [sp, #8] + 366 0010 0123 movs r3, #1 + 367 0012 0193 str r3, [sp, #4] + 368 0014 0DF11703 add r3, sp, #23 + 369 0018 0093 str r3, [sp] + 370 001a 0223 movs r3, #2 + 371 001c A021 movs r1, #160 + 372 .LVL20: + 373 .loc 1 444 2 is_stmt 0 view .LVU86 + 374 001e 0448 ldr r0, .L20 + 375 .LVL21: + 376 .loc 1 444 2 view .LVU87 + 377 0020 FFF7FEFF bl HAL_I2C_Mem_Write + 378 .LVL22: + 445:Core/Src/main.c **** HAL_Delay(5); + 379 .loc 1 445 2 is_stmt 1 view .LVU88 + 380 0024 0520 movs r0, #5 + 381 0026 FFF7FEFF bl HAL_Delay + 382 .LVL23: + 446:Core/Src/main.c **** } + 383 .loc 1 446 1 is_stmt 0 view .LVU89 + 384 002a 07B0 add sp, sp, #28 + 385 .cfi_def_cfa_offset 4 + 386 @ sp needed + 387 002c 5DF804FB ldr pc, [sp], #4 + 388 .L21: + 389 .align 2 + 390 .L20: + 391 0030 00000000 .word hi2c2 + 392 .cfi_endproc + 393 .LFE140: + 395 .section .text.Error_Handler,"ax",%progbits + 396 .align 1 + 397 .global Error_Handler + 398 .syntax unified + 399 .thumb + 400 .thumb_func + 402 Error_Handler: + 403 .LFB141: + 447:Core/Src/main.c **** /* USER CODE END 4 */ + 448:Core/Src/main.c **** + 449:Core/Src/main.c **** /** + 450:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. + 451:Core/Src/main.c **** * @retval None + 452:Core/Src/main.c **** */ + 453:Core/Src/main.c **** void Error_Handler(void) + 454:Core/Src/main.c **** { + 404 .loc 1 454 1 is_stmt 1 view -0 + 405 .cfi_startproc + 406 @ Volatile: function does not return. + 407 @ args = 0, pretend = 0, frame = 0 + 408 @ frame_needed = 0, uses_anonymous_args = 0 + 409 @ link register save eliminated. + 455:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ + 456:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ + 457:Core/Src/main.c **** __disable_irq(); + ARM GAS /tmp/cctSQMH6.s page 16 + + + 410 .loc 1 457 3 view .LVU91 + 411 .LBB7: + 412 .LBI7: + 413 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + ARM GAS /tmp/cctSQMH6.s page 17 + + + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + ARM GAS /tmp/cctSQMH6.s page 18 + + + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 414 .loc 2 140 27 view .LVU92 + 415 .LBB8: + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 416 .loc 2 142 3 view .LVU93 + 417 .syntax unified + 418 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 419 0000 72B6 cpsid i + 420 @ 0 "" 2 + 421 .thumb + 422 .syntax unified + 423 .L23: + 424 .LBE8: + 425 .LBE7: + 458:Core/Src/main.c **** while (1) + 426 .loc 1 458 3 discriminator 1 view .LVU94 + 459:Core/Src/main.c **** { + 460:Core/Src/main.c **** } + 427 .loc 1 460 3 discriminator 1 view .LVU95 + 458:Core/Src/main.c **** while (1) + 428 .loc 1 458 9 discriminator 1 view .LVU96 + 429 0002 FEE7 b .L23 + 430 .cfi_endproc + 431 .LFE141: + 433 .section .text.MX_CAN_Init,"ax",%progbits + 434 .align 1 + 435 .syntax unified + ARM GAS /tmp/cctSQMH6.s page 19 + + + 436 .thumb + 437 .thumb_func + 439 MX_CAN_Init: + 440 .LFB132: + 210:Core/Src/main.c **** + 441 .loc 1 210 1 view -0 + 442 .cfi_startproc + 443 @ args = 0, pretend = 0, frame = 0 + 444 @ frame_needed = 0, uses_anonymous_args = 0 + 445 0000 08B5 push {r3, lr} + 446 .cfi_def_cfa_offset 8 + 447 .cfi_offset 3, -8 + 448 .cfi_offset 14, -4 + 219:Core/Src/main.c **** hcan.Init.Prescaler = 2; + 449 .loc 1 219 3 view .LVU98 + 219:Core/Src/main.c **** hcan.Init.Prescaler = 2; + 450 .loc 1 219 17 is_stmt 0 view .LVU99 + 451 0002 0D48 ldr r0, .L28 + 452 0004 0D4B ldr r3, .L28+4 + 453 0006 0360 str r3, [r0] + 220:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; + 454 .loc 1 220 3 is_stmt 1 view .LVU100 + 220:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; + 455 .loc 1 220 23 is_stmt 0 view .LVU101 + 456 0008 0223 movs r3, #2 + 457 000a 4360 str r3, [r0, #4] + 221:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; + 458 .loc 1 221 3 is_stmt 1 view .LVU102 + 221:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; + 459 .loc 1 221 18 is_stmt 0 view .LVU103 + 460 000c 0023 movs r3, #0 + 461 000e 8360 str r3, [r0, #8] + 222:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_13TQ; + 462 .loc 1 222 3 is_stmt 1 view .LVU104 + 222:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_13TQ; + 463 .loc 1 222 27 is_stmt 0 view .LVU105 + 464 0010 C360 str r3, [r0, #12] + 223:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_2TQ; + 465 .loc 1 223 3 is_stmt 1 view .LVU106 + 223:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_2TQ; + 466 .loc 1 223 22 is_stmt 0 view .LVU107 + 467 0012 4FF44022 mov r2, #786432 + 468 0016 0261 str r2, [r0, #16] + 224:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; + 469 .loc 1 224 3 is_stmt 1 view .LVU108 + 224:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; + 470 .loc 1 224 22 is_stmt 0 view .LVU109 + 471 0018 4FF48012 mov r2, #1048576 + 472 001c 4261 str r2, [r0, #20] + 225:Core/Src/main.c **** hcan.Init.AutoBusOff = ENABLE; + 473 .loc 1 225 3 is_stmt 1 view .LVU110 + 225:Core/Src/main.c **** hcan.Init.AutoBusOff = ENABLE; + 474 .loc 1 225 31 is_stmt 0 view .LVU111 + 475 001e 0376 strb r3, [r0, #24] + 226:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; + 476 .loc 1 226 3 is_stmt 1 view .LVU112 + 226:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; + ARM GAS /tmp/cctSQMH6.s page 20 + + + 477 .loc 1 226 24 is_stmt 0 view .LVU113 + 478 0020 0122 movs r2, #1 + 479 0022 4276 strb r2, [r0, #25] + 227:Core/Src/main.c **** hcan.Init.AutoRetransmission = ENABLE; + 480 .loc 1 227 3 is_stmt 1 view .LVU114 + 227:Core/Src/main.c **** hcan.Init.AutoRetransmission = ENABLE; + 481 .loc 1 227 24 is_stmt 0 view .LVU115 + 482 0024 8376 strb r3, [r0, #26] + 228:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; + 483 .loc 1 228 3 is_stmt 1 view .LVU116 + 228:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; + 484 .loc 1 228 32 is_stmt 0 view .LVU117 + 485 0026 C276 strb r2, [r0, #27] + 229:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; + 486 .loc 1 229 3 is_stmt 1 view .LVU118 + 229:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; + 487 .loc 1 229 31 is_stmt 0 view .LVU119 + 488 0028 0377 strb r3, [r0, #28] + 230:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) + 489 .loc 1 230 3 is_stmt 1 view .LVU120 + 230:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) + 490 .loc 1 230 34 is_stmt 0 view .LVU121 + 491 002a 4377 strb r3, [r0, #29] + 231:Core/Src/main.c **** { + 492 .loc 1 231 3 is_stmt 1 view .LVU122 + 231:Core/Src/main.c **** { + 493 .loc 1 231 7 is_stmt 0 view .LVU123 + 494 002c FFF7FEFF bl HAL_CAN_Init + 495 .LVL24: + 231:Core/Src/main.c **** { + 496 .loc 1 231 6 view .LVU124 + 497 0030 00B9 cbnz r0, .L27 + 239:Core/Src/main.c **** + 498 .loc 1 239 1 view .LVU125 + 499 0032 08BD pop {r3, pc} + 500 .L27: + 233:Core/Src/main.c **** } + 501 .loc 1 233 5 is_stmt 1 view .LVU126 + 502 0034 FFF7FEFF bl Error_Handler + 503 .LVL25: + 504 .L29: + 505 .align 2 + 506 .L28: + 507 0038 00000000 .word hcan + 508 003c 00640040 .word 1073767424 + 509 .cfi_endproc + 510 .LFE132: + 512 .section .text.MX_I2C1_Init,"ax",%progbits + 513 .align 1 + 514 .syntax unified + 515 .thumb + 516 .thumb_func + 518 MX_I2C1_Init: + 519 .LFB133: + 247:Core/Src/main.c **** + 520 .loc 1 247 1 view -0 + 521 .cfi_startproc + ARM GAS /tmp/cctSQMH6.s page 21 + + + 522 @ args = 0, pretend = 0, frame = 0 + 523 @ frame_needed = 0, uses_anonymous_args = 0 + 524 0000 08B5 push {r3, lr} + 525 .cfi_def_cfa_offset 8 + 526 .cfi_offset 3, -8 + 527 .cfi_offset 14, -4 + 256:Core/Src/main.c **** hi2c1.Init.Timing = 0x2000090E; + 528 .loc 1 256 3 view .LVU128 + 256:Core/Src/main.c **** hi2c1.Init.Timing = 0x2000090E; + 529 .loc 1 256 18 is_stmt 0 view .LVU129 + 530 0002 1148 ldr r0, .L38 + 531 0004 114B ldr r3, .L38+4 + 532 0006 0360 str r3, [r0] + 257:Core/Src/main.c **** hi2c1.Init.OwnAddress1 = 0; + 533 .loc 1 257 3 is_stmt 1 view .LVU130 + 257:Core/Src/main.c **** hi2c1.Init.OwnAddress1 = 0; + 534 .loc 1 257 21 is_stmt 0 view .LVU131 + 535 0008 114B ldr r3, .L38+8 + 536 000a 4360 str r3, [r0, #4] + 258:Core/Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 537 .loc 1 258 3 is_stmt 1 view .LVU132 + 258:Core/Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 538 .loc 1 258 26 is_stmt 0 view .LVU133 + 539 000c 0023 movs r3, #0 + 540 000e 8360 str r3, [r0, #8] + 259:Core/Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 541 .loc 1 259 3 is_stmt 1 view .LVU134 + 259:Core/Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 542 .loc 1 259 29 is_stmt 0 view .LVU135 + 543 0010 0122 movs r2, #1 + 544 0012 C260 str r2, [r0, #12] + 260:Core/Src/main.c **** hi2c1.Init.OwnAddress2 = 0; + 545 .loc 1 260 3 is_stmt 1 view .LVU136 + 260:Core/Src/main.c **** hi2c1.Init.OwnAddress2 = 0; + 546 .loc 1 260 30 is_stmt 0 view .LVU137 + 547 0014 0361 str r3, [r0, #16] + 261:Core/Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 548 .loc 1 261 3 is_stmt 1 view .LVU138 + 261:Core/Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 549 .loc 1 261 26 is_stmt 0 view .LVU139 + 550 0016 4361 str r3, [r0, #20] + 262:Core/Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 551 .loc 1 262 3 is_stmt 1 view .LVU140 + 262:Core/Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 552 .loc 1 262 31 is_stmt 0 view .LVU141 + 553 0018 8361 str r3, [r0, #24] + 263:Core/Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 554 .loc 1 263 3 is_stmt 1 view .LVU142 + 263:Core/Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 555 .loc 1 263 30 is_stmt 0 view .LVU143 + 556 001a C361 str r3, [r0, #28] + 264:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 557 .loc 1 264 3 is_stmt 1 view .LVU144 + 264:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 558 .loc 1 264 28 is_stmt 0 view .LVU145 + 559 001c 0362 str r3, [r0, #32] + 265:Core/Src/main.c **** { + ARM GAS /tmp/cctSQMH6.s page 22 + + + 560 .loc 1 265 3 is_stmt 1 view .LVU146 + 265:Core/Src/main.c **** { + 561 .loc 1 265 7 is_stmt 0 view .LVU147 + 562 001e FFF7FEFF bl HAL_I2C_Init + 563 .LVL26: + 265:Core/Src/main.c **** { + 564 .loc 1 265 6 view .LVU148 + 565 0022 50B9 cbnz r0, .L35 + 272:Core/Src/main.c **** { + 566 .loc 1 272 3 is_stmt 1 view .LVU149 + 272:Core/Src/main.c **** { + 567 .loc 1 272 7 is_stmt 0 view .LVU150 + 568 0024 0021 movs r1, #0 + 569 0026 0848 ldr r0, .L38 + 570 0028 FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter + 571 .LVL27: + 272:Core/Src/main.c **** { + 572 .loc 1 272 6 view .LVU151 + 573 002c 38B9 cbnz r0, .L36 + 279:Core/Src/main.c **** { + 574 .loc 1 279 3 is_stmt 1 view .LVU152 + 279:Core/Src/main.c **** { + 575 .loc 1 279 7 is_stmt 0 view .LVU153 + 576 002e 0021 movs r1, #0 + 577 0030 0548 ldr r0, .L38 + 578 0032 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter + 579 .LVL28: + 279:Core/Src/main.c **** { + 580 .loc 1 279 6 view .LVU154 + 581 0036 20B9 cbnz r0, .L37 + 287:Core/Src/main.c **** + 582 .loc 1 287 1 view .LVU155 + 583 0038 08BD pop {r3, pc} + 584 .L35: + 267:Core/Src/main.c **** } + 585 .loc 1 267 5 is_stmt 1 view .LVU156 + 586 003a FFF7FEFF bl Error_Handler + 587 .LVL29: + 588 .L36: + 274:Core/Src/main.c **** } + 589 .loc 1 274 5 view .LVU157 + 590 003e FFF7FEFF bl Error_Handler + 591 .LVL30: + 592 .L37: + 281:Core/Src/main.c **** } + 593 .loc 1 281 5 view .LVU158 + 594 0042 FFF7FEFF bl Error_Handler + 595 .LVL31: + 596 .L39: + 597 0046 00BF .align 2 + 598 .L38: + 599 0048 00000000 .word hi2c1 + 600 004c 00540040 .word 1073763328 + 601 0050 0E090020 .word 536873230 + 602 .cfi_endproc + 603 .LFE133: + 605 .section .text.MX_I2C2_Init,"ax",%progbits + ARM GAS /tmp/cctSQMH6.s page 23 + + + 606 .align 1 + 607 .syntax unified + 608 .thumb + 609 .thumb_func + 611 MX_I2C2_Init: + 612 .LFB134: + 295:Core/Src/main.c **** + 613 .loc 1 295 1 view -0 + 614 .cfi_startproc + 615 @ args = 0, pretend = 0, frame = 0 + 616 @ frame_needed = 0, uses_anonymous_args = 0 + 617 0000 08B5 push {r3, lr} + 618 .cfi_def_cfa_offset 8 + 619 .cfi_offset 3, -8 + 620 .cfi_offset 14, -4 + 304:Core/Src/main.c **** hi2c2.Init.Timing = 0x2000090E; + 621 .loc 1 304 3 view .LVU160 + 304:Core/Src/main.c **** hi2c2.Init.Timing = 0x2000090E; + 622 .loc 1 304 18 is_stmt 0 view .LVU161 + 623 0002 1148 ldr r0, .L48 + 624 0004 114B ldr r3, .L48+4 + 625 0006 0360 str r3, [r0] + 305:Core/Src/main.c **** hi2c2.Init.OwnAddress1 = 0; + 626 .loc 1 305 3 is_stmt 1 view .LVU162 + 305:Core/Src/main.c **** hi2c2.Init.OwnAddress1 = 0; + 627 .loc 1 305 21 is_stmt 0 view .LVU163 + 628 0008 114B ldr r3, .L48+8 + 629 000a 4360 str r3, [r0, #4] + 306:Core/Src/main.c **** hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 630 .loc 1 306 3 is_stmt 1 view .LVU164 + 306:Core/Src/main.c **** hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 631 .loc 1 306 26 is_stmt 0 view .LVU165 + 632 000c 0023 movs r3, #0 + 633 000e 8360 str r3, [r0, #8] + 307:Core/Src/main.c **** hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 634 .loc 1 307 3 is_stmt 1 view .LVU166 + 307:Core/Src/main.c **** hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 635 .loc 1 307 29 is_stmt 0 view .LVU167 + 636 0010 0122 movs r2, #1 + 637 0012 C260 str r2, [r0, #12] + 308:Core/Src/main.c **** hi2c2.Init.OwnAddress2 = 0; + 638 .loc 1 308 3 is_stmt 1 view .LVU168 + 308:Core/Src/main.c **** hi2c2.Init.OwnAddress2 = 0; + 639 .loc 1 308 30 is_stmt 0 view .LVU169 + 640 0014 0361 str r3, [r0, #16] + 309:Core/Src/main.c **** hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 641 .loc 1 309 3 is_stmt 1 view .LVU170 + 309:Core/Src/main.c **** hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 642 .loc 1 309 26 is_stmt 0 view .LVU171 + 643 0016 4361 str r3, [r0, #20] + 310:Core/Src/main.c **** hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 644 .loc 1 310 3 is_stmt 1 view .LVU172 + 310:Core/Src/main.c **** hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 645 .loc 1 310 31 is_stmt 0 view .LVU173 + 646 0018 8361 str r3, [r0, #24] + 311:Core/Src/main.c **** hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 647 .loc 1 311 3 is_stmt 1 view .LVU174 + ARM GAS /tmp/cctSQMH6.s page 24 + + + 311:Core/Src/main.c **** hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 648 .loc 1 311 30 is_stmt 0 view .LVU175 + 649 001a C361 str r3, [r0, #28] + 312:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c2) != HAL_OK) + 650 .loc 1 312 3 is_stmt 1 view .LVU176 + 312:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c2) != HAL_OK) + 651 .loc 1 312 28 is_stmt 0 view .LVU177 + 652 001c 0362 str r3, [r0, #32] + 313:Core/Src/main.c **** { + 653 .loc 1 313 3 is_stmt 1 view .LVU178 + 313:Core/Src/main.c **** { + 654 .loc 1 313 7 is_stmt 0 view .LVU179 + 655 001e FFF7FEFF bl HAL_I2C_Init + 656 .LVL32: + 313:Core/Src/main.c **** { + 657 .loc 1 313 6 view .LVU180 + 658 0022 50B9 cbnz r0, .L45 + 320:Core/Src/main.c **** { + 659 .loc 1 320 3 is_stmt 1 view .LVU181 + 320:Core/Src/main.c **** { + 660 .loc 1 320 7 is_stmt 0 view .LVU182 + 661 0024 0021 movs r1, #0 + 662 0026 0848 ldr r0, .L48 + 663 0028 FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter + 664 .LVL33: + 320:Core/Src/main.c **** { + 665 .loc 1 320 6 view .LVU183 + 666 002c 38B9 cbnz r0, .L46 + 327:Core/Src/main.c **** { + 667 .loc 1 327 3 is_stmt 1 view .LVU184 + 327:Core/Src/main.c **** { + 668 .loc 1 327 7 is_stmt 0 view .LVU185 + 669 002e 0021 movs r1, #0 + 670 0030 0548 ldr r0, .L48 + 671 0032 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter + 672 .LVL34: + 327:Core/Src/main.c **** { + 673 .loc 1 327 6 view .LVU186 + 674 0036 20B9 cbnz r0, .L47 + 335:Core/Src/main.c **** + 675 .loc 1 335 1 view .LVU187 + 676 0038 08BD pop {r3, pc} + 677 .L45: + 315:Core/Src/main.c **** } + 678 .loc 1 315 5 is_stmt 1 view .LVU188 + 679 003a FFF7FEFF bl Error_Handler + 680 .LVL35: + 681 .L46: + 322:Core/Src/main.c **** } + 682 .loc 1 322 5 view .LVU189 + 683 003e FFF7FEFF bl Error_Handler + 684 .LVL36: + 685 .L47: + 329:Core/Src/main.c **** } + 686 .loc 1 329 5 view .LVU190 + 687 0042 FFF7FEFF bl Error_Handler + 688 .LVL37: + ARM GAS /tmp/cctSQMH6.s page 25 + + + 689 .L49: + 690 0046 00BF .align 2 + 691 .L48: + 692 0048 00000000 .word hi2c2 + 693 004c 00580040 .word 1073764352 + 694 0050 0E090020 .word 536873230 + 695 .cfi_endproc + 696 .LFE134: + 698 .section .text.MX_SPI1_Init,"ax",%progbits + 699 .align 1 + 700 .syntax unified + 701 .thumb + 702 .thumb_func + 704 MX_SPI1_Init: + 705 .LFB135: + 343:Core/Src/main.c **** + 706 .loc 1 343 1 view -0 + 707 .cfi_startproc + 708 @ args = 0, pretend = 0, frame = 0 + 709 @ frame_needed = 0, uses_anonymous_args = 0 + 710 0000 08B5 push {r3, lr} + 711 .cfi_def_cfa_offset 8 + 712 .cfi_offset 3, -8 + 713 .cfi_offset 14, -4 + 353:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; + 714 .loc 1 353 3 view .LVU192 + 353:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; + 715 .loc 1 353 18 is_stmt 0 view .LVU193 + 716 0002 1048 ldr r0, .L54 + 717 0004 104B ldr r3, .L54+4 + 718 0006 0360 str r3, [r0] + 354:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 719 .loc 1 354 3 is_stmt 1 view .LVU194 + 354:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 720 .loc 1 354 19 is_stmt 0 view .LVU195 + 721 0008 4FF48273 mov r3, #260 + 722 000c 4360 str r3, [r0, #4] + 355:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 723 .loc 1 355 3 is_stmt 1 view .LVU196 + 355:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 724 .loc 1 355 24 is_stmt 0 view .LVU197 + 725 000e 0023 movs r3, #0 + 726 0010 8360 str r3, [r0, #8] + 356:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 727 .loc 1 356 3 is_stmt 1 view .LVU198 + 356:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 728 .loc 1 356 23 is_stmt 0 view .LVU199 + 729 0012 4FF4E062 mov r2, #1792 + 730 0016 C260 str r2, [r0, #12] + 357:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 731 .loc 1 357 3 is_stmt 1 view .LVU200 + 357:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 732 .loc 1 357 26 is_stmt 0 view .LVU201 + 733 0018 0361 str r3, [r0, #16] + 358:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_SOFT; + 734 .loc 1 358 3 is_stmt 1 view .LVU202 + 358:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_SOFT; + ARM GAS /tmp/cctSQMH6.s page 26 + + + 735 .loc 1 358 23 is_stmt 0 view .LVU203 + 736 001a 4361 str r3, [r0, #20] + 359:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; + 737 .loc 1 359 3 is_stmt 1 view .LVU204 + 359:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; + 738 .loc 1 359 18 is_stmt 0 view .LVU205 + 739 001c 4FF40072 mov r2, #512 + 740 0020 8261 str r2, [r0, #24] + 360:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 741 .loc 1 360 3 is_stmt 1 view .LVU206 + 360:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 742 .loc 1 360 32 is_stmt 0 view .LVU207 + 743 0022 2022 movs r2, #32 + 744 0024 C261 str r2, [r0, #28] + 361:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 745 .loc 1 361 3 is_stmt 1 view .LVU208 + 361:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 746 .loc 1 361 23 is_stmt 0 view .LVU209 + 747 0026 0362 str r3, [r0, #32] + 362:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 748 .loc 1 362 3 is_stmt 1 view .LVU210 + 362:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 749 .loc 1 362 21 is_stmt 0 view .LVU211 + 750 0028 4362 str r3, [r0, #36] + 363:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 7; + 751 .loc 1 363 3 is_stmt 1 view .LVU212 + 363:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 7; + 752 .loc 1 363 29 is_stmt 0 view .LVU213 + 753 002a 8362 str r3, [r0, #40] + 364:Core/Src/main.c **** hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + 754 .loc 1 364 3 is_stmt 1 view .LVU214 + 364:Core/Src/main.c **** hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + 755 .loc 1 364 28 is_stmt 0 view .LVU215 + 756 002c 0722 movs r2, #7 + 757 002e C262 str r2, [r0, #44] + 365:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + 758 .loc 1 365 3 is_stmt 1 view .LVU216 + 365:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + 759 .loc 1 365 24 is_stmt 0 view .LVU217 + 760 0030 0363 str r3, [r0, #48] + 366:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) + 761 .loc 1 366 3 is_stmt 1 view .LVU218 + 366:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) + 762 .loc 1 366 23 is_stmt 0 view .LVU219 + 763 0032 0823 movs r3, #8 + 764 0034 4363 str r3, [r0, #52] + 367:Core/Src/main.c **** { + 765 .loc 1 367 3 is_stmt 1 view .LVU220 + 367:Core/Src/main.c **** { + 766 .loc 1 367 7 is_stmt 0 view .LVU221 + 767 0036 FFF7FEFF bl HAL_SPI_Init + 768 .LVL38: + 367:Core/Src/main.c **** { + 769 .loc 1 367 6 view .LVU222 + 770 003a 00B9 cbnz r0, .L53 + 375:Core/Src/main.c **** + 771 .loc 1 375 1 view .LVU223 + ARM GAS /tmp/cctSQMH6.s page 27 + + + 772 003c 08BD pop {r3, pc} + 773 .L53: + 369:Core/Src/main.c **** } + 774 .loc 1 369 5 is_stmt 1 view .LVU224 + 775 003e FFF7FEFF bl Error_Handler + 776 .LVL39: + 777 .L55: + 778 0042 00BF .align 2 + 779 .L54: + 780 0044 00000000 .word hspi1 + 781 0048 00300140 .word 1073819648 + 782 .cfi_endproc + 783 .LFE135: + 785 .section .text.SystemClock_Config,"ax",%progbits + 786 .align 1 + 787 .global SystemClock_Config + 788 .syntax unified + 789 .thumb + 790 .thumb_func + 792 SystemClock_Config: + 793 .LFB131: + 164:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 794 .loc 1 164 1 view -0 + 795 .cfi_startproc + 796 @ args = 0, pretend = 0, frame = 112 + 797 @ frame_needed = 0, uses_anonymous_args = 0 + 798 0000 00B5 push {lr} + 799 .cfi_def_cfa_offset 4 + 800 .cfi_offset 14, -4 + 801 0002 9DB0 sub sp, sp, #116 + 802 .cfi_def_cfa_offset 120 + 165:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 803 .loc 1 165 3 view .LVU226 + 165:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 804 .loc 1 165 22 is_stmt 0 view .LVU227 + 805 0004 2822 movs r2, #40 + 806 0006 0021 movs r1, #0 + 807 0008 12A8 add r0, sp, #72 + 808 000a FFF7FEFF bl memset + 809 .LVL40: + 166:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 810 .loc 1 166 3 is_stmt 1 view .LVU228 + 166:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 811 .loc 1 166 22 is_stmt 0 view .LVU229 + 812 000e 0021 movs r1, #0 + 813 0010 0D91 str r1, [sp, #52] + 814 0012 0E91 str r1, [sp, #56] + 815 0014 0F91 str r1, [sp, #60] + 816 0016 1091 str r1, [sp, #64] + 817 0018 1191 str r1, [sp, #68] + 167:Core/Src/main.c **** + 818 .loc 1 167 3 is_stmt 1 view .LVU230 + 167:Core/Src/main.c **** + 819 .loc 1 167 28 is_stmt 0 view .LVU231 + 820 001a 3422 movs r2, #52 + 821 001c 6846 mov r0, sp + 822 001e FFF7FEFF bl memset + ARM GAS /tmp/cctSQMH6.s page 28 + + + 823 .LVL41: + 172:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 824 .loc 1 172 3 is_stmt 1 view .LVU232 + 172:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 825 .loc 1 172 36 is_stmt 0 view .LVU233 + 826 0022 0323 movs r3, #3 + 827 0024 1293 str r3, [sp, #72] + 173:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 828 .loc 1 173 3 is_stmt 1 view .LVU234 + 173:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 829 .loc 1 173 30 is_stmt 0 view .LVU235 + 830 0026 4FF48033 mov r3, #65536 + 831 002a 1393 str r3, [sp, #76] + 174:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 832 .loc 1 174 3 is_stmt 1 view .LVU236 + 174:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 833 .loc 1 174 30 is_stmt 0 view .LVU237 + 834 002c 0123 movs r3, #1 + 835 002e 1693 str r3, [sp, #88] + 175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 836 .loc 1 175 3 is_stmt 1 view .LVU238 + 175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 837 .loc 1 175 41 is_stmt 0 view .LVU239 + 838 0030 1023 movs r3, #16 + 839 0032 1793 str r3, [sp, #92] + 176:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 840 .loc 1 176 3 is_stmt 1 view .LVU240 + 177:Core/Src/main.c **** { + 841 .loc 1 177 3 view .LVU241 + 177:Core/Src/main.c **** { + 842 .loc 1 177 7 is_stmt 0 view .LVU242 + 843 0034 12A8 add r0, sp, #72 + 844 0036 FFF7FEFF bl HAL_RCC_OscConfig + 845 .LVL42: + 177:Core/Src/main.c **** { + 846 .loc 1 177 6 view .LVU243 + 847 003a B8B9 cbnz r0, .L61 + 184:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 848 .loc 1 184 3 is_stmt 1 view .LVU244 + 184:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 849 .loc 1 184 31 is_stmt 0 view .LVU245 + 850 003c 0F23 movs r3, #15 + 851 003e 0D93 str r3, [sp, #52] + 186:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 852 .loc 1 186 3 is_stmt 1 view .LVU246 + 186:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 853 .loc 1 186 34 is_stmt 0 view .LVU247 + 854 0040 0123 movs r3, #1 + 855 0042 0E93 str r3, [sp, #56] + 187:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 856 .loc 1 187 3 is_stmt 1 view .LVU248 + 187:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 857 .loc 1 187 35 is_stmt 0 view .LVU249 + 858 0044 0021 movs r1, #0 + 859 0046 0F91 str r1, [sp, #60] + 188:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 860 .loc 1 188 3 is_stmt 1 view .LVU250 + ARM GAS /tmp/cctSQMH6.s page 29 + + + 188:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 861 .loc 1 188 36 is_stmt 0 view .LVU251 + 862 0048 1091 str r1, [sp, #64] + 189:Core/Src/main.c **** + 863 .loc 1 189 3 is_stmt 1 view .LVU252 + 189:Core/Src/main.c **** + 864 .loc 1 189 36 is_stmt 0 view .LVU253 + 865 004a 1191 str r1, [sp, #68] + 191:Core/Src/main.c **** { + 866 .loc 1 191 3 is_stmt 1 view .LVU254 + 191:Core/Src/main.c **** { + 867 .loc 1 191 7 is_stmt 0 view .LVU255 + 868 004c 0DA8 add r0, sp, #52 + 869 004e FFF7FEFF bl HAL_RCC_ClockConfig + 870 .LVL43: + 191:Core/Src/main.c **** { + 871 .loc 1 191 6 view .LVU256 + 872 0052 68B9 cbnz r0, .L62 + 195:Core/Src/main.c **** PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; + 873 .loc 1 195 3 is_stmt 1 view .LVU257 + 195:Core/Src/main.c **** PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_HSI; + 874 .loc 1 195 38 is_stmt 0 view .LVU258 + 875 0054 6023 movs r3, #96 + 876 0056 0093 str r3, [sp] + 196:Core/Src/main.c **** PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_HSI; + 877 .loc 1 196 3 is_stmt 1 view .LVU259 + 196:Core/Src/main.c **** PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_HSI; + 878 .loc 1 196 36 is_stmt 0 view .LVU260 + 879 0058 0023 movs r3, #0 + 880 005a 0793 str r3, [sp, #28] + 197:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 881 .loc 1 197 3 is_stmt 1 view .LVU261 + 197:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 882 .loc 1 197 36 is_stmt 0 view .LVU262 + 883 005c 0893 str r3, [sp, #32] + 198:Core/Src/main.c **** { + 884 .loc 1 198 3 is_stmt 1 view .LVU263 + 198:Core/Src/main.c **** { + 885 .loc 1 198 7 is_stmt 0 view .LVU264 + 886 005e 6846 mov r0, sp + 887 0060 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig + 888 .LVL44: + 198:Core/Src/main.c **** { + 889 .loc 1 198 6 view .LVU265 + 890 0064 30B9 cbnz r0, .L63 + 202:Core/Src/main.c **** + 891 .loc 1 202 1 view .LVU266 + 892 0066 1DB0 add sp, sp, #116 + 893 .cfi_remember_state + 894 .cfi_def_cfa_offset 4 + 895 @ sp needed + 896 0068 5DF804FB ldr pc, [sp], #4 + 897 .L61: + 898 .cfi_restore_state + 179:Core/Src/main.c **** } + 899 .loc 1 179 5 is_stmt 1 view .LVU267 + 900 006c FFF7FEFF bl Error_Handler + ARM GAS /tmp/cctSQMH6.s page 30 + + + 901 .LVL45: + 902 .L62: + 193:Core/Src/main.c **** } + 903 .loc 1 193 5 view .LVU268 + 904 0070 FFF7FEFF bl Error_Handler + 905 .LVL46: + 906 .L63: + 200:Core/Src/main.c **** } + 907 .loc 1 200 5 view .LVU269 + 908 0074 FFF7FEFF bl Error_Handler + 909 .LVL47: + 910 .cfi_endproc + 911 .LFE131: + 913 .section .text.main,"ax",%progbits + 914 .align 1 + 915 .global main + 916 .syntax unified + 917 .thumb + 918 .thumb_func + 920 main: + 921 .LFB130: + 89:Core/Src/main.c **** /* USER CODE BEGIN 1 */ + 922 .loc 1 89 1 view -0 + 923 .cfi_startproc + 924 @ args = 0, pretend = 0, frame = 24 + 925 @ frame_needed = 0, uses_anonymous_args = 0 + 926 0000 10B5 push {r4, lr} + 927 .cfi_def_cfa_offset 8 + 928 .cfi_offset 4, -8 + 929 .cfi_offset 14, -4 + 930 0002 86B0 sub sp, sp, #24 + 931 .cfi_def_cfa_offset 32 + 97:Core/Src/main.c **** + 932 .loc 1 97 3 view .LVU271 + 933 0004 FFF7FEFF bl HAL_Init + 934 .LVL48: + 104:Core/Src/main.c **** + 935 .loc 1 104 3 view .LVU272 + 936 0008 FFF7FEFF bl SystemClock_Config + 937 .LVL49: + 111:Core/Src/main.c **** MX_CAN_Init(); + 938 .loc 1 111 3 view .LVU273 + 939 000c FFF7FEFF bl MX_GPIO_Init + 940 .LVL50: + 112:Core/Src/main.c **** MX_I2C1_Init(); + 941 .loc 1 112 3 view .LVU274 + 942 0010 FFF7FEFF bl MX_CAN_Init + 943 .LVL51: + 113:Core/Src/main.c **** MX_I2C2_Init(); + 944 .loc 1 113 3 view .LVU275 + 945 0014 FFF7FEFF bl MX_I2C1_Init + 946 .LVL52: + 114:Core/Src/main.c **** MX_SPI1_Init(); + 947 .loc 1 114 3 view .LVU276 + 948 0018 FFF7FEFF bl MX_I2C2_Init + 949 .LVL53: + 115:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + ARM GAS /tmp/cctSQMH6.s page 31 + + + 950 .loc 1 115 3 view .LVU277 + 951 001c FFF7FEFF bl MX_SPI1_Init + 952 .LVL54: + 118:Core/Src/main.c **** if (sensor_init(i) != HAL_OK) { + 953 .loc 1 118 3 view .LVU278 + 954 .LBB9: + 118:Core/Src/main.c **** if (sensor_init(i) != HAL_OK) { + 955 .loc 1 118 8 view .LVU279 + 118:Core/Src/main.c **** if (sensor_init(i) != HAL_OK) { + 956 .loc 1 118 12 is_stmt 0 view .LVU280 + 957 0020 0024 movs r4, #0 + 118:Core/Src/main.c **** if (sensor_init(i) != HAL_OK) { + 958 .loc 1 118 3 view .LVU281 + 959 0022 00E0 b .L65 + 960 .LVL55: + 961 .L66: + 118:Core/Src/main.c **** if (sensor_init(i) != HAL_OK) { + 962 .loc 1 118 35 is_stmt 1 discriminator 2 view .LVU282 + 963 0024 0134 adds r4, r4, #1 + 964 .LVL56: + 965 .L65: + 118:Core/Src/main.c **** if (sensor_init(i) != HAL_OK) { + 966 .loc 1 118 21 discriminator 1 view .LVU283 + 967 0026 0B2C cmp r4, #11 + 968 0028 09DC bgt .L73 + 119:Core/Src/main.c **** last_error = HAL_GetTick(); + 969 .loc 1 119 6 view .LVU284 + 119:Core/Src/main.c **** last_error = HAL_GetTick(); + 970 .loc 1 119 10 is_stmt 0 view .LVU285 + 971 002a 2046 mov r0, r4 + 972 002c FFF7FEFF bl sensor_init + 973 .LVL57: + 119:Core/Src/main.c **** last_error = HAL_GetTick(); + 974 .loc 1 119 9 view .LVU286 + 975 0030 0028 cmp r0, #0 + 976 0032 F7D0 beq .L66 + 120:Core/Src/main.c **** } + 977 .loc 1 120 8 is_stmt 1 view .LVU287 + 120:Core/Src/main.c **** } + 978 .loc 1 120 21 is_stmt 0 view .LVU288 + 979 0034 FFF7FEFF bl HAL_GetTick + 980 .LVL58: + 120:Core/Src/main.c **** } + 981 .loc 1 120 19 view .LVU289 + 982 0038 134B ldr r3, .L74 + 983 003a 1860 str r0, [r3] + 984 003c F2E7 b .L66 + 985 .L73: + 986 .LBE9: + 124:Core/Src/main.c **** ams_can_init(&hcan, &hcan); + 987 .loc 1 124 4 is_stmt 1 view .LVU290 + 988 003e 1348 ldr r0, .L74+4 + 989 0040 FFF7FEFF bl AMS_Init + 990 .LVL59: + 125:Core/Src/main.c **** //amsConfigAuxMeasurement(9); + 991 .loc 1 125 4 view .LVU291 + 992 0044 1248 ldr r0, .L74+8 + ARM GAS /tmp/cctSQMH6.s page 32 + + + 993 0046 0146 mov r1, r0 + 994 0048 FFF7FEFF bl ams_can_init + 995 .LVL60: + 135:Core/Src/main.c **** uint16_t temperatures[N_SENSORS]; + 996 .loc 1 135 4 view .LVU292 + 997 004c 4521 movs r1, #69 + 998 004e 0120 movs r0, #1 + 999 0050 FFF7FEFF bl writeeeprom + 1000 .LVL61: + 136:Core/Src/main.c **** AMS_Loop(); + 1001 .loc 1 136 4 view .LVU293 + 137:Core/Src/main.c **** while (1){ + 1002 .loc 1 137 4 view .LVU294 + 1003 0054 FFF7FEFF bl AMS_Loop + 1004 .LVL62: + 1005 .L71: + 138:Core/Src/main.c **** if(BMS_IN_TEST_MODE == 1 ){ ////&& PENDING_MESSAGE_HANDLE == 1 + 1006 .loc 1 138 4 view .LVU295 + 139:Core/Src/main.c **** testLoop(&canTestData); + 1007 .loc 1 139 5 view .LVU296 + 140:Core/Src/main.c **** /* USER CODE END WHILE */ + 1008 .loc 1 140 7 view .LVU297 + 1009 0058 0E48 ldr r0, .L74+12 + 1010 005a FFF7FEFF bl testLoop + 1011 .LVL63: + 144:Core/Src/main.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 1012 .loc 1 144 4 view .LVU298 + 1013 .LBB10: + 144:Core/Src/main.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 1014 .loc 1 144 9 view .LVU299 + 144:Core/Src/main.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 1015 .loc 1 144 13 is_stmt 0 view .LVU300 + 1016 005e 0024 movs r4, #0 + 144:Core/Src/main.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 1017 .loc 1 144 4 view .LVU301 + 1018 0060 00E0 b .L68 + 1019 .LVL64: + 1020 .L69: + 144:Core/Src/main.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 1021 .loc 1 144 36 is_stmt 1 discriminator 2 view .LVU302 + 1022 0062 0134 adds r4, r4, #1 + 1023 .LVL65: + 1024 .L68: + 144:Core/Src/main.c **** if (sensor_read(i, &temperatures[i]) != HAL_OK) { + 1025 .loc 1 144 22 discriminator 1 view .LVU303 + 1026 0064 0B2C cmp r4, #11 + 1027 0066 F7DC bgt .L71 + 145:Core/Src/main.c **** sensor_init(i); + 1028 .loc 1 145 10 view .LVU304 + 145:Core/Src/main.c **** sensor_init(i); + 1029 .loc 1 145 14 is_stmt 0 view .LVU305 + 1030 0068 0DEB4401 add r1, sp, r4, lsl #1 + 1031 006c 2046 mov r0, r4 + 1032 006e FFF7FEFF bl sensor_read + 1033 .LVL66: + 145:Core/Src/main.c **** sensor_init(i); + 1034 .loc 1 145 13 view .LVU306 + ARM GAS /tmp/cctSQMH6.s page 33 + + + 1035 0072 0028 cmp r0, #0 + 1036 0074 F5D0 beq .L69 + 146:Core/Src/main.c **** last_error = HAL_GetTick(); + 1037 .loc 1 146 12 is_stmt 1 view .LVU307 + 1038 0076 2046 mov r0, r4 + 1039 0078 FFF7FEFF bl sensor_init + 1040 .LVL67: + 147:Core/Src/main.c **** } + 1041 .loc 1 147 12 view .LVU308 + 147:Core/Src/main.c **** } + 1042 .loc 1 147 25 is_stmt 0 view .LVU309 + 1043 007c FFF7FEFF bl HAL_GetTick + 1044 .LVL68: + 147:Core/Src/main.c **** } + 1045 .loc 1 147 23 view .LVU310 + 1046 0080 014B ldr r3, .L74 + 1047 0082 1860 str r0, [r3] + 1048 0084 EDE7 b .L69 + 1049 .L75: + 1050 0086 00BF .align 2 + 1051 .L74: + 1052 0088 00000000 .word last_error + 1053 008c 00000000 .word hspi1 + 1054 0090 00000000 .word hcan + 1055 0094 00000000 .word canTestData + 1056 .LBE10: + 1057 .cfi_endproc + 1058 .LFE130: + 1060 .section .bss.last_error,"aw",%nobits + 1061 .align 2 + 1064 last_error: + 1065 0000 00000000 .space 4 + 1066 .global hspi1 + 1067 .section .bss.hspi1,"aw",%nobits + 1068 .align 2 + 1071 hspi1: + 1072 0000 00000000 .space 100 + 1072 00000000 + 1072 00000000 + 1072 00000000 + 1072 00000000 + 1073 .global hi2c2 + 1074 .section .bss.hi2c2,"aw",%nobits + 1075 .align 2 + 1078 hi2c2: + 1079 0000 00000000 .space 76 + 1079 00000000 + 1079 00000000 + 1079 00000000 + 1079 00000000 + 1080 .global hi2c1 + 1081 .section .bss.hi2c1,"aw",%nobits + 1082 .align 2 + 1085 hi2c1: + 1086 0000 00000000 .space 76 + 1086 00000000 + 1086 00000000 + ARM GAS /tmp/cctSQMH6.s page 34 + + + 1086 00000000 + 1086 00000000 + 1087 .global hcan + 1088 .section .bss.hcan,"aw",%nobits + 1089 .align 2 + 1092 hcan: + 1093 0000 00000000 .space 40 + 1093 00000000 + 1093 00000000 + 1093 00000000 + 1093 00000000 + 1094 .text + 1095 .Letext0: + 1096 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1097 .file 4 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1098 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1099 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1100 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1101 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" + 1102 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h" + 1103 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 1104 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 1105 .file 12 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 1106 .file 13 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + 1107 .file 14 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 1108 .file 15 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h" + 1109 .file 16 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 1110 .file 17 "Core/Inc/Testbench.h" + 1111 .file 18 "Core/Inc/AMS_CAN.h" + 1112 .file 19 "Core/Inc/AMS_HighLevel.h" + 1113 .file 20 "" + ARM GAS /tmp/cctSQMH6.s page 35 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 main.c + /tmp/cctSQMH6.s:21 .text.MX_GPIO_Init:0000000000000000 $t + /tmp/cctSQMH6.s:26 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init + /tmp/cctSQMH6.s:152 .text.MX_GPIO_Init:0000000000000094 $d + /tmp/cctSQMH6.s:158 .text.sensor_init:0000000000000000 $t + /tmp/cctSQMH6.s:164 .text.sensor_init:0000000000000000 sensor_init + /tmp/cctSQMH6.s:208 .text.sensor_init:0000000000000028 $d + /tmp/cctSQMH6.s:1085 .bss.hi2c1:0000000000000000 hi2c1 + /tmp/cctSQMH6.s:213 .text.sensor_read:0000000000000000 $t + /tmp/cctSQMH6.s:219 .text.sensor_read:0000000000000000 sensor_read + /tmp/cctSQMH6.s:284 .text.sensor_read:0000000000000034 $d + /tmp/cctSQMH6.s:289 .text.readeeprom:0000000000000000 $t + /tmp/cctSQMH6.s:295 .text.readeeprom:0000000000000000 readeeprom + /tmp/cctSQMH6.s:337 .text.readeeprom:0000000000000030 $d + /tmp/cctSQMH6.s:1078 .bss.hi2c2:0000000000000000 hi2c2 + /tmp/cctSQMH6.s:342 .text.writeeeprom:0000000000000000 $t + /tmp/cctSQMH6.s:348 .text.writeeeprom:0000000000000000 writeeeprom + /tmp/cctSQMH6.s:391 .text.writeeeprom:0000000000000030 $d + /tmp/cctSQMH6.s:396 .text.Error_Handler:0000000000000000 $t + /tmp/cctSQMH6.s:402 .text.Error_Handler:0000000000000000 Error_Handler + /tmp/cctSQMH6.s:434 .text.MX_CAN_Init:0000000000000000 $t + /tmp/cctSQMH6.s:439 .text.MX_CAN_Init:0000000000000000 MX_CAN_Init + /tmp/cctSQMH6.s:507 .text.MX_CAN_Init:0000000000000038 $d + /tmp/cctSQMH6.s:1092 .bss.hcan:0000000000000000 hcan + /tmp/cctSQMH6.s:513 .text.MX_I2C1_Init:0000000000000000 $t + /tmp/cctSQMH6.s:518 .text.MX_I2C1_Init:0000000000000000 MX_I2C1_Init + /tmp/cctSQMH6.s:599 .text.MX_I2C1_Init:0000000000000048 $d + /tmp/cctSQMH6.s:606 .text.MX_I2C2_Init:0000000000000000 $t + /tmp/cctSQMH6.s:611 .text.MX_I2C2_Init:0000000000000000 MX_I2C2_Init + /tmp/cctSQMH6.s:692 .text.MX_I2C2_Init:0000000000000048 $d + /tmp/cctSQMH6.s:699 .text.MX_SPI1_Init:0000000000000000 $t + /tmp/cctSQMH6.s:704 .text.MX_SPI1_Init:0000000000000000 MX_SPI1_Init + /tmp/cctSQMH6.s:780 .text.MX_SPI1_Init:0000000000000044 $d + /tmp/cctSQMH6.s:1071 .bss.hspi1:0000000000000000 hspi1 + /tmp/cctSQMH6.s:786 .text.SystemClock_Config:0000000000000000 $t + /tmp/cctSQMH6.s:792 .text.SystemClock_Config:0000000000000000 SystemClock_Config + /tmp/cctSQMH6.s:914 .text.main:0000000000000000 $t + /tmp/cctSQMH6.s:920 .text.main:0000000000000000 main + /tmp/cctSQMH6.s:1052 .text.main:0000000000000088 $d + /tmp/cctSQMH6.s:1064 .bss.last_error:0000000000000000 last_error + /tmp/cctSQMH6.s:1061 .bss.last_error:0000000000000000 $d + /tmp/cctSQMH6.s:1068 .bss.hspi1:0000000000000000 $d + /tmp/cctSQMH6.s:1075 .bss.hi2c2:0000000000000000 $d + /tmp/cctSQMH6.s:1082 .bss.hi2c1:0000000000000000 $d + /tmp/cctSQMH6.s:1089 .bss.hcan:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_GPIO_WritePin +HAL_GPIO_Init +HAL_I2C_Master_Transmit +HAL_I2C_Master_Receive +HAL_I2C_Mem_Read +HAL_I2C_Mem_Write +HAL_Delay +HAL_CAN_Init +HAL_I2C_Init + ARM GAS /tmp/cctSQMH6.s page 36 + + +HAL_I2CEx_ConfigAnalogFilter +HAL_I2CEx_ConfigDigitalFilter +HAL_SPI_Init +memset +HAL_RCC_OscConfig +HAL_RCC_ClockConfig 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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal.lst new file mode 100644 index 0000000..34e8c53 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal.lst @@ -0,0 +1,1527 @@ +ARM GAS /tmp/ccjtZjrH.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c" + 20 .section .text.HAL_MspInit,"ax",%progbits + 21 .align 1 + 22 .weak HAL_MspInit + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_MspInit: + 28 .LFB132: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @file stm32f3xx_hal.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * This is the common part of the HAL initialization + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @verbatim + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ============================================================================== + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ##### How to use this driver ##### + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ============================================================================== + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** [..] + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** The common HAL driver contains a set of generic and common APIs that can be + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** used by the PPP peripheral drivers and the user to start using the HAL. + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** [..] + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** The HAL contains two APIs categories: + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) HAL Initialization and de-initialization functions + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) HAL Control functions + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @endverbatim + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ****************************************************************************** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @attention + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * All rights reserved.

    + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * This software component is licensed by ST under BSD 3-Clause license, + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * the "License"; You may not use this file except in compliance with the + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * License. You may obtain a copy of the License at: + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * opensource.org/licenses/BSD-3-Clause + ARM GAS /tmp/ccjtZjrH.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ****************************************************************************** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Includes ------------------------------------------------------------------*/ + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #include "stm32f3xx_hal.h" + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @addtogroup STM32F3xx_HAL_Driver + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL HAL + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief HAL module driver. + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #ifdef HAL_MODULE_ENABLED + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Private typedef -----------------------------------------------------------*/ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Private define ------------------------------------------------------------*/ + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Private Constants + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief STM32F3xx HAL Driver version number V1.5.6 + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\ + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** |(__STM32F3xx_HAL_VERSION_RC)) + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define IDCODE_DEVID_MASK (0x00000FFFU) + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @} + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Private macro -------------------------------------------------------------*/ + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Exported variables --------------------------------------------------------*/ + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Variables HAL Exported Variables + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __IO uint32_t uwTick; + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @} + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Private function prototypes -----------------------------------------------*/ + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Exported functions ---------------------------------------------------------*/ + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Functions HAL Exported Functions + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + ARM GAS /tmp/ccjtZjrH.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Initialization and de-initialization functions + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @verbatim + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** =============================================================================== + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ##### Initialization and de-initialization functions ##### + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** =============================================================================== + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** [..] This section provides functions allowing to: + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Initializes the Flash interface, the NVIC allocation and initial clock + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** configuration. It initializes the systick also when timeout is needed + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** and the backup domain when enabled. + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) de-Initializes common part of the HAL. + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Configure The time base source to have 1ms time base with a dedicated + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** Tick interrupt priority. + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (++) SysTick timer is used by default as source of time base, but user + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** can eventually implement his proper time base source (a general purpose + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** timer for example or other time source), keeping in mind that Time base + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** handled in milliseconds basis. + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (++) Time base configuration function (HAL_InitTick ()) is called automatically + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** at the beginning of the program after reset by HAL_Init() or at any time + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** when clock is configured, by HAL_RCC_ClockConfig(). + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (++) Source of time base is configured to generate interrupts at regular + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** time intervals. Care must be taken if HAL_Delay() is called from a + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** peripheral ISR process, the Tick interrupt line must have higher priority + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (numerically lower) than the peripheral interrupt. Otherwise the caller + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ISR process will be blocked. + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (++) functions affecting time base configurations are declared as __Weak + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** to make override possible in case of other implementations in user file. + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @endverbatim + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function configures the Flash prefetch, + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Configures time base source, NVIC and Low level hardware + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is called at the beginning of program after reset and before + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * the clock configuration + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note The Systick configuration is based on HSI clock, as HSI is the clock + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * used after a system Reset and the NVIC configuration is set to Priority group 4 + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note The time base configuration is based on MSI clock when exting from Reset. + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Once done, time base tick start incrementing. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * In the default implementation,Systick is used as source of time base. + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The tick variable is incremented each 1ms in its ISR. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval HAL status + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_StatusTypeDef HAL_Init(void) + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Configure Flash prefetch */ + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #if (PREFETCH_ENABLE != 0U) + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #endif /* PREFETCH_ENABLE */ + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + ARM GAS /tmp/ccjtZjrH.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Set Interrupt Group Priority */ + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_InitTick(TICK_INT_PRIORITY); + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Init the low level hardware */ + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_MspInit(); + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Return function status */ + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_OK; + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function de-Initializes common part of the HAL and stops the systick. + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is optional. + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval HAL status + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_StatusTypeDef HAL_DeInit(void) + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Reset of all peripherals */ + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB1_FORCE_RESET(); + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB1_RELEASE_RESET(); + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB2_FORCE_RESET(); + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_AHB_FORCE_RESET(); + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_AHB_RELEASE_RESET(); + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* De-Init the low level hardware */ + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_MspDeInit(); + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Return function status */ + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_OK; + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Initialize the MSP. + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_MspInit(void) + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 29 .loc 1 187 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* NOTE : This function should not be modified, when the callback is needed, + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** the HAL_MspInit could be implemented in the user file + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 34 .loc 1 191 1 view .LVU1 + 35 0000 7047 bx lr + 36 .cfi_endproc + 37 .LFE132: + 39 .section .text.HAL_MspDeInit,"ax",%progbits + ARM GAS /tmp/ccjtZjrH.s page 5 + + + 40 .align 1 + 41 .weak HAL_MspDeInit + 42 .syntax unified + 43 .thumb + 44 .thumb_func + 46 HAL_MspDeInit: + 47 .LFB133: + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief DeInitialize the MSP. + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_MspDeInit(void) + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 48 .loc 1 198 1 view -0 + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* NOTE : This function should not be modified, when the callback is needed, + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** the HAL_MspDeInit could be implemented in the user file + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 53 .loc 1 202 1 view .LVU3 + 54 0000 7047 bx lr + 55 .cfi_endproc + 56 .LFE133: + 58 .section .text.HAL_DeInit,"ax",%progbits + 59 .align 1 + 60 .global HAL_DeInit + 61 .syntax unified + 62 .thumb + 63 .thumb_func + 65 HAL_DeInit: + 66 .LFB131: + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Reset of all peripherals */ + 67 .loc 1 164 1 view -0 + 68 .cfi_startproc + 69 @ args = 0, pretend = 0, frame = 0 + 70 @ frame_needed = 0, uses_anonymous_args = 0 + 71 0000 10B5 push {r4, lr} + 72 .cfi_def_cfa_offset 8 + 73 .cfi_offset 4, -8 + 74 .cfi_offset 14, -4 + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB1_RELEASE_RESET(); + 75 .loc 1 166 3 view .LVU5 + 76 0002 074B ldr r3, .L5 + 77 0004 4FF0FF32 mov r2, #-1 + 78 0008 1A61 str r2, [r3, #16] + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 79 .loc 1 167 3 view .LVU6 + 80 000a 0024 movs r4, #0 + 81 000c 1C61 str r4, [r3, #16] + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + 82 .loc 1 169 3 view .LVU7 + 83 000e DA60 str r2, [r3, #12] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + ARM GAS /tmp/ccjtZjrH.s page 6 + + + 84 .loc 1 170 3 view .LVU8 + 85 0010 DC60 str r4, [r3, #12] + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_AHB_RELEASE_RESET(); + 86 .loc 1 172 3 view .LVU9 + 87 0012 9A62 str r2, [r3, #40] + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 88 .loc 1 173 3 view .LVU10 + 89 0014 9C62 str r4, [r3, #40] + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 90 .loc 1 176 3 view .LVU11 + 91 0016 FFF7FEFF bl HAL_MspDeInit + 92 .LVL0: + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 93 .loc 1 179 3 view .LVU12 + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 94 .loc 1 180 1 is_stmt 0 view .LVU13 + 95 001a 2046 mov r0, r4 + 96 001c 10BD pop {r4, pc} + 97 .L6: + 98 001e 00BF .align 2 + 99 .L5: + 100 0020 00100240 .word 1073876992 + 101 .cfi_endproc + 102 .LFE131: + 104 .section .text.HAL_InitTick,"ax",%progbits + 105 .align 1 + 106 .weak HAL_InitTick + 107 .syntax unified + 108 .thumb + 109 .thumb_func + 111 HAL_InitTick: + 112 .LVL1: + 113 .LFB134: + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function configures the source of the time base. + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The time source is configured to have 1ms time base with a dedicated + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Tick interrupt priority. + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is called automatically at the beginning of program after + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig() + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * It is used to generate interrupts at regular time intervals. + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The SysTick interrupt must have higher priority (numerically lower) + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The function is declared as __Weak to be overwritten in case of other + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementation in user file. + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @param TickPriority Tick interrupt priority. + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval HAL status + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 114 .loc 1 221 1 is_stmt 1 view -0 + 115 .cfi_startproc + 116 @ args = 0, pretend = 0, frame = 0 + 117 @ frame_needed = 0, uses_anonymous_args = 0 + 118 .loc 1 221 1 is_stmt 0 view .LVU15 + ARM GAS /tmp/ccjtZjrH.s page 7 + + + 119 0000 10B5 push {r4, lr} + 120 .cfi_def_cfa_offset 8 + 121 .cfi_offset 4, -8 + 122 .cfi_offset 14, -4 + 123 0002 0446 mov r4, r0 + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Configure the SysTick to have interrupt in 1ms time basis*/ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 124 .loc 1 223 3 is_stmt 1 view .LVU16 + 125 .loc 1 223 51 is_stmt 0 view .LVU17 + 126 0004 0E4B ldr r3, .L13 + 127 0006 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 128 0008 4FF47A73 mov r3, #1000 + 129 000c B3FBF2F3 udiv r3, r3, r2 + 130 .loc 1 223 7 view .LVU18 + 131 0010 0C4A ldr r2, .L13+4 + 132 0012 1068 ldr r0, [r2] + 133 .LVL2: + 134 .loc 1 223 7 view .LVU19 + 135 0014 B0FBF3F0 udiv r0, r0, r3 + 136 0018 FFF7FEFF bl HAL_SYSTICK_Config + 137 .LVL3: + 138 .loc 1 223 6 view .LVU20 + 139 001c 68B9 cbnz r0, .L9 + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_ERROR; + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Configure the SysTick IRQ priority */ + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 140 .loc 1 229 3 is_stmt 1 view .LVU21 + 141 .loc 1 229 6 is_stmt 0 view .LVU22 + 142 001e 0F2C cmp r4, #15 + 143 0020 01D9 bls .L12 + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTickPrio = TickPriority; + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** else + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_ERROR; + 144 .loc 1 236 12 view .LVU23 + 145 0022 0120 movs r0, #1 + 146 0024 0AE0 b .L8 + 147 .L12: + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTickPrio = TickPriority; + 148 .loc 1 231 5 is_stmt 1 view .LVU24 + 149 0026 0022 movs r2, #0 + 150 0028 2146 mov r1, r4 + 151 002a 4FF0FF30 mov r0, #-1 + 152 002e FFF7FEFF bl HAL_NVIC_SetPriority + 153 .LVL4: + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 154 .loc 1 232 5 view .LVU25 + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 155 .loc 1 232 16 is_stmt 0 view .LVU26 + 156 0032 054B ldr r3, .L13+8 + 157 0034 1C60 str r4, [r3] + ARM GAS /tmp/ccjtZjrH.s page 8 + + + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Return function status */ + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_OK; + 158 .loc 1 239 3 is_stmt 1 view .LVU27 + 159 .loc 1 239 10 is_stmt 0 view .LVU28 + 160 0036 0020 movs r0, #0 + 161 0038 00E0 b .L8 + 162 .L9: + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 163 .loc 1 225 12 view .LVU29 + 164 003a 0120 movs r0, #1 + 165 .L8: + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 166 .loc 1 240 1 view .LVU30 + 167 003c 10BD pop {r4, pc} + 168 .LVL5: + 169 .L14: + 170 .loc 1 240 1 view .LVU31 + 171 003e 00BF .align 2 + 172 .L13: + 173 0040 00000000 .word uwTickFreq + 174 0044 00000000 .word SystemCoreClock + 175 0048 00000000 .word uwTickPrio + 176 .cfi_endproc + 177 .LFE134: + 179 .section .text.HAL_Init,"ax",%progbits + 180 .align 1 + 181 .global HAL_Init + 182 .syntax unified + 183 .thumb + 184 .thumb_func + 186 HAL_Init: + 187 .LFB130: + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Configure Flash prefetch */ + 188 .loc 1 139 1 is_stmt 1 view -0 + 189 .cfi_startproc + 190 @ args = 0, pretend = 0, frame = 0 + 191 @ frame_needed = 0, uses_anonymous_args = 0 + 192 0000 08B5 push {r3, lr} + 193 .cfi_def_cfa_offset 8 + 194 .cfi_offset 3, -8 + 195 .cfi_offset 14, -4 + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #endif /* PREFETCH_ENABLE */ + 196 .loc 1 142 3 view .LVU33 + 197 0002 074A ldr r2, .L17 + 198 0004 1368 ldr r3, [r2] + 199 0006 43F01003 orr r3, r3, #16 + 200 000a 1360 str r3, [r2] + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 201 .loc 1 146 3 view .LVU34 + 202 000c 0320 movs r0, #3 + 203 000e FFF7FEFF bl HAL_NVIC_SetPriorityGrouping + 204 .LVL6: + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 205 .loc 1 149 3 view .LVU35 + 206 0012 0F20 movs r0, #15 + 207 0014 FFF7FEFF bl HAL_InitTick + ARM GAS /tmp/ccjtZjrH.s page 9 + + + 208 .LVL7: + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 209 .loc 1 152 3 view .LVU36 + 210 0018 FFF7FEFF bl HAL_MspInit + 211 .LVL8: + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 212 .loc 1 155 3 view .LVU37 + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 213 .loc 1 156 1 is_stmt 0 view .LVU38 + 214 001c 0020 movs r0, #0 + 215 001e 08BD pop {r3, pc} + 216 .L18: + 217 .align 2 + 218 .L17: + 219 0020 00200240 .word 1073881088 + 220 .cfi_endproc + 221 .LFE130: + 223 .section .text.HAL_IncTick,"ax",%progbits + 224 .align 1 + 225 .weak HAL_IncTick + 226 .syntax unified + 227 .thumb + 228 .thumb_func + 230 HAL_IncTick: + 231 .LFB135: + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @} + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief HAL Control functions + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @verbatim + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** =============================================================================== + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ##### HAL Control functions ##### + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** =============================================================================== + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** [..] This section provides functions allowing to: + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Provide a tick value in millisecond + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Provide a blocking delay in millisecond + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Suspend the time base source interrupt + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Resume the time base source interrupt + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Get the HAL API driver version + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Get the device identifier + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Get the device revision identifier + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Enable/Disable Debug module during Sleep mode + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Enable/Disable Debug module during STOP mode + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Enable/Disable Debug module during STANDBY mode + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @endverbatim + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function is called to increment a global variable "uwTick" + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * used as application time base. + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation, this variable is incremented each 1ms + ARM GAS /tmp/ccjtZjrH.s page 10 + + + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * in SysTick ISR. + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_IncTick(void) + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 232 .loc 1 279 1 is_stmt 1 view -0 + 233 .cfi_startproc + 234 @ args = 0, pretend = 0, frame = 0 + 235 @ frame_needed = 0, uses_anonymous_args = 0 + 236 @ link register save eliminated. + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTick += uwTickFreq; + 237 .loc 1 280 3 view .LVU40 + 238 .loc 1 280 10 is_stmt 0 view .LVU41 + 239 0000 034A ldr r2, .L20 + 240 0002 1168 ldr r1, [r2] + 241 0004 034B ldr r3, .L20+4 + 242 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 243 0008 0B44 add r3, r3, r1 + 244 000a 1360 str r3, [r2] + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 245 .loc 1 281 1 view .LVU42 + 246 000c 7047 bx lr + 247 .L21: + 248 000e 00BF .align 2 + 249 .L20: + 250 0010 00000000 .word uwTick + 251 0014 00000000 .word uwTickFreq + 252 .cfi_endproc + 253 .LFE135: + 255 .section .text.HAL_GetTick,"ax",%progbits + 256 .align 1 + 257 .weak HAL_GetTick + 258 .syntax unified + 259 .thumb + 260 .thumb_func + 262 HAL_GetTick: + 263 .LFB136: + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Povides a tick value in millisecond. + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note The function is declared as __Weak to be overwritten in case of other + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval tick value + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak uint32_t HAL_GetTick(void) + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 264 .loc 1 290 1 is_stmt 1 view -0 + 265 .cfi_startproc + 266 @ args = 0, pretend = 0, frame = 0 + 267 @ frame_needed = 0, uses_anonymous_args = 0 + 268 @ link register save eliminated. + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return uwTick; + 269 .loc 1 291 3 view .LVU44 + 270 .loc 1 291 10 is_stmt 0 view .LVU45 + 271 0000 014B ldr r3, .L23 + ARM GAS /tmp/ccjtZjrH.s page 11 + + + 272 0002 1868 ldr r0, [r3] + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 273 .loc 1 292 1 view .LVU46 + 274 0004 7047 bx lr + 275 .L24: + 276 0006 00BF .align 2 + 277 .L23: + 278 0008 00000000 .word uwTick + 279 .cfi_endproc + 280 .LFE136: + 282 .section .text.HAL_GetTickPrio,"ax",%progbits + 283 .align 1 + 284 .global HAL_GetTickPrio + 285 .syntax unified + 286 .thumb + 287 .thumb_func + 289 HAL_GetTickPrio: + 290 .LFB137: + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function returns a tick priority. + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval tick priority + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetTickPrio(void) + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 291 .loc 1 299 1 is_stmt 1 view -0 + 292 .cfi_startproc + 293 @ args = 0, pretend = 0, frame = 0 + 294 @ frame_needed = 0, uses_anonymous_args = 0 + 295 @ link register save eliminated. + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return uwTickPrio; + 296 .loc 1 300 3 view .LVU48 + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 297 .loc 1 301 1 is_stmt 0 view .LVU49 + 298 0000 014B ldr r3, .L26 + 299 0002 1868 ldr r0, [r3] + 300 0004 7047 bx lr + 301 .L27: + 302 0006 00BF .align 2 + 303 .L26: + 304 0008 00000000 .word uwTickPrio + 305 .cfi_endproc + 306 .LFE137: + 308 .section .text.HAL_SetTickFreq,"ax",%progbits + 309 .align 1 + 310 .global HAL_SetTickFreq + 311 .syntax unified + 312 .thumb + 313 .thumb_func + 315 HAL_SetTickFreq: + 316 .LVL9: + 317 .LFB138: + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Set new tick Freq. + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval status + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + ARM GAS /tmp/ccjtZjrH.s page 12 + + + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 318 .loc 1 308 1 is_stmt 1 view -0 + 319 .cfi_startproc + 320 @ args = 0, pretend = 0, frame = 0 + 321 @ frame_needed = 0, uses_anonymous_args = 0 + 322 .loc 1 308 1 is_stmt 0 view .LVU51 + 323 0000 10B5 push {r4, lr} + 324 .cfi_def_cfa_offset 8 + 325 .cfi_offset 4, -8 + 326 .cfi_offset 14, -4 + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_StatusTypeDef status = HAL_OK; + 327 .loc 1 309 3 is_stmt 1 view .LVU52 + 328 .LVL10: + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 329 .loc 1 310 3 view .LVU53 + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** assert_param(IS_TICKFREQ(Freq)); + 330 .loc 1 312 3 view .LVU54 + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (uwTickFreq != Freq) + 331 .loc 1 314 3 view .LVU55 + 332 .loc 1 314 18 is_stmt 0 view .LVU56 + 333 0002 084B ldr r3, .L33 + 334 0004 1C78 ldrb r4, [r3] @ zero_extendqisi2 + 335 .loc 1 314 6 view .LVU57 + 336 0006 8442 cmp r4, r0 + 337 0008 01D1 bne .L32 + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 338 .loc 1 309 21 view .LVU58 + 339 000a 0020 movs r0, #0 + 340 .LVL11: + 341 .L29: + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Back up uwTickFreq frequency */ + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** prevTickFreq = uwTickFreq; + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Update uwTickFreq global variable used by HAL_InitTick() */ + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTickFreq = Freq; + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Apply the new tick Freq */ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** status = HAL_InitTick(uwTickPrio); + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (status != HAL_OK) + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Restore previous tick frequency */ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTickFreq = prevTickFreq; + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return status; + 342 .loc 1 332 3 is_stmt 1 view .LVU59 + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 343 .loc 1 333 1 is_stmt 0 view .LVU60 + 344 000c 10BD pop {r4, pc} + 345 .LVL12: + 346 .L32: + ARM GAS /tmp/ccjtZjrH.s page 13 + + + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 347 .loc 1 317 5 is_stmt 1 view .LVU61 + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 348 .loc 1 320 5 view .LVU62 + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 349 .loc 1 320 16 is_stmt 0 view .LVU63 + 350 000e 1870 strb r0, [r3] + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 351 .loc 1 323 5 is_stmt 1 view .LVU64 + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 352 .loc 1 323 14 is_stmt 0 view .LVU65 + 353 0010 054B ldr r3, .L33+4 + 354 0012 1868 ldr r0, [r3] + 355 .LVL13: + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 356 .loc 1 323 14 view .LVU66 + 357 0014 FFF7FEFF bl HAL_InitTick + 358 .LVL14: + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 359 .loc 1 325 5 is_stmt 1 view .LVU67 + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 360 .loc 1 325 8 is_stmt 0 view .LVU68 + 361 0018 0028 cmp r0, #0 + 362 001a F7D0 beq .L29 + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 363 .loc 1 328 7 is_stmt 1 view .LVU69 + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 364 .loc 1 328 18 is_stmt 0 view .LVU70 + 365 001c 014B ldr r3, .L33 + 366 001e 1C70 strb r4, [r3] + 367 0020 F4E7 b .L29 + 368 .L34: + 369 0022 00BF .align 2 + 370 .L33: + 371 0024 00000000 .word uwTickFreq + 372 0028 00000000 .word uwTickPrio + 373 .cfi_endproc + 374 .LFE138: + 376 .section .text.HAL_GetTickFreq,"ax",%progbits + 377 .align 1 + 378 .global HAL_GetTickFreq + 379 .syntax unified + 380 .thumb + 381 .thumb_func + 383 HAL_GetTickFreq: + 384 .LFB139: + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Return tick frequency. + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval tick period in Hz + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_TickFreqTypeDef HAL_GetTickFreq(void) + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 385 .loc 1 340 1 is_stmt 1 view -0 + 386 .cfi_startproc + 387 @ args = 0, pretend = 0, frame = 0 + 388 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccjtZjrH.s page 14 + + + 389 @ link register save eliminated. + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return uwTickFreq; + 390 .loc 1 341 3 view .LVU72 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 391 .loc 1 342 1 is_stmt 0 view .LVU73 + 392 0000 014B ldr r3, .L36 + 393 0002 1878 ldrb r0, [r3] @ zero_extendqisi2 + 394 0004 7047 bx lr + 395 .L37: + 396 0006 00BF .align 2 + 397 .L36: + 398 0008 00000000 .word uwTickFreq + 399 .cfi_endproc + 400 .LFE139: + 402 .section .text.HAL_Delay,"ax",%progbits + 403 .align 1 + 404 .weak HAL_Delay + 405 .syntax unified + 406 .thumb + 407 .thumb_func + 409 HAL_Delay: + 410 .LVL15: + 411 .LFB140: + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function provides accurate delay (in milliseconds) based + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * on variable incremented. + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * It is used to generate interrupts at regular time intervals where uwTick + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is incremented. + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The function is declared as __Weak to be overwritten in case of other + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @param Delay specifies the delay time length, in milliseconds. + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_Delay(uint32_t Delay) + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 412 .loc 1 356 1 is_stmt 1 view -0 + 413 .cfi_startproc + 414 @ args = 0, pretend = 0, frame = 0 + 415 @ frame_needed = 0, uses_anonymous_args = 0 + 416 .loc 1 356 1 is_stmt 0 view .LVU75 + 417 0000 38B5 push {r3, r4, r5, lr} + 418 .cfi_def_cfa_offset 16 + 419 .cfi_offset 3, -16 + 420 .cfi_offset 4, -12 + 421 .cfi_offset 5, -8 + 422 .cfi_offset 14, -4 + 423 0002 0446 mov r4, r0 + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t tickstart = HAL_GetTick(); + 424 .loc 1 357 3 is_stmt 1 view .LVU76 + 425 .loc 1 357 24 is_stmt 0 view .LVU77 + 426 0004 FFF7FEFF bl HAL_GetTick + 427 .LVL16: + 428 .loc 1 357 24 view .LVU78 + 429 0008 0546 mov r5, r0 + 430 .LVL17: + ARM GAS /tmp/ccjtZjrH.s page 15 + + + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t wait = Delay; + 431 .loc 1 358 3 is_stmt 1 view .LVU79 + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Add freq to guarantee minimum wait */ + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (wait < HAL_MAX_DELAY) + 432 .loc 1 361 3 view .LVU80 + 433 .loc 1 361 6 is_stmt 0 view .LVU81 + 434 000a B4F1FF3F cmp r4, #-1 + 435 000e 02D0 beq .L40 + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** wait += (uint32_t)(uwTickFreq); + 436 .loc 1 363 5 is_stmt 1 view .LVU82 + 437 .loc 1 363 13 is_stmt 0 view .LVU83 + 438 0010 044B ldr r3, .L42 + 439 0012 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 440 .loc 1 363 10 view .LVU84 + 441 0014 1C44 add r4, r4, r3 + 442 .LVL18: + 443 .L40: + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** while((HAL_GetTick() - tickstart) < wait) + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 444 .loc 1 368 3 is_stmt 1 discriminator 1 view .LVU85 + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 445 .loc 1 366 37 discriminator 1 view .LVU86 + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 446 .loc 1 366 10 is_stmt 0 discriminator 1 view .LVU87 + 447 0016 FFF7FEFF bl HAL_GetTick + 448 .LVL19: + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 449 .loc 1 366 24 discriminator 1 view .LVU88 + 450 001a 401B subs r0, r0, r5 + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 451 .loc 1 366 37 discriminator 1 view .LVU89 + 452 001c A042 cmp r0, r4 + 453 001e FAD3 bcc .L40 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 454 .loc 1 369 1 view .LVU90 + 455 0020 38BD pop {r3, r4, r5, pc} + 456 .LVL20: + 457 .L43: + 458 .loc 1 369 1 view .LVU91 + 459 0022 00BF .align 2 + 460 .L42: + 461 0024 00000000 .word uwTickFreq + 462 .cfi_endproc + 463 .LFE140: + 465 .section .text.HAL_SuspendTick,"ax",%progbits + 466 .align 1 + 467 .weak HAL_SuspendTick + 468 .syntax unified + 469 .thumb + 470 .thumb_func + 472 HAL_SuspendTick: + 473 .LFB141: + ARM GAS /tmp/ccjtZjrH.s page 16 + + + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Suspend Tick increment. + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is called, the the SysTick interrupt will be disabled and so Tick increment + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is suspended. + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_SuspendTick(void) + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 474 .loc 1 383 1 is_stmt 1 view -0 + 475 .cfi_startproc + 476 @ args = 0, pretend = 0, frame = 0 + 477 @ frame_needed = 0, uses_anonymous_args = 0 + 478 @ link register save eliminated. + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Disable SysTick Interrupt */ + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + 479 .loc 1 385 3 view .LVU93 + 480 .loc 1 385 10 is_stmt 0 view .LVU94 + 481 0000 4FF0E022 mov r2, #-536813568 + 482 0004 1369 ldr r3, [r2, #16] + 483 .loc 1 385 17 view .LVU95 + 484 0006 23F00203 bic r3, r3, #2 + 485 000a 1361 str r3, [r2, #16] + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 486 .loc 1 387 1 view .LVU96 + 487 000c 7047 bx lr + 488 .cfi_endproc + 489 .LFE141: + 491 .section .text.HAL_ResumeTick,"ax",%progbits + 492 .align 1 + 493 .weak HAL_ResumeTick + 494 .syntax unified + 495 .thumb + 496 .thumb_func + 498 HAL_ResumeTick: + 499 .LFB142: + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Resume Tick increment. + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is called, the the SysTick interrupt will be enabled and so Tick increment + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is resumed. + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The function is declared as __Weak to be overwritten in case of other + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_ResumeTick(void) + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 500 .loc 1 400 1 is_stmt 1 view -0 + 501 .cfi_startproc + ARM GAS /tmp/ccjtZjrH.s page 17 + + + 502 @ args = 0, pretend = 0, frame = 0 + 503 @ frame_needed = 0, uses_anonymous_args = 0 + 504 @ link register save eliminated. + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Enable SysTick Interrupt */ + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + 505 .loc 1 402 3 view .LVU98 + 506 .loc 1 402 10 is_stmt 0 view .LVU99 + 507 0000 4FF0E022 mov r2, #-536813568 + 508 0004 1369 ldr r3, [r2, #16] + 509 .loc 1 402 18 view .LVU100 + 510 0006 43F00203 orr r3, r3, #2 + 511 000a 1361 str r3, [r2, #16] + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 512 .loc 1 404 1 view .LVU101 + 513 000c 7047 bx lr + 514 .cfi_endproc + 515 .LFE142: + 517 .section .text.HAL_GetHalVersion,"ax",%progbits + 518 .align 1 + 519 .global HAL_GetHalVersion + 520 .syntax unified + 521 .thumb + 522 .thumb_func + 524 HAL_GetHalVersion: + 525 .LFB143: + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function returns the HAL revision + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval version 0xXYZR (8bits for each decimal, R for RC) + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetHalVersion(void) + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 526 .loc 1 411 1 is_stmt 1 view -0 + 527 .cfi_startproc + 528 @ args = 0, pretend = 0, frame = 0 + 529 @ frame_needed = 0, uses_anonymous_args = 0 + 530 @ link register save eliminated. + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return __STM32F3xx_HAL_VERSION; + 531 .loc 1 412 2 view .LVU103 + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 532 .loc 1 413 1 is_stmt 0 view .LVU104 + 533 0000 0048 ldr r0, .L47 + 534 0002 7047 bx lr + 535 .L48: + 536 .align 2 + 537 .L47: + 538 0004 00060501 .word 17106432 + 539 .cfi_endproc + 540 .LFE143: + 542 .section .text.HAL_GetREVID,"ax",%progbits + 543 .align 1 + 544 .global HAL_GetREVID + 545 .syntax unified + 546 .thumb + 547 .thumb_func + 549 HAL_GetREVID: + ARM GAS /tmp/ccjtZjrH.s page 18 + + + 550 .LFB144: + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns the device revision identifier. + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device revision identifier + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetREVID(void) + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 551 .loc 1 420 1 is_stmt 1 view -0 + 552 .cfi_startproc + 553 @ args = 0, pretend = 0, frame = 0 + 554 @ frame_needed = 0, uses_anonymous_args = 0 + 555 @ link register save eliminated. + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return((DBGMCU->IDCODE) >> 16U); + 556 .loc 1 421 3 view .LVU106 + 557 .loc 1 421 17 is_stmt 0 view .LVU107 + 558 0000 014B ldr r3, .L50 + 559 0002 1868 ldr r0, [r3] + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 560 .loc 1 422 1 view .LVU108 + 561 0004 000C lsrs r0, r0, #16 + 562 0006 7047 bx lr + 563 .L51: + 564 .align 2 + 565 .L50: + 566 0008 002004E0 .word -536600576 + 567 .cfi_endproc + 568 .LFE144: + 570 .section .text.HAL_GetDEVID,"ax",%progbits + 571 .align 1 + 572 .global HAL_GetDEVID + 573 .syntax unified + 574 .thumb + 575 .thumb_func + 577 HAL_GetDEVID: + 578 .LFB145: + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns the device identifier. + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device identifier + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetDEVID(void) + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 579 .loc 1 429 1 is_stmt 1 view -0 + 580 .cfi_startproc + 581 @ args = 0, pretend = 0, frame = 0 + 582 @ frame_needed = 0, uses_anonymous_args = 0 + 583 @ link register save eliminated. + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); + 584 .loc 1 430 3 view .LVU110 + 585 .loc 1 430 17 is_stmt 0 view .LVU111 + 586 0000 024B ldr r3, .L53 + 587 0002 1868 ldr r0, [r3] + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 588 .loc 1 431 1 view .LVU112 + 589 0004 C0F30B00 ubfx r0, r0, #0, #12 + 590 0008 7047 bx lr + ARM GAS /tmp/ccjtZjrH.s page 19 + + + 591 .L54: + 592 000a 00BF .align 2 + 593 .L53: + 594 000c 002004E0 .word -536600576 + 595 .cfi_endproc + 596 .LFE145: + 598 .section .text.HAL_GetUIDw0,"ax",%progbits + 599 .align 1 + 600 .global HAL_GetUIDw0 + 601 .syntax unified + 602 .thumb + 603 .thumb_func + 605 HAL_GetUIDw0: + 606 .LFB146: + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns first word of the unique device identifier (UID based on 96 bits) + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device identifier + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetUIDw0(void) + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 607 .loc 1 438 1 is_stmt 1 view -0 + 608 .cfi_startproc + 609 @ args = 0, pretend = 0, frame = 0 + 610 @ frame_needed = 0, uses_anonymous_args = 0 + 611 @ link register save eliminated. + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return(READ_REG(*((uint32_t *)UID_BASE))); + 612 .loc 1 439 4 view .LVU114 + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 613 .loc 1 440 1 is_stmt 0 view .LVU115 + 614 0000 014B ldr r3, .L56 + 615 0002 D3F8AC07 ldr r0, [r3, #1964] + 616 0006 7047 bx lr + 617 .L57: + 618 .align 2 + 619 .L56: + 620 0008 00F0FF1F .word 536866816 + 621 .cfi_endproc + 622 .LFE146: + 624 .section .text.HAL_GetUIDw1,"ax",%progbits + 625 .align 1 + 626 .global HAL_GetUIDw1 + 627 .syntax unified + 628 .thumb + 629 .thumb_func + 631 HAL_GetUIDw1: + 632 .LFB147: + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns second word of the unique device identifier (UID based on 96 bits) + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device identifier + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetUIDw1(void) + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 633 .loc 1 447 1 is_stmt 1 view -0 + 634 .cfi_startproc + 635 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccjtZjrH.s page 20 + + + 636 @ frame_needed = 0, uses_anonymous_args = 0 + 637 @ link register save eliminated. + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + 638 .loc 1 448 4 view .LVU117 + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 639 .loc 1 449 1 is_stmt 0 view .LVU118 + 640 0000 014B ldr r3, .L59 + 641 0002 D3F8B007 ldr r0, [r3, #1968] + 642 0006 7047 bx lr + 643 .L60: + 644 .align 2 + 645 .L59: + 646 0008 00F0FF1F .word 536866816 + 647 .cfi_endproc + 648 .LFE147: + 650 .section .text.HAL_GetUIDw2,"ax",%progbits + 651 .align 1 + 652 .global HAL_GetUIDw2 + 653 .syntax unified + 654 .thumb + 655 .thumb_func + 657 HAL_GetUIDw2: + 658 .LFB148: + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns third word of the unique device identifier (UID based on 96 bits) + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device identifier + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetUIDw2(void) + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 659 .loc 1 456 1 is_stmt 1 view -0 + 660 .cfi_startproc + 661 @ args = 0, pretend = 0, frame = 0 + 662 @ frame_needed = 0, uses_anonymous_args = 0 + 663 @ link register save eliminated. + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + 664 .loc 1 457 4 view .LVU120 + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 665 .loc 1 458 1 is_stmt 0 view .LVU121 + 666 0000 014B ldr r3, .L62 + 667 0002 D3F8B407 ldr r0, [r3, #1972] + 668 0006 7047 bx lr + 669 .L63: + 670 .align 2 + 671 .L62: + 672 0008 00F0FF1F .word 536866816 + 673 .cfi_endproc + 674 .LFE148: + 676 .section .text.HAL_DBGMCU_EnableDBGSleepMode,"ax",%progbits + 677 .align 1 + 678 .global HAL_DBGMCU_EnableDBGSleepMode + 679 .syntax unified + 680 .thumb + 681 .thumb_func + 683 HAL_DBGMCU_EnableDBGSleepMode: + 684 .LFB149: + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + ARM GAS /tmp/ccjtZjrH.s page 21 + + + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Enable the Debug Module during SLEEP mode + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_EnableDBGSleepMode(void) + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 685 .loc 1 465 1 is_stmt 1 view -0 + 686 .cfi_startproc + 687 @ args = 0, pretend = 0, frame = 0 + 688 @ frame_needed = 0, uses_anonymous_args = 0 + 689 @ link register save eliminated. + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 690 .loc 1 466 3 view .LVU123 + 691 0000 024A ldr r2, .L65 + 692 0002 5368 ldr r3, [r2, #4] + 693 0004 43F00103 orr r3, r3, #1 + 694 0008 5360 str r3, [r2, #4] + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 695 .loc 1 467 1 is_stmt 0 view .LVU124 + 696 000a 7047 bx lr + 697 .L66: + 698 .align 2 + 699 .L65: + 700 000c 002004E0 .word -536600576 + 701 .cfi_endproc + 702 .LFE149: + 704 .section .text.HAL_DBGMCU_DisableDBGSleepMode,"ax",%progbits + 705 .align 1 + 706 .global HAL_DBGMCU_DisableDBGSleepMode + 707 .syntax unified + 708 .thumb + 709 .thumb_func + 711 HAL_DBGMCU_DisableDBGSleepMode: + 712 .LFB150: + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Disable the Debug Module during SLEEP mode + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_DisableDBGSleepMode(void) + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 713 .loc 1 474 1 is_stmt 1 view -0 + 714 .cfi_startproc + 715 @ args = 0, pretend = 0, frame = 0 + 716 @ frame_needed = 0, uses_anonymous_args = 0 + 717 @ link register save eliminated. + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 718 .loc 1 475 3 view .LVU126 + 719 0000 024A ldr r2, .L68 + 720 0002 5368 ldr r3, [r2, #4] + 721 0004 23F00103 bic r3, r3, #1 + 722 0008 5360 str r3, [r2, #4] + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 723 .loc 1 476 1 is_stmt 0 view .LVU127 + 724 000a 7047 bx lr + 725 .L69: + 726 .align 2 + ARM GAS /tmp/ccjtZjrH.s page 22 + + + 727 .L68: + 728 000c 002004E0 .word -536600576 + 729 .cfi_endproc + 730 .LFE150: + 732 .section .text.HAL_DBGMCU_EnableDBGStopMode,"ax",%progbits + 733 .align 1 + 734 .global HAL_DBGMCU_EnableDBGStopMode + 735 .syntax unified + 736 .thumb + 737 .thumb_func + 739 HAL_DBGMCU_EnableDBGStopMode: + 740 .LFB151: + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Enable the Debug Module during STOP mode + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_EnableDBGStopMode(void) + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 741 .loc 1 483 1 is_stmt 1 view -0 + 742 .cfi_startproc + 743 @ args = 0, pretend = 0, frame = 0 + 744 @ frame_needed = 0, uses_anonymous_args = 0 + 745 @ link register save eliminated. + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 746 .loc 1 484 3 view .LVU129 + 747 0000 024A ldr r2, .L71 + 748 0002 5368 ldr r3, [r2, #4] + 749 0004 43F00203 orr r3, r3, #2 + 750 0008 5360 str r3, [r2, #4] + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 751 .loc 1 485 1 is_stmt 0 view .LVU130 + 752 000a 7047 bx lr + 753 .L72: + 754 .align 2 + 755 .L71: + 756 000c 002004E0 .word -536600576 + 757 .cfi_endproc + 758 .LFE151: + 760 .section .text.HAL_DBGMCU_DisableDBGStopMode,"ax",%progbits + 761 .align 1 + 762 .global HAL_DBGMCU_DisableDBGStopMode + 763 .syntax unified + 764 .thumb + 765 .thumb_func + 767 HAL_DBGMCU_DisableDBGStopMode: + 768 .LFB152: + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Disable the Debug Module during STOP mode + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_DisableDBGStopMode(void) + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 769 .loc 1 492 1 is_stmt 1 view -0 + 770 .cfi_startproc + 771 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccjtZjrH.s page 23 + + + 772 @ frame_needed = 0, uses_anonymous_args = 0 + 773 @ link register save eliminated. + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 774 .loc 1 493 3 view .LVU132 + 775 0000 024A ldr r2, .L74 + 776 0002 5368 ldr r3, [r2, #4] + 777 0004 23F00203 bic r3, r3, #2 + 778 0008 5360 str r3, [r2, #4] + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 779 .loc 1 494 1 is_stmt 0 view .LVU133 + 780 000a 7047 bx lr + 781 .L75: + 782 .align 2 + 783 .L74: + 784 000c 002004E0 .word -536600576 + 785 .cfi_endproc + 786 .LFE152: + 788 .section .text.HAL_DBGMCU_EnableDBGStandbyMode,"ax",%progbits + 789 .align 1 + 790 .global HAL_DBGMCU_EnableDBGStandbyMode + 791 .syntax unified + 792 .thumb + 793 .thumb_func + 795 HAL_DBGMCU_EnableDBGStandbyMode: + 796 .LFB153: + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Enable the Debug Module during STANDBY mode + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_EnableDBGStandbyMode(void) + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 797 .loc 1 501 1 is_stmt 1 view -0 + 798 .cfi_startproc + 799 @ args = 0, pretend = 0, frame = 0 + 800 @ frame_needed = 0, uses_anonymous_args = 0 + 801 @ link register save eliminated. + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 802 .loc 1 502 3 view .LVU135 + 803 0000 024A ldr r2, .L77 + 804 0002 5368 ldr r3, [r2, #4] + 805 0004 43F00403 orr r3, r3, #4 + 806 0008 5360 str r3, [r2, #4] + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 807 .loc 1 503 1 is_stmt 0 view .LVU136 + 808 000a 7047 bx lr + 809 .L78: + 810 .align 2 + 811 .L77: + 812 000c 002004E0 .word -536600576 + 813 .cfi_endproc + 814 .LFE153: + 816 .section .text.HAL_DBGMCU_DisableDBGStandbyMode,"ax",%progbits + 817 .align 1 + 818 .global HAL_DBGMCU_DisableDBGStandbyMode + 819 .syntax unified + 820 .thumb + ARM GAS /tmp/ccjtZjrH.s page 24 + + + 821 .thumb_func + 823 HAL_DBGMCU_DisableDBGStandbyMode: + 824 .LFB154: + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Disable the Debug Module during STANDBY mode + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_DisableDBGStandbyMode(void) + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 825 .loc 1 510 1 is_stmt 1 view -0 + 826 .cfi_startproc + 827 @ args = 0, pretend = 0, frame = 0 + 828 @ frame_needed = 0, uses_anonymous_args = 0 + 829 @ link register save eliminated. + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 830 .loc 1 511 3 view .LVU138 + 831 0000 024A ldr r2, .L80 + 832 0002 5368 ldr r3, [r2, #4] + 833 0004 23F00403 bic r3, r3, #4 + 834 0008 5360 str r3, [r2, #4] + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 835 .loc 1 512 1 is_stmt 0 view .LVU139 + 836 000a 7047 bx lr + 837 .L81: + 838 .align 2 + 839 .L80: + 840 000c 002004E0 .word -536600576 + 841 .cfi_endproc + 842 .LFE154: + 844 .global uwTickFreq + 845 .section .data.uwTickFreq,"aw" + 848 uwTickFreq: + 849 0000 01 .byte 1 + 850 .global uwTickPrio + 851 .section .data.uwTickPrio,"aw" + 852 .align 2 + 855 uwTickPrio: + 856 0000 10000000 .word 16 + 857 .global uwTick + 858 .section .bss.uwTick,"aw",%nobits + 859 .align 2 + 862 uwTick: + 863 0000 00000000 .space 4 + 864 .text + 865 .Letext0: + 866 .file 2 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 867 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 868 .file 4 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 869 .file 5 "Drivers/CMSIS/Include/core_cm4.h" + 870 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 871 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 872 .file 8 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + 873 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h" + ARM GAS /tmp/ccjtZjrH.s page 25 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal.c + /tmp/ccjtZjrH.s:21 .text.HAL_MspInit:0000000000000000 $t + /tmp/ccjtZjrH.s:27 .text.HAL_MspInit:0000000000000000 HAL_MspInit + /tmp/ccjtZjrH.s:40 .text.HAL_MspDeInit:0000000000000000 $t + /tmp/ccjtZjrH.s:46 .text.HAL_MspDeInit:0000000000000000 HAL_MspDeInit + /tmp/ccjtZjrH.s:59 .text.HAL_DeInit:0000000000000000 $t + /tmp/ccjtZjrH.s:65 .text.HAL_DeInit:0000000000000000 HAL_DeInit + /tmp/ccjtZjrH.s:100 .text.HAL_DeInit:0000000000000020 $d + /tmp/ccjtZjrH.s:105 .text.HAL_InitTick:0000000000000000 $t + /tmp/ccjtZjrH.s:111 .text.HAL_InitTick:0000000000000000 HAL_InitTick + /tmp/ccjtZjrH.s:173 .text.HAL_InitTick:0000000000000040 $d + /tmp/ccjtZjrH.s:848 .data.uwTickFreq:0000000000000000 uwTickFreq + /tmp/ccjtZjrH.s:855 .data.uwTickPrio:0000000000000000 uwTickPrio + /tmp/ccjtZjrH.s:180 .text.HAL_Init:0000000000000000 $t + /tmp/ccjtZjrH.s:186 .text.HAL_Init:0000000000000000 HAL_Init + /tmp/ccjtZjrH.s:219 .text.HAL_Init:0000000000000020 $d + /tmp/ccjtZjrH.s:224 .text.HAL_IncTick:0000000000000000 $t + /tmp/ccjtZjrH.s:230 .text.HAL_IncTick:0000000000000000 HAL_IncTick + /tmp/ccjtZjrH.s:250 .text.HAL_IncTick:0000000000000010 $d + /tmp/ccjtZjrH.s:862 .bss.uwTick:0000000000000000 uwTick + /tmp/ccjtZjrH.s:256 .text.HAL_GetTick:0000000000000000 $t + /tmp/ccjtZjrH.s:262 .text.HAL_GetTick:0000000000000000 HAL_GetTick + /tmp/ccjtZjrH.s:278 .text.HAL_GetTick:0000000000000008 $d + /tmp/ccjtZjrH.s:283 .text.HAL_GetTickPrio:0000000000000000 $t + /tmp/ccjtZjrH.s:289 .text.HAL_GetTickPrio:0000000000000000 HAL_GetTickPrio + /tmp/ccjtZjrH.s:304 .text.HAL_GetTickPrio:0000000000000008 $d + /tmp/ccjtZjrH.s:309 .text.HAL_SetTickFreq:0000000000000000 $t + /tmp/ccjtZjrH.s:315 .text.HAL_SetTickFreq:0000000000000000 HAL_SetTickFreq + /tmp/ccjtZjrH.s:371 .text.HAL_SetTickFreq:0000000000000024 $d + /tmp/ccjtZjrH.s:377 .text.HAL_GetTickFreq:0000000000000000 $t + /tmp/ccjtZjrH.s:383 .text.HAL_GetTickFreq:0000000000000000 HAL_GetTickFreq + /tmp/ccjtZjrH.s:398 .text.HAL_GetTickFreq:0000000000000008 $d + /tmp/ccjtZjrH.s:403 .text.HAL_Delay:0000000000000000 $t + /tmp/ccjtZjrH.s:409 .text.HAL_Delay:0000000000000000 HAL_Delay + /tmp/ccjtZjrH.s:461 .text.HAL_Delay:0000000000000024 $d + /tmp/ccjtZjrH.s:466 .text.HAL_SuspendTick:0000000000000000 $t + /tmp/ccjtZjrH.s:472 .text.HAL_SuspendTick:0000000000000000 HAL_SuspendTick + /tmp/ccjtZjrH.s:492 .text.HAL_ResumeTick:0000000000000000 $t + /tmp/ccjtZjrH.s:498 .text.HAL_ResumeTick:0000000000000000 HAL_ResumeTick + /tmp/ccjtZjrH.s:518 .text.HAL_GetHalVersion:0000000000000000 $t + /tmp/ccjtZjrH.s:524 .text.HAL_GetHalVersion:0000000000000000 HAL_GetHalVersion + /tmp/ccjtZjrH.s:538 .text.HAL_GetHalVersion:0000000000000004 $d + /tmp/ccjtZjrH.s:543 .text.HAL_GetREVID:0000000000000000 $t + /tmp/ccjtZjrH.s:549 .text.HAL_GetREVID:0000000000000000 HAL_GetREVID + /tmp/ccjtZjrH.s:566 .text.HAL_GetREVID:0000000000000008 $d + /tmp/ccjtZjrH.s:571 .text.HAL_GetDEVID:0000000000000000 $t + /tmp/ccjtZjrH.s:577 .text.HAL_GetDEVID:0000000000000000 HAL_GetDEVID + /tmp/ccjtZjrH.s:594 .text.HAL_GetDEVID:000000000000000c $d + /tmp/ccjtZjrH.s:599 .text.HAL_GetUIDw0:0000000000000000 $t + /tmp/ccjtZjrH.s:605 .text.HAL_GetUIDw0:0000000000000000 HAL_GetUIDw0 + /tmp/ccjtZjrH.s:620 .text.HAL_GetUIDw0:0000000000000008 $d + /tmp/ccjtZjrH.s:625 .text.HAL_GetUIDw1:0000000000000000 $t + /tmp/ccjtZjrH.s:631 .text.HAL_GetUIDw1:0000000000000000 HAL_GetUIDw1 + /tmp/ccjtZjrH.s:646 .text.HAL_GetUIDw1:0000000000000008 $d + /tmp/ccjtZjrH.s:651 .text.HAL_GetUIDw2:0000000000000000 $t + /tmp/ccjtZjrH.s:657 .text.HAL_GetUIDw2:0000000000000000 HAL_GetUIDw2 + ARM GAS /tmp/ccjtZjrH.s page 26 + + + /tmp/ccjtZjrH.s:672 .text.HAL_GetUIDw2:0000000000000008 $d + /tmp/ccjtZjrH.s:677 .text.HAL_DBGMCU_EnableDBGSleepMode:0000000000000000 $t + /tmp/ccjtZjrH.s:683 .text.HAL_DBGMCU_EnableDBGSleepMode:0000000000000000 HAL_DBGMCU_EnableDBGSleepMode + /tmp/ccjtZjrH.s:700 .text.HAL_DBGMCU_EnableDBGSleepMode:000000000000000c $d + /tmp/ccjtZjrH.s:705 .text.HAL_DBGMCU_DisableDBGSleepMode:0000000000000000 $t + /tmp/ccjtZjrH.s:711 .text.HAL_DBGMCU_DisableDBGSleepMode:0000000000000000 HAL_DBGMCU_DisableDBGSleepMode + /tmp/ccjtZjrH.s:728 .text.HAL_DBGMCU_DisableDBGSleepMode:000000000000000c $d + /tmp/ccjtZjrH.s:733 .text.HAL_DBGMCU_EnableDBGStopMode:0000000000000000 $t + /tmp/ccjtZjrH.s:739 .text.HAL_DBGMCU_EnableDBGStopMode:0000000000000000 HAL_DBGMCU_EnableDBGStopMode + /tmp/ccjtZjrH.s:756 .text.HAL_DBGMCU_EnableDBGStopMode:000000000000000c $d + /tmp/ccjtZjrH.s:761 .text.HAL_DBGMCU_DisableDBGStopMode:0000000000000000 $t + /tmp/ccjtZjrH.s:767 .text.HAL_DBGMCU_DisableDBGStopMode:0000000000000000 HAL_DBGMCU_DisableDBGStopMode + /tmp/ccjtZjrH.s:784 .text.HAL_DBGMCU_DisableDBGStopMode:000000000000000c $d + /tmp/ccjtZjrH.s:789 .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000000000000 $t + /tmp/ccjtZjrH.s:795 .text.HAL_DBGMCU_EnableDBGStandbyMode:0000000000000000 HAL_DBGMCU_EnableDBGStandbyMode + /tmp/ccjtZjrH.s:812 .text.HAL_DBGMCU_EnableDBGStandbyMode:000000000000000c $d + /tmp/ccjtZjrH.s:817 .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000000000000 $t + /tmp/ccjtZjrH.s:823 .text.HAL_DBGMCU_DisableDBGStandbyMode:0000000000000000 HAL_DBGMCU_DisableDBGStandbyMode + /tmp/ccjtZjrH.s:840 .text.HAL_DBGMCU_DisableDBGStandbyMode:000000000000000c $d + /tmp/ccjtZjrH.s:852 .data.uwTickPrio:0000000000000000 $d + /tmp/ccjtZjrH.s:859 .bss.uwTick:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_SYSTICK_Config +HAL_NVIC_SetPriority +SystemCoreClock +HAL_NVIC_SetPriorityGrouping diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal.o new file mode 100644 index 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b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_can.d @@ -0,0 +1,58 @@ +build/stm32f3xx_hal_can.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_can.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_can.lst new file mode 100644 index 0000000..4498c80 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_can.lst @@ -0,0 +1,7264 @@ +ARM GAS /tmp/ccqPwHQi.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_can.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c" + 20 .section .text.HAL_CAN_MspInit,"ax",%progbits + 21 .align 1 + 22 .weak HAL_CAN_MspInit + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_CAN_MspInit: + 28 .LVL0: + 29 .LFB132: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @file stm32f3xx_hal_can.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief CAN HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * functionalities of the Controller Area Network (CAN) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Configuration functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Control functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Interrupts management + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Callbacks functions + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Peripheral State and Error functions + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### How to use this driver ##### + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Initialize the CAN low level resources by implementing the + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_MspInit(): + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Configure CAN pins + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) Enable the clock for the CAN GPIOs + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) Configure CAN pins as alternate function open-drain + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) Configure the CAN interrupt priority using + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_NVIC_SetPriority() + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + ARM GAS /tmp/ccqPwHQi.s page 2 + + + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** function resorts to HAL_CAN_MspInit() for low-level initialization. + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Configure the reception filters using the following configuration + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** functions: + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_ConfigFilter() + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Start the CAN module using HAL_CAN_Start() function. At this level + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the node is active on the bus: it receive messages, and can send + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** messages. + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) To manage messages transmission, the following Tx control functions + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can be used: + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_AddTxMessage() to request transmission of a new + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** message. + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** message. + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** mailboxes. + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** in a Tx mailbox. + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** sent, if time triggered communication mode is enabled. + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** using the HAL_CAN_GetRxMessage() function. The function + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** stored in the Rx Fifo. + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Calling the HAL_CAN_Stop() function stops the CAN module. + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *** Polling mode operation *** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================== + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Reception: + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** until at least one message is received. + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Then get the message using HAL_CAN_GetRxMessage(). + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Transmission: + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Monitor the Tx mailboxes availability until at least one Tx + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Then request transmission of a message using + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_AddTxMessage(). + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *** Interrupt mode operation *** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ================================ + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Notifications are activated using HAL_CAN_ActivateNotification() + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** function. Then, the process can be controlled through the + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** available user callbacks: HAL_CAN_xxxCallback(), using same APIs + ARM GAS /tmp/ccqPwHQi.s page 3 + + + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Notifications can be deactivated using + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_DeactivateNotification() function. + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** here. + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Directly get the Rx message in the callback, using + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_GetRxMessage(). + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Or deactivate the notification in the callback without + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** getting the Rx message. The Rx message can then be got later + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** using HAL_CAN_GetRxMessage(). Once the Rx message have been + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** read, the notification can be activated again. + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *** Sleep mode *** + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ================== + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) The CAN peripheral can be put in sleep mode (low power), using + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** current CAN activity (transmission or reception of a CAN frame) will + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** be completed. + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) A notification can be activated to be informed when the sleep mode + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** will be entered. + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) It can be checked if the sleep mode is entered using + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_IsSleepActive(). + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Note that the CAN state (accessible from the API HAL_CAN_GetState()) + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** submitted (the sleep mode is not yet entered), and become + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) The wake-up from sleep mode can be triggered by two ways: + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Using HAL_CAN_WakeUp(). When returning from this function, + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the sleep mode is exited (if return status is HAL_OK). + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) When a start of Rx CAN frame is detected by the CAN peripheral, + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if automatic wake up mode is enabled. + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *** Callback registration *** + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================= + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** allows the user to configure dynamically the driver callbacks. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Function HAL_CAN_RegisterCallback() allows to register following callbacks: + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + ARM GAS /tmp/ccqPwHQi.s page 4 + + + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) SleepCallback : Sleep Callback. + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) ErrorCallback : Error Callback. + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) MspInitCallback : CAN MspInit. + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) MspDeInitCallback : CAN MspDeInit. + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** and a pointer to the user callback function. + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** weak function. + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** and the Callback ID. + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** This function allows to reset following callbacks: + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) SleepCallback : Sleep Callback. + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) ErrorCallback : Error Callback. + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) MspInitCallback : CAN MspInit. + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) MspDeInitCallback : CAN MspDeInit. + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** all callbacks are set to the corresponding weak functions: + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** example HAL_CAN_ErrorCallback(). + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Exception done for MspInit and MspDeInit functions that are + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** these callbacks are null (not registered beforehand). + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Exception done MspInit/MspDeInit that can be registered/unregistered + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** In that case first register the MspInit/MspDeInit user callbacks + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** or HAL_CAN_Init() function. + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** not defined, the callback registration feature is not available and all callbacks + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** are set to the corresponding weak functions. + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ****************************************************************************** + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @attention + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + ARM GAS /tmp/ccqPwHQi.s page 5 + + + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * All rights reserved.

    + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This software component is licensed by ST under BSD 3-Clause license, + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the "License"; You may not use this file except in compliance with the + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * License. You may obtain a copy of the License at: + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * opensource.org/licenses/BSD-3-Clause + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ****************************************************************************** + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Includes ------------------------------------------------------------------*/ + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #include "stm32f3xx_hal.h" + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @addtogroup STM32F3xx_HAL_Driver + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if defined(CAN) + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN CAN + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief CAN driver modules + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #ifdef HAL_CAN_MODULE_ENABLED + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #ifdef HAL_CAN_LEGACY_MODULE_ENABLED + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private typedef -----------------------------------------------------------*/ + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private define ------------------------------------------------------------*/ + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Private_Constants CAN Private Constants + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #define CAN_TIMEOUT_VALUE 10U + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private macro -------------------------------------------------------------*/ + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private variables ---------------------------------------------------------*/ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private function prototypes -----------------------------------------------*/ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Exported functions --------------------------------------------------------*/ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions CAN Exported Functions + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Initialization and Configuration functions + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Initialization and de-initialization functions ##### + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] This section provides functions allowing to: + ARM GAS /tmp/ccqPwHQi.s page 6 + + + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_Init : Initialize and configure the CAN. + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_DeInit : De-initialize the CAN. + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_MspInit : Initialize the CAN MSP. + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Initializes the CAN peripheral according to the specified + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * parameters in the CAN_InitStruct. + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tickstart; + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check CAN handle */ + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan == NULL) + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_MODE(hcan->Init.Mode)); + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_RESET) + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset callbacks to legacy functions */ + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0M + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0F + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1M + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1F + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbo + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbo + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbo + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbo + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbo + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbo + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCal + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFr + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCal + ARM GAS /tmp/ccqPwHQi.s page 7 + + + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->MspInitCallback == NULL) + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Init the low level hardware: CLOCK, NVIC */ + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback(hcan); + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_RESET) + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Init the low level hardware: CLOCK, NVIC */ + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_MspInit(hcan); + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request initialisation */ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get tick */ + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** tickstart = HAL_GetTick(); + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wait initialisation acknowledge */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_ERROR; + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Exit from sleep mode */ + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get tick */ + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** tickstart = HAL_GetTick(); + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Sleep mode leave acknowledge */ + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_ERROR; + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + ARM GAS /tmp/ccqPwHQi.s page 8 + + + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the time triggered communication mode */ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.TimeTriggeredMode == ENABLE) + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the automatic bus-off management */ + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.AutoBusOff == ENABLE) + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the automatic wake-up mode */ + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.AutoWakeUp == ENABLE) + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the automatic retransmission */ + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.AutoRetransmission == ENABLE) + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the receive FIFO locked mode */ + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.ReceiveFifoLocked == ENABLE) + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the transmit FIFO priority */ + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.TransmitFifoPriority == ENABLE) + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + ARM GAS /tmp/ccqPwHQi.s page 9 + + + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the bit timing register */ + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Init.SyncJumpWidth | + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Init.TimeSeg1 | + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Init.TimeSeg2 | + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (hcan->Init.Prescaler - 1U))); + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Initialize the error code */ + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Initialize the CAN state */ + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_READY; + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Deinitializes the CAN peripheral registers to their default + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * reset values. + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check CAN handle */ + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan == NULL) + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Stop the CAN module */ + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (void)HAL_CAN_Stop(hcan); + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->MspDeInitCallback == NULL) + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* DeInit the low level hardware: CLOCK, NVIC */ + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback(hcan); + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* DeInit the low level hardware: CLOCK, NVIC */ + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_MspDeInit(hcan); + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + ARM GAS /tmp/ccqPwHQi.s page 10 + + + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset the CAN peripheral */ + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset the CAN ErrorCode */ + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_RESET; + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Initializes the CAN MSP. + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 30 .loc 1 507 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 @ link register save eliminated. + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 35 .loc 1 509 3 view .LVU1 + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_MspInit could be implemented in the user file + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 36 .loc 1 514 1 is_stmt 0 view .LVU2 + 37 0000 7047 bx lr + 38 .cfi_endproc + 39 .LFE132: + 41 .section .text.HAL_CAN_Init,"ax",%progbits + 42 .align 1 + 43 .global HAL_CAN_Init + 44 .syntax unified + 45 .thumb + 46 .thumb_func + 48 HAL_CAN_Init: + 49 .LVL1: + 50 .LFB130: + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tickstart; + 51 .loc 1 275 1 is_stmt 1 view -0 + 52 .cfi_startproc + 53 @ args = 0, pretend = 0, frame = 0 + 54 @ frame_needed = 0, uses_anonymous_args = 0 + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 55 .loc 1 276 3 view .LVU4 + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 56 .loc 1 279 3 view .LVU5 + ARM GAS /tmp/ccqPwHQi.s page 11 + + + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 57 .loc 1 279 6 is_stmt 0 view .LVU6 + 58 0000 0028 cmp r0, #0 + 59 0002 00F0A180 beq .L21 + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tickstart; + 60 .loc 1 275 1 view .LVU7 + 61 0006 38B5 push {r3, r4, r5, lr} + 62 .cfi_def_cfa_offset 16 + 63 .cfi_offset 3, -16 + 64 .cfi_offset 4, -12 + 65 .cfi_offset 5, -8 + 66 .cfi_offset 14, -4 + 67 0008 0446 mov r4, r0 + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + 68 .loc 1 285 3 is_stmt 1 view .LVU8 + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + 69 .loc 1 286 3 view .LVU9 + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + 70 .loc 1 287 3 view .LVU10 + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + 71 .loc 1 288 3 view .LVU11 + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + 72 .loc 1 289 3 view .LVU12 + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + 73 .loc 1 290 3 view .LVU13 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_MODE(hcan->Init.Mode)); + 74 .loc 1 291 3 view .LVU14 + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + 75 .loc 1 292 3 view .LVU15 + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + 76 .loc 1 293 3 view .LVU16 + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + 77 .loc 1 294 3 view .LVU17 + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + 78 .loc 1 295 3 view .LVU18 + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 79 .loc 1 296 3 view .LVU19 + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 80 .loc 1 326 3 view .LVU20 + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 81 .loc 1 326 11 is_stmt 0 view .LVU21 + 82 000a 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 83 .loc 1 326 6 view .LVU22 + 84 000e D3B1 cbz r3, .L26 + 85 .LVL2: + 86 .L4: + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 87 .loc 1 334 3 is_stmt 1 view .LVU23 + 88 0010 2268 ldr r2, [r4] + 89 0012 1368 ldr r3, [r2] + 90 0014 43F00103 orr r3, r3, #1 + 91 0018 1360 str r3, [r2] + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 92 .loc 1 337 3 view .LVU24 + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 93 .loc 1 337 15 is_stmt 0 view .LVU25 + ARM GAS /tmp/ccqPwHQi.s page 12 + + + 94 001a FFF7FEFF bl HAL_GetTick + 95 .LVL3: + 96 001e 0546 mov r5, r0 + 97 .LVL4: + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 98 .loc 1 340 3 is_stmt 1 view .LVU26 + 99 .L5: + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 100 .loc 1 340 47 view .LVU27 + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 101 .loc 1 340 15 is_stmt 0 view .LVU28 + 102 0020 2368 ldr r3, [r4] + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 103 .loc 1 340 25 view .LVU29 + 104 0022 5A68 ldr r2, [r3, #4] + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 105 .loc 1 340 47 view .LVU30 + 106 0024 12F0010F tst r2, #1 + 107 0028 10D1 bne .L27 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 108 .loc 1 342 5 is_stmt 1 view .LVU31 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 109 .loc 1 342 10 is_stmt 0 view .LVU32 + 110 002a FFF7FEFF bl HAL_GetTick + 111 .LVL5: + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 112 .loc 1 342 24 view .LVU33 + 113 002e 401B subs r0, r0, r5 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 114 .loc 1 342 8 view .LVU34 + 115 0030 0A28 cmp r0, #10 + 116 0032 F5D9 bls .L5 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 117 .loc 1 345 7 is_stmt 1 view .LVU35 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 118 .loc 1 345 11 is_stmt 0 view .LVU36 + 119 0034 636A ldr r3, [r4, #36] + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 120 .loc 1 345 23 view .LVU37 + 121 0036 43F40033 orr r3, r3, #131072 + 122 003a 6362 str r3, [r4, #36] + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 123 .loc 1 348 7 is_stmt 1 view .LVU38 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 124 .loc 1 348 19 is_stmt 0 view .LVU39 + 125 003c 0523 movs r3, #5 + 126 003e 84F82030 strb r3, [r4, #32] + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 127 .loc 1 350 7 is_stmt 1 view .LVU40 + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 128 .loc 1 350 14 is_stmt 0 view .LVU41 + 129 0042 0120 movs r0, #1 + 130 .L3: + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 131 .loc 1 450 1 view .LVU42 + 132 0044 38BD pop {r3, r4, r5, pc} + 133 .LVL6: + ARM GAS /tmp/ccqPwHQi.s page 13 + + + 134 .L26: + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 135 .loc 1 329 5 is_stmt 1 view .LVU43 + 136 0046 FFF7FEFF bl HAL_CAN_MspInit + 137 .LVL7: + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 138 .loc 1 329 5 is_stmt 0 view .LVU44 + 139 004a E1E7 b .L4 + 140 .LVL8: + 141 .L27: + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 142 .loc 1 355 3 is_stmt 1 view .LVU45 + 143 004c 1A68 ldr r2, [r3] + 144 004e 22F00202 bic r2, r2, #2 + 145 0052 1A60 str r2, [r3] + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 146 .loc 1 358 3 view .LVU46 + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 147 .loc 1 358 15 is_stmt 0 view .LVU47 + 148 0054 FFF7FEFF bl HAL_GetTick + 149 .LVL9: + 150 0058 0546 mov r5, r0 + 151 .LVL10: + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 152 .loc 1 361 3 is_stmt 1 view .LVU48 + 153 .L7: + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 154 .loc 1 361 47 view .LVU49 + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 155 .loc 1 361 15 is_stmt 0 view .LVU50 + 156 005a 2368 ldr r3, [r4] + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 157 .loc 1 361 25 view .LVU51 + 158 005c 5A68 ldr r2, [r3, #4] + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 159 .loc 1 361 47 view .LVU52 + 160 005e 12F0020F tst r2, #2 + 161 0062 0DD0 beq .L28 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 162 .loc 1 363 5 is_stmt 1 view .LVU53 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 163 .loc 1 363 10 is_stmt 0 view .LVU54 + 164 0064 FFF7FEFF bl HAL_GetTick + 165 .LVL11: + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 166 .loc 1 363 24 view .LVU55 + 167 0068 401B subs r0, r0, r5 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 168 .loc 1 363 8 view .LVU56 + 169 006a 0A28 cmp r0, #10 + 170 006c F5D9 bls .L7 + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 171 .loc 1 366 7 is_stmt 1 view .LVU57 + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 172 .loc 1 366 11 is_stmt 0 view .LVU58 + 173 006e 636A ldr r3, [r4, #36] + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccqPwHQi.s page 14 + + + 174 .loc 1 366 23 view .LVU59 + 175 0070 43F40033 orr r3, r3, #131072 + 176 0074 6362 str r3, [r4, #36] + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 177 .loc 1 369 7 is_stmt 1 view .LVU60 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 178 .loc 1 369 19 is_stmt 0 view .LVU61 + 179 0076 0523 movs r3, #5 + 180 0078 84F82030 strb r3, [r4, #32] + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 181 .loc 1 371 7 is_stmt 1 view .LVU62 + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 182 .loc 1 371 14 is_stmt 0 view .LVU63 + 183 007c 0120 movs r0, #1 + 184 007e E1E7 b .L3 + 185 .L28: + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 186 .loc 1 376 3 is_stmt 1 view .LVU64 + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 187 .loc 1 376 17 is_stmt 0 view .LVU65 + 188 0080 227E ldrb r2, [r4, #24] @ zero_extendqisi2 + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 189 .loc 1 376 6 view .LVU66 + 190 0082 012A cmp r2, #1 + 191 0084 3DD0 beq .L29 + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 192 .loc 1 382 5 is_stmt 1 view .LVU67 + 193 0086 1A68 ldr r2, [r3] + 194 0088 22F08002 bic r2, r2, #128 + 195 008c 1A60 str r2, [r3] + 196 .L10: + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 197 .loc 1 386 3 view .LVU68 + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 198 .loc 1 386 17 is_stmt 0 view .LVU69 + 199 008e 637E ldrb r3, [r4, #25] @ zero_extendqisi2 + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 200 .loc 1 386 6 view .LVU70 + 201 0090 012B cmp r3, #1 + 202 0092 3BD0 beq .L30 + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 203 .loc 1 392 5 is_stmt 1 view .LVU71 + 204 0094 2268 ldr r2, [r4] + 205 0096 1368 ldr r3, [r2] + 206 0098 23F04003 bic r3, r3, #64 + 207 009c 1360 str r3, [r2] + 208 .L12: + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 209 .loc 1 396 3 view .LVU72 + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 210 .loc 1 396 17 is_stmt 0 view .LVU73 + 211 009e A37E ldrb r3, [r4, #26] @ zero_extendqisi2 + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 212 .loc 1 396 6 view .LVU74 + 213 00a0 012B cmp r3, #1 + 214 00a2 39D0 beq .L31 + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + ARM GAS /tmp/ccqPwHQi.s page 15 + + + 215 .loc 1 402 5 is_stmt 1 view .LVU75 + 216 00a4 2268 ldr r2, [r4] + 217 00a6 1368 ldr r3, [r2] + 218 00a8 23F02003 bic r3, r3, #32 + 219 00ac 1360 str r3, [r2] + 220 .L14: + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 221 .loc 1 406 3 view .LVU76 + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 222 .loc 1 406 17 is_stmt 0 view .LVU77 + 223 00ae E37E ldrb r3, [r4, #27] @ zero_extendqisi2 + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 224 .loc 1 406 6 view .LVU78 + 225 00b0 012B cmp r3, #1 + 226 00b2 37D0 beq .L32 + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 227 .loc 1 412 5 is_stmt 1 view .LVU79 + 228 00b4 2268 ldr r2, [r4] + 229 00b6 1368 ldr r3, [r2] + 230 00b8 43F01003 orr r3, r3, #16 + 231 00bc 1360 str r3, [r2] + 232 .L16: + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 233 .loc 1 416 3 view .LVU80 + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 234 .loc 1 416 17 is_stmt 0 view .LVU81 + 235 00be 237F ldrb r3, [r4, #28] @ zero_extendqisi2 + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 236 .loc 1 416 6 view .LVU82 + 237 00c0 012B cmp r3, #1 + 238 00c2 35D0 beq .L33 + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 239 .loc 1 422 5 is_stmt 1 view .LVU83 + 240 00c4 2268 ldr r2, [r4] + 241 00c6 1368 ldr r3, [r2] + 242 00c8 23F00803 bic r3, r3, #8 + 243 00cc 1360 str r3, [r2] + 244 .L18: + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 245 .loc 1 426 3 view .LVU84 + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 246 .loc 1 426 17 is_stmt 0 view .LVU85 + 247 00ce 637F ldrb r3, [r4, #29] @ zero_extendqisi2 + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 248 .loc 1 426 6 view .LVU86 + 249 00d0 012B cmp r3, #1 + 250 00d2 33D0 beq .L34 + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 251 .loc 1 432 5 is_stmt 1 view .LVU87 + 252 00d4 2268 ldr r2, [r4] + 253 00d6 1368 ldr r3, [r2] + 254 00d8 23F00403 bic r3, r3, #4 + 255 00dc 1360 str r3, [r2] + 256 .L20: + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Init.SyncJumpWidth | + 257 .loc 1 436 3 view .LVU88 + 258 00de A368 ldr r3, [r4, #8] + ARM GAS /tmp/ccqPwHQi.s page 16 + + + 259 00e0 E268 ldr r2, [r4, #12] + 260 00e2 1343 orrs r3, r3, r2 + 261 00e4 2269 ldr r2, [r4, #16] + 262 00e6 1343 orrs r3, r3, r2 + 263 00e8 6269 ldr r2, [r4, #20] + 264 00ea 1343 orrs r3, r3, r2 + 265 00ec 6268 ldr r2, [r4, #4] + 266 00ee 013A subs r2, r2, #1 + 267 00f0 2168 ldr r1, [r4] + 268 00f2 1343 orrs r3, r3, r2 + 269 00f4 CB61 str r3, [r1, #28] + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 270 .loc 1 443 3 view .LVU89 + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 271 .loc 1 443 19 is_stmt 0 view .LVU90 + 272 00f6 0020 movs r0, #0 + 273 00f8 6062 str r0, [r4, #36] + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 274 .loc 1 446 3 is_stmt 1 view .LVU91 + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 275 .loc 1 446 15 is_stmt 0 view .LVU92 + 276 00fa 0123 movs r3, #1 + 277 00fc 84F82030 strb r3, [r4, #32] + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 278 .loc 1 449 3 is_stmt 1 view .LVU93 + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 279 .loc 1 449 10 is_stmt 0 view .LVU94 + 280 0100 A0E7 b .L3 + 281 .L29: + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 282 .loc 1 378 5 is_stmt 1 view .LVU95 + 283 0102 1A68 ldr r2, [r3] + 284 0104 42F08002 orr r2, r2, #128 + 285 0108 1A60 str r2, [r3] + 286 010a C0E7 b .L10 + 287 .L30: + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 288 .loc 1 388 5 view .LVU96 + 289 010c 2268 ldr r2, [r4] + 290 010e 1368 ldr r3, [r2] + 291 0110 43F04003 orr r3, r3, #64 + 292 0114 1360 str r3, [r2] + 293 0116 C2E7 b .L12 + 294 .L31: + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 295 .loc 1 398 5 view .LVU97 + 296 0118 2268 ldr r2, [r4] + 297 011a 1368 ldr r3, [r2] + 298 011c 43F02003 orr r3, r3, #32 + 299 0120 1360 str r3, [r2] + 300 0122 C4E7 b .L14 + 301 .L32: + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 302 .loc 1 408 5 view .LVU98 + 303 0124 2268 ldr r2, [r4] + 304 0126 1368 ldr r3, [r2] + 305 0128 23F01003 bic r3, r3, #16 + ARM GAS /tmp/ccqPwHQi.s page 17 + + + 306 012c 1360 str r3, [r2] + 307 012e C6E7 b .L16 + 308 .L33: + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 309 .loc 1 418 5 view .LVU99 + 310 0130 2268 ldr r2, [r4] + 311 0132 1368 ldr r3, [r2] + 312 0134 43F00803 orr r3, r3, #8 + 313 0138 1360 str r3, [r2] + 314 013a C8E7 b .L18 + 315 .L34: + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 316 .loc 1 428 5 view .LVU100 + 317 013c 2268 ldr r2, [r4] + 318 013e 1368 ldr r3, [r2] + 319 0140 43F00403 orr r3, r3, #4 + 320 0144 1360 str r3, [r2] + 321 0146 CAE7 b .L20 + 322 .LVL12: + 323 .L21: + 324 .cfi_def_cfa_offset 0 + 325 .cfi_restore 3 + 326 .cfi_restore 4 + 327 .cfi_restore 5 + 328 .cfi_restore 14 + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 329 .loc 1 281 12 is_stmt 0 view .LVU101 + 330 0148 0120 movs r0, #1 + 331 .LVL13: + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 332 .loc 1 450 1 view .LVU102 + 333 014a 7047 bx lr + 334 .cfi_endproc + 335 .LFE130: + 337 .section .text.HAL_CAN_MspDeInit,"ax",%progbits + 338 .align 1 + 339 .weak HAL_CAN_MspDeInit + 340 .syntax unified + 341 .thumb + 342 .thumb_func + 344 HAL_CAN_MspDeInit: + 345 .LVL14: + 346 .LFB133: + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief DeInitializes the CAN MSP. + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 347 .loc 1 523 1 is_stmt 1 view -0 + 348 .cfi_startproc + 349 @ args = 0, pretend = 0, frame = 0 + 350 @ frame_needed = 0, uses_anonymous_args = 0 + 351 @ link register save eliminated. + ARM GAS /tmp/ccqPwHQi.s page 18 + + + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 352 .loc 1 525 3 view .LVU104 + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_MspDeInit could be implemented in the user file + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 353 .loc 1 530 1 is_stmt 0 view .LVU105 + 354 0000 7047 bx lr + 355 .cfi_endproc + 356 .LFE133: + 358 .section .text.HAL_CAN_ConfigFilter,"ax",%progbits + 359 .align 1 + 360 .global HAL_CAN_ConfigFilter + 361 .syntax unified + 362 .thumb + 363 .thumb_func + 365 HAL_CAN_ConfigFilter: + 366 .LVL15: + 367 .LFB134: + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Register a CAN CallBack. + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * To be used instead of the weak predefined callback + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for CAN module + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param CallbackID ID of the callback to be registered + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be one of the following values: + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param pCallback pointer to the Callback function + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef Callb + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef status = HAL_OK; + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pCallback == NULL) + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccqPwHQi.s page 19 + + + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_READY) + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (CallbackID) + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0CompleteCallback = pCallback; + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1CompleteCallback = pCallback; + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2CompleteCallback = pCallback; + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0AbortCallback = pCallback; + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1AbortCallback = pCallback; + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2AbortCallback = pCallback; + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0MsgPendingCallback = pCallback; + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO0_FULL_CB_ID : + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0FullCallback = pCallback; + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1MsgPendingCallback = pCallback; + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO1_FULL_CB_ID : + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1FullCallback = pCallback; + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_SLEEP_CB_ID : + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->SleepCallback = pCallback; + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->WakeUpFromRxMsgCallback = pCallback; + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_ERROR_CB_ID : + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCallback = pCallback; + ARM GAS /tmp/ccqPwHQi.s page 20 + + + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPINIT_CB_ID : + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = pCallback; + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPDEINIT_CB_ID : + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = pCallback; + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default : + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if (hcan->State == HAL_CAN_STATE_RESET) + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (CallbackID) + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPINIT_CB_ID : + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = pCallback; + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPDEINIT_CB_ID : + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = pCallback; + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default : + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Unregister a CAN CallBack. + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * CAN callabck is redirected to the weak predefined callback + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for CAN module + ARM GAS /tmp/ccqPwHQi.s page 21 + + + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param CallbackID ID of the callback to be unregistered + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be one of the following values: + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef Cal + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef status = HAL_OK; + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_READY) + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (CallbackID) + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO0_FULL_CB_ID : + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + ARM GAS /tmp/ccqPwHQi.s page 22 + + + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO1_FULL_CB_ID : + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_SLEEP_CB_ID : + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->SleepCallback = HAL_CAN_SleepCallback; + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_ERROR_CB_ID : + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCallback = HAL_CAN_ErrorCallback; + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPINIT_CB_ID : + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = HAL_CAN_MspInit; + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPDEINIT_CB_ID : + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default : + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if (hcan->State == HAL_CAN_STATE_RESET) + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (CallbackID) + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPINIT_CB_ID : + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = HAL_CAN_MspInit; + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPDEINIT_CB_ID : + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default : + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + ARM GAS /tmp/ccqPwHQi.s page 23 + + + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group2 Configuration functions + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Configuration functions. + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Configuration functions ##### + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] This section provides functions allowing to: + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Configures the CAN reception filter according to the specified + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * parameters in the CAN_FilterInitStruct. + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * contains the filter configuration information. + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 368 .loc 1 839 1 is_stmt 1 view -0 + 369 .cfi_startproc + 370 @ args = 0, pretend = 0, frame = 0 + 371 @ frame_needed = 0, uses_anonymous_args = 0 + 372 @ link register save eliminated. + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t filternbrbitpos; + 373 .loc 1 840 3 view .LVU107 + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CAN_TypeDef *can_ip = hcan->Instance; + 374 .loc 1 841 3 view .LVU108 + 375 .loc 1 841 16 is_stmt 0 view .LVU109 + 376 0000 0268 ldr r2, [r0] + 377 .LVL16: + ARM GAS /tmp/ccqPwHQi.s page 24 + + + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 378 .loc 1 842 3 is_stmt 1 view .LVU110 + 379 .loc 1 842 24 is_stmt 0 view .LVU111 + 380 0002 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 381 .LVL17: + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 382 .loc 1 844 3 is_stmt 1 view .LVU112 + 383 .loc 1 844 38 is_stmt 0 view .LVU113 + 384 0006 013B subs r3, r3, #1 + 385 .LVL18: + 386 .loc 1 844 38 view .LVU114 + 387 0008 DBB2 uxtb r3, r3 + 388 .loc 1 844 6 view .LVU115 + 389 000a 012B cmp r3, #1 + 390 000c 05D9 bls .L50 + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* CAN is single instance with 14 dedicated filters banks */ + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Initialisation mode for the filter */ + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Convert filter number into bit position */ + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter Deactivation */ + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter Scale */ + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* 16-bit scale for the filter */ + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* First 16-bit identifier and First 16-bit mask */ + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Or First 16-bit identifier and Second 16-bit identifier */ + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Second 16-bit identifier and Second 16-bit mask */ + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ARM GAS /tmp/ccqPwHQi.s page 25 + + + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* 32-bit scale for the filter */ + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FS1R, filternbrbitpos); + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* 32-bit identifier or First 32-bit identifier */ + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* 32-bit mask or Second 32-bit identifier */ + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter Mode */ + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Id/Mask mode for the filter*/ + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Identifier list mode for the filter*/ + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FM1R, filternbrbitpos); + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter FIFO assignment */ + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* FIFO 0 assignation for the filter */ + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* FIFO 1 assignation for the filter */ + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FFA1R, filternbrbitpos); + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter activation */ + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FA1R, filternbrbitpos); + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Leave the initialisation mode for the filter */ + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + ARM GAS /tmp/ccqPwHQi.s page 26 + + + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 391 .loc 1 945 5 is_stmt 1 view .LVU116 + 392 .loc 1 945 9 is_stmt 0 view .LVU117 + 393 000e 436A ldr r3, [r0, #36] + 394 .loc 1 945 21 view .LVU118 + 395 0010 43F48023 orr r3, r3, #262144 + 396 0014 4362 str r3, [r0, #36] + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 397 .loc 1 947 5 is_stmt 1 view .LVU119 + 398 .loc 1 947 12 is_stmt 0 view .LVU120 + 399 0016 0120 movs r0, #1 + 400 .LVL19: + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 401 .loc 1 949 1 view .LVU121 + 402 0018 7047 bx lr + 403 .LVL20: + 404 .L50: + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t filternbrbitpos; + 405 .loc 1 839 1 view .LVU122 + 406 001a 30B4 push {r4, r5} + 407 .cfi_def_cfa_offset 8 + 408 .cfi_offset 4, -8 + 409 .cfi_offset 5, -4 + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + 410 .loc 1 848 5 is_stmt 1 view .LVU123 + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + 411 .loc 1 849 5 view .LVU124 + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + 412 .loc 1 850 5 view .LVU125 + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + 413 .loc 1 851 5 view .LVU126 + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + 414 .loc 1 852 5 view .LVU127 + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + 415 .loc 1 853 5 view .LVU128 + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + 416 .loc 1 854 5 view .LVU129 + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 417 .loc 1 855 5 view .LVU130 + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 418 .loc 1 860 5 view .LVU131 + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 419 .loc 1 863 5 view .LVU132 + 420 001c D2F80032 ldr r3, [r2, #512] + 421 0020 43F00103 orr r3, r3, #1 + 422 0024 C2F80032 str r3, [r2, #512] + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 423 .loc 1 866 5 view .LVU133 + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 424 .loc 1 866 52 is_stmt 0 view .LVU134 + 425 0028 4B69 ldr r3, [r1, #20] + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 426 .loc 1 866 65 view .LVU135 + ARM GAS /tmp/ccqPwHQi.s page 27 + + + 427 002a 03F01F03 and r3, r3, #31 + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 428 .loc 1 866 21 view .LVU136 + 429 002e 0120 movs r0, #1 + 430 .LVL21: + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 431 .loc 1 866 21 view .LVU137 + 432 0030 00FA03F3 lsl r3, r0, r3 + 433 .LVL22: + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 434 .loc 1 869 5 is_stmt 1 view .LVU138 + 435 0034 D2F81C02 ldr r0, [r2, #540] + 436 0038 6FEA030C mvn ip, r3 + 437 003c 20EA0300 bic r0, r0, r3 + 438 0040 C2F81C02 str r0, [r2, #540] + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 439 .loc 1 872 5 view .LVU139 + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 440 .loc 1 872 22 is_stmt 0 view .LVU140 + 441 0044 C869 ldr r0, [r1, #28] + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 442 .loc 1 872 8 view .LVU141 + 443 0046 B0B9 cbnz r0, .L38 + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 444 .loc 1 875 7 is_stmt 1 view .LVU142 + 445 0048 D2F80C02 ldr r0, [r2, #524] + 446 004c 0CEA0000 and r0, ip, r0 + 447 0050 C2F80C02 str r0, [r2, #524] + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 448 .loc 1 879 7 view .LVU143 + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 449 .loc 1 881 22 is_stmt 0 view .LVU144 + 450 0054 8C88 ldrh r4, [r1, #4] + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 451 .loc 1 879 44 view .LVU145 + 452 0056 4869 ldr r0, [r1, #20] + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 453 .loc 1 880 75 view .LVU146 + 454 0058 CD68 ldr r5, [r1, #12] + 455 005a 44EA0544 orr r4, r4, r5, lsl #16 + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 456 .loc 1 879 62 view .LVU147 + 457 005e 4830 adds r0, r0, #72 + 458 0060 42F83040 str r4, [r2, r0, lsl #3] + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 459 .loc 1 885 7 is_stmt 1 view .LVU148 + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 460 .loc 1 887 22 is_stmt 0 view .LVU149 + 461 0064 0C88 ldrh r4, [r1] + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 462 .loc 1 885 44 view .LVU150 + 463 0066 4869 ldr r0, [r1, #20] + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + 464 .loc 1 886 76 view .LVU151 + 465 0068 8D68 ldr r5, [r1, #8] + 466 006a 44EA0544 orr r4, r4, r5, lsl #16 + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + ARM GAS /tmp/ccqPwHQi.s page 28 + + + 467 .loc 1 885 62 view .LVU152 + 468 006e 4830 adds r0, r0, #72 + 469 0070 02EBC000 add r0, r2, r0, lsl #3 + 470 0074 4460 str r4, [r0, #4] + 471 .L38: + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 472 .loc 1 890 5 is_stmt 1 view .LVU153 + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 473 .loc 1 890 22 is_stmt 0 view .LVU154 + 474 0076 C869 ldr r0, [r1, #28] + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 475 .loc 1 890 8 view .LVU155 + 476 0078 0128 cmp r0, #1 + 477 007a 1BD0 beq .L51 + 478 .L39: + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 479 .loc 1 907 5 is_stmt 1 view .LVU156 + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 480 .loc 1 907 22 is_stmt 0 view .LVU157 + 481 007c 8869 ldr r0, [r1, #24] + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 482 .loc 1 907 8 view .LVU158 + 483 007e 80BB cbnz r0, .L40 + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 484 .loc 1 910 7 is_stmt 1 view .LVU159 + 485 0080 D2F80402 ldr r0, [r2, #516] + 486 0084 0CEA0000 and r0, ip, r0 + 487 0088 C2F80402 str r0, [r2, #516] + 488 .L41: + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 489 .loc 1 919 5 view .LVU160 + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 490 .loc 1 919 22 is_stmt 0 view .LVU161 + 491 008c 0869 ldr r0, [r1, #16] + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 492 .loc 1 919 8 view .LVU162 + 493 008e 70BB cbnz r0, .L42 + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 494 .loc 1 922 7 is_stmt 1 view .LVU163 + 495 0090 D2F81402 ldr r0, [r2, #532] + 496 0094 0CEA0000 and r0, ip, r0 + 497 0098 C2F81402 str r0, [r2, #532] + 498 .L43: + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 499 .loc 1 931 5 view .LVU164 + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 500 .loc 1 931 22 is_stmt 0 view .LVU165 + 501 009c 096A ldr r1, [r1, #32] + 502 .LVL23: + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 503 .loc 1 931 8 view .LVU166 + 504 009e 0129 cmp r1, #1 + 505 00a0 2BD0 beq .L52 + 506 .LVL24: + 507 .L44: + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 508 .loc 1 937 5 is_stmt 1 view .LVU167 + ARM GAS /tmp/ccqPwHQi.s page 29 + + + 509 00a2 D2F80032 ldr r3, [r2, #512] + 510 00a6 23F00103 bic r3, r3, #1 + 511 00aa C2F80032 str r3, [r2, #512] + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 512 .loc 1 940 5 view .LVU168 + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 513 .loc 1 940 12 is_stmt 0 view .LVU169 + 514 00ae 0020 movs r0, #0 + 515 .loc 1 949 1 view .LVU170 + 516 00b0 30BC pop {r4, r5} + 517 .cfi_remember_state + 518 .cfi_restore 5 + 519 .cfi_restore 4 + 520 .cfi_def_cfa_offset 0 + 521 00b2 7047 bx lr + 522 .LVL25: + 523 .L51: + 524 .cfi_restore_state + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 525 .loc 1 893 7 is_stmt 1 view .LVU171 + 526 00b4 D2F80C02 ldr r0, [r2, #524] + 527 00b8 1843 orrs r0, r0, r3 + 528 00ba C2F80C02 str r0, [r2, #524] + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 529 .loc 1 896 7 view .LVU172 + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 530 .loc 1 898 22 is_stmt 0 view .LVU173 + 531 00be 8C88 ldrh r4, [r1, #4] + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 532 .loc 1 896 44 view .LVU174 + 533 00c0 4869 ldr r0, [r1, #20] + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 534 .loc 1 897 72 view .LVU175 + 535 00c2 0D68 ldr r5, [r1] + 536 00c4 44EA0544 orr r4, r4, r5, lsl #16 + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 537 .loc 1 896 62 view .LVU176 + 538 00c8 4830 adds r0, r0, #72 + 539 00ca 42F83040 str r4, [r2, r0, lsl #3] + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 540 .loc 1 901 7 is_stmt 1 view .LVU177 + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 541 .loc 1 903 22 is_stmt 0 view .LVU178 + 542 00ce 8C89 ldrh r4, [r1, #12] + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 543 .loc 1 901 44 view .LVU179 + 544 00d0 4869 ldr r0, [r1, #20] + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + 545 .loc 1 902 76 view .LVU180 + 546 00d2 8D68 ldr r5, [r1, #8] + 547 00d4 44EA0544 orr r4, r4, r5, lsl #16 + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 548 .loc 1 901 62 view .LVU181 + 549 00d8 4830 adds r0, r0, #72 + 550 00da 02EBC000 add r0, r2, r0, lsl #3 + 551 00de 4460 str r4, [r0, #4] + 552 00e0 CCE7 b .L39 + ARM GAS /tmp/ccqPwHQi.s page 30 + + + 553 .L40: + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 554 .loc 1 915 7 is_stmt 1 view .LVU182 + 555 00e2 D2F80402 ldr r0, [r2, #516] + 556 00e6 1843 orrs r0, r0, r3 + 557 00e8 C2F80402 str r0, [r2, #516] + 558 00ec CEE7 b .L41 + 559 .L42: + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 560 .loc 1 927 7 view .LVU183 + 561 00ee D2F81402 ldr r0, [r2, #532] + 562 00f2 1843 orrs r0, r0, r3 + 563 00f4 C2F81402 str r0, [r2, #532] + 564 00f8 D0E7 b .L43 + 565 .LVL26: + 566 .L52: + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 567 .loc 1 933 7 view .LVU184 + 568 00fa D2F81C12 ldr r1, [r2, #540] + 569 00fe 0B43 orrs r3, r3, r1 + 570 .LVL27: + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 571 .loc 1 933 7 is_stmt 0 view .LVU185 + 572 0100 C2F81C32 str r3, [r2, #540] + 573 0104 CDE7 b .L44 + 574 .cfi_endproc + 575 .LFE134: + 577 .section .text.HAL_CAN_Start,"ax",%progbits + 578 .align 1 + 579 .global HAL_CAN_Start + 580 .syntax unified + 581 .thumb + 582 .thumb_func + 584 HAL_CAN_Start: + 585 .LVL28: + 586 .LFB135: + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group3 Control functions + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Control functions + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Control functions ##### + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] This section provides functions allowing to: + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_Start : Start the CAN module + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_Stop : Stop the CAN module + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RequestSleep : Request sleep mode entry. + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_WakeUp : Wake up from sleep mode. + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** and activate the corresponding + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** transmission request + ARM GAS /tmp/ccqPwHQi.s page 31 + + + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_AbortTxRequest : Abort transmission request + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pending on the selected Tx mailbox + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Start the CAN module. + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 587 .loc 1 989 1 is_stmt 1 view -0 + 588 .cfi_startproc + 589 @ args = 0, pretend = 0, frame = 0 + 590 @ frame_needed = 0, uses_anonymous_args = 0 + 591 .loc 1 989 1 is_stmt 0 view .LVU187 + 592 0000 70B5 push {r4, r5, r6, lr} + 593 .cfi_def_cfa_offset 16 + 594 .cfi_offset 4, -16 + 595 .cfi_offset 5, -12 + 596 .cfi_offset 6, -8 + 597 .cfi_offset 14, -4 + 598 0002 0446 mov r4, r0 + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tickstart; + 599 .loc 1 990 3 is_stmt 1 view .LVU188 + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_READY) + 600 .loc 1 992 3 view .LVU189 + 601 .loc 1 992 11 is_stmt 0 view .LVU190 + 602 0004 90F82050 ldrb r5, [r0, #32] @ zero_extendqisi2 + 603 0008 EDB2 uxtb r5, r5 + 604 .loc 1 992 6 view .LVU191 + 605 000a 012D cmp r5, #1 + 606 000c 06D0 beq .L59 + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN peripheral state */ + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_LISTENING; + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request leave initialisation */ + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get tick */ +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** tickstart = HAL_GetTick(); +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wait the acknowledge */ +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check for the Timeout */ +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + ARM GAS /tmp/ccqPwHQi.s page 32 + + +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_ERROR; +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset the CAN ErrorCode */ +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode = HAL_CAN_ERROR_NONE; +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + 607 .loc 1 1028 5 is_stmt 1 view .LVU192 + 608 .loc 1 1028 9 is_stmt 0 view .LVU193 + 609 000e 436A ldr r3, [r0, #36] + 610 .loc 1 1028 21 view .LVU194 + 611 0010 43F40023 orr r3, r3, #524288 + 612 0014 4362 str r3, [r0, #36] +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 613 .loc 1 1030 5 is_stmt 1 view .LVU195 + 614 .loc 1 1030 12 is_stmt 0 view .LVU196 + 615 0016 0125 movs r5, #1 + 616 .LVL29: + 617 .L56: +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 618 .loc 1 1032 1 view .LVU197 + 619 0018 2846 mov r0, r5 + 620 001a 70BD pop {r4, r5, r6, pc} + 621 .LVL30: + 622 .L59: + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 623 .loc 1 995 5 is_stmt 1 view .LVU198 + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 624 .loc 1 995 17 is_stmt 0 view .LVU199 + 625 001c 0223 movs r3, #2 + 626 001e 80F82030 strb r3, [r0, #32] + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 627 .loc 1 998 5 is_stmt 1 view .LVU200 + 628 0022 0268 ldr r2, [r0] + 629 0024 1368 ldr r3, [r2] + 630 0026 23F00103 bic r3, r3, #1 + 631 002a 1360 str r3, [r2] +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 632 .loc 1 1001 5 view .LVU201 +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 633 .loc 1 1001 17 is_stmt 0 view .LVU202 + ARM GAS /tmp/ccqPwHQi.s page 33 + + + 634 002c FFF7FEFF bl HAL_GetTick + 635 .LVL31: +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 636 .loc 1 1001 17 view .LVU203 + 637 0030 0646 mov r6, r0 + 638 .LVL32: +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 639 .loc 1 1004 5 is_stmt 1 view .LVU204 + 640 .L55: +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 641 .loc 1 1004 49 view .LVU205 +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 642 .loc 1 1004 17 is_stmt 0 view .LVU206 + 643 0032 2368 ldr r3, [r4] +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 644 .loc 1 1004 27 view .LVU207 + 645 0034 5B68 ldr r3, [r3, #4] +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 646 .loc 1 1004 49 view .LVU208 + 647 0036 13F0010F tst r3, #1 + 648 003a 0CD0 beq .L60 +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 649 .loc 1 1007 7 is_stmt 1 view .LVU209 +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 650 .loc 1 1007 12 is_stmt 0 view .LVU210 + 651 003c FFF7FEFF bl HAL_GetTick + 652 .LVL33: +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 653 .loc 1 1007 26 view .LVU211 + 654 0040 831B subs r3, r0, r6 +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 655 .loc 1 1007 10 view .LVU212 + 656 0042 0A2B cmp r3, #10 + 657 0044 F5D9 bls .L55 +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 658 .loc 1 1010 9 is_stmt 1 view .LVU213 +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 659 .loc 1 1010 13 is_stmt 0 view .LVU214 + 660 0046 636A ldr r3, [r4, #36] +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 661 .loc 1 1010 25 view .LVU215 + 662 0048 43F40033 orr r3, r3, #131072 + 663 004c 6362 str r3, [r4, #36] +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 664 .loc 1 1013 9 is_stmt 1 view .LVU216 +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 665 .loc 1 1013 21 is_stmt 0 view .LVU217 + 666 004e 0523 movs r3, #5 + 667 0050 84F82030 strb r3, [r4, #32] +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 668 .loc 1 1015 9 is_stmt 1 view .LVU218 +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 669 .loc 1 1015 16 is_stmt 0 view .LVU219 + 670 0054 E0E7 b .L56 + 671 .L60: +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 672 .loc 1 1020 5 is_stmt 1 view .LVU220 + ARM GAS /tmp/ccqPwHQi.s page 34 + + +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 673 .loc 1 1020 21 is_stmt 0 view .LVU221 + 674 0056 0025 movs r5, #0 + 675 0058 6562 str r5, [r4, #36] +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 676 .loc 1 1023 5 is_stmt 1 view .LVU222 +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 677 .loc 1 1023 12 is_stmt 0 view .LVU223 + 678 005a DDE7 b .L56 + 679 .cfi_endproc + 680 .LFE135: + 682 .section .text.HAL_CAN_Stop,"ax",%progbits + 683 .align 1 + 684 .global HAL_CAN_Stop + 685 .syntax unified + 686 .thumb + 687 .thumb_func + 689 HAL_CAN_Stop: + 690 .LVL34: + 691 .LFB136: +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Stop the CAN module and enable access to configuration registers. +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 692 .loc 1 1041 1 is_stmt 1 view -0 + 693 .cfi_startproc + 694 @ args = 0, pretend = 0, frame = 0 + 695 @ frame_needed = 0, uses_anonymous_args = 0 + 696 .loc 1 1041 1 is_stmt 0 view .LVU225 + 697 0000 38B5 push {r3, r4, r5, lr} + 698 .cfi_def_cfa_offset 16 + 699 .cfi_offset 3, -16 + 700 .cfi_offset 4, -12 + 701 .cfi_offset 5, -8 + 702 .cfi_offset 14, -4 + 703 0002 0446 mov r4, r0 +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tickstart; + 704 .loc 1 1042 3 is_stmt 1 view .LVU226 +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_LISTENING) + 705 .loc 1 1044 3 view .LVU227 + 706 .loc 1 1044 11 is_stmt 0 view .LVU228 + 707 0004 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 708 0008 DBB2 uxtb r3, r3 + 709 .loc 1 1044 6 view .LVU229 + 710 000a 022B cmp r3, #2 + 711 000c 05D0 beq .L67 +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request initialisation */ +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get tick */ + ARM GAS /tmp/ccqPwHQi.s page 35 + + +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** tickstart = HAL_GetTick(); +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wait the acknowledge */ +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check for the Timeout */ +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_ERROR; +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Exit from sleep mode */ +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN peripheral state */ +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_READY; +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + 712 .loc 1 1080 5 is_stmt 1 view .LVU230 + 713 .loc 1 1080 9 is_stmt 0 view .LVU231 + 714 000e 436A ldr r3, [r0, #36] + 715 .loc 1 1080 21 view .LVU232 + 716 0010 43F48013 orr r3, r3, #1048576 + 717 0014 4362 str r3, [r0, #36] +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 718 .loc 1 1082 5 is_stmt 1 view .LVU233 + 719 .loc 1 1082 12 is_stmt 0 view .LVU234 + 720 0016 0120 movs r0, #1 + 721 .LVL35: + 722 .L64: +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 723 .loc 1 1084 1 view .LVU235 + 724 0018 38BD pop {r3, r4, r5, pc} + 725 .LVL36: + 726 .L67: +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 727 .loc 1 1047 5 is_stmt 1 view .LVU236 + 728 001a 0268 ldr r2, [r0] + 729 001c 1368 ldr r3, [r2] + 730 001e 43F00103 orr r3, r3, #1 + 731 0022 1360 str r3, [r2] +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccqPwHQi.s page 36 + + + 732 .loc 1 1050 5 view .LVU237 +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 733 .loc 1 1050 17 is_stmt 0 view .LVU238 + 734 0024 FFF7FEFF bl HAL_GetTick + 735 .LVL37: +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 736 .loc 1 1050 17 view .LVU239 + 737 0028 0546 mov r5, r0 + 738 .LVL38: +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 739 .loc 1 1053 5 is_stmt 1 view .LVU240 + 740 .L63: +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 741 .loc 1 1053 49 view .LVU241 +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 742 .loc 1 1053 17 is_stmt 0 view .LVU242 + 743 002a 2368 ldr r3, [r4] +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 744 .loc 1 1053 27 view .LVU243 + 745 002c 5A68 ldr r2, [r3, #4] +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 746 .loc 1 1053 49 view .LVU244 + 747 002e 12F0010F tst r2, #1 + 748 0032 0DD1 bne .L68 +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 749 .loc 1 1056 7 is_stmt 1 view .LVU245 +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 750 .loc 1 1056 12 is_stmt 0 view .LVU246 + 751 0034 FFF7FEFF bl HAL_GetTick + 752 .LVL39: +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 753 .loc 1 1056 26 view .LVU247 + 754 0038 431B subs r3, r0, r5 +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 755 .loc 1 1056 10 view .LVU248 + 756 003a 0A2B cmp r3, #10 + 757 003c F5D9 bls .L63 +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 758 .loc 1 1059 9 is_stmt 1 view .LVU249 +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 759 .loc 1 1059 13 is_stmt 0 view .LVU250 + 760 003e 636A ldr r3, [r4, #36] +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 761 .loc 1 1059 25 view .LVU251 + 762 0040 43F40033 orr r3, r3, #131072 + 763 0044 6362 str r3, [r4, #36] +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 764 .loc 1 1062 9 is_stmt 1 view .LVU252 +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 765 .loc 1 1062 21 is_stmt 0 view .LVU253 + 766 0046 0523 movs r3, #5 + 767 0048 84F82030 strb r3, [r4, #32] +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 768 .loc 1 1064 9 is_stmt 1 view .LVU254 +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 769 .loc 1 1064 16 is_stmt 0 view .LVU255 + 770 004c 0120 movs r0, #1 + ARM GAS /tmp/ccqPwHQi.s page 37 + + + 771 004e E3E7 b .L64 + 772 .L68: +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 773 .loc 1 1069 5 is_stmt 1 view .LVU256 + 774 0050 1A68 ldr r2, [r3] + 775 0052 22F00202 bic r2, r2, #2 + 776 0056 1A60 str r2, [r3] +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 777 .loc 1 1072 5 view .LVU257 +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 778 .loc 1 1072 17 is_stmt 0 view .LVU258 + 779 0058 0123 movs r3, #1 + 780 005a 84F82030 strb r3, [r4, #32] +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 781 .loc 1 1075 5 is_stmt 1 view .LVU259 +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 782 .loc 1 1075 12 is_stmt 0 view .LVU260 + 783 005e 0020 movs r0, #0 + 784 0060 DAE7 b .L64 + 785 .cfi_endproc + 786 .LFE136: + 788 .section .text.HAL_CAN_DeInit,"ax",%progbits + 789 .align 1 + 790 .global HAL_CAN_DeInit + 791 .syntax unified + 792 .thumb + 793 .thumb_func + 795 HAL_CAN_DeInit: + 796 .LVL40: + 797 .LFB131: + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check CAN handle */ + 798 .loc 1 460 1 is_stmt 1 view -0 + 799 .cfi_startproc + 800 @ args = 0, pretend = 0, frame = 0 + 801 @ frame_needed = 0, uses_anonymous_args = 0 + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 802 .loc 1 462 3 view .LVU262 + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 803 .loc 1 462 6 is_stmt 0 view .LVU263 + 804 0000 80B1 cbz r0, .L71 + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check CAN handle */ + 805 .loc 1 460 1 view .LVU264 + 806 0002 10B5 push {r4, lr} + 807 .cfi_def_cfa_offset 8 + 808 .cfi_offset 4, -8 + 809 .cfi_offset 14, -4 + 810 0004 0446 mov r4, r0 + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 811 .loc 1 468 3 is_stmt 1 view .LVU265 + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 812 .loc 1 471 3 view .LVU266 + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 813 .loc 1 471 9 is_stmt 0 view .LVU267 + 814 0006 FFF7FEFF bl HAL_CAN_Stop + 815 .LVL41: + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + 816 .loc 1 484 3 is_stmt 1 view .LVU268 + ARM GAS /tmp/ccqPwHQi.s page 38 + + + 817 000a 2046 mov r0, r4 + 818 000c FFF7FEFF bl HAL_CAN_MspDeInit + 819 .LVL42: + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 820 .loc 1 488 3 view .LVU269 + 821 0010 2268 ldr r2, [r4] + 822 0012 1368 ldr r3, [r2] + 823 0014 43F40043 orr r3, r3, #32768 + 824 0018 1360 str r3, [r2] + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 825 .loc 1 491 3 view .LVU270 + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 826 .loc 1 491 19 is_stmt 0 view .LVU271 + 827 001a 0020 movs r0, #0 + 828 001c 6062 str r0, [r4, #36] + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 829 .loc 1 494 3 is_stmt 1 view .LVU272 + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 830 .loc 1 494 15 is_stmt 0 view .LVU273 + 831 001e 84F82000 strb r0, [r4, #32] + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 832 .loc 1 497 3 is_stmt 1 view .LVU274 + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 833 .loc 1 498 1 is_stmt 0 view .LVU275 + 834 0022 10BD pop {r4, pc} + 835 .LVL43: + 836 .L71: + 837 .cfi_def_cfa_offset 0 + 838 .cfi_restore 4 + 839 .cfi_restore 14 + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 840 .loc 1 464 12 view .LVU276 + 841 0024 0120 movs r0, #1 + 842 .LVL44: + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 843 .loc 1 498 1 view .LVU277 + 844 0026 7047 bx lr + 845 .cfi_endproc + 846 .LFE131: + 848 .section .text.HAL_CAN_RequestSleep,"ax",%progbits + 849 .align 1 + 850 .global HAL_CAN_RequestSleep + 851 .syntax unified + 852 .thumb + 853 .thumb_func + 855 HAL_CAN_RequestSleep: + 856 .LVL45: + 857 .LFB137: +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Request the sleep mode (low power) entry. +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * When returning from this function, Sleep mode will be entered +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * as soon as the current CAN activity (transmission or reception +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * of a CAN frame) has been completed. +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status. + ARM GAS /tmp/ccqPwHQi.s page 39 + + +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 858 .loc 1 1096 1 is_stmt 1 view -0 + 859 .cfi_startproc + 860 @ args = 0, pretend = 0, frame = 0 + 861 @ frame_needed = 0, uses_anonymous_args = 0 + 862 @ link register save eliminated. +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 863 .loc 1 1097 3 view .LVU279 + 864 .loc 1 1097 24 is_stmt 0 view .LVU280 + 865 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 866 .LVL46: +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 867 .loc 1 1099 3 is_stmt 1 view .LVU281 + 868 .loc 1 1099 38 is_stmt 0 view .LVU282 + 869 0004 013B subs r3, r3, #1 + 870 .LVL47: + 871 .loc 1 1099 38 view .LVU283 + 872 0006 DBB2 uxtb r3, r3 + 873 .loc 1 1099 6 view .LVU284 + 874 0008 012B cmp r3, #1 + 875 000a 05D9 bls .L79 +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request Sleep mode */ +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 876 .loc 1 1111 5 is_stmt 1 view .LVU285 + 877 .loc 1 1111 9 is_stmt 0 view .LVU286 + 878 000c 436A ldr r3, [r0, #36] + 879 .loc 1 1111 21 view .LVU287 + 880 000e 43F48023 orr r3, r3, #262144 + 881 0012 4362 str r3, [r0, #36] +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 882 .loc 1 1114 5 is_stmt 1 view .LVU288 + 883 .loc 1 1114 12 is_stmt 0 view .LVU289 + 884 0014 0120 movs r0, #1 + 885 .LVL48: +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 886 .loc 1 1116 1 view .LVU290 + 887 0016 7047 bx lr + 888 .LVL49: + 889 .L79: +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 890 .loc 1 1103 5 is_stmt 1 view .LVU291 + ARM GAS /tmp/ccqPwHQi.s page 40 + + + 891 0018 0268 ldr r2, [r0] + 892 001a 1368 ldr r3, [r2] + 893 001c 43F00203 orr r3, r3, #2 + 894 0020 1360 str r3, [r2] +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 895 .loc 1 1106 5 view .LVU292 +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 896 .loc 1 1106 12 is_stmt 0 view .LVU293 + 897 0022 0020 movs r0, #0 + 898 .LVL50: +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 899 .loc 1 1106 12 view .LVU294 + 900 0024 7047 bx lr + 901 .cfi_endproc + 902 .LFE137: + 904 .section .text.HAL_CAN_WakeUp,"ax",%progbits + 905 .align 1 + 906 .global HAL_CAN_WakeUp + 907 .syntax unified + 908 .thumb + 909 .thumb_func + 911 HAL_CAN_WakeUp: + 912 .LVL51: + 913 .LFB138: +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Wake up from sleep mode. +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * When returning with HAL_OK status from this function, Sleep mode +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * is exited. +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status. +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 914 .loc 1 1127 1 is_stmt 1 view -0 + 915 .cfi_startproc + 916 @ args = 0, pretend = 0, frame = 8 + 917 @ frame_needed = 0, uses_anonymous_args = 0 + 918 @ link register save eliminated. + 919 .loc 1 1127 1 is_stmt 0 view .LVU296 + 920 0000 82B0 sub sp, sp, #8 + 921 .cfi_def_cfa_offset 8 +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __IO uint32_t count = 0; + 922 .loc 1 1128 3 is_stmt 1 view .LVU297 + 923 .loc 1 1128 17 is_stmt 0 view .LVU298 + 924 0002 0023 movs r3, #0 + 925 0004 0193 str r3, [sp, #4] +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t timeout = 1000000U; + 926 .loc 1 1129 3 is_stmt 1 view .LVU299 + 927 .LVL52: +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 928 .loc 1 1130 3 view .LVU300 + 929 .loc 1 1130 24 is_stmt 0 view .LVU301 + 930 0006 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 931 .LVL53: +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccqPwHQi.s page 41 + + +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 932 .loc 1 1132 3 is_stmt 1 view .LVU302 + 933 .loc 1 1132 38 is_stmt 0 view .LVU303 + 934 000a 013B subs r3, r3, #1 + 935 .LVL54: + 936 .loc 1 1132 38 view .LVU304 + 937 000c DBB2 uxtb r3, r3 + 938 .loc 1 1132 6 view .LVU305 + 939 000e 012B cmp r3, #1 + 940 0010 18D8 bhi .L81 +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wake up request */ +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 941 .loc 1 1136 5 is_stmt 1 view .LVU306 + 942 0012 0268 ldr r2, [r0] + 943 0014 1368 ldr r3, [r2] + 944 0016 23F00203 bic r3, r3, #2 + 945 001a 1360 str r3, [r2] + 946 .L84: +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wait sleep mode is exited */ +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** do + 947 .loc 1 1139 5 view .LVU307 +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Increment counter */ +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** count++; + 948 .loc 1 1142 7 view .LVU308 + 949 .loc 1 1142 12 is_stmt 0 view .LVU309 + 950 001c 019B ldr r3, [sp, #4] + 951 001e 0133 adds r3, r3, #1 + 952 0020 0193 str r3, [sp, #4] +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check if timeout is reached */ +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (count > timeout) + 953 .loc 1 1145 7 is_stmt 1 view .LVU310 + 954 .loc 1 1145 17 is_stmt 0 view .LVU311 + 955 0022 019A ldr r2, [sp, #4] + 956 .loc 1 1145 10 view .LVU312 + 957 0024 0B4B ldr r3, .L87 + 958 0026 9A42 cmp r2, r3 + 959 0028 06D8 bhi .L86 +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + 960 .loc 1 1153 49 is_stmt 1 view .LVU313 + 961 .loc 1 1153 17 is_stmt 0 view .LVU314 + 962 002a 0368 ldr r3, [r0] + 963 .loc 1 1153 27 view .LVU315 + 964 002c 5B68 ldr r3, [r3, #4] + 965 .loc 1 1153 49 view .LVU316 + 966 002e 13F0020F tst r3, #2 + ARM GAS /tmp/ccqPwHQi.s page 42 + + + 967 0032 F3D1 bne .L84 +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 968 .loc 1 1156 12 view .LVU317 + 969 0034 0020 movs r0, #0 + 970 .LVL55: + 971 .loc 1 1156 12 view .LVU318 + 972 0036 0AE0 b .L83 + 973 .LVL56: + 974 .L86: +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 975 .loc 1 1148 9 is_stmt 1 view .LVU319 +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 976 .loc 1 1148 13 is_stmt 0 view .LVU320 + 977 0038 436A ldr r3, [r0, #36] +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 978 .loc 1 1148 25 view .LVU321 + 979 003a 43F40033 orr r3, r3, #131072 + 980 003e 4362 str r3, [r0, #36] +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 981 .loc 1 1150 9 is_stmt 1 view .LVU322 +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 982 .loc 1 1150 16 is_stmt 0 view .LVU323 + 983 0040 0120 movs r0, #1 + 984 .LVL57: +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 985 .loc 1 1150 16 view .LVU324 + 986 0042 04E0 b .L83 + 987 .LVL58: + 988 .L81: +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 989 .loc 1 1161 5 is_stmt 1 view .LVU325 + 990 .loc 1 1161 9 is_stmt 0 view .LVU326 + 991 0044 436A ldr r3, [r0, #36] + 992 .loc 1 1161 21 view .LVU327 + 993 0046 43F48023 orr r3, r3, #262144 + 994 004a 4362 str r3, [r0, #36] +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 995 .loc 1 1163 5 is_stmt 1 view .LVU328 + 996 .loc 1 1163 12 is_stmt 0 view .LVU329 + 997 004c 0120 movs r0, #1 + 998 .LVL59: + 999 .L83: +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1000 .loc 1 1165 1 view .LVU330 + 1001 004e 02B0 add sp, sp, #8 + 1002 .cfi_def_cfa_offset 0 + 1003 @ sp needed + 1004 0050 7047 bx lr + 1005 .L88: + ARM GAS /tmp/ccqPwHQi.s page 43 + + + 1006 0052 00BF .align 2 + 1007 .L87: + 1008 0054 40420F00 .word 1000000 + 1009 .cfi_endproc + 1010 .LFE138: + 1012 .section .text.HAL_CAN_IsSleepActive,"ax",%progbits + 1013 .align 1 + 1014 .global HAL_CAN_IsSleepActive + 1015 .syntax unified + 1016 .thumb + 1017 .thumb_func + 1019 HAL_CAN_IsSleepActive: + 1020 .LVL60: + 1021 .LFB139: +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Check is sleep mode is active. +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Status +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * - 0 : Sleep mode is not active. +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * - 1 : Sleep mode is active. +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1022 .loc 1 1176 1 is_stmt 1 view -0 + 1023 .cfi_startproc + 1024 @ args = 0, pretend = 0, frame = 0 + 1025 @ frame_needed = 0, uses_anonymous_args = 0 + 1026 @ link register save eliminated. +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t status = 0U; + 1027 .loc 1 1177 3 view .LVU332 +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1028 .loc 1 1178 3 view .LVU333 + 1029 .loc 1 1178 24 is_stmt 0 view .LVU334 + 1030 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 1031 .LVL61: +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1032 .loc 1 1180 3 is_stmt 1 view .LVU335 + 1033 .loc 1 1180 38 is_stmt 0 view .LVU336 + 1034 0004 013B subs r3, r3, #1 + 1035 .LVL62: + 1036 .loc 1 1180 38 view .LVU337 + 1037 0006 DBB2 uxtb r3, r3 + 1038 .loc 1 1180 6 view .LVU338 + 1039 0008 012B cmp r3, #1 + 1040 000a 01D9 bls .L93 +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1041 .loc 1 1177 12 view .LVU339 + 1042 000c 0020 movs r0, #0 + 1043 .LVL63: +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1044 .loc 1 1177 12 view .LVU340 + 1045 000e 7047 bx lr + 1046 .LVL64: + 1047 .L93: + ARM GAS /tmp/ccqPwHQi.s page 44 + + +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Sleep mode */ +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 1048 .loc 1 1184 5 is_stmt 1 view .LVU341 + 1049 .loc 1 1184 14 is_stmt 0 view .LVU342 + 1050 0010 0368 ldr r3, [r0] + 1051 .loc 1 1184 24 view .LVU343 + 1052 0012 5868 ldr r0, [r3, #4] + 1053 .LVL65: + 1054 .loc 1 1184 8 view .LVU344 + 1055 0014 10F00200 ands r0, r0, #2 + 1056 0018 00D1 bne .L92 + 1057 001a 7047 bx lr + 1058 .L92: +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = 1U; + 1059 .loc 1 1186 14 view .LVU345 + 1060 001c 0120 movs r0, #1 + 1061 .LVL66: +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 1062 .loc 1 1191 3 is_stmt 1 view .LVU346 +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1063 .loc 1 1192 1 is_stmt 0 view .LVU347 + 1064 001e 7047 bx lr + 1065 .cfi_endproc + 1066 .LFE139: + 1068 .section .text.HAL_CAN_AddTxMessage,"ax",%progbits + 1069 .align 1 + 1070 .global HAL_CAN_AddTxMessage + 1071 .syntax unified + 1072 .thumb + 1073 .thumb_func + 1075 HAL_CAN_AddTxMessage: + 1076 .LVL67: + 1077 .LFB140: +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Add a message to the first free Tx mailbox and activate the +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * corresponding transmission request. +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param aData array containing the payload of the Tx frame. +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param pTxMailbox pointer to a variable where the function will return +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the TxMailbox used to store the Tx message. +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be a value of @arg CAN_Tx_Mailboxes. +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8 +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1078 .loc 1 1207 1 is_stmt 1 view -0 + 1079 .cfi_startproc + ARM GAS /tmp/ccqPwHQi.s page 45 + + + 1080 @ args = 0, pretend = 0, frame = 0 + 1081 @ frame_needed = 0, uses_anonymous_args = 0 + 1082 .loc 1 1207 1 is_stmt 0 view .LVU349 + 1083 0000 30B5 push {r4, r5, lr} + 1084 .cfi_def_cfa_offset 12 + 1085 .cfi_offset 4, -12 + 1086 .cfi_offset 5, -8 + 1087 .cfi_offset 14, -4 +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t transmitmailbox; + 1088 .loc 1 1208 3 is_stmt 1 view .LVU350 +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1089 .loc 1 1209 3 view .LVU351 + 1090 .loc 1 1209 24 is_stmt 0 view .LVU352 + 1091 0002 90F820C0 ldrb ip, [r0, #32] @ zero_extendqisi2 + 1092 .LVL68: +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tsr = READ_REG(hcan->Instance->TSR); + 1093 .loc 1 1210 3 is_stmt 1 view .LVU353 + 1094 .loc 1 1210 12 is_stmt 0 view .LVU354 + 1095 0006 0468 ldr r4, [r0] + 1096 0008 A468 ldr r4, [r4, #8] + 1097 .LVL69: +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + 1098 .loc 1 1213 3 is_stmt 1 view .LVU355 +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_RTR(pHeader->RTR)); + 1099 .loc 1 1214 3 view .LVU356 +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_DLC(pHeader->DLC)); + 1100 .loc 1 1215 3 view .LVU357 +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pHeader->IDE == CAN_ID_STD) + 1101 .loc 1 1216 3 view .LVU358 +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_STDID(pHeader->StdId)); +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_EXTID(pHeader->ExtId)); + 1102 .loc 1 1222 5 view .LVU359 +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + 1103 .loc 1 1224 3 view .LVU360 +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1104 .loc 1 1226 3 view .LVU361 + 1105 .loc 1 1226 38 is_stmt 0 view .LVU362 + 1106 000a 0CF1FF3C add ip, ip, #-1 + 1107 .LVL70: + 1108 .loc 1 1226 38 view .LVU363 + 1109 000e 5FFA8CFC uxtb ip, ip + 1110 .loc 1 1226 6 view .LVU364 + 1111 0012 BCF1010F cmp ip, #1 + 1112 0016 6BD8 bhi .L95 +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check that all the Tx mailboxes are not full */ +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((tsr & CAN_TSR_TME0) != 0U) || + 1113 .loc 1 1230 5 is_stmt 1 view .LVU365 + ARM GAS /tmp/ccqPwHQi.s page 46 + + + 1114 .loc 1 1230 8 is_stmt 0 view .LVU366 + 1115 0018 14F0E05F tst r4, #469762048 + 1116 001c 62D0 beq .L96 +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((tsr & CAN_TSR_TME1) != 0U) || +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((tsr & CAN_TSR_TME2) != 0U)) +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Select an empty transmit mailbox */ +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + 1117 .loc 1 1235 7 is_stmt 1 view .LVU367 + 1118 .loc 1 1235 23 is_stmt 0 view .LVU368 + 1119 001e C4F3016C ubfx ip, r4, #24, #2 + 1120 .LVL71: +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check transmit mailbox value */ +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (transmitmailbox > 2U) + 1121 .loc 1 1238 7 is_stmt 1 view .LVU369 + 1122 .loc 1 1238 10 is_stmt 0 view .LVU370 + 1123 0022 BCF1020F cmp ip, #2 + 1124 0026 05D9 bls .L97 +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL; + 1125 .loc 1 1241 9 is_stmt 1 view .LVU371 + 1126 .loc 1 1241 13 is_stmt 0 view .LVU372 + 1127 0028 436A ldr r3, [r0, #36] + 1128 .LVL72: + 1129 .loc 1 1241 25 view .LVU373 + 1130 002a 43F40003 orr r3, r3, #8388608 + 1131 002e 4362 str r3, [r0, #36] +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1132 .loc 1 1243 9 is_stmt 1 view .LVU374 + 1133 .loc 1 1243 16 is_stmt 0 view .LVU375 + 1134 0030 0120 movs r0, #1 + 1135 .LVL73: + 1136 .loc 1 1243 16 view .LVU376 + 1137 0032 62E0 b .L98 + 1138 .LVL74: + 1139 .L97: +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Store the Tx mailbox */ +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *pTxMailbox = (uint32_t)1 << transmitmailbox; + 1140 .loc 1 1247 7 is_stmt 1 view .LVU377 + 1141 .loc 1 1247 33 is_stmt 0 view .LVU378 + 1142 0034 0124 movs r4, #1 + 1143 .LVL75: + 1144 .loc 1 1247 33 view .LVU379 + 1145 0036 04FA0CF4 lsl r4, r4, ip + 1146 .loc 1 1247 19 view .LVU380 + 1147 003a 1C60 str r4, [r3] +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set up the Id */ +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pHeader->IDE == CAN_ID_STD) + 1148 .loc 1 1250 7 is_stmt 1 view .LVU381 + 1149 .loc 1 1250 18 is_stmt 0 view .LVU382 + 1150 003c 8B68 ldr r3, [r1, #8] + ARM GAS /tmp/ccqPwHQi.s page 47 + + + 1151 .LVL76: + 1152 .loc 1 1250 10 view .LVU383 + 1153 003e 002B cmp r3, #0 + 1154 0040 3DD1 bne .L99 +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + 1155 .loc 1 1252 9 is_stmt 1 view .LVU384 + 1156 .loc 1 1252 68 is_stmt 0 view .LVU385 + 1157 0042 0D68 ldr r5, [r1] +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1158 .loc 1 1253 67 view .LVU386 + 1159 0044 CB68 ldr r3, [r1, #12] +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1160 .loc 1 1252 13 view .LVU387 + 1161 0046 0468 ldr r4, [r0] +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1162 .loc 1 1252 98 view .LVU388 + 1163 0048 43EA4555 orr r5, r3, r5, lsl #21 +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1164 .loc 1 1252 57 view .LVU389 + 1165 004c 0CF11803 add r3, ip, #24 + 1166 0050 1B01 lsls r3, r3, #4 + 1167 0052 E550 str r5, [r4, r3] + 1168 .L100: +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set up the DLC */ +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + 1169 .loc 1 1263 7 is_stmt 1 view .LVU390 + 1170 .loc 1 1263 11 is_stmt 0 view .LVU391 + 1171 0054 0368 ldr r3, [r0] + 1172 .loc 1 1263 66 view .LVU392 + 1173 0056 0C69 ldr r4, [r1, #16] + 1174 .loc 1 1263 56 view .LVU393 + 1175 0058 0CF1180E add lr, ip, #24 + 1176 005c 03EB0E13 add r3, r3, lr, lsl #4 + 1177 0060 5C60 str r4, [r3, #4] +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set up the Transmit Global Time mode */ +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pHeader->TransmitGlobalTime == ENABLE) + 1178 .loc 1 1266 7 is_stmt 1 view .LVU394 + 1179 .loc 1 1266 18 is_stmt 0 view .LVU395 + 1180 0062 0B7D ldrb r3, [r1, #20] @ zero_extendqisi2 + 1181 .loc 1 1266 10 view .LVU396 + 1182 0064 012B cmp r3, #1 + 1183 0066 35D0 beq .L103 + 1184 .LVL77: + 1185 .L101: +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + ARM GAS /tmp/ccqPwHQi.s page 48 + + +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set up the data field */ +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + 1186 .loc 1 1272 7 is_stmt 1 view .LVU397 + 1187 0068 D179 ldrb r1, [r2, #7] @ zero_extendqisi2 + 1188 006a 9379 ldrb r3, [r2, #6] @ zero_extendqisi2 + 1189 006c 1B04 lsls r3, r3, #16 + 1190 006e 43EA0163 orr r3, r3, r1, lsl #24 + 1191 0072 5179 ldrb r1, [r2, #5] @ zero_extendqisi2 + 1192 0074 43EA0123 orr r3, r3, r1, lsl #8 + 1193 0078 1479 ldrb r4, [r2, #4] @ zero_extendqisi2 + 1194 007a 0168 ldr r1, [r0] + 1195 007c 2343 orrs r3, r3, r4 + 1196 007e 01EB0C11 add r1, r1, ip, lsl #4 + 1197 0082 C1F88C31 str r3, [r1, #396] +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + 1198 .loc 1 1277 7 view .LVU398 + 1199 0086 D178 ldrb r1, [r2, #3] @ zero_extendqisi2 + 1200 0088 9378 ldrb r3, [r2, #2] @ zero_extendqisi2 + 1201 008a 1B04 lsls r3, r3, #16 + 1202 008c 43EA0163 orr r3, r3, r1, lsl #24 + 1203 0090 5178 ldrb r1, [r2, #1] @ zero_extendqisi2 + 1204 0092 43EA0123 orr r3, r3, r1, lsl #8 + 1205 0096 1178 ldrb r1, [r2] @ zero_extendqisi2 + 1206 0098 0268 ldr r2, [r0] + 1207 .LVL78: + 1208 .loc 1 1277 7 is_stmt 0 view .LVU399 + 1209 009a 0B43 orrs r3, r3, r1 + 1210 009c 02EB0C12 add r2, r2, ip, lsl #4 + 1211 00a0 C2F88831 str r3, [r2, #392] +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request transmission */ +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + 1212 .loc 1 1284 7 is_stmt 1 view .LVU400 + 1213 00a4 0268 ldr r2, [r0] + 1214 00a6 0CF1180C add ip, ip, #24 + 1215 .LVL79: + 1216 .loc 1 1284 7 is_stmt 0 view .LVU401 + 1217 00aa 4FEA0C1C lsl ip, ip, #4 + 1218 00ae 52F80C30 ldr r3, [r2, ip] + 1219 00b2 43F00103 orr r3, r3, #1 + 1220 00b6 42F80C30 str r3, [r2, ip] +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 1221 .loc 1 1287 7 is_stmt 1 view .LVU402 + 1222 .loc 1 1287 14 is_stmt 0 view .LVU403 + 1223 00ba 0020 movs r0, #0 + 1224 .LVL80: + ARM GAS /tmp/ccqPwHQi.s page 49 + + + 1225 .loc 1 1287 14 view .LVU404 + 1226 00bc 1DE0 b .L98 + 1227 .LVL81: + 1228 .L99: +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1229 .loc 1 1257 9 is_stmt 1 view .LVU405 +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1230 .loc 1 1257 68 is_stmt 0 view .LVU406 + 1231 00be 4C68 ldr r4, [r1, #4] +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1232 .loc 1 1257 98 view .LVU407 + 1233 00c0 43EAC403 orr r3, r3, r4, lsl #3 +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1234 .loc 1 1259 67 view .LVU408 + 1235 00c4 CC68 ldr r4, [r1, #12] +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1236 .loc 1 1258 73 view .LVU409 + 1237 00c6 2343 orrs r3, r3, r4 +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1238 .loc 1 1257 57 view .LVU410 + 1239 00c8 0CF11804 add r4, ip, #24 + 1240 00cc 2401 lsls r4, r4, #4 + 1241 00ce 0568 ldr r5, [r0] + 1242 00d0 2B51 str r3, [r5, r4] + 1243 00d2 BFE7 b .L100 + 1244 .L103: +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1245 .loc 1 1268 9 is_stmt 1 view .LVU411 + 1246 00d4 0368 ldr r3, [r0] + 1247 00d6 03EB0E13 add r3, r3, lr, lsl #4 + 1248 00da 5968 ldr r1, [r3, #4] + 1249 .LVL82: +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1250 .loc 1 1268 9 is_stmt 0 view .LVU412 + 1251 00dc 41F48071 orr r1, r1, #256 + 1252 00e0 5960 str r1, [r3, #4] + 1253 00e2 C1E7 b .L101 + 1254 .LVL83: + 1255 .L96: +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 1256 .loc 1 1292 7 is_stmt 1 view .LVU413 + 1257 .loc 1 1292 11 is_stmt 0 view .LVU414 + 1258 00e4 436A ldr r3, [r0, #36] + 1259 .LVL84: + 1260 .loc 1 1292 23 view .LVU415 + 1261 00e6 43F40013 orr r3, r3, #2097152 + 1262 00ea 4362 str r3, [r0, #36] +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1263 .loc 1 1294 7 is_stmt 1 view .LVU416 + 1264 .loc 1 1294 14 is_stmt 0 view .LVU417 + 1265 00ec 0120 movs r0, #1 + 1266 .LVL85: + ARM GAS /tmp/ccqPwHQi.s page 50 + + + 1267 .loc 1 1294 14 view .LVU418 + 1268 00ee 04E0 b .L98 + 1269 .LVL86: + 1270 .L95: +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 1271 .loc 1 1300 5 is_stmt 1 view .LVU419 + 1272 .loc 1 1300 9 is_stmt 0 view .LVU420 + 1273 00f0 436A ldr r3, [r0, #36] + 1274 .LVL87: + 1275 .loc 1 1300 21 view .LVU421 + 1276 00f2 43F48023 orr r3, r3, #262144 + 1277 00f6 4362 str r3, [r0, #36] +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1278 .loc 1 1302 5 is_stmt 1 view .LVU422 + 1279 .loc 1 1302 12 is_stmt 0 view .LVU423 + 1280 00f8 0120 movs r0, #1 + 1281 .LVL88: + 1282 .L98: +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1283 .loc 1 1304 1 view .LVU424 + 1284 00fa 30BD pop {r4, r5, pc} + 1285 .cfi_endproc + 1286 .LFE140: + 1288 .section .text.HAL_CAN_AbortTxRequest,"ax",%progbits + 1289 .align 1 + 1290 .global HAL_CAN_AbortTxRequest + 1291 .syntax unified + 1292 .thumb + 1293 .thumb_func + 1295 HAL_CAN_AbortTxRequest: + 1296 .LVL89: + 1297 .LFB141: +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Abort transmission requests +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param TxMailboxes List of the Tx Mailboxes to abort. +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be any combination of @arg CAN_Tx_Mailboxes. +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1298 .loc 1 1315 1 is_stmt 1 view -0 + 1299 .cfi_startproc + 1300 @ args = 0, pretend = 0, frame = 0 + 1301 @ frame_needed = 0, uses_anonymous_args = 0 + 1302 @ link register save eliminated. +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1303 .loc 1 1316 3 view .LVU426 + ARM GAS /tmp/ccqPwHQi.s page 51 + + + 1304 .loc 1 1316 24 is_stmt 0 view .LVU427 + 1305 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 1306 .LVL90: +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + 1307 .loc 1 1319 3 is_stmt 1 view .LVU428 +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1308 .loc 1 1321 3 view .LVU429 + 1309 .loc 1 1321 38 is_stmt 0 view .LVU430 + 1310 0004 013B subs r3, r3, #1 + 1311 .LVL91: + 1312 .loc 1 1321 38 view .LVU431 + 1313 0006 DBB2 uxtb r3, r3 + 1314 .loc 1 1321 6 view .LVU432 + 1315 0008 012B cmp r3, #1 + 1316 000a 05D9 bls .L110 +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 0 */ +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Add cancellation request for Tx Mailbox 0 */ +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 1 */ +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Add cancellation request for Tx Mailbox 1 */ +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 2 */ +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Add cancellation request for Tx Mailbox 2 */ +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 1317 .loc 1 1351 5 is_stmt 1 view .LVU433 + 1318 .loc 1 1351 9 is_stmt 0 view .LVU434 + 1319 000c 436A ldr r3, [r0, #36] + 1320 .loc 1 1351 21 view .LVU435 + 1321 000e 43F48023 orr r3, r3, #262144 + 1322 0012 4362 str r3, [r0, #36] +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1323 .loc 1 1353 5 is_stmt 1 view .LVU436 + ARM GAS /tmp/ccqPwHQi.s page 52 + + + 1324 .loc 1 1353 12 is_stmt 0 view .LVU437 + 1325 0014 0120 movs r0, #1 + 1326 .LVL92: +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1327 .loc 1 1355 1 view .LVU438 + 1328 0016 7047 bx lr + 1329 .LVL93: + 1330 .L110: +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1331 .loc 1 1325 5 is_stmt 1 view .LVU439 +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1332 .loc 1 1325 8 is_stmt 0 view .LVU440 + 1333 0018 11F0010F tst r1, #1 + 1334 001c 04D0 beq .L106 +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1335 .loc 1 1328 7 is_stmt 1 view .LVU441 + 1336 001e 0268 ldr r2, [r0] + 1337 0020 9368 ldr r3, [r2, #8] + 1338 0022 43F08003 orr r3, r3, #128 + 1339 0026 9360 str r3, [r2, #8] + 1340 .L106: +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1341 .loc 1 1332 5 view .LVU442 +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1342 .loc 1 1332 8 is_stmt 0 view .LVU443 + 1343 0028 11F0020F tst r1, #2 + 1344 002c 04D0 beq .L107 +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1345 .loc 1 1335 7 is_stmt 1 view .LVU444 + 1346 002e 0268 ldr r2, [r0] + 1347 0030 9368 ldr r3, [r2, #8] + 1348 0032 43F40043 orr r3, r3, #32768 + 1349 0036 9360 str r3, [r2, #8] + 1350 .L107: +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1351 .loc 1 1339 5 view .LVU445 +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1352 .loc 1 1339 8 is_stmt 0 view .LVU446 + 1353 0038 11F0040F tst r1, #4 + 1354 003c 04D0 beq .L108 +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1355 .loc 1 1342 7 is_stmt 1 view .LVU447 + 1356 003e 0268 ldr r2, [r0] + 1357 0040 9368 ldr r3, [r2, #8] + 1358 0042 43F40003 orr r3, r3, #8388608 + 1359 0046 9360 str r3, [r2, #8] + 1360 .L108: +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1361 .loc 1 1346 5 view .LVU448 +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1362 .loc 1 1346 12 is_stmt 0 view .LVU449 + 1363 0048 0020 movs r0, #0 + 1364 .LVL94: +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1365 .loc 1 1346 12 view .LVU450 + 1366 004a 7047 bx lr + ARM GAS /tmp/ccqPwHQi.s page 53 + + + 1367 .cfi_endproc + 1368 .LFE141: + 1370 .section .text.HAL_CAN_GetTxMailboxesFreeLevel,"ax",%progbits + 1371 .align 1 + 1372 .global HAL_CAN_GetTxMailboxesFreeLevel + 1373 .syntax unified + 1374 .thumb + 1375 .thumb_func + 1377 HAL_CAN_GetTxMailboxesFreeLevel: + 1378 .LVL95: + 1379 .LFB142: +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Number of free Tx Mailboxes. +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1380 .loc 1 1364 1 is_stmt 1 view -0 + 1381 .cfi_startproc + 1382 @ args = 0, pretend = 0, frame = 0 + 1383 @ frame_needed = 0, uses_anonymous_args = 0 + 1384 @ link register save eliminated. +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t freelevel = 0U; + 1385 .loc 1 1365 3 view .LVU452 +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1386 .loc 1 1366 3 view .LVU453 + 1387 .loc 1 1366 24 is_stmt 0 view .LVU454 + 1388 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 1389 .LVL96: +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1390 .loc 1 1368 3 is_stmt 1 view .LVU455 + 1391 .loc 1 1368 38 is_stmt 0 view .LVU456 + 1392 0004 013B subs r3, r3, #1 + 1393 .LVL97: + 1394 .loc 1 1368 38 view .LVU457 + 1395 0006 DBB2 uxtb r3, r3 + 1396 .loc 1 1368 6 view .LVU458 + 1397 0008 012B cmp r3, #1 + 1398 000a 01D9 bls .L117 +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1399 .loc 1 1365 12 view .LVU459 + 1400 000c 0020 movs r0, #0 + 1401 .LVL98: +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 0 status */ +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** freelevel++; +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 1 status */ +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + ARM GAS /tmp/ccqPwHQi.s page 54 + + +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** freelevel++; +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 2 status */ +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** freelevel++; +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return Tx Mailboxes free level */ +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return freelevel; + 1402 .loc 1 1391 3 is_stmt 1 view .LVU460 + 1403 .L111: +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1404 .loc 1 1392 1 is_stmt 0 view .LVU461 + 1405 000e 7047 bx lr + 1406 .LVL99: + 1407 .L117: +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1408 .loc 1 1372 5 is_stmt 1 view .LVU462 +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1409 .loc 1 1372 14 is_stmt 0 view .LVU463 + 1410 0010 0368 ldr r3, [r0] +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1411 .loc 1 1372 24 view .LVU464 + 1412 0012 9868 ldr r0, [r3, #8] + 1413 .LVL100: +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1414 .loc 1 1372 8 view .LVU465 + 1415 0014 10F08060 ands r0, r0, #67108864 + 1416 0018 00D0 beq .L113 +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1417 .loc 1 1374 16 view .LVU466 + 1418 001a 0120 movs r0, #1 + 1419 .L113: + 1420 .LVL101: +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1421 .loc 1 1378 5 is_stmt 1 view .LVU467 +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1422 .loc 1 1378 24 is_stmt 0 view .LVU468 + 1423 001c 9A68 ldr r2, [r3, #8] +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1424 .loc 1 1378 8 view .LVU469 + 1425 001e 12F0006F tst r2, #134217728 + 1426 0022 00D0 beq .L114 +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1427 .loc 1 1380 7 is_stmt 1 view .LVU470 +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1428 .loc 1 1380 16 is_stmt 0 view .LVU471 + 1429 0024 0130 adds r0, r0, #1 + 1430 .LVL102: + 1431 .L114: +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1432 .loc 1 1384 5 is_stmt 1 view .LVU472 +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + ARM GAS /tmp/ccqPwHQi.s page 55 + + + 1433 .loc 1 1384 24 is_stmt 0 view .LVU473 + 1434 0026 9B68 ldr r3, [r3, #8] +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1435 .loc 1 1384 8 view .LVU474 + 1436 0028 13F0805F tst r3, #268435456 + 1437 002c EFD0 beq .L111 +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1438 .loc 1 1386 7 is_stmt 1 view .LVU475 +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1439 .loc 1 1386 16 is_stmt 0 view .LVU476 + 1440 002e 0130 adds r0, r0, #1 + 1441 .LVL103: +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1442 .loc 1 1386 16 view .LVU477 + 1443 0030 7047 bx lr + 1444 .cfi_endproc + 1445 .LFE142: + 1447 .section .text.HAL_CAN_IsTxMessagePending,"ax",%progbits + 1448 .align 1 + 1449 .global HAL_CAN_IsTxMessagePending + 1450 .syntax unified + 1451 .thumb + 1452 .thumb_func + 1454 HAL_CAN_IsTxMessagePending: + 1455 .LVL104: + 1456 .LFB143: +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Check if a transmission request is pending on the selected Tx +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * Mailboxes. +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param TxMailboxes List of Tx Mailboxes to check. +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be any combination of @arg CAN_Tx_Mailboxes. +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Status +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * - 0 : No pending transmission request on any selected Tx Mailboxes. +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * - 1 : Pending transmission request on at least one of the selected +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * Tx Mailbox. +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1457 .loc 1 1407 1 is_stmt 1 view -0 + 1458 .cfi_startproc + 1459 @ args = 0, pretend = 0, frame = 0 + 1460 @ frame_needed = 0, uses_anonymous_args = 0 + 1461 @ link register save eliminated. +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t status = 0U; + 1462 .loc 1 1408 3 view .LVU479 +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1463 .loc 1 1409 3 view .LVU480 + 1464 .loc 1 1409 24 is_stmt 0 view .LVU481 + 1465 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 1466 .LVL105: +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + 1467 .loc 1 1412 3 is_stmt 1 view .LVU482 + ARM GAS /tmp/ccqPwHQi.s page 56 + + +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1468 .loc 1 1414 3 view .LVU483 + 1469 .loc 1 1414 38 is_stmt 0 view .LVU484 + 1470 0004 013B subs r3, r3, #1 + 1471 .LVL106: + 1472 .loc 1 1414 38 view .LVU485 + 1473 0006 DBB2 uxtb r3, r3 + 1474 .loc 1 1414 6 view .LVU486 + 1475 0008 012B cmp r3, #1 + 1476 000a 01D9 bls .L122 +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1477 .loc 1 1408 12 view .LVU487 + 1478 000c 0020 movs r0, #0 + 1479 .LVL107: +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1480 .loc 1 1408 12 view .LVU488 + 1481 000e 7047 bx lr + 1482 .LVL108: + 1483 .L122: +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check pending transmission request on the selected Tx Mailboxes */ +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_P + 1484 .loc 1 1418 5 is_stmt 1 view .LVU489 + 1485 .loc 1 1418 14 is_stmt 0 view .LVU490 + 1486 0010 0368 ldr r3, [r0] + 1487 .loc 1 1418 24 view .LVU491 + 1488 0012 9B68 ldr r3, [r3, #8] + 1489 .loc 1 1418 30 view .LVU492 + 1490 0014 03EA8163 and r3, r3, r1, lsl #26 + 1491 .loc 1 1418 8 view .LVU493 + 1492 0018 B3EB816F cmp r3, r1, lsl #26 + 1493 001c 01D0 beq .L123 +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = 1U; + 1494 .loc 1 1420 14 view .LVU494 + 1495 001e 0120 movs r0, #1 + 1496 .LVL109: +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return status */ +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 1497 .loc 1 1425 3 is_stmt 1 view .LVU495 +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1498 .loc 1 1426 1 is_stmt 0 view .LVU496 + 1499 0020 7047 bx lr + 1500 .LVL110: + 1501 .L123: +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1502 .loc 1 1408 12 view .LVU497 + 1503 0022 0020 movs r0, #0 + 1504 .LVL111: +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1505 .loc 1 1408 12 view .LVU498 + 1506 0024 7047 bx lr + ARM GAS /tmp/ccqPwHQi.s page 57 + + + 1507 .cfi_endproc + 1508 .LFE143: + 1510 .section .text.HAL_CAN_GetTxTimestamp,"ax",%progbits + 1511 .align 1 + 1512 .global HAL_CAN_GetTxTimestamp + 1513 .syntax unified + 1514 .thumb + 1515 .thumb_func + 1517 HAL_CAN_GetTxTimestamp: + 1518 .LVL112: + 1519 .LFB144: +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return timestamp of Tx message sent, if time triggered communication +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** mode is enabled. +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param TxMailbox Tx Mailbox where the timestamp of message sent will be +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * read. +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be one value of @arg CAN_Tx_Mailboxes. +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Timestamp of message sent from Tx Mailbox. +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1520 .loc 1 1439 1 is_stmt 1 view -0 + 1521 .cfi_startproc + 1522 @ args = 0, pretend = 0, frame = 0 + 1523 @ frame_needed = 0, uses_anonymous_args = 0 + 1524 @ link register save eliminated. +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t timestamp = 0U; + 1525 .loc 1 1440 3 view .LVU500 +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t transmitmailbox; + 1526 .loc 1 1441 3 view .LVU501 +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1527 .loc 1 1442 3 view .LVU502 + 1528 .loc 1 1442 24 is_stmt 0 view .LVU503 + 1529 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 1530 .LVL113: +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + 1531 .loc 1 1445 3 is_stmt 1 view .LVU504 +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1532 .loc 1 1447 3 view .LVU505 + 1533 .loc 1 1447 38 is_stmt 0 view .LVU506 + 1534 0004 013B subs r3, r3, #1 + 1535 .LVL114: + 1536 .loc 1 1447 38 view .LVU507 + 1537 0006 DBB2 uxtb r3, r3 + 1538 .loc 1 1447 6 view .LVU508 + 1539 0008 012B cmp r3, #1 + 1540 000a 01D9 bls .L127 +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t transmitmailbox; + 1541 .loc 1 1440 12 view .LVU509 + 1542 000c 0020 movs r0, #0 + 1543 .LVL115: + ARM GAS /tmp/ccqPwHQi.s page 58 + + +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Select the Tx mailbox */ +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** transmitmailbox = POSITION_VAL(TxMailbox); +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get timestamp */ +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TI +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return the timestamp */ +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return timestamp; + 1544 .loc 1 1458 3 is_stmt 1 view .LVU510 +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1545 .loc 1 1459 1 is_stmt 0 view .LVU511 + 1546 000e 7047 bx lr + 1547 .LVL116: + 1548 .L127: +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 1549 .loc 1 1451 5 is_stmt 1 view .LVU512 + 1550 .LBB4: + 1551 .LBI4: + 1552 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + ARM GAS /tmp/ccqPwHQi.s page 59 + + + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + ARM GAS /tmp/ccqPwHQi.s page 60 + + + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + ARM GAS /tmp/ccqPwHQi.s page 61 + + + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccqPwHQi.s page 62 + + + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccqPwHQi.s page 63 + + + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + ARM GAS /tmp/ccqPwHQi.s page 64 + + + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccqPwHQi.s page 65 + + + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccqPwHQi.s page 66 + + + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + ARM GAS /tmp/ccqPwHQi.s page 67 + + + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccqPwHQi.s page 68 + + + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + ARM GAS /tmp/ccqPwHQi.s page 69 + + + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + ARM GAS /tmp/ccqPwHQi.s page 70 + + + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + ARM GAS /tmp/ccqPwHQi.s page 71 + + + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccqPwHQi.s page 72 + + + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + ARM GAS /tmp/ccqPwHQi.s page 73 + + + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + ARM GAS /tmp/ccqPwHQi.s page 74 + + + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccqPwHQi.s page 75 + + + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 1553 .loc 2 981 31 view .LVU513 + 1554 .LBB5: + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 1555 .loc 2 983 3 view .LVU514 + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 1556 .loc 2 988 4 view .LVU515 + 1557 .syntax unified + 1558 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1559 0010 91FAA1F1 rbit r1, r1 + 1560 @ 0 "" 2 + 1561 .LVL117: + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + ARM GAS /tmp/ccqPwHQi.s page 76 + + + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 1562 .loc 2 1001 3 view .LVU516 + 1563 .loc 2 1001 3 is_stmt 0 view .LVU517 + 1564 .thumb + 1565 .syntax unified + 1566 .LBE5: + 1567 .LBE4: +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 1568 .loc 1 1451 21 view .LVU518 + 1569 0014 B1FA81F1 clz r1, r1 + 1570 .LVL118: +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1571 .loc 1 1454 5 is_stmt 1 view .LVU519 +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1572 .loc 1 1454 22 is_stmt 0 view .LVU520 + 1573 0018 0368 ldr r3, [r0] +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1574 .loc 1 1454 61 view .LVU521 + 1575 001a 1831 adds r1, r1, #24 + 1576 .LVL119: +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1577 .loc 1 1454 61 view .LVU522 + 1578 001c 03EB0113 add r3, r3, r1, lsl #4 + 1579 0020 5868 ldr r0, [r3, #4] + 1580 .LVL120: +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1581 .loc 1 1454 85 view .LVU523 + 1582 0022 000C lsrs r0, r0, #16 + 1583 .LVL121: +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1584 .loc 1 1454 85 view .LVU524 + 1585 0024 7047 bx lr + 1586 .cfi_endproc + 1587 .LFE144: + 1589 .section .text.HAL_CAN_GetRxMessage,"ax",%progbits + 1590 .align 1 + 1591 .global HAL_CAN_GetRxMessage + 1592 .syntax unified + 1593 .thumb + 1594 .thumb_func + 1596 HAL_CAN_GetRxMessage: + 1597 .LVL122: + 1598 .LFB145: +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param RxFifo Fifo number of the received message to be read. +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be a value of @arg CAN_receive_FIFO_number. +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * of the Rx frame will be stored. + ARM GAS /tmp/ccqPwHQi.s page 77 + + +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param aData array where the payload of the Rx frame will be stored. +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDe +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1599 .loc 1 1473 1 is_stmt 1 view -0 + 1600 .cfi_startproc + 1601 @ args = 0, pretend = 0, frame = 0 + 1602 @ frame_needed = 0, uses_anonymous_args = 0 + 1603 @ link register save eliminated. +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1604 .loc 1 1474 3 view .LVU526 + 1605 .loc 1 1474 24 is_stmt 0 view .LVU527 + 1606 0000 90F820C0 ldrb ip, [r0, #32] @ zero_extendqisi2 + 1607 .LVL123: +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_RX_FIFO(RxFifo)); + 1608 .loc 1 1476 3 is_stmt 1 view .LVU528 +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1609 .loc 1 1478 3 view .LVU529 + 1610 .loc 1 1478 38 is_stmt 0 view .LVU530 + 1611 0004 0CF1FF3C add ip, ip, #-1 + 1612 .LVL124: + 1613 .loc 1 1478 38 view .LVU531 + 1614 0008 5FFA8CFC uxtb ip, ip + 1615 .loc 1 1478 6 view .LVU532 + 1616 000c BCF1010F cmp ip, #1 + 1617 0010 00F29580 bhi .L129 +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1618 .loc 1 1473 1 view .LVU533 + 1619 0014 30B4 push {r4, r5} + 1620 .cfi_def_cfa_offset 8 + 1621 .cfi_offset 4, -8 + 1622 .cfi_offset 5, -4 +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the Rx FIFO */ +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 1623 .loc 1 1482 5 is_stmt 1 view .LVU534 + 1624 .loc 1 1482 8 is_stmt 0 view .LVU535 + 1625 0016 51B9 cbnz r1, .L130 +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check that the Rx FIFO 0 is not empty */ +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + 1626 .loc 1 1485 7 is_stmt 1 view .LVU536 + 1627 .loc 1 1485 16 is_stmt 0 view .LVU537 + 1628 0018 0468 ldr r4, [r0] + 1629 .loc 1 1485 26 view .LVU538 + 1630 001a E468 ldr r4, [r4, #12] + 1631 .loc 1 1485 10 view .LVU539 + 1632 001c 14F0030F tst r4, #3 + 1633 0020 10D1 bne .L131 +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 1634 .loc 1 1488 9 is_stmt 1 view .LVU540 + ARM GAS /tmp/ccqPwHQi.s page 78 + + + 1635 .loc 1 1488 13 is_stmt 0 view .LVU541 + 1636 0022 436A ldr r3, [r0, #36] + 1637 .LVL125: + 1638 .loc 1 1488 25 view .LVU542 + 1639 0024 43F40013 orr r3, r3, #2097152 + 1640 0028 4362 str r3, [r0, #36] +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1641 .loc 1 1490 9 is_stmt 1 view .LVU543 + 1642 .loc 1 1490 16 is_stmt 0 view .LVU544 + 1643 002a 0120 movs r0, #1 + 1644 .LVL126: + 1645 .loc 1 1490 16 view .LVU545 + 1646 002c 77E0 b .L132 + 1647 .LVL127: + 1648 .L130: +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else /* Rx element is assigned to Rx FIFO 1 */ +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check that the Rx FIFO 1 is not empty */ +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + 1649 .loc 1 1496 7 is_stmt 1 view .LVU546 + 1650 .loc 1 1496 16 is_stmt 0 view .LVU547 + 1651 002e 0468 ldr r4, [r0] + 1652 .loc 1 1496 26 view .LVU548 + 1653 0030 2469 ldr r4, [r4, #16] + 1654 .loc 1 1496 10 view .LVU549 + 1655 0032 14F0030F tst r4, #3 + 1656 0036 05D1 bne .L131 +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 1657 .loc 1 1499 9 is_stmt 1 view .LVU550 + 1658 .loc 1 1499 13 is_stmt 0 view .LVU551 + 1659 0038 436A ldr r3, [r0, #36] + 1660 .LVL128: + 1661 .loc 1 1499 25 view .LVU552 + 1662 003a 43F40013 orr r3, r3, #2097152 + 1663 003e 4362 str r3, [r0, #36] +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1664 .loc 1 1501 9 is_stmt 1 view .LVU553 + 1665 .loc 1 1501 16 is_stmt 0 view .LVU554 + 1666 0040 0120 movs r0, #1 + 1667 .LVL129: + 1668 .loc 1 1501 16 view .LVU555 + 1669 0042 6CE0 b .L132 + 1670 .LVL130: + 1671 .L131: +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get the header */ +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + 1672 .loc 1 1506 5 is_stmt 1 view .LVU556 + 1673 .loc 1 1506 71 is_stmt 0 view .LVU557 + ARM GAS /tmp/ccqPwHQi.s page 79 + + + 1674 0044 01F11B04 add r4, r1, #27 + 1675 0048 2401 lsls r4, r4, #4 + 1676 004a 0568 ldr r5, [r0] + 1677 004c 2C59 ldr r4, [r5, r4] + 1678 .loc 1 1506 33 view .LVU558 + 1679 004e 04F00404 and r4, r4, #4 + 1680 .loc 1 1506 18 view .LVU559 + 1681 0052 9460 str r4, [r2, #8] +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pHeader->IDE == CAN_ID_STD) + 1682 .loc 1 1507 5 is_stmt 1 view .LVU560 + 1683 .loc 1 1507 8 is_stmt 0 view .LVU561 + 1684 0054 002C cmp r4, #0 + 1685 0056 64D1 bne .L133 +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_ + 1686 .loc 1 1509 7 is_stmt 1 view .LVU562 + 1687 .loc 1 1509 77 is_stmt 0 view .LVU563 + 1688 0058 01F11B04 add r4, r1, #27 + 1689 005c 2401 lsls r4, r4, #4 + 1690 005e 0568 ldr r5, [r0] + 1691 0060 2C59 ldr r4, [r5, r4] + 1692 .loc 1 1509 83 view .LVU564 + 1693 0062 640D lsrs r4, r4, #21 + 1694 .loc 1 1509 22 view .LVU565 + 1695 0064 1460 str r4, [r2] + 1696 .L134: +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + 1697 .loc 1 1515 5 is_stmt 1 view .LVU566 + 1698 .loc 1 1515 40 is_stmt 0 view .LVU567 + 1699 0066 0468 ldr r4, [r0] + 1700 .loc 1 1515 72 view .LVU568 + 1701 0068 01F11B0C add ip, r1, #27 + 1702 006c 4FEA0C1C lsl ip, ip, #4 + 1703 0070 54F80C40 ldr r4, [r4, ip] + 1704 .loc 1 1515 34 view .LVU569 + 1705 0074 04F00204 and r4, r4, #2 + 1706 .loc 1 1515 18 view .LVU570 + 1707 0078 D460 str r4, [r2, #12] +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos + 1708 .loc 1 1516 5 is_stmt 1 view .LVU571 + 1709 .loc 1 1516 41 is_stmt 0 view .LVU572 + 1710 007a 0468 ldr r4, [r0] + 1711 .loc 1 1516 73 view .LVU573 + 1712 007c 6444 add r4, r4, ip + 1713 007e 6468 ldr r4, [r4, #4] + 1714 .loc 1 1516 80 view .LVU574 + 1715 0080 04F00F04 and r4, r4, #15 + 1716 .loc 1 1516 18 view .LVU575 + 1717 0084 1461 str r4, [r2, #16] +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_ + 1718 .loc 1 1517 5 is_stmt 1 view .LVU576 + 1719 .loc 1 1517 54 is_stmt 0 view .LVU577 + ARM GAS /tmp/ccqPwHQi.s page 80 + + + 1720 0086 0468 ldr r4, [r0] + 1721 .loc 1 1517 86 view .LVU578 + 1722 0088 6444 add r4, r4, ip + 1723 008a 6468 ldr r4, [r4, #4] + 1724 .loc 1 1517 93 view .LVU579 + 1725 008c C4F30724 ubfx r4, r4, #8, #8 + 1726 .loc 1 1517 31 view .LVU580 + 1727 0090 9461 str r4, [r2, #24] +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_ + 1728 .loc 1 1518 5 is_stmt 1 view .LVU581 + 1729 .loc 1 1518 48 is_stmt 0 view .LVU582 + 1730 0092 0468 ldr r4, [r0] + 1731 .loc 1 1518 80 view .LVU583 + 1732 0094 6444 add r4, r4, ip + 1733 0096 6468 ldr r4, [r4, #4] + 1734 .loc 1 1518 87 view .LVU584 + 1735 0098 240C lsrs r4, r4, #16 + 1736 .loc 1 1518 24 view .LVU585 + 1737 009a 5461 str r4, [r2, #20] +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get the data */ +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R + 1738 .loc 1 1521 5 is_stmt 1 view .LVU586 + 1739 .loc 1 1521 49 is_stmt 0 view .LVU587 + 1740 009c 0268 ldr r2, [r0] + 1741 .LVL131: + 1742 .loc 1 1521 81 view .LVU588 + 1743 009e 02EB0112 add r2, r2, r1, lsl #4 + 1744 00a2 D2F8B821 ldr r2, [r2, #440] + 1745 .loc 1 1521 14 view .LVU589 + 1746 00a6 1A70 strb r2, [r3] +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R + 1747 .loc 1 1522 5 is_stmt 1 view .LVU590 + 1748 .loc 1 1522 49 is_stmt 0 view .LVU591 + 1749 00a8 0268 ldr r2, [r0] + 1750 .loc 1 1522 81 view .LVU592 + 1751 00aa 02EB0112 add r2, r2, r1, lsl #4 + 1752 00ae D2F8B821 ldr r2, [r2, #440] + 1753 .loc 1 1522 16 view .LVU593 + 1754 00b2 C2F30722 ubfx r2, r2, #8, #8 + 1755 .loc 1 1522 14 view .LVU594 + 1756 00b6 5A70 strb r2, [r3, #1] +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R + 1757 .loc 1 1523 5 is_stmt 1 view .LVU595 + 1758 .loc 1 1523 49 is_stmt 0 view .LVU596 + 1759 00b8 0268 ldr r2, [r0] + 1760 .loc 1 1523 81 view .LVU597 + 1761 00ba 02EB0112 add r2, r2, r1, lsl #4 + 1762 00be D2F8B821 ldr r2, [r2, #440] + 1763 .loc 1 1523 16 view .LVU598 + 1764 00c2 C2F30742 ubfx r2, r2, #16, #8 + 1765 .loc 1 1523 14 view .LVU599 + 1766 00c6 9A70 strb r2, [r3, #2] +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R + 1767 .loc 1 1524 5 is_stmt 1 view .LVU600 + 1768 .loc 1 1524 49 is_stmt 0 view .LVU601 + 1769 00c8 0268 ldr r2, [r0] + ARM GAS /tmp/ccqPwHQi.s page 81 + + + 1770 .loc 1 1524 81 view .LVU602 + 1771 00ca 02EB0112 add r2, r2, r1, lsl #4 + 1772 00ce D2F8B821 ldr r2, [r2, #440] + 1773 .loc 1 1524 16 view .LVU603 + 1774 00d2 120E lsrs r2, r2, #24 + 1775 .loc 1 1524 14 view .LVU604 + 1776 00d4 DA70 strb r2, [r3, #3] +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R + 1777 .loc 1 1525 5 is_stmt 1 view .LVU605 + 1778 .loc 1 1525 49 is_stmt 0 view .LVU606 + 1779 00d6 0268 ldr r2, [r0] + 1780 .loc 1 1525 81 view .LVU607 + 1781 00d8 02EB0112 add r2, r2, r1, lsl #4 + 1782 00dc D2F8BC21 ldr r2, [r2, #444] + 1783 .loc 1 1525 14 view .LVU608 + 1784 00e0 1A71 strb r2, [r3, #4] +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R + 1785 .loc 1 1526 5 is_stmt 1 view .LVU609 + 1786 .loc 1 1526 49 is_stmt 0 view .LVU610 + 1787 00e2 0268 ldr r2, [r0] + 1788 .loc 1 1526 81 view .LVU611 + 1789 00e4 02EB0112 add r2, r2, r1, lsl #4 + 1790 00e8 D2F8BC21 ldr r2, [r2, #444] + 1791 .loc 1 1526 16 view .LVU612 + 1792 00ec C2F30722 ubfx r2, r2, #8, #8 + 1793 .loc 1 1526 14 view .LVU613 + 1794 00f0 5A71 strb r2, [r3, #5] +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R + 1795 .loc 1 1527 5 is_stmt 1 view .LVU614 + 1796 .loc 1 1527 49 is_stmt 0 view .LVU615 + 1797 00f2 0268 ldr r2, [r0] + 1798 .loc 1 1527 81 view .LVU616 + 1799 00f4 02EB0112 add r2, r2, r1, lsl #4 + 1800 00f8 D2F8BC21 ldr r2, [r2, #444] + 1801 .loc 1 1527 16 view .LVU617 + 1802 00fc C2F30742 ubfx r2, r2, #16, #8 + 1803 .loc 1 1527 14 view .LVU618 + 1804 0100 9A71 strb r2, [r3, #6] +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R + 1805 .loc 1 1528 5 is_stmt 1 view .LVU619 + 1806 .loc 1 1528 49 is_stmt 0 view .LVU620 + 1807 0102 0268 ldr r2, [r0] + 1808 .loc 1 1528 81 view .LVU621 + 1809 0104 02EB0112 add r2, r2, r1, lsl #4 + 1810 0108 D2F8BC21 ldr r2, [r2, #444] + 1811 .loc 1 1528 16 view .LVU622 + 1812 010c 120E lsrs r2, r2, #24 + 1813 .loc 1 1528 14 view .LVU623 + 1814 010e DA71 strb r2, [r3, #7] +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Release the FIFO */ +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 1815 .loc 1 1531 5 is_stmt 1 view .LVU624 + 1816 .loc 1 1531 8 is_stmt 0 view .LVU625 + 1817 0110 79B9 cbnz r1, .L135 +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Release RX FIFO 0 */ + ARM GAS /tmp/ccqPwHQi.s page 82 + + +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + 1818 .loc 1 1534 7 is_stmt 1 view .LVU626 + 1819 0112 0268 ldr r2, [r0] + 1820 0114 D368 ldr r3, [r2, #12] + 1821 .LVL132: + 1822 .loc 1 1534 7 is_stmt 0 view .LVU627 + 1823 0116 43F02003 orr r3, r3, #32 + 1824 011a D360 str r3, [r2, #12] + 1825 .L136: +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else /* Rx element is assigned to Rx FIFO 1 */ +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Release RX FIFO 1 */ +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 1826 .loc 1 1543 5 is_stmt 1 view .LVU628 + 1827 .loc 1 1543 12 is_stmt 0 view .LVU629 + 1828 011c 0020 movs r0, #0 + 1829 .LVL133: + 1830 .L132: +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1831 .loc 1 1552 1 view .LVU630 + 1832 011e 30BC pop {r4, r5} + 1833 .cfi_remember_state + 1834 .cfi_restore 5 + 1835 .cfi_restore 4 + 1836 .cfi_def_cfa_offset 0 + 1837 0120 7047 bx lr + 1838 .LVL134: + 1839 .L133: + 1840 .cfi_restore_state +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1841 .loc 1 1513 7 is_stmt 1 view .LVU631 +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1842 .loc 1 1513 95 is_stmt 0 view .LVU632 + 1843 0122 01F11B04 add r4, r1, #27 + 1844 0126 2401 lsls r4, r4, #4 + 1845 0128 0568 ldr r5, [r0] + 1846 012a 2C59 ldr r4, [r5, r4] +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1847 .loc 1 1513 101 view .LVU633 + 1848 012c E408 lsrs r4, r4, #3 +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1849 .loc 1 1513 22 view .LVU634 + 1850 012e 5460 str r4, [r2, #4] + 1851 0130 99E7 b .L134 + ARM GAS /tmp/ccqPwHQi.s page 83 + + + 1852 .LVL135: + 1853 .L135: +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1854 .loc 1 1539 7 is_stmt 1 view .LVU635 + 1855 0132 0268 ldr r2, [r0] + 1856 0134 1369 ldr r3, [r2, #16] + 1857 .LVL136: +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1858 .loc 1 1539 7 is_stmt 0 view .LVU636 + 1859 0136 43F02003 orr r3, r3, #32 + 1860 013a 1361 str r3, [r2, #16] + 1861 013c EEE7 b .L136 + 1862 .LVL137: + 1863 .L129: + 1864 .cfi_def_cfa_offset 0 + 1865 .cfi_restore 4 + 1866 .cfi_restore 5 +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 1867 .loc 1 1548 5 is_stmt 1 view .LVU637 +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 1868 .loc 1 1548 9 is_stmt 0 view .LVU638 + 1869 013e 436A ldr r3, [r0, #36] + 1870 .LVL138: +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 1871 .loc 1 1548 21 view .LVU639 + 1872 0140 43F48023 orr r3, r3, #262144 + 1873 0144 4362 str r3, [r0, #36] +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1874 .loc 1 1550 5 is_stmt 1 view .LVU640 +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1875 .loc 1 1550 12 is_stmt 0 view .LVU641 + 1876 0146 0120 movs r0, #1 + 1877 .LVL139: + 1878 .loc 1 1552 1 view .LVU642 + 1879 0148 7047 bx lr + 1880 .cfi_endproc + 1881 .LFE145: + 1883 .section .text.HAL_CAN_GetRxFifoFillLevel,"ax",%progbits + 1884 .align 1 + 1885 .global HAL_CAN_GetRxFifoFillLevel + 1886 .syntax unified + 1887 .thumb + 1888 .thumb_func + 1890 HAL_CAN_GetRxFifoFillLevel: + 1891 .LVL140: + 1892 .LFB146: +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return Rx FIFO fill level. +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param RxFifo Rx FIFO. +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be a value of @arg CAN_receive_FIFO_number. +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Number of messages available in Rx FIFO. +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + ARM GAS /tmp/ccqPwHQi.s page 84 + + + 1893 .loc 1 1563 1 is_stmt 1 view -0 + 1894 .cfi_startproc + 1895 @ args = 0, pretend = 0, frame = 0 + 1896 @ frame_needed = 0, uses_anonymous_args = 0 + 1897 @ link register save eliminated. +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t filllevel = 0U; + 1898 .loc 1 1564 3 view .LVU644 +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1899 .loc 1 1565 3 view .LVU645 + 1900 .loc 1 1565 24 is_stmt 0 view .LVU646 + 1901 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 1902 .LVL141: +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_RX_FIFO(RxFifo)); + 1903 .loc 1 1568 3 is_stmt 1 view .LVU647 +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1904 .loc 1 1570 3 view .LVU648 + 1905 .loc 1 1570 38 is_stmt 0 view .LVU649 + 1906 0004 013B subs r3, r3, #1 + 1907 .LVL142: + 1908 .loc 1 1570 38 view .LVU650 + 1909 0006 DBB2 uxtb r3, r3 + 1910 .loc 1 1570 6 view .LVU651 + 1911 0008 012B cmp r3, #1 + 1912 000a 01D9 bls .L145 +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1913 .loc 1 1564 12 view .LVU652 + 1914 000c 0020 movs r0, #0 + 1915 .LVL143: +1571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (RxFifo == CAN_RX_FIFO0) +1574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else /* RxFifo == CAN_RX_FIFO1 */ +1578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return Rx FIFO fill level */ +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return filllevel; + 1916 .loc 1 1584 3 is_stmt 1 view .LVU653 +1585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1917 .loc 1 1585 1 is_stmt 0 view .LVU654 + 1918 000e 7047 bx lr + 1919 .LVL144: + 1920 .L145: +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1921 .loc 1 1573 5 is_stmt 1 view .LVU655 +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1922 .loc 1 1573 8 is_stmt 0 view .LVU656 + 1923 0010 21B9 cbnz r1, .L143 +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + ARM GAS /tmp/ccqPwHQi.s page 85 + + + 1924 .loc 1 1575 7 is_stmt 1 view .LVU657 +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1925 .loc 1 1575 23 is_stmt 0 view .LVU658 + 1926 0012 0368 ldr r3, [r0] +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1927 .loc 1 1575 33 view .LVU659 + 1928 0014 D868 ldr r0, [r3, #12] + 1929 .LVL145: +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1930 .loc 1 1575 17 view .LVU660 + 1931 0016 00F00300 and r0, r0, #3 + 1932 .LVL146: +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1933 .loc 1 1575 17 view .LVU661 + 1934 001a 7047 bx lr + 1935 .LVL147: + 1936 .L143: +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1937 .loc 1 1579 7 is_stmt 1 view .LVU662 +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1938 .loc 1 1579 23 is_stmt 0 view .LVU663 + 1939 001c 0368 ldr r3, [r0] +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1940 .loc 1 1579 33 view .LVU664 + 1941 001e 1869 ldr r0, [r3, #16] + 1942 .LVL148: +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1943 .loc 1 1579 17 view .LVU665 + 1944 0020 00F00300 and r0, r0, #3 + 1945 .LVL149: +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1946 .loc 1 1579 17 view .LVU666 + 1947 0024 7047 bx lr + 1948 .cfi_endproc + 1949 .LFE146: + 1951 .section .text.HAL_CAN_ActivateNotification,"ax",%progbits + 1952 .align 1 + 1953 .global HAL_CAN_ActivateNotification + 1954 .syntax unified + 1955 .thumb + 1956 .thumb_func + 1958 HAL_CAN_ActivateNotification: + 1959 .LVL150: + 1960 .LFB147: +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group4 Interrupts management +1592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Interrupts management +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +1596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Interrupts management ##### +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +1598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] This section provides functions allowing to: + ARM GAS /tmp/ccqPwHQi.s page 86 + + +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_ActivateNotification : Enable interrupts +1600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_DeactivateNotification : Disable interrupts +1601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_IRQHandler : Handles CAN interrupt request +1602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim +1604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Enable interrupts. +1609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param ActiveITs indicates which interrupts will be enabled. +1612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be any combination of @arg CAN_Interrupts. +1613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +1616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1961 .loc 1 1616 1 is_stmt 1 view -0 + 1962 .cfi_startproc + 1963 @ args = 0, pretend = 0, frame = 0 + 1964 @ frame_needed = 0, uses_anonymous_args = 0 + 1965 @ link register save eliminated. +1617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1966 .loc 1 1617 3 view .LVU668 + 1967 .loc 1 1617 24 is_stmt 0 view .LVU669 + 1968 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 1969 .LVL151: +1618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_IT(ActiveITs)); + 1970 .loc 1 1620 3 is_stmt 1 view .LVU670 +1621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1971 .loc 1 1622 3 view .LVU671 + 1972 .loc 1 1622 38 is_stmt 0 view .LVU672 + 1973 0004 013B subs r3, r3, #1 + 1974 .LVL152: + 1975 .loc 1 1622 38 view .LVU673 + 1976 0006 DBB2 uxtb r3, r3 + 1977 .loc 1 1622 6 view .LVU674 + 1978 0008 012B cmp r3, #1 + 1979 000a 05D9 bls .L149 +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Enable the selected interrupts */ +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_ENABLE_IT(hcan, ActiveITs); +1627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 1980 .loc 1 1634 5 is_stmt 1 view .LVU675 + 1981 .loc 1 1634 9 is_stmt 0 view .LVU676 + ARM GAS /tmp/ccqPwHQi.s page 87 + + + 1982 000c 436A ldr r3, [r0, #36] + 1983 .loc 1 1634 21 view .LVU677 + 1984 000e 43F48023 orr r3, r3, #262144 + 1985 0012 4362 str r3, [r0, #36] +1635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1986 .loc 1 1636 5 is_stmt 1 view .LVU678 + 1987 .loc 1 1636 12 is_stmt 0 view .LVU679 + 1988 0014 0120 movs r0, #1 + 1989 .LVL153: +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1990 .loc 1 1638 1 view .LVU680 + 1991 0016 7047 bx lr + 1992 .LVL154: + 1993 .L149: +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 1994 .loc 1 1626 5 is_stmt 1 view .LVU681 + 1995 0018 0268 ldr r2, [r0] + 1996 001a 5369 ldr r3, [r2, #20] + 1997 001c 0B43 orrs r3, r3, r1 + 1998 001e 5361 str r3, [r2, #20] +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1999 .loc 1 1629 5 view .LVU682 +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2000 .loc 1 1629 12 is_stmt 0 view .LVU683 + 2001 0020 0020 movs r0, #0 + 2002 .LVL155: +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2003 .loc 1 1629 12 view .LVU684 + 2004 0022 7047 bx lr + 2005 .cfi_endproc + 2006 .LFE147: + 2008 .section .text.HAL_CAN_DeactivateNotification,"ax",%progbits + 2009 .align 1 + 2010 .global HAL_CAN_DeactivateNotification + 2011 .syntax unified + 2012 .thumb + 2013 .thumb_func + 2015 HAL_CAN_DeactivateNotification: + 2016 .LVL156: + 2017 .LFB148: +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Disable interrupts. +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param InactiveITs indicates which interrupts will be disabled. +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be any combination of @arg CAN_Interrupts. +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2018 .loc 1 1649 1 is_stmt 1 view -0 + 2019 .cfi_startproc + 2020 @ args = 0, pretend = 0, frame = 0 + 2021 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccqPwHQi.s page 88 + + + 2022 @ link register save eliminated. +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 2023 .loc 1 1650 3 view .LVU686 + 2024 .loc 1 1650 24 is_stmt 0 view .LVU687 + 2025 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 2026 .LVL157: +1651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_IT(InactiveITs)); + 2027 .loc 1 1653 3 is_stmt 1 view .LVU688 +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 2028 .loc 1 1655 3 view .LVU689 + 2029 .loc 1 1655 38 is_stmt 0 view .LVU690 + 2030 0004 013B subs r3, r3, #1 + 2031 .LVL158: + 2032 .loc 1 1655 38 view .LVU691 + 2033 0006 DBB2 uxtb r3, r3 + 2034 .loc 1 1655 6 view .LVU692 + 2035 0008 012B cmp r3, #1 + 2036 000a 05D9 bls .L153 +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Disable the selected interrupts */ +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_DISABLE_IT(hcan, InactiveITs); +1660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; +1663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 2037 .loc 1 1667 5 is_stmt 1 view .LVU693 + 2038 .loc 1 1667 9 is_stmt 0 view .LVU694 + 2039 000c 436A ldr r3, [r0, #36] + 2040 .loc 1 1667 21 view .LVU695 + 2041 000e 43F48023 orr r3, r3, #262144 + 2042 0012 4362 str r3, [r0, #36] +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 2043 .loc 1 1669 5 is_stmt 1 view .LVU696 + 2044 .loc 1 1669 12 is_stmt 0 view .LVU697 + 2045 0014 0120 movs r0, #1 + 2046 .LVL159: +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2047 .loc 1 1671 1 view .LVU698 + 2048 0016 7047 bx lr + 2049 .LVL160: + 2050 .L153: +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2051 .loc 1 1659 5 is_stmt 1 view .LVU699 + 2052 0018 0268 ldr r2, [r0] + 2053 001a 5369 ldr r3, [r2, #20] + 2054 001c 23EA0103 bic r3, r3, r1 + 2055 0020 5361 str r3, [r2, #20] + ARM GAS /tmp/ccqPwHQi.s page 89 + + +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2056 .loc 1 1662 5 view .LVU700 +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2057 .loc 1 1662 12 is_stmt 0 view .LVU701 + 2058 0022 0020 movs r0, #0 + 2059 .LVL161: +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2060 .loc 1 1662 12 view .LVU702 + 2061 0024 7047 bx lr + 2062 .cfi_endproc + 2063 .LFE148: + 2065 .section .text.HAL_CAN_TxMailbox0CompleteCallback,"ax",%progbits + 2066 .align 1 + 2067 .weak HAL_CAN_TxMailbox0CompleteCallback + 2068 .syntax unified + 2069 .thumb + 2070 .thumb_func + 2072 HAL_CAN_TxMailbox0CompleteCallback: + 2073 .LVL162: + 2074 .LFB150: +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Handles CAN interrupt request +1675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t errorcode = HAL_CAN_ERROR_NONE; +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t interrupts = READ_REG(hcan->Instance->IER); +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t msrflags = READ_REG(hcan->Instance->MSR); +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tsrflags = READ_REG(hcan->Instance->TSR); +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t esrflags = READ_REG(hcan->Instance->ESR); +1688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmit Mailbox empty interrupt management *****************************/ +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmit Mailbox 0 management *****************************************/ +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_RQCP0) != 0U) +1694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_TXOK0) != 0U) +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 0 complete callback */ +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0CompleteCallback(hcan); +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox0CompleteCallback(hcan); +1707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + ARM GAS /tmp/ccqPwHQi.s page 90 + + +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_ALST0) != 0U) +1712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_ALST0; +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if ((tsrflags & CAN_TSR_TERR0) != 0U) +1717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_TERR0; +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 0 abort callback */ +1724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0AbortCallback(hcan); +1727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox0AbortCallback(hcan); +1730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmit Mailbox 1 management *****************************************/ +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_RQCP1) != 0U) +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); +1740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_TXOK1) != 0U) +1742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 1 complete callback */ +1744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1CompleteCallback(hcan); +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox1CompleteCallback(hcan); +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_ALST1) != 0U) +1755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_ALST1; +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if ((tsrflags & CAN_TSR_TERR1) != 0U) +1760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_TERR1; +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + ARM GAS /tmp/ccqPwHQi.s page 91 + + +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 1 abort callback */ +1767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1AbortCallback(hcan); +1770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox1AbortCallback(hcan); +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmit Mailbox 2 management *****************************************/ +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_RQCP2) != 0U) +1780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); +1783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_TXOK2) != 0U) +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 2 complete callback */ +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2CompleteCallback(hcan); +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox2CompleteCallback(hcan); +1793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_ALST2) != 0U) +1798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_ALST2; +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if ((tsrflags & CAN_TSR_TERR2) != 0U) +1803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_TERR2; +1806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 2 abort callback */ +1810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2AbortCallback(hcan); +1813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox2AbortCallback(hcan); +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 overrun interrupt management *****************************/ + ARM GAS /tmp/ccqPwHQi.s page 92 + + +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Rx Fifo 0 overrun error */ +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_RX_FOV0; +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear FIFO0 Overrun Flag */ +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); +1832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 full interrupt management ********************************/ +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) +1837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((rf0rflags & CAN_RF0R_FULL0) != 0U) +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear FIFO 0 full Flag */ +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); +1842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 full Callback */ +1844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0FullCallback(hcan); +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFifo0FullCallback(hcan); +1850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 message pending interrupt management *********************/ +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) +1856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check if message is still pending */ +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 message pending Callback */ +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0MsgPendingCallback(hcan); +1864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFifo0MsgPendingCallback(hcan); +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 overrun interrupt management *****************************/ +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Rx Fifo 1 overrun error */ +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_RX_FOV1; +1878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear FIFO1 Overrun Flag */ + ARM GAS /tmp/ccqPwHQi.s page 93 + + +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 full interrupt management ********************************/ +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((rf1rflags & CAN_RF1R_FULL1) != 0U) +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear FIFO 1 full Flag */ +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 full Callback */ +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1FullCallback(hcan); +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFifo1FullCallback(hcan); +1899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 message pending interrupt management *********************/ +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) +1905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check if message is still pending */ +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 message pending Callback */ +1910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1MsgPendingCallback(hcan); +1913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFifo1MsgPendingCallback(hcan); +1916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Sleep interrupt management *********************************************/ +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) +1922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((msrflags & CAN_MSR_SLAKI) != 0U) +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear Sleep interrupt Flag */ +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Sleep Callback */ +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->SleepCallback(hcan); +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_SleepCallback(hcan); +1935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + ARM GAS /tmp/ccqPwHQi.s page 94 + + +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* WakeUp interrupt management *********************************************/ +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_WAKEUP) != 0U) +1941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((msrflags & CAN_MSR_WKUI) != 0U) +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear WakeUp Flag */ +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); +1946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* WakeUp Callback */ +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->WakeUpFromRxMsgCallback(hcan); +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_WakeUpFromRxMsgCallback(hcan); +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Error interrupts management *********************************************/ +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_ERROR) != 0U) +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((msrflags & CAN_MSR_ERRI) != 0U) +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Error Warning Flag */ +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EWGF) != 0U)) +1966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Error Warning */ +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_EWG; +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* No need for clear of Error Warning Flag as read-only */ +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Error Passive Flag */ +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && +1975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EPVF) != 0U)) +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Error Passive */ +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_EPV; +1979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* No need for clear of Error Passive Flag as read-only */ +1981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Bus-off Flag */ +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((interrupts & CAN_IT_BUSOFF) != 0U) && +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_BOFF) != 0U)) +1986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Bus-Off */ +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_BOF; +1989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* No need for clear of Error Bus-Off as read-only */ +1991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Last Error Code Flag */ + ARM GAS /tmp/ccqPwHQi.s page 95 + + +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_LEC) != 0U)) +1996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (esrflags & CAN_ESR_LEC) +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_0): +2000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Stuff error */ +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_STF; +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_1): +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Form error */ +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_FOR; +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Acknowledgement error */ +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_ACK; +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2): +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Bit recessive error */ +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_BR; +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Bit Dominant error */ +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_BD; +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to CRC error */ +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_CRC; +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default: +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear Last error code Flag */ +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear ERRI Flag */ +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call the Error call Back in case of Errors */ +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (errorcode != HAL_CAN_ERROR_NONE) +2038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code in handle */ +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= errorcode; +2041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call Error callback function */ +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +2044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCallback(hcan); +2046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_ErrorCallback(hcan); +2049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +2050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + ARM GAS /tmp/ccqPwHQi.s page 96 + + +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group5 Callback functions +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief CAN Callback functions +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * +2060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim +2061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +2062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Callback functions ##### +2063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** This subsection provides the following callback functions: +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox0CompleteCallback +2067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox1CompleteCallback +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox2CompleteCallback +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox0AbortCallback +2070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox1AbortCallback +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox2AbortCallback +2072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RxFifo0MsgPendingCallback +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RxFifo0FullCallback +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RxFifo1MsgPendingCallback +2075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RxFifo1FullCallback +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_SleepCallback +2077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_WakeUpFromRxMsgCallback +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_ErrorCallback +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim +2081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ +2082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 0 complete callback. +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2075 .loc 1 2091 1 is_stmt 1 view -0 + 2076 .cfi_startproc + 2077 @ args = 0, pretend = 0, frame = 0 + 2078 @ frame_needed = 0, uses_anonymous_args = 0 + 2079 @ link register save eliminated. +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2080 .loc 1 2093 3 view .LVU704 +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2081 .loc 1 2099 1 is_stmt 0 view .LVU705 + 2082 0000 7047 bx lr + ARM GAS /tmp/ccqPwHQi.s page 97 + + + 2083 .cfi_endproc + 2084 .LFE150: + 2086 .section .text.HAL_CAN_TxMailbox1CompleteCallback,"ax",%progbits + 2087 .align 1 + 2088 .weak HAL_CAN_TxMailbox1CompleteCallback + 2089 .syntax unified + 2090 .thumb + 2091 .thumb_func + 2093 HAL_CAN_TxMailbox1CompleteCallback: + 2094 .LVL163: + 2095 .LFB151: +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 1 complete callback. +2103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +2108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2096 .loc 1 2108 1 is_stmt 1 view -0 + 2097 .cfi_startproc + 2098 @ args = 0, pretend = 0, frame = 0 + 2099 @ frame_needed = 0, uses_anonymous_args = 0 + 2100 @ link register save eliminated. +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2101 .loc 1 2110 3 view .LVU707 +2111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the +2114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2102 .loc 1 2116 1 is_stmt 0 view .LVU708 + 2103 0000 7047 bx lr + 2104 .cfi_endproc + 2105 .LFE151: + 2107 .section .text.HAL_CAN_TxMailbox2CompleteCallback,"ax",%progbits + 2108 .align 1 + 2109 .weak HAL_CAN_TxMailbox2CompleteCallback + 2110 .syntax unified + 2111 .thumb + 2112 .thumb_func + 2114 HAL_CAN_TxMailbox2CompleteCallback: + 2115 .LVL164: + 2116 .LFB152: +2117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 2 complete callback. +2120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2117 .loc 1 2125 1 is_stmt 1 view -0 + ARM GAS /tmp/ccqPwHQi.s page 98 + + + 2118 .cfi_startproc + 2119 @ args = 0, pretend = 0, frame = 0 + 2120 @ frame_needed = 0, uses_anonymous_args = 0 + 2121 @ link register save eliminated. +2126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2122 .loc 1 2127 3 view .LVU710 +2128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the +2131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2123 .loc 1 2133 1 is_stmt 0 view .LVU711 + 2124 0000 7047 bx lr + 2125 .cfi_endproc + 2126 .LFE152: + 2128 .section .text.HAL_CAN_TxMailbox0AbortCallback,"ax",%progbits + 2129 .align 1 + 2130 .weak HAL_CAN_TxMailbox0AbortCallback + 2131 .syntax unified + 2132 .thumb + 2133 .thumb_func + 2135 HAL_CAN_TxMailbox0AbortCallback: + 2136 .LVL165: + 2137 .LFB153: +2134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 0 Cancellation callback. +2137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +2138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2138 .loc 1 2142 1 is_stmt 1 view -0 + 2139 .cfi_startproc + 2140 @ args = 0, pretend = 0, frame = 0 + 2141 @ frame_needed = 0, uses_anonymous_args = 0 + 2142 @ link register save eliminated. +2143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2143 .loc 1 2144 3 view .LVU713 +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox0AbortCallback could be implemented in the +2148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2144 .loc 1 2150 1 is_stmt 0 view .LVU714 + 2145 0000 7047 bx lr + 2146 .cfi_endproc + 2147 .LFE153: + 2149 .section .text.HAL_CAN_TxMailbox1AbortCallback,"ax",%progbits + 2150 .align 1 + 2151 .weak HAL_CAN_TxMailbox1AbortCallback + 2152 .syntax unified + ARM GAS /tmp/ccqPwHQi.s page 99 + + + 2153 .thumb + 2154 .thumb_func + 2156 HAL_CAN_TxMailbox1AbortCallback: + 2157 .LVL166: + 2158 .LFB154: +2151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 1 Cancellation callback. +2154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2159 .loc 1 2159 1 is_stmt 1 view -0 + 2160 .cfi_startproc + 2161 @ args = 0, pretend = 0, frame = 0 + 2162 @ frame_needed = 0, uses_anonymous_args = 0 + 2163 @ link register save eliminated. +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2164 .loc 1 2161 3 view .LVU716 +2162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox1AbortCallback could be implemented in the +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2165 .loc 1 2167 1 is_stmt 0 view .LVU717 + 2166 0000 7047 bx lr + 2167 .cfi_endproc + 2168 .LFE154: + 2170 .section .text.HAL_CAN_TxMailbox2AbortCallback,"ax",%progbits + 2171 .align 1 + 2172 .weak HAL_CAN_TxMailbox2AbortCallback + 2173 .syntax unified + 2174 .thumb + 2175 .thumb_func + 2177 HAL_CAN_TxMailbox2AbortCallback: + 2178 .LVL167: + 2179 .LFB155: +2168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 2 Cancellation callback. +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2180 .loc 1 2176 1 is_stmt 1 view -0 + 2181 .cfi_startproc + 2182 @ args = 0, pretend = 0, frame = 0 + 2183 @ frame_needed = 0, uses_anonymous_args = 0 + 2184 @ link register save eliminated. +2177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + ARM GAS /tmp/ccqPwHQi.s page 100 + + + 2185 .loc 1 2178 3 view .LVU719 +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox2AbortCallback could be implemented in the +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2186 .loc 1 2184 1 is_stmt 0 view .LVU720 + 2187 0000 7047 bx lr + 2188 .cfi_endproc + 2189 .LFE155: + 2191 .section .text.HAL_CAN_RxFifo0MsgPendingCallback,"ax",%progbits + 2192 .align 1 + 2193 .weak HAL_CAN_RxFifo0MsgPendingCallback + 2194 .syntax unified + 2195 .thumb + 2196 .thumb_func + 2198 HAL_CAN_RxFifo0MsgPendingCallback: + 2199 .LVL168: + 2200 .LFB156: +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Rx FIFO 0 message pending callback. +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +2193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2201 .loc 1 2193 1 is_stmt 1 view -0 + 2202 .cfi_startproc + 2203 @ args = 0, pretend = 0, frame = 0 + 2204 @ frame_needed = 0, uses_anonymous_args = 0 + 2205 @ link register save eliminated. +2194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2206 .loc 1 2195 3 view .LVU722 +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2207 .loc 1 2201 1 is_stmt 0 view .LVU723 + 2208 0000 7047 bx lr + 2209 .cfi_endproc + 2210 .LFE156: + 2212 .section .text.HAL_CAN_RxFifo0FullCallback,"ax",%progbits + 2213 .align 1 + 2214 .weak HAL_CAN_RxFifo0FullCallback + 2215 .syntax unified + 2216 .thumb + 2217 .thumb_func + 2219 HAL_CAN_RxFifo0FullCallback: + 2220 .LVL169: + 2221 .LFB157: +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccqPwHQi.s page 101 + + +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Rx FIFO 0 full callback. +2205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2222 .loc 1 2210 1 is_stmt 1 view -0 + 2223 .cfi_startproc + 2224 @ args = 0, pretend = 0, frame = 0 + 2225 @ frame_needed = 0, uses_anonymous_args = 0 + 2226 @ link register save eliminated. +2211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2227 .loc 1 2212 3 view .LVU725 +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_RxFifo0FullCallback could be implemented in the user +2216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** file +2217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2228 .loc 1 2218 1 is_stmt 0 view .LVU726 + 2229 0000 7047 bx lr + 2230 .cfi_endproc + 2231 .LFE157: + 2233 .section .text.HAL_CAN_RxFifo1MsgPendingCallback,"ax",%progbits + 2234 .align 1 + 2235 .weak HAL_CAN_RxFifo1MsgPendingCallback + 2236 .syntax unified + 2237 .thumb + 2238 .thumb_func + 2240 HAL_CAN_RxFifo1MsgPendingCallback: + 2241 .LVL170: + 2242 .LFB158: +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Rx FIFO 1 message pending callback. +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2243 .loc 1 2227 1 is_stmt 1 view -0 + 2244 .cfi_startproc + 2245 @ args = 0, pretend = 0, frame = 0 + 2246 @ frame_needed = 0, uses_anonymous_args = 0 + 2247 @ link register save eliminated. +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2248 .loc 1 2229 3 view .LVU728 +2230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the +2233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + ARM GAS /tmp/ccqPwHQi.s page 102 + + +2235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2249 .loc 1 2235 1 is_stmt 0 view .LVU729 + 2250 0000 7047 bx lr + 2251 .cfi_endproc + 2252 .LFE158: + 2254 .section .text.HAL_CAN_RxFifo1FullCallback,"ax",%progbits + 2255 .align 1 + 2256 .weak HAL_CAN_RxFifo1FullCallback + 2257 .syntax unified + 2258 .thumb + 2259 .thumb_func + 2261 HAL_CAN_RxFifo1FullCallback: + 2262 .LVL171: + 2263 .LFB159: +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Rx FIFO 1 full callback. +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2264 .loc 1 2244 1 is_stmt 1 view -0 + 2265 .cfi_startproc + 2266 @ args = 0, pretend = 0, frame = 0 + 2267 @ frame_needed = 0, uses_anonymous_args = 0 + 2268 @ link register save eliminated. +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2269 .loc 1 2246 3 view .LVU731 +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_RxFifo1FullCallback could be implemented in the user +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** file +2251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2270 .loc 1 2252 1 is_stmt 0 view .LVU732 + 2271 0000 7047 bx lr + 2272 .cfi_endproc + 2273 .LFE159: + 2275 .section .text.HAL_CAN_SleepCallback,"ax",%progbits + 2276 .align 1 + 2277 .weak HAL_CAN_SleepCallback + 2278 .syntax unified + 2279 .thumb + 2280 .thumb_func + 2282 HAL_CAN_SleepCallback: + 2283 .LVL172: + 2284 .LFB160: +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Sleep callback. +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + ARM GAS /tmp/ccqPwHQi.s page 103 + + +2260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2285 .loc 1 2261 1 is_stmt 1 view -0 + 2286 .cfi_startproc + 2287 @ args = 0, pretend = 0, frame = 0 + 2288 @ frame_needed = 0, uses_anonymous_args = 0 + 2289 @ link register save eliminated. +2262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2290 .loc 1 2263 3 view .LVU734 +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_SleepCallback could be implemented in the user file +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2291 .loc 1 2268 1 is_stmt 0 view .LVU735 + 2292 0000 7047 bx lr + 2293 .cfi_endproc + 2294 .LFE160: + 2296 .section .text.HAL_CAN_WakeUpFromRxMsgCallback,"ax",%progbits + 2297 .align 1 + 2298 .weak HAL_CAN_WakeUpFromRxMsgCallback + 2299 .syntax unified + 2300 .thumb + 2301 .thumb_func + 2303 HAL_CAN_WakeUpFromRxMsgCallback: + 2304 .LVL173: + 2305 .LFB161: +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief WakeUp from Rx message callback. +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2306 .loc 1 2277 1 is_stmt 1 view -0 + 2307 .cfi_startproc + 2308 @ args = 0, pretend = 0, frame = 0 + 2309 @ frame_needed = 0, uses_anonymous_args = 0 + 2310 @ link register save eliminated. +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2311 .loc 1 2279 3 view .LVU737 +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2312 .loc 1 2285 1 is_stmt 0 view .LVU738 + 2313 0000 7047 bx lr + 2314 .cfi_endproc + 2315 .LFE161: + 2317 .section .text.HAL_CAN_ErrorCallback,"ax",%progbits + 2318 .align 1 + ARM GAS /tmp/ccqPwHQi.s page 104 + + + 2319 .weak HAL_CAN_ErrorCallback + 2320 .syntax unified + 2321 .thumb + 2322 .thumb_func + 2324 HAL_CAN_ErrorCallback: + 2325 .LVL174: + 2326 .LFB162: +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Error CAN callback. +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2327 .loc 1 2294 1 is_stmt 1 view -0 + 2328 .cfi_startproc + 2329 @ args = 0, pretend = 0, frame = 0 + 2330 @ frame_needed = 0, uses_anonymous_args = 0 + 2331 @ link register save eliminated. +2295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 2332 .loc 1 2296 3 view .LVU740 +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_ErrorCallback could be implemented in the user file +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2333 .loc 1 2301 1 is_stmt 0 view .LVU741 + 2334 0000 7047 bx lr + 2335 .cfi_endproc + 2336 .LFE162: + 2338 .section .text.HAL_CAN_IRQHandler,"ax",%progbits + 2339 .align 1 + 2340 .global HAL_CAN_IRQHandler + 2341 .syntax unified + 2342 .thumb + 2343 .thumb_func + 2345 HAL_CAN_IRQHandler: + 2346 .LVL175: + 2347 .LFB149: +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t errorcode = HAL_CAN_ERROR_NONE; + 2348 .loc 1 1680 1 is_stmt 1 view -0 + 2349 .cfi_startproc + 2350 @ args = 0, pretend = 0, frame = 0 + 2351 @ frame_needed = 0, uses_anonymous_args = 0 +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t errorcode = HAL_CAN_ERROR_NONE; + 2352 .loc 1 1680 1 is_stmt 0 view .LVU743 + 2353 0000 2DE9F84F push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr} + 2354 .cfi_def_cfa_offset 40 + 2355 .cfi_offset 3, -40 + 2356 .cfi_offset 4, -36 + 2357 .cfi_offset 5, -32 + 2358 .cfi_offset 6, -28 + 2359 .cfi_offset 7, -24 + 2360 .cfi_offset 8, -20 + ARM GAS /tmp/ccqPwHQi.s page 105 + + + 2361 .cfi_offset 9, -16 + 2362 .cfi_offset 10, -12 + 2363 .cfi_offset 11, -8 + 2364 .cfi_offset 14, -4 + 2365 0004 0546 mov r5, r0 +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t interrupts = READ_REG(hcan->Instance->IER); + 2366 .loc 1 1681 3 is_stmt 1 view .LVU744 + 2367 .LVL176: +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t msrflags = READ_REG(hcan->Instance->MSR); + 2368 .loc 1 1682 3 view .LVU745 +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t msrflags = READ_REG(hcan->Instance->MSR); + 2369 .loc 1 1682 25 is_stmt 0 view .LVU746 + 2370 0006 0368 ldr r3, [r0] +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t msrflags = READ_REG(hcan->Instance->MSR); + 2371 .loc 1 1682 12 view .LVU747 + 2372 0008 5C69 ldr r4, [r3, #20] + 2373 .LVL177: +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + 2374 .loc 1 1683 3 is_stmt 1 view .LVU748 +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + 2375 .loc 1 1683 12 is_stmt 0 view .LVU749 + 2376 000a D3F80480 ldr r8, [r3, #4] + 2377 .LVL178: +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + 2378 .loc 1 1684 3 is_stmt 1 view .LVU750 +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + 2379 .loc 1 1684 12 is_stmt 0 view .LVU751 + 2380 000e 9F68 ldr r7, [r3, #8] + 2381 .LVL179: +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + 2382 .loc 1 1685 3 is_stmt 1 view .LVU752 +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + 2383 .loc 1 1685 12 is_stmt 0 view .LVU753 + 2384 0010 D3F80CB0 ldr fp, [r3, #12] + 2385 .LVL180: +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t esrflags = READ_REG(hcan->Instance->ESR); + 2386 .loc 1 1686 3 is_stmt 1 view .LVU754 +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t esrflags = READ_REG(hcan->Instance->ESR); + 2387 .loc 1 1686 12 is_stmt 0 view .LVU755 + 2388 0014 D3F810A0 ldr r10, [r3, #16] + 2389 .LVL181: +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2390 .loc 1 1687 3 is_stmt 1 view .LVU756 +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2391 .loc 1 1687 12 is_stmt 0 view .LVU757 + 2392 0018 D3F81890 ldr r9, [r3, #24] + 2393 .LVL182: +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2394 .loc 1 1690 3 is_stmt 1 view .LVU758 +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2395 .loc 1 1690 6 is_stmt 0 view .LVU759 + 2396 001c 14F00106 ands r6, r4, #1 + 2397 0020 3BD0 beq .L168 +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2398 .loc 1 1693 5 is_stmt 1 view .LVU760 +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2399 .loc 1 1693 8 is_stmt 0 view .LVU761 + ARM GAS /tmp/ccqPwHQi.s page 106 + + + 2400 0022 17F00106 ands r6, r7, #1 + 2401 0026 16D0 beq .L169 +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2402 .loc 1 1696 7 is_stmt 1 view .LVU762 + 2403 0028 0122 movs r2, #1 + 2404 002a 9A60 str r2, [r3, #8] +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2405 .loc 1 1698 7 view .LVU763 +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2406 .loc 1 1698 10 is_stmt 0 view .LVU764 + 2407 002c 17F0020F tst r7, #2 + 2408 0030 08D1 bne .L203 +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2409 .loc 1 1711 9 is_stmt 1 view .LVU765 +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2410 .loc 1 1711 12 is_stmt 0 view .LVU766 + 2411 0032 17F0040F tst r7, #4 + 2412 0036 0CD1 bne .L200 +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2413 .loc 1 1716 14 is_stmt 1 view .LVU767 +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2414 .loc 1 1716 17 is_stmt 0 view .LVU768 + 2415 0038 17F00806 ands r6, r7, #8 + 2416 003c 06D0 beq .L204 +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2417 .loc 1 1719 21 view .LVU769 + 2418 003e 4FF48056 mov r6, #4096 + 2419 0042 08E0 b .L169 + 2420 .L203: +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2421 .loc 1 1706 9 is_stmt 1 view .LVU770 + 2422 0044 FFF7FEFF bl HAL_CAN_TxMailbox0CompleteCallback + 2423 .LVL183: +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t interrupts = READ_REG(hcan->Instance->IER); + 2424 .loc 1 1681 12 is_stmt 0 view .LVU771 + 2425 0048 0026 movs r6, #0 + 2426 004a 04E0 b .L169 + 2427 .LVL184: + 2428 .L204: +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2429 .loc 1 1729 11 is_stmt 1 view .LVU772 + 2430 004c FFF7FEFF bl HAL_CAN_TxMailbox0AbortCallback + 2431 .LVL185: +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2432 .loc 1 1729 11 is_stmt 0 view .LVU773 + 2433 0050 01E0 b .L169 + 2434 .LVL186: + 2435 .L200: +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2436 .loc 1 1714 21 view .LVU774 + 2437 0052 4FF40066 mov r6, #2048 + 2438 .LVL187: + 2439 .L169: +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2440 .loc 1 1736 5 is_stmt 1 view .LVU775 +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2441 .loc 1 1736 8 is_stmt 0 view .LVU776 + ARM GAS /tmp/ccqPwHQi.s page 107 + + + 2442 0056 17F4807F tst r7, #256 + 2443 005a 0DD0 beq .L171 +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2444 .loc 1 1739 7 is_stmt 1 view .LVU777 + 2445 005c 2B68 ldr r3, [r5] + 2446 005e 4FF48072 mov r2, #256 + 2447 0062 9A60 str r2, [r3, #8] +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2448 .loc 1 1741 7 view .LVU778 +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2449 .loc 1 1741 10 is_stmt 0 view .LVU779 + 2450 0064 17F4007F tst r7, #512 + 2451 0068 40F08680 bne .L205 +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2452 .loc 1 1754 9 is_stmt 1 view .LVU780 +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2453 .loc 1 1754 12 is_stmt 0 view .LVU781 + 2454 006c 17F4806F tst r7, #1024 + 2455 0070 00F08680 beq .L173 +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2456 .loc 1 1757 11 is_stmt 1 view .LVU782 +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2457 .loc 1 1757 21 is_stmt 0 view .LVU783 + 2458 0074 46F40056 orr r6, r6, #8192 + 2459 .LVL188: + 2460 .L171: +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2461 .loc 1 1779 5 is_stmt 1 view .LVU784 +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2462 .loc 1 1779 8 is_stmt 0 view .LVU785 + 2463 0078 17F4803F tst r7, #65536 + 2464 007c 0DD0 beq .L168 +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2465 .loc 1 1782 7 is_stmt 1 view .LVU786 + 2466 007e 2B68 ldr r3, [r5] + 2467 0080 4FF48032 mov r2, #65536 + 2468 0084 9A60 str r2, [r3, #8] +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2469 .loc 1 1784 7 view .LVU787 +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2470 .loc 1 1784 10 is_stmt 0 view .LVU788 + 2471 0086 17F4003F tst r7, #131072 + 2472 008a 40F08380 bne .L206 +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2473 .loc 1 1797 9 is_stmt 1 view .LVU789 +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2474 .loc 1 1797 12 is_stmt 0 view .LVU790 + 2475 008e 17F4802F tst r7, #262144 + 2476 0092 00F08380 beq .L176 +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2477 .loc 1 1800 11 is_stmt 1 view .LVU791 +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2478 .loc 1 1800 21 is_stmt 0 view .LVU792 + 2479 0096 46F40046 orr r6, r6, #32768 + 2480 .LVL189: + 2481 .L168: +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + ARM GAS /tmp/ccqPwHQi.s page 108 + + + 2482 .loc 1 1823 3 is_stmt 1 view .LVU793 +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2483 .loc 1 1823 6 is_stmt 0 view .LVU794 + 2484 009a 14F0080F tst r4, #8 + 2485 009e 07D0 beq .L178 +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2486 .loc 1 1825 5 is_stmt 1 view .LVU795 +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2487 .loc 1 1825 8 is_stmt 0 view .LVU796 + 2488 00a0 1BF0100F tst fp, #16 + 2489 00a4 04D0 beq .L178 +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2490 .loc 1 1828 7 is_stmt 1 view .LVU797 +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2491 .loc 1 1828 17 is_stmt 0 view .LVU798 + 2492 00a6 46F40076 orr r6, r6, #512 + 2493 .LVL190: +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2494 .loc 1 1831 7 is_stmt 1 view .LVU799 + 2495 00aa 2B68 ldr r3, [r5] + 2496 00ac 1022 movs r2, #16 + 2497 00ae DA60 str r2, [r3, #12] + 2498 .L178: +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2499 .loc 1 1836 3 view .LVU800 +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2500 .loc 1 1836 6 is_stmt 0 view .LVU801 + 2501 00b0 14F0040F tst r4, #4 + 2502 00b4 02D0 beq .L179 +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2503 .loc 1 1838 5 is_stmt 1 view .LVU802 +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2504 .loc 1 1838 8 is_stmt 0 view .LVU803 + 2505 00b6 1BF0080F tst fp, #8 + 2506 00ba 79D1 bne .L207 + 2507 .L179: +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2508 .loc 1 1855 3 is_stmt 1 view .LVU804 +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2509 .loc 1 1855 6 is_stmt 0 view .LVU805 + 2510 00bc 14F0020F tst r4, #2 + 2511 00c0 04D0 beq .L180 +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2512 .loc 1 1858 5 is_stmt 1 view .LVU806 +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2513 .loc 1 1858 14 is_stmt 0 view .LVU807 + 2514 00c2 2B68 ldr r3, [r5] +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2515 .loc 1 1858 24 view .LVU808 + 2516 00c4 DB68 ldr r3, [r3, #12] +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2517 .loc 1 1858 8 view .LVU809 + 2518 00c6 13F0030F tst r3, #3 + 2519 00ca 78D1 bne .L208 + 2520 .L180: +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2521 .loc 1 1872 3 is_stmt 1 view .LVU810 + ARM GAS /tmp/ccqPwHQi.s page 109 + + +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2522 .loc 1 1872 6 is_stmt 0 view .LVU811 + 2523 00cc 14F0400F tst r4, #64 + 2524 00d0 07D0 beq .L181 +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2525 .loc 1 1874 5 is_stmt 1 view .LVU812 +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2526 .loc 1 1874 8 is_stmt 0 view .LVU813 + 2527 00d2 1AF0100F tst r10, #16 + 2528 00d6 04D0 beq .L181 +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2529 .loc 1 1877 7 is_stmt 1 view .LVU814 +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2530 .loc 1 1877 17 is_stmt 0 view .LVU815 + 2531 00d8 46F48066 orr r6, r6, #1024 + 2532 .LVL191: +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2533 .loc 1 1880 7 is_stmt 1 view .LVU816 + 2534 00dc 2B68 ldr r3, [r5] + 2535 00de 1022 movs r2, #16 + 2536 00e0 1A61 str r2, [r3, #16] + 2537 .L181: +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2538 .loc 1 1885 3 view .LVU817 +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2539 .loc 1 1885 6 is_stmt 0 view .LVU818 + 2540 00e2 14F0200F tst r4, #32 + 2541 00e6 02D0 beq .L182 +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2542 .loc 1 1887 5 is_stmt 1 view .LVU819 +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2543 .loc 1 1887 8 is_stmt 0 view .LVU820 + 2544 00e8 1AF0080F tst r10, #8 + 2545 00ec 6BD1 bne .L209 + 2546 .L182: +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2547 .loc 1 1904 3 is_stmt 1 view .LVU821 +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2548 .loc 1 1904 6 is_stmt 0 view .LVU822 + 2549 00ee 14F0100F tst r4, #16 + 2550 00f2 04D0 beq .L183 +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2551 .loc 1 1907 5 is_stmt 1 view .LVU823 +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2552 .loc 1 1907 14 is_stmt 0 view .LVU824 + 2553 00f4 2B68 ldr r3, [r5] +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2554 .loc 1 1907 24 view .LVU825 + 2555 00f6 1B69 ldr r3, [r3, #16] +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2556 .loc 1 1907 8 view .LVU826 + 2557 00f8 13F0030F tst r3, #3 + 2558 00fc 6AD1 bne .L210 + 2559 .L183: +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2560 .loc 1 1921 3 is_stmt 1 view .LVU827 +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + ARM GAS /tmp/ccqPwHQi.s page 110 + + + 2561 .loc 1 1921 6 is_stmt 0 view .LVU828 + 2562 00fe 14F4003F tst r4, #131072 + 2563 0102 02D0 beq .L184 +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2564 .loc 1 1923 5 is_stmt 1 view .LVU829 +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2565 .loc 1 1923 8 is_stmt 0 view .LVU830 + 2566 0104 18F0100F tst r8, #16 + 2567 0108 68D1 bne .L211 + 2568 .L184: +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2569 .loc 1 1940 3 is_stmt 1 view .LVU831 +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2570 .loc 1 1940 6 is_stmt 0 view .LVU832 + 2571 010a 14F4803F tst r4, #65536 + 2572 010e 02D0 beq .L185 +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2573 .loc 1 1942 5 is_stmt 1 view .LVU833 +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2574 .loc 1 1942 8 is_stmt 0 view .LVU834 + 2575 0110 18F0080F tst r8, #8 + 2576 0114 69D1 bne .L212 + 2577 .L185: +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2578 .loc 1 1959 3 is_stmt 1 view .LVU835 +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2579 .loc 1 1959 6 is_stmt 0 view .LVU836 + 2580 0116 14F4004F tst r4, #32768 + 2581 011a 7AD0 beq .L186 +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2582 .loc 1 1961 5 is_stmt 1 view .LVU837 +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2583 .loc 1 1961 8 is_stmt 0 view .LVU838 + 2584 011c 18F0040F tst r8, #4 + 2585 0120 74D0 beq .L187 +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EWGF) != 0U)) + 2586 .loc 1 1964 7 is_stmt 1 view .LVU839 +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EWGF) != 0U)) + 2587 .loc 1 1964 10 is_stmt 0 view .LVU840 + 2588 0122 14F4807F tst r4, #256 + 2589 0126 04D0 beq .L188 +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EWGF) != 0U)) + 2590 .loc 1 1964 55 discriminator 1 view .LVU841 + 2591 0128 19F0010F tst r9, #1 + 2592 012c 01D0 beq .L188 +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2593 .loc 1 1968 9 is_stmt 1 view .LVU842 +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2594 .loc 1 1968 19 is_stmt 0 view .LVU843 + 2595 012e 46F00106 orr r6, r6, #1 + 2596 .LVL192: + 2597 .L188: +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EPVF) != 0U)) + 2598 .loc 1 1974 7 is_stmt 1 view .LVU844 +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EPVF) != 0U)) + 2599 .loc 1 1974 10 is_stmt 0 view .LVU845 + 2600 0132 14F4007F tst r4, #512 + ARM GAS /tmp/ccqPwHQi.s page 111 + + + 2601 0136 04D0 beq .L189 +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EPVF) != 0U)) + 2602 .loc 1 1974 55 discriminator 1 view .LVU846 + 2603 0138 19F0020F tst r9, #2 + 2604 013c 01D0 beq .L189 +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2605 .loc 1 1978 9 is_stmt 1 view .LVU847 +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2606 .loc 1 1978 19 is_stmt 0 view .LVU848 + 2607 013e 46F00206 orr r6, r6, #2 + 2608 .LVL193: + 2609 .L189: +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_BOFF) != 0U)) + 2610 .loc 1 1984 7 is_stmt 1 view .LVU849 +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_BOFF) != 0U)) + 2611 .loc 1 1984 10 is_stmt 0 view .LVU850 + 2612 0142 14F4806F tst r4, #1024 + 2613 0146 04D0 beq .L190 +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_BOFF) != 0U)) + 2614 .loc 1 1984 48 discriminator 1 view .LVU851 + 2615 0148 19F0040F tst r9, #4 + 2616 014c 01D0 beq .L190 +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2617 .loc 1 1988 9 is_stmt 1 view .LVU852 +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2618 .loc 1 1988 19 is_stmt 0 view .LVU853 + 2619 014e 46F00406 orr r6, r6, #4 + 2620 .LVL194: + 2621 .L190: +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_LEC) != 0U)) + 2622 .loc 1 1994 7 is_stmt 1 view .LVU854 +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_LEC) != 0U)) + 2623 .loc 1 1994 10 is_stmt 0 view .LVU855 + 2624 0152 14F4006F tst r4, #2048 + 2625 0156 59D0 beq .L187 +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_LEC) != 0U)) + 2626 .loc 1 1994 57 discriminator 1 view .LVU856 + 2627 0158 19F07009 ands r9, r9, #112 + 2628 .LVL195: +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_LEC) != 0U)) + 2629 .loc 1 1994 57 discriminator 1 view .LVU857 + 2630 015c 56D0 beq .L187 +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2631 .loc 1 1997 9 is_stmt 1 view .LVU858 + 2632 015e B9F1400F cmp r9, #64 + 2633 0162 65D0 beq .L191 + 2634 0164 58D8 bhi .L192 + 2635 0166 B9F1200F cmp r9, #32 + 2636 016a 5ED0 beq .L193 + 2637 016c B9F1300F cmp r9, #48 + 2638 0170 42D1 bne .L213 +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2639 .loc 1 2009 13 view .LVU859 +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2640 .loc 1 2009 23 is_stmt 0 view .LVU860 + 2641 0172 46F02006 orr r6, r6, #32 + 2642 .LVL196: + ARM GAS /tmp/ccqPwHQi.s page 112 + + +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2): + 2643 .loc 1 2010 13 is_stmt 1 view .LVU861 + 2644 0176 44E0 b .L196 + 2645 .LVL197: + 2646 .L205: +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2647 .loc 1 1749 9 view .LVU862 + 2648 0178 2846 mov r0, r5 + 2649 017a FFF7FEFF bl HAL_CAN_TxMailbox1CompleteCallback + 2650 .LVL198: + 2651 017e 7BE7 b .L171 + 2652 .L173: +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2653 .loc 1 1759 14 view .LVU863 +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2654 .loc 1 1759 17 is_stmt 0 view .LVU864 + 2655 0180 17F4006F tst r7, #2048 + 2656 0184 02D0 beq .L174 +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2657 .loc 1 1762 11 is_stmt 1 view .LVU865 +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2658 .loc 1 1762 21 is_stmt 0 view .LVU866 + 2659 0186 46F48046 orr r6, r6, #16384 + 2660 .LVL199: +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2661 .loc 1 1762 21 view .LVU867 + 2662 018a 75E7 b .L171 + 2663 .L174: +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2664 .loc 1 1772 11 is_stmt 1 view .LVU868 + 2665 018c 2846 mov r0, r5 + 2666 018e FFF7FEFF bl HAL_CAN_TxMailbox1AbortCallback + 2667 .LVL200: + 2668 0192 71E7 b .L171 + 2669 .L206: +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2670 .loc 1 1792 9 view .LVU869 + 2671 0194 2846 mov r0, r5 + 2672 0196 FFF7FEFF bl HAL_CAN_TxMailbox2CompleteCallback + 2673 .LVL201: + 2674 019a 7EE7 b .L168 + 2675 .L176: +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2676 .loc 1 1802 14 view .LVU870 +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2677 .loc 1 1802 17 is_stmt 0 view .LVU871 + 2678 019c 17F4002F tst r7, #524288 + 2679 01a0 02D0 beq .L177 +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2680 .loc 1 1805 11 is_stmt 1 view .LVU872 +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2681 .loc 1 1805 21 is_stmt 0 view .LVU873 + 2682 01a2 46F48036 orr r6, r6, #65536 + 2683 .LVL202: +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2684 .loc 1 1805 21 view .LVU874 + 2685 01a6 78E7 b .L168 + ARM GAS /tmp/ccqPwHQi.s page 113 + + + 2686 .L177: +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2687 .loc 1 1815 11 is_stmt 1 view .LVU875 + 2688 01a8 2846 mov r0, r5 + 2689 01aa FFF7FEFF bl HAL_CAN_TxMailbox2AbortCallback + 2690 .LVL203: + 2691 01ae 74E7 b .L168 + 2692 .L207: +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2693 .loc 1 1841 7 view .LVU876 + 2694 01b0 2B68 ldr r3, [r5] + 2695 01b2 0822 movs r2, #8 + 2696 01b4 DA60 str r2, [r3, #12] +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2697 .loc 1 1849 7 view .LVU877 + 2698 01b6 2846 mov r0, r5 + 2699 01b8 FFF7FEFF bl HAL_CAN_RxFifo0FullCallback + 2700 .LVL204: + 2701 01bc 7EE7 b .L179 + 2702 .L208: +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2703 .loc 1 1866 7 view .LVU878 + 2704 01be 2846 mov r0, r5 + 2705 01c0 FFF7FEFF bl HAL_CAN_RxFifo0MsgPendingCallback + 2706 .LVL205: + 2707 01c4 82E7 b .L180 + 2708 .L209: +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2709 .loc 1 1890 7 view .LVU879 + 2710 01c6 2B68 ldr r3, [r5] + 2711 01c8 0822 movs r2, #8 + 2712 01ca 1A61 str r2, [r3, #16] +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2713 .loc 1 1898 7 view .LVU880 + 2714 01cc 2846 mov r0, r5 + 2715 01ce FFF7FEFF bl HAL_CAN_RxFifo1FullCallback + 2716 .LVL206: + 2717 01d2 8CE7 b .L182 + 2718 .L210: +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2719 .loc 1 1915 7 view .LVU881 + 2720 01d4 2846 mov r0, r5 + 2721 01d6 FFF7FEFF bl HAL_CAN_RxFifo1MsgPendingCallback + 2722 .LVL207: + 2723 01da 90E7 b .L183 + 2724 .L211: +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2725 .loc 1 1926 7 view .LVU882 + 2726 01dc 2B68 ldr r3, [r5] + 2727 01de 1022 movs r2, #16 + 2728 01e0 5A60 str r2, [r3, #4] +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2729 .loc 1 1934 7 view .LVU883 + 2730 01e2 2846 mov r0, r5 + 2731 01e4 FFF7FEFF bl HAL_CAN_SleepCallback + 2732 .LVL208: + 2733 01e8 8FE7 b .L184 + ARM GAS /tmp/ccqPwHQi.s page 114 + + + 2734 .L212: +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2735 .loc 1 1945 7 view .LVU884 + 2736 01ea 2B68 ldr r3, [r5] + 2737 01ec 0822 movs r2, #8 + 2738 01ee 5A60 str r2, [r3, #4] +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2739 .loc 1 1953 7 view .LVU885 + 2740 01f0 2846 mov r0, r5 + 2741 01f2 FFF7FEFF bl HAL_CAN_WakeUpFromRxMsgCallback + 2742 .LVL209: + 2743 01f6 8EE7 b .L185 + 2744 .LVL210: + 2745 .L213: +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2746 .loc 1 1997 9 is_stmt 0 view .LVU886 + 2747 01f8 B9F1100F cmp r9, #16 + 2748 01fc 01D1 bne .L196 +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2749 .loc 1 2001 13 is_stmt 1 view .LVU887 +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2750 .loc 1 2001 23 is_stmt 0 view .LVU888 + 2751 01fe 46F00806 orr r6, r6, #8 + 2752 .LVL211: +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_1): + 2753 .loc 1 2002 13 is_stmt 1 view .LVU889 + 2754 .L196: +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2755 .loc 1 2028 9 view .LVU890 + 2756 0202 2A68 ldr r2, [r5] + 2757 0204 9369 ldr r3, [r2, #24] + 2758 0206 23F07003 bic r3, r3, #112 + 2759 020a 9361 str r3, [r2, #24] + 2760 .L187: +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2761 .loc 1 2033 5 view .LVU891 + 2762 020c 2B68 ldr r3, [r5] + 2763 020e 0422 movs r2, #4 + 2764 0210 5A60 str r2, [r3, #4] + 2765 .L186: +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2766 .loc 1 2037 3 view .LVU892 +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2767 .loc 1 2037 6 is_stmt 0 view .LVU893 + 2768 0212 9EB9 cbnz r6, .L214 + 2769 .L167: +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2770 .loc 1 2051 1 view .LVU894 + 2771 0214 BDE8F88F pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc} + 2772 .LVL212: + 2773 .L192: +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2774 .loc 1 1997 9 view .LVU895 + 2775 0218 B9F1500F cmp r9, #80 + 2776 021c 0BD0 beq .L197 + 2777 021e B9F1600F cmp r9, #96 + 2778 0222 EED1 bne .L196 + ARM GAS /tmp/ccqPwHQi.s page 115 + + +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2779 .loc 1 2021 13 is_stmt 1 view .LVU896 +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2780 .loc 1 2021 23 is_stmt 0 view .LVU897 + 2781 0224 46F48076 orr r6, r6, #256 + 2782 .LVL213: +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default: + 2783 .loc 1 2022 13 is_stmt 1 view .LVU898 + 2784 0228 EBE7 b .L196 + 2785 .L193: +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2786 .loc 1 2005 13 view .LVU899 +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2787 .loc 1 2005 23 is_stmt 0 view .LVU900 + 2788 022a 46F01006 orr r6, r6, #16 + 2789 .LVL214: +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + 2790 .loc 1 2006 13 is_stmt 1 view .LVU901 + 2791 022e E8E7 b .L196 + 2792 .L191: +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2793 .loc 1 2013 13 view .LVU902 +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2794 .loc 1 2013 23 is_stmt 0 view .LVU903 + 2795 0230 46F04006 orr r6, r6, #64 + 2796 .LVL215: +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + 2797 .loc 1 2014 13 is_stmt 1 view .LVU904 + 2798 0234 E5E7 b .L196 + 2799 .L197: +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2800 .loc 1 2017 13 view .LVU905 +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 2801 .loc 1 2017 23 is_stmt 0 view .LVU906 + 2802 0236 46F08006 orr r6, r6, #128 + 2803 .LVL216: +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + 2804 .loc 1 2018 13 is_stmt 1 view .LVU907 + 2805 023a E2E7 b .L196 + 2806 .L214: +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2807 .loc 1 2040 5 view .LVU908 +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2808 .loc 1 2040 9 is_stmt 0 view .LVU909 + 2809 023c 6B6A ldr r3, [r5, #36] +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2810 .loc 1 2040 21 view .LVU910 + 2811 023e 3343 orrs r3, r3, r6 + 2812 0240 6B62 str r3, [r5, #36] +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 2813 .loc 1 2048 5 is_stmt 1 view .LVU911 + 2814 0242 2846 mov r0, r5 + 2815 0244 FFF7FEFF bl HAL_CAN_ErrorCallback + 2816 .LVL217: +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 2817 .loc 1 2051 1 is_stmt 0 view .LVU912 + 2818 0248 E4E7 b .L167 + ARM GAS /tmp/ccqPwHQi.s page 116 + + + 2819 .cfi_endproc + 2820 .LFE149: + 2822 .section .text.HAL_CAN_GetState,"ax",%progbits + 2823 .align 1 + 2824 .global HAL_CAN_GetState + 2825 .syntax unified + 2826 .thumb + 2827 .thumb_func + 2829 HAL_CAN_GetState: + 2830 .LVL218: + 2831 .LFB163: +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief CAN Peripheral State functions +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * +2310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Peripheral State and Error functions ##### +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** This subsection provides functions allowing to : +2316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetState() : Return the CAN state. +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetError() : Return the CAN error codes if any. +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. +2319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim +2321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return the CAN state. +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL state +2329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2832 .loc 1 2331 1 is_stmt 1 view -0 + 2833 .cfi_startproc + 2834 @ args = 0, pretend = 0, frame = 0 + 2835 @ frame_needed = 0, uses_anonymous_args = 0 + 2836 @ link register save eliminated. + 2837 .loc 1 2331 1 is_stmt 0 view .LVU914 + 2838 0000 0246 mov r2, r0 +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 2839 .loc 1 2332 3 is_stmt 1 view .LVU915 + 2840 .loc 1 2332 24 is_stmt 0 view .LVU916 + 2841 0002 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 2842 0006 D8B2 uxtb r0, r3 + 2843 .LVL219: +2333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 2844 .loc 1 2334 3 is_stmt 1 view .LVU917 + ARM GAS /tmp/ccqPwHQi.s page 117 + + + 2845 .loc 1 2334 38 is_stmt 0 view .LVU918 + 2846 0008 013B subs r3, r3, #1 + 2847 000a DBB2 uxtb r3, r3 + 2848 .loc 1 2334 6 view .LVU919 + 2849 000c 012B cmp r3, #1 + 2850 000e 00D9 bls .L219 + 2851 .LVL220: + 2852 .L216: +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +2336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check sleep mode acknowledge flag */ +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) +2339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Sleep mode is active */ +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** state = HAL_CAN_STATE_SLEEP_ACTIVE; +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check sleep mode request flag */ +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) +2345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Sleep mode request is pending */ +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** state = HAL_CAN_STATE_SLEEP_PENDING; +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +2350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Neither sleep mode request nor sleep mode acknowledge */ +2352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2853 .loc 1 2352 5 is_stmt 1 view .LVU920 +2353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return CAN state */ +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return state; + 2854 .loc 1 2356 3 view .LVU921 +2357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2855 .loc 1 2357 1 is_stmt 0 view .LVU922 + 2856 0010 7047 bx lr + 2857 .LVL221: + 2858 .L219: +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2859 .loc 1 2338 5 is_stmt 1 view .LVU923 +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2860 .loc 1 2338 14 is_stmt 0 view .LVU924 + 2861 0012 1368 ldr r3, [r2] +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2862 .loc 1 2338 24 view .LVU925 + 2863 0014 5A68 ldr r2, [r3, #4] + 2864 .LVL222: +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2865 .loc 1 2338 8 view .LVU926 + 2866 0016 12F0020F tst r2, #2 + 2867 001a 05D1 bne .L217 +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2868 .loc 1 2344 10 is_stmt 1 view .LVU927 +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2869 .loc 1 2344 29 is_stmt 0 view .LVU928 + 2870 001c 1B68 ldr r3, [r3] +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2871 .loc 1 2344 13 view .LVU929 + ARM GAS /tmp/ccqPwHQi.s page 118 + + + 2872 001e 13F0020F tst r3, #2 + 2873 0022 F5D0 beq .L216 +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2874 .loc 1 2347 13 view .LVU930 + 2875 0024 0320 movs r0, #3 + 2876 .LVL223: +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2877 .loc 1 2347 13 view .LVU931 + 2878 0026 F3E7 b .L216 + 2879 .LVL224: + 2880 .L217: +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2881 .loc 1 2341 13 view .LVU932 + 2882 0028 0420 movs r0, #4 + 2883 .LVL225: +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2884 .loc 1 2341 13 view .LVU933 + 2885 002a 7047 bx lr + 2886 .cfi_endproc + 2887 .LFE163: + 2889 .section .text.HAL_CAN_GetError,"ax",%progbits + 2890 .align 1 + 2891 .global HAL_CAN_GetError + 2892 .syntax unified + 2893 .thumb + 2894 .thumb_func + 2896 HAL_CAN_GetError: + 2897 .LVL226: + 2898 .LFB164: +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return the CAN error code. +2361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval CAN Error Code +2364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2899 .loc 1 2366 1 is_stmt 1 view -0 + 2900 .cfi_startproc + 2901 @ args = 0, pretend = 0, frame = 0 + 2902 @ frame_needed = 0, uses_anonymous_args = 0 + 2903 @ link register save eliminated. +2367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return CAN error code */ +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return hcan->ErrorCode; + 2904 .loc 1 2368 3 view .LVU935 + 2905 .loc 1 2368 14 is_stmt 0 view .LVU936 + 2906 0000 406A ldr r0, [r0, #36] + 2907 .LVL227: +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2908 .loc 1 2369 1 view .LVU937 + 2909 0002 7047 bx lr + 2910 .cfi_endproc + 2911 .LFE164: + 2913 .section .text.HAL_CAN_ResetError,"ax",%progbits + 2914 .align 1 + 2915 .global HAL_CAN_ResetError + ARM GAS /tmp/ccqPwHQi.s page 119 + + + 2916 .syntax unified + 2917 .thumb + 2918 .thumb_func + 2920 HAL_CAN_ResetError: + 2921 .LVL228: + 2922 .LFB165: +2370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Reset the CAN error code. +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +2378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2923 .loc 1 2378 1 is_stmt 1 view -0 + 2924 .cfi_startproc + 2925 @ args = 0, pretend = 0, frame = 0 + 2926 @ frame_needed = 0, uses_anonymous_args = 0 + 2927 @ link register save eliminated. +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef status = HAL_OK; + 2928 .loc 1 2379 3 view .LVU939 +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 2929 .loc 1 2380 3 view .LVU940 + 2930 .loc 1 2380 24 is_stmt 0 view .LVU941 + 2931 0000 90F82030 ldrb r3, [r0, #32] @ zero_extendqisi2 + 2932 .LVL229: +2381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 2933 .loc 1 2382 3 is_stmt 1 view .LVU942 + 2934 .loc 1 2382 38 is_stmt 0 view .LVU943 + 2935 0004 013B subs r3, r3, #1 + 2936 .LVL230: + 2937 .loc 1 2382 38 view .LVU944 + 2938 0006 DBB2 uxtb r3, r3 + 2939 .loc 1 2382 6 view .LVU945 + 2940 0008 012B cmp r3, #1 + 2941 000a 05D9 bls .L224 +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +2384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset CAN error code */ +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode = 0U; +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 2942 .loc 1 2391 5 is_stmt 1 view .LVU946 + 2943 .loc 1 2391 9 is_stmt 0 view .LVU947 + 2944 000c 436A ldr r3, [r0, #36] + 2945 .loc 1 2391 21 view .LVU948 + 2946 000e 43F48023 orr r3, r3, #262144 + 2947 0012 4362 str r3, [r0, #36] +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 2948 .loc 1 2393 5 is_stmt 1 view .LVU949 + 2949 .LVL231: + ARM GAS /tmp/ccqPwHQi.s page 120 + + + 2950 .loc 1 2393 12 is_stmt 0 view .LVU950 + 2951 0014 0120 movs r0, #1 + 2952 .LVL232: +2394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return the status */ +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 2953 .loc 1 2397 3 is_stmt 1 view .LVU951 +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2954 .loc 1 2398 1 is_stmt 0 view .LVU952 + 2955 0016 7047 bx lr + 2956 .LVL233: + 2957 .L224: +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2958 .loc 1 2386 5 is_stmt 1 view .LVU953 +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2959 .loc 1 2386 21 is_stmt 0 view .LVU954 + 2960 0018 0023 movs r3, #0 + 2961 001a 4362 str r3, [r0, #36] +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 2962 .loc 1 2379 21 view .LVU955 + 2963 001c 1846 mov r0, r3 + 2964 .LVL234: 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+ 43:Drivers/CMSIS/Include/core_cm4.h **** + 44:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 8.5, object/function definition in header file.
    + 45:Drivers/CMSIS/Include/core_cm4.h **** Function definitions in header files are used to allow 'inlining'. + 46:Drivers/CMSIS/Include/core_cm4.h **** + 47:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + 48:Drivers/CMSIS/Include/core_cm4.h **** Unions are used for effective representation of core registers. + 49:Drivers/CMSIS/Include/core_cm4.h **** + 50:Drivers/CMSIS/Include/core_cm4.h **** \li Advisory Rule 19.7, Function-like macro defined.
    + 51:Drivers/CMSIS/Include/core_cm4.h **** Function-like macros are used to allow more efficient code. + 52:Drivers/CMSIS/Include/core_cm4.h **** */ + 53:Drivers/CMSIS/Include/core_cm4.h **** + 54:Drivers/CMSIS/Include/core_cm4.h **** + 55:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* + 56:Drivers/CMSIS/Include/core_cm4.h **** * CMSIS definitions + 57:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ + 58:Drivers/CMSIS/Include/core_cm4.h **** /** + 59:Drivers/CMSIS/Include/core_cm4.h **** \ingroup Cortex_M4 + 60:Drivers/CMSIS/Include/core_cm4.h **** @{ + 61:Drivers/CMSIS/Include/core_cm4.h **** */ + 62:Drivers/CMSIS/Include/core_cm4.h **** + 63:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_version.h" + 64:Drivers/CMSIS/Include/core_cm4.h **** + 65:Drivers/CMSIS/Include/core_cm4.h **** /* CMSIS CM4 definitions */ + 66:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C + 67:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C + 68:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + 69:Drivers/CMSIS/Include/core_cm4.h **** __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL + 70:Drivers/CMSIS/Include/core_cm4.h **** + 71:Drivers/CMSIS/Include/core_cm4.h **** #define __CORTEX_M (4U) /*!< Cortex-M Core */ + 72:Drivers/CMSIS/Include/core_cm4.h **** + 73:Drivers/CMSIS/Include/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not. + 74:Drivers/CMSIS/Include/core_cm4.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun + 75:Drivers/CMSIS/Include/core_cm4.h **** */ + 76:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __CC_ARM ) + 77:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TARGET_FPU_VFP + 78:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 79:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 80:Drivers/CMSIS/Include/core_cm4.h **** #else + 81:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 82:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 83:Drivers/CMSIS/Include/core_cm4.h **** #endif + 84:Drivers/CMSIS/Include/core_cm4.h **** #else + 85:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 86:Drivers/CMSIS/Include/core_cm4.h **** #endif + ARM GAS /tmp/ccPJu8Ry.s page 3 + + + 87:Drivers/CMSIS/Include/core_cm4.h **** + 88:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 89:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARM_PCS_VFP + 90:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 91:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 92:Drivers/CMSIS/Include/core_cm4.h **** #else + 93:Drivers/CMSIS/Include/core_cm4.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN + 94:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 95:Drivers/CMSIS/Include/core_cm4.h **** #endif + 96:Drivers/CMSIS/Include/core_cm4.h **** #else + 97:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 98:Drivers/CMSIS/Include/core_cm4.h **** #endif + 99:Drivers/CMSIS/Include/core_cm4.h **** + 100:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __GNUC__ ) + 101:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 102:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 103:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 104:Drivers/CMSIS/Include/core_cm4.h **** #else + 105:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 106:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 107:Drivers/CMSIS/Include/core_cm4.h **** #endif + 108:Drivers/CMSIS/Include/core_cm4.h **** #else + 109:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 110:Drivers/CMSIS/Include/core_cm4.h **** #endif + 111:Drivers/CMSIS/Include/core_cm4.h **** + 112:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __ICCARM__ ) + 113:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARMVFP__ + 114:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 115:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 116:Drivers/CMSIS/Include/core_cm4.h **** #else + 117:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 118:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 119:Drivers/CMSIS/Include/core_cm4.h **** #endif + 120:Drivers/CMSIS/Include/core_cm4.h **** #else + 121:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 122:Drivers/CMSIS/Include/core_cm4.h **** #endif + 123:Drivers/CMSIS/Include/core_cm4.h **** + 124:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TI_ARM__ ) + 125:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TI_VFP_SUPPORT__ + 126:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 127:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 128:Drivers/CMSIS/Include/core_cm4.h **** #else + 129:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 130:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 131:Drivers/CMSIS/Include/core_cm4.h **** #endif + 132:Drivers/CMSIS/Include/core_cm4.h **** #else + 133:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 134:Drivers/CMSIS/Include/core_cm4.h **** #endif + 135:Drivers/CMSIS/Include/core_cm4.h **** + 136:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TASKING__ ) + 137:Drivers/CMSIS/Include/core_cm4.h **** #if defined __FPU_VFP__ + 138:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 139:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 140:Drivers/CMSIS/Include/core_cm4.h **** #else + 141:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 142:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 143:Drivers/CMSIS/Include/core_cm4.h **** #endif + ARM GAS /tmp/ccPJu8Ry.s page 4 + + + 144:Drivers/CMSIS/Include/core_cm4.h **** #else + 145:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 146:Drivers/CMSIS/Include/core_cm4.h **** #endif + 147:Drivers/CMSIS/Include/core_cm4.h **** + 148:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __CSMC__ ) + 149:Drivers/CMSIS/Include/core_cm4.h **** #if ( __CSMC__ & 0x400U) + 150:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 151:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 152:Drivers/CMSIS/Include/core_cm4.h **** #else + 153:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 154:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 155:Drivers/CMSIS/Include/core_cm4.h **** #endif + 156:Drivers/CMSIS/Include/core_cm4.h **** #else + 157:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 158:Drivers/CMSIS/Include/core_cm4.h **** #endif + 159:Drivers/CMSIS/Include/core_cm4.h **** + 160:Drivers/CMSIS/Include/core_cm4.h **** #endif + 161:Drivers/CMSIS/Include/core_cm4.h **** + 162:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + 163:Drivers/CMSIS/Include/core_cm4.h **** + 164:Drivers/CMSIS/Include/core_cm4.h **** + 165:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus + 166:Drivers/CMSIS/Include/core_cm4.h **** } + 167:Drivers/CMSIS/Include/core_cm4.h **** #endif + 168:Drivers/CMSIS/Include/core_cm4.h **** + 169:Drivers/CMSIS/Include/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */ + 170:Drivers/CMSIS/Include/core_cm4.h **** + 171:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CMSIS_GENERIC + 172:Drivers/CMSIS/Include/core_cm4.h **** + 173:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT + 174:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT + 175:Drivers/CMSIS/Include/core_cm4.h **** + 176:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus + 177:Drivers/CMSIS/Include/core_cm4.h **** extern "C" { + 178:Drivers/CMSIS/Include/core_cm4.h **** #endif + 179:Drivers/CMSIS/Include/core_cm4.h **** + 180:Drivers/CMSIS/Include/core_cm4.h **** /* check device defines and use defaults */ + 181:Drivers/CMSIS/Include/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES + 182:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CM4_REV + 183:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_REV 0x0000U + 184:Drivers/CMSIS/Include/core_cm4.h **** #warning "__CM4_REV not defined in device header file; using default!" + 185:Drivers/CMSIS/Include/core_cm4.h **** #endif + 186:Drivers/CMSIS/Include/core_cm4.h **** + 187:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __FPU_PRESENT + 188:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_PRESENT 0U + 189:Drivers/CMSIS/Include/core_cm4.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" + 190:Drivers/CMSIS/Include/core_cm4.h **** #endif + 191:Drivers/CMSIS/Include/core_cm4.h **** + 192:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __MPU_PRESENT + 193:Drivers/CMSIS/Include/core_cm4.h **** #define __MPU_PRESENT 0U + 194:Drivers/CMSIS/Include/core_cm4.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" + 195:Drivers/CMSIS/Include/core_cm4.h **** #endif + 196:Drivers/CMSIS/Include/core_cm4.h **** + 197:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __NVIC_PRIO_BITS + 198:Drivers/CMSIS/Include/core_cm4.h **** #define __NVIC_PRIO_BITS 3U + 199:Drivers/CMSIS/Include/core_cm4.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 200:Drivers/CMSIS/Include/core_cm4.h **** #endif + ARM GAS /tmp/ccPJu8Ry.s page 5 + + + 201:Drivers/CMSIS/Include/core_cm4.h **** + 202:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __Vendor_SysTickConfig + 203:Drivers/CMSIS/Include/core_cm4.h **** #define __Vendor_SysTickConfig 0U + 204:Drivers/CMSIS/Include/core_cm4.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 205:Drivers/CMSIS/Include/core_cm4.h **** #endif + 206:Drivers/CMSIS/Include/core_cm4.h **** #endif + 207:Drivers/CMSIS/Include/core_cm4.h **** + 208:Drivers/CMSIS/Include/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */ + 209:Drivers/CMSIS/Include/core_cm4.h **** /** + 210:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 211:Drivers/CMSIS/Include/core_cm4.h **** + 212:Drivers/CMSIS/Include/core_cm4.h **** IO Type Qualifiers are used + 213:Drivers/CMSIS/Include/core_cm4.h **** \li to specify the access to peripheral variables. + 214:Drivers/CMSIS/Include/core_cm4.h **** \li for automatic generation of peripheral register debug information. + 215:Drivers/CMSIS/Include/core_cm4.h **** */ + 216:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus + 217:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 218:Drivers/CMSIS/Include/core_cm4.h **** #else + 219:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 220:Drivers/CMSIS/Include/core_cm4.h **** #endif + 221:Drivers/CMSIS/Include/core_cm4.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 222:Drivers/CMSIS/Include/core_cm4.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 223:Drivers/CMSIS/Include/core_cm4.h **** + 224:Drivers/CMSIS/Include/core_cm4.h **** /* following defines should be used for structure members */ + 225:Drivers/CMSIS/Include/core_cm4.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 226:Drivers/CMSIS/Include/core_cm4.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + 227:Drivers/CMSIS/Include/core_cm4.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 228:Drivers/CMSIS/Include/core_cm4.h **** + 229:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group Cortex_M4 */ + 230:Drivers/CMSIS/Include/core_cm4.h **** + 231:Drivers/CMSIS/Include/core_cm4.h **** + 232:Drivers/CMSIS/Include/core_cm4.h **** + 233:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* + 234:Drivers/CMSIS/Include/core_cm4.h **** * Register Abstraction + 235:Drivers/CMSIS/Include/core_cm4.h **** Core Register contain: + 236:Drivers/CMSIS/Include/core_cm4.h **** - Core Register + 237:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Register + 238:Drivers/CMSIS/Include/core_cm4.h **** - Core SCB Register + 239:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Register + 240:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Register + 241:Drivers/CMSIS/Include/core_cm4.h **** - Core MPU Register + 242:Drivers/CMSIS/Include/core_cm4.h **** - Core FPU Register + 243:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ + 244:Drivers/CMSIS/Include/core_cm4.h **** /** + 245:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 246:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 247:Drivers/CMSIS/Include/core_cm4.h **** */ + 248:Drivers/CMSIS/Include/core_cm4.h **** + 249:Drivers/CMSIS/Include/core_cm4.h **** /** + 250:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 251:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CORE Status and Control Registers + 252:Drivers/CMSIS/Include/core_cm4.h **** \brief Core Register type definitions. + 253:Drivers/CMSIS/Include/core_cm4.h **** @{ + 254:Drivers/CMSIS/Include/core_cm4.h **** */ + 255:Drivers/CMSIS/Include/core_cm4.h **** + 256:Drivers/CMSIS/Include/core_cm4.h **** /** + 257:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Application Program Status Register (APSR). + ARM GAS /tmp/ccPJu8Ry.s page 6 + + + 258:Drivers/CMSIS/Include/core_cm4.h **** */ + 259:Drivers/CMSIS/Include/core_cm4.h **** typedef union + 260:Drivers/CMSIS/Include/core_cm4.h **** { + 261:Drivers/CMSIS/Include/core_cm4.h **** struct + 262:Drivers/CMSIS/Include/core_cm4.h **** { + 263:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + 264:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 265:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + 266:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 267:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 268:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 269:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 270:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 271:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ + 272:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ + 273:Drivers/CMSIS/Include/core_cm4.h **** } APSR_Type; + 274:Drivers/CMSIS/Include/core_cm4.h **** + 275:Drivers/CMSIS/Include/core_cm4.h **** /* APSR Register Definitions */ + 276:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Pos 31U /*!< APSR + 277:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 278:Drivers/CMSIS/Include/core_cm4.h **** + 279:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Pos 30U /*!< APSR + 280:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 281:Drivers/CMSIS/Include/core_cm4.h **** + 282:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Pos 29U /*!< APSR + 283:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + 284:Drivers/CMSIS/Include/core_cm4.h **** + 285:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Pos 28U /*!< APSR + 286:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 287:Drivers/CMSIS/Include/core_cm4.h **** + 288:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Pos 27U /*!< APSR + 289:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR + 290:Drivers/CMSIS/Include/core_cm4.h **** + 291:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Pos 16U /*!< APSR + 292:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR + 293:Drivers/CMSIS/Include/core_cm4.h **** + 294:Drivers/CMSIS/Include/core_cm4.h **** + 295:Drivers/CMSIS/Include/core_cm4.h **** /** + 296:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 297:Drivers/CMSIS/Include/core_cm4.h **** */ + 298:Drivers/CMSIS/Include/core_cm4.h **** typedef union + 299:Drivers/CMSIS/Include/core_cm4.h **** { + 300:Drivers/CMSIS/Include/core_cm4.h **** struct + 301:Drivers/CMSIS/Include/core_cm4.h **** { + 302:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 303:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 304:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ + 305:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ + 306:Drivers/CMSIS/Include/core_cm4.h **** } IPSR_Type; + 307:Drivers/CMSIS/Include/core_cm4.h **** + 308:Drivers/CMSIS/Include/core_cm4.h **** /* IPSR Register Definitions */ + 309:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 310:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 311:Drivers/CMSIS/Include/core_cm4.h **** + 312:Drivers/CMSIS/Include/core_cm4.h **** + 313:Drivers/CMSIS/Include/core_cm4.h **** /** + 314:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + ARM GAS /tmp/ccPJu8Ry.s page 7 + + + 315:Drivers/CMSIS/Include/core_cm4.h **** */ + 316:Drivers/CMSIS/Include/core_cm4.h **** typedef union + 317:Drivers/CMSIS/Include/core_cm4.h **** { + 318:Drivers/CMSIS/Include/core_cm4.h **** struct + 319:Drivers/CMSIS/Include/core_cm4.h **** { + 320:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + 322:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + 323:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 324:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + 325:Drivers/CMSIS/Include/core_cm4.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ + 326:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + 327:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 328:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 329:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 330:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 331:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 332:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ + 333:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ + 334:Drivers/CMSIS/Include/core_cm4.h **** } xPSR_Type; + 335:Drivers/CMSIS/Include/core_cm4.h **** + 336:Drivers/CMSIS/Include/core_cm4.h **** /* xPSR Register Definitions */ + 337:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Pos 31U /*!< xPSR + 338:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + 339:Drivers/CMSIS/Include/core_cm4.h **** + 340:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Pos 30U /*!< xPSR + 341:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 342:Drivers/CMSIS/Include/core_cm4.h **** + 343:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Pos 29U /*!< xPSR + 344:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 345:Drivers/CMSIS/Include/core_cm4.h **** + 346:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Pos 28U /*!< xPSR + 347:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 348:Drivers/CMSIS/Include/core_cm4.h **** + 349:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Pos 27U /*!< xPSR + 350:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR + 351:Drivers/CMSIS/Include/core_cm4.h **** + 352:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR + 353:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR + 354:Drivers/CMSIS/Include/core_cm4.h **** + 355:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Pos 24U /*!< xPSR + 356:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 357:Drivers/CMSIS/Include/core_cm4.h **** + 358:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Pos 16U /*!< xPSR + 359:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR + 360:Drivers/CMSIS/Include/core_cm4.h **** + 361:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR + 362:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR + 363:Drivers/CMSIS/Include/core_cm4.h **** + 364:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 365:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 366:Drivers/CMSIS/Include/core_cm4.h **** + 367:Drivers/CMSIS/Include/core_cm4.h **** + 368:Drivers/CMSIS/Include/core_cm4.h **** /** + 369:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Control Registers (CONTROL). + 370:Drivers/CMSIS/Include/core_cm4.h **** */ + 371:Drivers/CMSIS/Include/core_cm4.h **** typedef union + ARM GAS /tmp/ccPJu8Ry.s page 8 + + + 372:Drivers/CMSIS/Include/core_cm4.h **** { + 373:Drivers/CMSIS/Include/core_cm4.h **** struct + 374:Drivers/CMSIS/Include/core_cm4.h **** { + 375:Drivers/CMSIS/Include/core_cm4.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + 376:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 377:Drivers/CMSIS/Include/core_cm4.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + 378:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + 379:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ + 380:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ + 381:Drivers/CMSIS/Include/core_cm4.h **** } CONTROL_Type; + 382:Drivers/CMSIS/Include/core_cm4.h **** + 383:Drivers/CMSIS/Include/core_cm4.h **** /* CONTROL Register Definitions */ + 384:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT + 385:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT + 386:Drivers/CMSIS/Include/core_cm4.h **** + 387:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 388:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 389:Drivers/CMSIS/Include/core_cm4.h **** + 390:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT + 391:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT + 392:Drivers/CMSIS/Include/core_cm4.h **** + 393:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CORE */ + 394:Drivers/CMSIS/Include/core_cm4.h **** + 395:Drivers/CMSIS/Include/core_cm4.h **** + 396:Drivers/CMSIS/Include/core_cm4.h **** /** + 397:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 398:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 399:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the NVIC Registers + 400:Drivers/CMSIS/Include/core_cm4.h **** @{ + 401:Drivers/CMSIS/Include/core_cm4.h **** */ + 402:Drivers/CMSIS/Include/core_cm4.h **** + 403:Drivers/CMSIS/Include/core_cm4.h **** /** + 404:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 405:Drivers/CMSIS/Include/core_cm4.h **** */ + 406:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 407:Drivers/CMSIS/Include/core_cm4.h **** { + 408:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 409:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[24U]; + 410:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + 411:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RSERVED1[24U]; + 412:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 413:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[24U]; + 414:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + 415:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[24U]; + 416:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + 417:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[56U]; + 418:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi + 419:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[644U]; + 420:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis + 421:Drivers/CMSIS/Include/core_cm4.h **** } NVIC_Type; + 422:Drivers/CMSIS/Include/core_cm4.h **** + 423:Drivers/CMSIS/Include/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */ + 424:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I + 425:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I + 426:Drivers/CMSIS/Include/core_cm4.h **** + 427:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */ + 428:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccPJu8Ry.s page 9 + + + 429:Drivers/CMSIS/Include/core_cm4.h **** + 430:Drivers/CMSIS/Include/core_cm4.h **** /** + 431:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 432:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 433:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control Block Registers + 434:Drivers/CMSIS/Include/core_cm4.h **** @{ + 435:Drivers/CMSIS/Include/core_cm4.h **** */ + 436:Drivers/CMSIS/Include/core_cm4.h **** + 437:Drivers/CMSIS/Include/core_cm4.h **** /** + 438:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control Block (SCB). + 439:Drivers/CMSIS/Include/core_cm4.h **** */ + 440:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 441:Drivers/CMSIS/Include/core_cm4.h **** { + 442:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 443:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 444:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + 445:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 446:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 447:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 448:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe + 449:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 450:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist + 451:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + 452:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + 453:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register + 454:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + 455:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register + 456:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + 457:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + 458:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + 459:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + 460:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis + 461:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[5U]; + 462:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis + 463:Drivers/CMSIS/Include/core_cm4.h **** } SCB_Type; + 464:Drivers/CMSIS/Include/core_cm4.h **** + 465:Drivers/CMSIS/Include/core_cm4.h **** /* SCB CPUID Register Definitions */ + 466:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 467:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 468:Drivers/CMSIS/Include/core_cm4.h **** + 469:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 470:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 471:Drivers/CMSIS/Include/core_cm4.h **** + 472:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 473:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 474:Drivers/CMSIS/Include/core_cm4.h **** + 475:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 476:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 477:Drivers/CMSIS/Include/core_cm4.h **** + 478:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 479:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 480:Drivers/CMSIS/Include/core_cm4.h **** + 481:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */ + 482:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + 483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + 484:Drivers/CMSIS/Include/core_cm4.h **** + 485:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + ARM GAS /tmp/ccPJu8Ry.s page 10 + + + 486:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + 487:Drivers/CMSIS/Include/core_cm4.h **** + 488:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 489:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 490:Drivers/CMSIS/Include/core_cm4.h **** + 491:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 492:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 493:Drivers/CMSIS/Include/core_cm4.h **** + 494:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 495:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 496:Drivers/CMSIS/Include/core_cm4.h **** + 497:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 498:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 499:Drivers/CMSIS/Include/core_cm4.h **** + 500:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 501:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 502:Drivers/CMSIS/Include/core_cm4.h **** + 503:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 504:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 505:Drivers/CMSIS/Include/core_cm4.h **** + 506:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB + 507:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB + 508:Drivers/CMSIS/Include/core_cm4.h **** + 509:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 510:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 511:Drivers/CMSIS/Include/core_cm4.h **** + 512:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */ + 513:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB + 514:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB + 515:Drivers/CMSIS/Include/core_cm4.h **** + 516:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 517:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 518:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 519:Drivers/CMSIS/Include/core_cm4.h **** + 520:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 521:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 522:Drivers/CMSIS/Include/core_cm4.h **** + 523:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 524:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + 525:Drivers/CMSIS/Include/core_cm4.h **** + 526:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB + 527:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB + 528:Drivers/CMSIS/Include/core_cm4.h **** + 529:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 530:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 531:Drivers/CMSIS/Include/core_cm4.h **** + 532:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 533:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 534:Drivers/CMSIS/Include/core_cm4.h **** + 535:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB + 536:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB + 537:Drivers/CMSIS/Include/core_cm4.h **** + 538:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Control Register Definitions */ + 539:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + 540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 541:Drivers/CMSIS/Include/core_cm4.h **** + 542:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + ARM GAS /tmp/ccPJu8Ry.s page 11 + + + 543:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + 544:Drivers/CMSIS/Include/core_cm4.h **** + 545:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 546:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + 547:Drivers/CMSIS/Include/core_cm4.h **** + 548:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configuration Control Register Definitions */ + 549:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 550:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 551:Drivers/CMSIS/Include/core_cm4.h **** + 552:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB + 553:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB + 554:Drivers/CMSIS/Include/core_cm4.h **** + 555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB + 556:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB + 557:Drivers/CMSIS/Include/core_cm4.h **** + 558:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 559:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + 560:Drivers/CMSIS/Include/core_cm4.h **** + 561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB + 562:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB + 563:Drivers/CMSIS/Include/core_cm4.h **** + 564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB + 565:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB + 566:Drivers/CMSIS/Include/core_cm4.h **** + 567:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */ + 568:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB + 569:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB + 570:Drivers/CMSIS/Include/core_cm4.h **** + 571:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB + 572:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB + 573:Drivers/CMSIS/Include/core_cm4.h **** + 574:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB + 575:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB + 576:Drivers/CMSIS/Include/core_cm4.h **** + 577:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 578:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 579:Drivers/CMSIS/Include/core_cm4.h **** + 580:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB + 581:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB + 582:Drivers/CMSIS/Include/core_cm4.h **** + 583:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB + 584:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB + 585:Drivers/CMSIS/Include/core_cm4.h **** + 586:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB + 587:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB + 588:Drivers/CMSIS/Include/core_cm4.h **** + 589:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB + 590:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB + 591:Drivers/CMSIS/Include/core_cm4.h **** + 592:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB + 593:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB + 594:Drivers/CMSIS/Include/core_cm4.h **** + 595:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB + 596:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB + 597:Drivers/CMSIS/Include/core_cm4.h **** + 598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB + 599:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB + ARM GAS /tmp/ccPJu8Ry.s page 12 + + + 600:Drivers/CMSIS/Include/core_cm4.h **** + 601:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB + 602:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB + 603:Drivers/CMSIS/Include/core_cm4.h **** + 604:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB + 605:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB + 606:Drivers/CMSIS/Include/core_cm4.h **** + 607:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB + 608:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB + 609:Drivers/CMSIS/Include/core_cm4.h **** + 610:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */ + 611:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB + 612:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB + 613:Drivers/CMSIS/Include/core_cm4.h **** + 614:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB + 615:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB + 616:Drivers/CMSIS/Include/core_cm4.h **** + 617:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB + 618:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB + 619:Drivers/CMSIS/Include/core_cm4.h **** + 620:Drivers/CMSIS/Include/core_cm4.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ + 621:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB + 622:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB + 623:Drivers/CMSIS/Include/core_cm4.h **** + 624:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB + 625:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB + 626:Drivers/CMSIS/Include/core_cm4.h **** + 627:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB + 628:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB + 629:Drivers/CMSIS/Include/core_cm4.h **** + 630:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB + 631:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB + 632:Drivers/CMSIS/Include/core_cm4.h **** + 633:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB + 634:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB + 635:Drivers/CMSIS/Include/core_cm4.h **** + 636:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB + 637:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB + 638:Drivers/CMSIS/Include/core_cm4.h **** + 639:Drivers/CMSIS/Include/core_cm4.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ + 640:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB + 641:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB + 642:Drivers/CMSIS/Include/core_cm4.h **** + 643:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB + 644:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB + 645:Drivers/CMSIS/Include/core_cm4.h **** + 646:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB + 647:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB + 648:Drivers/CMSIS/Include/core_cm4.h **** + 649:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB + 650:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB + 651:Drivers/CMSIS/Include/core_cm4.h **** + 652:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB + 653:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB + 654:Drivers/CMSIS/Include/core_cm4.h **** + 655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB + 656:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB + ARM GAS /tmp/ccPJu8Ry.s page 13 + + + 657:Drivers/CMSIS/Include/core_cm4.h **** + 658:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB + 659:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB + 660:Drivers/CMSIS/Include/core_cm4.h **** + 661:Drivers/CMSIS/Include/core_cm4.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ + 662:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB + 663:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB + 664:Drivers/CMSIS/Include/core_cm4.h **** + 665:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB + 666:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB + 667:Drivers/CMSIS/Include/core_cm4.h **** + 668:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB + 669:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB + 670:Drivers/CMSIS/Include/core_cm4.h **** + 671:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB + 672:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB + 673:Drivers/CMSIS/Include/core_cm4.h **** + 674:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB + 675:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB + 676:Drivers/CMSIS/Include/core_cm4.h **** + 677:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB + 678:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB + 679:Drivers/CMSIS/Include/core_cm4.h **** + 680:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */ + 681:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB + 682:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB + 683:Drivers/CMSIS/Include/core_cm4.h **** + 684:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB + 685:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB + 686:Drivers/CMSIS/Include/core_cm4.h **** + 687:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB + 688:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB + 689:Drivers/CMSIS/Include/core_cm4.h **** + 690:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */ + 691:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB + 692:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB + 693:Drivers/CMSIS/Include/core_cm4.h **** + 694:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB + 695:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB + 696:Drivers/CMSIS/Include/core_cm4.h **** + 697:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB + 698:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB + 699:Drivers/CMSIS/Include/core_cm4.h **** + 700:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB + 701:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB + 702:Drivers/CMSIS/Include/core_cm4.h **** + 703:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB + 704:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB + 705:Drivers/CMSIS/Include/core_cm4.h **** + 706:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCB */ + 707:Drivers/CMSIS/Include/core_cm4.h **** + 708:Drivers/CMSIS/Include/core_cm4.h **** + 709:Drivers/CMSIS/Include/core_cm4.h **** /** + 710:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 711:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + 712:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control and ID Register not in the SCB + 713:Drivers/CMSIS/Include/core_cm4.h **** @{ + ARM GAS /tmp/ccPJu8Ry.s page 14 + + + 714:Drivers/CMSIS/Include/core_cm4.h **** */ + 715:Drivers/CMSIS/Include/core_cm4.h **** + 716:Drivers/CMSIS/Include/core_cm4.h **** /** + 717:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control and ID Register not in the SCB. + 718:Drivers/CMSIS/Include/core_cm4.h **** */ + 719:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 720:Drivers/CMSIS/Include/core_cm4.h **** { + 721:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; + 722:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist + 723:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + 724:Drivers/CMSIS/Include/core_cm4.h **** } SCnSCB_Type; + 725:Drivers/CMSIS/Include/core_cm4.h **** + 726:Drivers/CMSIS/Include/core_cm4.h **** /* Interrupt Controller Type Register Definitions */ + 727:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I + 728:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I + 729:Drivers/CMSIS/Include/core_cm4.h **** + 730:Drivers/CMSIS/Include/core_cm4.h **** /* Auxiliary Control Register Definitions */ + 731:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: + 732:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: + 733:Drivers/CMSIS/Include/core_cm4.h **** + 734:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: + 735:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: + 736:Drivers/CMSIS/Include/core_cm4.h **** + 737:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: + 738:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: + 739:Drivers/CMSIS/Include/core_cm4.h **** + 740:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: + 741:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: + 742:Drivers/CMSIS/Include/core_cm4.h **** + 743:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: + 744:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: + 745:Drivers/CMSIS/Include/core_cm4.h **** + 746:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */ + 747:Drivers/CMSIS/Include/core_cm4.h **** + 748:Drivers/CMSIS/Include/core_cm4.h **** + 749:Drivers/CMSIS/Include/core_cm4.h **** /** + 750:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 751:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 752:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Timer Registers. + 753:Drivers/CMSIS/Include/core_cm4.h **** @{ + 754:Drivers/CMSIS/Include/core_cm4.h **** */ + 755:Drivers/CMSIS/Include/core_cm4.h **** + 756:Drivers/CMSIS/Include/core_cm4.h **** /** + 757:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Timer (SysTick). + 758:Drivers/CMSIS/Include/core_cm4.h **** */ + 759:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 760:Drivers/CMSIS/Include/core_cm4.h **** { + 761:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 762:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 763:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 764:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 765:Drivers/CMSIS/Include/core_cm4.h **** } SysTick_Type; + 766:Drivers/CMSIS/Include/core_cm4.h **** + 767:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Control / Status Register Definitions */ + 768:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 769:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 770:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccPJu8Ry.s page 15 + + + 771:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + 772:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 773:Drivers/CMSIS/Include/core_cm4.h **** + 774:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + 775:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 776:Drivers/CMSIS/Include/core_cm4.h **** + 777:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 778:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 779:Drivers/CMSIS/Include/core_cm4.h **** + 780:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Reload Register Definitions */ + 781:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 782:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 783:Drivers/CMSIS/Include/core_cm4.h **** + 784:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Current Register Definitions */ + 785:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 786:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 787:Drivers/CMSIS/Include/core_cm4.h **** + 788:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Calibration Register Definitions */ + 789:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 790:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + 791:Drivers/CMSIS/Include/core_cm4.h **** + 792:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 793:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 794:Drivers/CMSIS/Include/core_cm4.h **** + 795:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 796:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 797:Drivers/CMSIS/Include/core_cm4.h **** + 798:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SysTick */ + 799:Drivers/CMSIS/Include/core_cm4.h **** + 800:Drivers/CMSIS/Include/core_cm4.h **** + 801:Drivers/CMSIS/Include/core_cm4.h **** /** + 802:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 803:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + 804:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + 805:Drivers/CMSIS/Include/core_cm4.h **** @{ + 806:Drivers/CMSIS/Include/core_cm4.h **** */ + 807:Drivers/CMSIS/Include/core_cm4.h **** + 808:Drivers/CMSIS/Include/core_cm4.h **** /** + 809:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + 810:Drivers/CMSIS/Include/core_cm4.h **** */ + 811:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 812:Drivers/CMSIS/Include/core_cm4.h **** { + 813:Drivers/CMSIS/Include/core_cm4.h **** __OM union + 814:Drivers/CMSIS/Include/core_cm4.h **** { + 815:Drivers/CMSIS/Include/core_cm4.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + 816:Drivers/CMSIS/Include/core_cm4.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + 817:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + 818:Drivers/CMSIS/Include/core_cm4.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + 819:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[864U]; + 820:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + 821:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[15U]; + 822:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + 823:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[15U]; + 824:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + 825:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[29U]; + 826:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * + 827:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + ARM GAS /tmp/ccPJu8Ry.s page 16 + + + 828:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg + 829:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[43U]; + 830:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + 831:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + 832:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[6U]; + 833:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re + 834:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re + 835:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re + 836:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re + 837:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re + 838:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re + 839:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re + 840:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re + 841:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re + 842:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re + 843:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re + 844:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re + 845:Drivers/CMSIS/Include/core_cm4.h **** } ITM_Type; + 846:Drivers/CMSIS/Include/core_cm4.h **** + 847:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Privilege Register Definitions */ + 848:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM + 849:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM + 850:Drivers/CMSIS/Include/core_cm4.h **** + 851:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Control Register Definitions */ + 852:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM + 853:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM + 854:Drivers/CMSIS/Include/core_cm4.h **** + 855:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM + 856:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM + 857:Drivers/CMSIS/Include/core_cm4.h **** + 858:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM + 859:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM + 860:Drivers/CMSIS/Include/core_cm4.h **** + 861:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM + 862:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM + 863:Drivers/CMSIS/Include/core_cm4.h **** + 864:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM + 865:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM + 866:Drivers/CMSIS/Include/core_cm4.h **** + 867:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM + 868:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM + 869:Drivers/CMSIS/Include/core_cm4.h **** + 870:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM + 871:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM + 872:Drivers/CMSIS/Include/core_cm4.h **** + 873:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM + 874:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM + 875:Drivers/CMSIS/Include/core_cm4.h **** + 876:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM + 877:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM + 878:Drivers/CMSIS/Include/core_cm4.h **** + 879:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Write Register Definitions */ + 880:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM + 881:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM + 882:Drivers/CMSIS/Include/core_cm4.h **** + 883:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Read Register Definitions */ + 884:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM + ARM GAS /tmp/ccPJu8Ry.s page 17 + + + 885:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM + 886:Drivers/CMSIS/Include/core_cm4.h **** + 887:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Mode Control Register Definitions */ + 888:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM + 889:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM + 890:Drivers/CMSIS/Include/core_cm4.h **** + 891:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Lock Status Register Definitions */ + 892:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM + 893:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM + 894:Drivers/CMSIS/Include/core_cm4.h **** + 895:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM + 896:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM + 897:Drivers/CMSIS/Include/core_cm4.h **** + 898:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM + 899:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM + 900:Drivers/CMSIS/Include/core_cm4.h **** + 901:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */ + 902:Drivers/CMSIS/Include/core_cm4.h **** + 903:Drivers/CMSIS/Include/core_cm4.h **** + 904:Drivers/CMSIS/Include/core_cm4.h **** /** + 905:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 906:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + 907:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) + 908:Drivers/CMSIS/Include/core_cm4.h **** @{ + 909:Drivers/CMSIS/Include/core_cm4.h **** */ + 910:Drivers/CMSIS/Include/core_cm4.h **** + 911:Drivers/CMSIS/Include/core_cm4.h **** /** + 912:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + 913:Drivers/CMSIS/Include/core_cm4.h **** */ + 914:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 915:Drivers/CMSIS/Include/core_cm4.h **** { + 916:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + 917:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + 918:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + 919:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe + 920:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + 921:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + 922:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe + 923:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register + 924:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + 925:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + 926:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + 927:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; + 928:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + 929:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + 930:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + 931:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[1U]; + 932:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + 933:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + 934:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + 935:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[1U]; + 936:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + 937:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + 938:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + 939:Drivers/CMSIS/Include/core_cm4.h **** } DWT_Type; + 940:Drivers/CMSIS/Include/core_cm4.h **** + 941:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Control Register Definitions */ + ARM GAS /tmp/ccPJu8Ry.s page 18 + + + 942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR + 943:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR + 944:Drivers/CMSIS/Include/core_cm4.h **** + 945:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR + 946:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR + 947:Drivers/CMSIS/Include/core_cm4.h **** + 948:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR + 949:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR + 950:Drivers/CMSIS/Include/core_cm4.h **** + 951:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR + 952:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR + 953:Drivers/CMSIS/Include/core_cm4.h **** + 954:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR + 955:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR + 956:Drivers/CMSIS/Include/core_cm4.h **** + 957:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR + 958:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR + 959:Drivers/CMSIS/Include/core_cm4.h **** + 960:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR + 961:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR + 962:Drivers/CMSIS/Include/core_cm4.h **** + 963:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR + 964:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR + 965:Drivers/CMSIS/Include/core_cm4.h **** + 966:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR + 967:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR + 968:Drivers/CMSIS/Include/core_cm4.h **** + 969:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR + 970:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR + 971:Drivers/CMSIS/Include/core_cm4.h **** + 972:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR + 973:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR + 974:Drivers/CMSIS/Include/core_cm4.h **** + 975:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR + 976:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR + 977:Drivers/CMSIS/Include/core_cm4.h **** + 978:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR + 979:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR + 980:Drivers/CMSIS/Include/core_cm4.h **** + 981:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR + 982:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR + 983:Drivers/CMSIS/Include/core_cm4.h **** + 984:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR + 985:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR + 986:Drivers/CMSIS/Include/core_cm4.h **** + 987:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR + 988:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR + 989:Drivers/CMSIS/Include/core_cm4.h **** + 990:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR + 991:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR + 992:Drivers/CMSIS/Include/core_cm4.h **** + 993:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR + 994:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR + 995:Drivers/CMSIS/Include/core_cm4.h **** + 996:Drivers/CMSIS/Include/core_cm4.h **** /* DWT CPI Count Register Definitions */ + 997:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI + 998:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI + ARM GAS /tmp/ccPJu8Ry.s page 19 + + + 999:Drivers/CMSIS/Include/core_cm4.h **** +1000:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */ +1001:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC +1002:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC +1003:Drivers/CMSIS/Include/core_cm4.h **** +1004:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Sleep Count Register Definitions */ +1005:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE +1006:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE +1007:Drivers/CMSIS/Include/core_cm4.h **** +1008:Drivers/CMSIS/Include/core_cm4.h **** /* DWT LSU Count Register Definitions */ +1009:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU +1010:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU +1011:Drivers/CMSIS/Include/core_cm4.h **** +1012:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */ +1013:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL +1014:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL +1015:Drivers/CMSIS/Include/core_cm4.h **** +1016:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Mask Register Definitions */ +1017:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS +1018:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS +1019:Drivers/CMSIS/Include/core_cm4.h **** +1020:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Function Register Definitions */ +1021:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN +1022:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN +1023:Drivers/CMSIS/Include/core_cm4.h **** +1024:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN +1025:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN +1026:Drivers/CMSIS/Include/core_cm4.h **** +1027:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN +1028:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN +1029:Drivers/CMSIS/Include/core_cm4.h **** +1030:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN +1031:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN +1032:Drivers/CMSIS/Include/core_cm4.h **** +1033:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN +1034:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN +1035:Drivers/CMSIS/Include/core_cm4.h **** +1036:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN +1037:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN +1038:Drivers/CMSIS/Include/core_cm4.h **** +1039:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN +1040:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN +1041:Drivers/CMSIS/Include/core_cm4.h **** +1042:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN +1043:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN +1044:Drivers/CMSIS/Include/core_cm4.h **** +1045:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN +1046:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN +1047:Drivers/CMSIS/Include/core_cm4.h **** +1048:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */ +1049:Drivers/CMSIS/Include/core_cm4.h **** +1050:Drivers/CMSIS/Include/core_cm4.h **** +1051:Drivers/CMSIS/Include/core_cm4.h **** /** +1052:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1053:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) +1054:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Trace Port Interface (TPI) +1055:Drivers/CMSIS/Include/core_cm4.h **** @{ + ARM GAS /tmp/ccPJu8Ry.s page 20 + + +1056:Drivers/CMSIS/Include/core_cm4.h **** */ +1057:Drivers/CMSIS/Include/core_cm4.h **** +1058:Drivers/CMSIS/Include/core_cm4.h **** /** +1059:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Trace Port Interface Register (TPI). +1060:Drivers/CMSIS/Include/core_cm4.h **** */ +1061:Drivers/CMSIS/Include/core_cm4.h **** typedef struct +1062:Drivers/CMSIS/Include/core_cm4.h **** { +1063:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg +1064:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis +1065:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[2U]; +1066:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg +1067:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[55U]; +1068:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * +1069:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[131U]; +1070:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis +1071:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi +1072:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte +1073:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[759U]; +1074:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ +1075:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ +1076:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ +1077:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[1U]; +1078:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ +1079:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ +1080:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ +1081:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[39U]; +1082:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ +1083:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ +1084:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED7[8U]; +1085:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ +1086:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +1087:Drivers/CMSIS/Include/core_cm4.h **** } TPI_Type; +1088:Drivers/CMSIS/Include/core_cm4.h **** +1089:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ +1090:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP +1091:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP +1092:Drivers/CMSIS/Include/core_cm4.h **** +1093:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */ +1094:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP +1095:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP +1096:Drivers/CMSIS/Include/core_cm4.h **** +1097:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */ +1098:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS +1099:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS +1100:Drivers/CMSIS/Include/core_cm4.h **** +1101:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS +1102:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS +1103:Drivers/CMSIS/Include/core_cm4.h **** +1104:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS +1105:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS +1106:Drivers/CMSIS/Include/core_cm4.h **** +1107:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS +1108:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS +1109:Drivers/CMSIS/Include/core_cm4.h **** +1110:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */ +1111:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC +1112:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC + ARM GAS /tmp/ccPJu8Ry.s page 21 + + +1113:Drivers/CMSIS/Include/core_cm4.h **** +1114:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC +1115:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC +1116:Drivers/CMSIS/Include/core_cm4.h **** +1117:Drivers/CMSIS/Include/core_cm4.h **** /* TPI TRIGGER Register Definitions */ +1118:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI +1119:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI +1120:Drivers/CMSIS/Include/core_cm4.h **** +1121:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ +1122:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF +1123:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF +1124:Drivers/CMSIS/Include/core_cm4.h **** +1125:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF +1126:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF +1127:Drivers/CMSIS/Include/core_cm4.h **** +1128:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF +1129:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF +1130:Drivers/CMSIS/Include/core_cm4.h **** +1131:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF +1132:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF +1133:Drivers/CMSIS/Include/core_cm4.h **** +1134:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF +1135:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF +1136:Drivers/CMSIS/Include/core_cm4.h **** +1137:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF +1138:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF +1139:Drivers/CMSIS/Include/core_cm4.h **** +1140:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF +1141:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF +1142:Drivers/CMSIS/Include/core_cm4.h **** +1143:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */ +1144:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA +1145:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA +1146:Drivers/CMSIS/Include/core_cm4.h **** +1147:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA +1148:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA +1149:Drivers/CMSIS/Include/core_cm4.h **** +1150:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ +1151:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF +1152:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF +1153:Drivers/CMSIS/Include/core_cm4.h **** +1154:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF +1155:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF +1156:Drivers/CMSIS/Include/core_cm4.h **** +1157:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF +1158:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF +1159:Drivers/CMSIS/Include/core_cm4.h **** +1160:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF +1161:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF +1162:Drivers/CMSIS/Include/core_cm4.h **** +1163:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF +1164:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF +1165:Drivers/CMSIS/Include/core_cm4.h **** +1166:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF +1167:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF +1168:Drivers/CMSIS/Include/core_cm4.h **** +1169:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF + ARM GAS /tmp/ccPJu8Ry.s page 22 + + +1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF +1171:Drivers/CMSIS/Include/core_cm4.h **** +1172:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */ +1173:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA +1174:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA +1175:Drivers/CMSIS/Include/core_cm4.h **** +1176:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA +1177:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA +1178:Drivers/CMSIS/Include/core_cm4.h **** +1179:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */ +1180:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC +1181:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC +1182:Drivers/CMSIS/Include/core_cm4.h **** +1183:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVID Register Definitions */ +1184:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV +1185:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV +1186:Drivers/CMSIS/Include/core_cm4.h **** +1187:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV +1188:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV +1189:Drivers/CMSIS/Include/core_cm4.h **** +1190:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV +1191:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV +1192:Drivers/CMSIS/Include/core_cm4.h **** +1193:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV +1194:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV +1195:Drivers/CMSIS/Include/core_cm4.h **** +1196:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV +1197:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV +1198:Drivers/CMSIS/Include/core_cm4.h **** +1199:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV +1200:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV +1201:Drivers/CMSIS/Include/core_cm4.h **** +1202:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVTYPE Register Definitions */ +1203:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV +1204:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV +1205:Drivers/CMSIS/Include/core_cm4.h **** +1206:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV +1207:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV +1208:Drivers/CMSIS/Include/core_cm4.h **** +1209:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */ +1210:Drivers/CMSIS/Include/core_cm4.h **** +1211:Drivers/CMSIS/Include/core_cm4.h **** +1212:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1213:Drivers/CMSIS/Include/core_cm4.h **** /** +1214:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1215:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) +1216:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Memory Protection Unit (MPU) +1217:Drivers/CMSIS/Include/core_cm4.h **** @{ +1218:Drivers/CMSIS/Include/core_cm4.h **** */ +1219:Drivers/CMSIS/Include/core_cm4.h **** +1220:Drivers/CMSIS/Include/core_cm4.h **** /** +1221:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Memory Protection Unit (MPU). +1222:Drivers/CMSIS/Include/core_cm4.h **** */ +1223:Drivers/CMSIS/Include/core_cm4.h **** typedef struct +1224:Drivers/CMSIS/Include/core_cm4.h **** { +1225:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ +1226:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + ARM GAS /tmp/ccPJu8Ry.s page 23 + + +1227:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ +1228:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register +1229:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re +1230:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address +1231:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and +1232:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address +1233:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and +1234:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address +1235:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and +1236:Drivers/CMSIS/Include/core_cm4.h **** } MPU_Type; +1237:Drivers/CMSIS/Include/core_cm4.h **** +1238:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_RALIASES 4U +1239:Drivers/CMSIS/Include/core_cm4.h **** +1240:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Type Register Definitions */ +1241:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU +1242:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU +1243:Drivers/CMSIS/Include/core_cm4.h **** +1244:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU +1245:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU +1246:Drivers/CMSIS/Include/core_cm4.h **** +1247:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU +1248:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU +1249:Drivers/CMSIS/Include/core_cm4.h **** +1250:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Control Register Definitions */ +1251:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU +1252:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU +1253:Drivers/CMSIS/Include/core_cm4.h **** +1254:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU +1255:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU +1256:Drivers/CMSIS/Include/core_cm4.h **** +1257:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU +1258:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU +1259:Drivers/CMSIS/Include/core_cm4.h **** +1260:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Number Register Definitions */ +1261:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU +1262:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU +1263:Drivers/CMSIS/Include/core_cm4.h **** +1264:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Base Address Register Definitions */ +1265:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU +1266:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU +1267:Drivers/CMSIS/Include/core_cm4.h **** +1268:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU +1269:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU +1270:Drivers/CMSIS/Include/core_cm4.h **** +1271:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU +1272:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU +1273:Drivers/CMSIS/Include/core_cm4.h **** +1274:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */ +1275:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU +1276:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU +1277:Drivers/CMSIS/Include/core_cm4.h **** +1278:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU +1279:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU +1280:Drivers/CMSIS/Include/core_cm4.h **** +1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU +1282:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU +1283:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccPJu8Ry.s page 24 + + +1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU +1285:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU +1286:Drivers/CMSIS/Include/core_cm4.h **** +1287:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Pos 18U /*!< MPU +1288:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU +1289:Drivers/CMSIS/Include/core_cm4.h **** +1290:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Pos 17U /*!< MPU +1291:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU +1292:Drivers/CMSIS/Include/core_cm4.h **** +1293:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Pos 16U /*!< MPU +1294:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU +1295:Drivers/CMSIS/Include/core_cm4.h **** +1296:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU +1297:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU +1298:Drivers/CMSIS/Include/core_cm4.h **** +1299:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU +1300:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU +1301:Drivers/CMSIS/Include/core_cm4.h **** +1302:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU +1303:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU +1304:Drivers/CMSIS/Include/core_cm4.h **** +1305:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_MPU */ +1306:Drivers/CMSIS/Include/core_cm4.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +1307:Drivers/CMSIS/Include/core_cm4.h **** +1308:Drivers/CMSIS/Include/core_cm4.h **** +1309:Drivers/CMSIS/Include/core_cm4.h **** /** +1310:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1311:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) +1312:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Floating Point Unit (FPU) +1313:Drivers/CMSIS/Include/core_cm4.h **** @{ +1314:Drivers/CMSIS/Include/core_cm4.h **** */ +1315:Drivers/CMSIS/Include/core_cm4.h **** +1316:Drivers/CMSIS/Include/core_cm4.h **** /** +1317:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Floating Point Unit (FPU). +1318:Drivers/CMSIS/Include/core_cm4.h **** */ +1319:Drivers/CMSIS/Include/core_cm4.h **** typedef struct +1320:Drivers/CMSIS/Include/core_cm4.h **** { +1321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; +1322:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R +1323:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R +1324:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co +1325:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 +1326:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 +1327:Drivers/CMSIS/Include/core_cm4.h **** } FPU_Type; +1328:Drivers/CMSIS/Include/core_cm4.h **** +1329:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Control Register Definitions */ +1330:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC +1331:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC +1332:Drivers/CMSIS/Include/core_cm4.h **** +1333:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC +1334:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC +1335:Drivers/CMSIS/Include/core_cm4.h **** +1336:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC +1337:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC +1338:Drivers/CMSIS/Include/core_cm4.h **** +1339:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC +1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC + ARM GAS /tmp/ccPJu8Ry.s page 25 + + +1341:Drivers/CMSIS/Include/core_cm4.h **** +1342:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC +1343:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC +1344:Drivers/CMSIS/Include/core_cm4.h **** +1345:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC +1346:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC +1347:Drivers/CMSIS/Include/core_cm4.h **** +1348:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC +1349:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC +1350:Drivers/CMSIS/Include/core_cm4.h **** +1351:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC +1352:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC +1353:Drivers/CMSIS/Include/core_cm4.h **** +1354:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC +1355:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC +1356:Drivers/CMSIS/Include/core_cm4.h **** +1357:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Address Register Definitions */ +1358:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA +1359:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA +1360:Drivers/CMSIS/Include/core_cm4.h **** +1361:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */ +1362:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS +1363:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS +1364:Drivers/CMSIS/Include/core_cm4.h **** +1365:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS +1366:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS +1367:Drivers/CMSIS/Include/core_cm4.h **** +1368:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS +1369:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS +1370:Drivers/CMSIS/Include/core_cm4.h **** +1371:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS +1372:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS +1373:Drivers/CMSIS/Include/core_cm4.h **** +1374:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */ +1375:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR +1376:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR +1377:Drivers/CMSIS/Include/core_cm4.h **** +1378:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR +1379:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR +1380:Drivers/CMSIS/Include/core_cm4.h **** +1381:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR +1382:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR +1383:Drivers/CMSIS/Include/core_cm4.h **** +1384:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR +1385:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR +1386:Drivers/CMSIS/Include/core_cm4.h **** +1387:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR +1388:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR +1389:Drivers/CMSIS/Include/core_cm4.h **** +1390:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR +1391:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR +1392:Drivers/CMSIS/Include/core_cm4.h **** +1393:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR +1394:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR +1395:Drivers/CMSIS/Include/core_cm4.h **** +1396:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR +1397:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR + ARM GAS /tmp/ccPJu8Ry.s page 26 + + +1398:Drivers/CMSIS/Include/core_cm4.h **** +1399:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */ +1400:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR +1401:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR +1402:Drivers/CMSIS/Include/core_cm4.h **** +1403:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR +1404:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR +1405:Drivers/CMSIS/Include/core_cm4.h **** +1406:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR +1407:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR +1408:Drivers/CMSIS/Include/core_cm4.h **** +1409:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR +1410:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR +1411:Drivers/CMSIS/Include/core_cm4.h **** +1412:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_FPU */ +1413:Drivers/CMSIS/Include/core_cm4.h **** +1414:Drivers/CMSIS/Include/core_cm4.h **** +1415:Drivers/CMSIS/Include/core_cm4.h **** /** +1416:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1417:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +1418:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Core Debug Registers +1419:Drivers/CMSIS/Include/core_cm4.h **** @{ +1420:Drivers/CMSIS/Include/core_cm4.h **** */ +1421:Drivers/CMSIS/Include/core_cm4.h **** +1422:Drivers/CMSIS/Include/core_cm4.h **** /** +1423:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Core Debug Register (CoreDebug). +1424:Drivers/CMSIS/Include/core_cm4.h **** */ +1425:Drivers/CMSIS/Include/core_cm4.h **** typedef struct +1426:Drivers/CMSIS/Include/core_cm4.h **** { +1427:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status +1428:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg +1429:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe +1430:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont +1431:Drivers/CMSIS/Include/core_cm4.h **** } CoreDebug_Type; +1432:Drivers/CMSIS/Include/core_cm4.h **** +1433:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */ +1434:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core +1435:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core +1436:Drivers/CMSIS/Include/core_cm4.h **** +1437:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core +1438:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core +1439:Drivers/CMSIS/Include/core_cm4.h **** +1440:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core +1441:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core +1442:Drivers/CMSIS/Include/core_cm4.h **** +1443:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core +1444:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core +1445:Drivers/CMSIS/Include/core_cm4.h **** +1446:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core +1447:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core +1448:Drivers/CMSIS/Include/core_cm4.h **** +1449:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core +1450:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core +1451:Drivers/CMSIS/Include/core_cm4.h **** +1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core +1453:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core +1454:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccPJu8Ry.s page 27 + + +1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core +1456:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core +1457:Drivers/CMSIS/Include/core_cm4.h **** +1458:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core +1459:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core +1460:Drivers/CMSIS/Include/core_cm4.h **** +1461:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core +1462:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core +1463:Drivers/CMSIS/Include/core_cm4.h **** +1464:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core +1465:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core +1466:Drivers/CMSIS/Include/core_cm4.h **** +1467:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core +1468:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core +1469:Drivers/CMSIS/Include/core_cm4.h **** +1470:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Core Register Selector Register Definitions */ +1471:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core +1472:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core +1473:Drivers/CMSIS/Include/core_cm4.h **** +1474:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core +1475:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core +1476:Drivers/CMSIS/Include/core_cm4.h **** +1477:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */ +1478:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core +1479:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core +1480:Drivers/CMSIS/Include/core_cm4.h **** +1481:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core +1482:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core +1483:Drivers/CMSIS/Include/core_cm4.h **** +1484:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core +1485:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core +1486:Drivers/CMSIS/Include/core_cm4.h **** +1487:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core +1488:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core +1489:Drivers/CMSIS/Include/core_cm4.h **** +1490:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core +1491:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core +1492:Drivers/CMSIS/Include/core_cm4.h **** +1493:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core +1494:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core +1495:Drivers/CMSIS/Include/core_cm4.h **** +1496:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core +1497:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core +1498:Drivers/CMSIS/Include/core_cm4.h **** +1499:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core +1500:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core +1501:Drivers/CMSIS/Include/core_cm4.h **** +1502:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core +1503:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core +1504:Drivers/CMSIS/Include/core_cm4.h **** +1505:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core +1506:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core +1507:Drivers/CMSIS/Include/core_cm4.h **** +1508:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core +1509:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core +1510:Drivers/CMSIS/Include/core_cm4.h **** +1511:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core + ARM GAS /tmp/ccPJu8Ry.s page 28 + + +1512:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core +1513:Drivers/CMSIS/Include/core_cm4.h **** +1514:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core +1515:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core +1516:Drivers/CMSIS/Include/core_cm4.h **** +1517:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */ +1518:Drivers/CMSIS/Include/core_cm4.h **** +1519:Drivers/CMSIS/Include/core_cm4.h **** +1520:Drivers/CMSIS/Include/core_cm4.h **** /** +1521:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1522:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_bitfield Core register bit field macros +1523:Drivers/CMSIS/Include/core_cm4.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +1524:Drivers/CMSIS/Include/core_cm4.h **** @{ +1525:Drivers/CMSIS/Include/core_cm4.h **** */ +1526:Drivers/CMSIS/Include/core_cm4.h **** +1527:Drivers/CMSIS/Include/core_cm4.h **** /** +1528:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a bit field value for use in a register bit range. +1529:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field. +1530:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +1531:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted value. +1532:Drivers/CMSIS/Include/core_cm4.h **** */ +1533:Drivers/CMSIS/Include/core_cm4.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +1534:Drivers/CMSIS/Include/core_cm4.h **** +1535:Drivers/CMSIS/Include/core_cm4.h **** /** +1536:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a register value to extract a bit filed value. +1537:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field. +1538:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +1539:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted bit field value. +1540:Drivers/CMSIS/Include/core_cm4.h **** */ +1541:Drivers/CMSIS/Include/core_cm4.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +1542:Drivers/CMSIS/Include/core_cm4.h **** +1543:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */ +1544:Drivers/CMSIS/Include/core_cm4.h **** +1545:Drivers/CMSIS/Include/core_cm4.h **** +1546:Drivers/CMSIS/Include/core_cm4.h **** /** +1547:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1548:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_base Core Definitions +1549:Drivers/CMSIS/Include/core_cm4.h **** \brief Definitions for base addresses, unions, and structures. +1550:Drivers/CMSIS/Include/core_cm4.h **** @{ +1551:Drivers/CMSIS/Include/core_cm4.h **** */ +1552:Drivers/CMSIS/Include/core_cm4.h **** +1553:Drivers/CMSIS/Include/core_cm4.h **** /* Memory mapping of Core Hardware */ +1554:Drivers/CMSIS/Include/core_cm4.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas +1555:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +1556:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +1557:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +1558:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address +1559:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +1560:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +1561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas +1562:Drivers/CMSIS/Include/core_cm4.h **** +1563:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register +1564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct +1565:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st +1566:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc +1567:Drivers/CMSIS/Include/core_cm4.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct +1568:Drivers/CMSIS/Include/core_cm4.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct + ARM GAS /tmp/ccPJu8Ry.s page 29 + + +1569:Drivers/CMSIS/Include/core_cm4.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct +1570:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration +1571:Drivers/CMSIS/Include/core_cm4.h **** +1572:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1573:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * +1574:Drivers/CMSIS/Include/core_cm4.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * +1575:Drivers/CMSIS/Include/core_cm4.h **** #endif +1576:Drivers/CMSIS/Include/core_cm4.h **** +1577:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +1578:Drivers/CMSIS/Include/core_cm4.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +1579:Drivers/CMSIS/Include/core_cm4.h **** +1580:Drivers/CMSIS/Include/core_cm4.h **** /*@} */ +1581:Drivers/CMSIS/Include/core_cm4.h **** +1582:Drivers/CMSIS/Include/core_cm4.h **** +1583:Drivers/CMSIS/Include/core_cm4.h **** +1584:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* +1585:Drivers/CMSIS/Include/core_cm4.h **** * Hardware Abstraction Layer +1586:Drivers/CMSIS/Include/core_cm4.h **** Core Function Interface contains: +1587:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Functions +1588:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Functions +1589:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Functions +1590:Drivers/CMSIS/Include/core_cm4.h **** - Core Register Access Functions +1591:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ +1592:Drivers/CMSIS/Include/core_cm4.h **** /** +1593:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +1594:Drivers/CMSIS/Include/core_cm4.h **** */ +1595:Drivers/CMSIS/Include/core_cm4.h **** +1596:Drivers/CMSIS/Include/core_cm4.h **** +1597:Drivers/CMSIS/Include/core_cm4.h **** +1598:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## NVIC functions #################################### */ +1599:Drivers/CMSIS/Include/core_cm4.h **** /** +1600:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface +1601:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions +1602:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that manage interrupts and exceptions via the NVIC. +1603:Drivers/CMSIS/Include/core_cm4.h **** @{ +1604:Drivers/CMSIS/Include/core_cm4.h **** */ +1605:Drivers/CMSIS/Include/core_cm4.h **** +1606:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_NVIC_VIRTUAL +1607:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +1608:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +1609:Drivers/CMSIS/Include/core_cm4.h **** #endif +1610:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +1611:Drivers/CMSIS/Include/core_cm4.h **** #else +1612:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +1613:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +1614:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ +1615:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +1616:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ +1617:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +1618:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +1619:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +1620:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetActive __NVIC_GetActive +1621:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriority __NVIC_SetPriority +1622:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriority __NVIC_GetPriority +1623:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SystemReset __NVIC_SystemReset +1624:Drivers/CMSIS/Include/core_cm4.h **** #endif /* CMSIS_NVIC_VIRTUAL */ +1625:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccPJu8Ry.s page 30 + + +1626:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_VECTAB_VIRTUAL +1627:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1628:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +1629:Drivers/CMSIS/Include/core_cm4.h **** #endif +1630:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1631:Drivers/CMSIS/Include/core_cm4.h **** #else +1632:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetVector __NVIC_SetVector +1633:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetVector __NVIC_GetVector +1634:Drivers/CMSIS/Include/core_cm4.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ +1635:Drivers/CMSIS/Include/core_cm4.h **** +1636:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_USER_IRQ_OFFSET 16 +1637:Drivers/CMSIS/Include/core_cm4.h **** +1638:Drivers/CMSIS/Include/core_cm4.h **** +1639:Drivers/CMSIS/Include/core_cm4.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ +1640:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret +1641:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu +1642:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu +1643:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret +1644:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu +1645:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu +1646:Drivers/CMSIS/Include/core_cm4.h **** +1647:Drivers/CMSIS/Include/core_cm4.h **** +1648:Drivers/CMSIS/Include/core_cm4.h **** /** +1649:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Priority Grouping +1650:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority grouping field using the required unlock sequence. +1651:Drivers/CMSIS/Include/core_cm4.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. +1652:Drivers/CMSIS/Include/core_cm4.h **** Only values from 0..7 are used. +1653:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available +1654:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +1655:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Priority grouping field. +1656:Drivers/CMSIS/Include/core_cm4.h **** */ +1657:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +1658:Drivers/CMSIS/Include/core_cm4.h **** { +1659:Drivers/CMSIS/Include/core_cm4.h **** uint32_t reg_value; +1660:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a +1661:Drivers/CMSIS/Include/core_cm4.h **** +1662:Drivers/CMSIS/Include/core_cm4.h **** reg_value = SCB->AIRCR; /* read old register +1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan +1664:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | +1665:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +1666:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a +1667:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value; +1668:Drivers/CMSIS/Include/core_cm4.h **** } +1669:Drivers/CMSIS/Include/core_cm4.h **** +1670:Drivers/CMSIS/Include/core_cm4.h **** +1671:Drivers/CMSIS/Include/core_cm4.h **** /** +1672:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Priority Grouping +1673:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. +1674:Drivers/CMSIS/Include/core_cm4.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). +1675:Drivers/CMSIS/Include/core_cm4.h **** */ +1676:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +1677:Drivers/CMSIS/Include/core_cm4.h **** { +1678:Drivers/CMSIS/Include/core_cm4.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +1679:Drivers/CMSIS/Include/core_cm4.h **** } +1680:Drivers/CMSIS/Include/core_cm4.h **** +1681:Drivers/CMSIS/Include/core_cm4.h **** +1682:Drivers/CMSIS/Include/core_cm4.h **** /** + ARM GAS /tmp/ccPJu8Ry.s page 31 + + +1683:Drivers/CMSIS/Include/core_cm4.h **** \brief Enable Interrupt +1684:Drivers/CMSIS/Include/core_cm4.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. +1685:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1686:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1687:Drivers/CMSIS/Include/core_cm4.h **** */ +1688:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +1689:Drivers/CMSIS/Include/core_cm4.h **** { +1690:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) +1691:Drivers/CMSIS/Include/core_cm4.h **** { +1692:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1693:Drivers/CMSIS/Include/core_cm4.h **** } +1694:Drivers/CMSIS/Include/core_cm4.h **** } +1695:Drivers/CMSIS/Include/core_cm4.h **** +1696:Drivers/CMSIS/Include/core_cm4.h **** +1697:Drivers/CMSIS/Include/core_cm4.h **** /** +1698:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Enable status +1699:Drivers/CMSIS/Include/core_cm4.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +1700:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1701:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt is not enabled. +1702:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt is enabled. +1703:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1704:Drivers/CMSIS/Include/core_cm4.h **** */ +1705:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +1706:Drivers/CMSIS/Include/core_cm4.h **** { +1707:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) +1708:Drivers/CMSIS/Include/core_cm4.h **** { +1709:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1710:Drivers/CMSIS/Include/core_cm4.h **** } +1711:Drivers/CMSIS/Include/core_cm4.h **** else +1712:Drivers/CMSIS/Include/core_cm4.h **** { +1713:Drivers/CMSIS/Include/core_cm4.h **** return(0U); +1714:Drivers/CMSIS/Include/core_cm4.h **** } +1715:Drivers/CMSIS/Include/core_cm4.h **** } +1716:Drivers/CMSIS/Include/core_cm4.h **** +1717:Drivers/CMSIS/Include/core_cm4.h **** +1718:Drivers/CMSIS/Include/core_cm4.h **** /** +1719:Drivers/CMSIS/Include/core_cm4.h **** \brief Disable Interrupt +1720:Drivers/CMSIS/Include/core_cm4.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. +1721:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1722:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1723:Drivers/CMSIS/Include/core_cm4.h **** */ +1724:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +1725:Drivers/CMSIS/Include/core_cm4.h **** { + 30 .loc 2 1725 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 @ link register save eliminated. +1726:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 35 .loc 2 1726 3 view .LVU1 + 36 .loc 2 1726 6 is_stmt 0 view .LVU2 + 37 0000 0028 cmp r0, #0 + 38 .LVL1: + 39 .loc 2 1726 6 view .LVU3 + 40 0002 0CDB blt .L1 +1727:Drivers/CMSIS/Include/core_cm4.h **** { +1728:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + ARM GAS /tmp/ccPJu8Ry.s page 32 + + + 41 .loc 2 1728 5 is_stmt 1 view .LVU4 + 42 .loc 2 1728 81 is_stmt 0 view .LVU5 + 43 0004 00F01F02 and r2, r0, #31 + 44 .loc 2 1728 34 view .LVU6 + 45 0008 4009 lsrs r0, r0, #5 + 46 .loc 2 1728 45 view .LVU7 + 47 000a 0123 movs r3, #1 + 48 000c 9340 lsls r3, r3, r2 + 49 .loc 2 1728 43 view .LVU8 + 50 000e 2030 adds r0, r0, #32 + 51 0010 034A ldr r2, .L3 + 52 0012 42F82030 str r3, [r2, r0, lsl #2] +1729:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); + 53 .loc 2 1729 5 is_stmt 1 view .LVU9 + 54 .LBB32: + 55 .LBI32: + 56 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + ARM GAS /tmp/ccPJu8Ry.s page 33 + + + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + ARM GAS /tmp/ccPJu8Ry.s page 34 + + + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccPJu8Ry.s page 35 + + + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccPJu8Ry.s page 36 + + + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccPJu8Ry.s page 37 + + + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccPJu8Ry.s page 38 + + + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + ARM GAS /tmp/ccPJu8Ry.s page 39 + + + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + ARM GAS /tmp/ccPJu8Ry.s page 40 + + + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccPJu8Ry.s page 41 + + + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + ARM GAS /tmp/ccPJu8Ry.s page 42 + + + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccPJu8Ry.s page 43 + + + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/ccPJu8Ry.s page 44 + + + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccPJu8Ry.s page 45 + + + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/ccPJu8Ry.s page 46 + + + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccPJu8Ry.s page 47 + + + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 57 .loc 3 877 27 view .LVU10 + 58 .LBB33: + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 59 .loc 3 879 3 view .LVU11 + 60 .syntax unified + 61 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 62 0016 BFF34F8F dsb 0xF + 63 @ 0 "" 2 + 64 .thumb + 65 .syntax unified + 66 .LBE33: + 67 .LBE32: +1730:Drivers/CMSIS/Include/core_cm4.h **** __ISB(); + 68 .loc 2 1730 5 view .LVU12 + 69 .LBB34: + 70 .LBI34: + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccPJu8Ry.s page 48 + + + 71 .loc 3 866 27 view .LVU13 + 72 .LBB35: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 73 .loc 3 868 3 view .LVU14 + 74 .syntax unified + 75 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 76 001a BFF36F8F isb 0xF + 77 @ 0 "" 2 + 78 .thumb + 79 .syntax unified + 80 .L1: + 81 .LBE35: + 82 .LBE34: +1731:Drivers/CMSIS/Include/core_cm4.h **** } +1732:Drivers/CMSIS/Include/core_cm4.h **** } + 83 .loc 2 1732 1 is_stmt 0 view .LVU15 + 84 001e 7047 bx lr + 85 .L4: + 86 .align 2 + 87 .L3: + 88 0020 00E100E0 .word -536813312 + 89 .cfi_endproc + 90 .LFE106: + 92 .section .text.__NVIC_SetPriority,"ax",%progbits + 93 .align 1 + 94 .syntax unified + 95 .thumb + 96 .thumb_func + 98 __NVIC_SetPriority: + 99 .LVL2: + 100 .LFB111: +1733:Drivers/CMSIS/Include/core_cm4.h **** +1734:Drivers/CMSIS/Include/core_cm4.h **** +1735:Drivers/CMSIS/Include/core_cm4.h **** /** +1736:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Pending Interrupt +1737:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe +1738:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1739:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not pending. +1740:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is pending. +1741:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1742:Drivers/CMSIS/Include/core_cm4.h **** */ +1743:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +1744:Drivers/CMSIS/Include/core_cm4.h **** { +1745:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) +1746:Drivers/CMSIS/Include/core_cm4.h **** { +1747:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1748:Drivers/CMSIS/Include/core_cm4.h **** } +1749:Drivers/CMSIS/Include/core_cm4.h **** else +1750:Drivers/CMSIS/Include/core_cm4.h **** { +1751:Drivers/CMSIS/Include/core_cm4.h **** return(0U); +1752:Drivers/CMSIS/Include/core_cm4.h **** } +1753:Drivers/CMSIS/Include/core_cm4.h **** } +1754:Drivers/CMSIS/Include/core_cm4.h **** +1755:Drivers/CMSIS/Include/core_cm4.h **** +1756:Drivers/CMSIS/Include/core_cm4.h **** /** +1757:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Pending Interrupt +1758:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + ARM GAS /tmp/ccPJu8Ry.s page 49 + + +1759:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1760:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1761:Drivers/CMSIS/Include/core_cm4.h **** */ +1762:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +1763:Drivers/CMSIS/Include/core_cm4.h **** { +1764:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) +1765:Drivers/CMSIS/Include/core_cm4.h **** { +1766:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1767:Drivers/CMSIS/Include/core_cm4.h **** } +1768:Drivers/CMSIS/Include/core_cm4.h **** } +1769:Drivers/CMSIS/Include/core_cm4.h **** +1770:Drivers/CMSIS/Include/core_cm4.h **** +1771:Drivers/CMSIS/Include/core_cm4.h **** /** +1772:Drivers/CMSIS/Include/core_cm4.h **** \brief Clear Pending Interrupt +1773:Drivers/CMSIS/Include/core_cm4.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +1774:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1775:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1776:Drivers/CMSIS/Include/core_cm4.h **** */ +1777:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +1778:Drivers/CMSIS/Include/core_cm4.h **** { +1779:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) +1780:Drivers/CMSIS/Include/core_cm4.h **** { +1781:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); +1782:Drivers/CMSIS/Include/core_cm4.h **** } +1783:Drivers/CMSIS/Include/core_cm4.h **** } +1784:Drivers/CMSIS/Include/core_cm4.h **** +1785:Drivers/CMSIS/Include/core_cm4.h **** +1786:Drivers/CMSIS/Include/core_cm4.h **** /** +1787:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Active Interrupt +1788:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific +1789:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1790:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not active. +1791:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is active. +1792:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1793:Drivers/CMSIS/Include/core_cm4.h **** */ +1794:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +1795:Drivers/CMSIS/Include/core_cm4.h **** { +1796:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) +1797:Drivers/CMSIS/Include/core_cm4.h **** { +1798:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1799:Drivers/CMSIS/Include/core_cm4.h **** } +1800:Drivers/CMSIS/Include/core_cm4.h **** else +1801:Drivers/CMSIS/Include/core_cm4.h **** { +1802:Drivers/CMSIS/Include/core_cm4.h **** return(0U); +1803:Drivers/CMSIS/Include/core_cm4.h **** } +1804:Drivers/CMSIS/Include/core_cm4.h **** } +1805:Drivers/CMSIS/Include/core_cm4.h **** +1806:Drivers/CMSIS/Include/core_cm4.h **** +1807:Drivers/CMSIS/Include/core_cm4.h **** /** +1808:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Priority +1809:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority of a device specific interrupt or a processor exception. +1810:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, +1811:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. +1812:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. +1813:Drivers/CMSIS/Include/core_cm4.h **** \param [in] priority Priority to set. +1814:Drivers/CMSIS/Include/core_cm4.h **** \note The priority cannot be set for every processor exception. +1815:Drivers/CMSIS/Include/core_cm4.h **** */ + ARM GAS /tmp/ccPJu8Ry.s page 50 + + +1816:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +1817:Drivers/CMSIS/Include/core_cm4.h **** { + 101 .loc 2 1817 1 is_stmt 1 view -0 + 102 .cfi_startproc + 103 @ args = 0, pretend = 0, frame = 0 + 104 @ frame_needed = 0, uses_anonymous_args = 0 + 105 @ link register save eliminated. +1818:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 106 .loc 2 1818 3 view .LVU17 + 107 .loc 2 1818 6 is_stmt 0 view .LVU18 + 108 0000 0028 cmp r0, #0 + 109 .LVL3: + 110 .loc 2 1818 6 view .LVU19 + 111 0002 08DB blt .L6 +1819:Drivers/CMSIS/Include/core_cm4.h **** { +1820:Drivers/CMSIS/Include/core_cm4.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u + 112 .loc 2 1820 5 is_stmt 1 view .LVU20 + 113 .loc 2 1820 48 is_stmt 0 view .LVU21 + 114 0004 0901 lsls r1, r1, #4 + 115 .LVL4: + 116 .loc 2 1820 48 view .LVU22 + 117 0006 C9B2 uxtb r1, r1 + 118 .loc 2 1820 46 view .LVU23 + 119 0008 00F16040 add r0, r0, #-536870912 + 120 000c 00F56140 add r0, r0, #57600 + 121 0010 80F80013 strb r1, [r0, #768] + 122 0014 7047 bx lr + 123 .LVL5: + 124 .L6: +1821:Drivers/CMSIS/Include/core_cm4.h **** } +1822:Drivers/CMSIS/Include/core_cm4.h **** else +1823:Drivers/CMSIS/Include/core_cm4.h **** { +1824:Drivers/CMSIS/Include/core_cm4.h **** SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u + 125 .loc 2 1824 5 is_stmt 1 view .LVU24 + 126 .loc 2 1824 32 is_stmt 0 view .LVU25 + 127 0016 00F00F00 and r0, r0, #15 + 128 .loc 2 1824 48 view .LVU26 + 129 001a 0901 lsls r1, r1, #4 + 130 .LVL6: + 131 .loc 2 1824 48 view .LVU27 + 132 001c C9B2 uxtb r1, r1 + 133 .loc 2 1824 46 view .LVU28 + 134 001e 014B ldr r3, .L8 + 135 0020 1954 strb r1, [r3, r0] +1825:Drivers/CMSIS/Include/core_cm4.h **** } +1826:Drivers/CMSIS/Include/core_cm4.h **** } + 136 .loc 2 1826 1 view .LVU29 + 137 0022 7047 bx lr + 138 .L9: + 139 .align 2 + 140 .L8: + 141 0024 14ED00E0 .word -536810220 + 142 .cfi_endproc + 143 .LFE111: + 145 .section .text.__NVIC_GetPriority,"ax",%progbits + 146 .align 1 + 147 .syntax unified + ARM GAS /tmp/ccPJu8Ry.s page 51 + + + 148 .thumb + 149 .thumb_func + 151 __NVIC_GetPriority: + 152 .LVL7: + 153 .LFB112: +1827:Drivers/CMSIS/Include/core_cm4.h **** +1828:Drivers/CMSIS/Include/core_cm4.h **** +1829:Drivers/CMSIS/Include/core_cm4.h **** /** +1830:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Priority +1831:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority of a device specific interrupt or a processor exception. +1832:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, +1833:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. +1834:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. +1835:Drivers/CMSIS/Include/core_cm4.h **** \return Interrupt Priority. +1836:Drivers/CMSIS/Include/core_cm4.h **** Value is aligned automatically to the implemented priority bits of the microc +1837:Drivers/CMSIS/Include/core_cm4.h **** */ +1838:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +1839:Drivers/CMSIS/Include/core_cm4.h **** { + 154 .loc 2 1839 1 is_stmt 1 view -0 + 155 .cfi_startproc + 156 @ args = 0, pretend = 0, frame = 0 + 157 @ frame_needed = 0, uses_anonymous_args = 0 + 158 @ link register save eliminated. +1840:Drivers/CMSIS/Include/core_cm4.h **** +1841:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 159 .loc 2 1841 3 view .LVU31 + 160 .loc 2 1841 6 is_stmt 0 view .LVU32 + 161 0000 0028 cmp r0, #0 + 162 .LVL8: + 163 .loc 2 1841 6 view .LVU33 + 164 0002 07DB blt .L11 +1842:Drivers/CMSIS/Include/core_cm4.h **** { +1843:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + 165 .loc 2 1843 5 is_stmt 1 view .LVU34 + 166 .loc 2 1843 31 is_stmt 0 view .LVU35 + 167 0004 00F16040 add r0, r0, #-536870912 + 168 0008 00F56140 add r0, r0, #57600 + 169 000c 90F80003 ldrb r0, [r0, #768] @ zero_extendqisi2 + 170 .loc 2 1843 64 view .LVU36 + 171 0010 0009 lsrs r0, r0, #4 + 172 0012 7047 bx lr + 173 .L11: +1844:Drivers/CMSIS/Include/core_cm4.h **** } +1845:Drivers/CMSIS/Include/core_cm4.h **** else +1846:Drivers/CMSIS/Include/core_cm4.h **** { +1847:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + 174 .loc 2 1847 5 is_stmt 1 view .LVU37 + 175 .loc 2 1847 50 is_stmt 0 view .LVU38 + 176 0014 00F00F00 and r0, r0, #15 + 177 .loc 2 1847 31 view .LVU39 + 178 0018 014B ldr r3, .L13 + 179 001a 185C ldrb r0, [r3, r0] @ zero_extendqisi2 + 180 .loc 2 1847 64 view .LVU40 + 181 001c 0009 lsrs r0, r0, #4 +1848:Drivers/CMSIS/Include/core_cm4.h **** } +1849:Drivers/CMSIS/Include/core_cm4.h **** } + 182 .loc 2 1849 1 view .LVU41 + ARM GAS /tmp/ccPJu8Ry.s page 52 + + + 183 001e 7047 bx lr + 184 .L14: + 185 .align 2 + 186 .L13: + 187 0020 14ED00E0 .word -536810220 + 188 .cfi_endproc + 189 .LFE112: + 191 .section .text.NVIC_EncodePriority,"ax",%progbits + 192 .align 1 + 193 .syntax unified + 194 .thumb + 195 .thumb_func + 197 NVIC_EncodePriority: + 198 .LVL9: + 199 .LFB113: +1850:Drivers/CMSIS/Include/core_cm4.h **** +1851:Drivers/CMSIS/Include/core_cm4.h **** +1852:Drivers/CMSIS/Include/core_cm4.h **** /** +1853:Drivers/CMSIS/Include/core_cm4.h **** \brief Encode Priority +1854:Drivers/CMSIS/Include/core_cm4.h **** \details Encodes the priority for an interrupt with the given priority group, +1855:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value, and subpriority value. +1856:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available +1857:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +1858:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group. +1859:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). +1860:Drivers/CMSIS/Include/core_cm4.h **** \param [in] SubPriority Subpriority value (starting from 0). +1861:Drivers/CMSIS/Include/core_cm4.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP +1862:Drivers/CMSIS/Include/core_cm4.h **** */ +1863:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin +1864:Drivers/CMSIS/Include/core_cm4.h **** { + 200 .loc 2 1864 1 is_stmt 1 view -0 + 201 .cfi_startproc + 202 @ args = 0, pretend = 0, frame = 0 + 203 @ frame_needed = 0, uses_anonymous_args = 0 + 204 .loc 2 1864 1 is_stmt 0 view .LVU43 + 205 0000 00B5 push {lr} + 206 .cfi_def_cfa_offset 4 + 207 .cfi_offset 14, -4 +1865:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 208 .loc 2 1865 3 is_stmt 1 view .LVU44 + 209 .loc 2 1865 12 is_stmt 0 view .LVU45 + 210 0002 00F00700 and r0, r0, #7 + 211 .LVL10: +1866:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; + 212 .loc 2 1866 3 is_stmt 1 view .LVU46 +1867:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; + 213 .loc 2 1867 3 view .LVU47 +1868:Drivers/CMSIS/Include/core_cm4.h **** +1869:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 214 .loc 2 1869 3 view .LVU48 + 215 .loc 2 1869 31 is_stmt 0 view .LVU49 + 216 0006 C0F1070C rsb ip, r0, #7 + 217 .loc 2 1869 23 view .LVU50 + 218 000a BCF1040F cmp ip, #4 + 219 000e 28BF it cs + 220 0010 4FF0040C movcs ip, #4 + 221 .LVL11: + ARM GAS /tmp/ccPJu8Ry.s page 53 + + +1870:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 222 .loc 2 1870 3 is_stmt 1 view .LVU51 + 223 .loc 2 1870 44 is_stmt 0 view .LVU52 + 224 0014 031D adds r3, r0, #4 + 225 .loc 2 1870 109 view .LVU53 + 226 0016 062B cmp r3, #6 + 227 0018 0FD9 bls .L17 + 228 .loc 2 1870 109 discriminator 1 view .LVU54 + 229 001a C31E subs r3, r0, #3 + 230 .L16: + 231 .LVL12: +1871:Drivers/CMSIS/Include/core_cm4.h **** +1872:Drivers/CMSIS/Include/core_cm4.h **** return ( + 232 .loc 2 1872 3 is_stmt 1 discriminator 4 view .LVU55 +1873:Drivers/CMSIS/Include/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits + 233 .loc 2 1873 30 is_stmt 0 discriminator 4 view .LVU56 + 234 001c 4FF0FF3E mov lr, #-1 + 235 0020 0EFA0CF0 lsl r0, lr, ip + 236 .LVL13: + 237 .loc 2 1873 30 discriminator 4 view .LVU57 + 238 0024 21EA0001 bic r1, r1, r0 + 239 .LVL14: + 240 .loc 2 1873 82 discriminator 4 view .LVU58 + 241 0028 9940 lsls r1, r1, r3 +1874:Drivers/CMSIS/Include/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 242 .loc 2 1874 30 discriminator 4 view .LVU59 + 243 002a 0EFA03FE lsl lr, lr, r3 + 244 002e 22EA0E02 bic r2, r2, lr + 245 .LVL15: +1875:Drivers/CMSIS/Include/core_cm4.h **** ); +1876:Drivers/CMSIS/Include/core_cm4.h **** } + 246 .loc 2 1876 1 discriminator 4 view .LVU60 + 247 0032 41EA0200 orr r0, r1, r2 + 248 0036 5DF804FB ldr pc, [sp], #4 + 249 .LVL16: + 250 .L17: +1870:Drivers/CMSIS/Include/core_cm4.h **** + 251 .loc 2 1870 109 view .LVU61 + 252 003a 0023 movs r3, #0 + 253 003c EEE7 b .L16 + 254 .cfi_endproc + 255 .LFE113: + 257 .section .text.NVIC_DecodePriority,"ax",%progbits + 258 .align 1 + 259 .syntax unified + 260 .thumb + 261 .thumb_func + 263 NVIC_DecodePriority: + 264 .LVL17: + 265 .LFB114: +1877:Drivers/CMSIS/Include/core_cm4.h **** +1878:Drivers/CMSIS/Include/core_cm4.h **** +1879:Drivers/CMSIS/Include/core_cm4.h **** /** +1880:Drivers/CMSIS/Include/core_cm4.h **** \brief Decode Priority +1881:Drivers/CMSIS/Include/core_cm4.h **** \details Decodes an interrupt priority value with a given priority group to +1882:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value and subpriority value. +1883:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available + ARM GAS /tmp/ccPJu8Ry.s page 54 + + +1884:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. +1885:Drivers/CMSIS/Include/core_cm4.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC +1886:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group. +1887:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). +1888:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pSubPriority Subpriority value (starting from 0). +1889:Drivers/CMSIS/Include/core_cm4.h **** */ +1890:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons +1891:Drivers/CMSIS/Include/core_cm4.h **** { + 266 .loc 2 1891 1 is_stmt 1 view -0 + 267 .cfi_startproc + 268 @ args = 0, pretend = 0, frame = 0 + 269 @ frame_needed = 0, uses_anonymous_args = 0 + 270 .loc 2 1891 1 is_stmt 0 view .LVU63 + 271 0000 10B5 push {r4, lr} + 272 .cfi_def_cfa_offset 8 + 273 .cfi_offset 4, -8 + 274 .cfi_offset 14, -4 +1892:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 275 .loc 2 1892 3 is_stmt 1 view .LVU64 + 276 .loc 2 1892 12 is_stmt 0 view .LVU65 + 277 0002 01F00701 and r1, r1, #7 + 278 .LVL18: +1893:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; + 279 .loc 2 1893 3 is_stmt 1 view .LVU66 +1894:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; + 280 .loc 2 1894 3 view .LVU67 +1895:Drivers/CMSIS/Include/core_cm4.h **** +1896:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 281 .loc 2 1896 3 view .LVU68 + 282 .loc 2 1896 31 is_stmt 0 view .LVU69 + 283 0006 C1F1070C rsb ip, r1, #7 + 284 .loc 2 1896 23 view .LVU70 + 285 000a BCF1040F cmp ip, #4 + 286 000e 28BF it cs + 287 0010 4FF0040C movcs ip, #4 + 288 .LVL19: +1897:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 289 .loc 2 1897 3 is_stmt 1 view .LVU71 + 290 .loc 2 1897 44 is_stmt 0 view .LVU72 + 291 0014 0C1D adds r4, r1, #4 + 292 .loc 2 1897 109 view .LVU73 + 293 0016 062C cmp r4, #6 + 294 0018 0FD9 bls .L21 + 295 .loc 2 1897 109 discriminator 1 view .LVU74 + 296 001a 0339 subs r1, r1, #3 + 297 .LVL20: + 298 .L20: +1898:Drivers/CMSIS/Include/core_cm4.h **** +1899:Drivers/CMSIS/Include/core_cm4.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 + 299 .loc 2 1899 3 is_stmt 1 discriminator 4 view .LVU75 + 300 .loc 2 1899 33 is_stmt 0 discriminator 4 view .LVU76 + 301 001c 20FA01F4 lsr r4, r0, r1 + 302 .LVL21: + 303 .loc 2 1899 53 discriminator 4 view .LVU77 + 304 0020 4FF0FF3E mov lr, #-1 + 305 0024 0EFA0CFC lsl ip, lr, ip + 306 .LVL22: + ARM GAS /tmp/ccPJu8Ry.s page 55 + + + 307 .loc 2 1899 53 discriminator 4 view .LVU78 + 308 0028 24EA0C04 bic r4, r4, ip + 309 .loc 2 1899 21 discriminator 4 view .LVU79 + 310 002c 1460 str r4, [r2] +1900:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 311 .loc 2 1900 3 is_stmt 1 discriminator 4 view .LVU80 + 312 .loc 2 1900 53 is_stmt 0 discriminator 4 view .LVU81 + 313 002e 0EFA01FE lsl lr, lr, r1 + 314 0032 20EA0E00 bic r0, r0, lr + 315 .LVL23: + 316 .loc 2 1900 21 discriminator 4 view .LVU82 + 317 0036 1860 str r0, [r3] +1901:Drivers/CMSIS/Include/core_cm4.h **** } + 318 .loc 2 1901 1 discriminator 4 view .LVU83 + 319 0038 10BD pop {r4, pc} + 320 .LVL24: + 321 .L21: +1897:Drivers/CMSIS/Include/core_cm4.h **** + 322 .loc 2 1897 109 view .LVU84 + 323 003a 0021 movs r1, #0 + 324 .LVL25: +1897:Drivers/CMSIS/Include/core_cm4.h **** + 325 .loc 2 1897 109 view .LVU85 + 326 003c EEE7 b .L20 + 327 .cfi_endproc + 328 .LFE114: + 330 .section .text.__NVIC_SystemReset,"ax",%progbits + 331 .align 1 + 332 .syntax unified + 333 .thumb + 334 .thumb_func + 336 __NVIC_SystemReset: + 337 .LFB117: +1902:Drivers/CMSIS/Include/core_cm4.h **** +1903:Drivers/CMSIS/Include/core_cm4.h **** +1904:Drivers/CMSIS/Include/core_cm4.h **** /** +1905:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Vector +1906:Drivers/CMSIS/Include/core_cm4.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. +1907:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, +1908:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. +1909:Drivers/CMSIS/Include/core_cm4.h **** VTOR must been relocated to SRAM before. +1910:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number +1911:Drivers/CMSIS/Include/core_cm4.h **** \param [in] vector Address of interrupt handler function +1912:Drivers/CMSIS/Include/core_cm4.h **** */ +1913:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +1914:Drivers/CMSIS/Include/core_cm4.h **** { +1915:Drivers/CMSIS/Include/core_cm4.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +1916:Drivers/CMSIS/Include/core_cm4.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +1917:Drivers/CMSIS/Include/core_cm4.h **** } +1918:Drivers/CMSIS/Include/core_cm4.h **** +1919:Drivers/CMSIS/Include/core_cm4.h **** +1920:Drivers/CMSIS/Include/core_cm4.h **** /** +1921:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Vector +1922:Drivers/CMSIS/Include/core_cm4.h **** \details Reads an interrupt vector from interrupt vector table. +1923:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, +1924:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. +1925:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. + ARM GAS /tmp/ccPJu8Ry.s page 56 + + +1926:Drivers/CMSIS/Include/core_cm4.h **** \return Address of interrupt handler function +1927:Drivers/CMSIS/Include/core_cm4.h **** */ +1928:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +1929:Drivers/CMSIS/Include/core_cm4.h **** { +1930:Drivers/CMSIS/Include/core_cm4.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +1931:Drivers/CMSIS/Include/core_cm4.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +1932:Drivers/CMSIS/Include/core_cm4.h **** } +1933:Drivers/CMSIS/Include/core_cm4.h **** +1934:Drivers/CMSIS/Include/core_cm4.h **** +1935:Drivers/CMSIS/Include/core_cm4.h **** /** +1936:Drivers/CMSIS/Include/core_cm4.h **** \brief System Reset +1937:Drivers/CMSIS/Include/core_cm4.h **** \details Initiates a system reset request to reset the MCU. +1938:Drivers/CMSIS/Include/core_cm4.h **** */ +1939:Drivers/CMSIS/Include/core_cm4.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +1940:Drivers/CMSIS/Include/core_cm4.h **** { + 338 .loc 2 1940 1 is_stmt 1 view -0 + 339 .cfi_startproc + 340 @ Volatile: function does not return. + 341 @ args = 0, pretend = 0, frame = 0 + 342 @ frame_needed = 0, uses_anonymous_args = 0 + 343 @ link register save eliminated. +1941:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure all outstanding memor + 344 .loc 2 1941 3 view .LVU87 + 345 .LBB36: + 346 .LBI36: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 347 .loc 3 877 27 view .LVU88 + 348 .LBB37: + 349 .loc 3 879 3 view .LVU89 + 350 .syntax unified + 351 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 352 0000 BFF34F8F dsb 0xF + 353 @ 0 "" 2 + 354 .thumb + 355 .syntax unified + 356 .LBE37: + 357 .LBE36: +1942:Drivers/CMSIS/Include/core_cm4.h **** buffered write are completed +1943:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 358 .loc 2 1943 3 view .LVU90 +1944:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 359 .loc 2 1944 32 is_stmt 0 view .LVU91 + 360 0004 0549 ldr r1, .L25 + 361 0006 CA68 ldr r2, [r1, #12] + 362 .loc 2 1944 40 view .LVU92 + 363 0008 02F4E062 and r2, r2, #1792 +1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 364 .loc 2 1943 17 view .LVU93 + 365 000c 044B ldr r3, .L25+4 + 366 000e 1343 orrs r3, r3, r2 +1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 367 .loc 2 1943 15 view .LVU94 + 368 0010 CB60 str r3, [r1, #12] +1945:Drivers/CMSIS/Include/core_cm4.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange +1946:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure completion of memory + 369 .loc 2 1946 3 is_stmt 1 view .LVU95 + 370 .LBB38: + ARM GAS /tmp/ccPJu8Ry.s page 57 + + + 371 .LBI38: + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372 .loc 3 877 27 view .LVU96 + 373 .LBB39: + 374 .loc 3 879 3 view .LVU97 + 375 .syntax unified + 376 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 377 0012 BFF34F8F dsb 0xF + 378 @ 0 "" 2 + 379 .thumb + 380 .syntax unified + 381 .L24: + 382 .LBE39: + 383 .LBE38: +1947:Drivers/CMSIS/Include/core_cm4.h **** +1948:Drivers/CMSIS/Include/core_cm4.h **** for(;;) /* wait until reset */ + 384 .loc 2 1948 3 discriminator 1 view .LVU98 +1949:Drivers/CMSIS/Include/core_cm4.h **** { +1950:Drivers/CMSIS/Include/core_cm4.h **** __NOP(); + 385 .loc 2 1950 5 discriminator 1 view .LVU99 + 386 .syntax unified + 387 @ 1950 "Drivers/CMSIS/Include/core_cm4.h" 1 + 388 0016 00BF nop + 389 @ 0 "" 2 +1948:Drivers/CMSIS/Include/core_cm4.h **** { + 390 .loc 2 1948 3 discriminator 1 view .LVU100 + 391 .thumb + 392 .syntax unified + 393 0018 FDE7 b .L24 + 394 .L26: + 395 001a 00BF .align 2 + 396 .L25: + 397 001c 00ED00E0 .word -536810240 + 398 0020 0400FA05 .word 100270084 + 399 .cfi_endproc + 400 .LFE117: + 402 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits + 403 .align 1 + 404 .global HAL_NVIC_SetPriorityGrouping + 405 .syntax unified + 406 .thumb + 407 .thumb_func + 409 HAL_NVIC_SetPriorityGrouping: + 410 .LVL26: + 411 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @file stm32f3xx_hal_cortex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief CORTEX HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * functionalities of the CORTEX: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + Peripheral Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @verbatim + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + ARM GAS /tmp/ccPJu8Ry.s page 58 + + + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### How to use this driver ##### + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** =========================================================== + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The Cortex-M4 exceptions are managed by CMSIS functions. + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority. + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority): + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest pre-emption priority + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest sub priority + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number) + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ======================================================== + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Setup SysTick Timer for time base + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** is a CMSIS function that: + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x0FU). + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Resets the SysTick Counter register. + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Starts the SysTick Counter. + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** inside the stm32f3xx_hal_cortex.h file. + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ****************************************************************************** + ARM GAS /tmp/ccPJu8Ry.s page 59 + + + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @attention + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * All rights reserved.

    + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * the "License"; You may not use this file except in compliance with the + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * License. You may obtain a copy of the License at: + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * opensource.org/licenses/BSD-3-Clause + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ****************************************************************************** + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Additional Tables: CORTEX_NVIC_Priority_Table + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The table below gives the allowed values of the pre-emption priority and subpriority according + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================ + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================ + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 4 + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -------------------------------------------------------------------------------------------- + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 3 + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -------------------------------------------------------------------------------------------- + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 2 + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -------------------------------------------------------------------------------------------- + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 1 + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -------------------------------------------------------------------------------------------- + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 0 + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================ + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #include "stm32f3xx_hal.h" + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief CORTEX CORTEX HAL module driver + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private typedef -----------------------------------------------------------*/ + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private define ------------------------------------------------------------*/ + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private macro -------------------------------------------------------------*/ + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private function prototypes -----------------------------------------------*/ + ARM GAS /tmp/ccPJu8Ry.s page 60 + + + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Exported functions ---------------------------------------------------------*/ + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initialization and Configuration functions + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @verbatim + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### Initialization and de-initialization functions ##### + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Systick functionalities + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets the priority grouping field (pre-emption priority and subpriority) + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * using the required unlock sequence. + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PriorityGroup The priority grouping bits length. + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values: + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 4 bits for subpriority + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 3 bits for subpriority + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 2 bits for subpriority + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 1 bits for subpriority + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 0 bits for subpriority + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority. + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 412 .loc 1 170 1 view -0 + 413 .cfi_startproc + 414 @ args = 0, pretend = 0, frame = 0 + 415 @ frame_needed = 0, uses_anonymous_args = 0 + 416 @ link register save eliminated. + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 417 .loc 1 172 3 view .LVU102 + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup); + 418 .loc 1 175 3 view .LVU103 + 419 .LBB40: + ARM GAS /tmp/ccPJu8Ry.s page 61 + + + 420 .LBI40: +1657:Drivers/CMSIS/Include/core_cm4.h **** { + 421 .loc 2 1657 22 view .LVU104 + 422 .LBB41: +1659:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a + 423 .loc 2 1659 3 view .LVU105 +1660:Drivers/CMSIS/Include/core_cm4.h **** + 424 .loc 2 1660 3 view .LVU106 +1662:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan + 425 .loc 2 1662 3 view .LVU107 +1662:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan + 426 .loc 2 1662 14 is_stmt 0 view .LVU108 + 427 0000 074A ldr r2, .L28 + 428 0002 D368 ldr r3, [r2, #12] + 429 .LVL27: +1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | + 430 .loc 2 1663 3 is_stmt 1 view .LVU109 +1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | + 431 .loc 2 1663 13 is_stmt 0 view .LVU110 + 432 0004 23F4E063 bic r3, r3, #1792 + 433 .LVL28: +1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | + 434 .loc 2 1663 13 view .LVU111 + 435 0008 1B04 lsls r3, r3, #16 + 436 000a 1B0C lsrs r3, r3, #16 + 437 .LVL29: +1664:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 438 .loc 2 1664 3 is_stmt 1 view .LVU112 +1666:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value; + 439 .loc 2 1666 35 is_stmt 0 view .LVU113 + 440 000c 0002 lsls r0, r0, #8 + 441 .LVL30: +1666:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value; + 442 .loc 2 1666 35 view .LVU114 + 443 000e 00F4E060 and r0, r0, #1792 +1665:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a + 444 .loc 2 1665 62 view .LVU115 + 445 0012 0343 orrs r3, r3, r0 + 446 .LVL31: +1664:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 447 .loc 2 1664 14 view .LVU116 + 448 0014 43F0BF63 orr r3, r3, #100139008 + 449 0018 43F40033 orr r3, r3, #131072 + 450 .LVL32: +1667:Drivers/CMSIS/Include/core_cm4.h **** } + 451 .loc 2 1667 3 is_stmt 1 view .LVU117 +1667:Drivers/CMSIS/Include/core_cm4.h **** } + 452 .loc 2 1667 14 is_stmt 0 view .LVU118 + 453 001c D360 str r3, [r2, #12] + 454 .LVL33: +1667:Drivers/CMSIS/Include/core_cm4.h **** } + 455 .loc 2 1667 14 view .LVU119 + 456 .LBE41: + 457 .LBE40: + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 458 .loc 1 176 1 view .LVU120 + 459 001e 7047 bx lr + ARM GAS /tmp/ccPJu8Ry.s page 62 + + + 460 .L29: + 461 .align 2 + 462 .L28: + 463 0020 00ED00E0 .word -536810240 + 464 .cfi_endproc + 465 .LFE130: + 467 .section .text.HAL_NVIC_SetPriority,"ax",%progbits + 468 .align 1 + 469 .global HAL_NVIC_SetPriority + 470 .syntax unified + 471 .thumb + 472 .thumb_func + 474 HAL_NVIC_SetPriority: + 475 .LVL34: + 476 .LFB131: + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PreemptPriority The pre-emption priority for the IRQn channel. + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Pr + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * A lower priority value indicates a higher priority + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel. + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Pr + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * A lower priority value indicates a higher priority. + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 477 .loc 1 192 1 is_stmt 1 view -0 + 478 .cfi_startproc + 479 @ args = 0, pretend = 0, frame = 0 + 480 @ frame_needed = 0, uses_anonymous_args = 0 + 481 .loc 1 192 1 is_stmt 0 view .LVU122 + 482 0000 10B5 push {r4, lr} + 483 .cfi_def_cfa_offset 8 + 484 .cfi_offset 4, -8 + 485 .cfi_offset 14, -4 + 486 0002 0446 mov r4, r0 + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t prioritygroup = 0x00U; + 487 .loc 1 193 3 is_stmt 1 view .LVU123 + 488 .LVL35: + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + 489 .loc 1 196 3 view .LVU124 + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + 490 .loc 1 197 3 view .LVU125 + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping(); + 491 .loc 1 199 3 view .LVU126 + 492 .LBB42: + 493 .LBI42: +1676:Drivers/CMSIS/Include/core_cm4.h **** { + 494 .loc 2 1676 26 view .LVU127 + ARM GAS /tmp/ccPJu8Ry.s page 63 + + + 495 .LBB43: +1678:Drivers/CMSIS/Include/core_cm4.h **** } + 496 .loc 2 1678 3 view .LVU128 +1678:Drivers/CMSIS/Include/core_cm4.h **** } + 497 .loc 2 1678 26 is_stmt 0 view .LVU129 + 498 0004 054B ldr r3, .L32 + 499 0006 D868 ldr r0, [r3, #12] + 500 .LVL36: +1678:Drivers/CMSIS/Include/core_cm4.h **** } + 501 .loc 2 1678 26 view .LVU130 + 502 .LBE43: + 503 .LBE42: + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 504 .loc 1 201 3 is_stmt 1 view .LVU131 + 505 0008 C0F30220 ubfx r0, r0, #8, #3 + 506 .LVL37: + 507 .loc 1 201 3 is_stmt 0 view .LVU132 + 508 000c FFF7FEFF bl NVIC_EncodePriority + 509 .LVL38: + 510 .loc 1 201 3 view .LVU133 + 511 0010 0146 mov r1, r0 + 512 0012 2046 mov r0, r4 + 513 0014 FFF7FEFF bl __NVIC_SetPriority + 514 .LVL39: + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 515 .loc 1 202 1 view .LVU134 + 516 0018 10BD pop {r4, pc} + 517 .L33: + 518 001a 00BF .align 2 + 519 .L32: + 520 001c 00ED00E0 .word -536810240 + 521 .cfi_endproc + 522 .LFE131: + 524 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits + 525 .align 1 + 526 .global HAL_NVIC_EnableIRQ + 527 .syntax unified + 528 .thumb + 529 .thumb_func + 531 HAL_NVIC_EnableIRQ: + 532 .LVL40: + 533 .LFB132: + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller. + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * function should be called before. + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 534 .loc 1 214 1 is_stmt 1 view -0 + 535 .cfi_startproc + ARM GAS /tmp/ccPJu8Ry.s page 64 + + + 536 @ args = 0, pretend = 0, frame = 0 + 537 @ frame_needed = 0, uses_anonymous_args = 0 + 538 @ link register save eliminated. + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 539 .loc 1 216 3 view .LVU136 + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable interrupt */ + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); + 540 .loc 1 219 3 view .LVU137 + 541 .LBB44: + 542 .LBI44: +1688:Drivers/CMSIS/Include/core_cm4.h **** { + 543 .loc 2 1688 22 view .LVU138 + 544 .LBB45: +1690:Drivers/CMSIS/Include/core_cm4.h **** { + 545 .loc 2 1690 3 view .LVU139 +1690:Drivers/CMSIS/Include/core_cm4.h **** { + 546 .loc 2 1690 6 is_stmt 0 view .LVU140 + 547 0000 0028 cmp r0, #0 + 548 .LVL41: +1690:Drivers/CMSIS/Include/core_cm4.h **** { + 549 .loc 2 1690 6 view .LVU141 + 550 0002 07DB blt .L34 +1692:Drivers/CMSIS/Include/core_cm4.h **** } + 551 .loc 2 1692 5 is_stmt 1 view .LVU142 +1692:Drivers/CMSIS/Include/core_cm4.h **** } + 552 .loc 2 1692 81 is_stmt 0 view .LVU143 + 553 0004 00F01F02 and r2, r0, #31 +1692:Drivers/CMSIS/Include/core_cm4.h **** } + 554 .loc 2 1692 34 view .LVU144 + 555 0008 4009 lsrs r0, r0, #5 +1692:Drivers/CMSIS/Include/core_cm4.h **** } + 556 .loc 2 1692 45 view .LVU145 + 557 000a 0123 movs r3, #1 + 558 000c 9340 lsls r3, r3, r2 +1692:Drivers/CMSIS/Include/core_cm4.h **** } + 559 .loc 2 1692 43 view .LVU146 + 560 000e 024A ldr r2, .L36 + 561 0010 42F82030 str r3, [r2, r0, lsl #2] + 562 .LVL42: + 563 .L34: +1692:Drivers/CMSIS/Include/core_cm4.h **** } + 564 .loc 2 1692 43 view .LVU147 + 565 .LBE45: + 566 .LBE44: + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 567 .loc 1 220 1 view .LVU148 + 568 0014 7047 bx lr + 569 .L37: + 570 0016 00BF .align 2 + 571 .L36: + 572 0018 00E100E0 .word -536813312 + 573 .cfi_endproc + 574 .LFE132: + 576 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits + 577 .align 1 + ARM GAS /tmp/ccPJu8Ry.s page 65 + + + 578 .global HAL_NVIC_DisableIRQ + 579 .syntax unified + 580 .thumb + 581 .thumb_func + 583 HAL_NVIC_DisableIRQ: + 584 .LVL43: + 585 .LFB133: + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller. + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 586 .loc 1 230 1 is_stmt 1 view -0 + 587 .cfi_startproc + 588 @ args = 0, pretend = 0, frame = 0 + 589 @ frame_needed = 0, uses_anonymous_args = 0 + 590 .loc 1 230 1 is_stmt 0 view .LVU150 + 591 0000 08B5 push {r3, lr} + 592 .cfi_def_cfa_offset 8 + 593 .cfi_offset 3, -8 + 594 .cfi_offset 14, -4 + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 595 .loc 1 232 3 is_stmt 1 view .LVU151 + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable interrupt */ + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); + 596 .loc 1 235 3 view .LVU152 + 597 0002 FFF7FEFF bl __NVIC_DisableIRQ + 598 .LVL44: + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 599 .loc 1 236 1 is_stmt 0 view .LVU153 + 600 0006 08BD pop {r3, pc} + 601 .cfi_endproc + 602 .LFE133: + 604 .section .text.HAL_NVIC_SystemReset,"ax",%progbits + 605 .align 1 + 606 .global HAL_NVIC_SystemReset + 607 .syntax unified + 608 .thumb + 609 .thumb_func + 611 HAL_NVIC_SystemReset: + 612 .LFB134: + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU. + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 613 .loc 1 243 1 is_stmt 1 view -0 + 614 .cfi_startproc + ARM GAS /tmp/ccPJu8Ry.s page 66 + + + 615 @ Volatile: function does not return. + 616 @ args = 0, pretend = 0, frame = 0 + 617 @ frame_needed = 0, uses_anonymous_args = 0 + 618 0000 08B5 push {r3, lr} + 619 .cfi_def_cfa_offset 8 + 620 .cfi_offset 3, -8 + 621 .cfi_offset 14, -4 + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* System Reset */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SystemReset(); + 622 .loc 1 245 3 view .LVU155 + 623 0002 FFF7FEFF bl __NVIC_SystemReset + 624 .LVL45: + 625 .cfi_endproc + 626 .LFE134: + 628 .section .text.HAL_SYSTICK_Config,"ax",%progbits + 629 .align 1 + 630 .global HAL_SYSTICK_Config + 631 .syntax unified + 632 .thumb + 633 .thumb_func + 635 HAL_SYSTICK_Config: + 636 .LVL46: + 637 .LFB135: + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Function failed. + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 638 .loc 1 256 1 view -0 + 639 .cfi_startproc + 640 @ args = 0, pretend = 0, frame = 0 + 641 @ frame_needed = 0, uses_anonymous_args = 0 + 642 @ link register save eliminated. + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return SysTick_Config(TicksNumb); + 643 .loc 1 257 4 view .LVU157 + 644 .LBB46: + 645 .LBI46: +1951:Drivers/CMSIS/Include/core_cm4.h **** } +1952:Drivers/CMSIS/Include/core_cm4.h **** } +1953:Drivers/CMSIS/Include/core_cm4.h **** +1954:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_NVICFunctions */ +1955:Drivers/CMSIS/Include/core_cm4.h **** +1956:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## MPU functions #################################### */ +1957:Drivers/CMSIS/Include/core_cm4.h **** +1958:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1959:Drivers/CMSIS/Include/core_cm4.h **** +1960:Drivers/CMSIS/Include/core_cm4.h **** #include "mpu_armv7.h" +1961:Drivers/CMSIS/Include/core_cm4.h **** +1962:Drivers/CMSIS/Include/core_cm4.h **** #endif +1963:Drivers/CMSIS/Include/core_cm4.h **** +1964:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccPJu8Ry.s page 67 + + +1965:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## FPU functions #################################### */ +1966:Drivers/CMSIS/Include/core_cm4.h **** /** +1967:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface +1968:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions +1969:Drivers/CMSIS/Include/core_cm4.h **** \brief Function that provides FPU type. +1970:Drivers/CMSIS/Include/core_cm4.h **** @{ +1971:Drivers/CMSIS/Include/core_cm4.h **** */ +1972:Drivers/CMSIS/Include/core_cm4.h **** +1973:Drivers/CMSIS/Include/core_cm4.h **** /** +1974:Drivers/CMSIS/Include/core_cm4.h **** \brief get FPU type +1975:Drivers/CMSIS/Include/core_cm4.h **** \details returns the FPU type +1976:Drivers/CMSIS/Include/core_cm4.h **** \returns +1977:Drivers/CMSIS/Include/core_cm4.h **** - \b 0: No FPU +1978:Drivers/CMSIS/Include/core_cm4.h **** - \b 1: Single precision FPU +1979:Drivers/CMSIS/Include/core_cm4.h **** - \b 2: Double + Single precision FPU +1980:Drivers/CMSIS/Include/core_cm4.h **** */ +1981:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) +1982:Drivers/CMSIS/Include/core_cm4.h **** { +1983:Drivers/CMSIS/Include/core_cm4.h **** uint32_t mvfr0; +1984:Drivers/CMSIS/Include/core_cm4.h **** +1985:Drivers/CMSIS/Include/core_cm4.h **** mvfr0 = FPU->MVFR0; +1986:Drivers/CMSIS/Include/core_cm4.h **** if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) +1987:Drivers/CMSIS/Include/core_cm4.h **** { +1988:Drivers/CMSIS/Include/core_cm4.h **** return 1U; /* Single precision FPU */ +1989:Drivers/CMSIS/Include/core_cm4.h **** } +1990:Drivers/CMSIS/Include/core_cm4.h **** else +1991:Drivers/CMSIS/Include/core_cm4.h **** { +1992:Drivers/CMSIS/Include/core_cm4.h **** return 0U; /* No FPU */ +1993:Drivers/CMSIS/Include/core_cm4.h **** } +1994:Drivers/CMSIS/Include/core_cm4.h **** } +1995:Drivers/CMSIS/Include/core_cm4.h **** +1996:Drivers/CMSIS/Include/core_cm4.h **** +1997:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_FpuFunctions */ +1998:Drivers/CMSIS/Include/core_cm4.h **** +1999:Drivers/CMSIS/Include/core_cm4.h **** +2000:Drivers/CMSIS/Include/core_cm4.h **** +2001:Drivers/CMSIS/Include/core_cm4.h **** /* ################################## SysTick function ######################################## +2002:Drivers/CMSIS/Include/core_cm4.h **** /** +2003:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface +2004:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions +2005:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that configure the System. +2006:Drivers/CMSIS/Include/core_cm4.h **** @{ +2007:Drivers/CMSIS/Include/core_cm4.h **** */ +2008:Drivers/CMSIS/Include/core_cm4.h **** +2009:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) +2010:Drivers/CMSIS/Include/core_cm4.h **** +2011:Drivers/CMSIS/Include/core_cm4.h **** /** +2012:Drivers/CMSIS/Include/core_cm4.h **** \brief System Tick Configuration +2013:Drivers/CMSIS/Include/core_cm4.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. +2014:Drivers/CMSIS/Include/core_cm4.h **** Counter is in free running mode to generate periodic interrupts. +2015:Drivers/CMSIS/Include/core_cm4.h **** \param [in] ticks Number of ticks between two interrupts. +2016:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Function succeeded. +2017:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Function failed. +2018:Drivers/CMSIS/Include/core_cm4.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the +2019:Drivers/CMSIS/Include/core_cm4.h **** function SysTick_Config is not included. In this case, the file device. +2020:Drivers/CMSIS/Include/core_cm4.h **** must contain a vendor-specific implementation of this function. +2021:Drivers/CMSIS/Include/core_cm4.h **** */ + ARM GAS /tmp/ccPJu8Ry.s page 68 + + +2022:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + 646 .loc 2 2022 26 view .LVU158 + 647 .LBB47: +2023:Drivers/CMSIS/Include/core_cm4.h **** { +2024:Drivers/CMSIS/Include/core_cm4.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 648 .loc 2 2024 3 view .LVU159 + 649 .loc 2 2024 14 is_stmt 0 view .LVU160 + 650 0000 0138 subs r0, r0, #1 + 651 .LVL47: + 652 .loc 2 2024 6 view .LVU161 + 653 0002 B0F1807F cmp r0, #16777216 + 654 0006 0BD2 bcs .L44 +2025:Drivers/CMSIS/Include/core_cm4.h **** { +2026:Drivers/CMSIS/Include/core_cm4.h **** return (1UL); /* Reload value impossible */ +2027:Drivers/CMSIS/Include/core_cm4.h **** } +2028:Drivers/CMSIS/Include/core_cm4.h **** +2029:Drivers/CMSIS/Include/core_cm4.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 655 .loc 2 2029 3 is_stmt 1 view .LVU162 + 656 .loc 2 2029 18 is_stmt 0 view .LVU163 + 657 0008 4FF0E023 mov r3, #-536813568 + 658 000c 5861 str r0, [r3, #20] +2030:Drivers/CMSIS/Include/core_cm4.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int + 659 .loc 2 2030 3 is_stmt 1 view .LVU164 + 660 .LVL48: + 661 .LBB48: + 662 .LBI48: +1816:Drivers/CMSIS/Include/core_cm4.h **** { + 663 .loc 2 1816 22 view .LVU165 + 664 .LBB49: +1818:Drivers/CMSIS/Include/core_cm4.h **** { + 665 .loc 2 1818 3 view .LVU166 +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 666 .loc 2 1824 5 view .LVU167 +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 667 .loc 2 1824 46 is_stmt 0 view .LVU168 + 668 000e 054A ldr r2, .L45 + 669 0010 F021 movs r1, #240 + 670 0012 82F82310 strb r1, [r2, #35] + 671 .LVL49: +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 672 .loc 2 1824 46 view .LVU169 + 673 .LBE49: + 674 .LBE48: +2031:Drivers/CMSIS/Include/core_cm4.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val + 675 .loc 2 2031 3 is_stmt 1 view .LVU170 + 676 .loc 2 2031 18 is_stmt 0 view .LVU171 + 677 0016 0020 movs r0, #0 + 678 .LVL50: + 679 .loc 2 2031 18 view .LVU172 + 680 0018 9861 str r0, [r3, #24] +2032:Drivers/CMSIS/Include/core_cm4.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 681 .loc 2 2032 3 is_stmt 1 view .LVU173 + 682 .loc 2 2032 18 is_stmt 0 view .LVU174 + 683 001a 0722 movs r2, #7 + 684 001c 1A61 str r2, [r3, #16] +2033:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_TICKINT_Msk | +2034:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi + ARM GAS /tmp/ccPJu8Ry.s page 69 + + +2035:Drivers/CMSIS/Include/core_cm4.h **** return (0UL); /* Function successful */ + 685 .loc 2 2035 3 is_stmt 1 view .LVU175 + 686 .loc 2 2035 10 is_stmt 0 view .LVU176 + 687 001e 7047 bx lr + 688 .L44: +2026:Drivers/CMSIS/Include/core_cm4.h **** } + 689 .loc 2 2026 12 view .LVU177 + 690 0020 0120 movs r0, #1 + 691 .LVL51: +2026:Drivers/CMSIS/Include/core_cm4.h **** } + 692 .loc 2 2026 12 view .LVU178 + 693 .LBE47: + 694 .LBE46: + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 695 .loc 1 258 1 view .LVU179 + 696 0022 7047 bx lr + 697 .L46: + 698 .align 2 + 699 .L45: + 700 0024 00ED00E0 .word -536810240 + 701 .cfi_endproc + 702 .LFE135: + 704 .section .text.HAL_MPU_Disable,"ax",%progbits + 705 .align 1 + 706 .global HAL_MPU_Disable + 707 .syntax unified + 708 .thumb + 709 .thumb_func + 711 HAL_MPU_Disable: + 712 .LFB136: + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @} + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Cortex control functions + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @verbatim + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### Peripheral Control functions ##### + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities. + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U) + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation) + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_Disable(void) + ARM GAS /tmp/ccPJu8Ry.s page 70 + + + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 713 .loc 1 286 1 is_stmt 1 view -0 + 714 .cfi_startproc + 715 @ args = 0, pretend = 0, frame = 0 + 716 @ frame_needed = 0, uses_anonymous_args = 0 + 717 @ link register save eliminated. + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable fault exceptions */ + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + 718 .loc 1 288 3 view .LVU181 + 719 .loc 1 288 6 is_stmt 0 view .LVU182 + 720 0000 044B ldr r3, .L48 + 721 0002 5A6A ldr r2, [r3, #36] + 722 .loc 1 288 14 view .LVU183 + 723 0004 22F48032 bic r2, r2, #65536 + 724 0008 5A62 str r2, [r3, #36] + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable the MPU */ + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->CTRL = 0U; + 725 .loc 1 291 3 is_stmt 1 view .LVU184 + 726 .loc 1 291 13 is_stmt 0 view .LVU185 + 727 000a 0022 movs r2, #0 + 728 000c C3F89420 str r2, [r3, #148] + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 729 .loc 1 292 1 view .LVU186 + 730 0010 7047 bx lr + 731 .L49: + 732 0012 00BF .align 2 + 733 .L48: + 734 0014 00ED00E0 .word -536810240 + 735 .cfi_endproc + 736 .LFE136: + 738 .section .text.HAL_MPU_Enable,"ax",%progbits + 739 .align 1 + 740 .global HAL_MPU_Enable + 741 .syntax unified + 742 .thumb + 743 .thumb_func + 745 HAL_MPU_Enable: + 746 .LVL52: + 747 .LFB137: + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Enables the MPU + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param MPU_Control Specifies the control mode of the MPU during hard fault, + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values: + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control) + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 748 .loc 1 306 1 is_stmt 1 view -0 + 749 .cfi_startproc + 750 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccPJu8Ry.s page 71 + + + 751 @ frame_needed = 0, uses_anonymous_args = 0 + 752 @ link register save eliminated. + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable the MPU */ + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + 753 .loc 1 308 3 view .LVU188 + 754 .loc 1 308 29 is_stmt 0 view .LVU189 + 755 0000 40F00100 orr r0, r0, #1 + 756 .LVL53: + 757 .loc 1 308 15 view .LVU190 + 758 0004 034B ldr r3, .L51 + 759 0006 C3F89400 str r0, [r3, #148] + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable fault exceptions */ + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + 760 .loc 1 311 3 is_stmt 1 view .LVU191 + 761 .loc 1 311 6 is_stmt 0 view .LVU192 + 762 000a 5A6A ldr r2, [r3, #36] + 763 .loc 1 311 14 view .LVU193 + 764 000c 42F48032 orr r2, r2, #65536 + 765 0010 5A62 str r2, [r3, #36] + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 766 .loc 1 312 1 view .LVU194 + 767 0012 7047 bx lr + 768 .L52: + 769 .align 2 + 770 .L51: + 771 0014 00ED00E0 .word -536810240 + 772 .cfi_endproc + 773 .LFE137: + 775 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits + 776 .align 1 + 777 .global HAL_MPU_ConfigRegion + 778 .syntax unified + 779 .thumb + 780 .thumb_func + 782 HAL_MPU_ConfigRegion: + 783 .LVL54: + 784 .LFB138: + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected. + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * the initialization and configuration information. + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 785 .loc 1 321 1 is_stmt 1 view -0 + 786 .cfi_startproc + 787 @ args = 0, pretend = 0, frame = 0 + 788 @ frame_needed = 0, uses_anonymous_args = 0 + 789 @ link register save eliminated. + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + 790 .loc 1 323 3 view .LVU196 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + 791 .loc 1 324 3 view .LVU197 + ARM GAS /tmp/ccPJu8Ry.s page 72 + + + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set the Region number */ + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; + 792 .loc 1 327 3 view .LVU198 + 793 .loc 1 327 22 is_stmt 0 view .LVU199 + 794 0000 4278 ldrb r2, [r0, #1] @ zero_extendqisi2 + 795 .loc 1 327 12 view .LVU200 + 796 0002 164B ldr r3, .L56 + 797 0004 C3F89820 str r2, [r3, #152] + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** if ((MPU_Init->Enable) != RESET) + 798 .loc 1 329 3 is_stmt 1 view .LVU201 + 799 .loc 1 329 16 is_stmt 0 view .LVU202 + 800 0008 0378 ldrb r3, [r0] @ zero_extendqisi2 + 801 .loc 1 329 6 view .LVU203 + 802 000a FBB1 cbz r3, .L54 + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + 803 .loc 1 332 5 is_stmt 1 view .LVU204 + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + 804 .loc 1 333 5 view .LVU205 + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + 805 .loc 1 334 5 view .LVU206 + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + 806 .loc 1 335 5 view .LVU207 + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + 807 .loc 1 336 5 view .LVU208 + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + 808 .loc 1 337 5 view .LVU209 + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + 809 .loc 1 338 5 view .LVU210 + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + 810 .loc 1 339 5 view .LVU211 + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress; + 811 .loc 1 341 5 view .LVU212 + 812 .loc 1 341 25 is_stmt 0 view .LVU213 + 813 000c 4368 ldr r3, [r0, #4] + 814 .loc 1 341 15 view .LVU214 + 815 000e 134A ldr r2, .L56 + 816 0010 C2F89C30 str r3, [r2, #156] + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 817 .loc 1 342 5 is_stmt 1 view .LVU215 + 818 .loc 1 342 36 is_stmt 0 view .LVU216 + 819 0014 017B ldrb r1, [r0, #12] @ zero_extendqisi2 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 820 .loc 1 343 36 view .LVU217 + 821 0016 C37A ldrb r3, [r0, #11] @ zero_extendqisi2 + 822 .loc 1 343 62 view .LVU218 + 823 0018 1B06 lsls r3, r3, #24 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 824 .loc 1 342 84 view .LVU219 + 825 001a 43EA0173 orr r3, r3, r1, lsl #28 + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 826 .loc 1 344 36 view .LVU220 + 827 001e 817A ldrb r1, [r0, #10] @ zero_extendqisi2 + ARM GAS /tmp/ccPJu8Ry.s page 73 + + + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 828 .loc 1 343 84 view .LVU221 + 829 0020 43EAC143 orr r3, r3, r1, lsl #19 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 830 .loc 1 345 36 view .LVU222 + 831 0024 417B ldrb r1, [r0, #13] @ zero_extendqisi2 + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 832 .loc 1 344 84 view .LVU223 + 833 0026 43EA8143 orr r3, r3, r1, lsl #18 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 834 .loc 1 346 36 view .LVU224 + 835 002a 817B ldrb r1, [r0, #14] @ zero_extendqisi2 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 836 .loc 1 345 84 view .LVU225 + 837 002c 43EA4143 orr r3, r3, r1, lsl #17 + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 838 .loc 1 347 36 view .LVU226 + 839 0030 C17B ldrb r1, [r0, #15] @ zero_extendqisi2 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 840 .loc 1 346 84 view .LVU227 + 841 0032 43EA0143 orr r3, r3, r1, lsl #16 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 842 .loc 1 348 36 view .LVU228 + 843 0036 417A ldrb r1, [r0, #9] @ zero_extendqisi2 + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 844 .loc 1 347 84 view .LVU229 + 845 0038 43EA0123 orr r3, r3, r1, lsl #8 + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 846 .loc 1 349 36 view .LVU230 + 847 003c 017A ldrb r1, [r0, #8] @ zero_extendqisi2 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 848 .loc 1 348 84 view .LVU231 + 849 003e 43EA4103 orr r3, r3, r1, lsl #1 + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 850 .loc 1 350 36 view .LVU232 + 851 0042 0178 ldrb r1, [r0] @ zero_extendqisi2 + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 852 .loc 1 349 84 view .LVU233 + 853 0044 0B43 orrs r3, r3, r1 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 854 .loc 1 342 15 view .LVU234 + 855 0046 C2F8A030 str r3, [r2, #160] + 856 004a 7047 bx lr + 857 .L54: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** else + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RBAR = 0x00U; + 858 .loc 1 354 5 is_stmt 1 view .LVU235 + 859 .loc 1 354 15 is_stmt 0 view .LVU236 + 860 004c 034B ldr r3, .L56 + 861 004e 0022 movs r2, #0 + 862 0050 C3F89C20 str r2, [r3, #156] + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = 0x00U; + 863 .loc 1 355 5 is_stmt 1 view .LVU237 + 864 .loc 1 355 15 is_stmt 0 view .LVU238 + 865 0054 C3F8A020 str r2, [r3, #160] + ARM GAS /tmp/ccPJu8Ry.s page 74 + + + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 866 .loc 1 357 1 view .LVU239 + 867 0058 7047 bx lr + 868 .L57: + 869 005a 00BF .align 2 + 870 .L56: + 871 005c 00ED00E0 .word -536810240 + 872 .cfi_endproc + 873 .LFE138: + 875 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits + 876 .align 1 + 877 .global HAL_NVIC_GetPriorityGrouping + 878 .syntax unified + 879 .thumb + 880 .thumb_func + 882 HAL_NVIC_GetPriorityGrouping: + 883 .LFB139: + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #endif /* __MPU_PRESENT */ + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void) + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 884 .loc 1 365 1 is_stmt 1 view -0 + 885 .cfi_startproc + 886 @ args = 0, pretend = 0, frame = 0 + 887 @ frame_needed = 0, uses_anonymous_args = 0 + 888 @ link register save eliminated. + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */ + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetPriorityGrouping(); + 889 .loc 1 367 3 view .LVU241 + 890 .LBB50: + 891 .LBI50: +1676:Drivers/CMSIS/Include/core_cm4.h **** { + 892 .loc 2 1676 26 view .LVU242 + 893 .LBB51: +1678:Drivers/CMSIS/Include/core_cm4.h **** } + 894 .loc 2 1678 3 view .LVU243 +1678:Drivers/CMSIS/Include/core_cm4.h **** } + 895 .loc 2 1678 26 is_stmt 0 view .LVU244 + 896 0000 024B ldr r3, .L59 + 897 0002 D868 ldr r0, [r3, #12] + 898 .LBE51: + 899 .LBE50: + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 900 .loc 1 368 1 view .LVU245 + 901 0004 C0F30220 ubfx r0, r0, #8, #3 + 902 0008 7047 bx lr + 903 .L60: + 904 000a 00BF .align 2 + 905 .L59: + 906 000c 00ED00E0 .word -536810240 + 907 .cfi_endproc + 908 .LFE139: + ARM GAS /tmp/ccPJu8Ry.s page 75 + + + 910 .section .text.HAL_NVIC_GetPriority,"ax",%progbits + 911 .align 1 + 912 .global HAL_NVIC_GetPriority + 913 .syntax unified + 914 .thumb + 915 .thumb_func + 917 HAL_NVIC_GetPriority: + 918 .LVL55: + 919 .LFB140: + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets the priority of an interrupt. + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PriorityGroup: the priority grouping bits length. + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values: + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 4 bits for subpriority + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 3 bits for subpriority + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 2 bits for subpriority + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 1 bits for subpriority + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 0 bits for subpriority + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param pSubPriority Pointer on the Subpriority value (starting from 0). + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint3 + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 920 .loc 1 392 1 is_stmt 1 view -0 + 921 .cfi_startproc + 922 @ args = 0, pretend = 0, frame = 0 + 923 @ frame_needed = 0, uses_anonymous_args = 0 + 924 .loc 1 392 1 is_stmt 0 view .LVU247 + 925 0000 70B5 push {r4, r5, r6, lr} + 926 .cfi_def_cfa_offset 16 + 927 .cfi_offset 4, -16 + 928 .cfi_offset 5, -12 + 929 .cfi_offset 6, -8 + 930 .cfi_offset 14, -4 + 931 0002 0C46 mov r4, r1 + 932 0004 1546 mov r5, r2 + 933 0006 1E46 mov r6, r3 + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 934 .loc 1 394 3 is_stmt 1 view .LVU248 + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); + 935 .loc 1 396 3 view .LVU249 + 936 0008 FFF7FEFF bl __NVIC_GetPriority + 937 .LVL56: + 938 .loc 1 396 3 is_stmt 0 view .LVU250 + 939 000c 3346 mov r3, r6 + ARM GAS /tmp/ccPJu8Ry.s page 76 + + + 940 000e 2A46 mov r2, r5 + 941 0010 2146 mov r1, r4 + 942 0012 FFF7FEFF bl NVIC_DecodePriority + 943 .LVL57: + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 944 .loc 1 397 1 view .LVU251 + 945 0016 70BD pop {r4, r5, r6, pc} + 946 .loc 1 397 1 view .LVU252 + 947 .cfi_endproc + 948 .LFE140: + 950 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits + 951 .align 1 + 952 .global HAL_NVIC_SetPendingIRQ + 953 .syntax unified + 954 .thumb + 955 .thumb_func + 957 HAL_NVIC_SetPendingIRQ: + 958 .LVL58: + 959 .LFB141: + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 960 .loc 1 407 1 is_stmt 1 view -0 + 961 .cfi_startproc + 962 @ args = 0, pretend = 0, frame = 0 + 963 @ frame_needed = 0, uses_anonymous_args = 0 + 964 @ link register save eliminated. + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set interrupt pending */ + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); + 965 .loc 1 409 3 view .LVU254 + 966 .LBB52: + 967 .LBI52: +1762:Drivers/CMSIS/Include/core_cm4.h **** { + 968 .loc 2 1762 22 view .LVU255 + 969 .LBB53: +1764:Drivers/CMSIS/Include/core_cm4.h **** { + 970 .loc 2 1764 3 view .LVU256 +1764:Drivers/CMSIS/Include/core_cm4.h **** { + 971 .loc 2 1764 6 is_stmt 0 view .LVU257 + 972 0000 0028 cmp r0, #0 + 973 .LVL59: +1764:Drivers/CMSIS/Include/core_cm4.h **** { + 974 .loc 2 1764 6 view .LVU258 + 975 0002 08DB blt .L63 +1766:Drivers/CMSIS/Include/core_cm4.h **** } + 976 .loc 2 1766 5 is_stmt 1 view .LVU259 +1766:Drivers/CMSIS/Include/core_cm4.h **** } + 977 .loc 2 1766 81 is_stmt 0 view .LVU260 + 978 0004 00F01F02 and r2, r0, #31 +1766:Drivers/CMSIS/Include/core_cm4.h **** } + ARM GAS /tmp/ccPJu8Ry.s page 77 + + + 979 .loc 2 1766 34 view .LVU261 + 980 0008 4009 lsrs r0, r0, #5 +1766:Drivers/CMSIS/Include/core_cm4.h **** } + 981 .loc 2 1766 45 view .LVU262 + 982 000a 0123 movs r3, #1 + 983 000c 9340 lsls r3, r3, r2 +1766:Drivers/CMSIS/Include/core_cm4.h **** } + 984 .loc 2 1766 43 view .LVU263 + 985 000e 4030 adds r0, r0, #64 + 986 0010 014A ldr r2, .L65 + 987 0012 42F82030 str r3, [r2, r0, lsl #2] + 988 .LVL60: + 989 .L63: +1766:Drivers/CMSIS/Include/core_cm4.h **** } + 990 .loc 2 1766 43 view .LVU264 + 991 .LBE53: + 992 .LBE52: + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 993 .loc 1 410 1 view .LVU265 + 994 0016 7047 bx lr + 995 .L66: + 996 .align 2 + 997 .L65: + 998 0018 00E100E0 .word -536813312 + 999 .cfi_endproc + 1000 .LFE141: + 1002 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits + 1003 .align 1 + 1004 .global HAL_NVIC_GetPendingIRQ + 1005 .syntax unified + 1006 .thumb + 1007 .thumb_func + 1009 HAL_NVIC_GetPendingIRQ: + 1010 .LVL61: + 1011 .LFB142: + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt). + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1012 .loc 1 422 1 is_stmt 1 view -0 + 1013 .cfi_startproc + 1014 @ args = 0, pretend = 0, frame = 0 + 1015 @ frame_needed = 0, uses_anonymous_args = 0 + 1016 @ link register save eliminated. + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Return 1 if pending else 0U */ + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); + 1017 .loc 1 424 3 view .LVU267 + 1018 .LBB54: + 1019 .LBI54: + ARM GAS /tmp/ccPJu8Ry.s page 78 + + +1743:Drivers/CMSIS/Include/core_cm4.h **** { + 1020 .loc 2 1743 26 view .LVU268 + 1021 .LBB55: +1745:Drivers/CMSIS/Include/core_cm4.h **** { + 1022 .loc 2 1745 3 view .LVU269 +1745:Drivers/CMSIS/Include/core_cm4.h **** { + 1023 .loc 2 1745 6 is_stmt 0 view .LVU270 + 1024 0000 0028 cmp r0, #0 + 1025 .LVL62: +1745:Drivers/CMSIS/Include/core_cm4.h **** { + 1026 .loc 2 1745 6 view .LVU271 + 1027 0002 0BDB blt .L69 +1747:Drivers/CMSIS/Include/core_cm4.h **** } + 1028 .loc 2 1747 5 is_stmt 1 view .LVU272 +1747:Drivers/CMSIS/Include/core_cm4.h **** } + 1029 .loc 2 1747 54 is_stmt 0 view .LVU273 + 1030 0004 4309 lsrs r3, r0, #5 +1747:Drivers/CMSIS/Include/core_cm4.h **** } + 1031 .loc 2 1747 35 view .LVU274 + 1032 0006 4033 adds r3, r3, #64 + 1033 0008 054A ldr r2, .L70 + 1034 000a 52F82330 ldr r3, [r2, r3, lsl #2] +1747:Drivers/CMSIS/Include/core_cm4.h **** } + 1035 .loc 2 1747 91 view .LVU275 + 1036 000e 00F01F00 and r0, r0, #31 +1747:Drivers/CMSIS/Include/core_cm4.h **** } + 1037 .loc 2 1747 103 view .LVU276 + 1038 0012 23FA00F0 lsr r0, r3, r0 +1747:Drivers/CMSIS/Include/core_cm4.h **** } + 1039 .loc 2 1747 12 view .LVU277 + 1040 0016 00F00100 and r0, r0, #1 + 1041 001a 7047 bx lr + 1042 .L69: +1751:Drivers/CMSIS/Include/core_cm4.h **** } + 1043 .loc 2 1751 11 view .LVU278 + 1044 001c 0020 movs r0, #0 + 1045 .LVL63: +1751:Drivers/CMSIS/Include/core_cm4.h **** } + 1046 .loc 2 1751 11 view .LVU279 + 1047 .LBE55: + 1048 .LBE54: + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1049 .loc 1 425 1 view .LVU280 + 1050 001e 7047 bx lr + 1051 .L71: + 1052 .align 2 + 1053 .L70: + 1054 0020 00E100E0 .word -536813312 + 1055 .cfi_endproc + 1056 .LFE142: + 1058 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits + 1059 .align 1 + 1060 .global HAL_NVIC_ClearPendingIRQ + 1061 .syntax unified + 1062 .thumb + 1063 .thumb_func + 1065 HAL_NVIC_ClearPendingIRQ: + ARM GAS /tmp/ccPJu8Ry.s page 79 + + + 1066 .LVL64: + 1067 .LFB143: + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt. + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1068 .loc 1 435 1 is_stmt 1 view -0 + 1069 .cfi_startproc + 1070 @ args = 0, pretend = 0, frame = 0 + 1071 @ frame_needed = 0, uses_anonymous_args = 0 + 1072 @ link register save eliminated. + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Clear pending interrupt */ + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); + 1073 .loc 1 437 3 view .LVU282 + 1074 .LBB56: + 1075 .LBI56: +1777:Drivers/CMSIS/Include/core_cm4.h **** { + 1076 .loc 2 1777 22 view .LVU283 + 1077 .LBB57: +1779:Drivers/CMSIS/Include/core_cm4.h **** { + 1078 .loc 2 1779 3 view .LVU284 +1779:Drivers/CMSIS/Include/core_cm4.h **** { + 1079 .loc 2 1779 6 is_stmt 0 view .LVU285 + 1080 0000 0028 cmp r0, #0 + 1081 .LVL65: +1779:Drivers/CMSIS/Include/core_cm4.h **** { + 1082 .loc 2 1779 6 view .LVU286 + 1083 0002 08DB blt .L72 +1781:Drivers/CMSIS/Include/core_cm4.h **** } + 1084 .loc 2 1781 5 is_stmt 1 view .LVU287 +1781:Drivers/CMSIS/Include/core_cm4.h **** } + 1085 .loc 2 1781 81 is_stmt 0 view .LVU288 + 1086 0004 00F01F02 and r2, r0, #31 +1781:Drivers/CMSIS/Include/core_cm4.h **** } + 1087 .loc 2 1781 34 view .LVU289 + 1088 0008 4009 lsrs r0, r0, #5 +1781:Drivers/CMSIS/Include/core_cm4.h **** } + 1089 .loc 2 1781 45 view .LVU290 + 1090 000a 0123 movs r3, #1 + 1091 000c 9340 lsls r3, r3, r2 +1781:Drivers/CMSIS/Include/core_cm4.h **** } + 1092 .loc 2 1781 43 view .LVU291 + 1093 000e 6030 adds r0, r0, #96 + 1094 0010 014A ldr r2, .L74 + 1095 0012 42F82030 str r3, [r2, r0, lsl #2] + 1096 .LVL66: + 1097 .L72: +1781:Drivers/CMSIS/Include/core_cm4.h **** } + 1098 .loc 2 1781 43 view .LVU292 + 1099 .LBE57: + 1100 .LBE56: + ARM GAS /tmp/ccPJu8Ry.s page 80 + + + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1101 .loc 1 438 1 view .LVU293 + 1102 0016 7047 bx lr + 1103 .L75: + 1104 .align 2 + 1105 .L74: + 1106 0018 00E100E0 .word -536813312 + 1107 .cfi_endproc + 1108 .LFE143: + 1110 .section .text.HAL_NVIC_GetActive,"ax",%progbits + 1111 .align 1 + 1112 .global HAL_NVIC_GetActive + 1113 .syntax unified + 1114 .thumb + 1115 .thumb_func + 1117 HAL_NVIC_GetActive: + 1118 .LVL67: + 1119 .LFB144: + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1120 .loc 1 449 1 is_stmt 1 view -0 + 1121 .cfi_startproc + 1122 @ args = 0, pretend = 0, frame = 0 + 1123 @ frame_needed = 0, uses_anonymous_args = 0 + 1124 @ link register save eliminated. + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Return 1 if active else 0U */ + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetActive(IRQn); + 1125 .loc 1 451 3 view .LVU295 + 1126 .LBB58: + 1127 .LBI58: +1794:Drivers/CMSIS/Include/core_cm4.h **** { + 1128 .loc 2 1794 26 view .LVU296 + 1129 .LBB59: +1796:Drivers/CMSIS/Include/core_cm4.h **** { + 1130 .loc 2 1796 3 view .LVU297 +1796:Drivers/CMSIS/Include/core_cm4.h **** { + 1131 .loc 2 1796 6 is_stmt 0 view .LVU298 + 1132 0000 0028 cmp r0, #0 + 1133 .LVL68: +1796:Drivers/CMSIS/Include/core_cm4.h **** { + 1134 .loc 2 1796 6 view .LVU299 + 1135 0002 0BDB blt .L78 +1798:Drivers/CMSIS/Include/core_cm4.h **** } + 1136 .loc 2 1798 5 is_stmt 1 view .LVU300 +1798:Drivers/CMSIS/Include/core_cm4.h **** } + 1137 .loc 2 1798 54 is_stmt 0 view .LVU301 + 1138 0004 4309 lsrs r3, r0, #5 +1798:Drivers/CMSIS/Include/core_cm4.h **** } + ARM GAS /tmp/ccPJu8Ry.s page 81 + + + 1139 .loc 2 1798 35 view .LVU302 + 1140 0006 8033 adds r3, r3, #128 + 1141 0008 054A ldr r2, .L79 + 1142 000a 52F82330 ldr r3, [r2, r3, lsl #2] +1798:Drivers/CMSIS/Include/core_cm4.h **** } + 1143 .loc 2 1798 91 view .LVU303 + 1144 000e 00F01F00 and r0, r0, #31 +1798:Drivers/CMSIS/Include/core_cm4.h **** } + 1145 .loc 2 1798 103 view .LVU304 + 1146 0012 23FA00F0 lsr r0, r3, r0 +1798:Drivers/CMSIS/Include/core_cm4.h **** } + 1147 .loc 2 1798 12 view .LVU305 + 1148 0016 00F00100 and r0, r0, #1 + 1149 001a 7047 bx lr + 1150 .L78: +1802:Drivers/CMSIS/Include/core_cm4.h **** } + 1151 .loc 2 1802 11 view .LVU306 + 1152 001c 0020 movs r0, #0 + 1153 .LVL69: +1802:Drivers/CMSIS/Include/core_cm4.h **** } + 1154 .loc 2 1802 11 view .LVU307 + 1155 .LBE59: + 1156 .LBE58: + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1157 .loc 1 452 1 view .LVU308 + 1158 001e 7047 bx lr + 1159 .L80: + 1160 .align 2 + 1161 .L79: + 1162 0020 00E100E0 .word -536813312 + 1163 .cfi_endproc + 1164 .LFE144: + 1166 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits + 1167 .align 1 + 1168 .global HAL_SYSTICK_CLKSourceConfig + 1169 .syntax unified + 1170 .thumb + 1171 .thumb_func + 1173 HAL_SYSTICK_CLKSourceConfig: + 1174 .LVL70: + 1175 .LFB145: + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Configures the SysTick clock source. + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source. + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values: + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1176 .loc 1 463 1 is_stmt 1 view -0 + 1177 .cfi_startproc + 1178 @ args = 0, pretend = 0, frame = 0 + 1179 @ frame_needed = 0, uses_anonymous_args = 0 + 1180 @ link register save eliminated. + ARM GAS /tmp/ccPJu8Ry.s page 82 + + + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + 1181 .loc 1 465 3 view .LVU310 + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + 1182 .loc 1 466 3 view .LVU311 + 1183 .loc 1 466 6 is_stmt 0 view .LVU312 + 1184 0000 0428 cmp r0, #4 + 1185 0002 06D0 beq .L84 + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** else + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + 1186 .loc 1 472 5 is_stmt 1 view .LVU313 + 1187 .loc 1 472 12 is_stmt 0 view .LVU314 + 1188 0004 4FF0E022 mov r2, #-536813568 + 1189 0008 1369 ldr r3, [r2, #16] + 1190 .loc 1 472 19 view .LVU315 + 1191 000a 23F00403 bic r3, r3, #4 + 1192 000e 1361 str r3, [r2, #16] + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1193 .loc 1 474 1 view .LVU316 + 1194 0010 7047 bx lr + 1195 .L84: + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1196 .loc 1 468 5 is_stmt 1 view .LVU317 + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1197 .loc 1 468 12 is_stmt 0 view .LVU318 + 1198 0012 4FF0E022 mov r2, #-536813568 + 1199 0016 1369 ldr r3, [r2, #16] + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1200 .loc 1 468 19 view .LVU319 + 1201 0018 43F00403 orr r3, r3, #4 + 1202 001c 1361 str r3, [r2, #16] + 1203 001e 7047 bx lr + 1204 .cfi_endproc + 1205 .LFE145: + 1207 .section .text.HAL_SYSTICK_Callback,"ax",%progbits + 1208 .align 1 + 1209 .weak HAL_SYSTICK_Callback + 1210 .syntax unified + 1211 .thumb + 1212 .thumb_func + 1214 HAL_SYSTICK_Callback: + 1215 .LFB147: + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request. + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + ARM GAS /tmp/ccPJu8Ry.s page 83 + + + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief SYSTICK callback. + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1216 .loc 1 490 1 is_stmt 1 view -0 + 1217 .cfi_startproc + 1218 @ args = 0, pretend = 0, frame = 0 + 1219 @ frame_needed = 0, uses_anonymous_args = 0 + 1220 @ link register save eliminated. + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1221 .loc 1 494 1 view .LVU321 + 1222 0000 7047 bx lr + 1223 .cfi_endproc + 1224 .LFE147: + 1226 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits + 1227 .align 1 + 1228 .global HAL_SYSTICK_IRQHandler + 1229 .syntax unified + 1230 .thumb + 1231 .thumb_func + 1233 HAL_SYSTICK_IRQHandler: + 1234 .LFB146: + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 1235 .loc 1 481 1 view -0 + 1236 .cfi_startproc + 1237 @ args = 0, pretend = 0, frame = 0 + 1238 @ frame_needed = 0, uses_anonymous_args = 0 + 1239 0000 08B5 push {r3, lr} + 1240 .cfi_def_cfa_offset 8 + 1241 .cfi_offset 3, -8 + 1242 .cfi_offset 14, -4 + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1243 .loc 1 482 3 view .LVU323 + 1244 0002 FFF7FEFF bl HAL_SYSTICK_Callback + 1245 .LVL71: + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 1246 .loc 1 483 1 is_stmt 0 view .LVU324 + 1247 0006 08BD pop {r3, pc} + 1248 .cfi_endproc + 1249 .LFE146: + 1251 .text + 1252 .Letext0: + 1253 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1254 .file 5 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1255 .file 6 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1256 .file 7 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1257 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h" + ARM GAS /tmp/ccPJu8Ry.s page 84 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_cortex.c + /tmp/ccPJu8Ry.s:21 .text.__NVIC_DisableIRQ:0000000000000000 $t + /tmp/ccPJu8Ry.s:26 .text.__NVIC_DisableIRQ:0000000000000000 __NVIC_DisableIRQ + /tmp/ccPJu8Ry.s:88 .text.__NVIC_DisableIRQ:0000000000000020 $d + /tmp/ccPJu8Ry.s:93 .text.__NVIC_SetPriority:0000000000000000 $t + /tmp/ccPJu8Ry.s:98 .text.__NVIC_SetPriority:0000000000000000 __NVIC_SetPriority + /tmp/ccPJu8Ry.s:141 .text.__NVIC_SetPriority:0000000000000024 $d + /tmp/ccPJu8Ry.s:146 .text.__NVIC_GetPriority:0000000000000000 $t + /tmp/ccPJu8Ry.s:151 .text.__NVIC_GetPriority:0000000000000000 __NVIC_GetPriority + /tmp/ccPJu8Ry.s:187 .text.__NVIC_GetPriority:0000000000000020 $d + /tmp/ccPJu8Ry.s:192 .text.NVIC_EncodePriority:0000000000000000 $t + /tmp/ccPJu8Ry.s:197 .text.NVIC_EncodePriority:0000000000000000 NVIC_EncodePriority + /tmp/ccPJu8Ry.s:258 .text.NVIC_DecodePriority:0000000000000000 $t + /tmp/ccPJu8Ry.s:263 .text.NVIC_DecodePriority:0000000000000000 NVIC_DecodePriority + /tmp/ccPJu8Ry.s:331 .text.__NVIC_SystemReset:0000000000000000 $t + /tmp/ccPJu8Ry.s:336 .text.__NVIC_SystemReset:0000000000000000 __NVIC_SystemReset + /tmp/ccPJu8Ry.s:397 .text.__NVIC_SystemReset:000000000000001c $d + /tmp/ccPJu8Ry.s:403 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 $t + /tmp/ccPJu8Ry.s:409 .text.HAL_NVIC_SetPriorityGrouping:0000000000000000 HAL_NVIC_SetPriorityGrouping + /tmp/ccPJu8Ry.s:463 .text.HAL_NVIC_SetPriorityGrouping:0000000000000020 $d + /tmp/ccPJu8Ry.s:468 .text.HAL_NVIC_SetPriority:0000000000000000 $t + /tmp/ccPJu8Ry.s:474 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority + /tmp/ccPJu8Ry.s:520 .text.HAL_NVIC_SetPriority:000000000000001c $d + /tmp/ccPJu8Ry.s:525 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t + /tmp/ccPJu8Ry.s:531 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ + /tmp/ccPJu8Ry.s:572 .text.HAL_NVIC_EnableIRQ:0000000000000018 $d + /tmp/ccPJu8Ry.s:577 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t + /tmp/ccPJu8Ry.s:583 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ + /tmp/ccPJu8Ry.s:605 .text.HAL_NVIC_SystemReset:0000000000000000 $t + /tmp/ccPJu8Ry.s:611 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset + /tmp/ccPJu8Ry.s:629 .text.HAL_SYSTICK_Config:0000000000000000 $t + /tmp/ccPJu8Ry.s:635 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config + /tmp/ccPJu8Ry.s:700 .text.HAL_SYSTICK_Config:0000000000000024 $d + /tmp/ccPJu8Ry.s:705 .text.HAL_MPU_Disable:0000000000000000 $t + /tmp/ccPJu8Ry.s:711 .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable + /tmp/ccPJu8Ry.s:734 .text.HAL_MPU_Disable:0000000000000014 $d + /tmp/ccPJu8Ry.s:739 .text.HAL_MPU_Enable:0000000000000000 $t + /tmp/ccPJu8Ry.s:745 .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable + /tmp/ccPJu8Ry.s:771 .text.HAL_MPU_Enable:0000000000000014 $d + /tmp/ccPJu8Ry.s:776 .text.HAL_MPU_ConfigRegion:0000000000000000 $t + /tmp/ccPJu8Ry.s:782 .text.HAL_MPU_ConfigRegion:0000000000000000 HAL_MPU_ConfigRegion + /tmp/ccPJu8Ry.s:871 .text.HAL_MPU_ConfigRegion:000000000000005c $d + /tmp/ccPJu8Ry.s:876 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 $t + /tmp/ccPJu8Ry.s:882 .text.HAL_NVIC_GetPriorityGrouping:0000000000000000 HAL_NVIC_GetPriorityGrouping + /tmp/ccPJu8Ry.s:906 .text.HAL_NVIC_GetPriorityGrouping:000000000000000c $d + /tmp/ccPJu8Ry.s:911 .text.HAL_NVIC_GetPriority:0000000000000000 $t + /tmp/ccPJu8Ry.s:917 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority + /tmp/ccPJu8Ry.s:951 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t + /tmp/ccPJu8Ry.s:957 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ + /tmp/ccPJu8Ry.s:998 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d + /tmp/ccPJu8Ry.s:1003 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t + /tmp/ccPJu8Ry.s:1009 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ + /tmp/ccPJu8Ry.s:1054 .text.HAL_NVIC_GetPendingIRQ:0000000000000020 $d + /tmp/ccPJu8Ry.s:1059 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t + /tmp/ccPJu8Ry.s:1065 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ + /tmp/ccPJu8Ry.s:1106 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d + ARM GAS /tmp/ccPJu8Ry.s page 85 + + + /tmp/ccPJu8Ry.s:1111 .text.HAL_NVIC_GetActive:0000000000000000 $t + /tmp/ccPJu8Ry.s:1117 .text.HAL_NVIC_GetActive:0000000000000000 HAL_NVIC_GetActive + /tmp/ccPJu8Ry.s:1162 .text.HAL_NVIC_GetActive:0000000000000020 $d + /tmp/ccPJu8Ry.s:1167 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t + /tmp/ccPJu8Ry.s:1173 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig + /tmp/ccPJu8Ry.s:1208 .text.HAL_SYSTICK_Callback:0000000000000000 $t + /tmp/ccPJu8Ry.s:1214 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback + /tmp/ccPJu8Ry.s:1227 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t + /tmp/ccPJu8Ry.s:1233 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler + +NO UNDEFINED SYMBOLS diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_cortex.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_cortex.o new file mode 100644 index 0000000000000000000000000000000000000000..7327a9de4afe8bc5e5b0914cf7fc2b2931294071 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z`hFSE_s5C&Q)26ydpDr(+STs!3H8mz>FJvk(D!NlsC28R4Cv{b2syu>*JIsx9QoA8@#*QC z7tmLO8xQv~|Io{-2; zu0`a$tfwLO1T*AdJ9soh&fnfAVBZ1AvArmgYOnbND()jCi>bpf)PK+PR1?u9spDzL q4Pc_I28Yjcte5i$>qOP5qZaG;B40sI-^762`n5{&FYkGWC-*;uDxEa| literal 0 HcmV?d00001 diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_dma.d b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_dma.d new file mode 100644 index 0000000..34cb86c --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_dma.d @@ -0,0 +1,58 @@ +build/stm32f3xx_hal_dma.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_dma.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_dma.lst new file mode 100644 index 0000000..e627a51 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_dma.lst @@ -0,0 +1,3047 @@ +ARM GAS /tmp/ccaRdTju.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_dma.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c" + 20 .section .text.DMA_SetConfig,"ax",%progbits + 21 .align 1 + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 DMA_SetConfig: + 27 .LVL0: + 28 .LFB142: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @file stm32f3xx_hal_dma.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief DMA HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * This file provides firmware functions to manage the following + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * functionalities of the Direct Memory Access (DMA) peripheral: + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + Initialization and de-initialization functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + IO operation functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + Peripheral State and errors functions + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @verbatim + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ============================================================================== + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### How to use this driver ##### + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ============================================================================== + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) Enable and configure the peripheral to be connected to the DMA Channel + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (except for internal SRAM / FLASH memories: no initialization is + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** necessary). Please refer to Reference manual for connection between peripherals + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** and DMA requests . + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) For a given Channel, program the required configuration through the following parameters: + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Transfer Direction, Source and Destination data formats, + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** using HAL_DMA_Init() function. + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of er + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** detection. + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) Use HAL_DMA_Abort() function to abort the current transfer + ARM GAS /tmp/ccaRdTju.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** *** Polling mode IO operation *** + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ================================= + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** address and destination address and the Length of data to be transferred + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case a fixed Timeout can be configured by User depending from his application. + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** *** Interrupt mode IO operation *** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =================================== + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Source address and destination address and the Length of data to be transferred. + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** In this case the DMA interrupt is configured + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** add his own function by customization of function pointer XferCpltCallback and + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** XferErrorCallback (i.e a member of DMA handle structure). + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** *** DMA HAL driver macros list *** + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ============================================= + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Below the list of most used macros in DMA HAL driver. + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (@) You can refer to the DMA HAL driver header file for more useful macros + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @endverbatim + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ****************************************************************************** + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @attention + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * All rights reserved.

    + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * This software component is licensed by ST under BSD 3-Clause license, + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the "License"; You may not use this file except in compliance with the + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * License. You may obtain a copy of the License at: + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * opensource.org/licenses/BSD-3-Clause + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ****************************************************************************** + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Includes ------------------------------------------------------------------*/ + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #include "stm32f3xx_hal.h" + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @addtogroup STM32F3xx_HAL_Driver + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA DMA + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief DMA HAL module driver + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + ARM GAS /tmp/ccaRdTju.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #ifdef HAL_DMA_MODULE_ENABLED + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private typedef -----------------------------------------------------------*/ + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private define ------------------------------------------------------------*/ + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private macro -------------------------------------------------------------*/ + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private variables ---------------------------------------------------------*/ + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private function prototypes -----------------------------------------------*/ + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Private_Functions DMA Private Functions + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Exported functions ---------------------------------------------------------*/ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions DMA Exported Functions + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Initialization and de-initialization functions + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @verbatim + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### Initialization and de-initialization functions ##### + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** This section provides functions allowing to initialize the DMA Channel source + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** and destination addresses, incrementation and data sizes, transfer direction, + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** The HAL_DMA_Init() function follows the DMA configuration procedures as described in + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** reference manual. + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @endverbatim + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Initialize the DMA according to the specified + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * parameters in the DMA_InitTypeDef and initialize the associated handle. + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t tmp = 0U; + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the DMA handle allocation */ + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(NULL == hdma) + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + ARM GAS /tmp/ccaRdTju.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the parameters */ + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change DMA peripheral state */ + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get the CR register value */ + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** tmp = hdma->Instance->CCR; + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CCR_DIR)); + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Prepare the DMA Channel configuration */ + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** tmp |= hdma->Init.Direction | + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Write to DMA Channel CR register */ + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR = tmp; + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Initialize DmaBaseAddress and ChannelIndex parameters used + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CalcBaseAndBitshift(hdma); + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Initialise the error code */ + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Initialize the DMA state*/ + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Allocate lock resource and initialize it */ + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Lock = HAL_UNLOCKED; + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_OK; + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief DeInitialize the DMA peripheral + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the DMA handle allocation */ + ARM GAS /tmp/ccaRdTju.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(NULL == hdma) + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the parameters */ + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the selected DMA Channelx */ + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset DMA Channel control register */ + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR = 0U; + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset DMA Channel Number of Data to Transfer register */ + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CNDTR = 0U; + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset DMA Channel peripheral address register */ + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CPAR = 0U; + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset DMA Channel memory address register */ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CMAR = 0U; + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get DMA Base Address */ + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CalcBaseAndBitshift(hdma); + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clean callbacks */ + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset the error code */ + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset the DMA state */ + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_RESET; + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Release Lock */ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_OK; + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief I/O operation functions + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @verbatim + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### IO operation functions ##### + ARM GAS /tmp/ccaRdTju.s page 6 + + + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] This section provides functions allowing to: + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Configure the source, destination address and data length and Start DMA transfer + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Configure the source, destination address and data length and + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Start DMA transfer with interrupt + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Abort DMA transfer + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Poll for transfer complete + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Handle DMA interrupt request + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @endverbatim + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Start the DMA Transfer. + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the parameters */ + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */ + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_LOCK(hdma); + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change DMA peripheral state */ + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the peripheral */ + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Enable the Peripheral */ + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR |= DMA_CCR_EN; + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Remain BUSY */ + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_BUSY; + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + ARM GAS /tmp/ccaRdTju.s page 7 + + + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Start the DMA Transfer with interrupt enabled. + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the parameters */ + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */ + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_LOCK(hdma); + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change DMA peripheral state */ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the peripheral */ + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Enable the transfer complete, & transfer error interrupts */ + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Half transfer interrupt is optional: enable it only if associated callback is available */ + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(NULL != hdma->XferHalfCpltCallback ) + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_IT_HT; + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Enable the Peripheral */ + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR |= DMA_CCR_EN; + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Remain BUSY */ + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_BUSY; + ARM GAS /tmp/ccaRdTju.s page 8 + + + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Abort the DMA Transfer. + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* no transfer ongoing */ + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable DMA IT */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the channel */ + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state*/ + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_OK; + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Abort the DMA Transfer in Interrupt mode. + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_BUSY != hdma->State) + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* no transfer ongoing */ + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + ARM GAS /tmp/ccaRdTju.s page 9 + + + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable DMA IT */ + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the channel */ + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Call User Abort callback */ + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->XferAbortCallback != NULL) + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback(hdma); + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Polling for transfer complete. + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param CompleteLevel Specifies the DMA level complete. + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param Timeout Timeout duration. + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t temp; + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t tickstart = 0U; + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_BUSY != hdma->State) + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* no transfer ongoing */ + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Polling mode not supported in circular mode */ + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + ARM GAS /tmp/ccaRdTju.s page 10 + + + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get the level transfer complete flag */ + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer Complete flag */ + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** temp = DMA_FLAG_TC1 << hdma->ChannelIndex; + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Half Transfer Complete flag */ + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** temp = DMA_FLAG_HT1 << hdma->ChannelIndex; + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get tick */ + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** tickstart = HAL_GetTick(); + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* When a DMA transfer error occurs */ + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Update error code */ + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State= HAL_DMA_STATE_READY; + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check for the Timeout */ + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(Timeout != HAL_MAX_DELAY) + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Update error code */ + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + ARM GAS /tmp/ccaRdTju.s page 11 + + + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the transfer complete flag */ + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* The selected Channelx EN bit is cleared (DMA is disabled and + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** all transfers are complete) */ + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process unlocked */ + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_OK; + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Handle DMA interrupt request. + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval None + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t flag_it = hdma->DmaBaseAddress->ISR; + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t source_it = hdma->Instance->CCR; + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Half Transfer Complete Interrupt management ******************************/ + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_ + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the half transfer interrupt */ + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_IT_HT; + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* DMA peripheral state is not updated in Half Transfer */ + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* State is updated only in Transfer Complete case */ + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Half transfer callback */ + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer Complete Interrupt management ***********************************/ + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DM + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + ARM GAS /tmp/ccaRdTju.s page 12 + + + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the transfer complete & transfer error interrupts */ + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* if the DMA mode is not CIRCULAR */ + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the transfer complete flag */ + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer complete callback */ + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback(hdma); + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer Error Interrupt management ***************************************/ + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & D + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* When a DMA transfer error occurs */ + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Then, disable all DMA interrupts */ + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Update error code */ + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->XferErrorCallback != NULL) + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer error callback */ + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback(hdma); + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Register callbacks + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param CallbackID User Callback identifer + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param pCallback pointer to private callback function which has pointer to + ARM GAS /tmp/ccaRdTju.s page 13 + + + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * a DMA_HandleTypeDef structure as parameter. + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */ + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_LOCK(hdma); + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** switch (CallbackID) + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback = pCallback; + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = pCallback; + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = pCallback; + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = pCallback; + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** default: + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Release Lock */ + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief UnRegister callbacks + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param CallbackID User Callback identifer + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + ARM GAS /tmp/ccaRdTju.s page 14 + + + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */ + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_LOCK(hdma); + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** switch (CallbackID) + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ALL_CB_ID: + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** default: + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Release Lock */ + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Peripheral State functions + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @verbatim + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### State and Errors functions ##### + ARM GAS /tmp/ccaRdTju.s page 15 + + + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** This subsection provides functions allowing to + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Check the DMA state + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Get error code + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @endverbatim + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Returns the DMA state. + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL state + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return hdma->State; + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Return the DMA error code + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval DMA Error Code + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return hdma->ErrorCode; + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Set the DMA Transfer parameters. + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 29 .loc 1 826 1 view -0 + 30 .cfi_startproc + ARM GAS /tmp/ccaRdTju.s page 16 + + + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 .loc 1 826 1 is_stmt 0 view .LVU1 + 35 0000 30B4 push {r4, r5} + 36 .cfi_def_cfa_offset 8 + 37 .cfi_offset 4, -8 + 38 .cfi_offset 5, -4 + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + 39 .loc 1 828 3 is_stmt 1 view .LVU2 + 40 .loc 1 828 47 is_stmt 0 view .LVU3 + 41 0002 0124 movs r4, #1 + 42 0004 056C ldr r5, [r0, #64] + 43 0006 AC40 lsls r4, r4, r5 + 44 .loc 1 828 31 view .LVU4 + 45 0008 C56B ldr r5, [r0, #60] + 46 000a 6C60 str r4, [r5, #4] + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel data length */ + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CNDTR = DataLength; + 47 .loc 1 831 3 is_stmt 1 view .LVU5 + 48 .loc 1 831 7 is_stmt 0 view .LVU6 + 49 000c 0468 ldr r4, [r0] + 50 .loc 1 831 25 view .LVU7 + 51 000e 6360 str r3, [r4, #4] + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Peripheral to Memory */ + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 52 .loc 1 834 3 is_stmt 1 view .LVU8 + 53 .loc 1 834 17 is_stmt 0 view .LVU9 + 54 0010 4368 ldr r3, [r0, #4] + 55 .LVL1: + 56 .loc 1 834 5 view .LVU10 + 57 0012 102B cmp r3, #16 + 58 0014 05D0 beq .L5 + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel destination address */ + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CPAR = DstAddress; + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel source address */ + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CMAR = SrcAddress; + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Memory to Peripheral */ + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel source address */ + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CPAR = SrcAddress; + 59 .loc 1 846 5 is_stmt 1 view .LVU11 + 60 .loc 1 846 9 is_stmt 0 view .LVU12 + 61 0016 0368 ldr r3, [r0] + 62 .loc 1 846 26 view .LVU13 + 63 0018 9960 str r1, [r3, #8] + 64 .LVL2: + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel destination address */ + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CMAR = DstAddress; + ARM GAS /tmp/ccaRdTju.s page 17 + + + 65 .loc 1 849 5 is_stmt 1 view .LVU14 + 66 .loc 1 849 9 is_stmt 0 view .LVU15 + 67 001a 0368 ldr r3, [r0] + 68 .loc 1 849 26 view .LVU16 + 69 001c DA60 str r2, [r3, #12] + 70 .L1: + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 71 .loc 1 851 1 view .LVU17 + 72 001e 30BC pop {r4, r5} + 73 .cfi_remember_state + 74 .cfi_restore 5 + 75 .cfi_restore 4 + 76 .cfi_def_cfa_offset 0 + 77 0020 7047 bx lr + 78 .LVL3: + 79 .L5: + 80 .cfi_restore_state + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 81 .loc 1 837 5 is_stmt 1 view .LVU18 + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 82 .loc 1 837 9 is_stmt 0 view .LVU19 + 83 0022 0368 ldr r3, [r0] + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 84 .loc 1 837 26 view .LVU20 + 85 0024 9A60 str r2, [r3, #8] + 86 .LVL4: + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 87 .loc 1 840 5 is_stmt 1 view .LVU21 + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 88 .loc 1 840 9 is_stmt 0 view .LVU22 + 89 0026 0368 ldr r3, [r0] + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 90 .loc 1 840 26 view .LVU23 + 91 0028 D960 str r1, [r3, #12] + 92 002a F8E7 b .L1 + 93 .cfi_endproc + 94 .LFE142: + 96 .section .text.DMA_CalcBaseAndBitshift,"ax",%progbits + 97 .align 1 + 98 .syntax unified + 99 .thumb + 100 .thumb_func + 102 DMA_CalcBaseAndBitshift: + 103 .LVL5: + 104 .LFB143: + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Set the DMA base address and channel index depending on DMA instance + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval None + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 105 .loc 1 860 1 is_stmt 1 view -0 + 106 .cfi_startproc + ARM GAS /tmp/ccaRdTju.s page 18 + + + 107 @ args = 0, pretend = 0, frame = 0 + 108 @ frame_needed = 0, uses_anonymous_args = 0 + 109 @ link register save eliminated. + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #if defined (DMA2) + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* calculation of the channel index */ + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 110 .loc 1 863 3 view .LVU25 + 111 .loc 1 863 22 is_stmt 0 view .LVU26 + 112 0000 0268 ldr r2, [r0] + 113 .loc 1 863 6 view .LVU27 + 114 0002 0C4B ldr r3, .L9 + 115 0004 9A42 cmp r2, r3 + 116 0006 0AD8 bhi .L7 + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* DMA1 */ + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Ch + 117 .loc 1 866 5 is_stmt 1 view .LVU28 + 118 .loc 1 866 53 is_stmt 0 view .LVU29 + 119 0008 0B4B ldr r3, .L9+4 + 120 000a 1344 add r3, r3, r2 + 121 .loc 1 866 80 view .LVU30 + 122 000c 0B4A ldr r2, .L9+8 + 123 000e A2FB0323 umull r2, r3, r2, r3 + 124 0012 1B09 lsrs r3, r3, #4 + 125 .loc 1 866 135 view .LVU31 + 126 0014 9B00 lsls r3, r3, #2 + 127 .loc 1 866 24 view .LVU32 + 128 0016 0364 str r3, [r0, #64] + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA1; + 129 .loc 1 867 5 is_stmt 1 view .LVU33 + 130 .loc 1 867 26 is_stmt 0 view .LVU34 + 131 0018 094B ldr r3, .L9+12 + 132 001a C363 str r3, [r0, #60] + 133 001c 7047 bx lr + 134 .L7: + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* DMA2 */ + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Ch + 135 .loc 1 872 5 is_stmt 1 view .LVU35 + 136 .loc 1 872 53 is_stmt 0 view .LVU36 + 137 001e 094B ldr r3, .L9+16 + 138 0020 1344 add r3, r3, r2 + 139 .loc 1 872 80 view .LVU37 + 140 0022 064A ldr r2, .L9+8 + 141 0024 A2FB0323 umull r2, r3, r2, r3 + 142 0028 1B09 lsrs r3, r3, #4 + 143 .loc 1 872 135 view .LVU38 + 144 002a 9B00 lsls r3, r3, #2 + 145 .loc 1 872 24 view .LVU39 + 146 002c 0364 str r3, [r0, #64] + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 147 .loc 1 873 5 is_stmt 1 view .LVU40 + 148 .loc 1 873 26 is_stmt 0 view .LVU41 + 149 002e 064B ldr r3, .L9+20 + 150 0030 C363 str r3, [r0, #60] + ARM GAS /tmp/ccaRdTju.s page 19 + + + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #else + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* calculation of the channel index */ + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* DMA1 */ + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Chan + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA1; + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #endif + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 151 .loc 1 881 1 view .LVU42 + 152 0032 7047 bx lr + 153 .L10: + 154 .align 2 + 155 .L9: + 156 0034 07040240 .word 1073873927 + 157 0038 F8FFFDBF .word -1073872904 + 158 003c CDCCCCCC .word -858993459 + 159 0040 00000240 .word 1073872896 + 160 0044 F8FBFDBF .word -1073873928 + 161 0048 00040240 .word 1073873920 + 162 .cfi_endproc + 163 .LFE143: + 165 .section .text.HAL_DMA_Init,"ax",%progbits + 166 .align 1 + 167 .global HAL_DMA_Init + 168 .syntax unified + 169 .thumb + 170 .thumb_func + 172 HAL_DMA_Init: + 173 .LVL6: + 174 .LFB130: + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t tmp = 0U; + 175 .loc 1 138 1 is_stmt 1 view -0 + 176 .cfi_startproc + 177 @ args = 0, pretend = 0, frame = 0 + 178 @ frame_needed = 0, uses_anonymous_args = 0 + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 179 .loc 1 139 3 view .LVU44 + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 180 .loc 1 142 3 view .LVU45 + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 181 .loc 1 142 5 is_stmt 0 view .LVU46 + 182 0000 20B3 cbz r0, .L13 + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t tmp = 0U; + 183 .loc 1 138 1 view .LVU47 + 184 0002 10B5 push {r4, lr} + 185 .cfi_def_cfa_offset 8 + 186 .cfi_offset 4, -8 + 187 .cfi_offset 14, -4 + 188 0004 0446 mov r4, r0 + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 189 .loc 1 148 3 is_stmt 1 view .LVU48 + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 190 .loc 1 149 3 view .LVU49 + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 191 .loc 1 150 3 view .LVU50 + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 192 .loc 1 151 3 view .LVU51 + ARM GAS /tmp/ccaRdTju.s page 20 + + + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 193 .loc 1 152 3 view .LVU52 + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 194 .loc 1 153 3 view .LVU53 + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 195 .loc 1 154 3 view .LVU54 + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 196 .loc 1 155 3 view .LVU55 + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 197 .loc 1 158 3 view .LVU56 + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 198 .loc 1 158 15 is_stmt 0 view .LVU57 + 199 0006 0223 movs r3, #2 + 200 0008 80F82130 strb r3, [r0, #33] + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 201 .loc 1 161 3 is_stmt 1 view .LVU58 + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 202 .loc 1 161 13 is_stmt 0 view .LVU59 + 203 000c 0168 ldr r1, [r0] + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 204 .loc 1 161 7 view .LVU60 + 205 000e 0A68 ldr r2, [r1] + 206 .LVL7: + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + 207 .loc 1 164 3 is_stmt 1 view .LVU61 + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + 208 .loc 1 164 7 is_stmt 0 view .LVU62 + 209 0010 22F47F52 bic r2, r2, #16320 + 210 .LVL8: + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + 211 .loc 1 164 7 view .LVU63 + 212 0014 22F03002 bic r2, r2, #48 + 213 .LVL9: + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 214 .loc 1 169 3 is_stmt 1 view .LVU64 + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 215 .loc 1 169 21 is_stmt 0 view .LVU65 + 216 0018 4368 ldr r3, [r0, #4] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 217 .loc 1 170 21 view .LVU66 + 218 001a 8068 ldr r0, [r0, #8] + 219 .LVL10: + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 220 .loc 1 169 39 view .LVU67 + 221 001c 0343 orrs r3, r3, r0 + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 222 .loc 1 170 54 view .LVU68 + 223 001e E068 ldr r0, [r4, #12] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 224 .loc 1 170 42 view .LVU69 + 225 0020 0343 orrs r3, r3, r0 + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 226 .loc 1 171 21 view .LVU70 + 227 0022 2069 ldr r0, [r4, #16] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 228 .loc 1 170 72 view .LVU71 + 229 0024 0343 orrs r3, r3, r0 + ARM GAS /tmp/ccaRdTju.s page 21 + + + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 230 .loc 1 171 54 view .LVU72 + 231 0026 6069 ldr r0, [r4, #20] + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 232 .loc 1 171 42 view .LVU73 + 233 0028 0343 orrs r3, r3, r0 + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 234 .loc 1 172 21 view .LVU74 + 235 002a A069 ldr r0, [r4, #24] + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 236 .loc 1 171 72 view .LVU75 + 237 002c 0343 orrs r3, r3, r0 + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 238 .loc 1 172 54 view .LVU76 + 239 002e E069 ldr r0, [r4, #28] + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 240 .loc 1 172 42 view .LVU77 + 241 0030 0343 orrs r3, r3, r0 + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 242 .loc 1 169 7 view .LVU78 + 243 0032 1343 orrs r3, r3, r2 + 244 .LVL11: + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 245 .loc 1 175 3 is_stmt 1 view .LVU79 + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 246 .loc 1 175 23 is_stmt 0 view .LVU80 + 247 0034 0B60 str r3, [r1] + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 248 .loc 1 179 3 is_stmt 1 view .LVU81 + 249 0036 2046 mov r0, r4 + 250 0038 FFF7FEFF bl DMA_CalcBaseAndBitshift + 251 .LVL12: + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 252 .loc 1 182 3 view .LVU82 + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 253 .loc 1 182 19 is_stmt 0 view .LVU83 + 254 003c 0020 movs r0, #0 + 255 003e A063 str r0, [r4, #56] + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 256 .loc 1 185 3 is_stmt 1 view .LVU84 + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 257 .loc 1 185 15 is_stmt 0 view .LVU85 + 258 0040 0123 movs r3, #1 + 259 0042 84F82130 strb r3, [r4, #33] + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 260 .loc 1 188 3 is_stmt 1 view .LVU86 + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 261 .loc 1 188 14 is_stmt 0 view .LVU87 + 262 0046 84F82000 strb r0, [r4, #32] + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 263 .loc 1 190 3 is_stmt 1 view .LVU88 + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 264 .loc 1 191 1 is_stmt 0 view .LVU89 + 265 004a 10BD pop {r4, pc} + 266 .LVL13: + 267 .L13: + 268 .cfi_def_cfa_offset 0 + ARM GAS /tmp/ccaRdTju.s page 22 + + + 269 .cfi_restore 4 + 270 .cfi_restore 14 + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 271 .loc 1 144 12 view .LVU90 + 272 004c 0120 movs r0, #1 + 273 .LVL14: + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 274 .loc 1 191 1 view .LVU91 + 275 004e 7047 bx lr + 276 .cfi_endproc + 277 .LFE130: + 279 .section .text.HAL_DMA_DeInit,"ax",%progbits + 280 .align 1 + 281 .global HAL_DMA_DeInit + 282 .syntax unified + 283 .thumb + 284 .thumb_func + 286 HAL_DMA_DeInit: + 287 .LVL15: + 288 .LFB131: + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the DMA handle allocation */ + 289 .loc 1 200 1 is_stmt 1 view -0 + 290 .cfi_startproc + 291 @ args = 0, pretend = 0, frame = 0 + 292 @ frame_needed = 0, uses_anonymous_args = 0 + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 293 .loc 1 202 3 view .LVU93 + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 294 .loc 1 202 5 is_stmt 0 view .LVU94 + 295 0000 08B3 cbz r0, .L20 + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the DMA handle allocation */ + 296 .loc 1 200 1 view .LVU95 + 297 0002 38B5 push {r3, r4, r5, lr} + 298 .cfi_def_cfa_offset 16 + 299 .cfi_offset 3, -16 + 300 .cfi_offset 4, -12 + 301 .cfi_offset 5, -8 + 302 .cfi_offset 14, -4 + 303 0004 0446 mov r4, r0 + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 304 .loc 1 208 3 is_stmt 1 view .LVU96 + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 305 .loc 1 211 3 view .LVU97 + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 306 .loc 1 211 7 is_stmt 0 view .LVU98 + 307 0006 0268 ldr r2, [r0] + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 308 .loc 1 211 17 view .LVU99 + 309 0008 1368 ldr r3, [r2] + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 310 .loc 1 211 23 view .LVU100 + 311 000a 23F00103 bic r3, r3, #1 + 312 000e 1360 str r3, [r2] + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 313 .loc 1 214 3 is_stmt 1 view .LVU101 + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 314 .loc 1 214 7 is_stmt 0 view .LVU102 + ARM GAS /tmp/ccaRdTju.s page 23 + + + 315 0010 0368 ldr r3, [r0] + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 316 .loc 1 214 24 view .LVU103 + 317 0012 0025 movs r5, #0 + 318 0014 1D60 str r5, [r3] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 319 .loc 1 217 3 is_stmt 1 view .LVU104 + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 320 .loc 1 217 7 is_stmt 0 view .LVU105 + 321 0016 0368 ldr r3, [r0] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 322 .loc 1 217 25 view .LVU106 + 323 0018 5D60 str r5, [r3, #4] + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 324 .loc 1 220 3 is_stmt 1 view .LVU107 + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 325 .loc 1 220 7 is_stmt 0 view .LVU108 + 326 001a 0368 ldr r3, [r0] + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 327 .loc 1 220 25 view .LVU109 + 328 001c 9D60 str r5, [r3, #8] + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 329 .loc 1 223 3 is_stmt 1 view .LVU110 + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 330 .loc 1 223 7 is_stmt 0 view .LVU111 + 331 001e 0368 ldr r3, [r0] + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 332 .loc 1 223 24 view .LVU112 + 333 0020 DD60 str r5, [r3, #12] + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 334 .loc 1 226 3 is_stmt 1 view .LVU113 + 335 0022 FFF7FEFF bl DMA_CalcBaseAndBitshift + 336 .LVL16: + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 337 .loc 1 229 3 view .LVU114 + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 338 .loc 1 229 52 is_stmt 0 view .LVU115 + 339 0026 216C ldr r1, [r4, #64] + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 340 .loc 1 229 7 view .LVU116 + 341 0028 E26B ldr r2, [r4, #60] + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 342 .loc 1 229 45 view .LVU117 + 343 002a 0123 movs r3, #1 + 344 002c 8B40 lsls r3, r3, r1 + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 345 .loc 1 229 30 view .LVU118 + 346 002e 5360 str r3, [r2, #4] + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 347 .loc 1 232 3 is_stmt 1 view .LVU119 + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 348 .loc 1 232 26 is_stmt 0 view .LVU120 + 349 0030 A562 str r5, [r4, #40] + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 350 .loc 1 233 3 is_stmt 1 view .LVU121 + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 351 .loc 1 233 30 is_stmt 0 view .LVU122 + ARM GAS /tmp/ccaRdTju.s page 24 + + + 352 0032 E562 str r5, [r4, #44] + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 353 .loc 1 234 3 is_stmt 1 view .LVU123 + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 354 .loc 1 234 27 is_stmt 0 view .LVU124 + 355 0034 2563 str r5, [r4, #48] + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 356 .loc 1 235 3 is_stmt 1 view .LVU125 + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 357 .loc 1 235 27 is_stmt 0 view .LVU126 + 358 0036 6563 str r5, [r4, #52] + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 359 .loc 1 238 3 is_stmt 1 view .LVU127 + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 360 .loc 1 238 19 is_stmt 0 view .LVU128 + 361 0038 A563 str r5, [r4, #56] + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 362 .loc 1 241 3 is_stmt 1 view .LVU129 + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 363 .loc 1 241 15 is_stmt 0 view .LVU130 + 364 003a 84F82150 strb r5, [r4, #33] + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 365 .loc 1 244 3 is_stmt 1 view .LVU131 + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 366 .loc 1 244 3 view .LVU132 + 367 003e 84F82050 strb r5, [r4, #32] + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 368 .loc 1 244 3 view .LVU133 + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 369 .loc 1 246 3 view .LVU134 + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 370 .loc 1 246 10 is_stmt 0 view .LVU135 + 371 0042 2846 mov r0, r5 + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 372 .loc 1 247 1 view .LVU136 + 373 0044 38BD pop {r3, r4, r5, pc} + 374 .LVL17: + 375 .L20: + 376 .cfi_def_cfa_offset 0 + 377 .cfi_restore 3 + 378 .cfi_restore 4 + 379 .cfi_restore 5 + 380 .cfi_restore 14 + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 381 .loc 1 204 12 view .LVU137 + 382 0046 0120 movs r0, #1 + 383 .LVL18: + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 384 .loc 1 247 1 view .LVU138 + 385 0048 7047 bx lr + 386 .cfi_endproc + 387 .LFE131: + 389 .section .text.HAL_DMA_Start,"ax",%progbits + 390 .align 1 + 391 .global HAL_DMA_Start + 392 .syntax unified + 393 .thumb + ARM GAS /tmp/ccaRdTju.s page 25 + + + 394 .thumb_func + 396 HAL_DMA_Start: + 397 .LVL19: + 398 .LFB132: + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 399 .loc 1 282 1 is_stmt 1 view -0 + 400 .cfi_startproc + 401 @ args = 0, pretend = 0, frame = 0 + 402 @ frame_needed = 0, uses_anonymous_args = 0 + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 403 .loc 1 282 1 is_stmt 0 view .LVU140 + 404 0000 70B5 push {r4, r5, r6, lr} + 405 .cfi_def_cfa_offset 16 + 406 .cfi_offset 4, -16 + 407 .cfi_offset 5, -12 + 408 .cfi_offset 6, -8 + 409 .cfi_offset 14, -4 + 410 0002 0446 mov r4, r0 + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 411 .loc 1 283 2 is_stmt 1 view .LVU141 + 412 .LVL20: + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 413 .loc 1 286 3 view .LVU142 + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 414 .loc 1 289 3 view .LVU143 + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 415 .loc 1 289 3 view .LVU144 + 416 0004 90F82000 ldrb r0, [r0, #32] @ zero_extendqisi2 + 417 .LVL21: + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 418 .loc 1 289 3 is_stmt 0 view .LVU145 + 419 0008 0128 cmp r0, #1 + 420 000a 1FD0 beq .L28 + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 421 .loc 1 289 3 is_stmt 1 discriminator 2 view .LVU146 + 422 000c 0120 movs r0, #1 + 423 000e 84F82000 strb r0, [r4, #32] + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 424 .loc 1 289 3 discriminator 2 view .LVU147 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 425 .loc 1 291 3 discriminator 2 view .LVU148 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 426 .loc 1 291 33 is_stmt 0 discriminator 2 view .LVU149 + 427 0012 94F82100 ldrb r0, [r4, #33] @ zero_extendqisi2 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 428 .loc 1 291 5 discriminator 2 view .LVU150 + 429 0016 0128 cmp r0, #1 + 430 0018 04D0 beq .L30 + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 431 .loc 1 310 4 is_stmt 1 view .LVU151 + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 432 .loc 1 310 4 view .LVU152 + 433 001a 0023 movs r3, #0 + 434 .LVL22: + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 435 .loc 1 310 4 is_stmt 0 view .LVU153 + 436 001c 84F82030 strb r3, [r4, #32] + ARM GAS /tmp/ccaRdTju.s page 26 + + + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 437 .loc 1 310 4 is_stmt 1 view .LVU154 + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 438 .loc 1 313 4 view .LVU155 + 439 .LVL23: + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 440 .loc 1 313 11 is_stmt 0 view .LVU156 + 441 0020 0220 movs r0, #2 + 442 .LVL24: + 443 .L26: + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 444 .loc 1 317 1 view .LVU157 + 445 0022 70BD pop {r4, r5, r6, pc} + 446 .LVL25: + 447 .L30: + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 448 .loc 1 294 4 is_stmt 1 view .LVU158 + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 449 .loc 1 294 16 is_stmt 0 view .LVU159 + 450 0024 0220 movs r0, #2 + 451 0026 84F82100 strb r0, [r4, #33] + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 452 .loc 1 296 4 is_stmt 1 view .LVU160 + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 453 .loc 1 296 20 is_stmt 0 view .LVU161 + 454 002a 0025 movs r5, #0 + 455 002c A563 str r5, [r4, #56] + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 456 .loc 1 299 4 is_stmt 1 view .LVU162 + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 457 .loc 1 299 8 is_stmt 0 view .LVU163 + 458 002e 2668 ldr r6, [r4] + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 459 .loc 1 299 18 view .LVU164 + 460 0030 3068 ldr r0, [r6] + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 461 .loc 1 299 24 view .LVU165 + 462 0032 20F00100 bic r0, r0, #1 + 463 0036 3060 str r0, [r6] + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 464 .loc 1 302 4 is_stmt 1 view .LVU166 + 465 0038 2046 mov r0, r4 + 466 003a FFF7FEFF bl DMA_SetConfig + 467 .LVL26: + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 468 .loc 1 305 4 view .LVU167 + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 469 .loc 1 305 8 is_stmt 0 view .LVU168 + 470 003e 2268 ldr r2, [r4] + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 471 .loc 1 305 18 view .LVU169 + 472 0040 1368 ldr r3, [r2] + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 473 .loc 1 305 24 view .LVU170 + 474 0042 43F00103 orr r3, r3, #1 + 475 0046 1360 str r3, [r2] + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + ARM GAS /tmp/ccaRdTju.s page 27 + + + 476 .loc 1 283 20 view .LVU171 + 477 0048 2846 mov r0, r5 + 478 004a EAE7 b .L26 + 479 .LVL27: + 480 .L28: + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 481 .loc 1 289 3 view .LVU172 + 482 004c 0220 movs r0, #2 + 483 004e E8E7 b .L26 + 484 .cfi_endproc + 485 .LFE132: + 487 .section .text.HAL_DMA_Start_IT,"ax",%progbits + 488 .align 1 + 489 .global HAL_DMA_Start_IT + 490 .syntax unified + 491 .thumb + 492 .thumb_func + 494 HAL_DMA_Start_IT: + 495 .LVL28: + 496 .LFB133: + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 497 .loc 1 329 1 is_stmt 1 view -0 + 498 .cfi_startproc + 499 @ args = 0, pretend = 0, frame = 0 + 500 @ frame_needed = 0, uses_anonymous_args = 0 + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 501 .loc 1 329 1 is_stmt 0 view .LVU174 + 502 0000 38B5 push {r3, r4, r5, lr} + 503 .cfi_def_cfa_offset 16 + 504 .cfi_offset 3, -16 + 505 .cfi_offset 4, -12 + 506 .cfi_offset 5, -8 + 507 .cfi_offset 14, -4 + 508 0002 0446 mov r4, r0 + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 509 .loc 1 330 2 is_stmt 1 view .LVU175 + 510 .LVL29: + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 511 .loc 1 333 3 view .LVU176 + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 512 .loc 1 336 3 view .LVU177 + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 513 .loc 1 336 3 view .LVU178 + 514 0004 90F82000 ldrb r0, [r0, #32] @ zero_extendqisi2 + 515 .LVL30: + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 516 .loc 1 336 3 is_stmt 0 view .LVU179 + 517 0008 0128 cmp r0, #1 + 518 000a 31D0 beq .L36 + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 519 .loc 1 336 3 is_stmt 1 discriminator 2 view .LVU180 + 520 000c 0120 movs r0, #1 + 521 000e 84F82000 strb r0, [r4, #32] + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 522 .loc 1 336 3 discriminator 2 view .LVU181 + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 523 .loc 1 338 3 discriminator 2 view .LVU182 + ARM GAS /tmp/ccaRdTju.s page 28 + + + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 524 .loc 1 338 33 is_stmt 0 discriminator 2 view .LVU183 + 525 0012 94F82100 ldrb r0, [r4, #33] @ zero_extendqisi2 + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 526 .loc 1 338 5 discriminator 2 view .LVU184 + 527 0016 0128 cmp r0, #1 + 528 0018 04D0 beq .L38 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 529 .loc 1 369 5 is_stmt 1 view .LVU185 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 530 .loc 1 369 5 view .LVU186 + 531 001a 0023 movs r3, #0 + 532 .LVL31: + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 533 .loc 1 369 5 is_stmt 0 view .LVU187 + 534 001c 84F82030 strb r3, [r4, #32] + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 535 .loc 1 369 5 is_stmt 1 view .LVU188 + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 536 .loc 1 372 5 view .LVU189 + 537 .LVL32: + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 538 .loc 1 372 12 is_stmt 0 view .LVU190 + 539 0020 0220 movs r0, #2 + 540 .LVL33: + 541 .L32: + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 542 .loc 1 376 1 view .LVU191 + 543 0022 38BD pop {r3, r4, r5, pc} + 544 .LVL34: + 545 .L38: + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 546 .loc 1 341 4 is_stmt 1 view .LVU192 + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 547 .loc 1 341 16 is_stmt 0 view .LVU193 + 548 0024 0220 movs r0, #2 + 549 0026 84F82100 strb r0, [r4, #33] + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 550 .loc 1 343 4 is_stmt 1 view .LVU194 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 551 .loc 1 343 20 is_stmt 0 view .LVU195 + 552 002a 0020 movs r0, #0 + 553 002c A063 str r0, [r4, #56] + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 554 .loc 1 346 4 is_stmt 1 view .LVU196 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 555 .loc 1 346 8 is_stmt 0 view .LVU197 + 556 002e 2568 ldr r5, [r4] + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 557 .loc 1 346 18 view .LVU198 + 558 0030 2868 ldr r0, [r5] + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 559 .loc 1 346 24 view .LVU199 + 560 0032 20F00100 bic r0, r0, #1 + 561 0036 2860 str r0, [r5] + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 562 .loc 1 349 4 is_stmt 1 view .LVU200 + ARM GAS /tmp/ccaRdTju.s page 29 + + + 563 0038 2046 mov r0, r4 + 564 003a FFF7FEFF bl DMA_SetConfig + 565 .LVL35: + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 566 .loc 1 353 5 view .LVU201 + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 567 .loc 1 353 20 is_stmt 0 view .LVU202 + 568 003e E36A ldr r3, [r4, #44] + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 569 .loc 1 353 7 view .LVU203 + 570 0040 5BB1 cbz r3, .L34 + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 571 .loc 1 355 7 is_stmt 1 view .LVU204 + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 572 .loc 1 355 11 is_stmt 0 view .LVU205 + 573 0042 2268 ldr r2, [r4] + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 574 .loc 1 355 21 view .LVU206 + 575 0044 1368 ldr r3, [r2] + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 576 .loc 1 355 27 view .LVU207 + 577 0046 43F00E03 orr r3, r3, #14 + 578 004a 1360 str r3, [r2] + 579 .L35: + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 580 .loc 1 364 4 is_stmt 1 view .LVU208 + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 581 .loc 1 364 8 is_stmt 0 view .LVU209 + 582 004c 2268 ldr r2, [r4] + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 583 .loc 1 364 18 view .LVU210 + 584 004e 1368 ldr r3, [r2] + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 585 .loc 1 364 24 view .LVU211 + 586 0050 43F00103 orr r3, r3, #1 + 587 0054 1360 str r3, [r2] + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 588 .loc 1 330 20 view .LVU212 + 589 0056 0020 movs r0, #0 + 590 0058 E3E7 b .L32 + 591 .L34: + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_IT_HT; + 592 .loc 1 359 5 is_stmt 1 view .LVU213 + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_IT_HT; + 593 .loc 1 359 9 is_stmt 0 view .LVU214 + 594 005a 2268 ldr r2, [r4] + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_IT_HT; + 595 .loc 1 359 19 view .LVU215 + 596 005c 1368 ldr r3, [r2] + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_IT_HT; + 597 .loc 1 359 25 view .LVU216 + 598 005e 43F00A03 orr r3, r3, #10 + 599 0062 1360 str r3, [r2] + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 600 .loc 1 360 5 is_stmt 1 view .LVU217 + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 601 .loc 1 360 9 is_stmt 0 view .LVU218 + ARM GAS /tmp/ccaRdTju.s page 30 + + + 602 0064 2268 ldr r2, [r4] + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 603 .loc 1 360 19 view .LVU219 + 604 0066 1368 ldr r3, [r2] + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 605 .loc 1 360 25 view .LVU220 + 606 0068 23F00403 bic r3, r3, #4 + 607 006c 1360 str r3, [r2] + 608 006e EDE7 b .L35 + 609 .LVL36: + 610 .L36: + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 611 .loc 1 336 3 view .LVU221 + 612 0070 0220 movs r0, #2 + 613 0072 D6E7 b .L32 + 614 .cfi_endproc + 615 .LFE133: + 617 .section .text.HAL_DMA_Abort,"ax",%progbits + 618 .align 1 + 619 .global HAL_DMA_Abort + 620 .syntax unified + 621 .thumb + 622 .thumb_func + 624 HAL_DMA_Abort: + 625 .LVL37: + 626 .LFB134: + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 627 .loc 1 385 1 is_stmt 1 view -0 + 628 .cfi_startproc + 629 @ args = 0, pretend = 0, frame = 0 + 630 @ frame_needed = 0, uses_anonymous_args = 0 + 631 @ link register save eliminated. + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 632 .loc 1 385 1 is_stmt 0 view .LVU223 + 633 0000 0346 mov r3, r0 + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 634 .loc 1 386 3 is_stmt 1 view .LVU224 + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 635 .loc 1 386 10 is_stmt 0 view .LVU225 + 636 0002 90F82120 ldrb r2, [r0, #33] @ zero_extendqisi2 + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 637 .loc 1 386 5 view .LVU226 + 638 0006 022A cmp r2, #2 + 639 0008 06D0 beq .L40 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 640 .loc 1 389 5 is_stmt 1 view .LVU227 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 641 .loc 1 389 21 is_stmt 0 view .LVU228 + 642 000a 0422 movs r2, #4 + 643 000c 8263 str r2, [r0, #56] + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 644 .loc 1 392 5 is_stmt 1 view .LVU229 + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 645 .loc 1 392 5 view .LVU230 + 646 000e 0022 movs r2, #0 + 647 0010 80F82020 strb r2, [r0, #32] + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + ARM GAS /tmp/ccaRdTju.s page 31 + + + 648 .loc 1 392 5 view .LVU231 + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 649 .loc 1 394 5 view .LVU232 + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 650 .loc 1 394 12 is_stmt 0 view .LVU233 + 651 0014 0120 movs r0, #1 + 652 .LVL38: + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 653 .loc 1 394 12 view .LVU234 + 654 0016 7047 bx lr + 655 .LVL39: + 656 .L40: + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 657 .loc 1 399 6 is_stmt 1 view .LVU235 + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 658 .loc 1 399 10 is_stmt 0 view .LVU236 + 659 0018 0168 ldr r1, [r0] + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 660 .loc 1 399 20 view .LVU237 + 661 001a 0A68 ldr r2, [r1] + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 662 .loc 1 399 26 view .LVU238 + 663 001c 22F00E02 bic r2, r2, #14 + 664 0020 0A60 str r2, [r1] + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 665 .loc 1 402 5 is_stmt 1 view .LVU239 + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 666 .loc 1 402 9 is_stmt 0 view .LVU240 + 667 0022 0168 ldr r1, [r0] + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 668 .loc 1 402 19 view .LVU241 + 669 0024 0A68 ldr r2, [r1] + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 670 .loc 1 402 25 view .LVU242 + 671 0026 22F00102 bic r2, r2, #1 + 672 002a 0A60 str r2, [r1] + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 673 .loc 1 405 5 is_stmt 1 view .LVU243 + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 674 .loc 1 405 55 is_stmt 0 view .LVU244 + 675 002c 026C ldr r2, [r0, #64] + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 676 .loc 1 405 9 view .LVU245 + 677 002e C06B ldr r0, [r0, #60] + 678 .LVL40: + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 679 .loc 1 405 48 view .LVU246 + 680 0030 0121 movs r1, #1 + 681 0032 01FA02F2 lsl r2, r1, r2 + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 682 .loc 1 405 32 view .LVU247 + 683 0036 4260 str r2, [r0, #4] + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 684 .loc 1 408 3 is_stmt 1 view .LVU248 + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 685 .loc 1 408 15 is_stmt 0 view .LVU249 + 686 0038 83F82110 strb r1, [r3, #33] + ARM GAS /tmp/ccaRdTju.s page 32 + + + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 687 .loc 1 411 3 is_stmt 1 view .LVU250 + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 688 .loc 1 411 3 view .LVU251 + 689 003c 0020 movs r0, #0 + 690 003e 83F82000 strb r0, [r3, #32] + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 691 .loc 1 411 3 view .LVU252 + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 692 .loc 1 413 3 view .LVU253 + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 693 .loc 1 414 1 is_stmt 0 view .LVU254 + 694 0042 7047 bx lr + 695 .cfi_endproc + 696 .LFE134: + 698 .section .text.HAL_DMA_Abort_IT,"ax",%progbits + 699 .align 1 + 700 .global HAL_DMA_Abort_IT + 701 .syntax unified + 702 .thumb + 703 .thumb_func + 705 HAL_DMA_Abort_IT: + 706 .LVL41: + 707 .LFB135: + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 708 .loc 1 423 1 is_stmt 1 view -0 + 709 .cfi_startproc + 710 @ args = 0, pretend = 0, frame = 0 + 711 @ frame_needed = 0, uses_anonymous_args = 0 + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 712 .loc 1 423 1 is_stmt 0 view .LVU256 + 713 0000 08B5 push {r3, lr} + 714 .cfi_def_cfa_offset 8 + 715 .cfi_offset 3, -8 + 716 .cfi_offset 14, -4 + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 717 .loc 1 424 3 is_stmt 1 view .LVU257 + 718 .LVL42: + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 719 .loc 1 426 3 view .LVU258 + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 720 .loc 1 426 32 is_stmt 0 view .LVU259 + 721 0002 90F82130 ldrb r3, [r0, #33] @ zero_extendqisi2 + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 722 .loc 1 426 5 view .LVU260 + 723 0006 022B cmp r3, #2 + 724 0008 03D0 beq .L43 + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 725 .loc 1 429 5 is_stmt 1 view .LVU261 + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 726 .loc 1 429 21 is_stmt 0 view .LVU262 + 727 000a 0423 movs r3, #4 + 728 000c 8363 str r3, [r0, #56] + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 729 .loc 1 431 5 is_stmt 1 view .LVU263 + 730 .LVL43: + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + ARM GAS /tmp/ccaRdTju.s page 33 + + + 731 .loc 1 431 12 is_stmt 0 view .LVU264 + 732 000e 0120 movs r0, #1 + 733 .LVL44: + 734 .L44: + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 735 .loc 1 457 3 is_stmt 1 view .LVU265 + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 736 .loc 1 458 1 is_stmt 0 view .LVU266 + 737 0010 08BD pop {r3, pc} + 738 .LVL45: + 739 .L43: + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 740 .loc 1 437 5 is_stmt 1 view .LVU267 + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 741 .loc 1 437 9 is_stmt 0 view .LVU268 + 742 0012 0268 ldr r2, [r0] + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 743 .loc 1 437 19 view .LVU269 + 744 0014 1368 ldr r3, [r2] + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 745 .loc 1 437 25 view .LVU270 + 746 0016 23F00E03 bic r3, r3, #14 + 747 001a 1360 str r3, [r2] + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 748 .loc 1 440 5 is_stmt 1 view .LVU271 + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 749 .loc 1 440 9 is_stmt 0 view .LVU272 + 750 001c 0268 ldr r2, [r0] + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 751 .loc 1 440 19 view .LVU273 + 752 001e 1368 ldr r3, [r2] + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 753 .loc 1 440 25 view .LVU274 + 754 0020 23F00103 bic r3, r3, #1 + 755 0024 1360 str r3, [r2] + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 756 .loc 1 443 5 is_stmt 1 view .LVU275 + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 757 .loc 1 443 54 is_stmt 0 view .LVU276 + 758 0026 036C ldr r3, [r0, #64] + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 759 .loc 1 443 9 view .LVU277 + 760 0028 C16B ldr r1, [r0, #60] + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 761 .loc 1 443 47 view .LVU278 + 762 002a 0122 movs r2, #1 + 763 002c 02FA03F3 lsl r3, r2, r3 + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 764 .loc 1 443 32 view .LVU279 + 765 0030 4B60 str r3, [r1, #4] + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 766 .loc 1 446 5 is_stmt 1 view .LVU280 + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 767 .loc 1 446 17 is_stmt 0 view .LVU281 + 768 0032 80F82120 strb r2, [r0, #33] + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 769 .loc 1 449 5 is_stmt 1 view .LVU282 + ARM GAS /tmp/ccaRdTju.s page 34 + + + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 770 .loc 1 449 5 view .LVU283 + 771 0036 0023 movs r3, #0 + 772 0038 80F82030 strb r3, [r0, #32] + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 773 .loc 1 449 5 view .LVU284 + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 774 .loc 1 452 5 view .LVU285 + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 775 .loc 1 452 12 is_stmt 0 view .LVU286 + 776 003c 436B ldr r3, [r0, #52] + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 777 .loc 1 452 7 view .LVU287 + 778 003e 13B1 cbz r3, .L45 + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 779 .loc 1 454 7 is_stmt 1 view .LVU288 + 780 0040 9847 blx r3 + 781 .LVL46: + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 782 .loc 1 424 21 is_stmt 0 view .LVU289 + 783 0042 0020 movs r0, #0 + 784 0044 E4E7 b .L44 + 785 .LVL47: + 786 .L45: + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 787 .loc 1 424 21 view .LVU290 + 788 0046 0020 movs r0, #0 + 789 .LVL48: + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 790 .loc 1 424 21 view .LVU291 + 791 0048 E2E7 b .L44 + 792 .cfi_endproc + 793 .LFE135: + 795 .section .text.HAL_DMA_PollForTransfer,"ax",%progbits + 796 .align 1 + 797 .global HAL_DMA_PollForTransfer + 798 .syntax unified + 799 .thumb + 800 .thumb_func + 802 HAL_DMA_PollForTransfer: + 803 .LVL49: + 804 .LFB136: + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t temp; + 805 .loc 1 469 1 is_stmt 1 view -0 + 806 .cfi_startproc + 807 @ args = 0, pretend = 0, frame = 0 + 808 @ frame_needed = 0, uses_anonymous_args = 0 + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t temp; + 809 .loc 1 469 1 is_stmt 0 view .LVU293 + 810 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 811 .cfi_def_cfa_offset 32 + 812 .cfi_offset 3, -32 + 813 .cfi_offset 4, -28 + 814 .cfi_offset 5, -24 + 815 .cfi_offset 6, -20 + 816 .cfi_offset 7, -16 + 817 .cfi_offset 8, -12 + ARM GAS /tmp/ccaRdTju.s page 35 + + + 818 .cfi_offset 9, -8 + 819 .cfi_offset 14, -4 + 820 0004 0446 mov r4, r0 + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t tickstart = 0U; + 821 .loc 1 470 3 is_stmt 1 view .LVU294 + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 822 .loc 1 471 3 view .LVU295 + 823 .LVL50: + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 824 .loc 1 473 3 view .LVU296 + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 825 .loc 1 473 32 is_stmt 0 view .LVU297 + 826 0006 90F82130 ldrb r3, [r0, #33] @ zero_extendqisi2 + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 827 .loc 1 473 5 view .LVU298 + 828 000a 022B cmp r3, #2 + 829 000c 07D0 beq .L48 + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 830 .loc 1 476 5 is_stmt 1 view .LVU299 + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 831 .loc 1 476 21 is_stmt 0 view .LVU300 + 832 000e 0423 movs r3, #4 + 833 0010 8363 str r3, [r0, #56] + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 834 .loc 1 477 5 is_stmt 1 view .LVU301 + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 835 .loc 1 477 5 view .LVU302 + 836 0012 0023 movs r3, #0 + 837 0014 80F82030 strb r3, [r0, #32] + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 838 .loc 1 477 5 view .LVU303 + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 839 .loc 1 478 5 view .LVU304 + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 840 .loc 1 478 12 is_stmt 0 view .LVU305 + 841 0018 0120 movs r0, #1 + 842 .LVL51: + 843 .L49: + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 844 .loc 1 561 1 view .LVU306 + 845 001a BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 846 .LVL52: + 847 .L48: + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 848 .loc 1 561 1 view .LVU307 + 849 001e 8846 mov r8, r1 + 850 0020 1646 mov r6, r2 + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 851 .loc 1 482 3 is_stmt 1 view .LVU308 + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 852 .loc 1 482 21 is_stmt 0 view .LVU309 + 853 0022 0368 ldr r3, [r0] + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 854 .loc 1 482 31 view .LVU310 + 855 0024 1B68 ldr r3, [r3] + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 856 .loc 1 482 6 view .LVU311 + ARM GAS /tmp/ccaRdTju.s page 36 + + + 857 0026 13F0200F tst r3, #32 + 858 002a 23D1 bne .L61 + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 859 .loc 1 489 3 is_stmt 1 view .LVU312 + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 860 .loc 1 489 5 is_stmt 0 view .LVU313 + 861 002c 39BB cbnz r1, .L51 + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 862 .loc 1 492 5 is_stmt 1 view .LVU314 + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 863 .loc 1 492 32 is_stmt 0 view .LVU315 + 864 002e 036C ldr r3, [r0, #64] + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 865 .loc 1 492 10 view .LVU316 + 866 0030 0227 movs r7, #2 + 867 0032 9F40 lsls r7, r7, r3 + 868 .LVL53: + 869 .L52: + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 870 .loc 1 501 3 is_stmt 1 view .LVU317 + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 871 .loc 1 501 15 is_stmt 0 view .LVU318 + 872 0034 FFF7FEFF bl HAL_GetTick + 873 .LVL54: + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 874 .loc 1 501 15 view .LVU319 + 875 0038 8146 mov r9, r0 + 876 .LVL55: + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 877 .loc 1 503 3 is_stmt 1 view .LVU320 + 878 .L55: + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 879 .loc 1 503 15 view .LVU321 + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 880 .loc 1 503 23 is_stmt 0 view .LVU322 + 881 003a E56B ldr r5, [r4, #60] + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 882 .loc 1 503 39 view .LVU323 + 883 003c 2B68 ldr r3, [r5] + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 884 .loc 1 503 15 view .LVU324 + 885 003e 3B42 tst r3, r7 + 886 0040 2CD1 bne .L62 + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 887 .loc 1 505 5 is_stmt 1 view .LVU325 + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 888 .loc 1 505 38 is_stmt 0 view .LVU326 + 889 0042 2968 ldr r1, [r5] + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 890 .loc 1 505 67 view .LVU327 + 891 0044 226C ldr r2, [r4, #64] + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 892 .loc 1 505 60 view .LVU328 + 893 0046 0823 movs r3, #8 + 894 0048 9340 lsls r3, r3, r2 + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 895 .loc 1 505 7 view .LVU329 + ARM GAS /tmp/ccaRdTju.s page 37 + + + 896 004a 1942 tst r1, r3 + 897 004c 1BD1 bne .L63 + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 898 .loc 1 524 5 is_stmt 1 view .LVU330 + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 899 .loc 1 524 7 is_stmt 0 view .LVU331 + 900 004e B6F1FF3F cmp r6, #-1 + 901 0052 F2D0 beq .L55 + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 902 .loc 1 526 7 is_stmt 1 view .LVU332 + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 903 .loc 1 526 9 is_stmt 0 view .LVU333 + 904 0054 2EB1 cbz r6, .L56 + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 905 .loc 1 526 31 discriminator 1 view .LVU334 + 906 0056 FFF7FEFF bl HAL_GetTick + 907 .LVL56: + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 908 .loc 1 526 45 discriminator 1 view .LVU335 + 909 005a A0EB0900 sub r0, r0, r9 + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 910 .loc 1 526 26 discriminator 1 view .LVU336 + 911 005e B042 cmp r0, r6 + 912 0060 EBD9 bls .L55 + 913 .L56: + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 914 .loc 1 529 9 is_stmt 1 view .LVU337 + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 915 .loc 1 529 25 is_stmt 0 view .LVU338 + 916 0062 2023 movs r3, #32 + 917 0064 A363 str r3, [r4, #56] + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 918 .loc 1 532 9 is_stmt 1 view .LVU339 + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 919 .loc 1 532 21 is_stmt 0 view .LVU340 + 920 0066 0120 movs r0, #1 + 921 0068 84F82100 strb r0, [r4, #33] + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 922 .loc 1 535 9 is_stmt 1 view .LVU341 + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 923 .loc 1 535 9 view .LVU342 + 924 006c 0023 movs r3, #0 + 925 006e 84F82030 strb r3, [r4, #32] + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 926 .loc 1 535 9 view .LVU343 + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 927 .loc 1 537 9 view .LVU344 + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 928 .loc 1 537 16 is_stmt 0 view .LVU345 + 929 0072 D2E7 b .L49 + 930 .LVL57: + 931 .L61: + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 932 .loc 1 484 5 is_stmt 1 view .LVU346 + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 933 .loc 1 484 21 is_stmt 0 view .LVU347 + 934 0074 4FF48073 mov r3, #256 + ARM GAS /tmp/ccaRdTju.s page 38 + + + 935 0078 8363 str r3, [r0, #56] + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 936 .loc 1 485 5 is_stmt 1 view .LVU348 + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 937 .loc 1 485 12 is_stmt 0 view .LVU349 + 938 007a 0120 movs r0, #1 + 939 .LVL58: + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 940 .loc 1 485 12 view .LVU350 + 941 007c CDE7 b .L49 + 942 .LVL59: + 943 .L51: + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 944 .loc 1 497 5 is_stmt 1 view .LVU351 + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 945 .loc 1 497 32 is_stmt 0 view .LVU352 + 946 007e 036C ldr r3, [r0, #64] + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 947 .loc 1 497 10 view .LVU353 + 948 0080 0427 movs r7, #4 + 949 0082 9F40 lsls r7, r7, r3 + 950 .LVL60: + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 951 .loc 1 497 10 view .LVU354 + 952 0084 D6E7 b .L52 + 953 .LVL61: + 954 .L63: + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 955 .loc 1 510 7 is_stmt 1 view .LVU355 + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 956 .loc 1 510 49 is_stmt 0 view .LVU356 + 957 0086 0120 movs r0, #1 + 958 0088 00FA02F2 lsl r2, r0, r2 + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 959 .loc 1 510 34 view .LVU357 + 960 008c 6A60 str r2, [r5, #4] + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 961 .loc 1 513 7 is_stmt 1 view .LVU358 + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 962 .loc 1 513 23 is_stmt 0 view .LVU359 + 963 008e A063 str r0, [r4, #56] + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 964 .loc 1 516 7 is_stmt 1 view .LVU360 + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 965 .loc 1 516 18 is_stmt 0 view .LVU361 + 966 0090 84F82100 strb r0, [r4, #33] + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 967 .loc 1 519 7 is_stmt 1 view .LVU362 + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 968 .loc 1 519 7 view .LVU363 + 969 0094 0023 movs r3, #0 + 970 0096 84F82030 strb r3, [r4, #32] + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 971 .loc 1 519 7 view .LVU364 + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 972 .loc 1 521 7 view .LVU365 + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + ARM GAS /tmp/ccaRdTju.s page 39 + + + 973 .loc 1 521 14 is_stmt 0 view .LVU366 + 974 009a BEE7 b .L49 + 975 .L62: + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 976 .loc 1 542 3 is_stmt 1 view .LVU367 + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 977 .loc 1 542 5 is_stmt 0 view .LVU368 + 978 009c B8F1000F cmp r8, #0 + 979 00a0 0AD1 bne .L58 + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 980 .loc 1 545 5 is_stmt 1 view .LVU369 + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 981 .loc 1 545 54 is_stmt 0 view .LVU370 + 982 00a2 226C ldr r2, [r4, #64] + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 983 .loc 1 545 47 view .LVU371 + 984 00a4 0223 movs r3, #2 + 985 00a6 9340 lsls r3, r3, r2 + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 986 .loc 1 545 32 view .LVU372 + 987 00a8 6B60 str r3, [r5, #4] + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 988 .loc 1 549 5 is_stmt 1 view .LVU373 + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 989 .loc 1 549 17 is_stmt 0 view .LVU374 + 990 00aa 0123 movs r3, #1 + 991 00ac 84F82130 strb r3, [r4, #33] + 992 .L59: + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 993 .loc 1 558 3 is_stmt 1 view .LVU375 + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 994 .loc 1 558 3 view .LVU376 + 995 00b0 0020 movs r0, #0 + 996 00b2 84F82000 strb r0, [r4, #32] + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 997 .loc 1 558 3 view .LVU377 + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 998 .loc 1 560 3 view .LVU378 + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 999 .loc 1 560 10 is_stmt 0 view .LVU379 + 1000 00b6 B0E7 b .L49 + 1001 .L58: + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1002 .loc 1 554 5 is_stmt 1 view .LVU380 + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1003 .loc 1 554 54 is_stmt 0 view .LVU381 + 1004 00b8 226C ldr r2, [r4, #64] + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1005 .loc 1 554 47 view .LVU382 + 1006 00ba 0423 movs r3, #4 + 1007 00bc 9340 lsls r3, r3, r2 + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1008 .loc 1 554 32 view .LVU383 + 1009 00be 6B60 str r3, [r5, #4] + 1010 00c0 F6E7 b .L59 + 1011 .cfi_endproc + 1012 .LFE136: + ARM GAS /tmp/ccaRdTju.s page 40 + + + 1014 .section .text.HAL_DMA_IRQHandler,"ax",%progbits + 1015 .align 1 + 1016 .global HAL_DMA_IRQHandler + 1017 .syntax unified + 1018 .thumb + 1019 .thumb_func + 1021 HAL_DMA_IRQHandler: + 1022 .LVL62: + 1023 .LFB137: + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t flag_it = hdma->DmaBaseAddress->ISR; + 1024 .loc 1 570 1 is_stmt 1 view -0 + 1025 .cfi_startproc + 1026 @ args = 0, pretend = 0, frame = 0 + 1027 @ frame_needed = 0, uses_anonymous_args = 0 + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t flag_it = hdma->DmaBaseAddress->ISR; + 1028 .loc 1 570 1 is_stmt 0 view .LVU385 + 1029 0000 38B5 push {r3, r4, r5, lr} + 1030 .cfi_def_cfa_offset 16 + 1031 .cfi_offset 3, -16 + 1032 .cfi_offset 4, -12 + 1033 .cfi_offset 5, -8 + 1034 .cfi_offset 14, -4 + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t source_it = hdma->Instance->CCR; + 1035 .loc 1 571 2 is_stmt 1 view .LVU386 + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t source_it = hdma->Instance->CCR; + 1036 .loc 1 571 25 is_stmt 0 view .LVU387 + 1037 0002 C36B ldr r3, [r0, #60] + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t source_it = hdma->Instance->CCR; + 1038 .loc 1 571 11 view .LVU388 + 1039 0004 1A68 ldr r2, [r3] + 1040 .LVL63: + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1041 .loc 1 572 3 is_stmt 1 view .LVU389 + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1042 .loc 1 572 28 is_stmt 0 view .LVU390 + 1043 0006 0468 ldr r4, [r0] + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1044 .loc 1 572 12 view .LVU391 + 1045 0008 2568 ldr r5, [r4] + 1046 .LVL64: + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1047 .loc 1 575 3 is_stmt 1 view .LVU392 + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1048 .loc 1 575 49 is_stmt 0 view .LVU393 + 1049 000a 016C ldr r1, [r0, #64] + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1050 .loc 1 575 42 view .LVU394 + 1051 000c 0423 movs r3, #4 + 1052 000e 8B40 lsls r3, r3, r1 + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1053 .loc 1 575 6 view .LVU395 + 1054 0010 1342 tst r3, r2 + 1055 0012 13D0 beq .L65 + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1056 .loc 1 575 67 discriminator 1 view .LVU396 + 1057 0014 15F0040F tst r5, #4 + 1058 0018 10D0 beq .L65 + ARM GAS /tmp/ccaRdTju.s page 41 + + + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1059 .loc 1 578 4 is_stmt 1 view .LVU397 + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1060 .loc 1 578 22 is_stmt 0 view .LVU398 + 1061 001a 2368 ldr r3, [r4] + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1062 .loc 1 578 6 view .LVU399 + 1063 001c 13F0200F tst r3, #32 + 1064 0020 03D1 bne .L66 + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1065 .loc 1 581 5 is_stmt 1 view .LVU400 + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1066 .loc 1 581 19 is_stmt 0 view .LVU401 + 1067 0022 2368 ldr r3, [r4] + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1068 .loc 1 581 25 view .LVU402 + 1069 0024 23F00403 bic r3, r3, #4 + 1070 0028 2360 str r3, [r4] + 1071 .L66: + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1072 .loc 1 585 4 is_stmt 1 view .LVU403 + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1073 .loc 1 585 53 is_stmt 0 view .LVU404 + 1074 002a 016C ldr r1, [r0, #64] + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1075 .loc 1 585 8 view .LVU405 + 1076 002c C26B ldr r2, [r0, #60] + 1077 .LVL65: + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1078 .loc 1 585 46 view .LVU406 + 1079 002e 0423 movs r3, #4 + 1080 0030 8B40 lsls r3, r3, r1 + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1081 .loc 1 585 31 view .LVU407 + 1082 0032 5360 str r3, [r2, #4] + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1083 .loc 1 590 4 is_stmt 1 view .LVU408 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1084 .loc 1 590 11 is_stmt 0 view .LVU409 + 1085 0034 C36A ldr r3, [r0, #44] + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1086 .loc 1 590 6 view .LVU410 + 1087 0036 03B1 cbz r3, .L64 + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1088 .loc 1 593 5 is_stmt 1 view .LVU411 + 1089 0038 9847 blx r3 + 1090 .LVL66: + 1091 .L64: + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1092 .loc 1 649 1 is_stmt 0 view .LVU412 + 1093 003a 38BD pop {r3, r4, r5, pc} + 1094 .LVL67: + 1095 .L65: + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1096 .loc 1 598 8 is_stmt 1 view .LVU413 + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1097 .loc 1 598 47 is_stmt 0 view .LVU414 + ARM GAS /tmp/ccaRdTju.s page 42 + + + 1098 003c 0223 movs r3, #2 + 1099 003e 8B40 lsls r3, r3, r1 + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1100 .loc 1 598 11 view .LVU415 + 1101 0040 1342 tst r3, r2 + 1102 0042 1AD0 beq .L68 + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1103 .loc 1 598 72 discriminator 1 view .LVU416 + 1104 0044 15F0020F tst r5, #2 + 1105 0048 17D0 beq .L68 + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1106 .loc 1 600 4 is_stmt 1 view .LVU417 + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1107 .loc 1 600 22 is_stmt 0 view .LVU418 + 1108 004a 2368 ldr r3, [r4] + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1109 .loc 1 600 6 view .LVU419 + 1110 004c 13F0200F tst r3, #32 + 1111 0050 06D1 bne .L69 + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1112 .loc 1 604 5 is_stmt 1 view .LVU420 + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1113 .loc 1 604 19 is_stmt 0 view .LVU421 + 1114 0052 2368 ldr r3, [r4] + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1115 .loc 1 604 25 view .LVU422 + 1116 0054 23F00A03 bic r3, r3, #10 + 1117 0058 2360 str r3, [r4] + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1118 .loc 1 607 5 is_stmt 1 view .LVU423 + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1119 .loc 1 607 17 is_stmt 0 view .LVU424 + 1120 005a 0123 movs r3, #1 + 1121 005c 80F82130 strb r3, [r0, #33] + 1122 .L69: + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1123 .loc 1 611 4 is_stmt 1 view .LVU425 + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1124 .loc 1 611 53 is_stmt 0 view .LVU426 + 1125 0060 016C ldr r1, [r0, #64] + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1126 .loc 1 611 8 view .LVU427 + 1127 0062 C26B ldr r2, [r0, #60] + 1128 .LVL68: + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1129 .loc 1 611 46 view .LVU428 + 1130 0064 0223 movs r3, #2 + 1131 0066 8B40 lsls r3, r3, r1 + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1132 .loc 1 611 31 view .LVU429 + 1133 0068 5360 str r3, [r2, #4] + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1134 .loc 1 614 4 is_stmt 1 view .LVU430 + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1135 .loc 1 614 4 view .LVU431 + 1136 006a 0023 movs r3, #0 + 1137 006c 80F82030 strb r3, [r0, #32] + ARM GAS /tmp/ccaRdTju.s page 43 + + + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1138 .loc 1 614 4 view .LVU432 + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1139 .loc 1 616 4 view .LVU433 + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1140 .loc 1 616 11 is_stmt 0 view .LVU434 + 1141 0070 836A ldr r3, [r0, #40] + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1142 .loc 1 616 6 view .LVU435 + 1143 0072 002B cmp r3, #0 + 1144 0074 E1D0 beq .L64 + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1145 .loc 1 619 5 is_stmt 1 view .LVU436 + 1146 0076 9847 blx r3 + 1147 .LVL69: + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1148 .loc 1 619 5 is_stmt 0 view .LVU437 + 1149 0078 DFE7 b .L64 + 1150 .LVL70: + 1151 .L68: + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1152 .loc 1 624 8 is_stmt 1 view .LVU438 + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1153 .loc 1 624 48 is_stmt 0 view .LVU439 + 1154 007a 0823 movs r3, #8 + 1155 007c 8B40 lsls r3, r3, r1 + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1156 .loc 1 624 11 view .LVU440 + 1157 007e 1342 tst r3, r2 + 1158 0080 DBD0 beq .L64 + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1159 .loc 1 624 73 discriminator 1 view .LVU441 + 1160 0082 15F0080F tst r5, #8 + 1161 0086 D8D0 beq .L64 + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1162 .loc 1 629 5 is_stmt 1 view .LVU442 + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1163 .loc 1 629 19 is_stmt 0 view .LVU443 + 1164 0088 2368 ldr r3, [r4] + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1165 .loc 1 629 25 view .LVU444 + 1166 008a 23F00E03 bic r3, r3, #14 + 1167 008e 2360 str r3, [r4] + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1168 .loc 1 632 5 is_stmt 1 view .LVU445 + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1169 .loc 1 632 54 is_stmt 0 view .LVU446 + 1170 0090 026C ldr r2, [r0, #64] + 1171 .LVL71: + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1172 .loc 1 632 9 view .LVU447 + 1173 0092 C16B ldr r1, [r0, #60] + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1174 .loc 1 632 47 view .LVU448 + 1175 0094 0123 movs r3, #1 + 1176 0096 03FA02F2 lsl r2, r3, r2 + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + ARM GAS /tmp/ccaRdTju.s page 44 + + + 1177 .loc 1 632 32 view .LVU449 + 1178 009a 4A60 str r2, [r1, #4] + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1179 .loc 1 635 5 is_stmt 1 view .LVU450 + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1180 .loc 1 635 21 is_stmt 0 view .LVU451 + 1181 009c 8363 str r3, [r0, #56] + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1182 .loc 1 638 5 is_stmt 1 view .LVU452 + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1183 .loc 1 638 17 is_stmt 0 view .LVU453 + 1184 009e 80F82130 strb r3, [r0, #33] + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1185 .loc 1 641 5 is_stmt 1 view .LVU454 + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1186 .loc 1 641 5 view .LVU455 + 1187 00a2 0023 movs r3, #0 + 1188 00a4 80F82030 strb r3, [r0, #32] + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1189 .loc 1 641 5 view .LVU456 + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1190 .loc 1 643 5 view .LVU457 + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1191 .loc 1 643 12 is_stmt 0 view .LVU458 + 1192 00a8 036B ldr r3, [r0, #48] + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1193 .loc 1 643 7 view .LVU459 + 1194 00aa 002B cmp r3, #0 + 1195 00ac C5D0 beq .L64 + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1196 .loc 1 646 6 is_stmt 1 view .LVU460 + 1197 00ae 9847 blx r3 + 1198 .LVL72: + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1199 .loc 1 649 1 is_stmt 0 view .LVU461 + 1200 00b0 C3E7 b .L64 + 1201 .cfi_endproc + 1202 .LFE137: + 1204 .section .text.HAL_DMA_RegisterCallback,"ax",%progbits + 1205 .align 1 + 1206 .global HAL_DMA_RegisterCallback + 1207 .syntax unified + 1208 .thumb + 1209 .thumb_func + 1211 HAL_DMA_RegisterCallback: + 1212 .LVL73: + 1213 .LFB138: + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1214 .loc 1 662 1 is_stmt 1 view -0 + 1215 .cfi_startproc + 1216 @ args = 0, pretend = 0, frame = 0 + 1217 @ frame_needed = 0, uses_anonymous_args = 0 + 1218 @ link register save eliminated. + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1219 .loc 1 662 1 is_stmt 0 view .LVU463 + 1220 0000 0346 mov r3, r0 + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + ARM GAS /tmp/ccaRdTju.s page 45 + + + 1221 .loc 1 663 3 is_stmt 1 view .LVU464 + 1222 .LVL74: + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1223 .loc 1 666 3 view .LVU465 + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1224 .loc 1 666 3 view .LVU466 + 1225 0002 90F82000 ldrb r0, [r0, #32] @ zero_extendqisi2 + 1226 .LVL75: + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1227 .loc 1 666 3 is_stmt 0 view .LVU467 + 1228 0006 0128 cmp r0, #1 + 1229 0008 1DD0 beq .L79 + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1230 .loc 1 666 3 is_stmt 1 discriminator 2 view .LVU468 + 1231 000a 0120 movs r0, #1 + 1232 000c 83F82000 strb r0, [r3, #32] + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1233 .loc 1 666 3 discriminator 2 view .LVU469 + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1234 .loc 1 668 3 discriminator 2 view .LVU470 + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1235 .loc 1 668 33 is_stmt 0 discriminator 2 view .LVU471 + 1236 0010 93F82100 ldrb r0, [r3, #33] @ zero_extendqisi2 + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1237 .loc 1 668 5 discriminator 2 view .LVU472 + 1238 0014 0128 cmp r0, #1 + 1239 0016 04D0 beq .L82 + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1240 .loc 1 695 12 view .LVU473 + 1241 0018 0120 movs r0, #1 + 1242 .L73: + 1243 .LVL76: + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1244 .loc 1 699 3 is_stmt 1 view .LVU474 + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1245 .loc 1 699 3 view .LVU475 + 1246 001a 0022 movs r2, #0 + 1247 .LVL77: + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1248 .loc 1 699 3 is_stmt 0 view .LVU476 + 1249 001c 83F82020 strb r2, [r3, #32] + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1250 .loc 1 699 3 is_stmt 1 view .LVU477 + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1251 .loc 1 701 3 view .LVU478 + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1252 .loc 1 701 10 is_stmt 0 view .LVU479 + 1253 0020 7047 bx lr + 1254 .LVL78: + 1255 .L82: + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1256 .loc 1 670 5 is_stmt 1 view .LVU480 + 1257 0022 0329 cmp r1, #3 + 1258 0024 F9D8 bhi .L73 + 1259 0026 DFE801F0 tbb [pc, r1] + 1260 .L75: + 1261 002a 02 .byte (.L78-.L75)/2 + ARM GAS /tmp/ccaRdTju.s page 46 + + + 1262 002b 05 .byte (.L77-.L75)/2 + 1263 002c 08 .byte (.L76-.L75)/2 + 1264 002d 0B .byte (.L74-.L75)/2 + 1265 .p2align 1 + 1266 .L78: + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1267 .loc 1 673 12 view .LVU481 + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1268 .loc 1 673 35 is_stmt 0 view .LVU482 + 1269 002e 9A62 str r2, [r3, #40] + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1270 .loc 1 674 12 is_stmt 1 view .LVU483 + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1271 .loc 1 663 21 is_stmt 0 view .LVU484 + 1272 0030 0846 mov r0, r1 + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1273 .loc 1 674 12 view .LVU485 + 1274 0032 F2E7 b .L73 + 1275 .L77: + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1276 .loc 1 677 12 is_stmt 1 view .LVU486 + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1277 .loc 1 677 39 is_stmt 0 view .LVU487 + 1278 0034 DA62 str r2, [r3, #44] + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1279 .loc 1 678 12 is_stmt 1 view .LVU488 + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1280 .loc 1 663 21 is_stmt 0 view .LVU489 + 1281 0036 0020 movs r0, #0 + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1282 .loc 1 678 12 view .LVU490 + 1283 0038 EFE7 b .L73 + 1284 .L76: + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1285 .loc 1 681 12 is_stmt 1 view .LVU491 + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1286 .loc 1 681 36 is_stmt 0 view .LVU492 + 1287 003a 1A63 str r2, [r3, #48] + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1288 .loc 1 682 12 is_stmt 1 view .LVU493 + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1289 .loc 1 663 21 is_stmt 0 view .LVU494 + 1290 003c 0020 movs r0, #0 + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1291 .loc 1 682 12 view .LVU495 + 1292 003e ECE7 b .L73 + 1293 .L74: + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1294 .loc 1 685 12 is_stmt 1 view .LVU496 + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1295 .loc 1 685 36 is_stmt 0 view .LVU497 + 1296 0040 5A63 str r2, [r3, #52] + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1297 .loc 1 686 12 is_stmt 1 view .LVU498 + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1298 .loc 1 663 21 is_stmt 0 view .LVU499 + 1299 0042 0020 movs r0, #0 + ARM GAS /tmp/ccaRdTju.s page 47 + + + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1300 .loc 1 686 12 view .LVU500 + 1301 0044 E9E7 b .L73 + 1302 .L79: + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1303 .loc 1 666 3 view .LVU501 + 1304 0046 0220 movs r0, #2 + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1305 .loc 1 702 1 view .LVU502 + 1306 0048 7047 bx lr + 1307 .cfi_endproc + 1308 .LFE138: + 1310 .section .text.HAL_DMA_UnRegisterCallback,"ax",%progbits + 1311 .align 1 + 1312 .global HAL_DMA_UnRegisterCallback + 1313 .syntax unified + 1314 .thumb + 1315 .thumb_func + 1317 HAL_DMA_UnRegisterCallback: + 1318 .LVL79: + 1319 .LFB139: + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1320 .loc 1 713 1 is_stmt 1 view -0 + 1321 .cfi_startproc + 1322 @ args = 0, pretend = 0, frame = 0 + 1323 @ frame_needed = 0, uses_anonymous_args = 0 + 1324 @ link register save eliminated. + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1325 .loc 1 713 1 is_stmt 0 view .LVU504 + 1326 0000 0346 mov r3, r0 + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1327 .loc 1 714 3 is_stmt 1 view .LVU505 + 1328 .LVL80: + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1329 .loc 1 717 3 view .LVU506 + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1330 .loc 1 717 3 view .LVU507 + 1331 0002 90F82020 ldrb r2, [r0, #32] @ zero_extendqisi2 + 1332 0006 012A cmp r2, #1 + 1333 0008 25D0 beq .L92 + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1334 .loc 1 717 3 discriminator 2 view .LVU508 + 1335 000a 0122 movs r2, #1 + 1336 000c 80F82020 strb r2, [r0, #32] + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1337 .loc 1 717 3 discriminator 2 view .LVU509 + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1338 .loc 1 719 3 discriminator 2 view .LVU510 + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1339 .loc 1 719 33 is_stmt 0 discriminator 2 view .LVU511 + 1340 0010 90F82100 ldrb r0, [r0, #33] @ zero_extendqisi2 + 1341 .LVL81: + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1342 .loc 1 719 5 discriminator 2 view .LVU512 + 1343 0014 9042 cmp r0, r2 + 1344 0016 04D0 beq .L95 + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + ARM GAS /tmp/ccaRdTju.s page 48 + + + 1345 .loc 1 753 12 view .LVU513 + 1346 0018 0120 movs r0, #1 + 1347 .L85: + 1348 .LVL82: + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1349 .loc 1 757 3 is_stmt 1 view .LVU514 + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1350 .loc 1 757 3 view .LVU515 + 1351 001a 0022 movs r2, #0 + 1352 001c 83F82020 strb r2, [r3, #32] + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1353 .loc 1 757 3 view .LVU516 + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1354 .loc 1 759 3 view .LVU517 + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1355 .loc 1 759 10 is_stmt 0 view .LVU518 + 1356 0020 7047 bx lr + 1357 .LVL83: + 1358 .L95: + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1359 .loc 1 721 5 is_stmt 1 view .LVU519 + 1360 0022 0429 cmp r1, #4 + 1361 0024 F9D8 bhi .L85 + 1362 0026 DFE801F0 tbb [pc, r1] + 1363 .L87: + 1364 002a 03 .byte (.L91-.L87)/2 + 1365 002b 07 .byte (.L90-.L87)/2 + 1366 002c 0A .byte (.L89-.L87)/2 + 1367 002d 0D .byte (.L88-.L87)/2 + 1368 002e 10 .byte (.L86-.L87)/2 + 1369 002f 00 .p2align 1 + 1370 .L91: + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1371 .loc 1 724 12 view .LVU520 + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1372 .loc 1 724 35 is_stmt 0 view .LVU521 + 1373 0030 0022 movs r2, #0 + 1374 0032 9A62 str r2, [r3, #40] + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1375 .loc 1 725 12 is_stmt 1 view .LVU522 + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1376 .loc 1 714 21 is_stmt 0 view .LVU523 + 1377 0034 0846 mov r0, r1 + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1378 .loc 1 725 12 view .LVU524 + 1379 0036 F0E7 b .L85 + 1380 .L90: + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1381 .loc 1 728 12 is_stmt 1 view .LVU525 + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1382 .loc 1 728 39 is_stmt 0 view .LVU526 + 1383 0038 0020 movs r0, #0 + 1384 003a D862 str r0, [r3, #44] + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1385 .loc 1 729 12 is_stmt 1 view .LVU527 + 1386 003c EDE7 b .L85 + 1387 .L89: + ARM GAS /tmp/ccaRdTju.s page 49 + + + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1388 .loc 1 732 12 view .LVU528 + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1389 .loc 1 732 36 is_stmt 0 view .LVU529 + 1390 003e 0020 movs r0, #0 + 1391 0040 1863 str r0, [r3, #48] + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1392 .loc 1 733 12 is_stmt 1 view .LVU530 + 1393 0042 EAE7 b .L85 + 1394 .L88: + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1395 .loc 1 736 12 view .LVU531 + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1396 .loc 1 736 36 is_stmt 0 view .LVU532 + 1397 0044 0020 movs r0, #0 + 1398 0046 5863 str r0, [r3, #52] + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1399 .loc 1 737 12 is_stmt 1 view .LVU533 + 1400 0048 E7E7 b .L85 + 1401 .L86: + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 1402 .loc 1 740 12 view .LVU534 + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 1403 .loc 1 740 35 is_stmt 0 view .LVU535 + 1404 004a 0020 movs r0, #0 + 1405 004c 9862 str r0, [r3, #40] + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 1406 .loc 1 741 12 is_stmt 1 view .LVU536 + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 1407 .loc 1 741 39 is_stmt 0 view .LVU537 + 1408 004e D862 str r0, [r3, #44] + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 1409 .loc 1 742 12 is_stmt 1 view .LVU538 + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 1410 .loc 1 742 36 is_stmt 0 view .LVU539 + 1411 0050 1863 str r0, [r3, #48] + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1412 .loc 1 743 12 is_stmt 1 view .LVU540 + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1413 .loc 1 743 36 is_stmt 0 view .LVU541 + 1414 0052 5863 str r0, [r3, #52] + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1415 .loc 1 744 12 is_stmt 1 view .LVU542 + 1416 0054 E1E7 b .L85 + 1417 .LVL84: + 1418 .L92: + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1419 .loc 1 717 3 is_stmt 0 view .LVU543 + 1420 0056 0220 movs r0, #2 + 1421 .LVL85: + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1422 .loc 1 760 1 view .LVU544 + 1423 0058 7047 bx lr + 1424 .cfi_endproc + 1425 .LFE139: + 1427 .section .text.HAL_DMA_GetState,"ax",%progbits + 1428 .align 1 + ARM GAS /tmp/ccaRdTju.s page 50 + + + 1429 .global HAL_DMA_GetState + 1430 .syntax unified + 1431 .thumb + 1432 .thumb_func + 1434 HAL_DMA_GetState: + 1435 .LVL86: + 1436 .LFB140: + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return hdma->State; + 1437 .loc 1 789 1 is_stmt 1 view -0 + 1438 .cfi_startproc + 1439 @ args = 0, pretend = 0, frame = 0 + 1440 @ frame_needed = 0, uses_anonymous_args = 0 + 1441 @ link register save eliminated. + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1442 .loc 1 790 3 view .LVU546 + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1443 .loc 1 791 1 is_stmt 0 view .LVU547 + 1444 0000 90F82100 ldrb r0, [r0, #33] @ zero_extendqisi2 + 1445 .LVL87: + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1446 .loc 1 791 1 view .LVU548 + 1447 0004 7047 bx lr + 1448 .cfi_endproc + 1449 .LFE140: + 1451 .section .text.HAL_DMA_GetError,"ax",%progbits + 1452 .align 1 + 1453 .global HAL_DMA_GetError + 1454 .syntax unified + 1455 .thumb + 1456 .thumb_func + 1458 HAL_DMA_GetError: + 1459 .LVL88: + 1460 .LFB141: + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return hdma->ErrorCode; + 1461 .loc 1 800 1 is_stmt 1 view -0 + 1462 .cfi_startproc + 1463 @ args = 0, pretend = 0, frame = 0 + 1464 @ frame_needed = 0, uses_anonymous_args = 0 + 1465 @ link register save eliminated. + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1466 .loc 1 801 3 view .LVU550 + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1467 .loc 1 801 14 is_stmt 0 view .LVU551 + 1468 0000 806B ldr r0, [r0, #56] + 1469 .LVL89: + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1470 .loc 1 802 1 view .LVU552 + 1471 0002 7047 bx lr + 1472 .cfi_endproc + 1473 .LFE141: + 1475 .text + 1476 .Letext0: + 1477 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1478 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1479 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1480 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1481 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + ARM GAS /tmp/ccaRdTju.s page 51 + + + 1482 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 1483 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccaRdTju.s page 52 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_dma.c + /tmp/ccaRdTju.s:21 .text.DMA_SetConfig:0000000000000000 $t + /tmp/ccaRdTju.s:26 .text.DMA_SetConfig:0000000000000000 DMA_SetConfig + /tmp/ccaRdTju.s:97 .text.DMA_CalcBaseAndBitshift:0000000000000000 $t + /tmp/ccaRdTju.s:102 .text.DMA_CalcBaseAndBitshift:0000000000000000 DMA_CalcBaseAndBitshift + /tmp/ccaRdTju.s:156 .text.DMA_CalcBaseAndBitshift:0000000000000034 $d + /tmp/ccaRdTju.s:166 .text.HAL_DMA_Init:0000000000000000 $t + /tmp/ccaRdTju.s:172 .text.HAL_DMA_Init:0000000000000000 HAL_DMA_Init + /tmp/ccaRdTju.s:280 .text.HAL_DMA_DeInit:0000000000000000 $t + /tmp/ccaRdTju.s:286 .text.HAL_DMA_DeInit:0000000000000000 HAL_DMA_DeInit + /tmp/ccaRdTju.s:390 .text.HAL_DMA_Start:0000000000000000 $t + /tmp/ccaRdTju.s:396 .text.HAL_DMA_Start:0000000000000000 HAL_DMA_Start + /tmp/ccaRdTju.s:488 .text.HAL_DMA_Start_IT:0000000000000000 $t + /tmp/ccaRdTju.s:494 .text.HAL_DMA_Start_IT:0000000000000000 HAL_DMA_Start_IT + /tmp/ccaRdTju.s:618 .text.HAL_DMA_Abort:0000000000000000 $t + /tmp/ccaRdTju.s:624 .text.HAL_DMA_Abort:0000000000000000 HAL_DMA_Abort + /tmp/ccaRdTju.s:699 .text.HAL_DMA_Abort_IT:0000000000000000 $t + /tmp/ccaRdTju.s:705 .text.HAL_DMA_Abort_IT:0000000000000000 HAL_DMA_Abort_IT + /tmp/ccaRdTju.s:796 .text.HAL_DMA_PollForTransfer:0000000000000000 $t + /tmp/ccaRdTju.s:802 .text.HAL_DMA_PollForTransfer:0000000000000000 HAL_DMA_PollForTransfer + /tmp/ccaRdTju.s:1015 .text.HAL_DMA_IRQHandler:0000000000000000 $t + /tmp/ccaRdTju.s:1021 .text.HAL_DMA_IRQHandler:0000000000000000 HAL_DMA_IRQHandler + /tmp/ccaRdTju.s:1205 .text.HAL_DMA_RegisterCallback:0000000000000000 $t + /tmp/ccaRdTju.s:1211 .text.HAL_DMA_RegisterCallback:0000000000000000 HAL_DMA_RegisterCallback + /tmp/ccaRdTju.s:1261 .text.HAL_DMA_RegisterCallback:000000000000002a $d + /tmp/ccaRdTju.s:1265 .text.HAL_DMA_RegisterCallback:000000000000002e $t + /tmp/ccaRdTju.s:1311 .text.HAL_DMA_UnRegisterCallback:0000000000000000 $t + /tmp/ccaRdTju.s:1317 .text.HAL_DMA_UnRegisterCallback:0000000000000000 HAL_DMA_UnRegisterCallback + /tmp/ccaRdTju.s:1364 .text.HAL_DMA_UnRegisterCallback:000000000000002a $d + /tmp/ccaRdTju.s:1428 .text.HAL_DMA_GetState:0000000000000000 $t + /tmp/ccaRdTju.s:1434 .text.HAL_DMA_GetState:0000000000000000 HAL_DMA_GetState + /tmp/ccaRdTju.s:1452 .text.HAL_DMA_GetError:0000000000000000 $t + /tmp/ccaRdTju.s:1458 .text.HAL_DMA_GetError:0000000000000000 HAL_DMA_GetError + /tmp/ccaRdTju.s:1369 .text.HAL_DMA_UnRegisterCallback:000000000000002f $d + /tmp/ccaRdTju.s:1369 .text.HAL_DMA_UnRegisterCallback:0000000000000030 $t + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_dma.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_dma.o new file mode 100644 index 0000000000000000000000000000000000000000..47e1b93f17700b3dd8007bcbc8d475e752a556a6 GIT binary patch literal 16136 zcmd5@dwg6~wch(YX7Xy1W|Fo^)Al53X`#&|X+!BFrFk_?+O$oR6iQK&$z;+AojjaO zOW{|r*n)6Df8L8IXtgM!i2kk!qE|&l9)kCx7B2$o^$Na%3R+RG_1XJ<`|LAwG7ZZ8 z@9y@TZ?Co2UTf{O*WPE(naNwXbazN8g;%6lAu^N@hu5hVyHUXkae+8r)PF`UwG*Fg ze&Rr4(27R~+v3G5?Nes_&OtN&y}|m2C%2mM_o4pX!86lFykPtLTJv7W-yUku-}d1@ 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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_exti.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_exti.lst new file mode 100644 index 0000000..a4e4499 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_exti.lst @@ -0,0 +1,1819 @@ +ARM GAS /tmp/ccQLKAuM.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_exti.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c" + 20 .section .text.HAL_EXTI_SetConfigLine,"ax",%progbits + 21 .align 1 + 22 .global HAL_EXTI_SetConfigLine + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_EXTI_SetConfigLine: + 28 .LVL0: + 29 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @file stm32f3xx_hal_exti.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief EXTI HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + IO operation functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @verbatim + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ============================================================================== + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ##### EXTI Peripheral features ##### + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ============================================================================== + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** [..] + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Each Exti line can be configured within this driver. + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Exti line can be configured in 3 different modes + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Interrupt + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Event + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Both of them + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Configurable Exti lines can be configured with 3 different triggers + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Rising + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Falling + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Both of them + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) When set in interrupt mode, configurable Exti lines have two different + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** interrupts pending registers which allow to distinguish which transition + ARM GAS /tmp/ccQLKAuM.s page 2 + + + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** occurs: + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Rising edge pending interrupt + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Falling + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** be selected through multiplexer. + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ##### How to use this driver ##### + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ============================================================================== + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** [..] + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Choose the interrupt line number by setting "Line" member from + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** EXTI_ConfigTypeDef structure. + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Configure the interrupt and/or event mode using "Mode" member from + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** EXTI_ConfigTypeDef structure. + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) For configurable lines, configure rising and/or falling trigger + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** "Trigger" member from EXTI_ConfigTypeDef structure. + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** member from GPIO_InitTypeDef structure. + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Get current Exti configuration of a dedicated line using + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_EXTI_GetConfigLine(). + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide exiting handle as parameter. + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide exiting handle as parameter. + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide exiting handle as first parameter. + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide which callback will be registered using one value from + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** EXTI_CallbackIDTypeDef. + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide callback function pointer. + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @endverbatim + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ****************************************************************************** + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @attention + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *

    © Copyright (c) 2019 STMicroelectronics. + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * All rights reserved.

    + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This software component is licensed by ST under BSD 3-Clause license, + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * the "License"; You may not use this file except in compliance with the + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * License. You may obtain a copy of the License at: + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * opensource.org/licenses/BSD-3-Clause + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ****************************************************************************** + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Includes ------------------------------------------------------------------*/ + ARM GAS /tmp/ccQLKAuM.s page 3 + + + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #include "stm32f3xx_hal.h" + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup STM32F3xx_HAL_Driver + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup EXTI + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** MISRA C:2012 deviation rule has been granted for following rule: + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * of bounds [0,3] in following API : + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * HAL_EXTI_SetConfigLine + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * HAL_EXTI_GetConfigLine + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * HAL_EXTI_ClearConfigLine + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #ifdef HAL_EXTI_MODULE_ENABLED + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private typedef -----------------------------------------------------------*/ + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private defines -----------------------------------------------------------*/ + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @defgroup EXTI_Private_Constants EXTI Private Constants + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between CPU IMR/EMR registers * + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling conf + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @} + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private macros ------------------------------------------------------------*/ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private variables ---------------------------------------------------------*/ + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private function prototypes -----------------------------------------------*/ + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Exported functions --------------------------------------------------------*/ + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group1 + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Configuration functions + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @verbatim + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** =============================================================================== + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ##### Configuration functions ##### + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** =============================================================================== + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @endverbatim + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Set configuration of a dedicated Exti line. + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param pExtiConfig Pointer on EXTI configuration to be set. + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + ARM GAS /tmp/ccQLKAuM.s page 4 + + + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 30 .loc 1 145 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 @ link register save eliminated. + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 35 .loc 1 146 3 view .LVU1 + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 36 .loc 1 147 3 view .LVU2 + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t linepos; + 37 .loc 1 148 3 view .LVU3 + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 38 .loc 1 149 3 view .LVU4 + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 39 .loc 1 150 3 view .LVU5 + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check null pointer */ + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 40 .loc 1 153 3 view .LVU6 + 41 .loc 1 153 6 is_stmt 0 view .LVU7 + 42 0000 0028 cmp r0, #0 + 43 0002 5ED0 beq .L12 + 44 .loc 1 153 23 discriminator 1 view .LVU8 + 45 0004 0029 cmp r1, #0 + 46 0006 5ED0 beq .L13 + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 47 .loc 1 145 1 view .LVU9 + 48 0008 F0B4 push {r4, r5, r6, r7} + 49 .cfi_def_cfa_offset 16 + 50 .cfi_offset 4, -16 + 51 .cfi_offset 5, -12 + 52 .cfi_offset 6, -8 + 53 .cfi_offset 7, -4 + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_ERROR; + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check parameters */ + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + 54 .loc 1 159 3 is_stmt 1 view .LVU10 + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + 55 .loc 1 160 3 view .LVU11 + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Assign line number to handle */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** hexti->Line = pExtiConfig->Line; + 56 .loc 1 163 3 view .LVU12 + 57 .loc 1 163 28 is_stmt 0 view .LVU13 + 58 000a 0A68 ldr r2, [r1] + 59 .loc 1 163 15 view .LVU14 + 60 000c 0260 str r2, [r0] + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Compute line register offset and line mask */ + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 61 .loc 1 166 3 is_stmt 1 view .LVU15 + 62 .loc 1 166 10 is_stmt 0 view .LVU16 + ARM GAS /tmp/ccQLKAuM.s page 5 + + + 63 000e C2F30043 ubfx r3, r2, #16, #1 + 64 .LVL1: + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 65 .loc 1 167 3 is_stmt 1 view .LVU17 + 66 .loc 1 167 11 is_stmt 0 view .LVU18 + 67 0012 02F01F04 and r4, r2, #31 + 68 .LVL2: + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << linepos); + 69 .loc 1 168 3 is_stmt 1 view .LVU19 + 70 .loc 1 168 12 is_stmt 0 view .LVU20 + 71 0016 0120 movs r0, #1 + 72 .LVL3: + 73 .loc 1 168 12 view .LVU21 + 74 0018 A040 lsls r0, r0, r4 + 75 .LVL4: + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure triggers for configurable lines */ + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + 76 .loc 1 171 3 is_stmt 1 view .LVU22 + 77 .loc 1 171 6 is_stmt 0 view .LVU23 + 78 001a 12F0007F tst r2, #33554432 + 79 001e 1BD0 beq .L3 + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + 80 .loc 1 173 5 is_stmt 1 view .LVU24 + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure rising trigger */ + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + 81 .loc 1 176 5 view .LVU25 + 82 .loc 1 176 28 is_stmt 0 view .LVU26 + 83 0020 4FEA431C lsl ip, r3, #5 + 84 .loc 1 176 13 view .LVU27 + 85 0024 294F ldr r7, .L19 + 86 .LVL5: + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 87 .loc 1 177 5 is_stmt 1 view .LVU28 + 88 .loc 1 177 12 is_stmt 0 view .LVU29 + 89 0026 5CF80750 ldr r5, [ip, r7] + 90 .LVL6: + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Mask or set line */ + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + 91 .loc 1 180 5 is_stmt 1 view .LVU30 + 92 .loc 1 180 21 is_stmt 0 view .LVU31 + 93 002a 8E68 ldr r6, [r1, #8] + 94 .loc 1 180 8 view .LVU32 + 95 002c 16F0010F tst r6, #1 + 96 0030 29D0 beq .L4 + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= maskline; + 97 .loc 1 182 7 is_stmt 1 view .LVU33 + 98 .loc 1 182 14 is_stmt 0 view .LVU34 + 99 0032 0543 orrs r5, r5, r0 + 100 .LVL7: + 101 .L5: + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + ARM GAS /tmp/ccQLKAuM.s page 6 + + + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline; + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store rising trigger mode */ + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 102 .loc 1 190 5 is_stmt 1 view .LVU35 + 103 .loc 1 190 14 is_stmt 0 view .LVU36 + 104 0034 4CF80750 str r5, [ip, r7] + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure falling trigger */ + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + 105 .loc 1 193 5 is_stmt 1 view .LVU37 + 106 .loc 1 193 13 is_stmt 0 view .LVU38 + 107 0038 254E ldr r6, .L19+4 + 108 .LVL8: + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 109 .loc 1 194 5 is_stmt 1 view .LVU39 + 110 .loc 1 194 12 is_stmt 0 view .LVU40 + 111 003a 5CF80650 ldr r5, [ip, r6] + 112 .LVL9: + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Mask or set line */ + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + 113 .loc 1 197 5 is_stmt 1 view .LVU41 + 114 .loc 1 197 8 is_stmt 0 view .LVU42 + 115 003e 8F68 ldr r7, [r1, #8] + 116 0040 17F0020F tst r7, #2 + 117 0044 22D0 beq .L6 + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= maskline; + 118 .loc 1 199 7 is_stmt 1 view .LVU43 + 119 .loc 1 199 14 is_stmt 0 view .LVU44 + 120 0046 0543 orrs r5, r5, r0 + 121 .LVL10: + 122 .L7: + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline; + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store falling trigger mode */ + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 123 .loc 1 207 5 is_stmt 1 view .LVU45 + 124 .loc 1 207 14 is_stmt 0 view .LVU46 + 125 0048 4CF80650 str r5, [ip, r6] + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure gpio port selection in case of gpio exti line */ + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 126 .loc 1 210 5 is_stmt 1 view .LVU47 + 127 .loc 1 210 28 is_stmt 0 view .LVU48 + 128 004c 0D68 ldr r5, [r1] + 129 .LVL11: + 130 .loc 1 210 28 view .LVU49 + 131 004e 05F0C06C and ip, r5, #100663296 + 132 .LVL12: + ARM GAS /tmp/ccQLKAuM.s page 7 + + + 133 .loc 1 210 8 view .LVU50 + 134 0052 BCF1C06F cmp ip, #100663296 + 135 0056 1CD0 beq .L18 + 136 .LVL13: + 137 .L3: + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure interrupt mode : read current mode */ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + 138 .loc 1 223 3 is_stmt 1 view .LVU51 + 139 .loc 1 223 25 is_stmt 0 view .LVU52 + 140 0058 5B01 lsls r3, r3, #5 + 141 .LVL14: + 142 .loc 1 223 11 view .LVU53 + 143 005a 03F18042 add r2, r3, #1073741824 + 144 005e 02F58232 add r2, r2, #66560 + 145 .LVL15: + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 146 .loc 1 224 3 is_stmt 1 view .LVU54 + 147 .loc 1 224 10 is_stmt 0 view .LVU55 + 148 0062 1468 ldr r4, [r2] + 149 .LVL16: + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Mask or set line */ + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + 150 .loc 1 227 3 is_stmt 1 view .LVU56 + 151 .loc 1 227 6 is_stmt 0 view .LVU57 + 152 0064 4D68 ldr r5, [r1, #4] + 153 0066 15F0010F tst r5, #1 + 154 006a 24D0 beq .L8 + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= maskline; + 155 .loc 1 229 5 is_stmt 1 view .LVU58 + 156 .loc 1 229 12 is_stmt 0 view .LVU59 + 157 006c 0443 orrs r4, r4, r0 + 158 .LVL17: + 159 .L9: + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline; + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store interrupt mode */ + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 160 .loc 1 237 3 is_stmt 1 view .LVU60 + 161 .loc 1 237 12 is_stmt 0 view .LVU61 + 162 006e 1460 str r4, [r2] + ARM GAS /tmp/ccQLKAuM.s page 8 + + + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure event mode : read current mode */ + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + 163 .loc 1 240 3 is_stmt 1 view .LVU62 + 164 .loc 1 240 11 is_stmt 0 view .LVU63 + 165 0070 184C ldr r4, .L19+8 + 166 .LVL18: + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 167 .loc 1 241 3 is_stmt 1 view .LVU64 + 168 .loc 1 241 10 is_stmt 0 view .LVU65 + 169 0072 1A59 ldr r2, [r3, r4] + 170 .LVL19: + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Mask or set line */ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + 171 .loc 1 244 3 is_stmt 1 view .LVU66 + 172 .loc 1 244 19 is_stmt 0 view .LVU67 + 173 0074 4968 ldr r1, [r1, #4] + 174 .LVL20: + 175 .loc 1 244 6 view .LVU68 + 176 0076 11F0020F tst r1, #2 + 177 007a 1FD0 beq .L10 + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= maskline; + 178 .loc 1 246 5 is_stmt 1 view .LVU69 + 179 .loc 1 246 12 is_stmt 0 view .LVU70 + 180 007c 0243 orrs r2, r2, r0 + 181 .LVL21: + 182 .L11: + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline; + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store event mode */ + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 183 .loc 1 254 3 is_stmt 1 view .LVU71 + 184 .loc 1 254 12 is_stmt 0 view .LVU72 + 185 007e 1A51 str r2, [r3, r4] + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_OK; + 186 .loc 1 256 3 is_stmt 1 view .LVU73 + 187 .loc 1 256 10 is_stmt 0 view .LVU74 + 188 0080 0020 movs r0, #0 + 189 .LVL22: + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 190 .loc 1 257 1 view .LVU75 + 191 0082 F0BC pop {r4, r5, r6, r7} + 192 .cfi_remember_state + 193 .cfi_restore 7 + 194 .cfi_restore 6 + 195 .cfi_restore 5 + 196 .cfi_restore 4 + 197 .cfi_def_cfa_offset 0 + 198 .LVL23: + 199 .loc 1 257 1 view .LVU76 + ARM GAS /tmp/ccQLKAuM.s page 9 + + + 200 0084 7047 bx lr + 201 .LVL24: + 202 .L4: + 203 .cfi_restore_state + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 204 .loc 1 186 7 is_stmt 1 view .LVU77 + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 205 .loc 1 186 14 is_stmt 0 view .LVU78 + 206 0086 25EA0005 bic r5, r5, r0 + 207 .LVL25: + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 208 .loc 1 186 14 view .LVU79 + 209 008a D3E7 b .L5 + 210 .LVL26: + 211 .L6: + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 212 .loc 1 203 7 is_stmt 1 view .LVU80 + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 213 .loc 1 203 14 is_stmt 0 view .LVU81 + 214 008c 25EA0005 bic r5, r5, r0 + 215 .LVL27: + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 216 .loc 1 203 14 view .LVU82 + 217 0090 DAE7 b .L7 + 218 .LVL28: + 219 .L18: + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 220 .loc 1 212 7 is_stmt 1 view .LVU83 + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 221 .loc 1 213 7 view .LVU84 + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 222 .loc 1 215 7 view .LVU85 + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 223 .loc 1 215 39 is_stmt 0 view .LVU86 + 224 0092 A408 lsrs r4, r4, #2 + 225 .LVL29: + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 226 .loc 1 215 14 view .LVU87 + 227 0094 104F ldr r7, .L19+12 + 228 0096 0234 adds r4, r4, #2 + 229 0098 57F82460 ldr r6, [r7, r4, lsl #2] + 230 .LVL30: + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 231 .loc 1 216 7 is_stmt 1 view .LVU88 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 232 .loc 1 216 80 is_stmt 0 view .LVU89 + 233 009c 02F00302 and r2, r2, #3 + 234 .LVL31: + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 235 .loc 1 216 69 view .LVU90 + 236 00a0 9200 lsls r2, r2, #2 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 237 .loc 1 216 40 view .LVU91 + 238 00a2 0F25 movs r5, #15 + 239 00a4 9540 lsls r5, r5, r2 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 240 .loc 1 216 14 view .LVU92 + ARM GAS /tmp/ccQLKAuM.s page 10 + + + 241 00a6 26EA0506 bic r6, r6, r5 + 242 .LVL32: + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 243 .loc 1 217 7 is_stmt 1 view .LVU93 + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 244 .loc 1 217 29 is_stmt 0 view .LVU94 + 245 00aa CD68 ldr r5, [r1, #12] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 246 .loc 1 217 39 view .LVU95 + 247 00ac 9540 lsls r5, r5, r2 + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 248 .loc 1 217 14 view .LVU96 + 249 00ae 3543 orrs r5, r5, r6 + 250 .LVL33: + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 251 .loc 1 218 7 is_stmt 1 view .LVU97 + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 252 .loc 1 218 37 is_stmt 0 view .LVU98 + 253 00b0 47F82450 str r5, [r7, r4, lsl #2] + 254 00b4 D0E7 b .L3 + 255 .LVL34: + 256 .L8: + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 257 .loc 1 233 5 is_stmt 1 view .LVU99 + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 258 .loc 1 233 12 is_stmt 0 view .LVU100 + 259 00b6 24EA0004 bic r4, r4, r0 + 260 .LVL35: + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 261 .loc 1 233 12 view .LVU101 + 262 00ba D8E7 b .L9 + 263 .LVL36: + 264 .L10: + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 265 .loc 1 250 5 is_stmt 1 view .LVU102 + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 266 .loc 1 250 12 is_stmt 0 view .LVU103 + 267 00bc 22EA0002 bic r2, r2, r0 + 268 .LVL37: + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 269 .loc 1 250 12 view .LVU104 + 270 00c0 DDE7 b .L11 + 271 .LVL38: + 272 .L12: + 273 .cfi_def_cfa_offset 0 + 274 .cfi_restore 4 + 275 .cfi_restore 5 + 276 .cfi_restore 6 + 277 .cfi_restore 7 + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 278 .loc 1 155 12 view .LVU105 + 279 00c2 0120 movs r0, #1 + 280 .LVL39: + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 281 .loc 1 155 12 view .LVU106 + 282 00c4 7047 bx lr + 283 .LVL40: + ARM GAS /tmp/ccQLKAuM.s page 11 + + + 284 .L13: + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 285 .loc 1 155 12 view .LVU107 + 286 00c6 0120 movs r0, #1 + 287 .LVL41: + 288 .loc 1 257 1 view .LVU108 + 289 00c8 7047 bx lr + 290 .L20: + 291 00ca 00BF .align 2 + 292 .L19: + 293 00cc 08040140 .word 1073808392 + 294 00d0 0C040140 .word 1073808396 + 295 00d4 04040140 .word 1073808388 + 296 00d8 00000140 .word 1073807360 + 297 .cfi_endproc + 298 .LFE130: + 300 .section .text.HAL_EXTI_GetConfigLine,"ax",%progbits + 301 .align 1 + 302 .global HAL_EXTI_GetConfigLine + 303 .syntax unified + 304 .thumb + 305 .thumb_func + 307 HAL_EXTI_GetConfigLine: + 308 .LVL42: + 309 .LFB131: + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Get configuration of a dedicated Exti line. + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param pExtiConfig Pointer on structure to store Exti configuration. + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 310 .loc 1 266 1 is_stmt 1 view -0 + 311 .cfi_startproc + 312 @ args = 0, pretend = 0, frame = 0 + 313 @ frame_needed = 0, uses_anonymous_args = 0 + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 314 .loc 1 267 3 view .LVU110 + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 315 .loc 1 268 3 view .LVU111 + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t linepos; + 316 .loc 1 269 3 view .LVU112 + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 317 .loc 1 270 3 view .LVU113 + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 318 .loc 1 271 3 view .LVU114 + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check null pointer */ + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 319 .loc 1 274 3 view .LVU115 + 320 .loc 1 274 6 is_stmt 0 view .LVU116 + 321 0000 0028 cmp r0, #0 + 322 0002 4DD0 beq .L28 + 323 .loc 1 274 23 discriminator 1 view .LVU117 + 324 0004 0029 cmp r1, #0 + ARM GAS /tmp/ccQLKAuM.s page 12 + + + 325 0006 4DD0 beq .L29 + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 326 .loc 1 266 1 view .LVU118 + 327 0008 10B5 push {r4, lr} + 328 .cfi_def_cfa_offset 8 + 329 .cfi_offset 4, -8 + 330 .cfi_offset 14, -4 + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_ERROR; + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check the parameter */ + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 331 .loc 1 280 3 is_stmt 1 view .LVU119 + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store handle line number to configuration structure */ + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Line = hexti->Line; + 332 .loc 1 283 3 view .LVU120 + 333 .loc 1 283 28 is_stmt 0 view .LVU121 + 334 000a 0368 ldr r3, [r0] + 335 .loc 1 283 21 view .LVU122 + 336 000c 0B60 str r3, [r1] + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 337 .loc 1 286 3 is_stmt 1 view .LVU123 + 338 .loc 1 286 10 is_stmt 0 view .LVU124 + 339 000e C3F30040 ubfx r0, r3, #16, #1 + 340 .LVL43: + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 341 .loc 1 287 3 is_stmt 1 view .LVU125 + 342 .loc 1 287 11 is_stmt 0 view .LVU126 + 343 0012 03F01F0E and lr, r3, #31 + 344 .LVL44: + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << linepos); + 345 .loc 1 288 3 is_stmt 1 view .LVU127 + 346 .loc 1 288 12 is_stmt 0 view .LVU128 + 347 0016 0122 movs r2, #1 + 348 0018 02FA0EF2 lsl r2, r2, lr + 349 .LVL45: + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 1] Get core mode : interrupt */ + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + 350 .loc 1 291 3 is_stmt 1 view .LVU129 + 351 .loc 1 291 25 is_stmt 0 view .LVU130 + 352 001c 4001 lsls r0, r0, #5 + 353 .LVL46: + 354 .loc 1 291 11 view .LVU131 + 355 001e 00F1804C add ip, r0, #1073741824 + 356 0022 0CF5823C add ip, ip, #66560 + 357 .LVL47: + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 358 .loc 1 292 3 is_stmt 1 view .LVU132 + 359 .loc 1 292 10 is_stmt 0 view .LVU133 + 360 0026 DCF80040 ldr r4, [ip] + 361 .LVL48: + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + ARM GAS /tmp/ccQLKAuM.s page 13 + + + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if selected line is enable */ + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 362 .loc 1 295 3 is_stmt 1 view .LVU134 + 363 .loc 1 295 6 is_stmt 0 view .LVU135 + 364 002a 2242 tst r2, r4 + 365 002c 24D0 beq .L23 + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + 366 .loc 1 297 5 is_stmt 1 view .LVU136 + 367 .loc 1 297 23 is_stmt 0 view .LVU137 + 368 002e 0124 movs r4, #1 + 369 .LVL49: + 370 .loc 1 297 23 view .LVU138 + 371 0030 4C60 str r4, [r1, #4] + 372 .L24: + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_NONE; + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get event mode */ + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + 373 .loc 1 305 3 is_stmt 1 view .LVU139 + 374 .loc 1 305 11 is_stmt 0 view .LVU140 + 375 0032 1E4C ldr r4, .L37 + 376 .LVL50: + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 377 .loc 1 306 3 is_stmt 1 view .LVU141 + 378 .loc 1 306 10 is_stmt 0 view .LVU142 + 379 0034 0459 ldr r4, [r0, r4] + 380 .LVL51: + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if selected line is enable */ + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 381 .loc 1 309 3 is_stmt 1 view .LVU143 + 382 .loc 1 309 6 is_stmt 0 view .LVU144 + 383 0036 2242 tst r2, r4 + 384 0038 03D0 beq .L25 + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Mode |= EXTI_MODE_EVENT; + 385 .loc 1 311 5 is_stmt 1 view .LVU145 + 386 .loc 1 311 16 is_stmt 0 view .LVU146 + 387 003a 4C68 ldr r4, [r1, #4] + 388 .LVL52: + 389 .loc 1 311 23 view .LVU147 + 390 003c 44F00204 orr r4, r4, #2 + 391 0040 4C60 str r4, [r1, #4] + 392 .L25: + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get default Trigger and GPIOSel configuration */ + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + 393 .loc 1 315 3 is_stmt 1 view .LVU148 + 394 .loc 1 315 24 is_stmt 0 view .LVU149 + 395 0042 0024 movs r4, #0 + 396 0044 8C60 str r4, [r1, #8] + ARM GAS /tmp/ccQLKAuM.s page 14 + + + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = 0x00u; + 397 .loc 1 316 3 is_stmt 1 view .LVU150 + 398 .loc 1 316 24 is_stmt 0 view .LVU151 + 399 0046 CC60 str r4, [r1, #12] + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 2] Get trigger for configurable lines : rising */ + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + 400 .loc 1 319 3 is_stmt 1 view .LVU152 + 401 .loc 1 319 6 is_stmt 0 view .LVU153 + 402 0048 13F0007F tst r3, #33554432 + 403 004c 2CD0 beq .L30 + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + 404 .loc 1 321 5 is_stmt 1 view .LVU154 + 405 .loc 1 321 13 is_stmt 0 view .LVU155 + 406 004e 184C ldr r4, .L37+4 + 407 .LVL53: + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 408 .loc 1 322 5 is_stmt 1 view .LVU156 + 409 .loc 1 322 12 is_stmt 0 view .LVU157 + 410 0050 0459 ldr r4, [r0, r4] + 411 .LVL54: + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 412 .loc 1 325 5 is_stmt 1 view .LVU158 + 413 .loc 1 325 8 is_stmt 0 view .LVU159 + 414 0052 2242 tst r2, r4 + 415 0054 01D0 beq .L26 + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + 416 .loc 1 327 7 is_stmt 1 view .LVU160 + 417 .loc 1 327 28 is_stmt 0 view .LVU161 + 418 0056 0124 movs r4, #1 + 419 .LVL55: + 420 .loc 1 327 28 view .LVU162 + 421 0058 8C60 str r4, [r1, #8] + 422 .L26: + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get falling configuration */ + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + 423 .loc 1 331 5 is_stmt 1 view .LVU163 + 424 .loc 1 331 13 is_stmt 0 view .LVU164 + 425 005a 164C ldr r4, .L37+8 + 426 .LVL56: + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 427 .loc 1 332 5 is_stmt 1 view .LVU165 + 428 .loc 1 332 12 is_stmt 0 view .LVU166 + 429 005c 0059 ldr r0, [r0, r4] + 430 .LVL57: + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 431 .loc 1 335 5 is_stmt 1 view .LVU167 + 432 .loc 1 335 8 is_stmt 0 view .LVU168 + 433 005e 0242 tst r2, r0 + ARM GAS /tmp/ccQLKAuM.s page 15 + + + 434 0060 03D0 beq .L27 + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + 435 .loc 1 337 7 is_stmt 1 view .LVU169 + 436 .loc 1 337 18 is_stmt 0 view .LVU170 + 437 0062 8A68 ldr r2, [r1, #8] + 438 .LVL58: + 439 .loc 1 337 28 view .LVU171 + 440 0064 42F00202 orr r2, r2, #2 + 441 0068 8A60 str r2, [r1, #8] + 442 .L27: + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 443 .loc 1 341 5 is_stmt 1 view .LVU172 + 444 .loc 1 341 28 is_stmt 0 view .LVU173 + 445 006a 03F0C063 and r3, r3, #100663296 + 446 .LVL59: + 447 .loc 1 341 8 view .LVU174 + 448 006e B3F1C06F cmp r3, #100663296 + 449 0072 04D0 beq .L36 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_OK; + 450 .loc 1 350 10 view .LVU175 + 451 0074 0020 movs r0, #0 + 452 .LVL60: + 453 .loc 1 350 10 view .LVU176 + 454 0076 18E0 b .L22 + 455 .LVL61: + 456 .L23: + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 457 .loc 1 301 5 is_stmt 1 view .LVU177 + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 458 .loc 1 301 23 is_stmt 0 view .LVU178 + 459 0078 0024 movs r4, #0 + 460 .LVL62: + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 461 .loc 1 301 23 view .LVU179 + 462 007a 4C60 str r4, [r1, #4] + 463 007c D9E7 b .L24 + 464 .LVL63: + 465 .L36: + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 466 .loc 1 343 7 is_stmt 1 view .LVU180 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> + 467 .loc 1 345 7 view .LVU181 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> + 468 .loc 1 345 39 is_stmt 0 view .LVU182 + 469 007e 4FEA9E03 lsr r3, lr, #2 + ARM GAS /tmp/ccQLKAuM.s page 16 + + + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> + 470 .loc 1 345 14 view .LVU183 + 471 0082 0233 adds r3, r3, #2 + 472 0084 0C4A ldr r2, .L37+12 + 473 0086 52F82320 ldr r2, [r2, r3, lsl #2] + 474 .LVL64: + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 475 .loc 1 346 7 is_stmt 1 view .LVU184 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 476 .loc 1 346 75 is_stmt 0 view .LVU185 + 477 008a 6FEA0E03 mvn r3, lr + 478 008e 03F00303 and r3, r3, #3 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 479 .loc 1 346 68 view .LVU186 + 480 0092 9B00 lsls r3, r3, #2 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 481 .loc 1 346 39 view .LVU187 + 482 0094 02FA03F3 lsl r3, r2, r3 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 483 .loc 1 346 98 view .LVU188 + 484 0098 1B0E lsrs r3, r3, #24 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 485 .loc 1 346 28 view .LVU189 + 486 009a CB60 str r3, [r1, #12] + 487 .loc 1 350 10 view .LVU190 + 488 009c 0020 movs r0, #0 + 489 009e 04E0 b .L22 + 490 .LVL65: + 491 .L28: + 492 .cfi_def_cfa_offset 0 + 493 .cfi_restore 4 + 494 .cfi_restore 14 + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 495 .loc 1 276 12 view .LVU191 + 496 00a0 0120 movs r0, #1 + 497 .LVL66: + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 498 .loc 1 276 12 view .LVU192 + 499 00a2 7047 bx lr + 500 .LVL67: + 501 .L29: + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 502 .loc 1 276 12 view .LVU193 + 503 00a4 0120 movs r0, #1 + 504 .LVL68: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 505 .loc 1 351 1 view .LVU194 + 506 00a6 7047 bx lr + 507 .LVL69: + 508 .L30: + 509 .cfi_def_cfa_offset 8 + 510 .cfi_offset 4, -8 + 511 .cfi_offset 14, -4 + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 512 .loc 1 350 10 view .LVU195 + 513 00a8 0020 movs r0, #0 + 514 .LVL70: + ARM GAS /tmp/ccQLKAuM.s page 17 + + + 515 .L22: + 516 .loc 1 351 1 view .LVU196 + 517 00aa 10BD pop {r4, pc} + 518 .L38: + 519 .align 2 + 520 .L37: + 521 00ac 04040140 .word 1073808388 + 522 00b0 08040140 .word 1073808392 + 523 00b4 0C040140 .word 1073808396 + 524 00b8 00000140 .word 1073807360 + 525 .cfi_endproc + 526 .LFE131: + 528 .section .text.HAL_EXTI_ClearConfigLine,"ax",%progbits + 529 .align 1 + 530 .global HAL_EXTI_ClearConfigLine + 531 .syntax unified + 532 .thumb + 533 .thumb_func + 535 HAL_EXTI_ClearConfigLine: + 536 .LVL71: + 537 .LFB132: + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Clear whole configuration of a dedicated Exti line. + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 538 .loc 1 359 1 is_stmt 1 view -0 + 539 .cfi_startproc + 540 @ args = 0, pretend = 0, frame = 0 + 541 @ frame_needed = 0, uses_anonymous_args = 0 + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 542 .loc 1 360 3 view .LVU198 + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 543 .loc 1 361 3 view .LVU199 + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t linepos; + 544 .loc 1 362 3 view .LVU200 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 545 .loc 1 363 3 view .LVU201 + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 546 .loc 1 364 3 view .LVU202 + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check null pointer */ + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if (hexti == NULL) + 547 .loc 1 367 3 view .LVU203 + 548 .loc 1 367 6 is_stmt 0 view .LVU204 + 549 0000 0028 cmp r0, #0 + 550 0002 40D0 beq .L41 + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 551 .loc 1 359 1 view .LVU205 + 552 0004 30B5 push {r4, r5, lr} + 553 .cfi_def_cfa_offset 12 + 554 .cfi_offset 4, -12 + 555 .cfi_offset 5, -8 + 556 .cfi_offset 14, -4 + ARM GAS /tmp/ccQLKAuM.s page 18 + + + 557 0006 8446 mov ip, r0 + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_ERROR; + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check the parameter */ + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 558 .loc 1 373 3 is_stmt 1 view .LVU206 + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 559 .loc 1 376 3 view .LVU207 + 560 .loc 1 376 19 is_stmt 0 view .LVU208 + 561 0008 0468 ldr r4, [r0] + 562 .loc 1 376 10 view .LVU209 + 563 000a C4F30043 ubfx r3, r4, #16, #1 + 564 .LVL72: + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 565 .loc 1 377 3 is_stmt 1 view .LVU210 + 566 .loc 1 377 11 is_stmt 0 view .LVU211 + 567 000e 04F01F0E and lr, r4, #31 + 568 .LVL73: + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << linepos); + 569 .loc 1 378 3 is_stmt 1 view .LVU212 + 570 .loc 1 378 12 is_stmt 0 view .LVU213 + 571 0012 0122 movs r2, #1 + 572 0014 02FA0EF2 lsl r2, r2, lr + 573 .LVL74: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 1] Clear interrupt mode */ + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + 574 .loc 1 381 3 is_stmt 1 view .LVU214 + 575 .loc 1 381 25 is_stmt 0 view .LVU215 + 576 0018 5B01 lsls r3, r3, #5 + 577 .LVL75: + 578 .loc 1 381 11 view .LVU216 + 579 001a 03F18041 add r1, r3, #1073741824 + 580 001e 01F58231 add r1, r1, #66560 + 581 .LVL76: + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 582 .loc 1 382 3 is_stmt 1 view .LVU217 + 583 .loc 1 382 13 is_stmt 0 view .LVU218 + 584 0022 0868 ldr r0, [r1] + 585 .LVL77: + 586 .loc 1 382 24 view .LVU219 + 587 0024 D543 mvns r5, r2 + 588 .loc 1 382 10 view .LVU220 + 589 0026 20EA0200 bic r0, r0, r2 + 590 .LVL78: + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 591 .loc 1 383 3 is_stmt 1 view .LVU221 + 592 .loc 1 383 12 is_stmt 0 view .LVU222 + 593 002a 0860 str r0, [r1] + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 2] Clear event mode */ + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + 594 .loc 1 386 3 is_stmt 1 view .LVU223 + ARM GAS /tmp/ccQLKAuM.s page 19 + + + 595 .loc 1 386 11 is_stmt 0 view .LVU224 + 596 002c 1848 ldr r0, .L49 + 597 .LVL79: + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 598 .loc 1 387 3 is_stmt 1 view .LVU225 + 599 .loc 1 387 13 is_stmt 0 view .LVU226 + 600 002e 1958 ldr r1, [r3, r0] + 601 .LVL80: + 602 .loc 1 387 10 view .LVU227 + 603 0030 21EA0202 bic r2, r1, r2 + 604 .LVL81: + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 605 .loc 1 388 3 is_stmt 1 view .LVU228 + 606 .loc 1 388 12 is_stmt 0 view .LVU229 + 607 0034 1A50 str r2, [r3, r0] + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 3] Clear triggers in case of configurable lines */ + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((hexti->Line & EXTI_CONFIG) != 0x00u) + 608 .loc 1 391 3 is_stmt 1 view .LVU230 + 609 .loc 1 391 13 is_stmt 0 view .LVU231 + 610 0036 DCF80020 ldr r2, [ip] + 611 .LVL82: + 612 .loc 1 391 6 view .LVU232 + 613 003a 12F0007F tst r2, #33554432 + 614 003e 24D0 beq .L42 + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + 615 .loc 1 393 5 is_stmt 1 view .LVU233 + 616 .loc 1 393 13 is_stmt 0 view .LVU234 + 617 0040 1449 ldr r1, .L49+4 + 618 .LVL83: + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 619 .loc 1 394 5 is_stmt 1 view .LVU235 + 620 .loc 1 394 15 is_stmt 0 view .LVU236 + 621 0042 5A58 ldr r2, [r3, r1] + 622 .loc 1 394 12 view .LVU237 + 623 0044 2A40 ands r2, r2, r5 + 624 .LVL84: + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 625 .loc 1 395 5 is_stmt 1 view .LVU238 + 626 .loc 1 395 14 is_stmt 0 view .LVU239 + 627 0046 5A50 str r2, [r3, r1] + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + 628 .loc 1 397 5 is_stmt 1 view .LVU240 + 629 .loc 1 397 13 is_stmt 0 view .LVU241 + 630 0048 134A ldr r2, .L49+8 + 631 .LVL85: + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 632 .loc 1 398 5 is_stmt 1 view .LVU242 + 633 .loc 1 398 15 is_stmt 0 view .LVU243 + 634 004a 9958 ldr r1, [r3, r2] + 635 .LVL86: + 636 .loc 1 398 12 view .LVU244 + 637 004c 0D40 ands r5, r5, r1 + 638 .LVL87: + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + ARM GAS /tmp/ccQLKAuM.s page 20 + + + 639 .loc 1 399 5 is_stmt 1 view .LVU245 + 640 .loc 1 399 14 is_stmt 0 view .LVU246 + 641 004e 9D50 str r5, [r3, r2] + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + 642 .loc 1 402 5 is_stmt 1 view .LVU247 + 643 .loc 1 402 15 is_stmt 0 view .LVU248 + 644 0050 DCF80030 ldr r3, [ip] + 645 .LVL88: + 646 .loc 1 402 22 view .LVU249 + 647 0054 03F0C063 and r3, r3, #100663296 + 648 .loc 1 402 8 view .LVU250 + 649 0058 B3F1C06F cmp r3, #100663296 + 650 005c 01D0 beq .L48 + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_OK; + 651 .loc 1 412 10 view .LVU251 + 652 005e 0020 movs r0, #0 + 653 0060 14E0 b .L40 + 654 .L48: + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 655 .loc 1 404 7 is_stmt 1 view .LVU252 + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 656 .loc 1 406 7 view .LVU253 + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 657 .loc 1 406 39 is_stmt 0 view .LVU254 + 658 0062 4FEA9E0E lsr lr, lr, #2 + 659 .LVL89: + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 660 .loc 1 406 14 view .LVU255 + 661 0066 0D49 ldr r1, .L49+12 + 662 0068 0EF1020E add lr, lr, #2 + 663 006c 51F82E30 ldr r3, [r1, lr, lsl #2] + 664 .LVL90: + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 665 .loc 1 407 7 is_stmt 1 view .LVU256 + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 666 .loc 1 407 80 is_stmt 0 view .LVU257 + 667 0070 04F00304 and r4, r4, #3 + 668 .LVL91: + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 669 .loc 1 407 69 view .LVU258 + 670 0074 A400 lsls r4, r4, #2 + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 671 .loc 1 407 40 view .LVU259 + 672 0076 0F22 movs r2, #15 + 673 0078 A240 lsls r2, r2, r4 + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + ARM GAS /tmp/ccQLKAuM.s page 21 + + + 674 .loc 1 407 14 view .LVU260 + 675 007a 23EA0203 bic r3, r3, r2 + 676 .LVL92: + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 677 .loc 1 408 7 is_stmt 1 view .LVU261 + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 678 .loc 1 408 37 is_stmt 0 view .LVU262 + 679 007e 41F82E30 str r3, [r1, lr, lsl #2] + 680 .loc 1 412 10 view .LVU263 + 681 0082 0020 movs r0, #0 + 682 0084 02E0 b .L40 + 683 .LVL93: + 684 .L41: + 685 .cfi_def_cfa_offset 0 + 686 .cfi_restore 4 + 687 .cfi_restore 5 + 688 .cfi_restore 14 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 689 .loc 1 369 12 view .LVU264 + 690 0086 0120 movs r0, #1 + 691 .LVL94: + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 692 .loc 1 413 1 view .LVU265 + 693 0088 7047 bx lr + 694 .LVL95: + 695 .L42: + 696 .cfi_def_cfa_offset 12 + 697 .cfi_offset 4, -12 + 698 .cfi_offset 5, -8 + 699 .cfi_offset 14, -4 + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 700 .loc 1 412 10 view .LVU266 + 701 008a 0020 movs r0, #0 + 702 .LVL96: + 703 .L40: + 704 .loc 1 413 1 view .LVU267 + 705 008c 30BD pop {r4, r5, pc} + 706 .L50: + 707 008e 00BF .align 2 + 708 .L49: + 709 0090 04040140 .word 1073808388 + 710 0094 08040140 .word 1073808392 + 711 0098 0C040140 .word 1073808396 + 712 009c 00000140 .word 1073807360 + 713 .cfi_endproc + 714 .LFE132: + 716 .section .text.HAL_EXTI_RegisterCallback,"ax",%progbits + 717 .align 1 + 718 .global HAL_EXTI_RegisterCallback + 719 .syntax unified + 720 .thumb + 721 .thumb_func + 723 HAL_EXTI_RegisterCallback: + 724 .LVL97: + 725 .LFB133: + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + ARM GAS /tmp/ccQLKAuM.s page 22 + + + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Register callback for a dedicated Exti line. + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param CallbackID User callback identifier. + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param pPendingCbfn function pointer to be stored as callback. + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef Callb + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 726 .loc 1 424 1 is_stmt 1 view -0 + 727 .cfi_startproc + 728 @ args = 0, pretend = 0, frame = 0 + 729 @ frame_needed = 0, uses_anonymous_args = 0 + 730 @ link register save eliminated. + 731 .loc 1 424 1 is_stmt 0 view .LVU269 + 732 0000 0346 mov r3, r0 + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef status = HAL_OK; + 733 .loc 1 425 3 is_stmt 1 view .LVU270 + 734 .LVL98: + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** switch (CallbackID) + 735 .loc 1 427 3 view .LVU271 + 736 0002 0846 mov r0, r1 + 737 .LVL99: + 738 .loc 1 427 3 is_stmt 0 view .LVU272 + 739 0004 09B9 cbnz r1, .L53 + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** case HAL_EXTI_COMMON_CB_ID: + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** hexti->PendingCallback = pPendingCbfn; + 740 .loc 1 430 7 is_stmt 1 view .LVU273 + 741 .loc 1 430 30 is_stmt 0 view .LVU274 + 742 0006 5A60 str r2, [r3, #4] + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** break; + 743 .loc 1 431 7 is_stmt 1 view .LVU275 + 744 0008 7047 bx lr + 745 .L53: + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** default: + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** status = HAL_ERROR; + 746 .loc 1 434 14 is_stmt 0 view .LVU276 + 747 000a 0120 movs r0, #1 + 748 .LVL100: + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** break; + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return status; + 749 .loc 1 438 3 is_stmt 1 view .LVU277 + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 750 .loc 1 439 1 is_stmt 0 view .LVU278 + 751 000c 7047 bx lr + 752 .cfi_endproc + 753 .LFE133: + 755 .section .text.HAL_EXTI_GetHandle,"ax",%progbits + 756 .align 1 + 757 .global HAL_EXTI_GetHandle + 758 .syntax unified + 759 .thumb + ARM GAS /tmp/ccQLKAuM.s page 23 + + + 760 .thumb_func + 762 HAL_EXTI_GetHandle: + 763 .LVL101: + 764 .LFB134: + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Store line number as handle private field. + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param ExtiLine Exti line number. + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter can be from 0 to @ref EXTI_LINE_NB. + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 765 .loc 1 449 1 is_stmt 1 view -0 + 766 .cfi_startproc + 767 @ args = 0, pretend = 0, frame = 0 + 768 @ frame_needed = 0, uses_anonymous_args = 0 + 769 @ link register save eliminated. + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check the parameters */ + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(ExtiLine)); + 770 .loc 1 451 3 view .LVU280 + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check null pointer */ + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if (hexti == NULL) + 771 .loc 1 454 3 view .LVU281 + 772 .loc 1 454 6 is_stmt 0 view .LVU282 + 773 0000 10B1 cbz r0, .L56 + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_ERROR; + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store line number as handle private field */ + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** hexti->Line = ExtiLine; + 774 .loc 1 461 5 is_stmt 1 view .LVU283 + 775 .loc 1 461 17 is_stmt 0 view .LVU284 + 776 0002 0160 str r1, [r0] + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_OK; + 777 .loc 1 463 5 is_stmt 1 view .LVU285 + 778 .loc 1 463 12 is_stmt 0 view .LVU286 + 779 0004 0020 movs r0, #0 + 780 .LVL102: + 781 .loc 1 463 12 view .LVU287 + 782 0006 7047 bx lr + 783 .LVL103: + 784 .L56: + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 785 .loc 1 456 12 view .LVU288 + 786 0008 0120 movs r0, #1 + 787 .LVL104: + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 788 .loc 1 465 1 view .LVU289 + 789 000a 7047 bx lr + 790 .cfi_endproc + ARM GAS /tmp/ccQLKAuM.s page 24 + + + 791 .LFE134: + 793 .section .text.HAL_EXTI_IRQHandler,"ax",%progbits + 794 .align 1 + 795 .global HAL_EXTI_IRQHandler + 796 .syntax unified + 797 .thumb + 798 .thumb_func + 800 HAL_EXTI_IRQHandler: + 801 .LVL105: + 802 .LFB135: + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @} + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group2 + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief EXTI IO functions. + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @verbatim + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** =============================================================================== + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ##### IO operation functions ##### + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** =============================================================================== + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @endverbatim + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Handle EXTI interrupt request. + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval none. + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 803 .loc 1 489 1 is_stmt 1 view -0 + 804 .cfi_startproc + 805 @ args = 0, pretend = 0, frame = 0 + 806 @ frame_needed = 0, uses_anonymous_args = 0 + 807 .loc 1 489 1 is_stmt 0 view .LVU291 + 808 0000 08B5 push {r3, lr} + 809 .cfi_def_cfa_offset 8 + 810 .cfi_offset 3, -8 + 811 .cfi_offset 14, -4 + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 812 .loc 1 490 3 is_stmt 1 view .LVU292 + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 813 .loc 1 491 3 view .LVU293 + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 814 .loc 1 492 3 view .LVU294 + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 815 .loc 1 493 3 view .LVU295 + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Compute line register offset and line mask */ + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 816 .loc 1 496 3 view .LVU296 + 817 .loc 1 496 19 is_stmt 0 view .LVU297 + 818 0002 0368 ldr r3, [r0] + ARM GAS /tmp/ccQLKAuM.s page 25 + + + 819 .loc 1 496 10 view .LVU298 + 820 0004 C3F30041 ubfx r1, r3, #16, #1 + 821 .LVL106: + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 822 .loc 1 497 3 is_stmt 1 view .LVU299 + 823 .loc 1 497 35 is_stmt 0 view .LVU300 + 824 0008 03F01F03 and r3, r3, #31 + 825 .loc 1 497 12 view .LVU301 + 826 000c 0122 movs r2, #1 + 827 000e 02FA03F3 lsl r3, r2, r3 + 828 .LVL107: + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get pending bit */ + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + 829 .loc 1 500 3 is_stmt 1 view .LVU302 + 830 .loc 1 500 24 is_stmt 0 view .LVU303 + 831 0012 4A01 lsls r2, r1, #5 + 832 .loc 1 500 11 view .LVU304 + 833 0014 0449 ldr r1, .L60 + 834 .LVL108: + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & maskline); + 835 .loc 1 501 3 is_stmt 1 view .LVU305 + 836 .loc 1 501 13 is_stmt 0 view .LVU306 + 837 0016 5258 ldr r2, [r2, r1] + 838 .LVL109: + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if (regval != 0x00u) + 839 .loc 1 503 3 is_stmt 1 view .LVU307 + 840 .loc 1 503 6 is_stmt 0 view .LVU308 + 841 0018 1A42 tst r2, r3 + 842 001a 04D0 beq .L57 + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Clear pending bit */ + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** EXTI->PR = maskline; + 843 .loc 1 506 5 is_stmt 1 view .LVU309 + 844 .loc 1 506 14 is_stmt 0 view .LVU310 + 845 001c 034A ldr r2, .L60+4 + 846 .LVL110: + 847 .loc 1 506 14 view .LVU311 + 848 001e 5361 str r3, [r2, #20] + 849 .LVL111: + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Call callback */ + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if (hexti->PendingCallback != NULL) + 850 .loc 1 509 5 is_stmt 1 view .LVU312 + 851 .loc 1 509 14 is_stmt 0 view .LVU313 + 852 0020 4368 ldr r3, [r0, #4] + 853 .LVL112: + 854 .loc 1 509 8 view .LVU314 + 855 0022 03B1 cbz r3, .L57 + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** hexti->PendingCallback(); + 856 .loc 1 511 7 is_stmt 1 view .LVU315 + 857 0024 9847 blx r3 + 858 .LVL113: + 859 .L57: + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + ARM GAS /tmp/ccQLKAuM.s page 26 + + + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 860 .loc 1 514 1 is_stmt 0 view .LVU316 + 861 0026 08BD pop {r3, pc} + 862 .L61: + 863 .align 2 + 864 .L60: + 865 0028 14040140 .word 1073808404 + 866 002c 00040140 .word 1073808384 + 867 .cfi_endproc + 868 .LFE135: + 870 .section .text.HAL_EXTI_GetPending,"ax",%progbits + 871 .align 1 + 872 .global HAL_EXTI_GetPending + 873 .syntax unified + 874 .thumb + 875 .thumb_func + 877 HAL_EXTI_GetPending: + 878 .LVL114: + 879 .LFB136: + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Get interrupt pending bit of a dedicated line. + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param Edge Specify which pending edge as to be checked. + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter can be one of the following values: + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING_FALLING + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter is kept for compatibility with other series. + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval 1 if interrupt is pending else 0. + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 880 .loc 1 526 1 is_stmt 1 view -0 + 881 .cfi_startproc + 882 @ args = 0, pretend = 0, frame = 0 + 883 @ frame_needed = 0, uses_anonymous_args = 0 + 884 @ link register save eliminated. + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 885 .loc 1 527 3 view .LVU318 + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 886 .loc 1 528 3 view .LVU319 + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t linepos; + 887 .loc 1 529 3 view .LVU320 + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 888 .loc 1 530 3 view .LVU321 + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 889 .loc 1 531 3 view .LVU322 + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check parameters */ + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 890 .loc 1 534 3 view .LVU323 + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 891 .loc 1 535 3 view .LVU324 + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 892 .loc 1 536 3 view .LVU325 + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + ARM GAS /tmp/ccQLKAuM.s page 27 + + + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 893 .loc 1 539 3 view .LVU326 + 894 .loc 1 539 19 is_stmt 0 view .LVU327 + 895 0000 0368 ldr r3, [r0] + 896 .loc 1 539 10 view .LVU328 + 897 0002 C3F30041 ubfx r1, r3, #16, #1 + 898 .LVL115: + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 899 .loc 1 540 3 is_stmt 1 view .LVU329 + 900 .loc 1 540 11 is_stmt 0 view .LVU330 + 901 0006 03F01F03 and r3, r3, #31 + 902 .LVL116: + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << linepos); + 903 .loc 1 541 3 is_stmt 1 view .LVU331 + 904 .loc 1 541 12 is_stmt 0 view .LVU332 + 905 000a 0122 movs r2, #1 + 906 000c 9A40 lsls r2, r2, r3 + 907 .LVL117: + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get pending bit */ + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + 908 .loc 1 544 3 is_stmt 1 view .LVU333 + 909 .loc 1 544 24 is_stmt 0 view .LVU334 + 910 000e 4901 lsls r1, r1, #5 + 911 .LVL118: + 912 .loc 1 544 11 view .LVU335 + 913 0010 0248 ldr r0, .L63 + 914 .LVL119: + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* return 1 if bit is set else 0 */ + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = ((*regaddr & maskline) >> linepos); + 915 .loc 1 546 3 is_stmt 1 view .LVU336 + 916 .loc 1 546 14 is_stmt 0 view .LVU337 + 917 0012 0858 ldr r0, [r1, r0] + 918 .LVL120: + 919 .loc 1 546 23 view .LVU338 + 920 0014 1040 ands r0, r0, r2 + 921 .LVL121: + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return regval; + 922 .loc 1 547 3 is_stmt 1 view .LVU339 + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 923 .loc 1 548 1 is_stmt 0 view .LVU340 + 924 0016 D840 lsrs r0, r0, r3 + 925 .LVL122: + 926 .loc 1 548 1 view .LVU341 + 927 0018 7047 bx lr + 928 .L64: + 929 001a 00BF .align 2 + 930 .L63: + 931 001c 14040140 .word 1073808404 + 932 .cfi_endproc + 933 .LFE136: + 935 .section .text.HAL_EXTI_ClearPending,"ax",%progbits + 936 .align 1 + 937 .global HAL_EXTI_ClearPending + 938 .syntax unified + 939 .thumb + 940 .thumb_func + ARM GAS /tmp/ccQLKAuM.s page 28 + + + 942 HAL_EXTI_ClearPending: + 943 .LVL123: + 944 .LFB137: + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Clear interrupt pending bit of a dedicated line. + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param Edge Specify which pending edge as to be clear. + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter can be one of the following values: + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING_FALLING + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter is kept for compatibility with other series. + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval None. + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 945 .loc 1 560 1 is_stmt 1 view -0 + 946 .cfi_startproc + 947 @ args = 0, pretend = 0, frame = 0 + 948 @ frame_needed = 0, uses_anonymous_args = 0 + 949 @ link register save eliminated. + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 950 .loc 1 561 3 view .LVU343 + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 951 .loc 1 562 3 view .LVU344 + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 952 .loc 1 563 3 view .LVU345 + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check parameters */ + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 953 .loc 1 566 3 view .LVU346 + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 954 .loc 1 567 3 view .LVU347 + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 955 .loc 1 568 3 view .LVU348 + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 956 .loc 1 571 3 view .LVU349 + 957 .loc 1 571 19 is_stmt 0 view .LVU350 + 958 0000 0368 ldr r3, [r0] + 959 .loc 1 571 10 view .LVU351 + 960 0002 C3F30042 ubfx r2, r3, #16, #1 + 961 .LVL124: + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 962 .loc 1 572 3 is_stmt 1 view .LVU352 + 963 .loc 1 572 35 is_stmt 0 view .LVU353 + 964 0006 03F01F03 and r3, r3, #31 + 965 .loc 1 572 12 view .LVU354 + 966 000a 0121 movs r1, #1 + 967 .LVL125: + 968 .loc 1 572 12 view .LVU355 + 969 000c 9940 lsls r1, r1, r3 + 970 .LVL126: + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get pending bit */ + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + 971 .loc 1 575 3 is_stmt 1 view .LVU356 + ARM GAS /tmp/ccQLKAuM.s page 29 + + + 972 .loc 1 575 24 is_stmt 0 view .LVU357 + 973 000e 5301 lsls r3, r2, #5 + 974 .loc 1 575 11 view .LVU358 + 975 0010 014A ldr r2, .L66 + 976 .LVL127: + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Clear Pending bit */ + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = maskline; + 977 .loc 1 578 3 is_stmt 1 view .LVU359 + 978 .loc 1 578 12 is_stmt 0 view .LVU360 + 979 0012 9950 str r1, [r3, r2] + 980 .LVL128: + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 981 .loc 1 579 1 view .LVU361 + 982 0014 7047 bx lr + 983 .L67: + 984 0016 00BF .align 2 + 985 .L66: + 986 0018 14040140 .word 1073808404 + 987 .cfi_endproc + 988 .LFE137: + 990 .section .text.HAL_EXTI_GenerateSWI,"ax",%progbits + 991 .align 1 + 992 .global HAL_EXTI_GenerateSWI + 993 .syntax unified + 994 .thumb + 995 .thumb_func + 997 HAL_EXTI_GenerateSWI: + 998 .LVL129: + 999 .LFB138: + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Generate a software interrupt for a dedicated line. + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval None. + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 1000 .loc 1 587 1 is_stmt 1 view -0 + 1001 .cfi_startproc + 1002 @ args = 0, pretend = 0, frame = 0 + 1003 @ frame_needed = 0, uses_anonymous_args = 0 + 1004 @ link register save eliminated. + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 1005 .loc 1 588 3 view .LVU363 + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 1006 .loc 1 589 3 view .LVU364 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 1007 .loc 1 590 3 view .LVU365 + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check parameters */ + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 1008 .loc 1 593 3 view .LVU366 + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 1009 .loc 1 594 3 view .LVU367 + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + ARM GAS /tmp/ccQLKAuM.s page 30 + + + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1010 .loc 1 597 3 view .LVU368 + 1011 .loc 1 597 19 is_stmt 0 view .LVU369 + 1012 0000 0368 ldr r3, [r0] + 1013 .loc 1 597 10 view .LVU370 + 1014 0002 C3F30042 ubfx r2, r3, #16, #1 + 1015 .LVL130: + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 1016 .loc 1 598 3 is_stmt 1 view .LVU371 + 1017 .loc 1 598 35 is_stmt 0 view .LVU372 + 1018 0006 03F01F03 and r3, r3, #31 + 1019 .loc 1 598 12 view .LVU373 + 1020 000a 0121 movs r1, #1 + 1021 000c 9940 lsls r1, r1, r3 + 1022 .LVL131: + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->SWIER + (EXTI_CONFIG_OFFSET * offset)); + 1023 .loc 1 600 3 is_stmt 1 view .LVU374 + 1024 .loc 1 600 27 is_stmt 0 view .LVU375 + 1025 000e 5301 lsls r3, r2, #5 + 1026 .loc 1 600 11 view .LVU376 + 1027 0010 014A ldr r2, .L69 + 1028 .LVL132: + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = maskline; + 1029 .loc 1 601 3 is_stmt 1 view .LVU377 + 1030 .loc 1 601 12 is_stmt 0 view .LVU378 + 1031 0012 9950 str r1, [r3, r2] + 1032 .LVL133: + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 1033 .loc 1 602 1 view .LVU379 + 1034 0014 7047 bx lr + 1035 .L70: + 1036 0016 00BF .align 2 + 1037 .L69: + 1038 0018 10040140 .word 1073808400 + 1039 .cfi_endproc + 1040 .LFE138: + 1042 .text + 1043 .Letext0: + 1044 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1045 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1046 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1047 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1048 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h" + ARM GAS /tmp/ccQLKAuM.s page 31 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_exti.c + /tmp/ccQLKAuM.s:21 .text.HAL_EXTI_SetConfigLine:0000000000000000 $t + /tmp/ccQLKAuM.s:27 .text.HAL_EXTI_SetConfigLine:0000000000000000 HAL_EXTI_SetConfigLine + /tmp/ccQLKAuM.s:293 .text.HAL_EXTI_SetConfigLine:00000000000000cc $d + /tmp/ccQLKAuM.s:301 .text.HAL_EXTI_GetConfigLine:0000000000000000 $t + /tmp/ccQLKAuM.s:307 .text.HAL_EXTI_GetConfigLine:0000000000000000 HAL_EXTI_GetConfigLine + /tmp/ccQLKAuM.s:521 .text.HAL_EXTI_GetConfigLine:00000000000000ac $d + /tmp/ccQLKAuM.s:529 .text.HAL_EXTI_ClearConfigLine:0000000000000000 $t + /tmp/ccQLKAuM.s:535 .text.HAL_EXTI_ClearConfigLine:0000000000000000 HAL_EXTI_ClearConfigLine + /tmp/ccQLKAuM.s:709 .text.HAL_EXTI_ClearConfigLine:0000000000000090 $d + /tmp/ccQLKAuM.s:717 .text.HAL_EXTI_RegisterCallback:0000000000000000 $t + /tmp/ccQLKAuM.s:723 .text.HAL_EXTI_RegisterCallback:0000000000000000 HAL_EXTI_RegisterCallback + /tmp/ccQLKAuM.s:756 .text.HAL_EXTI_GetHandle:0000000000000000 $t + /tmp/ccQLKAuM.s:762 .text.HAL_EXTI_GetHandle:0000000000000000 HAL_EXTI_GetHandle + /tmp/ccQLKAuM.s:794 .text.HAL_EXTI_IRQHandler:0000000000000000 $t + /tmp/ccQLKAuM.s:800 .text.HAL_EXTI_IRQHandler:0000000000000000 HAL_EXTI_IRQHandler + /tmp/ccQLKAuM.s:865 .text.HAL_EXTI_IRQHandler:0000000000000028 $d + /tmp/ccQLKAuM.s:871 .text.HAL_EXTI_GetPending:0000000000000000 $t + /tmp/ccQLKAuM.s:877 .text.HAL_EXTI_GetPending:0000000000000000 HAL_EXTI_GetPending + /tmp/ccQLKAuM.s:931 .text.HAL_EXTI_GetPending:000000000000001c $d + /tmp/ccQLKAuM.s:936 .text.HAL_EXTI_ClearPending:0000000000000000 $t + /tmp/ccQLKAuM.s:942 .text.HAL_EXTI_ClearPending:0000000000000000 HAL_EXTI_ClearPending + /tmp/ccQLKAuM.s:986 .text.HAL_EXTI_ClearPending:0000000000000018 $d + /tmp/ccQLKAuM.s:991 .text.HAL_EXTI_GenerateSWI:0000000000000000 $t + /tmp/ccQLKAuM.s:997 .text.HAL_EXTI_GenerateSWI:0000000000000000 HAL_EXTI_GenerateSWI + /tmp/ccQLKAuM.s:1038 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diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_flash.d b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_flash.d new file mode 100644 index 0000000..073172a --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_flash.d @@ -0,0 +1,58 @@ +build/stm32f3xx_hal_flash.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_flash.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_flash.lst new file mode 100644 index 0000000..3a7d915 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_flash.lst @@ -0,0 +1,2165 @@ +ARM GAS /tmp/ccX3tCBb.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_flash.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c" + 20 .section .text.FLASH_Program_HalfWord,"ax",%progbits + 21 .align 1 + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 FLASH_Program_HalfWord: + 27 .LVL0: + 28 .LFB141: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @file stm32f3xx_hal_flash.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief FLASH HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * functionalities of the internal FLASH memory: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + Program operations functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + Memory Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + Peripheral State functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ============================================================================== + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### FLASH peripheral features ##### + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ============================================================================== + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** to the Flash memory. It implements the erase and program Flash memory operations + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** and the read and write protection mechanisms. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] The Flash memory interface accelerates code execution with a system of instruction + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** prefetch. + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] The FLASH main features are: + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Flash memory read operations + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Flash memory program/erase operations + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Read / write protections + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Prefetch on I-Code + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Option Bytes programming + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + ARM GAS /tmp/ccX3tCBb.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### How to use this driver ##### + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ============================================================================== + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** This driver provides functions and macros to configure and program the FLASH + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** memory of all STM32F3xx devices. + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (#) FLASH Memory I/O Programming functions: this group includes all needed + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** functions to erase and program the main memory: + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Lock and Unlock the FLASH interface + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Erase function: Erase page, erase all pages + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Program functions: half word, word and doubleword + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (#) FLASH Option Bytes Programming functions: this group includes all needed + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** functions to manage the Option Bytes: + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Lock and Unlock the Option Bytes + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Set/Reset the write protection + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Set the Read protection Level + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Program the user Option Bytes + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Launch the Option Bytes loader + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Erase Option Bytes + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Program the data Option Bytes + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Get the Write protection. + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Get the user option bytes. + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (#) Interrupts and flags management functions : this group + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** includes all needed functions to: + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Handle FLASH interrupts + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Wait for last FLASH operation according to its status + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Get error flag status + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] In addition to these function, this driver includes a set of macros allowing + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** to handle the following operations: + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Set/Get the latency + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Enable/Disable the prefetch buffer + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Enable/Disable the half cycle access + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Enable/Disable the FLASH interrupts + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Monitor the FLASH flags status + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ****************************************************************************** + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @attention + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * All rights reserved.

    + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * This software component is licensed by ST under BSD 3-Clause license, + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * the "License"; You may not use this file except in compliance with the + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * License. You may obtain a copy of the License at: + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * opensource.org/licenses/BSD-3-Clause + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ****************************************************************************** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Includes ------------------------------------------------------------------*/ + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** #include "stm32f3xx_hal.h" + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @addtogroup STM32F3xx_HAL_Driver + ARM GAS /tmp/ccX3tCBb.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH FLASH + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief FLASH HAL module driver + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private typedef -----------------------------------------------------------*/ + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private define ------------------------------------------------------------*/ + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Private_Constants FLASH Private Constants + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private macro ---------------------------- ---------------------------------*/ + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Private_Macros FLASH Private Macros + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private variables ---------------------------------------------------------*/ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Private_Variables FLASH Private Variables + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Variables used for Erase pages under interruption*/ + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_ProcessTypeDef pFlash; + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private function prototypes -----------------------------------------------*/ + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Private_Functions FLASH Private Functions + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** static void FLASH_SetErrorCode(void); + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** extern void FLASH_PageErase(uint32_t PageAddress); + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Exported functions ---------------------------------------------------------*/ + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions FLASH Exported Functions + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Programming operation functions + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + ARM GAS /tmp/ccX3tCBb.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Program halfword, word or double word at a specified address + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note If an erase and a program operations are requested simultaneously, + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * the erase operation is performed before the program one. + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note FLASH should be previously erased before new programming (only exception to this + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * is when 0x0000 is programmed) + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Address Specifie the address to be programmed. + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Data Specifie the data to be programmed + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint8_t index = 0U; + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint8_t nbiterations = 0U; + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process Locked */ + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check the parameters */ + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for last operation to be completed */ + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(status == HAL_OK) + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */ + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** nbiterations = 1U; + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program word (32-bit = 2*16-bit) at a specified address. */ + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** nbiterations = 2U; + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program double word (64-bit = 4*16-bit) at a specified address. */ + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** nbiterations = 4U; + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + ARM GAS /tmp/ccX3tCBb.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** for (index = 0U; index < nbiterations; index++) + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for last operation to be completed */ + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* If the program operation is completed, disable the PG Bit */ + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* In case of error, stop programming procedure */ + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (status != HAL_OK) + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** break; + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process Unlocked */ + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return status; + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Program halfword, word or double word at a specified address with interrupt enabled. + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note If an erase and a program operations are requested simultaneously, + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * the erase operation is performed before the program one. + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Address Specifie the address to be programmed. + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Data Specifie the data to be programmed + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process Locked */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check the parameters */ + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Enable End of FLASH Operation and Error source interrupts */ + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = Address; + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Data = Data; + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + ARM GAS /tmp/ccX3tCBb.s page 6 + + + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */ + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining = 1U; + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program word (32-bit : 2*16-bit) at a specified address. */ + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining = 2U; + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program double word (64-bit : 4*16-bit) at a specified address. */ + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining = 4U; + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */ + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_Program_HalfWord(Address, (uint16_t)Data); + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return status; + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief This function handles FLASH interrupt request. + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval None + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** void HAL_FLASH_IRQHandler(void) + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t addresstmp = 0U; + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check FLASH operation error flags */ + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Return the faulty address */ + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Reset address */ + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = 0xFFFFFFFFU; + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Save the Error code */ + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_SetErrorCode(); + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH error interrupt user callback */ + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_OperationErrorCallback(addresstmp); + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Stop the procedure ongoing */ + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check FLASH End of Operation flag */ + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process can continue only if no error detected */ + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + ARM GAS /tmp/ccX3tCBb.s page 7 + + + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Nb of pages to erased can be decreased */ + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining--; + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check if there are still pages to erase */ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.DataRemaining != 0U) + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Indicate user which sector has been erased */ + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(addresstmp); + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Increment sector number*/ + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp; + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* If the erase operation is completed, disable the PER Bit */ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_PageErase(addresstmp); + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* No more pages to Erase, user callback can be called. */ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Reset Sector and stop Erase pages procedure */ + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp = 0xFFFFFFFFU; + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(addresstmp); + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Operation is completed, disable the MER Bit */ + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* MassErase ended. Return the selected bank */ + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(0U); + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Stop Mass Erase procedure*/ + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Nb of 16-bit data to program can be decreased */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining--; + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check if there are still 16-bit data to program */ + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.DataRemaining != 0U) + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Increment address to 16-bit */ + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address += 2U; + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Shift to have next 16-bit data */ + ARM GAS /tmp/ccX3tCBb.s page 8 + + + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Data = (pFlash.Data >> 16U); + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Operation is completed, disable the PG Bit */ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Program halfword (16-bit) at a specified address.*/ + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program ended. Return the selected address */ + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address); + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Reset Address and stop Program procedure */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = 0xFFFFFFFFU; + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Operation is completed, disable the PG, PER and MER Bits */ + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Disable End of FLASH Operation and Error source interrupts */ + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process Unlocked */ + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief FLASH end of operation interrupt callback + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Mass Erase: No return value expected + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Pages Erase: Address of the page which has been erased + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Program: Address which was selected for data program + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval none + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) + ARM GAS /tmp/ccX3tCBb.s page 9 + + + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** UNUSED(ReturnValue); + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief FLASH operation error interrupt callback + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Mass Erase: No return value expected + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Pages Erase: Address of the page which returned an error + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Program: Address which was selected for data program + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval none + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** UNUSED(ReturnValue); + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** the HAL_FLASH_OperationErrorCallback could be implemented in the user file + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief management functions + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** =============================================================================== + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### Peripheral Control functions ##### + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** =============================================================================== + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** This subsection provides a set of functions allowing to control the FLASH + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** memory operations. + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Unlock the FLASH control register access + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Unlock(void) + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Authorize the FLASH Registers access */ + ARM GAS /tmp/ccX3tCBb.s page 10 + + + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY1); + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY2); + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Verify Flash is unlocked */ + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** status = HAL_ERROR; + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return status; + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Locks the FLASH control register access + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Lock(void) + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Set the LOCK Bit to lock the FLASH Registers access */ + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_LOCK); + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_OK; + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Unlock the FLASH Option Control Registers access. + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Authorizes the Option Byte register programming */ + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_ERROR; + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_OK; + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Lock the FLASH Option Control Registers access. + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_OK; + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + ARM GAS /tmp/ccX3tCBb.s page 11 + + + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Launch the option byte loading. + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note This function will reset automatically the MCU. + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Set the OBL_Launch bit to launch the option byte loading */ + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for last operation to be completed */ + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Peripheral errors functions + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** =============================================================================== + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### Peripheral Errors functions ##### + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** =============================================================================== + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** This subsection permit to get in run-time errors of the FLASH peripheral. + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Get the specific FLASH error flag. + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval FLASH_ErrorCode The returned value can be: + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @ref FLASH_Error_Codes + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t HAL_FLASH_GetError(void) + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return pFlash.ErrorCode; + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @addtogroup FLASH_Private_Functions + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Program a half-word (16-bit) at a specified address. + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Address specify the address to be programmed. + ARM GAS /tmp/ccX3tCBb.s page 12 + + + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Data specify the data to be programmed. + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval None + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 29 .loc 1 605 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clean the error context */ + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 34 .loc 1 607 3 view .LVU1 + 35 .loc 1 607 20 is_stmt 0 view .LVU2 + 36 0000 044B ldr r3, .L2 + 37 0002 0022 movs r2, #0 + 38 0004 DA61 str r2, [r3, #28] + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Proceed to program the new data */ + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_PG); + 39 .loc 1 610 5 is_stmt 1 view .LVU3 + 40 0006 044A ldr r2, .L2+4 + 41 0008 1369 ldr r3, [r2, #16] + 42 000a 43F00103 orr r3, r3, #1 + 43 000e 1361 str r3, [r2, #16] + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Write data in the address */ + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** *(__IO uint16_t*)Address = Data; + 44 .loc 1 613 3 view .LVU4 + 45 .loc 1 613 28 is_stmt 0 view .LVU5 + 46 0010 0180 strh r1, [r0] @ movhi + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 47 .loc 1 614 1 view .LVU6 + 48 0012 7047 bx lr + 49 .L3: + 50 .align 2 + 51 .L2: + 52 0014 00000000 .word pFlash + 53 0018 00200240 .word 1073881088 + 54 .cfi_endproc + 55 .LFE141: + 57 .section .text.FLASH_SetErrorCode,"ax",%progbits + 58 .align 1 + 59 .syntax unified + 60 .thumb + 61 .thumb_func + 63 FLASH_SetErrorCode: + 64 .LFB143: + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Wait for a FLASH operation to complete. + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Timeout maximum flash operation timeout + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + ARM GAS /tmp/ccX3tCBb.s page 13 + + + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** Even if the FLASH operation fails, the BUSY flag will be reset and an error + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** flag will be set */ + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t tickstart = HAL_GetTick(); + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (Timeout != HAL_MAX_DELAY) + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_TIMEOUT; + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check FLASH End of Operation flag */ + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Save the error code*/ + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_SetErrorCode(); + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_ERROR; + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* There is no error flag set */ + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_OK; + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Set the specific FLASH error flag. + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval None + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** static void FLASH_SetErrorCode(void) + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 65 .loc 1 665 1 is_stmt 1 view -0 + 66 .cfi_startproc + 67 @ args = 0, pretend = 0, frame = 0 + 68 @ frame_needed = 0, uses_anonymous_args = 0 + 69 @ link register save eliminated. + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t flags = 0U; + 70 .loc 1 666 3 view .LVU8 + 71 .LVL1: + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + 72 .loc 1 668 3 view .LVU9 + 73 .loc 1 668 6 is_stmt 0 view .LVU10 + 74 0000 0C4B ldr r3, .L7 + 75 0002 DB68 ldr r3, [r3, #12] + 76 .loc 1 668 5 view .LVU11 + ARM GAS /tmp/ccX3tCBb.s page 14 + + + 77 0004 13F01003 ands r3, r3, #16 + 78 0008 05D0 beq .L5 + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + 79 .loc 1 670 5 is_stmt 1 view .LVU12 + 80 .loc 1 670 11 is_stmt 0 view .LVU13 + 81 000a 0B4A ldr r2, .L7+4 + 82 000c D369 ldr r3, [r2, #28] + 83 .loc 1 670 22 view .LVU14 + 84 000e 43F00203 orr r3, r3, #2 + 85 0012 D361 str r3, [r2, #28] + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** flags |= FLASH_FLAG_WRPERR; + 86 .loc 1 671 5 is_stmt 1 view .LVU15 + 87 .LVL2: + 88 .loc 1 671 11 is_stmt 0 view .LVU16 + 89 0014 1023 movs r3, #16 + 90 .LVL3: + 91 .L5: + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 92 .loc 1 673 3 is_stmt 1 view .LVU17 + 93 .loc 1 673 6 is_stmt 0 view .LVU18 + 94 0016 074A ldr r2, .L7 + 95 0018 D268 ldr r2, [r2, #12] + 96 .loc 1 673 5 view .LVU19 + 97 001a 12F0040F tst r2, #4 + 98 001e 06D0 beq .L6 + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + 99 .loc 1 675 5 is_stmt 1 view .LVU20 + 100 .loc 1 675 11 is_stmt 0 view .LVU21 + 101 0020 0549 ldr r1, .L7+4 + 102 0022 CA69 ldr r2, [r1, #28] + 103 .loc 1 675 22 view .LVU22 + 104 0024 42F00102 orr r2, r2, #1 + 105 0028 CA61 str r2, [r1, #28] + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** flags |= FLASH_FLAG_PGERR; + 106 .loc 1 676 5 is_stmt 1 view .LVU23 + 107 .loc 1 676 11 is_stmt 0 view .LVU24 + 108 002a 43F00403 orr r3, r3, #4 + 109 .LVL4: + 110 .L6: + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear FLASH error pending bits */ + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(flags); + 111 .loc 1 679 3 is_stmt 1 view .LVU25 + 112 002e 014A ldr r2, .L7 + 113 0030 D360 str r3, [r2, #12] + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 114 .loc 1 680 1 is_stmt 0 view .LVU26 + 115 0032 7047 bx lr + 116 .L8: + 117 .align 2 + 118 .L7: + 119 0034 00200240 .word 1073881088 + 120 0038 00000000 .word pFlash + 121 .cfi_endproc + ARM GAS /tmp/ccX3tCBb.s page 15 + + + 122 .LFE143: + 124 .section .text.HAL_FLASH_Program_IT,"ax",%progbits + 125 .align 1 + 126 .global HAL_FLASH_Program_IT + 127 .syntax unified + 128 .thumb + 129 .thumb_func + 131 HAL_FLASH_Program_IT: + 132 .LVL5: + 133 .LFB131: + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 134 .loc 1 241 1 is_stmt 1 view -0 + 135 .cfi_startproc + 136 @ args = 0, pretend = 0, frame = 0 + 137 @ frame_needed = 0, uses_anonymous_args = 0 + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 138 .loc 1 241 1 is_stmt 0 view .LVU28 + 139 0000 38B5 push {r3, r4, r5, lr} + 140 .cfi_def_cfa_offset 16 + 141 .cfi_offset 3, -16 + 142 .cfi_offset 4, -12 + 143 .cfi_offset 5, -8 + 144 .cfi_offset 14, -4 + 145 0002 1D46 mov r5, r3 + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 146 .loc 1 242 3 is_stmt 1 view .LVU29 + 147 .LVL6: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 148 .loc 1 245 3 view .LVU30 + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 149 .loc 1 245 3 view .LVU31 + 150 0004 174B ldr r3, .L18 + 151 0006 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 152 0008 012B cmp r3, #1 + 153 000a 28D0 beq .L14 + 154 000c 8446 mov ip, r0 + 155 000e 0846 mov r0, r1 + 156 .LVL7: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 157 .loc 1 245 3 is_stmt 0 view .LVU32 + 158 0010 1446 mov r4, r2 + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 159 .loc 1 245 3 is_stmt 1 discriminator 2 view .LVU33 + 160 0012 144B ldr r3, .L18 + 161 0014 0122 movs r2, #1 + 162 .LVL8: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 163 .loc 1 245 3 is_stmt 0 discriminator 2 view .LVU34 + 164 0016 1A76 strb r2, [r3, #24] + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 165 .loc 1 245 3 is_stmt 1 discriminator 2 view .LVU35 + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 166 .loc 1 248 3 discriminator 2 view .LVU36 + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 167 .loc 1 249 3 discriminator 2 view .LVU37 + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 168 .loc 1 252 3 discriminator 2 view .LVU38 + ARM GAS /tmp/ccX3tCBb.s page 16 + + + 169 0018 1349 ldr r1, .L18+4 + 170 .LVL9: + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 171 .loc 1 252 3 is_stmt 0 discriminator 2 view .LVU39 + 172 001a 0A69 ldr r2, [r1, #16] + 173 001c 42F4A052 orr r2, r2, #5120 + 174 0020 0A61 str r2, [r1, #16] + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Data = Data; + 175 .loc 1 254 3 is_stmt 1 discriminator 2 view .LVU40 + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Data = Data; + 176 .loc 1 254 18 is_stmt 0 discriminator 2 view .LVU41 + 177 0022 9860 str r0, [r3, #8] + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 178 .loc 1 255 3 is_stmt 1 discriminator 2 view .LVU42 + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 179 .loc 1 255 15 is_stmt 0 discriminator 2 view .LVU43 + 180 0024 C3E90445 strd r4, [r3, #16] + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 181 .loc 1 257 3 is_stmt 1 discriminator 2 view .LVU44 + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 182 .loc 1 257 5 is_stmt 0 discriminator 2 view .LVU45 + 183 0028 BCF1010F cmp ip, #1 + 184 002c 0CD0 beq .L16 + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 185 .loc 1 263 8 is_stmt 1 view .LVU46 + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 186 .loc 1 263 10 is_stmt 0 view .LVU47 + 187 002e BCF1020F cmp ip, #2 + 188 0032 0ED0 beq .L17 + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program double word (64-bit : 4*16-bit) at a specified address. */ + 189 .loc 1 271 5 is_stmt 1 view .LVU48 + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program double word (64-bit : 4*16-bit) at a specified address. */ + 190 .loc 1 271 29 is_stmt 0 view .LVU49 + 191 0034 0B4B ldr r3, .L18 + 192 0036 0522 movs r2, #5 + 193 0038 1A70 strb r2, [r3] + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 194 .loc 1 273 5 is_stmt 1 view .LVU50 + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 195 .loc 1 273 26 is_stmt 0 view .LVU51 + 196 003a 0422 movs r2, #4 + 197 003c 5A60 str r2, [r3, #4] + 198 .L12: + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 199 .loc 1 277 3 is_stmt 1 view .LVU52 + 200 003e A1B2 uxth r1, r4 + 201 0040 FFF7FEFF bl FLASH_Program_HalfWord + 202 .LVL10: + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 203 .loc 1 279 3 view .LVU53 + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 204 .loc 1 279 10 is_stmt 0 view .LVU54 + 205 0044 0020 movs r0, #0 + 206 .L10: + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 207 .loc 1 280 1 view .LVU55 + 208 0046 38BD pop {r3, r4, r5, pc} + ARM GAS /tmp/ccX3tCBb.s page 17 + + + 209 .LVL11: + 210 .L16: + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */ + 211 .loc 1 259 5 is_stmt 1 view .LVU56 + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */ + 212 .loc 1 259 29 is_stmt 0 view .LVU57 + 213 0048 0322 movs r2, #3 + 214 004a 1A70 strb r2, [r3] + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 215 .loc 1 261 5 is_stmt 1 view .LVU58 + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 216 .loc 1 261 26 is_stmt 0 view .LVU59 + 217 004c 0122 movs r2, #1 + 218 004e 5A60 str r2, [r3, #4] + 219 0050 F5E7 b .L12 + 220 .L17: + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program word (32-bit : 2*16-bit) at a specified address. */ + 221 .loc 1 265 5 is_stmt 1 view .LVU60 + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program word (32-bit : 2*16-bit) at a specified address. */ + 222 .loc 1 265 29 is_stmt 0 view .LVU61 + 223 0052 044B ldr r3, .L18 + 224 0054 0422 movs r2, #4 + 225 0056 1A70 strb r2, [r3] + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 226 .loc 1 267 5 is_stmt 1 view .LVU62 + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 227 .loc 1 267 26 is_stmt 0 view .LVU63 + 228 0058 0222 movs r2, #2 + 229 005a 5A60 str r2, [r3, #4] + 230 005c EFE7 b .L12 + 231 .LVL12: + 232 .L14: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 233 .loc 1 245 3 view .LVU64 + 234 005e 0220 movs r0, #2 + 235 .LVL13: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 236 .loc 1 245 3 view .LVU65 + 237 0060 F1E7 b .L10 + 238 .L19: + 239 0062 00BF .align 2 + 240 .L18: + 241 0064 00000000 .word pFlash + 242 0068 00200240 .word 1073881088 + 243 .cfi_endproc + 244 .LFE131: + 246 .section .text.HAL_FLASH_EndOfOperationCallback,"ax",%progbits + 247 .align 1 + 248 .weak HAL_FLASH_EndOfOperationCallback + 249 .syntax unified + 250 .thumb + 251 .thumb_func + 253 HAL_FLASH_EndOfOperationCallback: + 254 .LVL14: + 255 .LFB133: + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 256 .loc 1 430 1 is_stmt 1 view -0 + ARM GAS /tmp/ccX3tCBb.s page 18 + + + 257 .cfi_startproc + 258 @ args = 0, pretend = 0, frame = 0 + 259 @ frame_needed = 0, uses_anonymous_args = 0 + 260 @ link register save eliminated. + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 261 .loc 1 432 3 view .LVU67 + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 262 .loc 1 437 1 is_stmt 0 view .LVU68 + 263 0000 7047 bx lr + 264 .cfi_endproc + 265 .LFE133: + 267 .section .text.HAL_FLASH_OperationErrorCallback,"ax",%progbits + 268 .align 1 + 269 .weak HAL_FLASH_OperationErrorCallback + 270 .syntax unified + 271 .thumb + 272 .thumb_func + 274 HAL_FLASH_OperationErrorCallback: + 275 .LVL15: + 276 .LFB134: + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 277 .loc 1 448 1 is_stmt 1 view -0 + 278 .cfi_startproc + 279 @ args = 0, pretend = 0, frame = 0 + 280 @ frame_needed = 0, uses_anonymous_args = 0 + 281 @ link register save eliminated. + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 282 .loc 1 450 3 view .LVU70 + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 283 .loc 1 455 1 is_stmt 0 view .LVU71 + 284 0000 7047 bx lr + 285 .cfi_endproc + 286 .LFE134: + 288 .section .text.HAL_FLASH_IRQHandler,"ax",%progbits + 289 .align 1 + 290 .global HAL_FLASH_IRQHandler + 291 .syntax unified + 292 .thumb + 293 .thumb_func + 295 HAL_FLASH_IRQHandler: + 296 .LFB132: + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t addresstmp = 0U; + 297 .loc 1 287 1 is_stmt 1 view -0 + 298 .cfi_startproc + 299 @ args = 0, pretend = 0, frame = 0 + 300 @ frame_needed = 0, uses_anonymous_args = 0 + 301 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 302 .cfi_def_cfa_offset 24 + 303 .cfi_offset 3, -24 + 304 .cfi_offset 4, -20 + 305 .cfi_offset 5, -16 + 306 .cfi_offset 6, -12 + 307 .cfi_offset 7, -8 + 308 .cfi_offset 14, -4 + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 309 .loc 1 288 3 view .LVU73 + 310 .LVL16: + ARM GAS /tmp/ccX3tCBb.s page 19 + + + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 311 .loc 1 291 3 view .LVU74 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 312 .loc 1 291 6 is_stmt 0 view .LVU75 + 313 0002 524B ldr r3, .L40 + 314 0004 DB68 ldr r3, [r3, #12] + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 315 .loc 1 291 5 view .LVU76 + 316 0006 13F0100F tst r3, #16 + 317 000a 04D1 bne .L23 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 318 .loc 1 291 48 discriminator 1 view .LVU77 + 319 000c 4F4B ldr r3, .L40 + 320 000e DB68 ldr r3, [r3, #12] + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 321 .loc 1 291 46 discriminator 1 view .LVU78 + 322 0010 13F0040F tst r3, #4 + 323 0014 0BD0 beq .L24 + 324 .L23: + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Reset address */ + 325 .loc 1 294 5 is_stmt 1 view .LVU79 + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Reset address */ + 326 .loc 1 294 16 is_stmt 0 view .LVU80 + 327 0016 4E4C ldr r4, .L40+4 + 328 0018 A568 ldr r5, [r4, #8] + 329 .LVL17: + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 330 .loc 1 296 5 is_stmt 1 view .LVU81 + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 331 .loc 1 296 20 is_stmt 0 view .LVU82 + 332 001a 4FF0FF33 mov r3, #-1 + 333 001e A360 str r3, [r4, #8] + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 334 .loc 1 299 5 is_stmt 1 view .LVU83 + 335 0020 FFF7FEFF bl FLASH_SetErrorCode + 336 .LVL18: + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 337 .loc 1 302 5 view .LVU84 + 338 0024 2846 mov r0, r5 + 339 0026 FFF7FEFF bl HAL_FLASH_OperationErrorCallback + 340 .LVL19: + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 341 .loc 1 305 5 view .LVU85 + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 342 .loc 1 305 29 is_stmt 0 view .LVU86 + 343 002a 0023 movs r3, #0 + 344 002c 2370 strb r3, [r4] + 345 .LVL20: + 346 .L24: + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 347 .loc 1 309 3 is_stmt 1 view .LVU87 + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 348 .loc 1 309 6 is_stmt 0 view .LVU88 + 349 002e 474B ldr r3, .L40 + 350 0030 DB68 ldr r3, [r3, #12] + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 351 .loc 1 309 5 view .LVU89 + ARM GAS /tmp/ccX3tCBb.s page 20 + + + 352 0032 13F0200F tst r3, #32 + 353 0036 2BD0 beq .L25 + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 354 .loc 1 312 5 is_stmt 1 view .LVU90 + 355 0038 444B ldr r3, .L40 + 356 003a 2022 movs r2, #32 + 357 003c DA60 str r2, [r3, #12] + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 358 .loc 1 315 5 view .LVU91 + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 359 .loc 1 315 14 is_stmt 0 view .LVU92 + 360 003e 444B ldr r3, .L40+4 + 361 0040 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 362 .loc 1 315 7 view .LVU93 + 363 0042 2BB3 cbz r3, .L25 + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 364 .loc 1 317 7 is_stmt 1 view .LVU94 + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 365 .loc 1 317 16 is_stmt 0 view .LVU95 + 366 0044 424B ldr r3, .L40+4 + 367 0046 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 368 0048 DBB2 uxtb r3, r3 + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 369 .loc 1 317 9 view .LVU96 + 370 004a 012B cmp r3, #1 + 371 004c 30D0 beq .L35 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 372 .loc 1 348 12 is_stmt 1 view .LVU97 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 373 .loc 1 348 21 is_stmt 0 view .LVU98 + 374 004e 404B ldr r3, .L40+4 + 375 0050 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 376 0052 DBB2 uxtb r3, r3 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 377 .loc 1 348 14 view .LVU99 + 378 0054 022B cmp r3, #2 + 379 0056 4AD0 beq .L36 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 380 .loc 1 363 9 is_stmt 1 view .LVU100 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 381 .loc 1 363 15 is_stmt 0 view .LVU101 + 382 0058 3D4B ldr r3, .L40+4 + 383 005a 5A68 ldr r2, [r3, #4] + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 384 .loc 1 363 29 view .LVU102 + 385 005c 013A subs r2, r2, #1 + 386 005e 5A60 str r2, [r3, #4] + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 387 .loc 1 366 9 is_stmt 1 view .LVU103 + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 388 .loc 1 366 18 is_stmt 0 view .LVU104 + 389 0060 5B68 ldr r3, [r3, #4] + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 390 .loc 1 366 11 view .LVU105 + 391 0062 002B cmp r3, #0 + 392 0064 4FD1 bne .L37 + ARM GAS /tmp/ccX3tCBb.s page 21 + + + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 393 .loc 1 385 11 is_stmt 1 view .LVU106 + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 394 .loc 1 385 21 is_stmt 0 view .LVU107 + 395 0066 3A4B ldr r3, .L40+4 + 396 0068 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 397 006a DBB2 uxtb r3, r3 + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 398 .loc 1 385 14 view .LVU108 + 399 006c 032B cmp r3, #3 + 400 006e 62D0 beq .L38 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 401 .loc 1 389 16 is_stmt 1 view .LVU109 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 402 .loc 1 389 26 is_stmt 0 view .LVU110 + 403 0070 374B ldr r3, .L40+4 + 404 0072 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 405 0074 DBB2 uxtb r3, r3 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 406 .loc 1 389 19 view .LVU111 + 407 0076 042B cmp r3, #4 + 408 0078 62D0 beq .L39 + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 409 .loc 1 395 13 is_stmt 1 view .LVU112 + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 410 .loc 1 395 52 is_stmt 0 view .LVU113 + 411 007a 354B ldr r3, .L40+4 + 412 007c 9868 ldr r0, [r3, #8] + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 413 .loc 1 395 13 view .LVU114 + 414 007e 0638 subs r0, r0, #6 + 415 0080 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 416 .LVL21: + 417 .L31: + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 418 .loc 1 399 11 is_stmt 1 view .LVU115 + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 419 .loc 1 399 26 is_stmt 0 view .LVU116 + 420 0084 324B ldr r3, .L40+4 + 421 0086 4FF0FF32 mov r2, #-1 + 422 008a 9A60 str r2, [r3, #8] + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 423 .loc 1 400 11 is_stmt 1 view .LVU117 + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 424 .loc 1 400 35 is_stmt 0 view .LVU118 + 425 008c 0022 movs r2, #0 + 426 008e 1A70 strb r2, [r3] + 427 .L25: + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 428 .loc 1 407 3 is_stmt 1 view .LVU119 + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 429 .loc 1 407 12 is_stmt 0 view .LVU120 + 430 0090 2F4B ldr r3, .L40+4 + 431 0092 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 432 .loc 1 407 5 view .LVU121 + 433 0094 5BB9 cbnz r3, .L22 + ARM GAS /tmp/ccX3tCBb.s page 22 + + + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 434 .loc 1 410 5 is_stmt 1 view .LVU122 + 435 0096 2D4B ldr r3, .L40 + 436 0098 1A69 ldr r2, [r3, #16] + 437 009a 22F00702 bic r2, r2, #7 + 438 009e 1A61 str r2, [r3, #16] + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 439 .loc 1 413 5 view .LVU123 + 440 00a0 1A69 ldr r2, [r3, #16] + 441 00a2 22F4A052 bic r2, r2, #5120 + 442 00a6 1A61 str r2, [r3, #16] + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 443 .loc 1 416 5 view .LVU124 + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 444 .loc 1 416 5 view .LVU125 + 445 00a8 294B ldr r3, .L40+4 + 446 00aa 0022 movs r2, #0 + 447 00ac 1A76 strb r2, [r3, #24] + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 448 .loc 1 416 5 view .LVU126 + 449 .L22: + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 450 .loc 1 418 1 is_stmt 0 view .LVU127 + 451 00ae F8BD pop {r3, r4, r5, r6, r7, pc} + 452 .L35: + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 453 .loc 1 320 9 is_stmt 1 view .LVU128 + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 454 .loc 1 320 15 is_stmt 0 view .LVU129 + 455 00b0 274B ldr r3, .L40+4 + 456 00b2 5A68 ldr r2, [r3, #4] + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 457 .loc 1 320 29 view .LVU130 + 458 00b4 013A subs r2, r2, #1 + 459 00b6 5A60 str r2, [r3, #4] + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 460 .loc 1 323 9 is_stmt 1 view .LVU131 + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 461 .loc 1 323 18 is_stmt 0 view .LVU132 + 462 00b8 5B68 ldr r3, [r3, #4] + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 463 .loc 1 323 11 view .LVU133 + 464 00ba 7BB1 cbz r3, .L27 + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Indicate user which sector has been erased */ + 465 .loc 1 325 11 is_stmt 1 view .LVU134 + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Indicate user which sector has been erased */ + 466 .loc 1 325 22 is_stmt 0 view .LVU135 + 467 00bc 244C ldr r4, .L40+4 + 468 00be A068 ldr r0, [r4, #8] + 469 .LVL22: + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 470 .loc 1 327 11 is_stmt 1 view .LVU136 + 471 00c0 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 472 .LVL23: + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp; + 473 .loc 1 330 11 view .LVU137 + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp; + ARM GAS /tmp/ccX3tCBb.s page 23 + + + 474 .loc 1 330 30 is_stmt 0 view .LVU138 + 475 00c4 A068 ldr r0, [r4, #8] + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp; + 476 .loc 1 330 22 view .LVU139 + 477 00c6 00F50060 add r0, r0, #2048 + 478 .LVL24: + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 479 .loc 1 331 11 is_stmt 1 view .LVU140 + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 480 .loc 1 331 26 is_stmt 0 view .LVU141 + 481 00ca A060 str r0, [r4, #8] + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 482 .loc 1 334 11 is_stmt 1 view .LVU142 + 483 00cc 1F4A ldr r2, .L40 + 484 00ce 1369 ldr r3, [r2, #16] + 485 00d0 23F00203 bic r3, r3, #2 + 486 00d4 1361 str r3, [r2, #16] + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 487 .loc 1 336 11 view .LVU143 + 488 00d6 FFF7FEFF bl FLASH_PageErase + 489 .LVL25: + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 490 .loc 1 336 11 is_stmt 0 view .LVU144 + 491 00da D9E7 b .L25 + 492 .LVL26: + 493 .L27: + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 494 .loc 1 342 11 is_stmt 1 view .LVU145 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 495 .loc 1 342 26 is_stmt 0 view .LVU146 + 496 00dc 1C4B ldr r3, .L40+4 + 497 00de 4FF0FF30 mov r0, #-1 + 498 00e2 9860 str r0, [r3, #8] + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 499 .loc 1 343 11 is_stmt 1 view .LVU147 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 500 .loc 1 343 35 is_stmt 0 view .LVU148 + 501 00e4 0022 movs r2, #0 + 502 00e6 1A70 strb r2, [r3] + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 503 .loc 1 345 11 is_stmt 1 view .LVU149 + 504 00e8 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 505 .LVL27: + 506 00ec D0E7 b .L25 + 507 .LVL28: + 508 .L36: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 509 .loc 1 351 9 view .LVU150 + 510 00ee 174A ldr r2, .L40 + 511 00f0 1369 ldr r3, [r2, #16] + 512 00f2 23F00403 bic r3, r3, #4 + 513 00f6 1361 str r3, [r2, #16] + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 514 .loc 1 355 11 view .LVU151 + 515 00f8 0020 movs r0, #0 + 516 00fa FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 517 .LVL29: + ARM GAS /tmp/ccX3tCBb.s page 24 + + + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 518 .loc 1 358 11 view .LVU152 + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 519 .loc 1 358 35 is_stmt 0 view .LVU153 + 520 00fe 144B ldr r3, .L40+4 + 521 0100 0022 movs r2, #0 + 522 0102 1A70 strb r2, [r3] + 523 0104 C4E7 b .L25 + 524 .L37: + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 525 .loc 1 369 11 is_stmt 1 view .LVU154 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 526 .loc 1 369 17 is_stmt 0 view .LVU155 + 527 0106 124B ldr r3, .L40+4 + 528 0108 9A68 ldr r2, [r3, #8] + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 529 .loc 1 369 26 view .LVU156 + 530 010a 0232 adds r2, r2, #2 + 531 010c 9A60 str r2, [r3, #8] + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 532 .loc 1 370 11 is_stmt 1 view .LVU157 + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 533 .loc 1 370 22 is_stmt 0 view .LVU158 + 534 010e 9868 ldr r0, [r3, #8] + 535 .LVL30: + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 536 .loc 1 373 11 is_stmt 1 view .LVU159 + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 537 .loc 1 373 32 is_stmt 0 view .LVU160 + 538 0110 D3E90467 ldrd r6, [r3, #16] + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 539 .loc 1 373 38 view .LVU161 + 540 0114 340C lsrs r4, r6, #16 + 541 0116 44EA0744 orr r4, r4, r7, lsl #16 + 542 011a 3D0C lsrs r5, r7, #16 + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 543 .loc 1 373 23 view .LVU162 + 544 011c C3E90445 strd r4, [r3, #16] + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 545 .loc 1 376 11 is_stmt 1 view .LVU163 + 546 0120 0A49 ldr r1, .L40 + 547 0122 0A69 ldr r2, [r1, #16] + 548 0124 22F00102 bic r2, r2, #1 + 549 0128 0A61 str r2, [r1, #16] + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 550 .loc 1 379 11 view .LVU164 + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 551 .loc 1 379 62 is_stmt 0 view .LVU165 + 552 012a D3E90423 ldrd r2, [r3, #16] + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 553 .loc 1 379 11 view .LVU166 + 554 012e 91B2 uxth r1, r2 + 555 0130 FFF7FEFF bl FLASH_Program_HalfWord + 556 .LVL31: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 557 .loc 1 379 11 view .LVU167 + 558 0134 ACE7 b .L25 + ARM GAS /tmp/ccX3tCBb.s page 25 + + + 559 .LVL32: + 560 .L38: + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 561 .loc 1 387 13 is_stmt 1 view .LVU168 + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 562 .loc 1 387 52 is_stmt 0 view .LVU169 + 563 0136 064B ldr r3, .L40+4 + 564 0138 9868 ldr r0, [r3, #8] + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 565 .loc 1 387 13 view .LVU170 + 566 013a FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 567 .LVL33: + 568 013e A1E7 b .L31 + 569 .L39: + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 570 .loc 1 391 13 is_stmt 1 view .LVU171 + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 571 .loc 1 391 52 is_stmt 0 view .LVU172 + 572 0140 034B ldr r3, .L40+4 + 573 0142 9868 ldr r0, [r3, #8] + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 574 .loc 1 391 13 view .LVU173 + 575 0144 0238 subs r0, r0, #2 + 576 0146 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 577 .LVL34: + 578 014a 9BE7 b .L31 + 579 .L41: + 580 .align 2 + 581 .L40: + 582 014c 00200240 .word 1073881088 + 583 0150 00000000 .word pFlash + 584 .cfi_endproc + 585 .LFE132: + 587 .section .text.HAL_FLASH_Unlock,"ax",%progbits + 588 .align 1 + 589 .global HAL_FLASH_Unlock + 590 .syntax unified + 591 .thumb + 592 .thumb_func + 594 HAL_FLASH_Unlock: + 595 .LFB135: + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 596 .loc 1 481 1 is_stmt 1 view -0 + 597 .cfi_startproc + 598 @ args = 0, pretend = 0, frame = 0 + 599 @ frame_needed = 0, uses_anonymous_args = 0 + 600 @ link register save eliminated. + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 601 .loc 1 482 3 view .LVU175 + 602 .LVL35: + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 603 .loc 1 484 3 view .LVU176 + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 604 .loc 1 484 6 is_stmt 0 view .LVU177 + 605 0000 0A4B ldr r3, .L46 + 606 0002 1B69 ldr r3, [r3, #16] + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + ARM GAS /tmp/ccX3tCBb.s page 26 + + + 607 .loc 1 484 5 view .LVU178 + 608 0004 13F0800F tst r3, #128 + 609 0008 0BD0 beq .L44 + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY2); + 610 .loc 1 487 5 is_stmt 1 view .LVU179 + 611 000a 084B ldr r3, .L46 + 612 000c 084A ldr r2, .L46+4 + 613 000e 5A60 str r2, [r3, #4] + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 614 .loc 1 488 5 view .LVU180 + 615 0010 02F18832 add r2, r2, #-2004318072 + 616 0014 5A60 str r2, [r3, #4] + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 617 .loc 1 491 5 view .LVU181 + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 618 .loc 1 491 8 is_stmt 0 view .LVU182 + 619 0016 1B69 ldr r3, [r3, #16] + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 620 .loc 1 491 7 view .LVU183 + 621 0018 13F0800F tst r3, #128 + 622 001c 03D1 bne .L45 + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 623 .loc 1 482 21 view .LVU184 + 624 001e 0020 movs r0, #0 + 625 0020 7047 bx lr + 626 .L44: + 627 0022 0020 movs r0, #0 + 628 0024 7047 bx lr + 629 .L45: + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 630 .loc 1 493 14 view .LVU185 + 631 0026 0120 movs r0, #1 + 632 .LVL36: + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 633 .loc 1 497 3 is_stmt 1 view .LVU186 + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 634 .loc 1 498 1 is_stmt 0 view .LVU187 + 635 0028 7047 bx lr + 636 .L47: + 637 002a 00BF .align 2 + 638 .L46: + 639 002c 00200240 .word 1073881088 + 640 0030 23016745 .word 1164378403 + 641 .cfi_endproc + 642 .LFE135: + 644 .section .text.HAL_FLASH_Lock,"ax",%progbits + 645 .align 1 + 646 .global HAL_FLASH_Lock + 647 .syntax unified + 648 .thumb + 649 .thumb_func + 651 HAL_FLASH_Lock: + 652 .LFB136: + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Set the LOCK Bit to lock the FLASH Registers access */ + 653 .loc 1 505 1 is_stmt 1 view -0 + 654 .cfi_startproc + 655 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccX3tCBb.s page 27 + + + 656 @ frame_needed = 0, uses_anonymous_args = 0 + 657 @ link register save eliminated. + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 658 .loc 1 507 3 view .LVU189 + 659 0000 034A ldr r2, .L49 + 660 0002 1369 ldr r3, [r2, #16] + 661 0004 43F08003 orr r3, r3, #128 + 662 0008 1361 str r3, [r2, #16] + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 663 .loc 1 509 3 view .LVU190 + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 664 .loc 1 510 1 is_stmt 0 view .LVU191 + 665 000a 0020 movs r0, #0 + 666 000c 7047 bx lr + 667 .L50: + 668 000e 00BF .align 2 + 669 .L49: + 670 0010 00200240 .word 1073881088 + 671 .cfi_endproc + 672 .LFE136: + 674 .section .text.HAL_FLASH_OB_Unlock,"ax",%progbits + 675 .align 1 + 676 .global HAL_FLASH_OB_Unlock + 677 .syntax unified + 678 .thumb + 679 .thumb_func + 681 HAL_FLASH_OB_Unlock: + 682 .LFB137: + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + 683 .loc 1 517 1 is_stmt 1 view -0 + 684 .cfi_startproc + 685 @ args = 0, pretend = 0, frame = 0 + 686 @ frame_needed = 0, uses_anonymous_args = 0 + 687 @ link register save eliminated. + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 688 .loc 1 518 3 view .LVU193 + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 689 .loc 1 518 7 is_stmt 0 view .LVU194 + 690 0000 074B ldr r3, .L54 + 691 0002 1B69 ldr r3, [r3, #16] + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 692 .loc 1 518 6 view .LVU195 + 693 0004 13F4007F tst r3, #512 + 694 0008 07D1 bne .L53 + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + 695 .loc 1 521 5 is_stmt 1 view .LVU196 + 696 000a 054B ldr r3, .L54 + 697 000c 054A ldr r2, .L54+4 + 698 000e 9A60 str r2, [r3, #8] + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 699 .loc 1 522 5 view .LVU197 + 700 0010 02F18832 add r2, r2, #-2004318072 + 701 0014 9A60 str r2, [r3, #8] + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 702 .loc 1 529 3 view .LVU198 + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 703 .loc 1 529 10 is_stmt 0 view .LVU199 + ARM GAS /tmp/ccX3tCBb.s page 28 + + + 704 0016 0020 movs r0, #0 + 705 0018 7047 bx lr + 706 .L53: + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 707 .loc 1 526 12 view .LVU200 + 708 001a 0120 movs r0, #1 + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 709 .loc 1 530 1 view .LVU201 + 710 001c 7047 bx lr + 711 .L55: + 712 001e 00BF .align 2 + 713 .L54: + 714 0020 00200240 .word 1073881088 + 715 0024 23016745 .word 1164378403 + 716 .cfi_endproc + 717 .LFE137: + 719 .section .text.HAL_FLASH_OB_Lock,"ax",%progbits + 720 .align 1 + 721 .global HAL_FLASH_OB_Lock + 722 .syntax unified + 723 .thumb + 724 .thumb_func + 726 HAL_FLASH_OB_Lock: + 727 .LFB138: + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + 728 .loc 1 537 1 is_stmt 1 view -0 + 729 .cfi_startproc + 730 @ args = 0, pretend = 0, frame = 0 + 731 @ frame_needed = 0, uses_anonymous_args = 0 + 732 @ link register save eliminated. + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 733 .loc 1 539 3 view .LVU203 + 734 0000 034A ldr r2, .L57 + 735 0002 1369 ldr r3, [r2, #16] + 736 0004 23F40073 bic r3, r3, #512 + 737 0008 1361 str r3, [r2, #16] + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 738 .loc 1 541 3 view .LVU204 + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 739 .loc 1 542 1 is_stmt 0 view .LVU205 + 740 000a 0020 movs r0, #0 + 741 000c 7047 bx lr + 742 .L58: + 743 000e 00BF .align 2 + 744 .L57: + 745 0010 00200240 .word 1073881088 + 746 .cfi_endproc + 747 .LFE138: + 749 .section .text.HAL_FLASH_GetError,"ax",%progbits + 750 .align 1 + 751 .global HAL_FLASH_GetError + 752 .syntax unified + 753 .thumb + 754 .thumb_func + 756 HAL_FLASH_GetError: + 757 .LFB140: + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return pFlash.ErrorCode; + ARM GAS /tmp/ccX3tCBb.s page 29 + + + 758 .loc 1 582 1 is_stmt 1 view -0 + 759 .cfi_startproc + 760 @ args = 0, pretend = 0, frame = 0 + 761 @ frame_needed = 0, uses_anonymous_args = 0 + 762 @ link register save eliminated. + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 763 .loc 1 583 4 view .LVU207 + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 764 .loc 1 583 17 is_stmt 0 view .LVU208 + 765 0000 014B ldr r3, .L60 + 766 0002 D869 ldr r0, [r3, #28] + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 767 .loc 1 584 1 view .LVU209 + 768 0004 7047 bx lr + 769 .L61: + 770 0006 00BF .align 2 + 771 .L60: + 772 0008 00000000 .word pFlash + 773 .cfi_endproc + 774 .LFE140: + 776 .section .text.FLASH_WaitForLastOperation,"ax",%progbits + 777 .align 1 + 778 .global FLASH_WaitForLastOperation + 779 .syntax unified + 780 .thumb + 781 .thumb_func + 783 FLASH_WaitForLastOperation: + 784 .LVL37: + 785 .LFB142: + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + 786 .loc 1 622 1 is_stmt 1 view -0 + 787 .cfi_startproc + 788 @ args = 0, pretend = 0, frame = 0 + 789 @ frame_needed = 0, uses_anonymous_args = 0 + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + 790 .loc 1 622 1 is_stmt 0 view .LVU211 + 791 0000 38B5 push {r3, r4, r5, lr} + 792 .cfi_def_cfa_offset 16 + 793 .cfi_offset 3, -16 + 794 .cfi_offset 4, -12 + 795 .cfi_offset 5, -8 + 796 .cfi_offset 14, -4 + 797 0002 0446 mov r4, r0 + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 798 .loc 1 627 3 is_stmt 1 view .LVU212 + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 799 .loc 1 627 24 is_stmt 0 view .LVU213 + 800 0004 FFF7FEFF bl HAL_GetTick + 801 .LVL38: + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 802 .loc 1 627 24 view .LVU214 + 803 0008 0546 mov r5, r0 + 804 .LVL39: + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 805 .loc 1 629 3 is_stmt 1 view .LVU215 + 806 .L64: + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + ARM GAS /tmp/ccX3tCBb.s page 30 + + + 807 .loc 1 629 9 view .LVU216 + 808 000a 144B ldr r3, .L73 + 809 000c DB68 ldr r3, [r3, #12] + 810 000e 13F0010F tst r3, #1 + 811 0012 0AD0 beq .L72 + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 812 .loc 1 631 5 view .LVU217 + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 813 .loc 1 631 8 is_stmt 0 view .LVU218 + 814 0014 B4F1FF3F cmp r4, #-1 + 815 0018 F7D0 beq .L64 + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 816 .loc 1 633 7 is_stmt 1 view .LVU219 + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 817 .loc 1 633 9 is_stmt 0 view .LVU220 + 818 001a 24B1 cbz r4, .L65 + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 819 .loc 1 633 31 discriminator 1 view .LVU221 + 820 001c FFF7FEFF bl HAL_GetTick + 821 .LVL40: + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 822 .loc 1 633 44 discriminator 1 view .LVU222 + 823 0020 401B subs r0, r0, r5 + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 824 .loc 1 633 26 discriminator 1 view .LVU223 + 825 0022 A042 cmp r0, r4 + 826 0024 F1D9 bls .L64 + 827 .L65: + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 828 .loc 1 635 9 is_stmt 1 view .LVU224 + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 829 .loc 1 635 16 is_stmt 0 view .LVU225 + 830 0026 0320 movs r0, #3 + 831 0028 12E0 b .L66 + 832 .L72: + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 833 .loc 1 641 3 is_stmt 1 view .LVU226 + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 834 .loc 1 641 7 is_stmt 0 view .LVU227 + 835 002a 0C4B ldr r3, .L73 + 836 002c DB68 ldr r3, [r3, #12] + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 837 .loc 1 641 6 view .LVU228 + 838 002e 13F0200F tst r3, #32 + 839 0032 02D0 beq .L68 + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 840 .loc 1 644 5 is_stmt 1 view .LVU229 + 841 0034 094B ldr r3, .L73 + 842 0036 2022 movs r2, #32 + 843 0038 DA60 str r2, [r3, #12] + 844 .L68: + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 845 .loc 1 647 3 view .LVU230 + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 846 .loc 1 647 6 is_stmt 0 view .LVU231 + 847 003a 084B ldr r3, .L73 + 848 003c DB68 ldr r3, [r3, #12] + ARM GAS /tmp/ccX3tCBb.s page 31 + + + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 849 .loc 1 647 5 view .LVU232 + 850 003e 13F0100F tst r3, #16 + 851 0042 06D1 bne .L69 + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 852 .loc 1 648 6 discriminator 1 view .LVU233 + 853 0044 054B ldr r3, .L73 + 854 0046 DB68 ldr r3, [r3, #12] + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 855 .loc 1 647 47 discriminator 1 view .LVU234 + 856 0048 13F0040F tst r3, #4 + 857 004c 01D1 bne .L69 + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 858 .loc 1 656 10 view .LVU235 + 859 004e 0020 movs r0, #0 + 860 .L66: + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 861 .loc 1 657 1 view .LVU236 + 862 0050 38BD pop {r3, r4, r5, pc} + 863 .LVL41: + 864 .L69: + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_ERROR; + 865 .loc 1 651 5 is_stmt 1 view .LVU237 + 866 0052 FFF7FEFF bl FLASH_SetErrorCode + 867 .LVL42: + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 868 .loc 1 652 5 view .LVU238 + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 869 .loc 1 652 12 is_stmt 0 view .LVU239 + 870 0056 0120 movs r0, #1 + 871 0058 FAE7 b .L66 + 872 .L74: + 873 005a 00BF .align 2 + 874 .L73: + 875 005c 00200240 .word 1073881088 + 876 .cfi_endproc + 877 .LFE142: + 879 .section .text.HAL_FLASH_Program,"ax",%progbits + 880 .align 1 + 881 .global HAL_FLASH_Program + 882 .syntax unified + 883 .thumb + 884 .thumb_func + 886 HAL_FLASH_Program: + 887 .LVL43: + 888 .LFB130: + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 889 .loc 1 169 1 is_stmt 1 view -0 + 890 .cfi_startproc + 891 @ args = 0, pretend = 0, frame = 0 + 892 @ frame_needed = 0, uses_anonymous_args = 0 + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 893 .loc 1 169 1 is_stmt 0 view .LVU241 + 894 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 895 .cfi_def_cfa_offset 32 + 896 .cfi_offset 3, -32 + 897 .cfi_offset 4, -28 + ARM GAS /tmp/ccX3tCBb.s page 32 + + + 898 .cfi_offset 5, -24 + 899 .cfi_offset 6, -20 + 900 .cfi_offset 7, -16 + 901 .cfi_offset 8, -12 + 902 .cfi_offset 9, -8 + 903 .cfi_offset 14, -4 + 904 0004 1E46 mov r6, r3 + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint8_t index = 0U; + 905 .loc 1 170 3 is_stmt 1 view .LVU242 + 906 .LVL44: + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint8_t nbiterations = 0U; + 907 .loc 1 171 3 view .LVU243 + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 908 .loc 1 172 3 view .LVU244 + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 909 .loc 1 175 3 view .LVU245 + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 910 .loc 1 175 3 view .LVU246 + 911 0006 244B ldr r3, .L87 + 912 0008 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 913 000a 012B cmp r3, #1 + 914 000c 41D0 beq .L81 + 915 000e 0446 mov r4, r0 + 916 0010 0F46 mov r7, r1 + 917 0012 9046 mov r8, r2 + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 918 .loc 1 175 3 discriminator 2 view .LVU247 + 919 0014 204B ldr r3, .L87 + 920 0016 0122 movs r2, #1 + 921 .LVL45: + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 922 .loc 1 175 3 is_stmt 0 discriminator 2 view .LVU248 + 923 0018 1A76 strb r2, [r3, #24] + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 924 .loc 1 175 3 is_stmt 1 discriminator 2 view .LVU249 + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 925 .loc 1 178 3 discriminator 2 view .LVU250 + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 926 .loc 1 179 3 discriminator 2 view .LVU251 + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 927 .loc 1 182 5 discriminator 2 view .LVU252 + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 928 .loc 1 182 14 is_stmt 0 discriminator 2 view .LVU253 + 929 001a 4CF25030 movw r0, #50000 + 930 .LVL46: + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 931 .loc 1 182 14 discriminator 2 view .LVU254 + 932 001e FFF7FEFF bl FLASH_WaitForLastOperation + 933 .LVL47: + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 934 .loc 1 184 3 is_stmt 1 discriminator 2 view .LVU255 + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 935 .loc 1 184 5 is_stmt 0 discriminator 2 view .LVU256 + 936 0022 0346 mov r3, r0 + 937 0024 78BB cbnz r0, .L77 + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 938 .loc 1 186 5 is_stmt 1 view .LVU257 + ARM GAS /tmp/ccX3tCBb.s page 33 + + + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 939 .loc 1 186 7 is_stmt 0 view .LVU258 + 940 0026 012C cmp r4, #1 + 941 0028 08D0 beq .L82 + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 942 .loc 1 191 10 is_stmt 1 view .LVU259 + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 943 .loc 1 191 12 is_stmt 0 view .LVU260 + 944 002a 022C cmp r4, #2 + 945 002c 03D0 beq .L85 + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 946 .loc 1 199 20 view .LVU261 + 947 002e 4FF00409 mov r9, #4 + 948 .L78: + 949 .LVL48: + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 950 .loc 1 202 5 is_stmt 1 view .LVU262 + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 951 .loc 1 202 16 is_stmt 0 view .LVU263 + 952 0032 1C46 mov r4, r3 + 953 .LVL49: + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 954 .loc 1 202 5 view .LVU264 + 955 0034 07E0 b .L79 + 956 .LVL50: + 957 .L85: + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 958 .loc 1 194 20 view .LVU265 + 959 0036 4FF00209 mov r9, #2 + 960 003a FAE7 b .L78 + 961 .L82: + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 962 .loc 1 189 20 view .LVU266 + 963 003c 4FF00109 mov r9, #1 + 964 0040 F7E7 b .L78 + 965 .LVL51: + 966 .L86: + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 967 .loc 1 202 49 is_stmt 1 discriminator 2 view .LVU267 + 968 0042 0134 adds r4, r4, #1 + 969 .LVL52: + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 970 .loc 1 202 49 is_stmt 0 discriminator 2 view .LVU268 + 971 0044 E4B2 uxtb r4, r4 + 972 .LVL53: + 973 .L79: + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 974 .loc 1 202 28 is_stmt 1 discriminator 1 view .LVU269 + 975 0046 4C45 cmp r4, r9 + 976 0048 1DD2 bcs .L77 + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 977 .loc 1 204 7 view .LVU270 + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 978 .loc 1 204 77 is_stmt 0 view .LVU271 + 979 004a 2101 lsls r1, r4, #4 + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 980 .loc 1 204 70 view .LVU272 + ARM GAS /tmp/ccX3tCBb.s page 34 + + + 981 004c C1F12002 rsb r2, r1, #32 + 982 0050 A1F12003 sub r3, r1, #32 + 983 .LVL54: + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 984 .loc 1 204 70 view .LVU273 + 985 0054 28FA01F1 lsr r1, r8, r1 + 986 0058 06FA02F2 lsl r2, r6, r2 + 987 005c 1143 orrs r1, r1, r2 + 988 005e 26FA03F3 lsr r3, r6, r3 + 989 0062 1943 orrs r1, r1, r3 + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 990 .loc 1 204 7 view .LVU274 + 991 0064 89B2 uxth r1, r1 + 992 0066 07EB4400 add r0, r7, r4, lsl #1 + 993 006a FFF7FEFF bl FLASH_Program_HalfWord + 994 .LVL55: + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 995 .loc 1 207 9 is_stmt 1 view .LVU275 + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 996 .loc 1 207 18 is_stmt 0 view .LVU276 + 997 006e 4CF25030 movw r0, #50000 + 998 0072 FFF7FEFF bl FLASH_WaitForLastOperation + 999 .LVL56: + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* In case of error, stop programming procedure */ + 1000 .loc 1 210 9 is_stmt 1 view .LVU277 + 1001 0076 094B ldr r3, .L87+4 + 1002 0078 1D69 ldr r5, [r3, #16] + 1003 007a 25F00105 bic r5, r5, #1 + 1004 007e 1D61 str r5, [r3, #16] + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 1005 .loc 1 212 7 view .LVU278 + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 1006 .loc 1 212 10 is_stmt 0 view .LVU279 + 1007 0080 0346 mov r3, r0 + 1008 0082 0028 cmp r0, #0 + 1009 0084 DDD0 beq .L86 + 1010 .LVL57: + 1011 .L77: + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 1012 .loc 1 220 3 is_stmt 1 view .LVU280 + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 1013 .loc 1 220 3 view .LVU281 + 1014 0086 044A ldr r2, .L87 + 1015 0088 0021 movs r1, #0 + 1016 008a 1176 strb r1, [r2, #24] + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 1017 .loc 1 220 3 view .LVU282 + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 1018 .loc 1 222 3 view .LVU283 + 1019 .LVL58: + 1020 .L76: + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 1021 .loc 1 223 1 is_stmt 0 view .LVU284 + 1022 008c 1846 mov r0, r3 + 1023 008e BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 1024 .LVL59: + 1025 .L81: + ARM GAS /tmp/ccX3tCBb.s page 35 + + + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 1026 .loc 1 175 3 view .LVU285 + 1027 0092 0223 movs r3, #2 + 1028 0094 FAE7 b .L76 + 1029 .L88: + 1030 0096 00BF .align 2 + 1031 .L87: + 1032 0098 00000000 .word pFlash + 1033 009c 00200240 .word 1073881088 + 1034 .cfi_endproc + 1035 .LFE130: + 1037 .section .text.HAL_FLASH_OB_Launch,"ax",%progbits + 1038 .align 1 + 1039 .global HAL_FLASH_OB_Launch + 1040 .syntax unified + 1041 .thumb + 1042 .thumb_func + 1044 HAL_FLASH_OB_Launch: + 1045 .LFB139: + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Set the OBL_Launch bit to launch the option byte loading */ + 1046 .loc 1 550 1 is_stmt 1 view -0 + 1047 .cfi_startproc + 1048 @ args = 0, pretend = 0, frame = 0 + 1049 @ frame_needed = 0, uses_anonymous_args = 0 + 1050 0000 08B5 push {r3, lr} + 1051 .cfi_def_cfa_offset 8 + 1052 .cfi_offset 3, -8 + 1053 .cfi_offset 14, -4 + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 1054 .loc 1 552 3 view .LVU287 + 1055 0002 054A ldr r2, .L91 + 1056 0004 1369 ldr r3, [r2, #16] + 1057 0006 43F40053 orr r3, r3, #8192 + 1058 000a 1361 str r3, [r2, #16] + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 1059 .loc 1 555 3 view .LVU288 + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 1060 .loc 1 555 10 is_stmt 0 view .LVU289 + 1061 000c 4CF25030 movw r0, #50000 + 1062 0010 FFF7FEFF bl FLASH_WaitForLastOperation + 1063 .LVL60: + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 1064 .loc 1 556 1 view .LVU290 + 1065 0014 08BD pop {r3, pc} + 1066 .L92: + 1067 0016 00BF .align 2 + 1068 .L91: + 1069 0018 00200240 .word 1073881088 + 1070 .cfi_endproc + 1071 .LFE139: + 1073 .global pFlash + 1074 .section .bss.pFlash,"aw",%nobits + 1075 .align 3 + 1078 pFlash: + 1079 0000 00000000 .space 32 + 1079 00000000 + 1079 00000000 + ARM GAS /tmp/ccX3tCBb.s page 36 + + + 1079 00000000 + 1079 00000000 + 1080 .text + 1081 .Letext0: + 1082 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1083 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1084 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1085 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1086 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1087 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h" + 1088 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccX3tCBb.s page 37 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_flash.c + /tmp/ccX3tCBb.s:21 .text.FLASH_Program_HalfWord:0000000000000000 $t + /tmp/ccX3tCBb.s:26 .text.FLASH_Program_HalfWord:0000000000000000 FLASH_Program_HalfWord + /tmp/ccX3tCBb.s:52 .text.FLASH_Program_HalfWord:0000000000000014 $d + /tmp/ccX3tCBb.s:1078 .bss.pFlash:0000000000000000 pFlash + /tmp/ccX3tCBb.s:58 .text.FLASH_SetErrorCode:0000000000000000 $t + /tmp/ccX3tCBb.s:63 .text.FLASH_SetErrorCode:0000000000000000 FLASH_SetErrorCode + /tmp/ccX3tCBb.s:119 .text.FLASH_SetErrorCode:0000000000000034 $d + /tmp/ccX3tCBb.s:125 .text.HAL_FLASH_Program_IT:0000000000000000 $t + /tmp/ccX3tCBb.s:131 .text.HAL_FLASH_Program_IT:0000000000000000 HAL_FLASH_Program_IT + /tmp/ccX3tCBb.s:241 .text.HAL_FLASH_Program_IT:0000000000000064 $d + /tmp/ccX3tCBb.s:247 .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 $t + /tmp/ccX3tCBb.s:253 .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 HAL_FLASH_EndOfOperationCallback + /tmp/ccX3tCBb.s:268 .text.HAL_FLASH_OperationErrorCallback:0000000000000000 $t + /tmp/ccX3tCBb.s:274 .text.HAL_FLASH_OperationErrorCallback:0000000000000000 HAL_FLASH_OperationErrorCallback + /tmp/ccX3tCBb.s:289 .text.HAL_FLASH_IRQHandler:0000000000000000 $t + /tmp/ccX3tCBb.s:295 .text.HAL_FLASH_IRQHandler:0000000000000000 HAL_FLASH_IRQHandler + /tmp/ccX3tCBb.s:582 .text.HAL_FLASH_IRQHandler:000000000000014c $d + /tmp/ccX3tCBb.s:588 .text.HAL_FLASH_Unlock:0000000000000000 $t + /tmp/ccX3tCBb.s:594 .text.HAL_FLASH_Unlock:0000000000000000 HAL_FLASH_Unlock + /tmp/ccX3tCBb.s:639 .text.HAL_FLASH_Unlock:000000000000002c $d + /tmp/ccX3tCBb.s:645 .text.HAL_FLASH_Lock:0000000000000000 $t + /tmp/ccX3tCBb.s:651 .text.HAL_FLASH_Lock:0000000000000000 HAL_FLASH_Lock + /tmp/ccX3tCBb.s:670 .text.HAL_FLASH_Lock:0000000000000010 $d + /tmp/ccX3tCBb.s:675 .text.HAL_FLASH_OB_Unlock:0000000000000000 $t + /tmp/ccX3tCBb.s:681 .text.HAL_FLASH_OB_Unlock:0000000000000000 HAL_FLASH_OB_Unlock + /tmp/ccX3tCBb.s:714 .text.HAL_FLASH_OB_Unlock:0000000000000020 $d + /tmp/ccX3tCBb.s:720 .text.HAL_FLASH_OB_Lock:0000000000000000 $t + /tmp/ccX3tCBb.s:726 .text.HAL_FLASH_OB_Lock:0000000000000000 HAL_FLASH_OB_Lock + /tmp/ccX3tCBb.s:745 .text.HAL_FLASH_OB_Lock:0000000000000010 $d + /tmp/ccX3tCBb.s:750 .text.HAL_FLASH_GetError:0000000000000000 $t + /tmp/ccX3tCBb.s:756 .text.HAL_FLASH_GetError:0000000000000000 HAL_FLASH_GetError + /tmp/ccX3tCBb.s:772 .text.HAL_FLASH_GetError:0000000000000008 $d + /tmp/ccX3tCBb.s:777 .text.FLASH_WaitForLastOperation:0000000000000000 $t + /tmp/ccX3tCBb.s:783 .text.FLASH_WaitForLastOperation:0000000000000000 FLASH_WaitForLastOperation + /tmp/ccX3tCBb.s:875 .text.FLASH_WaitForLastOperation:000000000000005c $d + /tmp/ccX3tCBb.s:880 .text.HAL_FLASH_Program:0000000000000000 $t + /tmp/ccX3tCBb.s:886 .text.HAL_FLASH_Program:0000000000000000 HAL_FLASH_Program + /tmp/ccX3tCBb.s:1032 .text.HAL_FLASH_Program:0000000000000098 $d + /tmp/ccX3tCBb.s:1038 .text.HAL_FLASH_OB_Launch:0000000000000000 $t + /tmp/ccX3tCBb.s:1044 .text.HAL_FLASH_OB_Launch:0000000000000000 HAL_FLASH_OB_Launch + /tmp/ccX3tCBb.s:1069 .text.HAL_FLASH_OB_Launch:0000000000000018 $d + /tmp/ccX3tCBb.s:1075 .bss.pFlash:0000000000000000 $d + +UNDEFINED SYMBOLS +FLASH_PageErase +HAL_GetTick diff --git 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a/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/stm32f3xx_hal_msp.d b/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/stm32f3xx_hal_msp.d new file mode 100644 index 0000000..0e6f5d4 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/stm32f3xx_hal_msp.d @@ -0,0 +1,60 @@ +Core/Src/stm32f3xx_hal_msp.o: ../Core/Src/stm32f3xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + ../Core/Inc/stm32f3xx_hal_conf.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +../Core/Inc/main.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +../Core/Inc/stm32f3xx_hal_conf.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: 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    • + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * the "License"; You may not use this file except in compliance with the + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * License. You may obtain a copy of the License at: + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * opensource.org/licenses/BSD-3-Clause + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ****************************************************************************** + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Includes ------------------------------------------------------------------*/ + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #include "stm32f3xx_hal.h" + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASH + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASH_Private_Variables + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Variables used for Erase pages under interruption*/ + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** extern FLASH_ProcessTypeDef pFlash; + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx FLASHEx + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief FLASH HAL Extension module driver + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private define ------------------------------------------------------------*/ + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW) + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0) + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1) + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private macro -------------------------------------------------------------*/ + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + ARM GAS /tmp/ccLRLOP3.s page 3 + + + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/ + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Erase operations */ + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static void FLASH_MassErase(void); + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** void FLASH_PageErase(uint32_t PageAddress); + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Option bytes control */ + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void); + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void); + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetUser(void); + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Exported functions ---------------------------------------------------------*/ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief FLASH Memory Erasing functions + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @verbatim + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ##### FLASH Erasing Programming functions ##### + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** [..] The FLASH Memory Erasing functions, includes the following functions: + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (+) HAL_FLASHEx_Erase: return only when erase has been done + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** is called with parameter 0xFFFFFFFF + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** [..] Any operation of erase should follow these steps: + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** program memory access. + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (#) Call the desired function to erase page. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (recommended to protect the FLASH memory against possible unwanted operation). + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @endverbatim + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory pages + ARM GAS /tmp/ccLRLOP3.s page 4 + + + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * must be called before. + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (recommended to protect the FLASH memory against possible unwanted operation) + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param[out] PageError pointer to variable that + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information on faulty page in case of error + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (0xFFFFFFFF means that all the pages have been correctly erased) + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t address = 0U; + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Locked */ + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Mass Erase requested for Bank1 */ + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Mass erase to be done*/ + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_MassErase(); + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the MER Bit */ + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Page Erase is requested */ + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Page Erase requested on address located on bank1 */ + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Initialization of PageError variable*/ + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *PageError = 0xFFFFFFFFU; + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Erase page by page to be done*/ + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** for(address = pEraseInit->PageAddress; + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + ARM GAS /tmp/ccLRLOP3.s page 5 + + + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_PageErase(address); + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the PER Bit */ + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* In case of error, stop erase procedure and return the faulty address */ + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *PageError = address; + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** break; + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * must be called before. + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (recommended to protect the FLASH memory against possible unwanted operation) + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Locked */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If procedure already ongoing, reject the next one */ + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return HAL_ERROR; + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable End of FLASH Operation and Error source interrupts */ + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + ARM GAS /tmp/ccLRLOP3.s page 6 + + + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Mass erase to be done*/ + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_MassErase(); + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Erase by page to be done*/ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.DataRemaining = pEraseInit->NbPages; + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.Address = pEraseInit->PageAddress; + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Erase 1st page and wait for IT*/ + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_PageErase(pEraseInit->PageAddress); + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Option Bytes Programming functions + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @verbatim + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ##### Option Bytes Programming functions ##### + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** [..] + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** This subsection provides a set of functions allowing to control the FLASH + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** option bytes operations. + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @endverbatim + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Erases the FLASH option bytes. + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note This functions erases all option bytes except the Read protection (RDP). + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interf + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options b + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of t + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (system reset will occur) + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint8_t rdptmp = OB_RDP_LEVEL_0; + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + ARM GAS /tmp/ccLRLOP3.s page 7 + + + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get the actual read protection Option Byte value */ + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** rdptmp = FLASH_OB_GetRDP(); + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the previous operation is completed, proceed to erase the option bytes */ + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTER); + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the OPTER Bit */ + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Restore the last read protection Option Byte value */ + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_RDP_LevelConfig(rdptmp); + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Return the erase status */ + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Program option bytes + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interf + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options b + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of t + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (system reset will occur) + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Locked */ + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Write protection configuration */ + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + ARM GAS /tmp/ccLRLOP3.s page 8 + + + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_WRPSTATE(pOBInit->WRPState)); + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable of Write protection on the selected page */ + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Disable of Write protection on the selected page */ + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Read protection configuration */ + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* USER configuration */ + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_UserConfig(pOBInit->USERConfig); + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* DATA configuration*/ + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + ARM GAS /tmp/ccLRLOP3.s page 9 + + + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Get the Option byte configuration + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval None + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Get WRP*/ + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->WRPPage = FLASH_OB_GetWRP(); + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Get RDP Level*/ + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->RDPLevel = FLASH_OB_GetRDP(); + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Get USER*/ + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->USERConfig = FLASH_OB_GetUser(); + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Get the Option byte user data + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param DATAAdress Address of the option byte DATA + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_DATA_ADDRESS_DATA0 + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_DATA_ADDRESS_DATA1 + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval Value programmed in USER data + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t value = 0U; + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (DATAAdress == OB_DATA_ADDRESS_DATA0) + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get value programmed in OB USER Data0 */ + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get value programmed in OB USER Data1 */ + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return value; + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + ARM GAS /tmp/ccLRLOP3.s page 10 + + + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Functions + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Full erase of FLASH memory Bank + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval None + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static void FLASH_MassErase(void) + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 28 .loc 1 501 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 33 .loc 1 503 3 view .LVU1 + 34 .loc 1 503 20 is_stmt 0 view .LVU2 + 35 0000 064B ldr r3, .L2 + 36 0002 0022 movs r2, #0 + 37 0004 DA61 str r2, [r3, #28] + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Only bank1 will be erased*/ + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_MER); + 38 .loc 1 506 5 is_stmt 1 view .LVU3 + 39 0006 064B ldr r3, .L2+4 + 40 0008 1A69 ldr r2, [r3, #16] + 41 000a 42F00402 orr r2, r2, #4 + 42 000e 1A61 str r2, [r3, #16] + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 43 .loc 1 507 5 view .LVU4 + 44 0010 1A69 ldr r2, [r3, #16] + 45 0012 42F04002 orr r2, r2, #64 + 46 0016 1A61 str r2, [r3, #16] + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 47 .loc 1 508 1 is_stmt 0 view .LVU5 + 48 0018 7047 bx lr + 49 .L3: + 50 001a 00BF .align 2 + 51 .L2: + 52 001c 00000000 .word pFlash + 53 0020 00200240 .word 1073881088 + 54 .cfi_endproc + 55 .LFE136: + 57 .section .text.FLASH_OB_GetWRP,"ax",%progbits + 58 .align 1 + 59 .syntax unified + 60 .thumb + 61 .thumb_func + 63 FLASH_OB_GetWRP: + 64 .LFB142: + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccLRLOP3.s page 11 + + + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Enable the write protection of the desired pages + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note An option byte erase is done automatically in this function. + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note When the memory read protection level is selected (RDP level = 1), + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * it is not possible to program or erase the flash page i if + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param WriteProtectPage specifies the page(s) to be write protected. + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP0_Data = 0xFFFFU; + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP1_Data = 0xFFFFU; + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP2_WRP2) + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP2_Data = 0xFFFFU; + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP3_WRP3) + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP3_Data = 0xFFFFU; + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_WRP(WriteProtectPage)); + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get current write protected pages and the new pages to be protected ******/ + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES0TO15MASK) + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES0TO31MASK */ + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES16TO31MASK) + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO63MASK */ + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES32TO47MASK) + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO47MASK */ + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES48TO127MASK) + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(OB_WRP_PAGES48TO255MASK) + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES48TO63MASK */ + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccLRLOP3.s page 12 + + + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* To be able to write again option byte, need to perform a option byte erase */ + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = HAL_FLASHEx_OBErase(); + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK) + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable write protection */ + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP0_WRP0) + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(WRP0_Data != 0xFFU) + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP0 &= WRP0_Data; + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP0_WRP0 */ + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP1 &= WRP1_Data; + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP2_WRP2) + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP2 &= WRP2_Data; + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP3_WRP3) + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP3 &= WRP3_Data; + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* if the program operation is completed, disable the OPTPG Bit */ + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Disable the write protection of the desired pages + ARM GAS /tmp/ccLRLOP3.s page 13 + + + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note An option byte erase is done automatically in this function. + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note When the memory read protection level is selected (RDP level = 1), + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * it is not possible to program or erase the flash page i if + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param WriteProtectPage specifies the page(s) to be write unprotected. + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP0_Data = 0xFFFFU; + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP1_Data = 0xFFFFU; + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP2_WRP2) + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP2_Data = 0xFFFFU; + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP3_WRP3) + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP3_Data = 0xFFFFU; + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_WRP(WriteProtectPage)); + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get current write protected pages and the new pages to be unprotected ******/ + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES0TO15MASK) + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES0TO31MASK */ + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES16TO31MASK) + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO63MASK */ + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES32TO47MASK) + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO47MASK */ + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES48TO127MASK) + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(OB_WRP_PAGES48TO255MASK) + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES48TO63MASK */ + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* To be able to write again option byte, need to perform a option byte erase */ + ARM GAS /tmp/ccLRLOP3.s page 14 + + + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = HAL_FLASHEx_OBErase(); + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK) + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP0_WRP0) + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(WRP0_Data != 0xFFU) + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP0 |= WRP0_Data; + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP0_WRP0 */ + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP1 |= WRP1_Data; + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP2_WRP2) + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP2 |= WRP2_Data; + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP3_WRP3) + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP3 |= WRP3_Data; + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* if the program operation is completed, disable the OPTPG Bit */ + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Set the read protection level. + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param ReadProtectLevel specifies the read protection level. + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection + ARM GAS /tmp/ccLRLOP3.s page 15 + + + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Full chip protection + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the previous operation is completed, proceed to erase the option bytes */ + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTER); + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the OPTER Bit */ + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable the Option Bytes Programming operation */ + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRITE_REG(OB->RDP, ReadProtectLevel); + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* if the program operation is completed, disable the OPTPG Bit */ + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Program the FLASH User Option Byte. + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) + ARM GAS /tmp/ccLRLOP3.s page 16 + + + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET))); + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */ + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable the Option Bytes Programming operation */ + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->USER = (UserConfig | 0x08U); + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #else + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->USER = (UserConfig | 0x88U); + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* if the program operation is completed, disable the OPTPG Bit */ + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Programs a half word at a specified Option Byte Data address. + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interf + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options b + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of t + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (system reset will occur) + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param Address specifies the address to be programmed. + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This parameter can be 0x1FFFF804 or 0x1FFFF806. + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param Data specifies the data to be programmed. + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccLRLOP3.s page 17 + + + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_DATA_ADDRESS(Address)); + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enables the Option Bytes Programming operation */ + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *(__IO uint16_t*)Address = Data; + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the program operation is completed, disable the OPTPG Bit */ + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Return the Option Byte Data Program Status */ + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Return the FLASH Write Protection Option Bytes value. + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval The FLASH Write Protection Option Bytes value + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void) + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 65 .loc 1 882 1 is_stmt 1 view -0 + 66 .cfi_startproc + 67 @ args = 0, pretend = 0, frame = 0 + 68 @ frame_needed = 0, uses_anonymous_args = 0 + 69 @ link register save eliminated. + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Return the FLASH write protection Register value */ + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return (uint32_t)(READ_REG(FLASH->WRPR)); + 70 .loc 1 884 3 view .LVU7 + 71 .loc 1 884 10 is_stmt 0 view .LVU8 + 72 0000 014B ldr r3, .L5 + 73 0002 186A ldr r0, [r3, #32] + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 74 .loc 1 885 1 view .LVU9 + 75 0004 7047 bx lr + 76 .L6: + 77 0006 00BF .align 2 + 78 .L5: + 79 0008 00200240 .word 1073881088 + 80 .cfi_endproc + 81 .LFE142: + 83 .section .text.FLASH_OB_GetRDP,"ax",%progbits + 84 .align 1 + 85 .syntax unified + 86 .thumb + 87 .thumb_func + 89 FLASH_OB_GetRDP: + ARM GAS /tmp/ccLRLOP3.s page 18 + + + 90 .LFB143: + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Returns the FLASH Read Protection level. + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval FLASH RDP level + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Full chip protection + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void) + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 91 .loc 1 896 1 is_stmt 1 view -0 + 92 .cfi_startproc + 93 @ args = 0, pretend = 0, frame = 0 + 94 @ frame_needed = 0, uses_anonymous_args = 0 + 95 @ link register save eliminated. + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t tmp_reg = 0U; + 96 .loc 1 897 3 view .LVU11 + 97 .LVL0: + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Read RDP level bits */ + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_RDPRT) + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); + 98 .loc 1 901 3 view .LVU12 + 99 .loc 1 901 13 is_stmt 0 view .LVU13 + 100 0000 064B ldr r3, .L11 + 101 0002 DB69 ldr r3, [r3, #28] + 102 .loc 1 901 11 view .LVU14 + 103 0004 03F00603 and r3, r3, #6 + 104 .LVL1: + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(FLASH_OBR_LEVEL1_PROT) + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT)); + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* FLASH_OBR_RDPRT */ + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_RDPRT) + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (tmp_reg == FLASH_OBR_RDPRT_2) + 105 .loc 1 907 3 is_stmt 1 view .LVU15 + 106 .loc 1 907 6 is_stmt 0 view .LVU16 + 107 0008 062B cmp r3, #6 + 108 000a 02D0 beq .L9 + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(FLASH_OBR_LEVEL1_PROT) + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (tmp_reg == FLASH_OBR_LEVEL2_PROT) + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* FLASH_OBR_RDPRT */ + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return OB_RDP_LEVEL_2; + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else if (tmp_reg == 0U) + 109 .loc 1 914 8 is_stmt 1 view .LVU17 + 110 .loc 1 914 11 is_stmt 0 view .LVU18 + 111 000c 1BB9 cbnz r3, .L10 + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return OB_RDP_LEVEL_0; + 112 .loc 1 916 12 view .LVU19 + 113 000e AA20 movs r0, #170 + 114 0010 7047 bx lr + 115 .L9: + ARM GAS /tmp/ccLRLOP3.s page 19 + + + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 116 .loc 1 912 12 view .LVU20 + 117 0012 CC20 movs r0, #204 + 118 0014 7047 bx lr + 119 .L10: + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return OB_RDP_LEVEL_1; + 120 .loc 1 920 12 view .LVU21 + 121 0016 BB20 movs r0, #187 + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 122 .loc 1 922 1 view .LVU22 + 123 0018 7047 bx lr + 124 .L12: + 125 001a 00BF .align 2 + 126 .L11: + 127 001c 00200240 .word 1073881088 + 128 .cfi_endproc + 129 .LFE143: + 131 .section .text.FLASH_OB_RDP_LevelConfig,"ax",%progbits + 132 .align 1 + 133 .syntax unified + 134 .thumb + 135 .thumb_func + 137 FLASH_OB_RDP_LevelConfig: + 138 .LVL2: + 139 .LFB139: + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 140 .loc 1 744 1 is_stmt 1 view -0 + 141 .cfi_startproc + 142 @ args = 0, pretend = 0, frame = 0 + 143 @ frame_needed = 0, uses_anonymous_args = 0 + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 144 .loc 1 744 1 is_stmt 0 view .LVU24 + 145 0000 38B5 push {r3, r4, r5, lr} + 146 .cfi_def_cfa_offset 16 + 147 .cfi_offset 3, -16 + 148 .cfi_offset 4, -12 + 149 .cfi_offset 5, -8 + 150 .cfi_offset 14, -4 + 151 0002 0546 mov r5, r0 + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 152 .loc 1 745 3 is_stmt 1 view .LVU25 + 153 .LVL3: + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 154 .loc 1 748 3 view .LVU26 + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 155 .loc 1 751 3 view .LVU27 + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 156 .loc 1 751 12 is_stmt 0 view .LVU28 + 157 0004 4CF25030 movw r0, #50000 + 158 .LVL4: + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 159 .loc 1 751 12 view .LVU29 + 160 0008 FFF7FEFF bl FLASH_WaitForLastOperation + ARM GAS /tmp/ccLRLOP3.s page 20 + + + 161 .LVL5: + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 162 .loc 1 753 3 is_stmt 1 view .LVU30 + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 163 .loc 1 753 5 is_stmt 0 view .LVU31 + 164 000c 00B1 cbz r0, .L16 + 165 .LVL6: + 166 .L14: + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 167 .loc 1 783 3 is_stmt 1 view .LVU32 + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 168 .loc 1 784 1 is_stmt 0 view .LVU33 + 169 000e 38BD pop {r3, r4, r5, pc} + 170 .LVL7: + 171 .L16: + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 172 .loc 1 756 5 is_stmt 1 view .LVU34 + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 173 .loc 1 756 22 is_stmt 0 view .LVU35 + 174 0010 124B ldr r3, .L17 + 175 0012 0022 movs r2, #0 + 176 0014 DA61 str r2, [r3, #28] + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 177 .loc 1 759 5 is_stmt 1 view .LVU36 + 178 0016 124C ldr r4, .L17+4 + 179 0018 2369 ldr r3, [r4, #16] + 180 001a 43F02003 orr r3, r3, #32 + 181 001e 2361 str r3, [r4, #16] + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 182 .loc 1 760 5 view .LVU37 + 183 0020 2369 ldr r3, [r4, #16] + 184 0022 43F04003 orr r3, r3, #64 + 185 0026 2361 str r3, [r4, #16] + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 186 .loc 1 763 5 view .LVU38 + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 187 .loc 1 763 14 is_stmt 0 view .LVU39 + 188 0028 4CF25030 movw r0, #50000 + 189 002c FFF7FEFF bl FLASH_WaitForLastOperation + 190 .LVL8: + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 191 .loc 1 766 5 is_stmt 1 view .LVU40 + 192 0030 2369 ldr r3, [r4, #16] + 193 0032 23F02003 bic r3, r3, #32 + 194 0036 2361 str r3, [r4, #16] + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 195 .loc 1 768 5 view .LVU41 + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 196 .loc 1 768 7 is_stmt 0 view .LVU42 + 197 0038 0028 cmp r0, #0 + 198 003a E8D1 bne .L14 + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 199 .loc 1 771 7 is_stmt 1 view .LVU43 + 200 003c 2369 ldr r3, [r4, #16] + 201 003e 43F01003 orr r3, r3, #16 + 202 0042 2361 str r3, [r4, #16] + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccLRLOP3.s page 21 + + + 203 .loc 1 773 7 view .LVU44 + 204 0044 074B ldr r3, .L17+8 + 205 0046 1D80 strh r5, [r3] @ movhi + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 206 .loc 1 776 7 view .LVU45 + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 207 .loc 1 776 16 is_stmt 0 view .LVU46 + 208 0048 4CF25030 movw r0, #50000 + 209 .LVL9: + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 210 .loc 1 776 16 view .LVU47 + 211 004c FFF7FEFF bl FLASH_WaitForLastOperation + 212 .LVL10: + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 213 .loc 1 779 7 is_stmt 1 view .LVU48 + 214 0050 2369 ldr r3, [r4, #16] + 215 0052 23F01003 bic r3, r3, #16 + 216 0056 2361 str r3, [r4, #16] + 217 0058 D9E7 b .L14 + 218 .L18: + 219 005a 00BF .align 2 + 220 .L17: + 221 005c 00000000 .word pFlash + 222 0060 00200240 .word 1073881088 + 223 0064 00F8FF1F .word 536868864 + 224 .cfi_endproc + 225 .LFE139: + 227 .section .text.FLASH_OB_UserConfig,"ax",%progbits + 228 .align 1 + 229 .syntax unified + 230 .thumb + 231 .thumb_func + 233 FLASH_OB_UserConfig: + 234 .LVL11: + 235 .LFB140: + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 236 .loc 1 795 1 view -0 + 237 .cfi_startproc + 238 @ args = 0, pretend = 0, frame = 0 + 239 @ frame_needed = 0, uses_anonymous_args = 0 + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 240 .loc 1 795 1 is_stmt 0 view .LVU50 + 241 0000 38B5 push {r3, r4, r5, lr} + 242 .cfi_def_cfa_offset 16 + 243 .cfi_offset 3, -16 + 244 .cfi_offset 4, -12 + 245 .cfi_offset 5, -8 + 246 .cfi_offset 14, -4 + 247 0002 0446 mov r4, r0 + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 248 .loc 1 796 3 is_stmt 1 view .LVU51 + 249 .LVL12: + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + 250 .loc 1 799 3 view .LVU52 + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); + 251 .loc 1 800 3 view .LVU53 + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); + ARM GAS /tmp/ccLRLOP3.s page 22 + + + 252 .loc 1 801 3 view .LVU54 + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); + 253 .loc 1 802 3 view .LVU55 + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); + 254 .loc 1 803 3 view .LVU56 + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) + 255 .loc 1 804 3 view .LVU57 + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 256 .loc 1 810 3 view .LVU58 + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 257 .loc 1 810 12 is_stmt 0 view .LVU59 + 258 0004 4CF25030 movw r0, #50000 + 259 .LVL13: + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 260 .loc 1 810 12 view .LVU60 + 261 0008 FFF7FEFF bl FLASH_WaitForLastOperation + 262 .LVL14: + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 263 .loc 1 812 3 is_stmt 1 view .LVU61 + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 264 .loc 1 812 5 is_stmt 0 view .LVU62 + 265 000c 00B1 cbz r0, .L22 + 266 .LVL15: + 267 .L20: + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 268 .loc 1 833 3 is_stmt 1 view .LVU63 + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 269 .loc 1 834 1 is_stmt 0 view .LVU64 + 270 000e 38BD pop {r3, r4, r5, pc} + 271 .LVL16: + 272 .L22: + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 273 .loc 1 815 5 is_stmt 1 view .LVU65 + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 274 .loc 1 815 22 is_stmt 0 view .LVU66 + 275 0010 0A4B ldr r3, .L23 + 276 0012 0022 movs r2, #0 + 277 0014 DA61 str r2, [r3, #28] + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 278 .loc 1 818 5 is_stmt 1 view .LVU67 + 279 0016 0A4D ldr r5, .L23+4 + 280 0018 2B69 ldr r3, [r5, #16] + 281 001a 43F01003 orr r3, r3, #16 + 282 001e 2B61 str r3, [r5, #16] + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif + 283 .loc 1 823 5 view .LVU68 + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif + 284 .loc 1 823 14 is_stmt 0 view .LVU69 + 285 0020 44F08800 orr r0, r4, #136 + 286 0024 074B ldr r3, .L23+8 + 287 0026 5880 strh r0, [r3, #2] @ movhi + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 288 .loc 1 827 5 is_stmt 1 view .LVU70 + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 289 .loc 1 827 14 is_stmt 0 view .LVU71 + 290 0028 4CF25030 movw r0, #50000 + 291 002c FFF7FEFF bl FLASH_WaitForLastOperation + ARM GAS /tmp/ccLRLOP3.s page 23 + + + 292 .LVL17: + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 293 .loc 1 830 5 is_stmt 1 view .LVU72 + 294 0030 2B69 ldr r3, [r5, #16] + 295 0032 23F01003 bic r3, r3, #16 + 296 0036 2B61 str r3, [r5, #16] + 297 0038 E9E7 b .L20 + 298 .L24: + 299 003a 00BF .align 2 + 300 .L23: + 301 003c 00000000 .word pFlash + 302 0040 00200240 .word 1073881088 + 303 0044 00F8FF1F .word 536868864 + 304 .cfi_endproc + 305 .LFE140: + 307 .section .text.FLASH_OB_ProgramData,"ax",%progbits + 308 .align 1 + 309 .syntax unified + 310 .thumb + 311 .thumb_func + 313 FLASH_OB_ProgramData: + 314 .LVL18: + 315 .LFB141: + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 316 .loc 1 849 1 view -0 + 317 .cfi_startproc + 318 @ args = 0, pretend = 0, frame = 0 + 319 @ frame_needed = 0, uses_anonymous_args = 0 + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 320 .loc 1 849 1 is_stmt 0 view .LVU74 + 321 0000 70B5 push {r4, r5, r6, lr} + 322 .cfi_def_cfa_offset 16 + 323 .cfi_offset 4, -16 + 324 .cfi_offset 5, -12 + 325 .cfi_offset 6, -8 + 326 .cfi_offset 14, -4 + 327 0002 0546 mov r5, r0 + 328 0004 0C46 mov r4, r1 + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 329 .loc 1 850 3 is_stmt 1 view .LVU75 + 330 .LVL19: + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 331 .loc 1 853 3 view .LVU76 + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 332 .loc 1 856 3 view .LVU77 + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 333 .loc 1 856 12 is_stmt 0 view .LVU78 + 334 0006 4CF25030 movw r0, #50000 + 335 .LVL20: + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 336 .loc 1 856 12 view .LVU79 + 337 000a FFF7FEFF bl FLASH_WaitForLastOperation + 338 .LVL21: + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 339 .loc 1 858 3 is_stmt 1 view .LVU80 + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 340 .loc 1 858 5 is_stmt 0 view .LVU81 + ARM GAS /tmp/ccLRLOP3.s page 24 + + + 341 000e 00B1 cbz r0, .L28 + 342 .L26: + 343 .LVL22: + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 344 .loc 1 874 3 is_stmt 1 view .LVU82 + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 345 .loc 1 875 1 is_stmt 0 view .LVU83 + 346 0010 70BD pop {r4, r5, r6, pc} + 347 .LVL23: + 348 .L28: + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 349 .loc 1 861 5 is_stmt 1 view .LVU84 + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 350 .loc 1 861 22 is_stmt 0 view .LVU85 + 351 0012 094B ldr r3, .L29 + 352 0014 0022 movs r2, #0 + 353 0016 DA61 str r2, [r3, #28] + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *(__IO uint16_t*)Address = Data; + 354 .loc 1 864 5 is_stmt 1 view .LVU86 + 355 0018 084E ldr r6, .L29+4 + 356 001a 3369 ldr r3, [r6, #16] + 357 001c 43F01003 orr r3, r3, #16 + 358 0020 3361 str r3, [r6, #16] + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 359 .loc 1 865 5 view .LVU87 + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 360 .loc 1 865 30 is_stmt 0 view .LVU88 + 361 0022 2C80 strh r4, [r5] @ movhi + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 362 .loc 1 868 5 is_stmt 1 view .LVU89 + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 363 .loc 1 868 14 is_stmt 0 view .LVU90 + 364 0024 4CF25030 movw r0, #50000 + 365 0028 FFF7FEFF bl FLASH_WaitForLastOperation + 366 .LVL24: + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 367 .loc 1 871 5 is_stmt 1 view .LVU91 + 368 002c 3369 ldr r3, [r6, #16] + 369 002e 23F01003 bic r3, r3, #16 + 370 0032 3361 str r3, [r6, #16] + 371 0034 ECE7 b .L26 + 372 .L30: + 373 0036 00BF .align 2 + 374 .L29: + 375 0038 00000000 .word pFlash + 376 003c 00200240 .word 1073881088 + 377 .cfi_endproc + 378 .LFE141: + 380 .section .text.FLASH_OB_GetUser,"ax",%progbits + 381 .align 1 + 382 .syntax unified + 383 .thumb + 384 .thumb_func + 386 FLASH_OB_GetUser: + 387 .LFB144: + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + ARM GAS /tmp/ccLRLOP3.s page 25 + + + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Return the FLASH User Option Byte value. + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nB + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetUser(void) + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 388 .loc 1 931 1 view -0 + 389 .cfi_startproc + 390 @ args = 0, pretend = 0, frame = 0 + 391 @ frame_needed = 0, uses_anonymous_args = 0 + 392 @ link register save eliminated. + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Return the User Option Byte */ + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); + 393 .loc 1 933 3 view .LVU93 + 394 .loc 1 933 21 is_stmt 0 view .LVU94 + 395 0000 064B ldr r3, .L32 + 396 0002 D869 ldr r0, [r3, #28] + 397 .loc 1 933 42 view .LVU95 + 398 0004 00F4EE40 and r0, r0, #30464 + 399 .LVL25: + 400 .LBB8: + 401 .LBI8: + 402 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccLRLOP3.s page 26 + + + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + ARM GAS /tmp/ccLRLOP3.s page 27 + + + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + ARM GAS /tmp/ccLRLOP3.s page 28 + + + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccLRLOP3.s page 29 + + + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccLRLOP3.s page 30 + + + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccLRLOP3.s page 31 + + + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccLRLOP3.s page 32 + + + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + ARM GAS /tmp/ccLRLOP3.s page 33 + + + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + ARM GAS /tmp/ccLRLOP3.s page 34 + + + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + ARM GAS /tmp/ccLRLOP3.s page 35 + + + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccLRLOP3.s page 36 + + + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + ARM GAS /tmp/ccLRLOP3.s page 37 + + + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + ARM GAS /tmp/ccLRLOP3.s page 38 + + + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + ARM GAS /tmp/ccLRLOP3.s page 39 + + + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccLRLOP3.s page 40 + + + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + ARM GAS /tmp/ccLRLOP3.s page 41 + + + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccLRLOP3.s page 42 + + + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 403 .loc 2 981 31 is_stmt 1 view .LVU96 + 404 .LBB9: + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 405 .loc 2 983 3 view .LVU97 + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 406 .loc 2 988 4 view .LVU98 + 407 0008 4FF48073 mov r3, #256 + 408 .syntax unified + 409 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 410 000c 93FAA3F3 rbit r3, r3 + 411 @ 0 "" 2 + 412 .LVL26: + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + ARM GAS /tmp/ccLRLOP3.s page 43 + + + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 413 .loc 2 1001 3 view .LVU99 + 414 .loc 2 1001 3 is_stmt 0 view .LVU100 + 415 .thumb + 416 .syntax unified + 417 .LBE9: + 418 .LBE8: + 419 .loc 1 933 63 view .LVU101 + 420 0010 B3FA83F3 clz r3, r3 + 421 .loc 1 933 60 view .LVU102 + 422 0014 D840 lsrs r0, r0, r3 + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 423 .loc 1 934 1 view .LVU103 + 424 0016 C0B2 uxtb r0, r0 + 425 0018 7047 bx lr + 426 .L33: + 427 001a 00BF .align 2 + 428 .L32: + 429 001c 00200240 .word 1073881088 + 430 .cfi_endproc + 431 .LFE144: + 433 .section .text.HAL_FLASHEx_OBErase,"ax",%progbits + 434 .align 1 + 435 .global HAL_FLASHEx_OBErase + 436 .syntax unified + 437 .thumb + 438 .thumb_func + 440 HAL_FLASHEx_OBErase: + 441 .LFB132: + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint8_t rdptmp = OB_RDP_LEVEL_0; + 442 .loc 1 314 1 is_stmt 1 view -0 + 443 .cfi_startproc + 444 @ args = 0, pretend = 0, frame = 0 + 445 @ frame_needed = 0, uses_anonymous_args = 0 + 446 0000 38B5 push {r3, r4, r5, lr} + 447 .cfi_def_cfa_offset 16 + 448 .cfi_offset 3, -16 + 449 .cfi_offset 4, -12 + 450 .cfi_offset 5, -8 + 451 .cfi_offset 14, -4 + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 452 .loc 1 315 3 view .LVU105 + 453 .LVL27: + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 454 .loc 1 316 3 view .LVU106 + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 455 .loc 1 319 3 view .LVU107 + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 456 .loc 1 319 12 is_stmt 0 view .LVU108 + ARM GAS /tmp/ccLRLOP3.s page 44 + + + 457 0002 FFF7FEFF bl FLASH_OB_GetRDP + 458 .LVL28: + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 459 .loc 1 319 10 view .LVU109 + 460 0006 C5B2 uxtb r5, r0 + 461 .LVL29: + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 462 .loc 1 322 3 is_stmt 1 view .LVU110 + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 463 .loc 1 322 12 is_stmt 0 view .LVU111 + 464 0008 4CF25030 movw r0, #50000 + 465 000c FFF7FEFF bl FLASH_WaitForLastOperation + 466 .LVL30: + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 467 .loc 1 324 3 is_stmt 1 view .LVU112 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 468 .loc 1 324 5 is_stmt 0 view .LVU113 + 469 0010 00B1 cbz r0, .L37 + 470 .LVL31: + 471 .L35: + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 472 .loc 1 347 3 is_stmt 1 view .LVU114 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 473 .loc 1 348 1 is_stmt 0 view .LVU115 + 474 0012 38BD pop {r3, r4, r5, pc} + 475 .LVL32: + 476 .L37: + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 477 .loc 1 327 5 is_stmt 1 view .LVU116 + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 478 .loc 1 327 22 is_stmt 0 view .LVU117 + 479 0014 0C4B ldr r3, .L38 + 480 0016 0022 movs r2, #0 + 481 0018 DA61 str r2, [r3, #28] + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 482 .loc 1 330 5 is_stmt 1 view .LVU118 + 483 001a 0C4C ldr r4, .L38+4 + 484 001c 2369 ldr r3, [r4, #16] + 485 001e 43F02003 orr r3, r3, #32 + 486 0022 2361 str r3, [r4, #16] + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 487 .loc 1 331 5 view .LVU119 + 488 0024 2369 ldr r3, [r4, #16] + 489 0026 43F04003 orr r3, r3, #64 + 490 002a 2361 str r3, [r4, #16] + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 491 .loc 1 334 5 view .LVU120 + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 492 .loc 1 334 14 is_stmt 0 view .LVU121 + 493 002c 4CF25030 movw r0, #50000 + 494 0030 FFF7FEFF bl FLASH_WaitForLastOperation + 495 .LVL33: + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 496 .loc 1 337 5 is_stmt 1 view .LVU122 + 497 0034 2369 ldr r3, [r4, #16] + 498 0036 23F02003 bic r3, r3, #32 + 499 003a 2361 str r3, [r4, #16] + ARM GAS /tmp/ccLRLOP3.s page 45 + + + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 500 .loc 1 339 5 view .LVU123 + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 501 .loc 1 339 7 is_stmt 0 view .LVU124 + 502 003c 0028 cmp r0, #0 + 503 003e E8D1 bne .L35 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 504 .loc 1 342 7 is_stmt 1 view .LVU125 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 505 .loc 1 342 16 is_stmt 0 view .LVU126 + 506 0040 2846 mov r0, r5 + 507 .LVL34: + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 508 .loc 1 342 16 view .LVU127 + 509 0042 FFF7FEFF bl FLASH_OB_RDP_LevelConfig + 510 .LVL35: + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 511 .loc 1 342 16 view .LVU128 + 512 0046 E4E7 b .L35 + 513 .L39: + 514 .align 2 + 515 .L38: + 516 0048 00000000 .word pFlash + 517 004c 00200240 .word 1073881088 + 518 .cfi_endproc + 519 .LFE132: + 521 .section .text.FLASH_OB_EnableWRP,"ax",%progbits + 522 .align 1 + 523 .syntax unified + 524 .thumb + 525 .thumb_func + 527 FLASH_OB_EnableWRP: + 528 .LVL36: + 529 .LFB137: + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 530 .loc 1 522 1 is_stmt 1 view -0 + 531 .cfi_startproc + 532 @ args = 0, pretend = 0, frame = 0 + 533 @ frame_needed = 0, uses_anonymous_args = 0 + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 534 .loc 1 522 1 is_stmt 0 view .LVU130 + 535 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 536 .cfi_def_cfa_offset 24 + 537 .cfi_offset 3, -24 + 538 .cfi_offset 4, -20 + 539 .cfi_offset 5, -16 + 540 .cfi_offset 6, -12 + 541 .cfi_offset 7, -8 + 542 .cfi_offset 14, -4 + 543 0002 0446 mov r4, r0 + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP0_Data = 0xFFFFU; + 544 .loc 1 523 3 is_stmt 1 view .LVU131 + 545 .LVL37: + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 546 .loc 1 524 3 view .LVU132 + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 547 .loc 1 526 3 view .LVU133 + ARM GAS /tmp/ccLRLOP3.s page 46 + + + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 548 .loc 1 529 3 view .LVU134 + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 549 .loc 1 532 3 view .LVU135 + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 550 .loc 1 536 3 view .LVU136 + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 551 .loc 1 539 3 view .LVU137 + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 552 .loc 1 539 37 is_stmt 0 view .LVU138 + 553 0004 FFF7FEFF bl FLASH_OB_GetWRP + 554 .LVL38: + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 555 .loc 1 539 20 view .LVU139 + 556 0008 20EA0400 bic r0, r0, r4 + 557 .LVL39: + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES0TO31MASK */ + 558 .loc 1 542 3 is_stmt 1 view .LVU140 + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES0TO31MASK */ + 559 .loc 1 542 13 is_stmt 0 view .LVU141 + 560 000c C5B2 uxtb r5, r0 + 561 .LVL40: + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO63MASK */ + 562 .loc 1 546 3 is_stmt 1 view .LVU142 + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO63MASK */ + 563 .loc 1 546 13 is_stmt 0 view .LVU143 + 564 000e C0F30727 ubfx r7, r0, #8, #8 + 565 .LVL41: + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO47MASK */ + 566 .loc 1 550 3 is_stmt 1 view .LVU144 + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO47MASK */ + 567 .loc 1 550 13 is_stmt 0 view .LVU145 + 568 0012 C0F30746 ubfx r6, r0, #16, #8 + 569 .LVL42: + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(OB_WRP_PAGES48TO255MASK) + 570 .loc 1 554 3 is_stmt 1 view .LVU146 + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(OB_WRP_PAGES48TO255MASK) + 571 .loc 1 554 13 is_stmt 0 view .LVU147 + 572 0016 040E lsrs r4, r0, #24 + 573 .LVL43: + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 574 .loc 1 560 3 is_stmt 1 view .LVU148 + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 575 .loc 1 560 12 is_stmt 0 view .LVU149 + 576 0018 4CF25030 movw r0, #50000 + 577 .LVL44: + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 578 .loc 1 560 12 view .LVU150 + 579 001c FFF7FEFF bl FLASH_WaitForLastOperation + 580 .LVL45: + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 581 .loc 1 562 3 is_stmt 1 view .LVU151 + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 582 .loc 1 562 5 is_stmt 0 view .LVU152 + 583 0020 0346 mov r3, r0 + 584 0022 08B1 cbz r0, .L47 + 585 .LVL46: + ARM GAS /tmp/ccLRLOP3.s page 47 + + + 586 .L41: + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 587 .loc 1 619 3 is_stmt 1 view .LVU153 + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 588 .loc 1 620 1 is_stmt 0 view .LVU154 + 589 0024 1846 mov r0, r3 + 590 0026 F8BD pop {r3, r4, r5, r6, r7, pc} + 591 .LVL47: + 592 .L47: + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 593 .loc 1 565 5 is_stmt 1 view .LVU155 + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 594 .loc 1 565 22 is_stmt 0 view .LVU156 + 595 0028 234B ldr r3, .L52 + 596 002a 0022 movs r2, #0 + 597 002c DA61 str r2, [r3, #28] + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK) + 598 .loc 1 568 5 is_stmt 1 view .LVU157 + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK) + 599 .loc 1 568 14 is_stmt 0 view .LVU158 + 600 002e FFF7FEFF bl HAL_FLASHEx_OBErase + 601 .LVL48: + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 602 .loc 1 569 5 is_stmt 1 view .LVU159 + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 603 .loc 1 569 8 is_stmt 0 view .LVU160 + 604 0032 0346 mov r3, r0 + 605 0034 0028 cmp r0, #0 + 606 0036 F5D1 bne .L41 + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 607 .loc 1 572 7 is_stmt 1 view .LVU161 + 608 0038 2049 ldr r1, .L52+4 + 609 003a 0A69 ldr r2, [r1, #16] + 610 003c 42F01002 orr r2, r2, #16 + 611 0040 0A61 str r2, [r1, #16] + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 612 .loc 1 575 7 view .LVU162 + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 613 .loc 1 575 9 is_stmt 0 view .LVU163 + 614 0042 FF2D cmp r5, #255 + 615 0044 0ED1 bne .L48 + 616 .LVL49: + 617 .L42: + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 618 .loc 1 585 7 is_stmt 1 view .LVU164 + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 619 .loc 1 585 9 is_stmt 0 view .LVU165 + 620 0046 23B9 cbnz r3, .L43 + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 621 .loc 1 585 29 discriminator 1 view .LVU166 + 622 0048 FF2F cmp r7, #255 + 623 004a 15D1 bne .L49 + 624 .LVL50: + 625 .L44: + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 626 .loc 1 595 7 is_stmt 1 view .LVU167 + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + ARM GAS /tmp/ccLRLOP3.s page 48 + + + 627 .loc 1 595 9 is_stmt 0 view .LVU168 + 628 004c 23B9 cbnz r3, .L45 + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 629 .loc 1 595 29 discriminator 1 view .LVU169 + 630 004e FF2E cmp r6, #255 + 631 0050 1CD1 bne .L50 + 632 .LVL51: + 633 .L43: + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 634 .loc 1 605 7 is_stmt 1 view .LVU170 + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 635 .loc 1 605 9 is_stmt 0 view .LVU171 + 636 0052 0BB9 cbnz r3, .L45 + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 637 .loc 1 605 29 discriminator 1 view .LVU172 + 638 0054 FF2C cmp r4, #255 + 639 0056 23D1 bne .L51 + 640 .L45: + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 641 .loc 1 615 7 is_stmt 1 view .LVU173 + 642 0058 1849 ldr r1, .L52+4 + 643 005a 0A69 ldr r2, [r1, #16] + 644 005c 22F01002 bic r2, r2, #16 + 645 0060 0A61 str r2, [r1, #16] + 646 0062 DFE7 b .L41 + 647 .LVL52: + 648 .L48: + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 649 .loc 1 577 9 view .LVU174 + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 650 .loc 1 577 11 is_stmt 0 view .LVU175 + 651 0064 164B ldr r3, .L52+8 + 652 0066 1A89 ldrh r2, [r3, #8] + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 653 .loc 1 577 18 view .LVU176 + 654 0068 1540 ands r5, r5, r2 + 655 .LVL53: + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 656 .loc 1 577 18 view .LVU177 + 657 006a 1D81 strh r5, [r3, #8] @ movhi + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 658 .loc 1 580 9 is_stmt 1 view .LVU178 + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 659 .loc 1 580 18 is_stmt 0 view .LVU179 + 660 006c 4CF25030 movw r0, #50000 + 661 .LVL54: + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 662 .loc 1 580 18 view .LVU180 + 663 0070 FFF7FEFF bl FLASH_WaitForLastOperation + 664 .LVL55: + 665 0074 0346 mov r3, r0 + 666 .LVL56: + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 667 .loc 1 580 18 view .LVU181 + 668 0076 E6E7 b .L42 + 669 .L49: + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccLRLOP3.s page 49 + + + 670 .loc 1 587 9 is_stmt 1 view .LVU182 + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 671 .loc 1 587 11 is_stmt 0 view .LVU183 + 672 0078 114B ldr r3, .L52+8 + 673 .LVL57: + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 674 .loc 1 587 11 view .LVU184 + 675 007a 5A89 ldrh r2, [r3, #10] + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 676 .loc 1 587 18 view .LVU185 + 677 007c 1740 ands r7, r7, r2 + 678 .LVL58: + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 679 .loc 1 587 18 view .LVU186 + 680 007e 5F81 strh r7, [r3, #10] @ movhi + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 681 .loc 1 590 9 is_stmt 1 view .LVU187 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 682 .loc 1 590 18 is_stmt 0 view .LVU188 + 683 0080 4CF25030 movw r0, #50000 + 684 0084 FFF7FEFF bl FLASH_WaitForLastOperation + 685 .LVL59: + 686 0088 0346 mov r3, r0 + 687 .LVL60: + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 688 .loc 1 590 18 view .LVU189 + 689 008a DFE7 b .L44 + 690 .L50: + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 691 .loc 1 597 9 is_stmt 1 view .LVU190 + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 692 .loc 1 597 11 is_stmt 0 view .LVU191 + 693 008c 0C4B ldr r3, .L52+8 + 694 .LVL61: + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 695 .loc 1 597 11 view .LVU192 + 696 008e 9A89 ldrh r2, [r3, #12] + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 697 .loc 1 597 18 view .LVU193 + 698 0090 1640 ands r6, r6, r2 + 699 .LVL62: + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 700 .loc 1 597 18 view .LVU194 + 701 0092 9E81 strh r6, [r3, #12] @ movhi + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 702 .loc 1 600 9 is_stmt 1 view .LVU195 + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 703 .loc 1 600 18 is_stmt 0 view .LVU196 + 704 0094 4CF25030 movw r0, #50000 + 705 0098 FFF7FEFF bl FLASH_WaitForLastOperation + 706 .LVL63: + 707 009c 0346 mov r3, r0 + 708 .LVL64: + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 709 .loc 1 600 18 view .LVU197 + 710 009e D8E7 b .L43 + 711 .L51: + ARM GAS /tmp/ccLRLOP3.s page 50 + + + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 712 .loc 1 607 9 is_stmt 1 view .LVU198 + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 713 .loc 1 607 11 is_stmt 0 view .LVU199 + 714 00a0 074B ldr r3, .L52+8 + 715 .LVL65: + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 716 .loc 1 607 11 view .LVU200 + 717 00a2 DA89 ldrh r2, [r3, #14] + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 718 .loc 1 607 18 view .LVU201 + 719 00a4 04EA0200 and r0, r4, r2 + 720 00a8 D881 strh r0, [r3, #14] @ movhi + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 721 .loc 1 610 9 is_stmt 1 view .LVU202 + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 722 .loc 1 610 18 is_stmt 0 view .LVU203 + 723 00aa 4CF25030 movw r0, #50000 + 724 00ae FFF7FEFF bl FLASH_WaitForLastOperation + 725 .LVL66: + 726 00b2 0346 mov r3, r0 + 727 .LVL67: + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 728 .loc 1 610 18 view .LVU204 + 729 00b4 D0E7 b .L45 + 730 .L53: + 731 00b6 00BF .align 2 + 732 .L52: + 733 00b8 00000000 .word pFlash + 734 00bc 00200240 .word 1073881088 + 735 00c0 00F8FF1F .word 536868864 + 736 .cfi_endproc + 737 .LFE137: + 739 .section .text.FLASH_OB_DisableWRP,"ax",%progbits + 740 .align 1 + 741 .syntax unified + 742 .thumb + 743 .thumb_func + 745 FLASH_OB_DisableWRP: + 746 .LVL68: + 747 .LFB138: + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 748 .loc 1 634 1 is_stmt 1 view -0 + 749 .cfi_startproc + 750 @ args = 0, pretend = 0, frame = 0 + 751 @ frame_needed = 0, uses_anonymous_args = 0 + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 752 .loc 1 634 1 is_stmt 0 view .LVU206 + 753 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 754 .cfi_def_cfa_offset 24 + 755 .cfi_offset 3, -24 + 756 .cfi_offset 4, -20 + 757 .cfi_offset 5, -16 + 758 .cfi_offset 6, -12 + 759 .cfi_offset 7, -8 + 760 .cfi_offset 14, -4 + 761 0002 0446 mov r4, r0 + ARM GAS /tmp/ccLRLOP3.s page 51 + + + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP0_Data = 0xFFFFU; + 762 .loc 1 635 3 is_stmt 1 view .LVU207 + 763 .LVL69: + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 764 .loc 1 636 3 view .LVU208 + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 765 .loc 1 638 3 view .LVU209 + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 766 .loc 1 641 3 view .LVU210 + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 767 .loc 1 644 3 view .LVU211 + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 768 .loc 1 648 3 view .LVU212 + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 769 .loc 1 651 3 view .LVU213 + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 770 .loc 1 651 23 is_stmt 0 view .LVU214 + 771 0004 FFF7FEFF bl FLASH_OB_GetWRP + 772 .LVL70: + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 773 .loc 1 651 20 view .LVU215 + 774 0008 2043 orrs r0, r0, r4 + 775 .LVL71: + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES0TO31MASK */ + 776 .loc 1 654 3 is_stmt 1 view .LVU216 + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES0TO31MASK */ + 777 .loc 1 654 13 is_stmt 0 view .LVU217 + 778 000a C5B2 uxtb r5, r0 + 779 .LVL72: + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO63MASK */ + 780 .loc 1 658 3 is_stmt 1 view .LVU218 + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO63MASK */ + 781 .loc 1 658 13 is_stmt 0 view .LVU219 + 782 000c C0F30727 ubfx r7, r0, #8, #8 + 783 .LVL73: + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO47MASK */ + 784 .loc 1 662 3 is_stmt 1 view .LVU220 + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO47MASK */ + 785 .loc 1 662 13 is_stmt 0 view .LVU221 + 786 0010 C0F30746 ubfx r6, r0, #16, #8 + 787 .LVL74: + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(OB_WRP_PAGES48TO255MASK) + 788 .loc 1 666 3 is_stmt 1 view .LVU222 + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(OB_WRP_PAGES48TO255MASK) + 789 .loc 1 666 13 is_stmt 0 view .LVU223 + 790 0014 040E lsrs r4, r0, #24 + 791 .LVL75: + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 792 .loc 1 673 3 is_stmt 1 view .LVU224 + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 793 .loc 1 673 12 is_stmt 0 view .LVU225 + 794 0016 4CF25030 movw r0, #50000 + 795 .LVL76: + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 796 .loc 1 673 12 view .LVU226 + 797 001a FFF7FEFF bl FLASH_WaitForLastOperation + 798 .LVL77: + ARM GAS /tmp/ccLRLOP3.s page 52 + + + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 799 .loc 1 675 3 is_stmt 1 view .LVU227 + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 800 .loc 1 675 5 is_stmt 0 view .LVU228 + 801 001e 0346 mov r3, r0 + 802 0020 08B1 cbz r0, .L61 + 803 .LVL78: + 804 .L55: + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 805 .loc 1 730 3 is_stmt 1 view .LVU229 + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 806 .loc 1 731 1 is_stmt 0 view .LVU230 + 807 0022 1846 mov r0, r3 + 808 0024 F8BD pop {r3, r4, r5, r6, r7, pc} + 809 .LVL79: + 810 .L61: + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 811 .loc 1 678 5 is_stmt 1 view .LVU231 + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 812 .loc 1 678 22 is_stmt 0 view .LVU232 + 813 0026 254B ldr r3, .L66 + 814 0028 0022 movs r2, #0 + 815 002a DA61 str r2, [r3, #28] + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK) + 816 .loc 1 681 5 is_stmt 1 view .LVU233 + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK) + 817 .loc 1 681 14 is_stmt 0 view .LVU234 + 818 002c FFF7FEFF bl HAL_FLASHEx_OBErase + 819 .LVL80: + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 820 .loc 1 682 5 is_stmt 1 view .LVU235 + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 821 .loc 1 682 8 is_stmt 0 view .LVU236 + 822 0030 0346 mov r3, r0 + 823 0032 0028 cmp r0, #0 + 824 0034 F5D1 bne .L55 + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 825 .loc 1 684 7 is_stmt 1 view .LVU237 + 826 0036 2249 ldr r1, .L66+4 + 827 0038 0A69 ldr r2, [r1, #16] + 828 003a 42F01002 orr r2, r2, #16 + 829 003e 0A61 str r2, [r1, #16] + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 830 .loc 1 687 7 view .LVU238 + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 831 .loc 1 687 9 is_stmt 0 view .LVU239 + 832 0040 FF2D cmp r5, #255 + 833 0042 0ED1 bne .L62 + 834 .LVL81: + 835 .L56: + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 836 .loc 1 697 7 is_stmt 1 view .LVU240 + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 837 .loc 1 697 9 is_stmt 0 view .LVU241 + 838 0044 23B9 cbnz r3, .L57 + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 839 .loc 1 697 29 discriminator 1 view .LVU242 + ARM GAS /tmp/ccLRLOP3.s page 53 + + + 840 0046 FF2F cmp r7, #255 + 841 0048 16D1 bne .L63 + 842 .L58: + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 843 .loc 1 707 7 is_stmt 1 view .LVU243 + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 844 .loc 1 707 9 is_stmt 0 view .LVU244 + 845 004a 23B9 cbnz r3, .L59 + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 846 .loc 1 707 29 discriminator 1 view .LVU245 + 847 004c FF2E cmp r6, #255 + 848 004e 1ED1 bne .L64 + 849 .L57: + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 850 .loc 1 717 7 is_stmt 1 view .LVU246 + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 851 .loc 1 717 9 is_stmt 0 view .LVU247 + 852 0050 0BB9 cbnz r3, .L59 + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 853 .loc 1 717 29 discriminator 1 view .LVU248 + 854 0052 FF2C cmp r4, #255 + 855 0054 26D1 bne .L65 + 856 .L59: + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 857 .loc 1 727 7 is_stmt 1 view .LVU249 + 858 0056 1A49 ldr r1, .L66+4 + 859 0058 0A69 ldr r2, [r1, #16] + 860 005a 22F01002 bic r2, r2, #16 + 861 005e 0A61 str r2, [r1, #16] + 862 0060 DFE7 b .L55 + 863 .LVL82: + 864 .L62: + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 865 .loc 1 689 9 view .LVU250 + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 866 .loc 1 689 11 is_stmt 0 view .LVU251 + 867 0062 184A ldr r2, .L66+8 + 868 0064 1389 ldrh r3, [r2, #8] + 869 0066 9BB2 uxth r3, r3 + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 870 .loc 1 689 18 view .LVU252 + 871 0068 2B43 orrs r3, r3, r5 + 872 006a 1381 strh r3, [r2, #8] @ movhi + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 873 .loc 1 692 9 is_stmt 1 view .LVU253 + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 874 .loc 1 692 18 is_stmt 0 view .LVU254 + 875 006c 4CF25030 movw r0, #50000 + 876 .LVL83: + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 877 .loc 1 692 18 view .LVU255 + 878 0070 FFF7FEFF bl FLASH_WaitForLastOperation + 879 .LVL84: + 880 0074 0346 mov r3, r0 + 881 .LVL85: + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 882 .loc 1 692 18 view .LVU256 + ARM GAS /tmp/ccLRLOP3.s page 54 + + + 883 0076 E5E7 b .L56 + 884 .L63: + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 885 .loc 1 699 9 is_stmt 1 view .LVU257 + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 886 .loc 1 699 11 is_stmt 0 view .LVU258 + 887 0078 124A ldr r2, .L66+8 + 888 007a 5389 ldrh r3, [r2, #10] + 889 .LVL86: + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 890 .loc 1 699 11 view .LVU259 + 891 007c 9BB2 uxth r3, r3 + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 892 .loc 1 699 18 view .LVU260 + 893 007e 3B43 orrs r3, r3, r7 + 894 0080 5381 strh r3, [r2, #10] @ movhi + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 895 .loc 1 702 9 is_stmt 1 view .LVU261 + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 896 .loc 1 702 18 is_stmt 0 view .LVU262 + 897 0082 4CF25030 movw r0, #50000 + 898 0086 FFF7FEFF bl FLASH_WaitForLastOperation + 899 .LVL87: + 900 008a 0346 mov r3, r0 + 901 .LVL88: + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 902 .loc 1 702 18 view .LVU263 + 903 008c DDE7 b .L58 + 904 .L64: + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 905 .loc 1 709 9 is_stmt 1 view .LVU264 + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 906 .loc 1 709 11 is_stmt 0 view .LVU265 + 907 008e 0D4A ldr r2, .L66+8 + 908 0090 9389 ldrh r3, [r2, #12] + 909 .LVL89: + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 910 .loc 1 709 11 view .LVU266 + 911 0092 9BB2 uxth r3, r3 + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 912 .loc 1 709 18 view .LVU267 + 913 0094 3343 orrs r3, r3, r6 + 914 0096 9381 strh r3, [r2, #12] @ movhi + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 915 .loc 1 712 9 is_stmt 1 view .LVU268 + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 916 .loc 1 712 18 is_stmt 0 view .LVU269 + 917 0098 4CF25030 movw r0, #50000 + 918 009c FFF7FEFF bl FLASH_WaitForLastOperation + 919 .LVL90: + 920 00a0 0346 mov r3, r0 + 921 .LVL91: + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 922 .loc 1 712 18 view .LVU270 + 923 00a2 D5E7 b .L57 + 924 .L65: + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccLRLOP3.s page 55 + + + 925 .loc 1 719 9 is_stmt 1 view .LVU271 + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 926 .loc 1 719 11 is_stmt 0 view .LVU272 + 927 00a4 074A ldr r2, .L66+8 + 928 00a6 D389 ldrh r3, [r2, #14] + 929 .LVL92: + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 930 .loc 1 719 11 view .LVU273 + 931 00a8 9BB2 uxth r3, r3 + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 932 .loc 1 719 18 view .LVU274 + 933 00aa 2343 orrs r3, r3, r4 + 934 00ac D381 strh r3, [r2, #14] @ movhi + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 935 .loc 1 722 9 is_stmt 1 view .LVU275 + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 936 .loc 1 722 18 is_stmt 0 view .LVU276 + 937 00ae 4CF25030 movw r0, #50000 + 938 00b2 FFF7FEFF bl FLASH_WaitForLastOperation + 939 .LVL93: + 940 00b6 0346 mov r3, r0 + 941 .LVL94: + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 942 .loc 1 722 18 view .LVU277 + 943 00b8 CDE7 b .L59 + 944 .L67: + 945 00ba 00BF .align 2 + 946 .L66: + 947 00bc 00000000 .word pFlash + 948 00c0 00200240 .word 1073881088 + 949 00c4 00F8FF1F .word 536868864 + 950 .cfi_endproc + 951 .LFE138: + 953 .section .text.HAL_FLASHEx_OBProgram,"ax",%progbits + 954 .align 1 + 955 .global HAL_FLASHEx_OBProgram + 956 .syntax unified + 957 .thumb + 958 .thumb_func + 960 HAL_FLASHEx_OBProgram: + 961 .LVL95: + 962 .LFB133: + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 963 .loc 1 363 1 is_stmt 1 view -0 + 964 .cfi_startproc + 965 @ args = 0, pretend = 0, frame = 0 + 966 @ frame_needed = 0, uses_anonymous_args = 0 + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 967 .loc 1 364 3 view .LVU279 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 968 .loc 1 367 3 view .LVU280 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 969 .loc 1 367 3 view .LVU281 + 970 0000 254B ldr r3, .L86 + 971 0002 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 972 0004 012B cmp r3, #1 + 973 0006 44D0 beq .L76 + ARM GAS /tmp/ccLRLOP3.s page 56 + + + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 974 .loc 1 363 1 is_stmt 0 discriminator 2 view .LVU282 + 975 0008 10B5 push {r4, lr} + 976 .cfi_def_cfa_offset 8 + 977 .cfi_offset 4, -8 + 978 .cfi_offset 14, -4 + 979 000a 0446 mov r4, r0 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 980 .loc 1 367 3 is_stmt 1 discriminator 2 view .LVU283 + 981 000c 224B ldr r3, .L86 + 982 000e 0122 movs r2, #1 + 983 0010 1A76 strb r2, [r3, #24] + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 984 .loc 1 367 3 discriminator 2 view .LVU284 + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 985 .loc 1 370 3 discriminator 2 view .LVU285 + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 986 .loc 1 373 3 discriminator 2 view .LVU286 + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 987 .loc 1 373 14 is_stmt 0 discriminator 2 view .LVU287 + 988 0012 0368 ldr r3, [r0] + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 989 .loc 1 373 5 discriminator 2 view .LVU288 + 990 0014 13F0010F tst r3, #1 + 991 0018 0ED0 beq .L77 + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + 992 .loc 1 375 5 is_stmt 1 view .LVU289 + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 993 .loc 1 376 5 view .LVU290 + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 994 .loc 1 376 16 is_stmt 0 view .LVU291 + 995 001a 4368 ldr r3, [r0, #4] + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 996 .loc 1 376 8 view .LVU292 + 997 001c 9342 cmp r3, r2 + 998 001e 07D0 beq .L82 + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 999 .loc 1 384 7 is_stmt 1 view .LVU293 + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1000 .loc 1 384 16 is_stmt 0 view .LVU294 + 1001 0020 8068 ldr r0, [r0, #8] + 1002 .LVL96: + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1003 .loc 1 384 16 view .LVU295 + 1004 0022 FFF7FEFF bl FLASH_OB_DisableWRP + 1005 .LVL97: + 1006 .L72: + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1007 .loc 1 386 5 is_stmt 1 view .LVU296 + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1008 .loc 1 386 8 is_stmt 0 view .LVU297 + 1009 0026 40B1 cbz r0, .L70 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1010 .loc 1 389 7 is_stmt 1 view .LVU298 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1011 .loc 1 389 7 view .LVU299 + 1012 0028 1B4B ldr r3, .L86 + ARM GAS /tmp/ccLRLOP3.s page 57 + + + 1013 002a 0022 movs r2, #0 + 1014 002c 1A76 strb r2, [r3, #24] + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1015 .loc 1 389 7 view .LVU300 + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1016 .loc 1 390 7 view .LVU301 + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1017 .loc 1 390 14 is_stmt 0 view .LVU302 + 1018 002e 13E0 b .L69 + 1019 .LVL98: + 1020 .L82: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1021 .loc 1 379 7 is_stmt 1 view .LVU303 + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1022 .loc 1 379 16 is_stmt 0 view .LVU304 + 1023 0030 8068 ldr r0, [r0, #8] + 1024 .LVL99: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1025 .loc 1 379 16 view .LVU305 + 1026 0032 FFF7FEFF bl FLASH_OB_EnableWRP + 1027 .LVL100: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1028 .loc 1 379 16 view .LVU306 + 1029 0036 F6E7 b .L72 + 1030 .LVL101: + 1031 .L77: + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1032 .loc 1 364 21 view .LVU307 + 1033 0038 0120 movs r0, #1 + 1034 .LVL102: + 1035 .L70: + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1036 .loc 1 395 3 is_stmt 1 view .LVU308 + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1037 .loc 1 395 14 is_stmt 0 view .LVU309 + 1038 003a 2368 ldr r3, [r4] + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1039 .loc 1 395 5 view .LVU310 + 1040 003c 13F0020F tst r3, #2 + 1041 0040 0BD1 bne .L83 + 1042 .L73: + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1043 .loc 1 407 3 is_stmt 1 view .LVU311 + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1044 .loc 1 407 14 is_stmt 0 view .LVU312 + 1045 0042 2368 ldr r3, [r4] + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1046 .loc 1 407 5 view .LVU313 + 1047 0044 13F0040F tst r3, #4 + 1048 0048 10D1 bne .L84 + 1049 .L74: + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1050 .loc 1 419 3 is_stmt 1 view .LVU314 + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1051 .loc 1 419 14 is_stmt 0 view .LVU315 + 1052 004a 2368 ldr r3, [r4] + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + ARM GAS /tmp/ccLRLOP3.s page 58 + + + 1053 .loc 1 419 5 view .LVU316 + 1054 004c 13F0080F tst r3, #8 + 1055 0050 15D1 bne .L85 + 1056 .L75: + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1057 .loc 1 431 3 is_stmt 1 view .LVU317 + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1058 .loc 1 431 3 view .LVU318 + 1059 0052 114B ldr r3, .L86 + 1060 0054 0022 movs r2, #0 + 1061 0056 1A76 strb r2, [r3, #24] + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1062 .loc 1 431 3 view .LVU319 + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1063 .loc 1 433 3 view .LVU320 + 1064 .L69: + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1065 .loc 1 434 1 is_stmt 0 view .LVU321 + 1066 0058 10BD pop {r4, pc} + 1067 .LVL103: + 1068 .L83: + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1069 .loc 1 397 5 is_stmt 1 view .LVU322 + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1070 .loc 1 397 14 is_stmt 0 view .LVU323 + 1071 005a 207B ldrb r0, [r4, #12] @ zero_extendqisi2 + 1072 .LVL104: + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1073 .loc 1 397 14 view .LVU324 + 1074 005c FFF7FEFF bl FLASH_OB_RDP_LevelConfig + 1075 .LVL105: + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1076 .loc 1 398 5 is_stmt 1 view .LVU325 + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1077 .loc 1 398 8 is_stmt 0 view .LVU326 + 1078 0060 0028 cmp r0, #0 + 1079 0062 EED0 beq .L73 + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1080 .loc 1 401 7 is_stmt 1 view .LVU327 + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1081 .loc 1 401 7 view .LVU328 + 1082 0064 0C4B ldr r3, .L86 + 1083 0066 0022 movs r2, #0 + 1084 0068 1A76 strb r2, [r3, #24] + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1085 .loc 1 401 7 view .LVU329 + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1086 .loc 1 402 7 view .LVU330 + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1087 .loc 1 402 14 is_stmt 0 view .LVU331 + 1088 006a F5E7 b .L69 + 1089 .L84: + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1090 .loc 1 409 5 is_stmt 1 view .LVU332 + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1091 .loc 1 409 14 is_stmt 0 view .LVU333 + 1092 006c 607B ldrb r0, [r4, #13] @ zero_extendqisi2 + ARM GAS /tmp/ccLRLOP3.s page 59 + + + 1093 .LVL106: + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1094 .loc 1 409 14 view .LVU334 + 1095 006e FFF7FEFF bl FLASH_OB_UserConfig + 1096 .LVL107: + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1097 .loc 1 410 5 is_stmt 1 view .LVU335 + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1098 .loc 1 410 8 is_stmt 0 view .LVU336 + 1099 0072 0028 cmp r0, #0 + 1100 0074 E9D0 beq .L74 + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1101 .loc 1 413 7 is_stmt 1 view .LVU337 + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1102 .loc 1 413 7 view .LVU338 + 1103 0076 084B ldr r3, .L86 + 1104 0078 0022 movs r2, #0 + 1105 007a 1A76 strb r2, [r3, #24] + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1106 .loc 1 413 7 view .LVU339 + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1107 .loc 1 414 7 view .LVU340 + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1108 .loc 1 414 14 is_stmt 0 view .LVU341 + 1109 007c ECE7 b .L69 + 1110 .L85: + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1111 .loc 1 421 5 is_stmt 1 view .LVU342 + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1112 .loc 1 421 14 is_stmt 0 view .LVU343 + 1113 007e 217D ldrb r1, [r4, #20] @ zero_extendqisi2 + 1114 0080 2069 ldr r0, [r4, #16] + 1115 .LVL108: + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 1116 .loc 1 421 14 view .LVU344 + 1117 0082 FFF7FEFF bl FLASH_OB_ProgramData + 1118 .LVL109: + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1119 .loc 1 422 5 is_stmt 1 view .LVU345 + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1120 .loc 1 422 8 is_stmt 0 view .LVU346 + 1121 0086 0028 cmp r0, #0 + 1122 0088 E3D0 beq .L75 + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1123 .loc 1 425 7 is_stmt 1 view .LVU347 + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1124 .loc 1 425 7 view .LVU348 + 1125 008a 034B ldr r3, .L86 + 1126 008c 0022 movs r2, #0 + 1127 008e 1A76 strb r2, [r3, #24] + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1128 .loc 1 425 7 view .LVU349 + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1129 .loc 1 426 7 view .LVU350 + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1130 .loc 1 426 14 is_stmt 0 view .LVU351 + 1131 0090 E2E7 b .L69 + ARM GAS /tmp/ccLRLOP3.s page 60 + + + 1132 .LVL110: + 1133 .L76: + 1134 .cfi_def_cfa_offset 0 + 1135 .cfi_restore 4 + 1136 .cfi_restore 14 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1137 .loc 1 367 3 view .LVU352 + 1138 0092 0220 movs r0, #2 + 1139 .LVL111: + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1140 .loc 1 434 1 view .LVU353 + 1141 0094 7047 bx lr + 1142 .L87: + 1143 0096 00BF .align 2 + 1144 .L86: + 1145 0098 00000000 .word pFlash + 1146 .cfi_endproc + 1147 .LFE133: + 1149 .section .text.HAL_FLASHEx_OBGetConfig,"ax",%progbits + 1150 .align 1 + 1151 .global HAL_FLASHEx_OBGetConfig + 1152 .syntax unified + 1153 .thumb + 1154 .thumb_func + 1156 HAL_FLASHEx_OBGetConfig: + 1157 .LVL112: + 1158 .LFB134: + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + 1159 .loc 1 444 1 is_stmt 1 view -0 + 1160 .cfi_startproc + 1161 @ args = 0, pretend = 0, frame = 0 + 1162 @ frame_needed = 0, uses_anonymous_args = 0 + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + 1163 .loc 1 444 1 is_stmt 0 view .LVU355 + 1164 0000 10B5 push {r4, lr} + 1165 .cfi_def_cfa_offset 8 + 1166 .cfi_offset 4, -8 + 1167 .cfi_offset 14, -4 + 1168 0002 0446 mov r4, r0 + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1169 .loc 1 445 3 is_stmt 1 view .LVU356 + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1170 .loc 1 445 23 is_stmt 0 view .LVU357 + 1171 0004 0723 movs r3, #7 + 1172 0006 0360 str r3, [r0] + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1173 .loc 1 448 3 is_stmt 1 view .LVU358 + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1174 .loc 1 448 22 is_stmt 0 view .LVU359 + 1175 0008 FFF7FEFF bl FLASH_OB_GetWRP + 1176 .LVL113: + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1177 .loc 1 448 20 view .LVU360 + 1178 000c A060 str r0, [r4, #8] + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1179 .loc 1 451 3 is_stmt 1 view .LVU361 + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccLRLOP3.s page 61 + + + 1180 .loc 1 451 23 is_stmt 0 view .LVU362 + 1181 000e FFF7FEFF bl FLASH_OB_GetRDP + 1182 .LVL114: + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1183 .loc 1 451 21 view .LVU363 + 1184 0012 2073 strb r0, [r4, #12] + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1185 .loc 1 454 3 is_stmt 1 view .LVU364 + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1186 .loc 1 454 25 is_stmt 0 view .LVU365 + 1187 0014 FFF7FEFF bl FLASH_OB_GetUser + 1188 .LVL115: + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1189 .loc 1 454 23 view .LVU366 + 1190 0018 6073 strb r0, [r4, #13] + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1191 .loc 1 455 1 view .LVU367 + 1192 001a 10BD pop {r4, pc} + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1193 .loc 1 455 1 view .LVU368 + 1194 .cfi_endproc + 1195 .LFE134: + 1197 .section .text.HAL_FLASHEx_OBGetUserData,"ax",%progbits + 1198 .align 1 + 1199 .global HAL_FLASHEx_OBGetUserData + 1200 .syntax unified + 1201 .thumb + 1202 .thumb_func + 1204 HAL_FLASHEx_OBGetUserData: + 1205 .LVL116: + 1206 .LFB135: + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t value = 0U; + 1207 .loc 1 466 1 is_stmt 1 view -0 + 1208 .cfi_startproc + 1209 @ args = 0, pretend = 0, frame = 0 + 1210 @ frame_needed = 0, uses_anonymous_args = 0 + 1211 @ link register save eliminated. + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1212 .loc 1 467 3 view .LVU370 + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1213 .loc 1 469 3 view .LVU371 + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1214 .loc 1 469 6 is_stmt 0 view .LVU372 + 1215 0000 0D4B ldr r3, .L94 + 1216 0002 9842 cmp r0, r3 + 1217 0004 0BD0 beq .L93 + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1218 .loc 1 477 5 is_stmt 1 view .LVU373 + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1219 .loc 1 477 13 is_stmt 0 view .LVU374 + 1220 0006 0D4B ldr r3, .L94+4 + 1221 0008 D869 ldr r0, [r3, #28] + 1222 .LVL117: + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1223 .loc 1 477 13 view .LVU375 + 1224 000a 00F07F40 and r0, r0, #-16777216 + 1225 .LVL118: + ARM GAS /tmp/ccLRLOP3.s page 62 + + + 1226 .LBB10: + 1227 .LBI10: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1228 .loc 2 981 31 is_stmt 1 view .LVU376 + 1229 .LBB11: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1230 .loc 2 983 3 view .LVU377 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1231 .loc 2 988 4 view .LVU378 + 1232 000e 4FF07F43 mov r3, #-16777216 + 1233 .syntax unified + 1234 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1235 0012 93FAA3F3 rbit r3, r3 + 1236 @ 0 "" 2 + 1237 .LVL119: + 1238 .loc 2 1001 3 view .LVU379 + 1239 .loc 2 1001 3 is_stmt 0 view .LVU380 + 1240 .thumb + 1241 .syntax unified + 1242 .LBE11: + 1243 .LBE10: + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1244 .loc 1 477 54 view .LVU381 + 1245 0016 B3FA83F3 clz r3, r3 + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1246 .loc 1 477 11 view .LVU382 + 1247 001a D840 lsrs r0, r0, r3 + 1248 .LVL120: + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1249 .loc 1 480 3 is_stmt 1 view .LVU383 + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1250 .loc 1 481 1 is_stmt 0 view .LVU384 + 1251 001c 7047 bx lr + 1252 .LVL121: + 1253 .L93: + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1254 .loc 1 472 5 is_stmt 1 view .LVU385 + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1255 .loc 1 472 13 is_stmt 0 view .LVU386 + 1256 001e 074B ldr r3, .L94+4 + 1257 0020 D869 ldr r0, [r3, #28] + 1258 .LVL122: + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1259 .loc 1 472 13 view .LVU387 + 1260 0022 00F47F00 and r0, r0, #16711680 + 1261 .LVL123: + 1262 .LBB12: + 1263 .LBI12: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1264 .loc 2 981 31 is_stmt 1 view .LVU388 + 1265 .LBB13: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1266 .loc 2 983 3 view .LVU389 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1267 .loc 2 988 4 view .LVU390 + 1268 0026 4FF47F03 mov r3, #16711680 + 1269 .syntax unified + ARM GAS /tmp/ccLRLOP3.s page 63 + + + 1270 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1271 002a 93FAA3F3 rbit r3, r3 + 1272 @ 0 "" 2 + 1273 .LVL124: + 1274 .loc 2 1001 3 view .LVU391 + 1275 .loc 2 1001 3 is_stmt 0 view .LVU392 + 1276 .thumb + 1277 .syntax unified + 1278 .LBE13: + 1279 .LBE12: + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1280 .loc 1 472 54 view .LVU393 + 1281 002e B3FA83F3 clz r3, r3 + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1282 .loc 1 472 11 view .LVU394 + 1283 0032 D840 lsrs r0, r0, r3 + 1284 .LVL125: + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1285 .loc 1 472 11 view .LVU395 + 1286 0034 7047 bx lr + 1287 .L95: + 1288 0036 00BF .align 2 + 1289 .L94: + 1290 0038 04F8FF1F .word 536868868 + 1291 003c 00200240 .word 1073881088 + 1292 .cfi_endproc + 1293 .LFE135: + 1295 .section .text.FLASH_PageErase,"ax",%progbits + 1296 .align 1 + 1297 .global FLASH_PageErase + 1298 .syntax unified + 1299 .thumb + 1300 .thumb_func + 1302 FLASH_PageErase: + 1303 .LVL126: + 1304 .LFB145: + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASH + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASH_Private_Functions + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Erase the specified FLASH memory page + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param PageAddress FLASH page to erase + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series + ARM GAS /tmp/ccLRLOP3.s page 64 + + + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval None + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** void FLASH_PageErase(uint32_t PageAddress) + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1305 .loc 1 960 1 is_stmt 1 view -0 + 1306 .cfi_startproc + 1307 @ args = 0, pretend = 0, frame = 0 + 1308 @ frame_needed = 0, uses_anonymous_args = 0 + 1309 @ link register save eliminated. + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 1310 .loc 1 962 3 view .LVU397 + 1311 .loc 1 962 20 is_stmt 0 view .LVU398 + 1312 0000 064B ldr r3, .L97 + 1313 0002 0022 movs r2, #0 + 1314 0004 DA61 str r2, [r3, #28] + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Proceed to erase the page */ + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_PER); + 1315 .loc 1 965 5 is_stmt 1 view .LVU399 + 1316 0006 064B ldr r3, .L97+4 + 1317 0008 1A69 ldr r2, [r3, #16] + 1318 000a 42F00202 orr r2, r2, #2 + 1319 000e 1A61 str r2, [r3, #16] + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRITE_REG(FLASH->AR, PageAddress); + 1320 .loc 1 966 5 view .LVU400 + 1321 0010 5861 str r0, [r3, #20] + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 1322 .loc 1 967 5 view .LVU401 + 1323 0012 1A69 ldr r2, [r3, #16] + 1324 0014 42F04002 orr r2, r2, #64 + 1325 0018 1A61 str r2, [r3, #16] + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1326 .loc 1 968 1 is_stmt 0 view .LVU402 + 1327 001a 7047 bx lr + 1328 .L98: + 1329 .align 2 + 1330 .L97: + 1331 001c 00000000 .word pFlash + 1332 0020 00200240 .word 1073881088 + 1333 .cfi_endproc + 1334 .LFE145: + 1336 .section .text.HAL_FLASHEx_Erase,"ax",%progbits + 1337 .align 1 + 1338 .global HAL_FLASHEx_Erase + 1339 .syntax unified + 1340 .thumb + 1341 .thumb_func + 1343 HAL_FLASHEx_Erase: + 1344 .LVL127: + 1345 .LFB130: + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 1346 .loc 1 160 1 is_stmt 1 view -0 + 1347 .cfi_startproc + 1348 @ args = 0, pretend = 0, frame = 0 + 1349 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccLRLOP3.s page 65 + + + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t address = 0U; + 1350 .loc 1 161 3 view .LVU404 + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1351 .loc 1 162 3 view .LVU405 + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1352 .loc 1 165 3 view .LVU406 + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1353 .loc 1 165 3 view .LVU407 + 1354 0000 264B ldr r3, .L116 + 1355 0002 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 1356 0004 012B cmp r3, #1 + 1357 0006 45D0 beq .L106 + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 1358 .loc 1 160 1 is_stmt 0 discriminator 2 view .LVU408 + 1359 0008 70B5 push {r4, r5, r6, lr} + 1360 .cfi_def_cfa_offset 16 + 1361 .cfi_offset 4, -16 + 1362 .cfi_offset 5, -12 + 1363 .cfi_offset 6, -8 + 1364 .cfi_offset 14, -4 + 1365 000a 0546 mov r5, r0 + 1366 000c 0E46 mov r6, r1 + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1367 .loc 1 165 3 is_stmt 1 discriminator 2 view .LVU409 + 1368 000e 234B ldr r3, .L116 + 1369 0010 0122 movs r2, #1 + 1370 0012 1A76 strb r2, [r3, #24] + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1371 .loc 1 165 3 discriminator 2 view .LVU410 + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1372 .loc 1 168 3 discriminator 2 view .LVU411 + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1373 .loc 1 170 3 discriminator 2 view .LVU412 + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1374 .loc 1 170 17 is_stmt 0 discriminator 2 view .LVU413 + 1375 0014 0368 ldr r3, [r0] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1376 .loc 1 170 6 discriminator 2 view .LVU414 + 1377 0016 9342 cmp r3, r2 + 1378 0018 20D0 beq .L113 + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + 1379 .loc 1 190 5 is_stmt 1 view .LVU415 + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1380 .loc 1 191 5 view .LVU416 + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1381 .loc 1 195 7 view .LVU417 + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1382 .loc 1 195 11 is_stmt 0 view .LVU418 + 1383 001a 4CF25030 movw r0, #50000 + 1384 .LVL128: + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1385 .loc 1 195 11 view .LVU419 + 1386 001e FFF7FEFF bl FLASH_WaitForLastOperation + 1387 .LVL129: + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1388 .loc 1 195 10 view .LVU420 + 1389 0022 88BB cbnz r0, .L108 + ARM GAS /tmp/ccLRLOP3.s page 66 + + + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1390 .loc 1 198 9 is_stmt 1 view .LVU421 + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1391 .loc 1 198 20 is_stmt 0 view .LVU422 + 1392 0024 4FF0FF33 mov r3, #-1 + 1393 0028 3360 str r3, [r6] + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + 1394 .loc 1 201 9 is_stmt 1 view .LVU423 + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + 1395 .loc 1 201 21 is_stmt 0 view .LVU424 + 1396 002a 6C68 ldr r4, [r5, #4] + 1397 .LVL130: + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t address = 0U; + 1398 .loc 1 161 21 view .LVU425 + 1399 002c 0121 movs r1, #1 + 1400 .LVL131: + 1401 .L103: + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 1402 .loc 1 202 21 is_stmt 1 view .LVU426 + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 1403 .loc 1 202 35 is_stmt 0 view .LVU427 + 1404 002e AA68 ldr r2, [r5, #8] + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 1405 .loc 1 202 76 view .LVU428 + 1406 0030 6B68 ldr r3, [r5, #4] + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 1407 .loc 1 202 64 view .LVU429 + 1408 0032 03EBC223 add r3, r3, r2, lsl #11 + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 1409 .loc 1 202 21 view .LVU430 + 1410 0036 A342 cmp r3, r4 + 1411 0038 27D9 bls .L102 + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1412 .loc 1 205 11 is_stmt 1 view .LVU431 + 1413 003a 2046 mov r0, r4 + 1414 003c FFF7FEFF bl FLASH_PageErase + 1415 .LVL132: + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1416 .loc 1 208 11 view .LVU432 + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1417 .loc 1 208 20 is_stmt 0 view .LVU433 + 1418 0040 4CF25030 movw r0, #50000 + 1419 0044 FFF7FEFF bl FLASH_WaitForLastOperation + 1420 .LVL133: + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1421 .loc 1 211 11 is_stmt 1 view .LVU434 + 1422 0048 154A ldr r2, .L116+4 + 1423 004a 1369 ldr r3, [r2, #16] + 1424 004c 23F00203 bic r3, r3, #2 + 1425 0050 1361 str r3, [r2, #16] + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1426 .loc 1 213 11 view .LVU435 + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1427 .loc 1 213 14 is_stmt 0 view .LVU436 + 1428 0052 0146 mov r1, r0 + 1429 0054 B0B9 cbnz r0, .L114 + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + ARM GAS /tmp/ccLRLOP3.s page 67 + + + 1430 .loc 1 203 21 is_stmt 1 view .LVU437 + 1431 0056 04F50064 add r4, r4, #2048 + 1432 .LVL134: + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1433 .loc 1 203 21 is_stmt 0 view .LVU438 + 1434 005a E8E7 b .L103 + 1435 .LVL135: + 1436 .L113: + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1437 .loc 1 174 7 is_stmt 1 view .LVU439 + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1438 .loc 1 174 11 is_stmt 0 view .LVU440 + 1439 005c 4CF25030 movw r0, #50000 + 1440 .LVL136: + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1441 .loc 1 174 11 view .LVU441 + 1442 0060 FFF7FEFF bl FLASH_WaitForLastOperation + 1443 .LVL137: + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1444 .loc 1 174 10 view .LVU442 + 1445 0064 08B1 cbz r0, .L115 + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t address = 0U; + 1446 .loc 1 161 21 view .LVU443 + 1447 0066 0121 movs r1, #1 + 1448 0068 0FE0 b .L102 + 1449 .L115: + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1450 .loc 1 177 9 is_stmt 1 view .LVU444 + 1451 006a FFF7FEFF bl FLASH_MassErase + 1452 .LVL138: + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1453 .loc 1 180 9 view .LVU445 + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1454 .loc 1 180 18 is_stmt 0 view .LVU446 + 1455 006e 4CF25030 movw r0, #50000 + 1456 0072 FFF7FEFF bl FLASH_WaitForLastOperation + 1457 .LVL139: + 1458 0076 0146 mov r1, r0 + 1459 .LVL140: + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1460 .loc 1 183 9 is_stmt 1 view .LVU447 + 1461 0078 094A ldr r2, .L116+4 + 1462 007a 1369 ldr r3, [r2, #16] + 1463 007c 23F00403 bic r3, r3, #4 + 1464 0080 1361 str r3, [r2, #16] + 1465 0082 02E0 b .L102 + 1466 .LVL141: + 1467 .L114: + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** break; + 1468 .loc 1 216 13 view .LVU448 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** break; + 1469 .loc 1 216 24 is_stmt 0 view .LVU449 + 1470 0084 3460 str r4, [r6] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1471 .loc 1 217 13 is_stmt 1 view .LVU450 + 1472 0086 00E0 b .L102 + 1473 .LVL142: + ARM GAS /tmp/ccLRLOP3.s page 68 + + + 1474 .L108: + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t address = 0U; + 1475 .loc 1 161 21 is_stmt 0 view .LVU451 + 1476 0088 0121 movs r1, #1 + 1477 .LVL143: + 1478 .L102: + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1479 .loc 1 224 3 is_stmt 1 view .LVU452 + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1480 .loc 1 224 3 view .LVU453 + 1481 008a 044B ldr r3, .L116 + 1482 008c 0022 movs r2, #0 + 1483 008e 1A76 strb r2, [r3, #24] + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1484 .loc 1 224 3 view .LVU454 + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1485 .loc 1 226 3 view .LVU455 + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1486 .loc 1 227 1 is_stmt 0 view .LVU456 + 1487 0090 0846 mov r0, r1 + 1488 0092 70BD pop {r4, r5, r6, pc} + 1489 .LVL144: + 1490 .L106: + 1491 .cfi_def_cfa_offset 0 + 1492 .cfi_restore 4 + 1493 .cfi_restore 5 + 1494 .cfi_restore 6 + 1495 .cfi_restore 14 + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1496 .loc 1 165 3 view .LVU457 + 1497 0094 0221 movs r1, #2 + 1498 .LVL145: + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1499 .loc 1 227 1 view .LVU458 + 1500 0096 0846 mov r0, r1 + 1501 .LVL146: + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1502 .loc 1 227 1 view .LVU459 + 1503 0098 7047 bx lr + 1504 .L117: + 1505 009a 00BF .align 2 + 1506 .L116: + 1507 009c 00000000 .word pFlash + 1508 00a0 00200240 .word 1073881088 + 1509 .cfi_endproc + 1510 .LFE130: + 1512 .section .text.HAL_FLASHEx_Erase_IT,"ax",%progbits + 1513 .align 1 + 1514 .global HAL_FLASHEx_Erase_IT + 1515 .syntax unified + 1516 .thumb + 1517 .thumb_func + 1519 HAL_FLASHEx_Erase_IT: + 1520 .LVL147: + 1521 .LFB131: + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1522 .loc 1 241 1 is_stmt 1 view -0 + ARM GAS /tmp/ccLRLOP3.s page 69 + + + 1523 .cfi_startproc + 1524 @ args = 0, pretend = 0, frame = 0 + 1525 @ frame_needed = 0, uses_anonymous_args = 0 + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1526 .loc 1 241 1 is_stmt 0 view .LVU461 + 1527 0000 10B5 push {r4, lr} + 1528 .cfi_def_cfa_offset 8 + 1529 .cfi_offset 4, -8 + 1530 .cfi_offset 14, -4 + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1531 .loc 1 242 3 is_stmt 1 view .LVU462 + 1532 .LVL148: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1533 .loc 1 245 3 view .LVU463 + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1534 .loc 1 245 3 view .LVU464 + 1535 0002 144B ldr r3, .L125 + 1536 0004 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 1537 0006 012B cmp r3, #1 + 1538 0008 1FD0 beq .L121 + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1539 .loc 1 245 3 discriminator 2 view .LVU465 + 1540 000a 124B ldr r3, .L125 + 1541 000c 0122 movs r2, #1 + 1542 000e 1A76 strb r2, [r3, #24] + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1543 .loc 1 245 3 discriminator 2 view .LVU466 + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1544 .loc 1 248 3 discriminator 2 view .LVU467 + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1545 .loc 1 248 13 is_stmt 0 discriminator 2 view .LVU468 + 1546 0010 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1547 .loc 1 248 6 discriminator 2 view .LVU469 + 1548 0012 03F0FF04 and r4, r3, #255 + 1549 0016 D3B9 cbnz r3, .L122 + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1550 .loc 1 254 3 is_stmt 1 view .LVU470 + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1551 .loc 1 257 3 view .LVU471 + 1552 0018 0F4A ldr r2, .L125+4 + 1553 001a 1369 ldr r3, [r2, #16] + 1554 001c 43F4A053 orr r3, r3, #5120 + 1555 0020 1361 str r3, [r2, #16] + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1556 .loc 1 259 3 view .LVU472 + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1557 .loc 1 259 17 is_stmt 0 view .LVU473 + 1558 0022 0368 ldr r3, [r0] + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1559 .loc 1 259 6 view .LVU474 + 1560 0024 012B cmp r3, #1 + 1561 0026 0AD0 beq .L124 + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + 1562 .loc 1 270 5 is_stmt 1 view .LVU475 + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1563 .loc 1 271 5 view .LVU476 + ARM GAS /tmp/ccLRLOP3.s page 70 + + + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.DataRemaining = pEraseInit->NbPages; + 1564 .loc 1 273 5 view .LVU477 + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.DataRemaining = pEraseInit->NbPages; + 1565 .loc 1 273 29 is_stmt 0 view .LVU478 + 1566 0028 0A4B ldr r3, .L125 + 1567 002a 0122 movs r2, #1 + 1568 002c 1A70 strb r2, [r3] + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.Address = pEraseInit->PageAddress; + 1569 .loc 1 274 5 is_stmt 1 view .LVU479 + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.Address = pEraseInit->PageAddress; + 1570 .loc 1 274 38 is_stmt 0 view .LVU480 + 1571 002e 8268 ldr r2, [r0, #8] + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.Address = pEraseInit->PageAddress; + 1572 .loc 1 274 26 view .LVU481 + 1573 0030 5A60 str r2, [r3, #4] + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1574 .loc 1 275 5 is_stmt 1 view .LVU482 + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1575 .loc 1 275 32 is_stmt 0 view .LVU483 + 1576 0032 4068 ldr r0, [r0, #4] + 1577 .LVL149: + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1578 .loc 1 275 20 view .LVU484 + 1579 0034 9860 str r0, [r3, #8] + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1580 .loc 1 278 5 is_stmt 1 view .LVU485 + 1581 0036 FFF7FEFF bl FLASH_PageErase + 1582 .LVL150: + 1583 .L119: + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1584 .loc 1 282 1 is_stmt 0 view .LVU486 + 1585 003a 2046 mov r0, r4 + 1586 003c 10BD pop {r4, pc} + 1587 .LVL151: + 1588 .L124: + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_MassErase(); + 1589 .loc 1 262 5 is_stmt 1 view .LVU487 + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_MassErase(); + 1590 .loc 1 262 29 is_stmt 0 view .LVU488 + 1591 003e 054B ldr r3, .L125 + 1592 0040 0222 movs r2, #2 + 1593 0042 1A70 strb r2, [r3] + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1594 .loc 1 263 9 is_stmt 1 view .LVU489 + 1595 0044 FFF7FEFF bl FLASH_MassErase + 1596 .LVL152: + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1597 .loc 1 263 9 is_stmt 0 view .LVU490 + 1598 0048 F7E7 b .L119 + 1599 .LVL153: + 1600 .L121: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 1601 .loc 1 245 3 view .LVU491 + 1602 004a 0224 movs r4, #2 + 1603 004c F5E7 b .L119 + 1604 .L122: + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccLRLOP3.s page 71 + + + 1605 .loc 1 250 12 view .LVU492 + 1606 004e 0124 movs r4, #1 + 1607 0050 F3E7 b .L119 + 1608 .L126: + 1609 0052 00BF .align 2 + 1610 .L125: + 1611 0054 00000000 .word pFlash + 1612 0058 00200240 .word 1073881088 + 1613 .cfi_endproc + 1614 .LFE131: + 1616 .text + 1617 .Letext0: + 1618 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1619 .file 4 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1620 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1621 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1622 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h" + 1623 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h" + ARM GAS /tmp/ccLRLOP3.s page 72 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_flash_ex.c + /tmp/ccLRLOP3.s:21 .text.FLASH_MassErase:0000000000000000 $t + /tmp/ccLRLOP3.s:26 .text.FLASH_MassErase:0000000000000000 FLASH_MassErase + /tmp/ccLRLOP3.s:52 .text.FLASH_MassErase:000000000000001c $d + /tmp/ccLRLOP3.s:58 .text.FLASH_OB_GetWRP:0000000000000000 $t + /tmp/ccLRLOP3.s:63 .text.FLASH_OB_GetWRP:0000000000000000 FLASH_OB_GetWRP + /tmp/ccLRLOP3.s:79 .text.FLASH_OB_GetWRP:0000000000000008 $d + /tmp/ccLRLOP3.s:84 .text.FLASH_OB_GetRDP:0000000000000000 $t + /tmp/ccLRLOP3.s:89 .text.FLASH_OB_GetRDP:0000000000000000 FLASH_OB_GetRDP + /tmp/ccLRLOP3.s:127 .text.FLASH_OB_GetRDP:000000000000001c $d + /tmp/ccLRLOP3.s:132 .text.FLASH_OB_RDP_LevelConfig:0000000000000000 $t + /tmp/ccLRLOP3.s:137 .text.FLASH_OB_RDP_LevelConfig:0000000000000000 FLASH_OB_RDP_LevelConfig + /tmp/ccLRLOP3.s:221 .text.FLASH_OB_RDP_LevelConfig:000000000000005c $d + /tmp/ccLRLOP3.s:228 .text.FLASH_OB_UserConfig:0000000000000000 $t + /tmp/ccLRLOP3.s:233 .text.FLASH_OB_UserConfig:0000000000000000 FLASH_OB_UserConfig + /tmp/ccLRLOP3.s:301 .text.FLASH_OB_UserConfig:000000000000003c $d + /tmp/ccLRLOP3.s:308 .text.FLASH_OB_ProgramData:0000000000000000 $t + /tmp/ccLRLOP3.s:313 .text.FLASH_OB_ProgramData:0000000000000000 FLASH_OB_ProgramData + /tmp/ccLRLOP3.s:375 .text.FLASH_OB_ProgramData:0000000000000038 $d + /tmp/ccLRLOP3.s:381 .text.FLASH_OB_GetUser:0000000000000000 $t + /tmp/ccLRLOP3.s:386 .text.FLASH_OB_GetUser:0000000000000000 FLASH_OB_GetUser + /tmp/ccLRLOP3.s:429 .text.FLASH_OB_GetUser:000000000000001c $d + /tmp/ccLRLOP3.s:434 .text.HAL_FLASHEx_OBErase:0000000000000000 $t + /tmp/ccLRLOP3.s:440 .text.HAL_FLASHEx_OBErase:0000000000000000 HAL_FLASHEx_OBErase + /tmp/ccLRLOP3.s:516 .text.HAL_FLASHEx_OBErase:0000000000000048 $d + /tmp/ccLRLOP3.s:522 .text.FLASH_OB_EnableWRP:0000000000000000 $t + /tmp/ccLRLOP3.s:527 .text.FLASH_OB_EnableWRP:0000000000000000 FLASH_OB_EnableWRP + /tmp/ccLRLOP3.s:733 .text.FLASH_OB_EnableWRP:00000000000000b8 $d + /tmp/ccLRLOP3.s:740 .text.FLASH_OB_DisableWRP:0000000000000000 $t + /tmp/ccLRLOP3.s:745 .text.FLASH_OB_DisableWRP:0000000000000000 FLASH_OB_DisableWRP + /tmp/ccLRLOP3.s:947 .text.FLASH_OB_DisableWRP:00000000000000bc $d + /tmp/ccLRLOP3.s:954 .text.HAL_FLASHEx_OBProgram:0000000000000000 $t + /tmp/ccLRLOP3.s:960 .text.HAL_FLASHEx_OBProgram:0000000000000000 HAL_FLASHEx_OBProgram + /tmp/ccLRLOP3.s:1145 .text.HAL_FLASHEx_OBProgram:0000000000000098 $d + /tmp/ccLRLOP3.s:1150 .text.HAL_FLASHEx_OBGetConfig:0000000000000000 $t + /tmp/ccLRLOP3.s:1156 .text.HAL_FLASHEx_OBGetConfig:0000000000000000 HAL_FLASHEx_OBGetConfig + /tmp/ccLRLOP3.s:1198 .text.HAL_FLASHEx_OBGetUserData:0000000000000000 $t + /tmp/ccLRLOP3.s:1204 .text.HAL_FLASHEx_OBGetUserData:0000000000000000 HAL_FLASHEx_OBGetUserData + /tmp/ccLRLOP3.s:1290 .text.HAL_FLASHEx_OBGetUserData:0000000000000038 $d + /tmp/ccLRLOP3.s:1296 .text.FLASH_PageErase:0000000000000000 $t + /tmp/ccLRLOP3.s:1302 .text.FLASH_PageErase:0000000000000000 FLASH_PageErase + /tmp/ccLRLOP3.s:1331 .text.FLASH_PageErase:000000000000001c $d + /tmp/ccLRLOP3.s:1337 .text.HAL_FLASHEx_Erase:0000000000000000 $t + /tmp/ccLRLOP3.s:1343 .text.HAL_FLASHEx_Erase:0000000000000000 HAL_FLASHEx_Erase + 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    © Copyright (c) 2016 STMicroelectronics. + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * All rights reserved.
    + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This software component is licensed by ST under BSD 3-Clause license, + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * the "License"; You may not use this file except in compliance with the + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * License. You may obtain a copy of the License at: + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * opensource.org/licenses/BSD-3-Clause + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ****************************************************************************** + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** #include "stm32f3xx_hal.h" + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @addtogroup STM32F3xx_HAL_Driver + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO GPIO + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief GPIO HAL module driver + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** MISRA C:2012 deviation rule has been granted for following rules: + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * which may be out of array bounds [..,UNKNOWN] in following APIs: + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * HAL_GPIO_Init + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * HAL_GPIO_DeInit + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** #ifdef HAL_GPIO_MODULE_ENABLED + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private typedef -----------------------------------------------------------*/ + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private defines -----------------------------------------------------------*/ + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @addtogroup GPIO_Private_Constants + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** #define GPIO_NUMBER (16U) + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @} + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private macros ------------------------------------------------------------*/ + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private macros ------------------------------------------------------------*/ + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO_Private_Macros GPIO Private Macros + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @} + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + ARM GAS /tmp/ccrayVSd.s page 4 + + + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private variables ---------------------------------------------------------*/ + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Exported functions --------------------------------------------------------*/ + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions GPIO Exported Functions + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Initialization and Configuration functions + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @verbatim + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** =============================================================================== + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ##### Initialization and de-initialization functions ##### + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** =============================================================================== + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @endverbatim + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * the configuration information for the specified GPIO peripheral. + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 30 .loc 1 172 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 8 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 .loc 1 172 1 is_stmt 0 view .LVU1 + 35 0000 F0B5 push {r4, r5, r6, r7, lr} + 36 .cfi_def_cfa_offset 20 + 37 .cfi_offset 4, -20 + 38 .cfi_offset 5, -16 + 39 .cfi_offset 6, -12 + 40 .cfi_offset 7, -8 + 41 .cfi_offset 14, -4 + 42 0002 83B0 sub sp, sp, #12 + 43 .cfi_def_cfa_offset 32 + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t position = 0x00u; + 44 .loc 1 173 3 is_stmt 1 view .LVU2 + 45 .LVL1: + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t iocurrent; + 46 .loc 1 174 3 view .LVU3 + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t temp; + 47 .loc 1 175 3 view .LVU4 + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 48 .loc 1 178 3 view .LVU5 + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + 49 .loc 1 179 3 view .LVU6 + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + ARM GAS /tmp/ccrayVSd.s page 5 + + + 50 .loc 1 180 3 view .LVU7 + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the port pins */ + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** while (((GPIO_Init->Pin) >> position) != 0x00u) + 51 .loc 1 183 3 view .LVU8 + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t iocurrent; + 52 .loc 1 173 12 is_stmt 0 view .LVU9 + 53 0004 0023 movs r3, #0 + 54 .loc 1 183 9 view .LVU10 + 55 0006 62E0 b .L2 + 56 .LVL2: + 57 .L20: + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Get current io position */ + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** iocurrent = (GPIO_Init->Pin) & (1uL << position); + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (iocurrent != 0x00u) + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*--------------------- GPIO Mode Configuration ------------------------*/ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* In case of Output or Alternate function mode selection */ + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_A + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the Speed parameter */ + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + 58 .loc 1 195 9 is_stmt 1 view .LVU11 + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the IO Speed */ + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->OSPEEDR; + 59 .loc 1 197 9 view .LVU12 + 60 .loc 1 197 14 is_stmt 0 view .LVU13 + 61 0008 8568 ldr r5, [r0, #8] + 62 .LVL3: + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + 63 .loc 1 198 9 is_stmt 1 view .LVU14 + 64 .loc 1 198 55 is_stmt 0 view .LVU15 + 65 000a 5E00 lsls r6, r3, #1 + 66 .loc 1 198 42 view .LVU16 + 67 000c 0324 movs r4, #3 + 68 000e B440 lsls r4, r4, r6 + 69 .loc 1 198 14 view .LVU17 + 70 0010 25EA0405 bic r5, r5, r4 + 71 .LVL4: + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2u)); + 72 .loc 1 199 9 is_stmt 1 view .LVU18 + 73 .loc 1 199 27 is_stmt 0 view .LVU19 + 74 0014 CC68 ldr r4, [r1, #12] + 75 .loc 1 199 35 view .LVU20 + 76 0016 B440 lsls r4, r4, r6 + 77 .loc 1 199 14 view .LVU21 + 78 0018 2C43 orrs r4, r4, r5 + 79 .LVL5: + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 80 .loc 1 200 9 is_stmt 1 view .LVU22 + 81 .loc 1 200 24 is_stmt 0 view .LVU23 + 82 001a 8460 str r4, [r0, #8] + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the IO Output Type */ + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->OTYPER; + ARM GAS /tmp/ccrayVSd.s page 6 + + + 83 .loc 1 203 9 is_stmt 1 view .LVU24 + 84 .loc 1 203 14 is_stmt 0 view .LVU25 + 85 001c 4568 ldr r5, [r0, #4] + 86 .LVL6: + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 87 .loc 1 204 9 is_stmt 1 view .LVU26 + 88 .loc 1 204 14 is_stmt 0 view .LVU27 + 89 001e 25EA0C05 bic r5, r5, ip + 90 .LVL7: + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 91 .loc 1 205 9 is_stmt 1 view .LVU28 + 92 .loc 1 205 29 is_stmt 0 view .LVU29 + 93 0022 4C68 ldr r4, [r1, #4] + 94 .loc 1 205 51 view .LVU30 + 95 0024 C4F30014 ubfx r4, r4, #4, #1 + 96 .loc 1 205 71 view .LVU31 + 97 0028 9C40 lsls r4, r4, r3 + 98 .loc 1 205 14 view .LVU32 + 99 002a 2C43 orrs r4, r4, r5 + 100 .LVL8: + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 101 .loc 1 206 9 is_stmt 1 view .LVU33 + 102 .loc 1 206 23 is_stmt 0 view .LVU34 + 103 002c 4460 str r4, [r0, #4] + 104 002e 5FE0 b .L4 + 105 .LVL9: + 106 .L21: + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the Pull parameter */ + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Activate the Pull-up or Pull down resistor for the current IO */ + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->PUPDR; + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*--------------------- GPIO Mode Configuration ------------------------*/ + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* In case of Alternate function mode selection */ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the Alternate function parameters */ + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + 107 .loc 1 226 9 is_stmt 1 view .LVU35 + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + 108 .loc 1 227 9 view .LVU36 + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure Alternate function mapped with the current IO */ + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->AFR[position >> 3u]; + 109 .loc 1 230 9 view .LVU37 + 110 .loc 1 230 36 is_stmt 0 view .LVU38 + 111 0030 DD08 lsrs r5, r3, #3 + 112 .loc 1 230 14 view .LVU39 + ARM GAS /tmp/ccrayVSd.s page 7 + + + 113 0032 0835 adds r5, r5, #8 + 114 0034 50F82540 ldr r4, [r0, r5, lsl #2] + 115 .LVL10: + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(0xFu << ((position & 0x07u) * 4u)); + 116 .loc 1 231 9 is_stmt 1 view .LVU40 + 117 .loc 1 231 38 is_stmt 0 view .LVU41 + 118 0038 03F0070C and ip, r3, #7 + 119 .loc 1 231 47 view .LVU42 + 120 003c 4FEA8C0C lsl ip, ip, #2 + 121 .loc 1 231 24 view .LVU43 + 122 0040 4FF00F0E mov lr, #15 + 123 0044 0EFA0CFE lsl lr, lr, ip + 124 .loc 1 231 14 view .LVU44 + 125 0048 24EA0E0E bic lr, r4, lr + 126 .LVL11: + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + 127 .loc 1 232 9 is_stmt 1 view .LVU45 + 128 .loc 1 232 28 is_stmt 0 view .LVU46 + 129 004c 0C69 ldr r4, [r1, #16] + 130 .loc 1 232 41 view .LVU47 + 131 004e 04FA0CF4 lsl r4, r4, ip + 132 .loc 1 232 14 view .LVU48 + 133 0052 44EA0E04 orr r4, r4, lr + 134 .LVL12: + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->AFR[position >> 3u] = temp; + 135 .loc 1 233 9 is_stmt 1 view .LVU49 + 136 .loc 1 233 36 is_stmt 0 view .LVU50 + 137 0056 40F82540 str r4, [r0, r5, lsl #2] + 138 005a 60E0 b .L6 + 139 .LVL13: + 140 .L22: + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->MODER; + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER = temp; + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*--------------------- EXTI Mode Configuration ------------------------*/ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Enable SYSCFG Clock */ + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = SYSCFG->EXTICR[position >> 2u]; + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 141 .loc 1 251 18 view .LVU51 + 142 005c 0424 movs r4, #4 + 143 005e 00E0 b .L7 + 144 .L13: + 145 0060 0024 movs r4, #0 + 146 .L7: + 147 .loc 1 251 40 discriminator 20 view .LVU52 + 148 0062 04FA0EF4 lsl r4, r4, lr + ARM GAS /tmp/ccrayVSd.s page 8 + + + 149 .loc 1 251 14 discriminator 20 view .LVU53 + 150 0066 2C43 orrs r4, r4, r5 + 151 .LVL14: + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 152 .loc 1 252 9 is_stmt 1 discriminator 20 view .LVU54 + 153 .loc 1 252 40 is_stmt 0 discriminator 20 view .LVU55 + 154 0068 0CF1020C add ip, ip, #2 + 155 006c 524D ldr r5, .L23 + 156 006e 45F82C40 str r4, [r5, ip, lsl #2] + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = EXTI->IMR; + 157 .loc 1 255 9 is_stmt 1 discriminator 20 view .LVU56 + 158 .loc 1 255 14 is_stmt 0 discriminator 20 view .LVU57 + 159 0072 524C ldr r4, .L23+4 + 160 .LVL15: + 161 .loc 1 255 14 discriminator 20 view .LVU58 + 162 0074 2568 ldr r5, [r4] + 163 .LVL16: + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent); + 164 .loc 1 256 9 is_stmt 1 discriminator 20 view .LVU59 + 165 .loc 1 256 17 is_stmt 0 discriminator 20 view .LVU60 + 166 0076 D443 mvns r4, r2 + 167 .loc 1 256 14 discriminator 20 view .LVU61 + 168 0078 25EA0206 bic r6, r5, r2 + 169 .LVL17: + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 170 .loc 1 257 9 is_stmt 1 discriminator 20 view .LVU62 + 171 .loc 1 257 11 is_stmt 0 discriminator 20 view .LVU63 + 172 007c 4F68 ldr r7, [r1, #4] + 173 007e 17F4803F tst r7, #65536 + 174 0082 01D0 beq .L8 + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= iocurrent; + 175 .loc 1 259 11 is_stmt 1 view .LVU64 + 176 .loc 1 259 16 is_stmt 0 view .LVU65 + 177 0084 42EA0506 orr r6, r2, r5 + 178 .LVL18: + 179 .L8: + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->IMR = temp; + 180 .loc 1 261 9 is_stmt 1 view .LVU66 + 181 .loc 1 261 19 is_stmt 0 view .LVU67 + 182 0088 4C4D ldr r5, .L23+4 + 183 008a 2E60 str r6, [r5] + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = EXTI->EMR; + 184 .loc 1 263 9 is_stmt 1 view .LVU68 + 185 .loc 1 263 14 is_stmt 0 view .LVU69 + 186 008c 6D68 ldr r5, [r5, #4] + 187 .LVL19: + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent); + 188 .loc 1 264 9 is_stmt 1 view .LVU70 + 189 .loc 1 264 14 is_stmt 0 view .LVU71 + 190 008e 04EA0506 and r6, r4, r5 + 191 .LVL20: + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + ARM GAS /tmp/ccrayVSd.s page 9 + + + 192 .loc 1 265 9 is_stmt 1 view .LVU72 + 193 .loc 1 265 11 is_stmt 0 view .LVU73 + 194 0092 4F68 ldr r7, [r1, #4] + 195 0094 17F4003F tst r7, #131072 + 196 0098 01D0 beq .L9 + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= iocurrent; + 197 .loc 1 267 11 is_stmt 1 view .LVU74 + 198 .loc 1 267 16 is_stmt 0 view .LVU75 + 199 009a 42EA0506 orr r6, r2, r5 + 200 .LVL21: + 201 .L9: + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->EMR = temp; + 202 .loc 1 269 9 is_stmt 1 view .LVU76 + 203 .loc 1 269 19 is_stmt 0 view .LVU77 + 204 009e 474D ldr r5, .L23+4 + 205 00a0 6E60 str r6, [r5, #4] + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = EXTI->RTSR; + 206 .loc 1 272 9 is_stmt 1 view .LVU78 + 207 .loc 1 272 14 is_stmt 0 view .LVU79 + 208 00a2 AD68 ldr r5, [r5, #8] + 209 .LVL22: + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent); + 210 .loc 1 273 9 is_stmt 1 view .LVU80 + 211 .loc 1 273 14 is_stmt 0 view .LVU81 + 212 00a4 04EA0506 and r6, r4, r5 + 213 .LVL23: + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 214 .loc 1 274 9 is_stmt 1 view .LVU82 + 215 .loc 1 274 11 is_stmt 0 view .LVU83 + 216 00a8 4F68 ldr r7, [r1, #4] + 217 00aa 17F4801F tst r7, #1048576 + 218 00ae 01D0 beq .L10 + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= iocurrent; + 219 .loc 1 276 11 is_stmt 1 view .LVU84 + 220 .loc 1 276 16 is_stmt 0 view .LVU85 + 221 00b0 42EA0506 orr r6, r2, r5 + 222 .LVL24: + 223 .L10: + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->RTSR = temp; + 224 .loc 1 278 9 is_stmt 1 view .LVU86 + 225 .loc 1 278 20 is_stmt 0 view .LVU87 + 226 00b4 414D ldr r5, .L23+4 + 227 00b6 AE60 str r6, [r5, #8] + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = EXTI->FTSR; + 228 .loc 1 280 9 is_stmt 1 view .LVU88 + 229 .loc 1 280 14 is_stmt 0 view .LVU89 + 230 00b8 ED68 ldr r5, [r5, #12] + 231 .LVL25: + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent); + 232 .loc 1 281 9 is_stmt 1 view .LVU90 + ARM GAS /tmp/ccrayVSd.s page 10 + + + 233 .loc 1 281 14 is_stmt 0 view .LVU91 + 234 00ba 2C40 ands r4, r4, r5 + 235 .LVL26: + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 236 .loc 1 282 9 is_stmt 1 view .LVU92 + 237 .loc 1 282 22 is_stmt 0 view .LVU93 + 238 00bc 4E68 ldr r6, [r1, #4] + 239 .loc 1 282 11 view .LVU94 + 240 00be 16F4001F tst r6, #2097152 + 241 00c2 01D0 beq .L11 + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= iocurrent; + 242 .loc 1 284 11 is_stmt 1 view .LVU95 + 243 .loc 1 284 16 is_stmt 0 view .LVU96 + 244 00c4 42EA0504 orr r4, r2, r5 + 245 .LVL27: + 246 .L11: + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->FTSR = temp; + 247 .loc 1 286 9 is_stmt 1 view .LVU97 + 248 .loc 1 286 20 is_stmt 0 view .LVU98 + 249 00c8 3C4A ldr r2, .L23+4 + 250 .LVL28: + 251 .loc 1 286 20 view .LVU99 + 252 00ca D460 str r4, [r2, #12] + 253 .LVL29: + 254 .L3: + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** position++; + 255 .loc 1 290 5 is_stmt 1 view .LVU100 + 256 .loc 1 290 13 is_stmt 0 view .LVU101 + 257 00cc 0133 adds r3, r3, #1 + 258 .LVL30: + 259 .L2: + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 260 .loc 1 183 41 is_stmt 1 view .LVU102 + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 261 .loc 1 183 21 is_stmt 0 view .LVU103 + 262 00ce 0A68 ldr r2, [r1] + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 263 .loc 1 183 41 view .LVU104 + 264 00d0 32FA03F4 lsrs r4, r2, r3 + 265 00d4 6ED0 beq .L19 + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 266 .loc 1 186 5 is_stmt 1 view .LVU105 + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 267 .loc 1 186 41 is_stmt 0 view .LVU106 + 268 00d6 4FF0010C mov ip, #1 + 269 00da 0CFA03FC lsl ip, ip, r3 + 270 .LVL31: + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 271 .loc 1 188 5 is_stmt 1 view .LVU107 + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 272 .loc 1 188 8 is_stmt 0 view .LVU108 + 273 00de 1CEA0202 ands r2, ip, r2 + ARM GAS /tmp/ccrayVSd.s page 11 + + + 274 .LVL32: + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 275 .loc 1 188 8 view .LVU109 + 276 00e2 F3D0 beq .L3 + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 277 .loc 1 192 7 is_stmt 1 view .LVU110 + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 278 .loc 1 192 21 is_stmt 0 view .LVU111 + 279 00e4 4C68 ldr r4, [r1, #4] + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 280 .loc 1 192 28 view .LVU112 + 281 00e6 04F00304 and r4, r4, #3 + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 282 .loc 1 192 57 view .LVU113 + 283 00ea 013C subs r4, r4, #1 + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 284 .loc 1 192 9 view .LVU114 + 285 00ec 012C cmp r4, #1 + 286 00ee 8BD9 bls .L20 + 287 .L4: + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 288 .loc 1 209 7 is_stmt 1 view .LVU115 + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 289 .loc 1 209 20 is_stmt 0 view .LVU116 + 290 00f0 4C68 ldr r4, [r1, #4] + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 291 .loc 1 209 27 view .LVU117 + 292 00f2 04F00304 and r4, r4, #3 + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 293 .loc 1 209 9 view .LVU118 + 294 00f6 032C cmp r4, #3 + 295 00f8 0CD0 beq .L5 + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 296 .loc 1 212 9 is_stmt 1 view .LVU119 + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + 297 .loc 1 215 9 view .LVU120 + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + 298 .loc 1 215 14 is_stmt 0 view .LVU121 + 299 00fa C468 ldr r4, [r0, #12] + 300 .LVL33: + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 301 .loc 1 216 9 is_stmt 1 view .LVU122 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 302 .loc 1 216 50 is_stmt 0 view .LVU123 + 303 00fc 5D00 lsls r5, r3, #1 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 304 .loc 1 216 37 view .LVU124 + 305 00fe 4FF0030C mov ip, #3 + 306 0102 0CFA05FC lsl ip, ip, r5 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 307 .loc 1 216 14 view .LVU125 + 308 0106 24EA0C0C bic ip, r4, ip + 309 .LVL34: + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 310 .loc 1 217 9 is_stmt 1 view .LVU126 + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 311 .loc 1 217 28 is_stmt 0 view .LVU127 + ARM GAS /tmp/ccrayVSd.s page 12 + + + 312 010a 8C68 ldr r4, [r1, #8] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 313 .loc 1 217 36 view .LVU128 + 314 010c AC40 lsls r4, r4, r5 + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 315 .loc 1 217 14 view .LVU129 + 316 010e 44EA0C04 orr r4, r4, ip + 317 .LVL35: + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 318 .loc 1 218 9 is_stmt 1 view .LVU130 + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 319 .loc 1 218 22 is_stmt 0 view .LVU131 + 320 0112 C460 str r4, [r0, #12] + 321 .LVL36: + 322 .L5: + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 323 .loc 1 223 7 is_stmt 1 view .LVU132 + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 324 .loc 1 223 20 is_stmt 0 view .LVU133 + 325 0114 4C68 ldr r4, [r1, #4] + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 326 .loc 1 223 27 view .LVU134 + 327 0116 04F00304 and r4, r4, #3 + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 328 .loc 1 223 9 view .LVU135 + 329 011a 022C cmp r4, #2 + 330 011c 88D0 beq .L21 + 331 .L6: + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); + 332 .loc 1 237 7 is_stmt 1 view .LVU136 + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); + 333 .loc 1 237 12 is_stmt 0 view .LVU137 + 334 011e 0468 ldr r4, [r0] + 335 .LVL37: + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 336 .loc 1 238 7 is_stmt 1 view .LVU138 + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 337 .loc 1 238 48 is_stmt 0 view .LVU139 + 338 0120 4FEA430E lsl lr, r3, #1 + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 339 .loc 1 238 35 view .LVU140 + 340 0124 4FF0030C mov ip, #3 + 341 0128 0CFA0EFC lsl ip, ip, lr + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 342 .loc 1 238 12 view .LVU141 + 343 012c 24EA0C0C bic ip, r4, ip + 344 .LVL38: + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER = temp; + 345 .loc 1 239 7 is_stmt 1 view .LVU142 + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER = temp; + 346 .loc 1 239 26 is_stmt 0 view .LVU143 + 347 0130 4C68 ldr r4, [r1, #4] + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER = temp; + 348 .loc 1 239 33 view .LVU144 + 349 0132 04F00304 and r4, r4, #3 + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER = temp; + 350 .loc 1 239 46 view .LVU145 + ARM GAS /tmp/ccrayVSd.s page 13 + + + 351 0136 04FA0EF4 lsl r4, r4, lr + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER = temp; + 352 .loc 1 239 12 view .LVU146 + 353 013a 44EA0C04 orr r4, r4, ip + 354 .LVL39: + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 355 .loc 1 240 7 is_stmt 1 view .LVU147 + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 356 .loc 1 240 20 is_stmt 0 view .LVU148 + 357 013e 0460 str r4, [r0] + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 358 .loc 1 244 7 is_stmt 1 view .LVU149 + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 359 .loc 1 244 20 is_stmt 0 view .LVU150 + 360 0140 4C68 ldr r4, [r1, #4] + 361 .LVL40: + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 362 .loc 1 244 9 view .LVU151 + 363 0142 14F4403F tst r4, #196608 + 364 0146 C1D0 beq .L3 + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 365 .loc 1 247 9 is_stmt 1 view .LVU152 + 366 .LBB2: + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 367 .loc 1 247 9 view .LVU153 + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 368 .loc 1 247 9 view .LVU154 + 369 0148 1D4C ldr r4, .L23+8 + 370 014a A569 ldr r5, [r4, #24] + 371 014c 45F00105 orr r5, r5, #1 + 372 0150 A561 str r5, [r4, #24] + 373 .LVL41: + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 374 .loc 1 247 9 view .LVU155 + 375 0152 A469 ldr r4, [r4, #24] + 376 0154 04F00104 and r4, r4, #1 + 377 0158 0194 str r4, [sp, #4] + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 378 .loc 1 247 9 view .LVU156 + 379 015a 019C ldr r4, [sp, #4] + 380 .LBE2: + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 381 .loc 1 247 9 view .LVU157 + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 382 .loc 1 249 9 view .LVU158 + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 383 .loc 1 249 40 is_stmt 0 view .LVU159 + 384 015c 4FEA930C lsr ip, r3, #2 + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 385 .loc 1 249 14 view .LVU160 + 386 0160 0CF10205 add r5, ip, #2 + 387 0164 144C ldr r4, .L23 + 388 0166 54F82550 ldr r5, [r4, r5, lsl #2] + 389 .LVL42: + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 390 .loc 1 250 9 is_stmt 1 view .LVU161 + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + ARM GAS /tmp/ccrayVSd.s page 14 + + + 391 .loc 1 250 45 is_stmt 0 view .LVU162 + 392 016a 03F0030E and lr, r3, #3 + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 393 .loc 1 250 33 view .LVU163 + 394 016e 4FEA8E0E lsl lr, lr, #2 + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 395 .loc 1 250 26 view .LVU164 + 396 0172 0F24 movs r4, #15 + 397 0174 04FA0EF4 lsl r4, r4, lr + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 398 .loc 1 250 14 view .LVU165 + 399 0178 25EA0405 bic r5, r5, r4 + 400 .LVL43: + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 401 .loc 1 251 9 is_stmt 1 view .LVU166 + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 402 .loc 1 251 18 is_stmt 0 view .LVU167 + 403 017c B0F1904F cmp r0, #1207959552 + 404 0180 3FF46EAF beq .L13 + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 405 .loc 1 251 18 discriminator 1 view .LVU168 + 406 0184 0F4C ldr r4, .L23+12 + 407 0186 A042 cmp r0, r4 + 408 0188 0ED0 beq .L14 + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 409 .loc 1 251 18 discriminator 3 view .LVU169 + 410 018a 04F58064 add r4, r4, #1024 + 411 018e A042 cmp r0, r4 + 412 0190 0CD0 beq .L15 + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 413 .loc 1 251 18 discriminator 5 view .LVU170 + 414 0192 04F58064 add r4, r4, #1024 + 415 0196 A042 cmp r0, r4 + 416 0198 0AD0 beq .L16 + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 417 .loc 1 251 18 discriminator 7 view .LVU171 + 418 019a 04F58064 add r4, r4, #1024 + 419 019e A042 cmp r0, r4 + 420 01a0 3FF45CAF beq .L22 + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 421 .loc 1 251 18 view .LVU172 + 422 01a4 0524 movs r4, #5 + 423 01a6 5CE7 b .L7 + 424 .L14: + 425 01a8 0124 movs r4, #1 + 426 01aa 5AE7 b .L7 + 427 .L15: + 428 01ac 0224 movs r4, #2 + 429 01ae 58E7 b .L7 + 430 .L16: + 431 01b0 0324 movs r4, #3 + 432 01b2 56E7 b .L7 + 433 .LVL44: + 434 .L19: + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 435 .loc 1 292 1 view .LVU173 + ARM GAS /tmp/ccrayVSd.s page 15 + + + 436 01b4 03B0 add sp, sp, #12 + 437 .cfi_def_cfa_offset 20 + 438 @ sp needed + 439 01b6 F0BD pop {r4, r5, r6, r7, pc} + 440 .L24: + 441 .align 2 + 442 .L23: + 443 01b8 00000140 .word 1073807360 + 444 01bc 00040140 .word 1073808384 + 445 01c0 00100240 .word 1073876992 + 446 01c4 00040048 .word 1207960576 + 447 .cfi_endproc + 448 .LFE130: + 450 .section .text.HAL_GPIO_DeInit,"ax",%progbits + 451 .align 1 + 452 .global HAL_GPIO_DeInit + 453 .syntax unified + 454 .thumb + 455 .thumb_func + 457 HAL_GPIO_DeInit: + 458 .LVL45: + 459 .LFB131: + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief De-initialize the GPIOx peripheral registers to their default reset values. + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32 + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be written. + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 460 .loc 1 302 1 is_stmt 1 view -0 + 461 .cfi_startproc + 462 @ args = 0, pretend = 0, frame = 0 + 463 @ frame_needed = 0, uses_anonymous_args = 0 + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t position = 0x00u; + 464 .loc 1 303 3 view .LVU175 + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t iocurrent; + 465 .loc 1 304 3 view .LVU176 + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t tmp; + 466 .loc 1 305 3 view .LVU177 + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 467 .loc 1 308 3 view .LVU178 + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 468 .loc 1 309 3 view .LVU179 + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the port pins */ + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** while ((GPIO_Pin >> position) != 0x00u) + 469 .loc 1 312 3 view .LVU180 + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t iocurrent; + 470 .loc 1 303 12 is_stmt 0 view .LVU181 + 471 0000 0023 movs r3, #0 + 472 .LVL46: + 473 .loc 1 312 33 is_stmt 1 view .LVU182 + ARM GAS /tmp/ccrayVSd.s page 16 + + + 474 0002 31FA03F2 lsrs r2, r1, r3 + 475 0006 7AD0 beq .L39 + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t position = 0x00u; + 476 .loc 1 302 1 is_stmt 0 view .LVU183 + 477 0008 F0B5 push {r4, r5, r6, r7, lr} + 478 .cfi_def_cfa_offset 20 + 479 .cfi_offset 4, -20 + 480 .cfi_offset 5, -16 + 481 .cfi_offset 6, -12 + 482 .cfi_offset 7, -8 + 483 .cfi_offset 14, -4 + 484 000a 2EE0 b .L30 + 485 .LVL47: + 486 .L42: + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Get current io position */ + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** iocurrent = (GPIO_Pin) & (1uL << position); + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (iocurrent != 0x00u) + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*------------------------- EXTI Mode Configuration --------------------*/ + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear the External Interrupt or Event for the current IO */ + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp = SYSCFG->EXTICR[position >> 2u]; + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp &= (0x0FuL << (4u * (position & 0x03u))); + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + 487 .loc 1 324 19 view .LVU184 + 488 000c 0425 movs r5, #4 + 489 000e 00E0 b .L28 + 490 .L31: + 491 0010 0025 movs r5, #0 + 492 .L28: + 493 .loc 1 324 41 discriminator 20 view .LVU185 + 494 0012 05FA0CF5 lsl r5, r5, ip + 495 .loc 1 324 10 discriminator 20 view .LVU186 + 496 0016 A542 cmp r5, r4 + 497 0018 55D0 beq .L40 + 498 .LVL48: + 499 .L29: + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->IMR &= ~((uint32_t)iocurrent); + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->RTSR &= ~((uint32_t)iocurrent); + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->FTSR &= ~((uint32_t)iocurrent); + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp = 0x0FuL << (4u * (position & 0x03u)); + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] &= ~tmp; + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*------------------------- GPIO Mode Configuration --------------------*/ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure IO Direction in Input Floating Mode */ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u)); + 500 .loc 1 341 7 is_stmt 1 view .LVU187 + ARM GAS /tmp/ccrayVSd.s page 17 + + + 501 .loc 1 341 12 is_stmt 0 view .LVU188 + 502 001a 0468 ldr r4, [r0] + 503 .loc 1 341 56 view .LVU189 + 504 001c 5D00 lsls r5, r3, #1 + 505 .loc 1 341 43 view .LVU190 + 506 001e 4FF0030C mov ip, #3 + 507 0022 0CFA05FC lsl ip, ip, r5 + 508 .loc 1 341 20 view .LVU191 + 509 0026 24EA0C04 bic r4, r4, ip + 510 002a 0460 str r4, [r0] + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the default Alternate Function in current IO */ + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ; + 511 .loc 1 344 7 is_stmt 1 view .LVU192 + 512 .loc 1 344 17 is_stmt 0 view .LVU193 + 513 002c 4FEAD30E lsr lr, r3, #3 + 514 0030 0EF1080E add lr, lr, #8 + 515 0034 50F82E40 ldr r4, [r0, lr, lsl #2] + 516 .loc 1 344 48 view .LVU194 + 517 0038 03F00706 and r6, r3, #7 + 518 .loc 1 344 77 view .LVU195 + 519 003c B600 lsls r6, r6, #2 + 520 .loc 1 344 44 view .LVU196 + 521 003e 0F25 movs r5, #15 + 522 0040 B540 lsls r5, r5, r6 + 523 .loc 1 344 34 view .LVU197 + 524 0042 24EA0504 bic r4, r4, r5 + 525 0046 40F82E40 str r4, [r0, lr, lsl #2] + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + 526 .loc 1 347 7 is_stmt 1 view .LVU198 + 527 .loc 1 347 12 is_stmt 0 view .LVU199 + 528 004a C468 ldr r4, [r0, #12] + 529 .loc 1 347 20 view .LVU200 + 530 004c 24EA0C04 bic r4, r4, ip + 531 0050 C460 str r4, [r0, #12] + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the default value IO Output Type */ + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + 532 .loc 1 350 7 is_stmt 1 view .LVU201 + 533 .loc 1 350 12 is_stmt 0 view .LVU202 + 534 0052 4468 ldr r4, [r0, #4] + 535 .loc 1 350 22 view .LVU203 + 536 0054 24EA0202 bic r2, r4, r2 + 537 .LVL49: + 538 .loc 1 350 22 view .LVU204 + 539 0058 4260 str r2, [r0, #4] + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the default value for IO Speed */ + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + 540 .loc 1 353 7 is_stmt 1 view .LVU205 + 541 .loc 1 353 12 is_stmt 0 view .LVU206 + 542 005a 8268 ldr r2, [r0, #8] + 543 .loc 1 353 22 view .LVU207 + 544 005c 22EA0C02 bic r2, r2, ip + 545 0060 8260 str r2, [r0, #8] + ARM GAS /tmp/ccrayVSd.s page 18 + + + 546 .L27: + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** position++; + 547 .loc 1 356 5 is_stmt 1 view .LVU208 + 548 .loc 1 356 13 is_stmt 0 view .LVU209 + 549 0062 0133 adds r3, r3, #1 + 550 .LVL50: + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 551 .loc 1 312 33 is_stmt 1 view .LVU210 + 552 0064 31FA03F2 lsrs r2, r1, r3 + 553 0068 48D0 beq .L41 + 554 .LVL51: + 555 .L30: + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 556 .loc 1 315 5 view .LVU211 + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 557 .loc 1 315 35 is_stmt 0 view .LVU212 + 558 006a 0122 movs r2, #1 + 559 006c 9A40 lsls r2, r2, r3 + 560 .LVL52: + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 561 .loc 1 317 5 is_stmt 1 view .LVU213 + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 562 .loc 1 317 8 is_stmt 0 view .LVU214 + 563 006e 12EA0107 ands r7, r2, r1 + 564 .LVL53: + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 565 .loc 1 317 8 view .LVU215 + 566 0072 F6D0 beq .L27 + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp &= (0x0FuL << (4u * (position & 0x03u))); + 567 .loc 1 322 7 is_stmt 1 view .LVU216 + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp &= (0x0FuL << (4u * (position & 0x03u))); + 568 .loc 1 322 37 is_stmt 0 view .LVU217 + 569 0074 4FEA930E lsr lr, r3, #2 + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp &= (0x0FuL << (4u * (position & 0x03u))); + 570 .loc 1 322 11 view .LVU218 + 571 0078 0EF10205 add r5, lr, #2 + 572 007c 204C ldr r4, .L43 + 573 007e 54F82540 ldr r4, [r4, r5, lsl #2] + 574 .LVL54: + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + 575 .loc 1 323 7 is_stmt 1 view .LVU219 + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + 576 .loc 1 323 41 is_stmt 0 view .LVU220 + 577 0082 03F0030C and ip, r3, #3 + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + 578 .loc 1 323 29 view .LVU221 + 579 0086 4FEA8C0C lsl ip, ip, #2 + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + 580 .loc 1 323 22 view .LVU222 + 581 008a 0F25 movs r5, #15 + 582 008c 05FA0CF6 lsl r6, r5, ip + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + 583 .loc 1 323 11 view .LVU223 + 584 0090 3440 ands r4, r4, r6 + 585 .LVL55: + ARM GAS /tmp/ccrayVSd.s page 19 + + + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 586 .loc 1 324 7 is_stmt 1 view .LVU224 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 587 .loc 1 324 19 is_stmt 0 view .LVU225 + 588 0092 B0F1904F cmp r0, #1207959552 + 589 0096 BBD0 beq .L31 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 590 .loc 1 324 19 discriminator 1 view .LVU226 + 591 0098 1A4D ldr r5, .L43+4 + 592 009a A842 cmp r0, r5 + 593 009c 0DD0 beq .L32 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 594 .loc 1 324 19 discriminator 3 view .LVU227 + 595 009e 05F58065 add r5, r5, #1024 + 596 00a2 A842 cmp r0, r5 + 597 00a4 0BD0 beq .L33 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 598 .loc 1 324 19 discriminator 5 view .LVU228 + 599 00a6 05F58065 add r5, r5, #1024 + 600 00aa A842 cmp r0, r5 + 601 00ac 09D0 beq .L34 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 602 .loc 1 324 19 discriminator 7 view .LVU229 + 603 00ae 05F58065 add r5, r5, #1024 + 604 00b2 A842 cmp r0, r5 + 605 00b4 AAD0 beq .L42 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 606 .loc 1 324 19 view .LVU230 + 607 00b6 0525 movs r5, #5 + 608 00b8 ABE7 b .L28 + 609 .L32: + 610 00ba 0125 movs r5, #1 + 611 00bc A9E7 b .L28 + 612 .L33: + 613 00be 0225 movs r5, #2 + 614 00c0 A7E7 b .L28 + 615 .L34: + 616 00c2 0325 movs r5, #3 + 617 00c4 A5E7 b .L28 + 618 .L40: + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 619 .loc 1 327 9 is_stmt 1 view .LVU231 + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 620 .loc 1 327 13 is_stmt 0 view .LVU232 + 621 00c6 104C ldr r4, .L43+8 + 622 .LVL56: + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 623 .loc 1 327 13 view .LVU233 + 624 00c8 2568 ldr r5, [r4] + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 625 .loc 1 327 19 view .LVU234 + 626 00ca 25EA0705 bic r5, r5, r7 + 627 00ce 2560 str r5, [r4] + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 628 .loc 1 328 9 is_stmt 1 view .LVU235 + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 629 .loc 1 328 13 is_stmt 0 view .LVU236 + ARM GAS /tmp/ccrayVSd.s page 20 + + + 630 00d0 6568 ldr r5, [r4, #4] + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 631 .loc 1 328 19 view .LVU237 + 632 00d2 25EA0705 bic r5, r5, r7 + 633 00d6 6560 str r5, [r4, #4] + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->FTSR &= ~((uint32_t)iocurrent); + 634 .loc 1 331 9 is_stmt 1 view .LVU238 + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->FTSR &= ~((uint32_t)iocurrent); + 635 .loc 1 331 13 is_stmt 0 view .LVU239 + 636 00d8 A568 ldr r5, [r4, #8] + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->FTSR &= ~((uint32_t)iocurrent); + 637 .loc 1 331 20 view .LVU240 + 638 00da 25EA0705 bic r5, r5, r7 + 639 00de A560 str r5, [r4, #8] + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 640 .loc 1 332 9 is_stmt 1 view .LVU241 + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 641 .loc 1 332 13 is_stmt 0 view .LVU242 + 642 00e0 E568 ldr r5, [r4, #12] + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 643 .loc 1 332 20 view .LVU243 + 644 00e2 25EA0705 bic r5, r5, r7 + 645 00e6 E560 str r5, [r4, #12] + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] &= ~tmp; + 646 .loc 1 335 9 is_stmt 1 view .LVU244 + 647 .LVL57: + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 648 .loc 1 336 9 view .LVU245 + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 649 .loc 1 336 23 is_stmt 0 view .LVU246 + 650 00e8 054F ldr r7, .L43 + 651 .LVL58: + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 652 .loc 1 336 23 view .LVU247 + 653 00ea 0EF10204 add r4, lr, #2 + 654 00ee 57F82450 ldr r5, [r7, r4, lsl #2] + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 655 .loc 1 336 40 view .LVU248 + 656 00f2 25EA0605 bic r5, r5, r6 + 657 00f6 47F82450 str r5, [r7, r4, lsl #2] + 658 00fa 8EE7 b .L29 + 659 .LVL59: + 660 .L41: + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 661 .loc 1 358 1 view .LVU249 + 662 00fc F0BD pop {r4, r5, r6, r7, pc} + 663 .LVL60: + 664 .L39: + 665 .cfi_def_cfa_offset 0 + 666 .cfi_restore 4 + 667 .cfi_restore 5 + 668 .cfi_restore 6 + 669 .cfi_restore 7 + 670 .cfi_restore 14 + 671 .loc 1 358 1 view .LVU250 + 672 00fe 7047 bx lr + ARM GAS /tmp/ccrayVSd.s page 21 + + + 673 .L44: + 674 .align 2 + 675 .L43: + 676 0100 00000140 .word 1073807360 + 677 0104 00040048 .word 1207960576 + 678 0108 00040140 .word 1073808384 + 679 .cfi_endproc + 680 .LFE131: + 682 .section .text.HAL_GPIO_ReadPin,"ax",%progbits + 683 .align 1 + 684 .global HAL_GPIO_ReadPin + 685 .syntax unified + 686 .thumb + 687 .thumb_func + 689 HAL_GPIO_ReadPin: + 690 .LVL61: + 691 .LFB132: + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @} + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @verbatim + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** =============================================================================== + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ##### IO operation functions ##### + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** =============================================================================== + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @endverbatim + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Read the specified input port pin. + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to read. + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be GPIO_PIN_x where x can be (0..15). + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval The input port pin value. + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 692 .loc 1 384 1 is_stmt 1 view -0 + 693 .cfi_startproc + 694 @ args = 0, pretend = 0, frame = 0 + 695 @ frame_needed = 0, uses_anonymous_args = 0 + 696 @ link register save eliminated. + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIO_PinState bitstatus; + 697 .loc 1 385 3 view .LVU252 + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 698 .loc 1 388 3 view .LVU253 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + 699 .loc 1 390 3 view .LVU254 + ARM GAS /tmp/ccrayVSd.s page 22 + + + 700 .loc 1 390 12 is_stmt 0 view .LVU255 + 701 0000 0369 ldr r3, [r0, #16] + 702 .loc 1 390 5 view .LVU256 + 703 0002 1942 tst r1, r3 + 704 0004 01D0 beq .L47 + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** bitstatus = GPIO_PIN_SET; + 705 .loc 1 392 15 view .LVU257 + 706 0006 0120 movs r0, #1 + 707 .LVL62: + 708 .loc 1 392 15 view .LVU258 + 709 0008 7047 bx lr + 710 .LVL63: + 711 .L47: + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** else + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** bitstatus = GPIO_PIN_RESET; + 712 .loc 1 396 15 view .LVU259 + 713 000a 0020 movs r0, #0 + 714 .LVL64: + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** return bitstatus; + 715 .loc 1 398 3 is_stmt 1 view .LVU260 + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 716 .loc 1 399 1 is_stmt 0 view .LVU261 + 717 000c 7047 bx lr + 718 .cfi_endproc + 719 .LFE132: + 721 .section .text.HAL_GPIO_WritePin,"ax",%progbits + 722 .align 1 + 723 .global HAL_GPIO_WritePin + 724 .syntax unified + 725 .thumb + 726 .thumb_func + 728 HAL_GPIO_WritePin: + 729 .LVL65: + 730 .LFB133: + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Set or clear the selected data port bit. + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * accesses. In this way, there is no risk of an IRQ occurring between + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * the read and the modify access. + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be written. + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param PinState specifies the value to be written to the selected bit. + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be one of the GPIO_PinState enum values: + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @arg GPIO_PIN_RESET: to clear the port pin + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @arg GPIO_PIN_SET: to set the port pin + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + ARM GAS /tmp/ccrayVSd.s page 23 + + + 731 .loc 1 418 1 is_stmt 1 view -0 + 732 .cfi_startproc + 733 @ args = 0, pretend = 0, frame = 0 + 734 @ frame_needed = 0, uses_anonymous_args = 0 + 735 @ link register save eliminated. + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 736 .loc 1 420 3 view .LVU263 + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_ACTION(PinState)); + 737 .loc 1 421 3 view .LVU264 + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if(PinState != GPIO_PIN_RESET) + 738 .loc 1 423 3 view .LVU265 + 739 .loc 1 423 5 is_stmt 0 view .LVU266 + 740 0000 0AB1 cbz r2, .L49 + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->BSRR = (uint32_t)GPIO_Pin; + 741 .loc 1 425 5 is_stmt 1 view .LVU267 + 742 .loc 1 425 17 is_stmt 0 view .LVU268 + 743 0002 8161 str r1, [r0, #24] + 744 0004 7047 bx lr + 745 .L49: + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** else + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->BRR = (uint32_t)GPIO_Pin; + 746 .loc 1 429 5 is_stmt 1 view .LVU269 + 747 .loc 1 429 16 is_stmt 0 view .LVU270 + 748 0006 8162 str r1, [r0, #40] + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 749 .loc 1 431 1 view .LVU271 + 750 0008 7047 bx lr + 751 .cfi_endproc + 752 .LFE133: + 754 .section .text.HAL_GPIO_TogglePin,"ax",%progbits + 755 .align 1 + 756 .global HAL_GPIO_TogglePin + 757 .syntax unified + 758 .thumb + 759 .thumb_func + 761 HAL_GPIO_TogglePin: + 762 .LVL66: + 763 .LFB134: + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Toggle the specified GPIO pin. + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the pin to be toggled. + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 764 .loc 1 440 1 is_stmt 1 view -0 + 765 .cfi_startproc + 766 @ args = 0, pretend = 0, frame = 0 + 767 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccrayVSd.s page 24 + + + 768 @ link register save eliminated. + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t odr; + 769 .loc 1 441 3 view .LVU273 + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 770 .loc 1 444 3 view .LVU274 + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* get current Ouput Data Register value */ + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** odr = GPIOx->ODR; + 771 .loc 1 447 3 view .LVU275 + 772 .loc 1 447 7 is_stmt 0 view .LVU276 + 773 0000 4369 ldr r3, [r0, #20] + 774 .LVL67: + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Set selected pins that were at low level, and reset ones that were high */ + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); + 775 .loc 1 450 3 is_stmt 1 view .LVU277 + 776 .loc 1 450 23 is_stmt 0 view .LVU278 + 777 0002 01EA0302 and r2, r1, r3 + 778 .loc 1 450 59 view .LVU279 + 779 0006 21EA0301 bic r1, r1, r3 + 780 .LVL68: + 781 .loc 1 450 51 view .LVU280 + 782 000a 41EA0241 orr r1, r1, r2, lsl #16 + 783 .loc 1 450 15 view .LVU281 + 784 000e 8161 str r1, [r0, #24] + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 785 .loc 1 451 1 view .LVU282 + 786 0010 7047 bx lr + 787 .cfi_endproc + 788 .LFE134: + 790 .section .text.HAL_GPIO_LockPin,"ax",%progbits + 791 .align 1 + 792 .global HAL_GPIO_LockPin + 793 .syntax unified + 794 .thumb + 795 .thumb_func + 797 HAL_GPIO_LockPin: + 798 .LVL69: + 799 .LFB135: + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Lock GPIO Pins configuration registers. + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @note The configuration of the locked GPIO pins can no longer be modified + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * until the next reset. + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bits to be locked. + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 800 .loc 1 465 1 is_stmt 1 view -0 + 801 .cfi_startproc + ARM GAS /tmp/ccrayVSd.s page 25 + + + 802 @ args = 0, pretend = 0, frame = 8 + 803 @ frame_needed = 0, uses_anonymous_args = 0 + 804 @ link register save eliminated. + 805 .loc 1 465 1 is_stmt 0 view .LVU284 + 806 0000 82B0 sub sp, sp, #8 + 807 .cfi_def_cfa_offset 8 + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** __IO uint32_t tmp = GPIO_LCKR_LCKK; + 808 .loc 1 466 3 is_stmt 1 view .LVU285 + 809 .loc 1 466 17 is_stmt 0 view .LVU286 + 810 0002 4FF48033 mov r3, #65536 + 811 0006 0193 str r3, [sp, #4] + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + 812 .loc 1 469 3 is_stmt 1 view .LVU287 + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 813 .loc 1 470 3 view .LVU288 + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Apply lock key write sequence */ + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp |= GPIO_Pin; + 814 .loc 1 473 3 view .LVU289 + 815 .loc 1 473 7 is_stmt 0 view .LVU290 + 816 0008 019B ldr r3, [sp, #4] + 817 000a 0B43 orrs r3, r3, r1 + 818 000c 0193 str r3, [sp, #4] + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 819 .loc 1 475 3 is_stmt 1 view .LVU291 + 820 .loc 1 475 15 is_stmt 0 view .LVU292 + 821 000e 019B ldr r3, [sp, #4] + 822 0010 C361 str r3, [r0, #28] + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */ + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->LCKR = GPIO_Pin; + 823 .loc 1 477 3 is_stmt 1 view .LVU293 + 824 .loc 1 477 15 is_stmt 0 view .LVU294 + 825 0012 C161 str r1, [r0, #28] + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 826 .loc 1 479 3 is_stmt 1 view .LVU295 + 827 .loc 1 479 15 is_stmt 0 view .LVU296 + 828 0014 019B ldr r3, [sp, #4] + 829 0016 C361 str r3, [r0, #28] + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Read LCKK register. This read is mandatory to complete key lock sequence */ + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp = GPIOx->LCKR; + 830 .loc 1 481 3 is_stmt 1 view .LVU297 + 831 .loc 1 481 14 is_stmt 0 view .LVU298 + 832 0018 C369 ldr r3, [r0, #28] + 833 .loc 1 481 7 view .LVU299 + 834 001a 0193 str r3, [sp, #4] + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* read again in order to confirm lock is active */ + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + 835 .loc 1 484 2 is_stmt 1 view .LVU300 + 836 .loc 1 484 11 is_stmt 0 view .LVU301 + 837 001c C369 ldr r3, [r0, #28] + 838 .loc 1 484 4 view .LVU302 + 839 001e 13F4803F tst r3, #65536 + ARM GAS /tmp/ccrayVSd.s page 26 + + + 840 0022 02D0 beq .L54 + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** return HAL_OK; + 841 .loc 1 486 12 view .LVU303 + 842 0024 0020 movs r0, #0 + 843 .LVL70: + 844 .L53: + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** else + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** return HAL_ERROR; + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 845 .loc 1 492 1 view .LVU304 + 846 0026 02B0 add sp, sp, #8 + 847 .cfi_remember_state + 848 .cfi_def_cfa_offset 0 + 849 @ sp needed + 850 0028 7047 bx lr + 851 .LVL71: + 852 .L54: + 853 .cfi_restore_state + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 854 .loc 1 490 12 view .LVU305 + 855 002a 0120 movs r0, #1 + 856 .LVL72: + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 857 .loc 1 490 12 view .LVU306 + 858 002c FBE7 b .L53 + 859 .cfi_endproc + 860 .LFE135: + 862 .section .text.HAL_GPIO_EXTI_Callback,"ax",%progbits + 863 .align 1 + 864 .weak HAL_GPIO_EXTI_Callback + 865 .syntax unified + 866 .thumb + 867 .thumb_func + 869 HAL_GPIO_EXTI_Callback: + 870 .LVL73: + 871 .LFB137: + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Handle EXTI interrupt request. + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + ARM GAS /tmp/ccrayVSd.s page 27 + + + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief EXTI line detection callback. + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 872 .loc 1 515 1 is_stmt 1 view -0 + 873 .cfi_startproc + 874 @ args = 0, pretend = 0, frame = 0 + 875 @ frame_needed = 0, uses_anonymous_args = 0 + 876 @ link register save eliminated. + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Prevent unused argument(s) compilation warning */ + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** UNUSED(GPIO_Pin); + 877 .loc 1 517 3 view .LVU308 + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* NOTE: This function should not be modified, when the callback is needed, + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** the HAL_GPIO_EXTI_Callback could be implemented in the user file + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 878 .loc 1 522 1 is_stmt 0 view .LVU309 + 879 0000 7047 bx lr + 880 .cfi_endproc + 881 .LFE137: + 883 .section .text.HAL_GPIO_EXTI_IRQHandler,"ax",%progbits + 884 .align 1 + 885 .global HAL_GPIO_EXTI_IRQHandler + 886 .syntax unified + 887 .thumb + 888 .thumb_func + 890 HAL_GPIO_EXTI_IRQHandler: + 891 .LVL74: + 892 .LFB136: + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 893 .loc 1 500 1 is_stmt 1 view -0 + 894 .cfi_startproc + 895 @ args = 0, pretend = 0, frame = 0 + 896 @ frame_needed = 0, uses_anonymous_args = 0 + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 897 .loc 1 500 1 is_stmt 0 view .LVU311 + 898 0000 08B5 push {r3, lr} + 899 .cfi_def_cfa_offset 8 + 900 .cfi_offset 3, -8 + 901 .cfi_offset 14, -4 + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 902 .loc 1 502 3 is_stmt 1 view .LVU312 + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 903 .loc 1 502 6 is_stmt 0 view .LVU313 + 904 0002 054B ldr r3, .L61 + 905 0004 5B69 ldr r3, [r3, #20] + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 906 .loc 1 502 5 view .LVU314 + 907 0006 0342 tst r3, r0 + 908 0008 00D1 bne .L60 + 909 .LVL75: + 910 .L57: + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 911 .loc 1 507 1 view .LVU315 + ARM GAS /tmp/ccrayVSd.s page 28 + + + 912 000a 08BD pop {r3, pc} + 913 .LVL76: + 914 .L60: + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 915 .loc 1 504 5 is_stmt 1 view .LVU316 + 916 000c 024B ldr r3, .L61 + 917 000e 5861 str r0, [r3, #20] + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 918 .loc 1 505 5 view .LVU317 + 919 0010 FFF7FEFF bl HAL_GPIO_EXTI_Callback + 920 .LVL77: + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 921 .loc 1 507 1 is_stmt 0 view .LVU318 + 922 0014 F9E7 b .L57 + 923 .L62: + 924 0016 00BF .align 2 + 925 .L61: + 926 0018 00040140 .word 1073808384 + 927 .cfi_endproc + 928 .LFE136: + 930 .text + 931 .Letext0: + 932 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 933 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 934 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 935 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 936 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + ARM GAS /tmp/ccrayVSd.s page 29 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_gpio.c + /tmp/ccrayVSd.s:21 .text.HAL_GPIO_Init:0000000000000000 $t + /tmp/ccrayVSd.s:27 .text.HAL_GPIO_Init:0000000000000000 HAL_GPIO_Init + /tmp/ccrayVSd.s:443 .text.HAL_GPIO_Init:00000000000001b8 $d + /tmp/ccrayVSd.s:451 .text.HAL_GPIO_DeInit:0000000000000000 $t + /tmp/ccrayVSd.s:457 .text.HAL_GPIO_DeInit:0000000000000000 HAL_GPIO_DeInit + /tmp/ccrayVSd.s:676 .text.HAL_GPIO_DeInit:0000000000000100 $d + /tmp/ccrayVSd.s:683 .text.HAL_GPIO_ReadPin:0000000000000000 $t + /tmp/ccrayVSd.s:689 .text.HAL_GPIO_ReadPin:0000000000000000 HAL_GPIO_ReadPin + /tmp/ccrayVSd.s:722 .text.HAL_GPIO_WritePin:0000000000000000 $t + /tmp/ccrayVSd.s:728 .text.HAL_GPIO_WritePin:0000000000000000 HAL_GPIO_WritePin + /tmp/ccrayVSd.s:755 .text.HAL_GPIO_TogglePin:0000000000000000 $t + /tmp/ccrayVSd.s:761 .text.HAL_GPIO_TogglePin:0000000000000000 HAL_GPIO_TogglePin + /tmp/ccrayVSd.s:791 .text.HAL_GPIO_LockPin:0000000000000000 $t + /tmp/ccrayVSd.s:797 .text.HAL_GPIO_LockPin:0000000000000000 HAL_GPIO_LockPin + /tmp/ccrayVSd.s:863 .text.HAL_GPIO_EXTI_Callback:0000000000000000 $t + /tmp/ccrayVSd.s:869 .text.HAL_GPIO_EXTI_Callback:0000000000000000 HAL_GPIO_EXTI_Callback + /tmp/ccrayVSd.s:884 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 $t + /tmp/ccrayVSd.s:890 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 HAL_GPIO_EXTI_IRQHandler + /tmp/ccrayVSd.s:926 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000018 $d + +NO UNDEFINED SYMBOLS diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_gpio.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_gpio.o new file mode 100644 index 0000000000000000000000000000000000000000..818ff3dee0987723a80cae770b5574c98ec3434e GIT binary patch literal 10964 zcmd5?eRNyJm7jUev#;*lV@2My!`m$4quUTRd{- zVYY7c_`c}%O!q$5R=Z$`Uqqj4tMA-9(jBc`aEadNu~W>mACj(-;p4w?IxiVGQ`@F5 z7P$Hs?soMrmbl$#U7vUt+-_IQIO{sywcs||pfPgX@Ur8~Yn*kTuJ3f6)Lg;7?lbjm z!QR^FYn`Yt_7EIY{b&h>hGF2qWuervgc0ga$-Te#qxJzV4D9?va-rL`LI{v+q z-bXv!^Tzvg;YT}M3X2rBp1$sT!h78b?){4sns?_3-FwXm{qW)ojPW*R;40OCYztf0 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zW!YPvW$$`ruYruAJd1U<*&clGWREV|(+F+7w{ecX0=!*py;-Ga%T4UN^ELytP1Bh) zdpv%M_~uYg{Y8^Z{_cdHZfzxy;@^KznY|{EUn+!I!_K@|a2|yK(@UP`$uEsF`Gmbp bIR=N%WH`$XvDl7s^xC|P-ETWXolX81$=Psz literal 0 HcmV?d00001 diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c.d b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c.d new file mode 100644 index 0000000..dbf507e --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c.d @@ -0,0 +1,58 @@ +build/stm32f3xx_hal_i2c.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c.lst new file mode 100644 index 0000000..0e2e568 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c.lst @@ -0,0 +1,25237 @@ +ARM GAS /tmp/ccE2rRGE.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_i2c.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c" + 20 .section .text.I2C_Flush_TXDR,"ax",%progbits + 21 .align 1 + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 I2C_Flush_TXDR: + 27 .LVL0: + 28 .LFB193: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @file stm32f3xx_hal_i2c.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * functionalities of the Inter Integrated Circuit (I2C) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + IO operation functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + Peripheral State and Errors functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @verbatim + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ============================================================================== + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ##### How to use this driver ##### + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ============================================================================== + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** The I2C HAL driver can be used as follows: + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) Declare a I2C_HandleTypeDef handle structure, for example: + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef hi2c; + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (##) Enable the I2Cx interface clock + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (##) I2C pins configuration + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Enable the clock for the I2C GPIOs + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure I2C pins as alternate function open-drain + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (##) NVIC configuration if you need to use interrupt process + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure the I2Cx interrupt priority + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Enable the NVIC I2C IRQ Channel + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (##) DMA Configuration if you need to use DMA process + ARM GAS /tmp/ccE2rRGE.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Declare a DMA_HandleTypeDef handle structure for + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the transmit or receive channel + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Enable the DMAx interface clock using + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure the DMA handle parameters + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure the DMA Tx or Rx channel + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the DMA Tx or Rx channel + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addres + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level H + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceRead + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Polling mode IO operation *** + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ================================= + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit( + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Polling mode IO MEM operation *** + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ===================================== + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_W + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_ + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Interrupt mode IO operation *** + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =================================== + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Trans + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receiv + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmi + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_ + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Interrupt mode or DMA mode IO sequential operation *** + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ========================================================== + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (@) These interfaces allow to manage a sequential transfer with a repeated start condition + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** when a direction change during transfer + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) A specific option field manage the different steps of a sequential transfer + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfac + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** no sequential mode + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start con + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and data to transfer without a final stop condition + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** start condition, address and data to transfer without a final stop cond + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** an then permit a call the same master sequential interface several time + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_D + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** transfer + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if no direction change and without a final stop condition in both cases + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** transfer + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if no direction change and with a final stop condition in both cases + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a re + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** after several call of the same master sequential interface several time + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (link with option I2C_FIRST_AND_NEXT_FRAME). + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Usage can, transfer several bytes one by one using + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Receive sequence permit to call the opposite interface Receive or Tra + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** without stopping the communication and so generate a restart conditio + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart c + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** each call of the same master sequential + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** interface. + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Usage can, transfer several bytes one by one with a restart with slave + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** each bytes using + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** generation of STOP condition. + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Different sequential I2C interfaces are listed below: + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is execut + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltC + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + ARM GAS /tmp/ccE2rRGE.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_A + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_DisableListen_IT() + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code to check the Address Match Code and the transmission direction reques + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (Write/Read). + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is execute + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCa + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed a + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Interrupt mode IO MEM operation *** + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ======================================= + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Mem_Write_IT() + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Mem_Read_IT() + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** DMA mode IO operation *** + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ============================== + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Transmit_DMA() + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Receive_DMA() + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Slave_Transmit_DMA() + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Slave_Receive_DMA() + ARM GAS /tmp/ccE2rRGE.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** DMA mode IO MEM operation *** + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ================================= + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Mem_Write_DMA() + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Mem_Read_DMA() + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** I2C HAL driver macros list *** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ================================== + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Below the list of most used macros in I2C HAL driver. + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Callback registration *** + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ============================================= + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** allows the user to configure dynamically the driver callbacks. + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to register an interrupt callback. + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Function HAL_I2C_RegisterCallback() allows to register following callbacks: + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + ARM GAS /tmp/ccE2rRGE.s page 6 + + + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and a pointer to the user callback function. + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCall + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** weak function. + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and the Callback ID. + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This function allows to reset following callbacks: + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** all callbacks are set to the corresponding weak functions: + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Exception done for MspInit and MspDeInit functions that are + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** these callbacks are null (not registered beforehand). + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Then, the user first registers the MspInit/MspDeInit user callbacks + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Init() function. + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** not defined, the callback registration feature is not available and all callbacks + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** are set to the corresponding weak functions. + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (@) You can refer to the I2C HAL driver header file for more useful macros + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @endverbatim + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ****************************************************************************** + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @attention + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * All rights reserved.

    + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This software component is licensed by ST under BSD 3-Clause license, + ARM GAS /tmp/ccE2rRGE.s page 7 + + + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the "License"; You may not use this file except in compliance with the + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * License. You may obtain a copy of the License at: + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * opensource.org/licenses/BSD-3-Clause + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ****************************************************************************** + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Includes ------------------------------------------------------------------*/ + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #include "stm32f3xx_hal.h" + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @addtogroup STM32F3xx_HAL_Driver + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C I2C + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C HAL module driver + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #ifdef HAL_I2C_MODULE_ENABLED + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private typedef -----------------------------------------------------------*/ + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private define ------------------------------------------------------------*/ + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Private_Define I2C Private Define + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define MAX_NBYTE_SIZE 255U + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define SLAVE_ADDR_SHIFT 7U + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define SLAVE_ADDR_MSK 0x06U + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private define for @ref PreviousState usage */ + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Mask State define, keep only RX and TX bits */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Default Value */ + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MASTER)) + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Master Busy TX, combinaison of State LSB and Mode enum */ + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MASTER)) + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Master Busy RX, combinaison of State LSB and Mode enum */ + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_SLAVE)) + ARM GAS /tmp/ccE2rRGE.s page 8 + + + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_SLAVE)) + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MEM)) + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MEM)) + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private define to centralize the enable/disable of Interrupts */ + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @ref I2C_XFER_LISTEN_IT */ + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @ref I2C_XFER_LISTEN_IT */ + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2 + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and @ref I2C_XFER_RX_IT */ + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of glo + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and NACK treatment */ + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evene + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private define Sequential Transfer Options default/reset value */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_NO_OPTION_FRAME (0xFFFF0000U) + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private macro -------------------------------------------------------------*/ + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private variables ---------------------------------------------------------*/ + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function prototypes -----------------------------------------------*/ + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Private_Functions I2C Private Functions + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to handle DMA transfer */ + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma); + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + ARM GAS /tmp/ccE2rRGE.s page 9 + + + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t T + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions for I2C transfer IRQ handler */ + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to handle flags during polling transfer */ + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout, uint32_t Tickstart); + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to centralize the enable/disable of Interrupts */ + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function to treat different error callback */ + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function to flush TXDR register */ + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function to handle start, restart or stop a transfer */ + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Request); + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function to Convert Specific options */ + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Exported functions --------------------------------------------------------*/ + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions I2C Exported Functions + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Initialization and Configuration functions + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + ARM GAS /tmp/ccE2rRGE.s page 10 + + + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @verbatim + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ##### Initialization and de-initialization functions ##### + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] This subsection provides a set of functions allowing to initialize and + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** deinitialize the I2Cx peripheral: + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) User must Implement HAL_I2C_MspInit() function in which he configures + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Call the function HAL_I2C_Init() to configure the selected device with + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the selected configuration: + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Clock Timing + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Own Address 1 + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Addressing mode (Master, Slave) + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Dual Addressing mode + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Own Address 2 + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Own Address 2 Mask + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) General call mode + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Nostretch mode + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Call the function HAL_I2C_DeInit() to restore the default configuration + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** of the selected I2Cx peripheral. + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @endverbatim + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Initializes the I2C according to the specified parameters + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in the I2C_InitTypeDef and initialize the associated handle. + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c == NULL) + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_RESET) + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Allocate lock resource and initialize it */ + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Lock = HAL_UNLOCKED; + ARM GAS /tmp/ccE2rRGE.s page 11 + + + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init the I2C Callback settings */ + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->MspInitCallback == NULL) + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback(hi2c); + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MspInit(hi2c); + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable the selected I2C peripheral */ + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Frequency range */ + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Own Address1 before set the Own Address1 configuration */ + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Own Address1 and ack own address1 mode */ + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else /* I2C_ADDRESSINGMODE_10BIT */ + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Addressing Master mode */ + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 = (I2C_CR2_ADD10); + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + ARM GAS /tmp/ccE2rRGE.s page 12 + + + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Own Address2 before set the Own Address2 configuration */ + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Dual mode and Own Address2 */ + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Generalcall and NoStretch mode */ + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the selected I2C peripheral */ + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_ENABLE(hi2c); + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DeInitialize the I2C peripheral. + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c == NULL) + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable the I2C Peripheral Clock */ + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->MspDeInitCallback == NULL) + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback(hi2c); + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + ARM GAS /tmp/ccE2rRGE.s page 13 + + + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MspDeInit(hi2c); + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Release Lock */ + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Initialize the I2C MSP. + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MspInit could be implemented in the user file + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DeInitialize the I2C MSP. + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MspDeInit could be implemented in the user file + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Register a User I2C Callback + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * To be used instead of the weak predefined callback + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param CallbackID ID of the callback to be registered + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + ARM GAS /tmp/ccE2rRGE.s page 14 + + + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pCallback pointer to the Callback function + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Callb + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** pI2C_CallbackTypeDef pCallback) + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (pCallback == NULL) + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process locked */ + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** switch (CallbackID) + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = pCallback; + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = pCallback; + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = pCallback; + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = pCallback; + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback = pCallback; + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemTxCpltCallback = pCallback; + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemRxCpltCallback = pCallback; + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + ARM GAS /tmp/ccE2rRGE.s page 15 + + + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCallback = pCallback; + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AbortCpltCallback = pCallback; + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** default : + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** switch (CallbackID) + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** default : + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Release Lock */ + ARM GAS /tmp/ccE2rRGE.s page 16 + + + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Unregister an I2C Callback + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * I2C callback is redirected to the weak predefined callback + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param CallbackID ID of the callback to be unregistered + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Cal + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process locked */ + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** switch (CallbackID) + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallb + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallb + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallba + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallba + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallbac + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + ARM GAS /tmp/ccE2rRGE.s page 17 + + + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** default : + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** switch (CallbackID) + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** default : + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + ARM GAS /tmp/ccE2rRGE.s page 18 + + + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Release Lock */ + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Register the Slave Address Match I2C Callback + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pCallback pointer to the Address Match Callback function + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pC + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (pCallback == NULL) + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process locked */ + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback = pCallback; + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Release Lock */ + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief UnRegister the Slave Address Match I2C Callback + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined cal + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + ARM GAS /tmp/ccE2rRGE.s page 19 + + +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process locked */ +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Release Lock */ +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Data transfers functions +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @verbatim +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ##### IO operation functions ##### +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This subsection provides a set of functions allowing to manage the I2C data +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** transfers. +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) There are two modes of transfer: +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Blocking mode : The communication is performed in the polling mode. +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** The status of all data processing is returned by the same function +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** after finishing transfer. +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) No-Blocking mode : The communication is performed using Interrupts +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or DMA. These functions return the status of the transfer startup. +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** The end of the data processing will be indicated through the +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** using DMA mode. +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) Blocking mode functions are : +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit() +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive() +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit() +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive() + ARM GAS /tmp/ccE2rRGE.s page 20 + + +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write() +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read() +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_IsDeviceReady() +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) No-Blocking mode functions with Interrupt are : +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_IT() +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_IT() +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_IT() +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_IT() +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_IT() +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_IT() +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_IT() +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_IT() +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_IT() +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_IT() +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_EnableListen_IT() +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_DisableListen_IT() +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Abort_IT() +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) No-Blocking mode functions with DMA are : +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_DMA() +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_DMA() +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_DMA() +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_DMA() +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_DMA() +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_DMA() +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_DMA() +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_DMA() +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_DMA() +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_DMA() +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_MasterTxCpltCallback() +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_MasterRxCpltCallback() +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_SlaveTxCpltCallback() +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_SlaveRxCpltCallback() +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_MemTxCpltCallback() +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_MemRxCpltCallback() +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_AddrCallback() +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_ListenCpltCallback() +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_ErrorCallback() +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_AbortCpltCallback() +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @endverbatim +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmits in master mode an amount of data in blocking mode. +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + ARM GAS /tmp/ccE2rRGE.s page 21 + + +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pD +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t Timeout) +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + ARM GAS /tmp/ccE2rRGE.s page 22 + + +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receives in master mode an amount of data in blocking mode. +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value + ARM GAS /tmp/ccE2rRGE.s page 23 + + +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pDa +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t Timeout) +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ + ARM GAS /tmp/ccE2rRGE.s page 24 + + +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 25 + + +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmits in slave mode an amount of data in blocking mode. +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout) +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If 10bit addressing mode is selected */ +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 26 + + +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until DIR flag is set Transmitter mode */ +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Normal use case for Transmitter mode */ +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* A NACK is generated to confirm the end of transfer */ +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP flag */ +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 27 + + +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in blocking mode +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout) +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ + ARM GAS /tmp/ccE2rRGE.s page 28 + + +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until DIR flag is reset Receiver mode */ +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store Last receive data if any */ +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 29 + + +1570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP flag */ +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt +1609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size) +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +1621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + ARM GAS /tmp/ccE2rRGE.s page 30 + + +1627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRIT +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccE2rRGE.s page 31 + + +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t * +1689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size) +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ +1727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +1740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 32 + + +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 33 + + +1798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +1840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA +1851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccE2rRGE.s page 34 + + +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size) +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +1864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +1897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +1899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +1905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +1909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance-> + ARM GAS /tmp/ccE2rRGE.s page 35 + + +1912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); +1913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +1922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +1946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +1949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + ARM GAS /tmp/ccE2rRGE.s page 36 + + +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +1989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +1993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with DMA +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +2007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size) +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 37 + + +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +2044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +2046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +2049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); +2060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART * +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ +2081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ + ARM GAS /tmp/ccE2rRGE.s page 38 + + +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +2118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +2130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +2136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + ARM GAS /tmp/ccE2rRGE.s page 39 + + +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +2175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +2177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +2190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); +2191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + ARM GAS /tmp/ccE2rRGE.s page 40 + + +2197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +2240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with DMA +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + ARM GAS /tmp/ccE2rRGE.s page 41 + + +2254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +2281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +2284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); +2295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 42 + + +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Write an amount of data in blocking mode to a specific memory address +2352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +2361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddre +2364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Ti +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +2367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 43 + + +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST +2412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS +2417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do +2420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccE2rRGE.s page 44 + + +2425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +2429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +2432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +2435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +2437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +2440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +2448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } while (hi2c->XferCount > 0U); +2459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +2468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +2480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + ARM GAS /tmp/ccE2rRGE.s page 45 + + +2482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Read an amount of data in blocking mode from a specific memory address +2489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +2498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddres +2501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Tim +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +2504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +2523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +2534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +2535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_ +2538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 46 + + +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +2545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +2550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do +2560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +2562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) +2563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +2569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +2572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +2574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +2575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +2577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +2580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, +2588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 47 + + +2596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } while (hi2c->XferCount > 0U); +2598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +2607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +2619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory addres +2627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +2641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +2642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 48 + + +2653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +2672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar +2688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) +2689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +2697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +2707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + ARM GAS /tmp/ccE2rRGE.s page 49 + + +2710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +2712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory addre +2721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAdd +2732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +2735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +2736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +2766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + ARM GAS /tmp/ccE2rRGE.s page 50 + + +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart +2782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +2799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +2800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +2803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +2805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address +2813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemA + ARM GAS /tmp/ccE2rRGE.s page 51 + + +2824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +2827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +2828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +2859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar +2875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) +2876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 52 + + +2881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +2884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +2887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +2889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +2897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); +2898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +2917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +2919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ + ARM GAS /tmp/ccE2rRGE.s page 53 + + +2938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +2951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. +2960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be read +2968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +2974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +2975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +2991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + ARM GAS /tmp/ccE2rRGE.s page 54 + + +2995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +3001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +3006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +3007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +3018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart +3022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +3032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +3035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +3038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +3039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +3041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); +3043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + ARM GAS /tmp/ccE2rRGE.s page 55 + + +3052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_RE +3063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +3078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +3095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +3099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Checks if target device is ready for communication. +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This function is used with Memory devices +3105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccE2rRGE.s page 56 + + +3109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Trials Number of trials +3110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +3111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Tria +3114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout) +3115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +3117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __IO uint32_t I2C_Trials = 0UL; +3119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp1; +3121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp2; +3122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +3126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +3128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; +3134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do +3137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Start */ +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); +3140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +3142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is set or a NACK flag is set*/ +3143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); +3144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); +3146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); +3147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while ((tmp1 == RESET) && (tmp2 == RESET)) +3149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +3151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +3159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 57 + + +3166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); +3168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); +3169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if the NACKF flag has not been set */ +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) +3173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +3181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Device is ready */ +3184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +3190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +3200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag, auto generated with autoend*/ +3203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if the maximum allowed number of trials has been reached */ +3207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_Trials == Trials) +3208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Stop */ +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +3211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +3219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Trials */ + ARM GAS /tmp/ccE2rRGE.s page 58 + + +3223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Trials++; +3224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } while (I2C_Trials < Trials); +3225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +3231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +3240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Inte +3245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +3259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +3260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +3276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + ARM GAS /tmp/ccE2rRGE.s page 59 + + +3280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do not generate Restart Condition */ +3293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ +3295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +3323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +3327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. +3332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccE2rRGE.s page 60 + + +3337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin +3343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +3346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +3347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +3358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +3364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do not generate Restart Condition */ +3381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ +3383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) + ARM GAS /tmp/ccE2rRGE.s page 61 + + +3394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +3400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +3405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +3408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +3411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +3412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +3414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance-> +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); +3416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + ARM GAS /tmp/ccE2rRGE.s page 62 + + +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +3473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +3475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +3476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +3491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +3495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Inter +3500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + ARM GAS /tmp/ccE2rRGE.s page 63 + + +3508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8 +3511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +3514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +3515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +3531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do not generate Restart Condition */ +3548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ +3550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 64 + + +3565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +3576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +3578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +3582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA +3587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +3601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +3602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +3619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 65 + + +3622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do not generate Restart Condition */ +3636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ +3638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +3655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +3660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +3662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +3663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +3666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +3667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +3669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p +3670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); +3671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ + ARM GAS /tmp/ccE2rRGE.s page 66 + + +3679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +3706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +3730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +3731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process + ARM GAS /tmp/ccE2rRGE.s page 67 + + +3736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +3740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +3746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +3750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +3764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t XferOptions) +3765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +3770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +3772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +3779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +3786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable associated Interrupts */ +3788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 68 + + +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +3794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +3800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX */ +3802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +3803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +3806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +3812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +3813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +3817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +3821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +3824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +3826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +3828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +3829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +3830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* REnable ADDR interrupt */ +3839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +3840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +3842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + ARM GAS /tmp/ccE2rRGE.s page 69 + + +3850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t +3860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t XferOptions) +3861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +3868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +3870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +3880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +3884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable associated Interrupts */ +3886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +3889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +3894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +3898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX */ +3900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +3901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +3904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 70 + + +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +3909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +3911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +3913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +3920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX */ +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +3923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +3926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +3933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +3936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +3937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +3941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +3945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +3948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +3953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +3955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +3956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +3960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +3963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + ARM GAS /tmp/ccE2rRGE.s page 71 + + +3964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset XferSize */ +3986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = 0; +3987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +3992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +4004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +4016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +4017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + ARM GAS /tmp/ccE2rRGE.s page 72 + + +4021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +4023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +4036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Si +4041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t XferOptions) +4042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +4044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +4047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +4049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +4056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +4063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable associated Interrupts */ +4065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 73 + + +4078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX */ +4079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +4094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +4098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) +4103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +4115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +4117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +4119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +4132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +4133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + ARM GAS /tmp/ccE2rRGE.s page 74 + + +4135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +4137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t XferOptions) +4138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +4140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +4142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +4145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +4147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +4149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +4154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +4161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable associated Interrupts */ +4163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX */ +4177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +4186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +4188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +4190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ + ARM GAS /tmp/ccE2rRGE.s page 75 + + +4192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +4197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX */ +4199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +4200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +4203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +4210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; +4213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +4218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; +4222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +4225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +4230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +4232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +4233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +4235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +4237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +4239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, +4240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); +4241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +4245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ + ARM GAS /tmp/ccE2rRGE.s page 76 + + +4249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +4250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +4258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +4261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset XferSize */ +4263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = 0; +4264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +4268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +4272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +4273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) +4281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +4293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +4295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +4298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +4300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 77 + + +4306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Enable the Address listen mode with Interrupt. +4309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +4314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +4316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the Address Match interrupt */ +4321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +4324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +4328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Disable the Address listen mode with Interrupt. +4333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C +4335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +4338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmp; +4341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address listen mode only if a transfer is not ongoing */ +4343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +4344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); +4347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +4350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable the Address Match interrupt */ +4352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +4355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; +4359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + ARM GAS /tmp/ccE2rRGE.s page 78 + + +4363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Abort a master I2C IT or DMA process communication with Interrupt. +4364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +4367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +4368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +4371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) +4373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +4378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +4379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +4382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +4384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +4386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +4387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +4391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set State at HAL_I2C_STATE_ABORT */ +4394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_ABORT; +4395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ +4397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfe +4398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); +4399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +4406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +4407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +4409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong usage of abort function */ +4413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This function should be used only in case of abort monitored by master device */ +4414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} + ARM GAS /tmp/ccE2rRGE.s page 79 + + +4420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +4423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ +4424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C event interrupt request. +4428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +4433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ +4435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +4436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +4437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C events treatment -------------------------------------*/ +4439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferISR != NULL) +4440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR(hi2c, itflags, itsources); +4442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C error interrupt request. +4447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +4452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +4454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +4455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmperror; +4456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C Bus error interrupt occurred ------------------------------------*/ +4458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ +4459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; +4462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear BERR flag */ +4464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); +4465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ +4468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ +4469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; +4472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear OVR flag */ +4474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); +4475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 80 + + +4477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ +4478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ +4479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; +4482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ARLO flag */ +4484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); +4485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +4488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; +4489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Error Callback in case of Error detected */ +4491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_ +4492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, tmperror); +4494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Master Tx Transfer completed callback. +4499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +4504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MasterTxCpltCallback could be implemented in the user file +4510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Master Rx Transfer completed callback. +4515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +4520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MasterRxCpltCallback could be implemented in the user file +4526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @brief Slave Tx Transfer completed callback. +4530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + ARM GAS /tmp/ccE2rRGE.s page 81 + + +4534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +4535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file +4541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Slave Rx Transfer completed callback. +4546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +4551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file +4557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Slave Address Match callback. +4562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFE +4565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param AddrMatchCode Address Match Code +4566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrM +4569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(TransferDirection); +4573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(AddrMatchCode); +4574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_AddrCallback() could be implemented in the user file +4577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Listen Complete callback. +4582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +4587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 82 + + +4591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_ListenCpltCallback() could be implemented in the user file +4593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Memory Tx Transfer completed callback. +4598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +4603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MemTxCpltCallback could be implemented in the user file +4609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Memory Rx Transfer completed callback. +4614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +4619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MemRxCpltCallback could be implemented in the user file +4625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C error callback. +4630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +4635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_ErrorCallback could be implemented in the user file +4641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C abort callback. +4646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/ccE2rRGE.s page 83 + + +4648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +4651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_AbortCpltCallback could be implemented in the user file +4657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +4662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions +4665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Peripheral State, Mode and Error functions +4666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * +4667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @verbatim +4668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== +4669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ##### Peripheral State, Mode and Error functions ##### +4670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== +4671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] +4672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This subsection permit to get in run-time the status of the peripheral +4673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and the data flow. +4674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @endverbatim +4676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ +4677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Return the I2C handle state. +4681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL state +4684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +4686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return I2C handle state */ +4688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return hi2c->State; +4689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Returns the I2C Master, Slave, Memory or no mode. +4693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for I2C module +4695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL mode +4696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +4698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return hi2c->Mode; +4700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Return the I2C error code. +4704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + ARM GAS /tmp/ccE2rRGE.s page 84 + + +4705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval I2C Error Code +4707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +4709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return hi2c->ErrorCode; +4711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +4715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +4719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @addtogroup I2C_Private_Functions +4722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ +4723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. +4727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +4734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +4735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t devaddress; +4737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +4738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ +4743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +4744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +4746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set corresponding Error Code */ +4749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +4750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +4751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +4754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ +4757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) +4758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +4760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +4761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 85 + + +4762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +4763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +4764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +4766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +4767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +4769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +4770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ +4772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) +4773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +4775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +4776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +4778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +4779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +4781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +4782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ +4784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +4785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +4787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); +4789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +4791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +4793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START +4794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +4799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, +4801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); +4802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, +4806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +4807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +4813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +4814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +4817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + ARM GAS /tmp/ccE2rRGE.s page 86 + + +4819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +4821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +4823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ +4827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +4828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +4832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +4834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +4835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Stop */ +4837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +4838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +4843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +4849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +4851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +4856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ +4859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +4860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master complete process */ +4862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, tmpITFlags); +4863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +4869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. +4873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. + ARM GAS /tmp/ccE2rRGE.s page 87 + + +4876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +4880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +4881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +4883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +4884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process locked */ +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if STOPF is set */ +4889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ +4890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +4891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave complete process */ +4893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, tmpITFlags); +4894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ +4897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +4898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check that I2C transfer finished */ +4900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +4901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean XferCount == 0*/ +4902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* So clear Flag NACKF only */ +4903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) +4906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +4907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +4908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Listen complete process */ +4910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +4911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME) +4913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +4915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +4918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Last Byte is Transmitted */ +4921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +4923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +4927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + ARM GAS /tmp/ccE2rRGE.s page 88 + + +4933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +4934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +4937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +4940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +4943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ +4947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) +4948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +4950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +4952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +4953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +4955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +4956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +4958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +4959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount == 0U) && \ +4962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +4963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +4966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ +4969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) +4970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, tmpITFlags); +4972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ +4974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) +4975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR only if XferCount not reach "0" */ +4977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* A TXIS flag can be set, during STOP treatment */ +4978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if all Data have already been sent */ +4979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ +4980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +4981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +4983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +4984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +4986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +4987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +4989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + ARM GAS /tmp/ccE2rRGE.s page 89 + + +4990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) +4994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Last Byte is Transmitted */ +4996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +4998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +5010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. +5014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +5022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t devaddress; +5024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +5025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +5027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ +5030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set corresponding Error Code */ +5036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +5039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* But enable STOP interrupt, to treat it */ +5040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +5041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +5042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +5044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + ARM GAS /tmp/ccE2rRGE.s page 90 + + +5047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable TC interrupt */ +5050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); +5051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +5053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Recover Slave address */ +5055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); +5056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare the new XferSize to transfer */ +5058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +5059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +5061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +5062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +5066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +5067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +5069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +5073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the new XferSize in Nbytes register */ +5077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +5078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +5080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +5081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +5083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +5086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +5090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +5095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +5096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +5099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ + ARM GAS /tmp/ccE2rRGE.s page 91 + + +5104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ +5109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +5112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +5114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +5116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +5117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Stop */ +5119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +5120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +5125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +5131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ +5136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master complete process */ +5139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); +5140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +5150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. +5154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + ARM GAS /tmp/ccE2rRGE.s page 92 + + +5161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +5162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +5164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t treatdmanack = 0U; +5165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; +5166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process locked */ +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if STOPF is set */ +5171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ +5172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave complete process */ +5175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, ITFlags); +5176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ +5179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check that I2C transfer finished */ +5182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +5183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean XferCount == 0 */ +5184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* So clear Flag NACKF only */ +5185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || +5186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) +5187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Split check of hdmarx, for MISRA compliance */ +5189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +5190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) +5192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) +5194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** treatdmanack = 1U; +5196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Split check of hdmatx, for MISRA compliance */ +5201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +5202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) +5204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) +5206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** treatdmanack = 1U; +5208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (treatdmanack == 1U) +5213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) +5215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +5216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +5217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 93 + + +5218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, ITFlags); +5220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAM +5222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +5227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +5242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ +5249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpstate = hi2c->State; +5250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +5252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) +5254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +5256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN +5258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +5264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Only Clear NACK Flag, no DMA treatment is pending */ +5274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + ARM GAS /tmp/ccE2rRGE.s page 94 + + +5275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ +5278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) +5279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, ITFlags); +5281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +5291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for write reques +5295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +5300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +5302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +5303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, +5306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t +5307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +5308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI +5310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +5315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +5319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Memory Address */ +5321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +5328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 95 + + +5332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +5333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +5340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) +5341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +5343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +5346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for read request +5350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +5355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +5357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +5358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, +5361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t T +5362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +5363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR +5365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +5370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +5374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Memory Address */ +5376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +5383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +5388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 96 + + +5389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TC flag is set */ +5395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) +5396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +5398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +5401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Address complete process callback. +5405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint8_t transferdirection; +5412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t slaveaddrcode; +5413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t ownadd1code; +5414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t ownadd2code; +5415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +5417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(ITFlags); +5418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* In case of Listen state, need to inform upper layer of address match code event */ +5420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +5421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** transferdirection = I2C_GET_DIR(hi2c); +5423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); +5424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); +5425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); +5426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If 10bits addressing mode is selected */ +5428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +5429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) +5431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = ownadd1code; +5433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrEventCount++; +5434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) +5435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset Address Event counter */ +5437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrEventCount = 0U; +5438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +5440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +5441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Slave Addr callback */ + ARM GAS /tmp/ccE2rRGE.s page 97 + + +5446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = ownadd2code; +5456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +5458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +5459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Slave Addr callback */ +5464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* else 7 bits addressing mode is selected */ +5472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +5475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +5476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Slave Addr callback */ +5481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Else clear address flag only */ +5489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +5492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +5493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Master sequential complete process. +5501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None + ARM GAS /tmp/ccE2rRGE.s page 98 + + +5503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +5505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset I2C handle mode */ +5507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No Generate Stop, to permit restart mode */ +5510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ +5511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +5515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +5516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +5526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +5528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +5531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +5535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +5536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +5546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +5548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Slave sequential complete process. +5554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +5558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + ARM GAS /tmp/ccE2rRGE.s page 99 + + +5560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset I2C handle mode */ +5562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +5565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) +5566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +5568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +5569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) +5571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +5573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +5574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +5578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +5581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ +5583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +5584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +5585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +5595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +5597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +5601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ +5603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +5604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +5615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); + ARM GAS /tmp/ccE2rRGE.s page 100 + + +5617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Master complete process. +5627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmperror; +5634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +5635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __IO uint32_t tmpreg; +5636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +5638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +5639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +5641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +5645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +5650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +5654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +5657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +5658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset handle parameters */ +5660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +5661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) +5664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set acknowledge error code */ +5669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Fetch Last receive data if any */ +5673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + ARM GAS /tmp/ccE2rRGE.s page 101 + + +5674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +5676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpreg = (uint8_t)hi2c->Instance->RXDR; +5677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(tmpreg); +5678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +5681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +5684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; +5685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) +5688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ +5693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +5699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemTxCpltCallback(hi2c); +5708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MemTxCpltCallback(hi2c); +5710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +5722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +5724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +5728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + ARM GAS /tmp/ccE2rRGE.s page 102 + + +5731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +5734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemRxCpltCallback(hi2c); +5743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MemRxCpltCallback(hi2c); +5745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +5757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +5759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Slave complete process. +5770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); +5777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +5778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; +5779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +5781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +5782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +5784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) +5785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +5787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + ARM GAS /tmp/ccE2rRGE.s page 103 + + +5788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) +5790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +5792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +5797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +5800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +5801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +5803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +5804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +5806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +5809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) +5810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +5812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +5813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +5815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); +5817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) +5820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +5822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +5823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +5825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); +5827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +5832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store Last receive data if any */ +5835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) +5836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +5838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +5839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +5841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +5842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +5844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + ARM GAS /tmp/ccE2rRGE.s page 104 + + +5845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +5847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +5849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +5850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* All data are not transferred, so set error code accordingly */ +5854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +5855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +5862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) +5864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +5870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +5873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +5876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ +5878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +5890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +5892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + ARM GAS /tmp/ccE2rRGE.s page 105 + + +5902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +5906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +5908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +5921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +5923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Listen complete process. +5929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset handle parameters */ +5936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +5941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store Last receive data if any */ +5943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) +5944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +5946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +5947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +5949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; +5950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +5952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; +5954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; +5955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 106 + + +5959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable all Interrupts*/ +5962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +5963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +5973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +5975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C interrupts error process. +5980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ErrorCode Error code to handle. +5982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +5985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; +5987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmppreviousstate; +5988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset handle parameters */ +5990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = 0U; +5993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set new error code */ +5995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= ErrorCode; +5996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_LISTEN) || +5999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || +6000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) +6001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable all interrupts, except interrupts related to LISTEN state */ +6003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); +6004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* keep HAL_I2C_STATE_LISTEN if set */ +6006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +6007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +6008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable all interrupts */ +6012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +6013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If state is an abort treatment on going, don't change state */ +6015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This change will be do later */ + ARM GAS /tmp/ccE2rRGE.s page 107 + + +6016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State != HAL_I2C_STATE_ABORT) +6017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set HAL_I2C_STATE_READY */ +6019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +6022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX transfer if any */ +6025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmppreviousstate = hi2c->PreviousState; +6026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ +6027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) +6028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +6030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) +6035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +6037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +6038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +6039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX */ +6044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +6045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +6047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +6048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX transfer if any */ +6056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ +6057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) +6058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +6060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) +6065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +6067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +6068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +6069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 108 + + +6073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX */ +6074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +6075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ +6077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +6078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Error callback treatment. +6093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +6097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) +6099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AbortCpltCallback(hi2c); +6109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_AbortCpltCallback(hi2c); +6111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCallback(hi2c); +6123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ErrorCallback(hi2c); +6125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + ARM GAS /tmp/ccE2rRGE.s page 109 + + +6130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Tx data register flush process. +6131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +6135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 29 .loc 1 6135 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. +6136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If a pending TXIS flag is set */ +6137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write a dummy data in TXDR to clear it */ +6138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 34 .loc 1 6138 3 view .LVU1 + 35 .loc 1 6138 7 is_stmt 0 view .LVU2 + 36 0000 0368 ldr r3, [r0] + 37 0002 9A69 ldr r2, [r3, #24] + 38 .loc 1 6138 6 view .LVU3 + 39 0004 12F0020F tst r2, #2 + 40 0008 01D0 beq .L2 +6139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = 0x00U; + 41 .loc 1 6140 5 is_stmt 1 view .LVU4 + 42 .loc 1 6140 26 is_stmt 0 view .LVU5 + 43 000a 0022 movs r2, #0 + 44 000c 9A62 str r2, [r3, #40] + 45 .L2: +6141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register if not empty */ +6144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 46 .loc 1 6144 3 is_stmt 1 view .LVU6 + 47 .loc 1 6144 7 is_stmt 0 view .LVU7 + 48 000e 0368 ldr r3, [r0] + 49 0010 9A69 ldr r2, [r3, #24] + 50 .loc 1 6144 6 view .LVU8 + 51 0012 12F0010F tst r2, #1 + 52 0016 03D1 bne .L1 +6145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 53 .loc 1 6146 5 is_stmt 1 view .LVU9 + 54 0018 9A69 ldr r2, [r3, #24] + 55 001a 42F00102 orr r2, r2, #1 + 56 001e 9A61 str r2, [r3, #24] + 57 .L1: +6147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 58 .loc 1 6148 1 is_stmt 0 view .LVU10 + 59 0020 7047 bx lr + 60 .cfi_endproc + 61 .LFE193: + 63 .section .text.I2C_TransferConfig,"ax",%progbits + 64 .align 1 + 65 .syntax unified + 66 .thumb + 67 .thumb_func + ARM GAS /tmp/ccE2rRGE.s page 110 + + + 69 I2C_TransferConfig: + 70 .LVL1: + 71 .LFB205: +6149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C master transmit process complete callback. +6152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +6156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupt */ +6167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +6168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Buffer pointer */ +6173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +6186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, +6187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) +6188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable TC interrupts */ +6195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C slave transmit process complete callback. +6202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle + ARM GAS /tmp/ccE2rRGE.s page 111 + + +6203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +6206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) +6212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Last Byte is Transmitted */ +6217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C master receive process complete callback. +6230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +6234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupt */ +6245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +6246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Buffer pointer */ +6251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 112 + + +6260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +6264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, +6265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) +6266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable TC interrupts */ +6273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C slave receive process complete callback. +6280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +6284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ +6290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +6291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C communication error callback. +6308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma) +6312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Acknowledge */ + ARM GAS /tmp/ccE2rRGE.s page 113 + + +6317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +6318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C communication abort callback +6325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * (To be called at end of DMA Abort procedure). +6326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle. +6327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +6330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset AbortCpltCallback */ +6335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +6336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +6338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +6340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +6342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout. +6349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Flag Specifies the I2C flag to check. +6352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Status The new Flag status (SET or RESET). +6353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta +6358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout, uint32_t Tickstart) +6359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) +6361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccE2rRGE.s page 114 + + +6374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +6378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. +6382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +6390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) +6392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if a NACK is detected */ +6394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +6416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. +6420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +6428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +6430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 115 + + +6431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if a NACK is detected */ +6432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +6451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. +6455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +6463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) +6465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if a NACK is detected */ +6467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if a STOPF is detected */ +6473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) +6474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if an RXNE is pending */ +6476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store Last receive data if any */ +6477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) +6478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return HAL_OK */ +6480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* The Reading of data from RXDR will be done in caller function */ +6481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +6482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +6486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 116 + + +6488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +6490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +6492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +6515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles Acknowledge failed detection during an I2C Communication. +6519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_ +6526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) +6528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* In case of Soft End condition, generate the STOP condition */ +6530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +6531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Stop */ +6533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +6534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOP Flag is reset */ +6536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* AutoEnd should be initiate after AF */ +6537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +6538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + ARM GAS /tmp/ccE2rRGE.s page 117 + + +6545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACKF Flag */ +6557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +6560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +6563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +6564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +6567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +6569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +6576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; +6578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag ar +6582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Specifies the slave address to be programmed. +6584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Specifies the number of bytes to be programmed. +6585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter must be a value between 0 and 255. +6586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Mode New state of the I2C START condition generation. +6587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: +6588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_RELOAD_MODE Enable Reload mode . +6589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. +6590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. +6591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Request New state of the I2C START condition generation. +6592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: +6593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. +6594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). +6595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. +6596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. +6597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t +6600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Request) +6601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 118 + + + 72 .loc 1 6601 1 is_stmt 1 view -0 + 73 .cfi_startproc + 74 @ args = 4, pretend = 0, frame = 0 + 75 @ frame_needed = 0, uses_anonymous_args = 0 + 76 @ link register save eliminated. + 77 .loc 1 6601 1 is_stmt 0 view .LVU12 + 78 0000 30B4 push {r4, r5} + 79 .cfi_def_cfa_offset 8 + 80 .cfi_offset 4, -8 + 81 .cfi_offset 5, -4 + 82 0002 029D ldr r5, [sp, #8] +6602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +6603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 83 .loc 1 6603 3 is_stmt 1 view .LVU13 +6604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_TRANSFER_MODE(Mode)); + 84 .loc 1 6604 3 view .LVU14 +6605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_TRANSFER_REQUEST(Request)); + 85 .loc 1 6605 3 view .LVU15 +6606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* update CR2 register */ +6608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** MODIFY_REG(hi2c->Instance->CR2, + 86 .loc 1 6608 3 view .LVU16 + 87 0004 0468 ldr r4, [r0] + 88 0006 6068 ldr r0, [r4, #4] + 89 .LVL2: + 90 .loc 1 6608 3 is_stmt 0 view .LVU17 + 91 0008 4FEA555C lsr ip, r5, #21 + 92 000c 0CF4806C and ip, ip, #1024 + 93 0010 4CF07F7C orr ip, ip, #66846720 + 94 0014 4CF4583C orr ip, ip, #221184 + 95 0018 4CF47F7C orr ip, ip, #1020 + 96 001c 4CF0030C orr ip, ip, #3 + 97 0020 20EA0C00 bic r0, r0, ip + 98 0024 C1F30901 ubfx r1, r1, #0, #10 + 99 .LVL3: + 100 .loc 1 6608 3 view .LVU18 + 101 0028 41EA0241 orr r1, r1, r2, lsl #16 + 102 002c 1943 orrs r1, r1, r3 + 103 002e 2943 orrs r1, r1, r5 + 104 0030 0843 orrs r0, r0, r1 + 105 0032 6060 str r0, [r4, #4] +6609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ +6610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ +6611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_CR2_START | I2C_CR2_STOP)), \ +6612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ +6613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ +6614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)Mode | (uint32_t)Request)); +6615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 106 .loc 1 6615 1 view .LVU19 + 107 0034 30BC pop {r4, r5} + 108 .cfi_restore 5 + 109 .cfi_restore 4 + 110 .cfi_def_cfa_offset 0 + 111 .LVL4: + 112 .loc 1 6615 1 view .LVU20 + 113 0036 7047 bx lr + 114 .cfi_endproc + ARM GAS /tmp/ccE2rRGE.s page 119 + + + 115 .LFE205: + 117 .section .text.I2C_Enable_IRQ,"ax",%progbits + 118 .align 1 + 119 .syntax unified + 120 .thumb + 121 .thumb_func + 123 I2C_Enable_IRQ: + 124 .LVL5: + 125 .LFB206: +6616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Manage the enabling of Interrupts. +6619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +6622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +6625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 126 .loc 1 6625 1 is_stmt 1 view -0 + 127 .cfi_startproc + 128 @ args = 0, pretend = 0, frame = 0 + 129 @ frame_needed = 0, uses_anonymous_args = 0 + 130 @ link register save eliminated. +6626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 131 .loc 1 6626 3 view .LVU22 +6627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + 132 .loc 1 6628 3 view .LVU23 + 133 .loc 1 6628 12 is_stmt 0 view .LVU24 + 134 0000 436B ldr r3, [r0, #52] + 135 .loc 1 6628 6 view .LVU25 + 136 0002 1A4A ldr r2, .L20 + 137 0004 9342 cmp r3, r2 + 138 0006 15D0 beq .L7 + 139 .loc 1 6628 45 discriminator 1 view .LVU26 + 140 0008 194A ldr r2, .L20+4 + 141 000a 9342 cmp r3, r2 + 142 000c 12D0 beq .L7 +6629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) +6630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) +6632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK and ADDR interrupts */ +6634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) +6638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +6640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +6641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) +6644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupts */ +6646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + ARM GAS /tmp/ccE2rRGE.s page 120 + + +6647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) +6650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable TC interrupts */ +6652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +6653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 143 .loc 1 6657 5 is_stmt 1 view .LVU27 + 144 .loc 1 6657 8 is_stmt 0 view .LVU28 + 145 000e 11F4004F tst r1, #32768 + 146 0012 28D1 bne .L17 +6626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 147 .loc 1 6626 12 view .LVU29 + 148 0014 0023 movs r3, #0 + 149 .L12: + 150 .LVL6: +6658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, and ADDR interrupts */ +6660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +6661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 151 .loc 1 6663 5 is_stmt 1 view .LVU30 + 152 .loc 1 6663 8 is_stmt 0 view .LVU31 + 153 0016 11F0010F tst r1, #1 + 154 001a 01D0 beq .L13 +6664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +6666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 155 .loc 1 6666 7 is_stmt 1 view .LVU32 + 156 .loc 1 6666 14 is_stmt 0 view .LVU33 + 157 001c 43F0F203 orr r3, r3, #242 + 158 .LVL7: + 159 .L13: +6667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 160 .loc 1 6669 5 is_stmt 1 view .LVU34 + 161 .loc 1 6669 8 is_stmt 0 view .LVU35 + 162 0020 11F0020F tst r1, #2 + 163 0024 01D0 beq .L14 +6670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and TXI interrupts */ +6672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 164 .loc 1 6672 7 is_stmt 1 view .LVU36 + 165 .loc 1 6672 14 is_stmt 0 view .LVU37 + 166 0026 43F0F403 orr r3, r3, #244 + 167 .LVL8: + 168 .L14: +6673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 169 .loc 1 6675 5 is_stmt 1 view .LVU38 + ARM GAS /tmp/ccE2rRGE.s page 121 + + + 170 .loc 1 6675 8 is_stmt 0 view .LVU39 + 171 002a 2029 cmp r1, #32 + 172 002c 0ED1 bne .L11 +6676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupts */ +6678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; + 173 .loc 1 6678 7 is_stmt 1 view .LVU40 + 174 .loc 1 6678 14 is_stmt 0 view .LVU41 + 175 002e 43F02003 orr r3, r3, #32 + 176 .LVL9: + 177 .loc 1 6678 14 view .LVU42 + 178 0032 0BE0 b .L11 + 179 .LVL10: + 180 .L7: +6631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 181 .loc 1 6631 5 is_stmt 1 view .LVU43 +6631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 182 .loc 1 6631 8 is_stmt 0 view .LVU44 + 183 0034 11F4004F tst r1, #32768 + 184 0038 03D1 bne .L15 +6637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 185 .loc 1 6637 5 is_stmt 1 view .LVU45 +6637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 186 .loc 1 6637 8 is_stmt 0 view .LVU46 + 187 003a 1029 cmp r1, #16 + 188 003c 0BD0 beq .L16 +6626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 189 .loc 1 6626 12 view .LVU47 + 190 003e 0023 movs r3, #0 + 191 0040 00E0 b .L9 + 192 .L15: +6634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 193 .loc 1 6634 14 view .LVU48 + 194 0042 B823 movs r3, #184 + 195 .L9: + 196 .LVL11: +6643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 197 .loc 1 6643 5 is_stmt 1 view .LVU49 +6643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 198 .loc 1 6643 8 is_stmt 0 view .LVU50 + 199 0044 2029 cmp r1, #32 + 200 0046 08D0 beq .L18 + 201 .L10: +6649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 202 .loc 1 6649 5 is_stmt 1 view .LVU51 +6649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 203 .loc 1 6649 8 is_stmt 0 view .LVU52 + 204 0048 4029 cmp r1, #64 + 205 004a 09D0 beq .L19 + 206 .L11: +6679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable interrupts only at the end */ +6683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* to avoid the risk of I2C interrupt handle execution before */ +6684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* all interrupts requested done */ +6685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + ARM GAS /tmp/ccE2rRGE.s page 122 + + + 207 .loc 1 6685 3 is_stmt 1 view .LVU53 + 208 004c 0168 ldr r1, [r0] + 209 .LVL12: + 210 .loc 1 6685 3 is_stmt 0 view .LVU54 + 211 004e 0A68 ldr r2, [r1] + 212 0050 1343 orrs r3, r3, r2 + 213 .LVL13: + 214 .loc 1 6685 3 view .LVU55 + 215 0052 0B60 str r3, [r1] +6686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 216 .loc 1 6686 1 view .LVU56 + 217 0054 7047 bx lr + 218 .LVL14: + 219 .L16: +6640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 220 .loc 1 6640 14 view .LVU57 + 221 0056 9023 movs r3, #144 + 222 0058 F4E7 b .L9 + 223 .LVL15: + 224 .L18: +6646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 225 .loc 1 6646 7 is_stmt 1 view .LVU58 +6646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 226 .loc 1 6646 14 is_stmt 0 view .LVU59 + 227 005a 43F06003 orr r3, r3, #96 + 228 .LVL16: +6646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 229 .loc 1 6646 14 view .LVU60 + 230 005e F3E7 b .L10 + 231 .L19: +6652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 232 .loc 1 6652 7 is_stmt 1 view .LVU61 +6652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 233 .loc 1 6652 14 is_stmt 0 view .LVU62 + 234 0060 43F04003 orr r3, r3, #64 + 235 .LVL17: +6652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 236 .loc 1 6652 14 view .LVU63 + 237 0064 F2E7 b .L11 + 238 .LVL18: + 239 .L17: +6660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 240 .loc 1 6660 14 view .LVU64 + 241 0066 B823 movs r3, #184 + 242 0068 D5E7 b .L12 + 243 .L21: + 244 006a 00BF .align 2 + 245 .L20: + 246 006c 00000000 .word I2C_Master_ISR_DMA + 247 0070 00000000 .word I2C_Slave_ISR_DMA + 248 .cfi_endproc + 249 .LFE206: + 251 .section .text.I2C_Disable_IRQ,"ax",%progbits + 252 .align 1 + 253 .syntax unified + 254 .thumb + 255 .thumb_func + ARM GAS /tmp/ccE2rRGE.s page 123 + + + 257 I2C_Disable_IRQ: + 258 .LVL19: + 259 .LFB207: +6687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Manage the disabling of Interrupts. +6690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +6693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +6696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 260 .loc 1 6696 1 is_stmt 1 view -0 + 261 .cfi_startproc + 262 @ args = 0, pretend = 0, frame = 0 + 263 @ frame_needed = 0, uses_anonymous_args = 0 + 264 @ link register save eliminated. +6697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 265 .loc 1 6697 3 view .LVU66 +6698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 266 .loc 1 6699 3 view .LVU67 + 267 .loc 1 6699 6 is_stmt 0 view .LVU68 + 268 0000 11F0010F tst r1, #1 + 269 0004 09D0 beq .L29 +6700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable TC and TXI interrupts */ +6702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + 270 .loc 1 6702 5 is_stmt 1 view .LVU69 + 271 .LVL20: +6703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 272 .loc 1 6704 5 view .LVU70 + 273 .loc 1 6704 24 is_stmt 0 view .LVU71 + 274 0006 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 275 .loc 1 6704 8 view .LVU72 + 276 000a 03F02803 and r3, r3, #40 + 277 000e 282B cmp r3, #40 + 278 0010 01D0 beq .L32 +6705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +6707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 279 .loc 1 6707 14 view .LVU73 + 280 0012 F223 movs r3, #242 + 281 0014 02E0 b .L23 + 282 .L32: +6702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 283 .loc 1 6702 12 view .LVU74 + 284 0016 4223 movs r3, #66 + 285 0018 00E0 b .L23 + 286 .LVL21: + 287 .L29: +6697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 288 .loc 1 6697 12 view .LVU75 + 289 001a 0023 movs r3, #0 + 290 .LVL22: + ARM GAS /tmp/ccE2rRGE.s page 124 + + + 291 .L23: +6708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 292 .loc 1 6711 3 is_stmt 1 view .LVU76 + 293 .loc 1 6711 6 is_stmt 0 view .LVU77 + 294 001c 11F0020F tst r1, #2 + 295 0020 09D0 beq .L24 +6712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable TC and RXI interrupts */ +6714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + 296 .loc 1 6714 5 is_stmt 1 view .LVU78 + 297 .loc 1 6714 12 is_stmt 0 view .LVU79 + 298 0022 43F0440C orr ip, r3, #68 + 299 .LVL23: +6715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 300 .loc 1 6716 5 is_stmt 1 view .LVU80 + 301 .loc 1 6716 24 is_stmt 0 view .LVU81 + 302 0026 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 303 .loc 1 6716 8 view .LVU82 + 304 002a 02F02802 and r2, r2, #40 + 305 002e 282A cmp r2, #40 + 306 0030 10D0 beq .L31 +6717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +6719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 307 .loc 1 6719 7 is_stmt 1 view .LVU83 + 308 .loc 1 6719 14 is_stmt 0 view .LVU84 + 309 0032 43F0F403 orr r3, r3, #244 + 310 .LVL24: + 311 .L24: +6720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 312 .loc 1 6723 3 is_stmt 1 view .LVU85 + 313 .loc 1 6723 6 is_stmt 0 view .LVU86 + 314 0036 11F4004F tst r1, #32768 + 315 003a 0DD1 bne .L33 + 316 .L25: +6724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable ADDR, NACK and STOP interrupts */ +6726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +6727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 317 .loc 1 6729 3 is_stmt 1 view .LVU87 + 318 .loc 1 6729 6 is_stmt 0 view .LVU88 + 319 003c 1029 cmp r1, #16 + 320 003e 0ED0 beq .L34 + 321 .L26: +6730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +6732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +6733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 125 + + +6734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 322 .loc 1 6735 3 is_stmt 1 view .LVU89 + 323 .loc 1 6735 6 is_stmt 0 view .LVU90 + 324 0040 2029 cmp r1, #32 + 325 0042 0FD0 beq .L35 + 326 .L27: +6736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupts */ +6738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; +6739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) + 327 .loc 1 6741 3 is_stmt 1 view .LVU91 + 328 .loc 1 6741 6 is_stmt 0 view .LVU92 + 329 0044 4029 cmp r1, #64 + 330 0046 10D0 beq .L36 + 331 .L28: +6742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable TC interrupts */ +6744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +6745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable interrupts only at the end */ +6748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* to avoid a breaking situation like at "t" time */ +6749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* all disable interrupts request are not done */ +6750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + 332 .loc 1 6750 3 is_stmt 1 view .LVU93 + 333 0048 0168 ldr r1, [r0] + 334 .LVL25: + 335 .loc 1 6750 3 is_stmt 0 view .LVU94 + 336 004a 0A68 ldr r2, [r1] + 337 004c 22EA0303 bic r3, r2, r3 + 338 .LVL26: + 339 .loc 1 6750 3 view .LVU95 + 340 0050 0B60 str r3, [r1] +6751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 341 .loc 1 6751 1 view .LVU96 + 342 0052 7047 bx lr + 343 .LVL27: + 344 .L31: +6714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 345 .loc 1 6714 12 view .LVU97 + 346 0054 6346 mov r3, ip + 347 0056 EEE7 b .L24 + 348 .LVL28: + 349 .L33: +6726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 350 .loc 1 6726 5 is_stmt 1 view .LVU98 +6726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 351 .loc 1 6726 12 is_stmt 0 view .LVU99 + 352 0058 43F0B803 orr r3, r3, #184 + 353 .LVL29: +6726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 354 .loc 1 6726 12 view .LVU100 + 355 005c EEE7 b .L25 + 356 .L34: + ARM GAS /tmp/ccE2rRGE.s page 126 + + +6732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 357 .loc 1 6732 5 is_stmt 1 view .LVU101 +6732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 358 .loc 1 6732 12 is_stmt 0 view .LVU102 + 359 005e 43F09003 orr r3, r3, #144 + 360 .LVL30: +6732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 361 .loc 1 6732 12 view .LVU103 + 362 0062 EDE7 b .L26 + 363 .L35: +6738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 364 .loc 1 6738 5 is_stmt 1 view .LVU104 +6738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 365 .loc 1 6738 12 is_stmt 0 view .LVU105 + 366 0064 43F02003 orr r3, r3, #32 + 367 .LVL31: +6738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 368 .loc 1 6738 12 view .LVU106 + 369 0068 ECE7 b .L27 + 370 .L36: +6744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 371 .loc 1 6744 5 is_stmt 1 view .LVU107 +6744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 372 .loc 1 6744 12 is_stmt 0 view .LVU108 + 373 006a 43F04003 orr r3, r3, #64 + 374 .LVL32: +6744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 375 .loc 1 6744 12 view .LVU109 + 376 006e EBE7 b .L28 + 377 .cfi_endproc + 378 .LFE207: + 380 .section .text.I2C_ConvertOtherXferOptions,"ax",%progbits + 381 .align 1 + 382 .syntax unified + 383 .thumb + 384 .thumb_func + 386 I2C_ConvertOtherXferOptions: + 387 .LVL33: + 388 .LFB208: +6752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. +6755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +6759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 389 .loc 1 6759 1 is_stmt 1 view -0 + 390 .cfi_startproc + 391 @ args = 0, pretend = 0, frame = 0 + 392 @ frame_needed = 0, uses_anonymous_args = 0 + 393 @ link register save eliminated. +6760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if user set XferOptions to I2C_OTHER_FRAME */ +6761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +6762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_FRAME */ +6763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_OTHER_FRAME) + 394 .loc 1 6763 3 view .LVU111 + ARM GAS /tmp/ccE2rRGE.s page 127 + + + 395 .loc 1 6763 11 is_stmt 0 view .LVU112 + 396 0000 C36A ldr r3, [r0, #44] + 397 .loc 1 6763 6 view .LVU113 + 398 0002 AA2B cmp r3, #170 + 399 0004 04D0 beq .L40 +6764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_FRAME; +6766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ +6768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +6769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* then generate a stop condition at the end of transfer */ +6770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ +6771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + 400 .loc 1 6771 8 is_stmt 1 view .LVU114 + 401 .loc 1 6771 16 is_stmt 0 view .LVU115 + 402 0006 C36A ldr r3, [r0, #44] + 403 .loc 1 6771 11 view .LVU116 + 404 0008 B3F52A4F cmp r3, #43520 + 405 000c 03D0 beq .L41 + 406 .L37: +6772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; +6774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +6778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 407 .loc 1 6779 1 view .LVU117 + 408 000e 7047 bx lr + 409 .L40: +6765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 410 .loc 1 6765 5 is_stmt 1 view .LVU118 +6765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 411 .loc 1 6765 23 is_stmt 0 view .LVU119 + 412 0010 0023 movs r3, #0 + 413 0012 C362 str r3, [r0, #44] + 414 0014 7047 bx lr + 415 .L41: +6773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 416 .loc 1 6773 5 is_stmt 1 view .LVU120 +6773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 417 .loc 1 6773 23 is_stmt 0 view .LVU121 + 418 0016 4FF00073 mov r3, #33554432 + 419 001a C362 str r3, [r0, #44] +6778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 420 .loc 1 6778 3 is_stmt 1 view .LVU122 + 421 .loc 1 6779 1 is_stmt 0 view .LVU123 + 422 001c F7E7 b .L37 + 423 .cfi_endproc + 424 .LFE208: + 426 .section .text.I2C_IsAcknowledgeFailed,"ax",%progbits + 427 .align 1 + 428 .syntax unified + 429 .thumb + 430 .thumb_func + 432 I2C_IsAcknowledgeFailed: + ARM GAS /tmp/ccE2rRGE.s page 128 + + + 433 .LVL34: + 434 .LFB204: +6526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 435 .loc 1 6526 1 is_stmt 1 view -0 + 436 .cfi_startproc + 437 @ args = 0, pretend = 0, frame = 0 + 438 @ frame_needed = 0, uses_anonymous_args = 0 +6526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 439 .loc 1 6526 1 is_stmt 0 view .LVU125 + 440 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 441 .cfi_def_cfa_offset 24 + 442 .cfi_offset 3, -24 + 443 .cfi_offset 4, -20 + 444 .cfi_offset 5, -16 + 445 .cfi_offset 6, -12 + 446 .cfi_offset 7, -8 + 447 .cfi_offset 14, -4 + 448 0002 0E46 mov r6, r1 +6527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 449 .loc 1 6527 3 is_stmt 1 view .LVU126 +6527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 450 .loc 1 6527 7 is_stmt 0 view .LVU127 + 451 0004 0368 ldr r3, [r0] + 452 0006 9969 ldr r1, [r3, #24] + 453 .LVL35: +6527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 454 .loc 1 6527 6 view .LVU128 + 455 0008 11F0100F tst r1, #16 + 456 000c 46D0 beq .L49 + 457 000e 0546 mov r5, r0 + 458 0010 1746 mov r7, r2 +6530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 459 .loc 1 6530 5 is_stmt 1 view .LVU129 +6530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 460 .loc 1 6530 9 is_stmt 0 view .LVU130 + 461 0012 5A68 ldr r2, [r3, #4] + 462 .LVL36: +6530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 463 .loc 1 6530 8 view .LVU131 + 464 0014 12F0007F tst r2, #33554432 + 465 0018 03D1 bne .L45 +6533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 466 .loc 1 6533 7 is_stmt 1 view .LVU132 +6533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 467 .loc 1 6533 21 is_stmt 0 view .LVU133 + 468 001a 5A68 ldr r2, [r3, #4] +6533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 469 .loc 1 6533 27 view .LVU134 + 470 001c 42F48042 orr r2, r2, #16384 + 471 0020 5A60 str r2, [r3, #4] + 472 .LVL37: + 473 .L45: +6537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 474 .loc 1 6537 53 is_stmt 1 view .LVU135 +6537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 475 .loc 1 6537 12 is_stmt 0 view .LVU136 + 476 0022 2B68 ldr r3, [r5] + ARM GAS /tmp/ccE2rRGE.s page 129 + + + 477 0024 9C69 ldr r4, [r3, #24] +6537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 478 .loc 1 6537 53 view .LVU137 + 479 0026 14F0200F tst r4, #32 + 480 002a 17D1 bne .L51 +6540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 481 .loc 1 6540 7 is_stmt 1 view .LVU138 +6540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 482 .loc 1 6540 10 is_stmt 0 view .LVU139 + 483 002c B6F1FF3F cmp r6, #-1 + 484 0030 F7D0 beq .L45 +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 485 .loc 1 6542 9 is_stmt 1 view .LVU140 +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 486 .loc 1 6542 15 is_stmt 0 view .LVU141 + 487 0032 FFF7FEFF bl HAL_GetTick + 488 .LVL38: +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 489 .loc 1 6542 29 view .LVU142 + 490 0036 C01B subs r0, r0, r7 +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 491 .loc 1 6542 12 view .LVU143 + 492 0038 B042 cmp r0, r6 + 493 003a 01D8 bhi .L46 +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 494 .loc 1 6542 53 discriminator 1 view .LVU144 + 495 003c 002E cmp r6, #0 + 496 003e F0D1 bne .L45 + 497 .L46: +6544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 498 .loc 1 6544 11 is_stmt 1 view .LVU145 +6544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 499 .loc 1 6544 15 is_stmt 0 view .LVU146 + 500 0040 6B6C ldr r3, [r5, #68] +6544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 501 .loc 1 6544 27 view .LVU147 + 502 0042 43F02003 orr r3, r3, #32 + 503 0046 6B64 str r3, [r5, #68] +6545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 504 .loc 1 6545 11 is_stmt 1 view .LVU148 +6545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 505 .loc 1 6545 23 is_stmt 0 view .LVU149 + 506 0048 2023 movs r3, #32 + 507 004a 85F84130 strb r3, [r5, #65] +6546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 508 .loc 1 6546 11 is_stmt 1 view .LVU150 +6546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 509 .loc 1 6546 22 is_stmt 0 view .LVU151 + 510 004e 0023 movs r3, #0 + 511 0050 85F84230 strb r3, [r5, #66] +6549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 512 .loc 1 6549 11 is_stmt 1 view .LVU152 +6549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 513 .loc 1 6549 11 view .LVU153 + 514 0054 85F84030 strb r3, [r5, #64] +6549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 515 .loc 1 6549 11 view .LVU154 + ARM GAS /tmp/ccE2rRGE.s page 130 + + +6551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 516 .loc 1 6551 11 view .LVU155 +6551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 517 .loc 1 6551 18 is_stmt 0 view .LVU156 + 518 0058 0120 movs r0, #1 + 519 005a 20E0 b .L43 + 520 .L51: +6557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 521 .loc 1 6557 5 is_stmt 1 view .LVU157 + 522 005c 1022 movs r2, #16 + 523 005e DA61 str r2, [r3, #28] +6560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 524 .loc 1 6560 5 view .LVU158 + 525 0060 2B68 ldr r3, [r5] + 526 0062 2024 movs r4, #32 + 527 0064 DC61 str r4, [r3, #28] +6563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 528 .loc 1 6563 5 view .LVU159 + 529 0066 2846 mov r0, r5 + 530 0068 FFF7FEFF bl I2C_Flush_TXDR + 531 .LVL39: +6566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 532 .loc 1 6566 5 view .LVU160 + 533 006c 2A68 ldr r2, [r5] + 534 006e 5368 ldr r3, [r2, #4] + 535 0070 23F0FF73 bic r3, r3, #33423360 + 536 0074 23F48B33 bic r3, r3, #71168 + 537 0078 23F4FF73 bic r3, r3, #510 + 538 007c 23F00103 bic r3, r3, #1 + 539 0080 5360 str r3, [r2, #4] +6568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 540 .loc 1 6568 5 view .LVU161 +6568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 541 .loc 1 6568 9 is_stmt 0 view .LVU162 + 542 0082 6B6C ldr r3, [r5, #68] +6568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 543 .loc 1 6568 21 view .LVU163 + 544 0084 43F00403 orr r3, r3, #4 + 545 0088 6B64 str r3, [r5, #68] +6569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 546 .loc 1 6569 5 is_stmt 1 view .LVU164 +6569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 547 .loc 1 6569 17 is_stmt 0 view .LVU165 + 548 008a 85F84140 strb r4, [r5, #65] +6570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 549 .loc 1 6570 5 is_stmt 1 view .LVU166 +6570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 550 .loc 1 6570 16 is_stmt 0 view .LVU167 + 551 008e 0023 movs r3, #0 + 552 0090 85F84230 strb r3, [r5, #66] +6573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 553 .loc 1 6573 5 is_stmt 1 view .LVU168 +6573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 554 .loc 1 6573 5 view .LVU169 + 555 0094 85F84030 strb r3, [r5, #64] +6573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 556 .loc 1 6573 5 view .LVU170 + ARM GAS /tmp/ccE2rRGE.s page 131 + + +6575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 557 .loc 1 6575 5 view .LVU171 +6575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 558 .loc 1 6575 12 is_stmt 0 view .LVU172 + 559 0098 0120 movs r0, #1 + 560 009a 00E0 b .L43 + 561 .LVL40: + 562 .L49: +6577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 563 .loc 1 6577 10 view .LVU173 + 564 009c 0020 movs r0, #0 + 565 .LVL41: + 566 .L43: +6578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 567 .loc 1 6578 1 view .LVU174 + 568 009e F8BD pop {r3, r4, r5, r6, r7, pc} +6578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 569 .loc 1 6578 1 view .LVU175 + 570 .cfi_endproc + 571 .LFE204: + 573 .section .text.I2C_WaitOnTXISFlagUntilTimeout,"ax",%progbits + 574 .align 1 + 575 .syntax unified + 576 .thumb + 577 .thumb_func + 579 I2C_WaitOnTXISFlagUntilTimeout: + 580 .LVL42: + 581 .LFB201: +6390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 582 .loc 1 6390 1 is_stmt 1 view -0 + 583 .cfi_startproc + 584 @ args = 0, pretend = 0, frame = 0 + 585 @ frame_needed = 0, uses_anonymous_args = 0 +6390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 586 .loc 1 6390 1 is_stmt 0 view .LVU177 + 587 0000 70B5 push {r4, r5, r6, lr} + 588 .cfi_def_cfa_offset 16 + 589 .cfi_offset 4, -16 + 590 .cfi_offset 5, -12 + 591 .cfi_offset 6, -8 + 592 .cfi_offset 14, -4 + 593 0002 0446 mov r4, r0 + 594 0004 0D46 mov r5, r1 + 595 0006 1646 mov r6, r2 +6391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 596 .loc 1 6391 3 is_stmt 1 view .LVU178 + 597 .LVL43: + 598 .L55: +6391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 599 .loc 1 6391 50 view .LVU179 +6391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 600 .loc 1 6391 10 is_stmt 0 view .LVU180 + 601 0008 2368 ldr r3, [r4] + 602 000a 9B69 ldr r3, [r3, #24] +6391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 603 .loc 1 6391 50 view .LVU181 + 604 000c 13F0020F tst r3, #2 + ARM GAS /tmp/ccE2rRGE.s page 132 + + + 605 0010 1DD1 bne .L60 +6394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 606 .loc 1 6394 5 is_stmt 1 view .LVU182 +6394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 607 .loc 1 6394 9 is_stmt 0 view .LVU183 + 608 0012 3246 mov r2, r6 + 609 0014 2946 mov r1, r5 + 610 0016 2046 mov r0, r4 + 611 0018 FFF7FEFF bl I2C_IsAcknowledgeFailed + 612 .LVL44: +6394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 613 .loc 1 6394 8 view .LVU184 + 614 001c C8B9 cbnz r0, .L58 +6400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 615 .loc 1 6400 5 is_stmt 1 view .LVU185 +6400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 616 .loc 1 6400 8 is_stmt 0 view .LVU186 + 617 001e B5F1FF3F cmp r5, #-1 + 618 0022 F1D0 beq .L55 +6402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 619 .loc 1 6402 7 is_stmt 1 view .LVU187 +6402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 620 .loc 1 6402 13 is_stmt 0 view .LVU188 + 621 0024 FFF7FEFF bl HAL_GetTick + 622 .LVL45: +6402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 623 .loc 1 6402 27 view .LVU189 + 624 0028 801B subs r0, r0, r6 +6402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 625 .loc 1 6402 10 view .LVU190 + 626 002a A842 cmp r0, r5 + 627 002c 01D8 bhi .L56 +6402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 628 .loc 1 6402 51 discriminator 1 view .LVU191 + 629 002e 002D cmp r5, #0 + 630 0030 EAD1 bne .L55 + 631 .L56: +6404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 632 .loc 1 6404 9 is_stmt 1 view .LVU192 +6404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 633 .loc 1 6404 13 is_stmt 0 view .LVU193 + 634 0032 636C ldr r3, [r4, #68] +6404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 635 .loc 1 6404 25 view .LVU194 + 636 0034 43F02003 orr r3, r3, #32 + 637 0038 6364 str r3, [r4, #68] +6405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 638 .loc 1 6405 9 is_stmt 1 view .LVU195 +6405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 639 .loc 1 6405 21 is_stmt 0 view .LVU196 + 640 003a 2023 movs r3, #32 + 641 003c 84F84130 strb r3, [r4, #65] +6406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 642 .loc 1 6406 9 is_stmt 1 view .LVU197 +6406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 643 .loc 1 6406 20 is_stmt 0 view .LVU198 + 644 0040 0023 movs r3, #0 + ARM GAS /tmp/ccE2rRGE.s page 133 + + + 645 0042 84F84230 strb r3, [r4, #66] +6409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 646 .loc 1 6409 9 is_stmt 1 view .LVU199 +6409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 647 .loc 1 6409 9 view .LVU200 + 648 0046 84F84030 strb r3, [r4, #64] +6409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 649 .loc 1 6409 9 view .LVU201 +6411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 650 .loc 1 6411 9 view .LVU202 +6411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 651 .loc 1 6411 16 is_stmt 0 view .LVU203 + 652 004a 0120 movs r0, #1 + 653 004c 00E0 b .L54 + 654 .L60: +6415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 655 .loc 1 6415 10 view .LVU204 + 656 004e 0020 movs r0, #0 + 657 .L54: +6416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 658 .loc 1 6416 1 view .LVU205 + 659 0050 70BD pop {r4, r5, r6, pc} + 660 .LVL46: + 661 .L58: +6396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 662 .loc 1 6396 14 view .LVU206 + 663 0052 0120 movs r0, #1 + 664 0054 FCE7 b .L54 + 665 .cfi_endproc + 666 .LFE201: + 668 .section .text.I2C_WaitOnFlagUntilTimeout,"ax",%progbits + 669 .align 1 + 670 .syntax unified + 671 .thumb + 672 .thumb_func + 674 I2C_WaitOnFlagUntilTimeout: + 675 .LVL47: + 676 .LFB200: +6359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 677 .loc 1 6359 1 is_stmt 1 view -0 + 678 .cfi_startproc + 679 @ args = 4, pretend = 0, frame = 0 + 680 @ frame_needed = 0, uses_anonymous_args = 0 +6359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 681 .loc 1 6359 1 is_stmt 0 view .LVU208 + 682 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 683 .cfi_def_cfa_offset 24 + 684 .cfi_offset 4, -24 + 685 .cfi_offset 5, -20 + 686 .cfi_offset 6, -16 + 687 .cfi_offset 7, -12 + 688 .cfi_offset 8, -8 + 689 .cfi_offset 14, -4 + 690 0004 0646 mov r6, r0 + 691 0006 8846 mov r8, r1 + 692 0008 1746 mov r7, r2 + 693 000a 1D46 mov r5, r3 + ARM GAS /tmp/ccE2rRGE.s page 134 + + +6360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 694 .loc 1 6360 3 is_stmt 1 view .LVU209 + 695 .LVL48: + 696 .L63: +6360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 697 .loc 1 6360 41 view .LVU210 +6360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 698 .loc 1 6360 10 is_stmt 0 view .LVU211 + 699 000c 3468 ldr r4, [r6] + 700 000e A469 ldr r4, [r4, #24] + 701 0010 38EA0404 bics r4, r8, r4 + 702 0014 0CBF ite eq + 703 0016 0124 moveq r4, #1 + 704 0018 0024 movne r4, #0 +6360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 705 .loc 1 6360 41 view .LVU212 + 706 001a BC42 cmp r4, r7 + 707 001c 18D1 bne .L68 +6363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 708 .loc 1 6363 5 is_stmt 1 view .LVU213 +6363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 709 .loc 1 6363 8 is_stmt 0 view .LVU214 + 710 001e B5F1FF3F cmp r5, #-1 + 711 0022 F3D0 beq .L63 +6365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 712 .loc 1 6365 7 is_stmt 1 view .LVU215 +6365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 713 .loc 1 6365 13 is_stmt 0 view .LVU216 + 714 0024 FFF7FEFF bl HAL_GetTick + 715 .LVL49: +6365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 716 .loc 1 6365 27 view .LVU217 + 717 0028 069B ldr r3, [sp, #24] + 718 002a C01A subs r0, r0, r3 +6365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 719 .loc 1 6365 10 view .LVU218 + 720 002c A842 cmp r0, r5 + 721 002e 01D8 bhi .L64 +6365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 722 .loc 1 6365 51 discriminator 1 view .LVU219 + 723 0030 002D cmp r5, #0 + 724 0032 EBD1 bne .L63 + 725 .L64: +6367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 726 .loc 1 6367 9 is_stmt 1 view .LVU220 +6367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 727 .loc 1 6367 13 is_stmt 0 view .LVU221 + 728 0034 736C ldr r3, [r6, #68] +6367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 729 .loc 1 6367 25 view .LVU222 + 730 0036 43F02003 orr r3, r3, #32 + 731 003a 7364 str r3, [r6, #68] +6368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 732 .loc 1 6368 9 is_stmt 1 view .LVU223 +6368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 733 .loc 1 6368 21 is_stmt 0 view .LVU224 + 734 003c 2023 movs r3, #32 + ARM GAS /tmp/ccE2rRGE.s page 135 + + + 735 003e 86F84130 strb r3, [r6, #65] +6369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 736 .loc 1 6369 9 is_stmt 1 view .LVU225 +6369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 737 .loc 1 6369 20 is_stmt 0 view .LVU226 + 738 0042 0023 movs r3, #0 + 739 0044 86F84230 strb r3, [r6, #66] +6372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 740 .loc 1 6372 9 is_stmt 1 view .LVU227 +6372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 741 .loc 1 6372 9 view .LVU228 + 742 0048 86F84030 strb r3, [r6, #64] +6372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 743 .loc 1 6372 9 view .LVU229 +6373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 744 .loc 1 6373 9 view .LVU230 +6373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 745 .loc 1 6373 16 is_stmt 0 view .LVU231 + 746 004c 0120 movs r0, #1 + 747 004e 00E0 b .L65 + 748 .L68: +6377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 749 .loc 1 6377 10 view .LVU232 + 750 0050 0020 movs r0, #0 + 751 .L65: +6378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 752 .loc 1 6378 1 view .LVU233 + 753 0052 BDE8F081 pop {r4, r5, r6, r7, r8, pc} +6378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 754 .loc 1 6378 1 view .LVU234 + 755 .cfi_endproc + 756 .LFE200: + 758 .section .text.I2C_RequestMemoryWrite,"ax",%progbits + 759 .align 1 + 760 .syntax unified + 761 .thumb + 762 .thumb_func + 764 I2C_RequestMemoryWrite: + 765 .LVL50: + 766 .LFB183: +5308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 767 .loc 1 5308 1 is_stmt 1 view -0 + 768 .cfi_startproc + 769 @ args = 8, pretend = 0, frame = 0 + 770 @ frame_needed = 0, uses_anonymous_args = 0 +5308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 771 .loc 1 5308 1 is_stmt 0 view .LVU236 + 772 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 773 .cfi_def_cfa_offset 24 + 774 .cfi_offset 4, -24 + 775 .cfi_offset 5, -20 + 776 .cfi_offset 6, -16 + 777 .cfi_offset 7, -12 + 778 .cfi_offset 8, -8 + 779 .cfi_offset 14, -4 + 780 0004 82B0 sub sp, sp, #8 + 781 .cfi_def_cfa_offset 32 + ARM GAS /tmp/ccE2rRGE.s page 136 + + + 782 0006 0446 mov r4, r0 + 783 0008 9046 mov r8, r2 + 784 000a 1D46 mov r5, r3 + 785 000c 089E ldr r6, [sp, #32] + 786 000e 099F ldr r7, [sp, #36] +5309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 787 .loc 1 5309 3 is_stmt 1 view .LVU237 + 788 0010 194B ldr r3, .L78 + 789 .LVL51: +5309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 790 .loc 1 5309 3 is_stmt 0 view .LVU238 + 791 0012 0093 str r3, [sp] + 792 0014 4FF08073 mov r3, #16777216 + 793 0018 EAB2 uxtb r2, r5 + 794 .LVL52: +5309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 795 .loc 1 5309 3 view .LVU239 + 796 001a FFF7FEFF bl I2C_TransferConfig + 797 .LVL53: +5312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 798 .loc 1 5312 3 is_stmt 1 view .LVU240 +5312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 799 .loc 1 5312 7 is_stmt 0 view .LVU241 + 800 001e 3A46 mov r2, r7 + 801 0020 3146 mov r1, r6 + 802 0022 2046 mov r0, r4 + 803 0024 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 804 .LVL54: +5312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 805 .loc 1 5312 6 view .LVU242 + 806 0028 F8B9 cbnz r0, .L73 +5318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 807 .loc 1 5318 3 is_stmt 1 view .LVU243 +5318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 808 .loc 1 5318 6 is_stmt 0 view .LVU244 + 809 002a 012D cmp r5, #1 + 810 002c 0ED1 bne .L71 +5321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 811 .loc 1 5321 5 is_stmt 1 view .LVU245 +5321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 812 .loc 1 5321 9 is_stmt 0 view .LVU246 + 813 002e 2368 ldr r3, [r4] +5321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 814 .loc 1 5321 28 view .LVU247 + 815 0030 5FFA88F2 uxtb r2, r8 +5321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 816 .loc 1 5321 26 view .LVU248 + 817 0034 9A62 str r2, [r3, #40] + 818 .L72: +5340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 819 .loc 1 5340 3 is_stmt 1 view .LVU249 +5340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 820 .loc 1 5340 7 is_stmt 0 view .LVU250 + 821 0036 0097 str r7, [sp] + 822 0038 3346 mov r3, r6 + 823 003a 0022 movs r2, #0 + 824 003c 8021 movs r1, #128 + ARM GAS /tmp/ccE2rRGE.s page 137 + + + 825 003e 2046 mov r0, r4 + 826 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 827 .LVL55: +5340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 828 .loc 1 5340 6 view .LVU251 + 829 0044 A8B9 cbnz r0, .L77 + 830 .L70: +5346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 831 .loc 1 5346 1 view .LVU252 + 832 0046 02B0 add sp, sp, #8 + 833 .cfi_remember_state + 834 .cfi_def_cfa_offset 24 + 835 @ sp needed + 836 0048 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 837 .LVL56: + 838 .L71: + 839 .cfi_restore_state +5327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 840 .loc 1 5327 5 is_stmt 1 view .LVU253 +5327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 841 .loc 1 5327 9 is_stmt 0 view .LVU254 + 842 004c 2368 ldr r3, [r4] +5327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 843 .loc 1 5327 28 view .LVU255 + 844 004e 4FEA1822 lsr r2, r8, #8 +5327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 845 .loc 1 5327 26 view .LVU256 + 846 0052 9A62 str r2, [r3, #40] +5330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 847 .loc 1 5330 5 is_stmt 1 view .LVU257 +5330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 848 .loc 1 5330 9 is_stmt 0 view .LVU258 + 849 0054 3A46 mov r2, r7 + 850 0056 3146 mov r1, r6 + 851 0058 2046 mov r0, r4 + 852 005a FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 853 .LVL57: +5330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 854 .loc 1 5330 8 view .LVU259 + 855 005e 30B9 cbnz r0, .L74 +5336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 856 .loc 1 5336 5 is_stmt 1 view .LVU260 +5336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 857 .loc 1 5336 9 is_stmt 0 view .LVU261 + 858 0060 2368 ldr r3, [r4] +5336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 859 .loc 1 5336 28 view .LVU262 + 860 0062 5FFA88F2 uxtb r2, r8 +5336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 861 .loc 1 5336 26 view .LVU263 + 862 0066 9A62 str r2, [r3, #40] + 863 0068 E5E7 b .L72 + 864 .L73: +5314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 865 .loc 1 5314 12 view .LVU264 + 866 006a 0120 movs r0, #1 + 867 006c EBE7 b .L70 + ARM GAS /tmp/ccE2rRGE.s page 138 + + + 868 .L74: +5332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 869 .loc 1 5332 14 view .LVU265 + 870 006e 0120 movs r0, #1 + 871 0070 E9E7 b .L70 + 872 .L77: +5342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 873 .loc 1 5342 12 view .LVU266 + 874 0072 0120 movs r0, #1 + 875 0074 E7E7 b .L70 + 876 .L79: + 877 0076 00BF .align 2 + 878 .L78: + 879 0078 00200080 .word -2147475456 + 880 .cfi_endproc + 881 .LFE183: + 883 .section .text.I2C_RequestMemoryRead,"ax",%progbits + 884 .align 1 + 885 .syntax unified + 886 .thumb + 887 .thumb_func + 889 I2C_RequestMemoryRead: + 890 .LVL58: + 891 .LFB184: +5363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 892 .loc 1 5363 1 is_stmt 1 view -0 + 893 .cfi_startproc + 894 @ args = 8, pretend = 0, frame = 0 + 895 @ frame_needed = 0, uses_anonymous_args = 0 +5363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 896 .loc 1 5363 1 is_stmt 0 view .LVU268 + 897 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 898 .cfi_def_cfa_offset 24 + 899 .cfi_offset 4, -24 + 900 .cfi_offset 5, -20 + 901 .cfi_offset 6, -16 + 902 .cfi_offset 7, -12 + 903 .cfi_offset 8, -8 + 904 .cfi_offset 14, -4 + 905 0004 82B0 sub sp, sp, #8 + 906 .cfi_def_cfa_offset 32 + 907 0006 0446 mov r4, r0 + 908 0008 9046 mov r8, r2 + 909 000a 1D46 mov r5, r3 + 910 000c 089E ldr r6, [sp, #32] + 911 000e 099F ldr r7, [sp, #36] +5364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 912 .loc 1 5364 3 is_stmt 1 view .LVU269 + 913 0010 184B ldr r3, .L89 + 914 .LVL59: +5364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 915 .loc 1 5364 3 is_stmt 0 view .LVU270 + 916 0012 0093 str r3, [sp] + 917 0014 0023 movs r3, #0 + 918 0016 EAB2 uxtb r2, r5 + 919 .LVL60: +5364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 139 + + + 920 .loc 1 5364 3 view .LVU271 + 921 0018 FFF7FEFF bl I2C_TransferConfig + 922 .LVL61: +5367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 923 .loc 1 5367 3 is_stmt 1 view .LVU272 +5367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 924 .loc 1 5367 7 is_stmt 0 view .LVU273 + 925 001c 3A46 mov r2, r7 + 926 001e 3146 mov r1, r6 + 927 0020 2046 mov r0, r4 + 928 0022 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 929 .LVL62: +5367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 930 .loc 1 5367 6 view .LVU274 + 931 0026 F8B9 cbnz r0, .L84 +5373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 932 .loc 1 5373 3 is_stmt 1 view .LVU275 +5373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 933 .loc 1 5373 6 is_stmt 0 view .LVU276 + 934 0028 012D cmp r5, #1 + 935 002a 0ED1 bne .L82 +5376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 936 .loc 1 5376 5 is_stmt 1 view .LVU277 +5376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 937 .loc 1 5376 9 is_stmt 0 view .LVU278 + 938 002c 2368 ldr r3, [r4] +5376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 939 .loc 1 5376 28 view .LVU279 + 940 002e 5FFA88F2 uxtb r2, r8 +5376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 941 .loc 1 5376 26 view .LVU280 + 942 0032 9A62 str r2, [r3, #40] + 943 .L83: +5395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 944 .loc 1 5395 3 is_stmt 1 view .LVU281 +5395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 945 .loc 1 5395 7 is_stmt 0 view .LVU282 + 946 0034 0097 str r7, [sp] + 947 0036 3346 mov r3, r6 + 948 0038 0022 movs r2, #0 + 949 003a 4021 movs r1, #64 + 950 003c 2046 mov r0, r4 + 951 003e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 952 .LVL63: +5395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 953 .loc 1 5395 6 view .LVU283 + 954 0042 A8B9 cbnz r0, .L88 + 955 .L81: +5401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 956 .loc 1 5401 1 view .LVU284 + 957 0044 02B0 add sp, sp, #8 + 958 .cfi_remember_state + 959 .cfi_def_cfa_offset 24 + 960 @ sp needed + 961 0046 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 962 .LVL64: + 963 .L82: + ARM GAS /tmp/ccE2rRGE.s page 140 + + + 964 .cfi_restore_state +5382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 965 .loc 1 5382 5 is_stmt 1 view .LVU285 +5382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 966 .loc 1 5382 9 is_stmt 0 view .LVU286 + 967 004a 2368 ldr r3, [r4] +5382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 968 .loc 1 5382 28 view .LVU287 + 969 004c 4FEA1822 lsr r2, r8, #8 +5382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 970 .loc 1 5382 26 view .LVU288 + 971 0050 9A62 str r2, [r3, #40] +5385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 972 .loc 1 5385 5 is_stmt 1 view .LVU289 +5385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 973 .loc 1 5385 9 is_stmt 0 view .LVU290 + 974 0052 3A46 mov r2, r7 + 975 0054 3146 mov r1, r6 + 976 0056 2046 mov r0, r4 + 977 0058 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 978 .LVL65: +5385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 979 .loc 1 5385 8 view .LVU291 + 980 005c 30B9 cbnz r0, .L85 +5391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 981 .loc 1 5391 5 is_stmt 1 view .LVU292 +5391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 982 .loc 1 5391 9 is_stmt 0 view .LVU293 + 983 005e 2368 ldr r3, [r4] +5391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 984 .loc 1 5391 28 view .LVU294 + 985 0060 5FFA88F2 uxtb r2, r8 +5391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 986 .loc 1 5391 26 view .LVU295 + 987 0064 9A62 str r2, [r3, #40] + 988 0066 E5E7 b .L83 + 989 .L84: +5369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 990 .loc 1 5369 12 view .LVU296 + 991 0068 0120 movs r0, #1 + 992 006a EBE7 b .L81 + 993 .L85: +5387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 994 .loc 1 5387 14 view .LVU297 + 995 006c 0120 movs r0, #1 + 996 006e E9E7 b .L81 + 997 .L88: +5397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 998 .loc 1 5397 12 view .LVU298 + 999 0070 0120 movs r0, #1 + 1000 0072 E7E7 b .L81 + 1001 .L90: + 1002 .align 2 + 1003 .L89: + 1004 0074 00200080 .word -2147475456 + 1005 .cfi_endproc + 1006 .LFE184: + ARM GAS /tmp/ccE2rRGE.s page 141 + + + 1008 .section .text.I2C_WaitOnSTOPFlagUntilTimeout,"ax",%progbits + 1009 .align 1 + 1010 .syntax unified + 1011 .thumb + 1012 .thumb_func + 1014 I2C_WaitOnSTOPFlagUntilTimeout: + 1015 .LVL66: + 1016 .LFB202: +6428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 1017 .loc 1 6428 1 is_stmt 1 view -0 + 1018 .cfi_startproc + 1019 @ args = 0, pretend = 0, frame = 0 + 1020 @ frame_needed = 0, uses_anonymous_args = 0 +6428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 1021 .loc 1 6428 1 is_stmt 0 view .LVU300 + 1022 0000 70B5 push {r4, r5, r6, lr} + 1023 .cfi_def_cfa_offset 16 + 1024 .cfi_offset 4, -16 + 1025 .cfi_offset 5, -12 + 1026 .cfi_offset 6, -8 + 1027 .cfi_offset 14, -4 + 1028 0002 0546 mov r5, r0 + 1029 0004 0C46 mov r4, r1 + 1030 0006 1646 mov r6, r2 +6429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1031 .loc 1 6429 3 is_stmt 1 view .LVU301 + 1032 .LVL67: + 1033 .L92: +6429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1034 .loc 1 6429 51 view .LVU302 +6429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1035 .loc 1 6429 10 is_stmt 0 view .LVU303 + 1036 0008 2B68 ldr r3, [r5] + 1037 000a 9B69 ldr r3, [r3, #24] +6429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1038 .loc 1 6429 51 view .LVU304 + 1039 000c 13F0200F tst r3, #32 + 1040 0010 1AD1 bne .L98 +6432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1041 .loc 1 6432 5 is_stmt 1 view .LVU305 +6432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1042 .loc 1 6432 9 is_stmt 0 view .LVU306 + 1043 0012 3246 mov r2, r6 + 1044 0014 2146 mov r1, r4 + 1045 0016 2846 mov r0, r5 + 1046 0018 FFF7FEFF bl I2C_IsAcknowledgeFailed + 1047 .LVL68: +6432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1048 .loc 1 6432 8 view .LVU307 + 1049 001c B0B9 cbnz r0, .L96 +6438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1050 .loc 1 6438 5 is_stmt 1 view .LVU308 +6438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1051 .loc 1 6438 11 is_stmt 0 view .LVU309 + 1052 001e FFF7FEFF bl HAL_GetTick + 1053 .LVL69: +6438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 142 + + + 1054 .loc 1 6438 25 view .LVU310 + 1055 0022 801B subs r0, r0, r6 +6438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1056 .loc 1 6438 8 view .LVU311 + 1057 0024 A042 cmp r0, r4 + 1058 0026 01D8 bhi .L94 +6438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1059 .loc 1 6438 49 discriminator 1 view .LVU312 + 1060 0028 002C cmp r4, #0 + 1061 002a EDD1 bne .L92 + 1062 .L94: +6440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1063 .loc 1 6440 7 is_stmt 1 view .LVU313 +6440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1064 .loc 1 6440 11 is_stmt 0 view .LVU314 + 1065 002c 6B6C ldr r3, [r5, #68] +6440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1066 .loc 1 6440 23 view .LVU315 + 1067 002e 43F02003 orr r3, r3, #32 + 1068 0032 6B64 str r3, [r5, #68] +6441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1069 .loc 1 6441 7 is_stmt 1 view .LVU316 +6441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1070 .loc 1 6441 19 is_stmt 0 view .LVU317 + 1071 0034 2023 movs r3, #32 + 1072 0036 85F84130 strb r3, [r5, #65] +6442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1073 .loc 1 6442 7 is_stmt 1 view .LVU318 +6442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1074 .loc 1 6442 18 is_stmt 0 view .LVU319 + 1075 003a 0023 movs r3, #0 + 1076 003c 85F84230 strb r3, [r5, #66] +6445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1077 .loc 1 6445 7 is_stmt 1 view .LVU320 +6445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1078 .loc 1 6445 7 view .LVU321 + 1079 0040 85F84030 strb r3, [r5, #64] +6445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1080 .loc 1 6445 7 view .LVU322 +6447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1081 .loc 1 6447 7 view .LVU323 +6447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1082 .loc 1 6447 14 is_stmt 0 view .LVU324 + 1083 0044 0120 movs r0, #1 + 1084 .L93: +6451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1085 .loc 1 6451 1 view .LVU325 + 1086 0046 70BD pop {r4, r5, r6, pc} + 1087 .LVL70: + 1088 .L98: +6450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1089 .loc 1 6450 10 view .LVU326 + 1090 0048 0020 movs r0, #0 + 1091 004a FCE7 b .L93 + 1092 .L96: +6434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1093 .loc 1 6434 14 view .LVU327 + ARM GAS /tmp/ccE2rRGE.s page 143 + + + 1094 004c 0120 movs r0, #1 + 1095 004e FAE7 b .L93 + 1096 .cfi_endproc + 1097 .LFE202: + 1099 .section .text.I2C_WaitOnRXNEFlagUntilTimeout,"ax",%progbits + 1100 .align 1 + 1101 .syntax unified + 1102 .thumb + 1103 .thumb_func + 1105 I2C_WaitOnRXNEFlagUntilTimeout: + 1106 .LVL71: + 1107 .LFB203: +6463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 1108 .loc 1 6463 1 is_stmt 1 view -0 + 1109 .cfi_startproc + 1110 @ args = 0, pretend = 0, frame = 0 + 1111 @ frame_needed = 0, uses_anonymous_args = 0 +6463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 1112 .loc 1 6463 1 is_stmt 0 view .LVU329 + 1113 0000 70B5 push {r4, r5, r6, lr} + 1114 .cfi_def_cfa_offset 16 + 1115 .cfi_offset 4, -16 + 1116 .cfi_offset 5, -12 + 1117 .cfi_offset 6, -8 + 1118 .cfi_offset 14, -4 + 1119 0002 0446 mov r4, r0 + 1120 0004 0D46 mov r5, r1 + 1121 0006 1646 mov r6, r2 +6464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1122 .loc 1 6464 3 is_stmt 1 view .LVU330 + 1123 .LVL72: + 1124 .L100: +6464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1125 .loc 1 6464 50 view .LVU331 +6464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1126 .loc 1 6464 10 is_stmt 0 view .LVU332 + 1127 0008 2368 ldr r3, [r4] + 1128 000a 9B69 ldr r3, [r3, #24] +6464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1129 .loc 1 6464 50 view .LVU333 + 1130 000c 13F0040F tst r3, #4 + 1131 0010 3ED1 bne .L108 +6467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1132 .loc 1 6467 5 is_stmt 1 view .LVU334 +6467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1133 .loc 1 6467 9 is_stmt 0 view .LVU335 + 1134 0012 3246 mov r2, r6 + 1135 0014 2946 mov r1, r5 + 1136 0016 2046 mov r0, r4 + 1137 0018 FFF7FEFF bl I2C_IsAcknowledgeFailed + 1138 .LVL73: +6467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1139 .loc 1 6467 8 view .LVU336 + 1140 001c 0146 mov r1, r0 + 1141 001e 0028 cmp r0, #0 + 1142 0020 38D1 bne .L106 +6473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 144 + + + 1143 .loc 1 6473 5 is_stmt 1 view .LVU337 +6473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1144 .loc 1 6473 9 is_stmt 0 view .LVU338 + 1145 0022 2368 ldr r3, [r4] + 1146 0024 9A69 ldr r2, [r3, #24] +6473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1147 .loc 1 6473 8 view .LVU339 + 1148 0026 12F0200F tst r2, #32 + 1149 002a 13D1 bne .L109 +6503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1150 .loc 1 6503 5 is_stmt 1 view .LVU340 +6503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1151 .loc 1 6503 11 is_stmt 0 view .LVU341 + 1152 002c FFF7FEFF bl HAL_GetTick + 1153 .LVL74: +6503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1154 .loc 1 6503 25 view .LVU342 + 1155 0030 801B subs r0, r0, r6 +6503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1156 .loc 1 6503 8 view .LVU343 + 1157 0032 A842 cmp r0, r5 + 1158 0034 01D8 bhi .L104 +6503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1159 .loc 1 6503 49 discriminator 1 view .LVU344 + 1160 0036 002D cmp r5, #0 + 1161 0038 E6D1 bne .L100 + 1162 .L104: +6505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1163 .loc 1 6505 7 is_stmt 1 view .LVU345 +6505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1164 .loc 1 6505 11 is_stmt 0 view .LVU346 + 1165 003a 636C ldr r3, [r4, #68] +6505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1166 .loc 1 6505 23 view .LVU347 + 1167 003c 43F02003 orr r3, r3, #32 + 1168 0040 6364 str r3, [r4, #68] +6506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1169 .loc 1 6506 7 is_stmt 1 view .LVU348 +6506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1170 .loc 1 6506 19 is_stmt 0 view .LVU349 + 1171 0042 2023 movs r3, #32 + 1172 0044 84F84130 strb r3, [r4, #65] +6509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1173 .loc 1 6509 7 is_stmt 1 view .LVU350 +6509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1174 .loc 1 6509 7 view .LVU351 + 1175 0048 0023 movs r3, #0 + 1176 004a 84F84030 strb r3, [r4, #64] +6509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1177 .loc 1 6509 7 view .LVU352 +6511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1178 .loc 1 6511 7 view .LVU353 +6511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1179 .loc 1 6511 14 is_stmt 0 view .LVU354 + 1180 004e 0121 movs r1, #1 + 1181 .L101: +6515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 145 + + + 1182 .loc 1 6515 1 view .LVU355 + 1183 0050 0846 mov r0, r1 + 1184 0052 70BD pop {r4, r5, r6, pc} + 1185 .LVL75: + 1186 .L109: +6477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1187 .loc 1 6477 7 is_stmt 1 view .LVU356 +6477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1188 .loc 1 6477 12 is_stmt 0 view .LVU357 + 1189 0054 9A69 ldr r2, [r3, #24] +6477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1190 .loc 1 6477 10 view .LVU358 + 1191 0056 12F0040F tst r2, #4 + 1192 005a 02D0 beq .L103 +6477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1193 .loc 1 6477 68 discriminator 1 view .LVU359 + 1194 005c 228D ldrh r2, [r4, #40] +6477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1195 .loc 1 6477 60 discriminator 1 view .LVU360 + 1196 005e 002A cmp r2, #0 + 1197 0060 F6D1 bne .L101 + 1198 .L103: +6486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1199 .loc 1 6486 9 is_stmt 1 view .LVU361 + 1200 0062 2022 movs r2, #32 + 1201 0064 DA61 str r2, [r3, #28] +6489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1202 .loc 1 6489 9 view .LVU362 + 1203 0066 2168 ldr r1, [r4] + 1204 0068 4B68 ldr r3, [r1, #4] + 1205 006a 23F0FF73 bic r3, r3, #33423360 + 1206 006e 23F48B33 bic r3, r3, #71168 + 1207 0072 23F4FF73 bic r3, r3, #510 + 1208 0076 23F00103 bic r3, r3, #1 + 1209 007a 4B60 str r3, [r1, #4] +6491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1210 .loc 1 6491 9 view .LVU363 +6491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1211 .loc 1 6491 25 is_stmt 0 view .LVU364 + 1212 007c 0023 movs r3, #0 + 1213 007e 6364 str r3, [r4, #68] +6492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1214 .loc 1 6492 9 is_stmt 1 view .LVU365 +6492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1215 .loc 1 6492 21 is_stmt 0 view .LVU366 + 1216 0080 84F84120 strb r2, [r4, #65] +6493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1217 .loc 1 6493 9 is_stmt 1 view .LVU367 +6493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1218 .loc 1 6493 20 is_stmt 0 view .LVU368 + 1219 0084 84F84230 strb r3, [r4, #66] +6496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1220 .loc 1 6496 9 is_stmt 1 view .LVU369 +6496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1221 .loc 1 6496 9 view .LVU370 + 1222 0088 84F84030 strb r3, [r4, #64] +6496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 146 + + + 1223 .loc 1 6496 9 view .LVU371 +6498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1224 .loc 1 6498 9 view .LVU372 +6498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1225 .loc 1 6498 16 is_stmt 0 view .LVU373 + 1226 008c 0121 movs r1, #1 + 1227 008e DFE7 b .L101 + 1228 .L108: +6514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1229 .loc 1 6514 10 view .LVU374 + 1230 0090 0021 movs r1, #0 + 1231 0092 DDE7 b .L101 + 1232 .L106: +6469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1233 .loc 1 6469 14 view .LVU375 + 1234 0094 0121 movs r1, #1 + 1235 0096 DBE7 b .L101 + 1236 .cfi_endproc + 1237 .LFE203: + 1239 .section .text.HAL_I2C_MspInit,"ax",%progbits + 1240 .align 1 + 1241 .weak HAL_I2C_MspInit + 1242 .syntax unified + 1243 .thumb + 1244 .thumb_func + 1246 HAL_I2C_MspInit: + 1247 .LVL76: + 1248 .LFB132: + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1249 .loc 1 679 1 is_stmt 1 view -0 + 1250 .cfi_startproc + 1251 @ args = 0, pretend = 0, frame = 0 + 1252 @ frame_needed = 0, uses_anonymous_args = 0 + 1253 @ link register save eliminated. + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1254 .loc 1 681 3 view .LVU377 + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1255 .loc 1 686 1 is_stmt 0 view .LVU378 + 1256 0000 7047 bx lr + 1257 .cfi_endproc + 1258 .LFE132: + 1260 .section .text.HAL_I2C_Init,"ax",%progbits + 1261 .align 1 + 1262 .global HAL_I2C_Init + 1263 .syntax unified + 1264 .thumb + 1265 .thumb_func + 1267 HAL_I2C_Init: + 1268 .LVL77: + 1269 .LFB130: + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1270 .loc 1 523 1 is_stmt 1 view -0 + 1271 .cfi_startproc + 1272 @ args = 0, pretend = 0, frame = 0 + 1273 @ frame_needed = 0, uses_anonymous_args = 0 + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1274 .loc 1 525 3 view .LVU380 + ARM GAS /tmp/ccE2rRGE.s page 147 + + + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1275 .loc 1 525 6 is_stmt 0 view .LVU381 + 1276 0000 0028 cmp r0, #0 + 1277 0002 59D0 beq .L117 + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1278 .loc 1 523 1 view .LVU382 + 1279 0004 10B5 push {r4, lr} + 1280 .cfi_def_cfa_offset 8 + 1281 .cfi_offset 4, -8 + 1282 .cfi_offset 14, -4 + 1283 0006 0446 mov r4, r0 + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 1284 .loc 1 531 3 is_stmt 1 view .LVU383 + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 1285 .loc 1 532 3 view .LVU384 + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 1286 .loc 1 533 3 view .LVU385 + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 1287 .loc 1 534 3 view .LVU386 + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 1288 .loc 1 535 3 view .LVU387 + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 1289 .loc 1 536 3 view .LVU388 + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 1290 .loc 1 537 3 view .LVU389 + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1291 .loc 1 538 3 view .LVU390 + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1292 .loc 1 540 3 view .LVU391 + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1293 .loc 1 540 11 is_stmt 0 view .LVU392 + 1294 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1295 .loc 1 540 6 view .LVU393 + 1296 000c 002B cmp r3, #0 + 1297 000e 43D0 beq .L122 + 1298 .LVL78: + 1299 .L113: + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1300 .loc 1 571 3 is_stmt 1 view .LVU394 + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1301 .loc 1 571 15 is_stmt 0 view .LVU395 + 1302 0010 2423 movs r3, #36 + 1303 0012 84F84130 strb r3, [r4, #65] + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1304 .loc 1 574 3 is_stmt 1 view .LVU396 + 1305 0016 2268 ldr r2, [r4] + 1306 0018 1368 ldr r3, [r2] + 1307 001a 23F00103 bic r3, r3, #1 + 1308 001e 1360 str r3, [r2] + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1309 .loc 1 578 3 view .LVU397 + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1310 .loc 1 578 39 is_stmt 0 view .LVU398 + 1311 0020 6368 ldr r3, [r4, #4] + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1312 .loc 1 578 7 view .LVU399 + ARM GAS /tmp/ccE2rRGE.s page 148 + + + 1313 0022 2268 ldr r2, [r4] + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1314 .loc 1 578 47 view .LVU400 + 1315 0024 23F07063 bic r3, r3, #251658240 + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1316 .loc 1 578 27 view .LVU401 + 1317 0028 1361 str r3, [r2, #16] + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1318 .loc 1 582 3 is_stmt 1 view .LVU402 + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1319 .loc 1 582 7 is_stmt 0 view .LVU403 + 1320 002a 2268 ldr r2, [r4] + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1321 .loc 1 582 17 view .LVU404 + 1322 002c 9368 ldr r3, [r2, #8] + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1323 .loc 1 582 24 view .LVU405 + 1324 002e 23F40043 bic r3, r3, #32768 + 1325 0032 9360 str r3, [r2, #8] + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1326 .loc 1 585 3 is_stmt 1 view .LVU406 + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1327 .loc 1 585 17 is_stmt 0 view .LVU407 + 1328 0034 E368 ldr r3, [r4, #12] + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1329 .loc 1 585 6 view .LVU408 + 1330 0036 012B cmp r3, #1 + 1331 0038 33D0 beq .L123 + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1332 .loc 1 591 5 is_stmt 1 view .LVU409 + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1333 .loc 1 591 75 is_stmt 0 view .LVU410 + 1334 003a A368 ldr r3, [r4, #8] + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1335 .loc 1 591 9 view .LVU411 + 1336 003c 2268 ldr r2, [r4] + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1337 .loc 1 591 63 view .LVU412 + 1338 003e 43F40443 orr r3, r3, #33792 + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1339 .loc 1 591 26 view .LVU413 + 1340 0042 9360 str r3, [r2, #8] + 1341 .L115: + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1342 .loc 1 596 3 is_stmt 1 view .LVU414 + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1343 .loc 1 596 17 is_stmt 0 view .LVU415 + 1344 0044 E368 ldr r3, [r4, #12] + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1345 .loc 1 596 6 view .LVU416 + 1346 0046 022B cmp r3, #2 + 1347 0048 31D0 beq .L124 + 1348 .L116: + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1349 .loc 1 601 3 is_stmt 1 view .LVU417 + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1350 .loc 1 601 7 is_stmt 0 view .LVU418 + ARM GAS /tmp/ccE2rRGE.s page 149 + + + 1351 004a 2268 ldr r2, [r4] + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1352 .loc 1 601 17 view .LVU419 + 1353 004c 5368 ldr r3, [r2, #4] + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1354 .loc 1 601 23 view .LVU420 + 1355 004e 43F00073 orr r3, r3, #33554432 + 1356 0052 43F40043 orr r3, r3, #32768 + 1357 0056 5360 str r3, [r2, #4] + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1358 .loc 1 605 3 is_stmt 1 view .LVU421 + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1359 .loc 1 605 7 is_stmt 0 view .LVU422 + 1360 0058 2268 ldr r2, [r4] + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1361 .loc 1 605 17 view .LVU423 + 1362 005a D368 ldr r3, [r2, #12] + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1363 .loc 1 605 24 view .LVU424 + 1364 005c 23F40043 bic r3, r3, #32768 + 1365 0060 D360 str r3, [r2, #12] + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1366 .loc 1 608 3 is_stmt 1 view .LVU425 + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1367 .loc 1 608 37 is_stmt 0 view .LVU426 + 1368 0062 2369 ldr r3, [r4, #16] + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1369 .loc 1 608 66 view .LVU427 + 1370 0064 6269 ldr r2, [r4, #20] + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1371 .loc 1 608 54 view .LVU428 + 1372 0066 1343 orrs r3, r3, r2 + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1373 .loc 1 609 38 view .LVU429 + 1374 0068 A169 ldr r1, [r4, #24] + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1375 .loc 1 608 7 view .LVU430 + 1376 006a 2268 ldr r2, [r4] + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1377 .loc 1 608 79 view .LVU431 + 1378 006c 43EA0123 orr r3, r3, r1, lsl #8 + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1379 .loc 1 608 24 view .LVU432 + 1380 0070 D360 str r3, [r2, #12] + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1381 .loc 1 613 3 is_stmt 1 view .LVU433 + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1382 .loc 1 613 36 is_stmt 0 view .LVU434 + 1383 0072 E369 ldr r3, [r4, #28] + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1384 .loc 1 613 65 view .LVU435 + 1385 0074 216A ldr r1, [r4, #32] + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1386 .loc 1 613 7 view .LVU436 + 1387 0076 2268 ldr r2, [r4] + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1388 .loc 1 613 53 view .LVU437 + ARM GAS /tmp/ccE2rRGE.s page 150 + + + 1389 0078 0B43 orrs r3, r3, r1 + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1390 .loc 1 613 23 view .LVU438 + 1391 007a 1360 str r3, [r2] + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1392 .loc 1 616 3 is_stmt 1 view .LVU439 + 1393 007c 2268 ldr r2, [r4] + 1394 007e 1368 ldr r3, [r2] + 1395 0080 43F00103 orr r3, r3, #1 + 1396 0084 1360 str r3, [r2] + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1397 .loc 1 618 3 view .LVU440 + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1398 .loc 1 618 19 is_stmt 0 view .LVU441 + 1399 0086 0020 movs r0, #0 + 1400 0088 6064 str r0, [r4, #68] + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1401 .loc 1 619 3 is_stmt 1 view .LVU442 + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1402 .loc 1 619 15 is_stmt 0 view .LVU443 + 1403 008a 2023 movs r3, #32 + 1404 008c 84F84130 strb r3, [r4, #65] + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1405 .loc 1 620 3 is_stmt 1 view .LVU444 + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1406 .loc 1 620 23 is_stmt 0 view .LVU445 + 1407 0090 2063 str r0, [r4, #48] + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1408 .loc 1 621 3 is_stmt 1 view .LVU446 + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1409 .loc 1 621 14 is_stmt 0 view .LVU447 + 1410 0092 84F84200 strb r0, [r4, #66] + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1411 .loc 1 623 3 is_stmt 1 view .LVU448 + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1412 .loc 1 624 1 is_stmt 0 view .LVU449 + 1413 0096 10BD pop {r4, pc} + 1414 .LVL79: + 1415 .L122: + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1416 .loc 1 543 5 is_stmt 1 view .LVU450 + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1417 .loc 1 543 16 is_stmt 0 view .LVU451 + 1418 0098 80F84030 strb r3, [r0, #64] + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1419 .loc 1 567 5 is_stmt 1 view .LVU452 + 1420 009c FFF7FEFF bl HAL_I2C_MspInit + 1421 .LVL80: + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1422 .loc 1 567 5 is_stmt 0 view .LVU453 + 1423 00a0 B6E7 b .L113 + 1424 .L123: + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1425 .loc 1 587 5 is_stmt 1 view .LVU454 + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1426 .loc 1 587 56 is_stmt 0 view .LVU455 + 1427 00a2 A368 ldr r3, [r4, #8] + ARM GAS /tmp/ccE2rRGE.s page 151 + + + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1428 .loc 1 587 9 view .LVU456 + 1429 00a4 2268 ldr r2, [r4] + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1430 .loc 1 587 44 view .LVU457 + 1431 00a6 43F40043 orr r3, r3, #32768 + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1432 .loc 1 587 26 view .LVU458 + 1433 00aa 9360 str r3, [r2, #8] + 1434 00ac CAE7 b .L115 + 1435 .L124: + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1436 .loc 1 598 5 is_stmt 1 view .LVU459 + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1437 .loc 1 598 9 is_stmt 0 view .LVU460 + 1438 00ae 2368 ldr r3, [r4] + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1439 .loc 1 598 25 view .LVU461 + 1440 00b0 4FF40062 mov r2, #2048 + 1441 00b4 5A60 str r2, [r3, #4] + 1442 00b6 C8E7 b .L116 + 1443 .LVL81: + 1444 .L117: + 1445 .cfi_def_cfa_offset 0 + 1446 .cfi_restore 4 + 1447 .cfi_restore 14 + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1448 .loc 1 527 12 view .LVU462 + 1449 00b8 0120 movs r0, #1 + 1450 .LVL82: + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1451 .loc 1 624 1 view .LVU463 + 1452 00ba 7047 bx lr + 1453 .cfi_endproc + 1454 .LFE130: + 1456 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 1457 .align 1 + 1458 .weak HAL_I2C_MspDeInit + 1459 .syntax unified + 1460 .thumb + 1461 .thumb_func + 1463 HAL_I2C_MspDeInit: + 1464 .LVL83: + 1465 .LFB133: + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1466 .loc 1 695 1 is_stmt 1 view -0 + 1467 .cfi_startproc + 1468 @ args = 0, pretend = 0, frame = 0 + 1469 @ frame_needed = 0, uses_anonymous_args = 0 + 1470 @ link register save eliminated. + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1471 .loc 1 697 3 view .LVU465 + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1472 .loc 1 702 1 is_stmt 0 view .LVU466 + 1473 0000 7047 bx lr + 1474 .cfi_endproc + 1475 .LFE133: + ARM GAS /tmp/ccE2rRGE.s page 152 + + + 1477 .section .text.HAL_I2C_DeInit,"ax",%progbits + 1478 .align 1 + 1479 .global HAL_I2C_DeInit + 1480 .syntax unified + 1481 .thumb + 1482 .thumb_func + 1484 HAL_I2C_DeInit: + 1485 .LVL84: + 1486 .LFB131: + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1487 .loc 1 633 1 is_stmt 1 view -0 + 1488 .cfi_startproc + 1489 @ args = 0, pretend = 0, frame = 0 + 1490 @ frame_needed = 0, uses_anonymous_args = 0 + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1491 .loc 1 635 3 view .LVU468 + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1492 .loc 1 635 6 is_stmt 0 view .LVU469 + 1493 0000 A8B1 cbz r0, .L128 + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1494 .loc 1 633 1 view .LVU470 + 1495 0002 10B5 push {r4, lr} + 1496 .cfi_def_cfa_offset 8 + 1497 .cfi_offset 4, -8 + 1498 .cfi_offset 14, -4 + 1499 0004 0446 mov r4, r0 + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1500 .loc 1 641 3 is_stmt 1 view .LVU471 + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1501 .loc 1 643 3 view .LVU472 + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1502 .loc 1 643 15 is_stmt 0 view .LVU473 + 1503 0006 2423 movs r3, #36 + 1504 0008 80F84130 strb r3, [r0, #65] + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1505 .loc 1 646 3 is_stmt 1 view .LVU474 + 1506 000c 0268 ldr r2, [r0] + 1507 000e 1368 ldr r3, [r2] + 1508 0010 23F00103 bic r3, r3, #1 + 1509 0014 1360 str r3, [r2] + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1510 .loc 1 658 3 view .LVU475 + 1511 0016 FFF7FEFF bl HAL_I2C_MspDeInit + 1512 .LVL85: + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1513 .loc 1 661 3 view .LVU476 + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1514 .loc 1 661 19 is_stmt 0 view .LVU477 + 1515 001a 0020 movs r0, #0 + 1516 001c 6064 str r0, [r4, #68] + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1517 .loc 1 662 3 is_stmt 1 view .LVU478 + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1518 .loc 1 662 15 is_stmt 0 view .LVU479 + 1519 001e 84F84100 strb r0, [r4, #65] + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1520 .loc 1 663 3 is_stmt 1 view .LVU480 + ARM GAS /tmp/ccE2rRGE.s page 153 + + + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1521 .loc 1 663 23 is_stmt 0 view .LVU481 + 1522 0022 2063 str r0, [r4, #48] + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1523 .loc 1 664 3 is_stmt 1 view .LVU482 + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1524 .loc 1 664 14 is_stmt 0 view .LVU483 + 1525 0024 84F84200 strb r0, [r4, #66] + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1526 .loc 1 667 3 is_stmt 1 view .LVU484 + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1527 .loc 1 667 3 view .LVU485 + 1528 0028 84F84000 strb r0, [r4, #64] + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1529 .loc 1 667 3 view .LVU486 + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1530 .loc 1 669 3 view .LVU487 + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1531 .loc 1 670 1 is_stmt 0 view .LVU488 + 1532 002c 10BD pop {r4, pc} + 1533 .LVL86: + 1534 .L128: + 1535 .cfi_def_cfa_offset 0 + 1536 .cfi_restore 4 + 1537 .cfi_restore 14 + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1538 .loc 1 637 12 view .LVU489 + 1539 002e 0120 movs r0, #1 + 1540 .LVL87: + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1541 .loc 1 670 1 view .LVU490 + 1542 0030 7047 bx lr + 1543 .cfi_endproc + 1544 .LFE131: + 1546 .section .text.HAL_I2C_Master_Transmit,"ax",%progbits + 1547 .align 1 + 1548 .global HAL_I2C_Master_Transmit + 1549 .syntax unified + 1550 .thumb + 1551 .thumb_func + 1553 HAL_I2C_Master_Transmit: + 1554 .LVL88: + 1555 .LFB134: +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 1556 .loc 1 1117 1 is_stmt 1 view -0 + 1557 .cfi_startproc + 1558 @ args = 4, pretend = 0, frame = 0 + 1559 @ frame_needed = 0, uses_anonymous_args = 0 +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 1560 .loc 1 1117 1 is_stmt 0 view .LVU492 + 1561 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 1562 .cfi_def_cfa_offset 32 + 1563 .cfi_offset 4, -32 + 1564 .cfi_offset 5, -28 + 1565 .cfi_offset 6, -24 + 1566 .cfi_offset 7, -20 + 1567 .cfi_offset 8, -16 + ARM GAS /tmp/ccE2rRGE.s page 154 + + + 1568 .cfi_offset 9, -12 + 1569 .cfi_offset 10, -8 + 1570 .cfi_offset 14, -4 + 1571 0004 82B0 sub sp, sp, #8 + 1572 .cfi_def_cfa_offset 40 + 1573 0006 0F46 mov r7, r1 + 1574 0008 0A9E ldr r6, [sp, #40] +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1575 .loc 1 1118 3 is_stmt 1 view .LVU493 +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1576 .loc 1 1120 3 view .LVU494 +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1577 .loc 1 1120 11 is_stmt 0 view .LVU495 + 1578 000a 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 1579 .LVL89: +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1580 .loc 1 1120 11 view .LVU496 + 1581 000e C9B2 uxtb r1, r1 +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1582 .loc 1 1120 6 view .LVU497 + 1583 0010 2029 cmp r1, #32 + 1584 0012 40F0A380 bne .L141 + 1585 0016 0446 mov r4, r0 + 1586 0018 9046 mov r8, r2 + 1587 001a 9946 mov r9, r3 +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1588 .loc 1 1123 5 is_stmt 1 view .LVU498 +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1589 .loc 1 1123 5 view .LVU499 + 1590 001c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 1591 .LVL90: +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1592 .loc 1 1123 5 is_stmt 0 view .LVU500 + 1593 0020 012B cmp r3, #1 + 1594 0022 00F09F80 beq .L142 +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1595 .loc 1 1123 5 is_stmt 1 discriminator 2 view .LVU501 + 1596 0026 4FF0010A mov r10, #1 + 1597 002a 80F840A0 strb r10, [r0, #64] +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1598 .loc 1 1123 5 discriminator 2 view .LVU502 +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1599 .loc 1 1126 5 discriminator 2 view .LVU503 +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1600 .loc 1 1126 17 is_stmt 0 discriminator 2 view .LVU504 + 1601 002e FFF7FEFF bl HAL_GetTick + 1602 .LVL91: +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1603 .loc 1 1126 17 discriminator 2 view .LVU505 + 1604 0032 0546 mov r5, r0 + 1605 .LVL92: +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1606 .loc 1 1128 5 is_stmt 1 discriminator 2 view .LVU506 +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1607 .loc 1 1128 9 is_stmt 0 discriminator 2 view .LVU507 + 1608 0034 0090 str r0, [sp] + 1609 0036 1923 movs r3, #25 + ARM GAS /tmp/ccE2rRGE.s page 155 + + + 1610 0038 5246 mov r2, r10 + 1611 003a 4FF40041 mov r1, #32768 + 1612 003e 2046 mov r0, r4 + 1613 .LVL93: +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1614 .loc 1 1128 9 discriminator 2 view .LVU508 + 1615 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1616 .LVL94: +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1617 .loc 1 1128 8 discriminator 2 view .LVU509 + 1618 0044 0028 cmp r0, #0 + 1619 0046 40F08F80 bne .L143 +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1620 .loc 1 1133 5 is_stmt 1 view .LVU510 +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1621 .loc 1 1133 21 is_stmt 0 view .LVU511 + 1622 004a 2123 movs r3, #33 + 1623 004c 84F84130 strb r3, [r4, #65] +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1624 .loc 1 1134 5 is_stmt 1 view .LVU512 +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1625 .loc 1 1134 21 is_stmt 0 view .LVU513 + 1626 0050 1023 movs r3, #16 + 1627 0052 84F84230 strb r3, [r4, #66] +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1628 .loc 1 1135 5 is_stmt 1 view .LVU514 +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1629 .loc 1 1135 21 is_stmt 0 view .LVU515 + 1630 0056 0023 movs r3, #0 + 1631 0058 6364 str r3, [r4, #68] +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 1632 .loc 1 1138 5 is_stmt 1 view .LVU516 +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 1633 .loc 1 1138 21 is_stmt 0 view .LVU517 + 1634 005a C4F82480 str r8, [r4, #36] +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1635 .loc 1 1139 5 is_stmt 1 view .LVU518 +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1636 .loc 1 1139 21 is_stmt 0 view .LVU519 + 1637 005e A4F82A90 strh r9, [r4, #42] @ movhi +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1638 .loc 1 1140 5 is_stmt 1 view .LVU520 +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1639 .loc 1 1140 21 is_stmt 0 view .LVU521 + 1640 0062 6363 str r3, [r4, #52] +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1641 .loc 1 1144 5 is_stmt 1 view .LVU522 +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1642 .loc 1 1144 13 is_stmt 0 view .LVU523 + 1643 0064 638D ldrh r3, [r4, #42] + 1644 0066 9BB2 uxth r3, r3 +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1645 .loc 1 1144 8 view .LVU524 + 1646 0068 FF2B cmp r3, #255 + 1647 006a 0AD9 bls .L135 +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1648 .loc 1 1146 7 is_stmt 1 view .LVU525 + ARM GAS /tmp/ccE2rRGE.s page 156 + + +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1649 .loc 1 1146 22 is_stmt 0 view .LVU526 + 1650 006c FF22 movs r2, #255 + 1651 006e 2285 strh r2, [r4, #40] @ movhi +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 1652 .loc 1 1147 7 is_stmt 1 view .LVU527 + 1653 0070 414B ldr r3, .L149 + 1654 0072 0093 str r3, [sp] + 1655 0074 4FF08073 mov r3, #16777216 + 1656 0078 3946 mov r1, r7 + 1657 007a 2046 mov r0, r4 + 1658 007c FFF7FEFF bl I2C_TransferConfig + 1659 .LVL95: + 1660 0080 18E0 b .L137 + 1661 .L135: +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1662 .loc 1 1152 7 view .LVU528 +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1663 .loc 1 1152 28 is_stmt 0 view .LVU529 + 1664 0082 628D ldrh r2, [r4, #42] + 1665 0084 92B2 uxth r2, r2 +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1666 .loc 1 1152 22 view .LVU530 + 1667 0086 2285 strh r2, [r4, #40] @ movhi +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 1668 .loc 1 1153 7 is_stmt 1 view .LVU531 + 1669 0088 3B4B ldr r3, .L149 + 1670 008a 0093 str r3, [sp] + 1671 008c 4FF00073 mov r3, #33554432 + 1672 0090 D2B2 uxtb r2, r2 + 1673 0092 3946 mov r1, r7 + 1674 0094 2046 mov r0, r4 + 1675 0096 FFF7FEFF bl I2C_TransferConfig + 1676 .LVL96: + 1677 009a 0BE0 b .L137 + 1678 .L139: +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1679 .loc 1 1189 11 view .LVU532 +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1680 .loc 1 1189 32 is_stmt 0 view .LVU533 + 1681 009c 628D ldrh r2, [r4, #42] + 1682 009e 92B2 uxth r2, r2 +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1683 .loc 1 1189 26 view .LVU534 + 1684 00a0 2285 strh r2, [r4, #40] @ movhi +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 1685 .loc 1 1190 11 is_stmt 1 view .LVU535 + 1686 00a2 0023 movs r3, #0 + 1687 00a4 0093 str r3, [sp] + 1688 00a6 4FF00073 mov r3, #33554432 + 1689 00aa D2B2 uxtb r2, r2 + 1690 00ac 3946 mov r1, r7 + 1691 00ae 2046 mov r0, r4 + 1692 00b0 FFF7FEFF bl I2C_TransferConfig + 1693 .LVL97: + 1694 .L137: +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 157 + + + 1695 .loc 1 1157 28 view .LVU536 +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1696 .loc 1 1157 16 is_stmt 0 view .LVU537 + 1697 00b4 638D ldrh r3, [r4, #42] + 1698 00b6 9BB2 uxth r3, r3 +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1699 .loc 1 1157 28 view .LVU538 + 1700 00b8 002B cmp r3, #0 + 1701 00ba 33D0 beq .L148 +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1702 .loc 1 1160 7 is_stmt 1 view .LVU539 +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1703 .loc 1 1160 11 is_stmt 0 view .LVU540 + 1704 00bc 2A46 mov r2, r5 + 1705 00be 3146 mov r1, r6 + 1706 00c0 2046 mov r0, r4 + 1707 00c2 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1708 .LVL98: +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1709 .loc 1 1160 10 view .LVU541 + 1710 00c6 0028 cmp r0, #0 + 1711 00c8 50D1 bne .L144 +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1712 .loc 1 1165 7 is_stmt 1 view .LVU542 +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1713 .loc 1 1165 35 is_stmt 0 view .LVU543 + 1714 00ca 626A ldr r2, [r4, #36] +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1715 .loc 1 1165 11 view .LVU544 + 1716 00cc 2368 ldr r3, [r4] +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1717 .loc 1 1165 30 view .LVU545 + 1718 00ce 1278 ldrb r2, [r2] @ zero_extendqisi2 +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1719 .loc 1 1165 28 view .LVU546 + 1720 00d0 9A62 str r2, [r3, #40] +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1721 .loc 1 1168 7 is_stmt 1 view .LVU547 +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1722 .loc 1 1168 11 is_stmt 0 view .LVU548 + 1723 00d2 636A ldr r3, [r4, #36] +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1724 .loc 1 1168 21 view .LVU549 + 1725 00d4 0133 adds r3, r3, #1 + 1726 00d6 6362 str r3, [r4, #36] +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 1727 .loc 1 1170 7 is_stmt 1 view .LVU550 +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 1728 .loc 1 1170 11 is_stmt 0 view .LVU551 + 1729 00d8 638D ldrh r3, [r4, #42] + 1730 00da 9BB2 uxth r3, r3 +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 1731 .loc 1 1170 22 view .LVU552 + 1732 00dc 013B subs r3, r3, #1 + 1733 00de 9BB2 uxth r3, r3 + 1734 00e0 6385 strh r3, [r4, #42] @ movhi +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 158 + + + 1735 .loc 1 1171 7 is_stmt 1 view .LVU553 +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1736 .loc 1 1171 11 is_stmt 0 view .LVU554 + 1737 00e2 238D ldrh r3, [r4, #40] +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1738 .loc 1 1171 21 view .LVU555 + 1739 00e4 013B subs r3, r3, #1 + 1740 00e6 9BB2 uxth r3, r3 + 1741 00e8 2385 strh r3, [r4, #40] @ movhi +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1742 .loc 1 1173 7 is_stmt 1 view .LVU556 +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1743 .loc 1 1173 16 is_stmt 0 view .LVU557 + 1744 00ea 628D ldrh r2, [r4, #42] + 1745 00ec 92B2 uxth r2, r2 +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1746 .loc 1 1173 10 view .LVU558 + 1747 00ee 002A cmp r2, #0 + 1748 00f0 E0D0 beq .L137 +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1749 .loc 1 1173 35 discriminator 1 view .LVU559 + 1750 00f2 002B cmp r3, #0 + 1751 00f4 DED1 bne .L137 +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1752 .loc 1 1176 9 is_stmt 1 view .LVU560 +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1753 .loc 1 1176 13 is_stmt 0 view .LVU561 + 1754 00f6 0095 str r5, [sp] + 1755 00f8 3346 mov r3, r6 + 1756 00fa 0022 movs r2, #0 + 1757 00fc 8021 movs r1, #128 + 1758 00fe 2046 mov r0, r4 + 1759 0100 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1760 .LVL99: +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1761 .loc 1 1176 12 view .LVU562 + 1762 0104 A0BB cbnz r0, .L145 +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1763 .loc 1 1181 9 is_stmt 1 view .LVU563 +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1764 .loc 1 1181 17 is_stmt 0 view .LVU564 + 1765 0106 638D ldrh r3, [r4, #42] + 1766 0108 9BB2 uxth r3, r3 +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1767 .loc 1 1181 12 view .LVU565 + 1768 010a FF2B cmp r3, #255 + 1769 010c C6D9 bls .L139 +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1770 .loc 1 1183 11 is_stmt 1 view .LVU566 +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1771 .loc 1 1183 26 is_stmt 0 view .LVU567 + 1772 010e FF22 movs r2, #255 + 1773 0110 2285 strh r2, [r4, #40] @ movhi +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 1774 .loc 1 1184 11 is_stmt 1 view .LVU568 + 1775 0112 0023 movs r3, #0 + 1776 0114 0093 str r3, [sp] + ARM GAS /tmp/ccE2rRGE.s page 159 + + + 1777 0116 4FF08073 mov r3, #16777216 + 1778 011a 3946 mov r1, r7 + 1779 011c 2046 mov r0, r4 + 1780 011e FFF7FEFF bl I2C_TransferConfig + 1781 .LVL100: + 1782 0122 C7E7 b .L137 + 1783 .L148: +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1784 .loc 1 1198 5 view .LVU569 +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1785 .loc 1 1198 9 is_stmt 0 view .LVU570 + 1786 0124 2A46 mov r2, r5 + 1787 0126 3146 mov r1, r6 + 1788 0128 2046 mov r0, r4 + 1789 012a FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 1790 .LVL101: +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1791 .loc 1 1198 8 view .LVU571 + 1792 012e 08BB cbnz r0, .L146 +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1793 .loc 1 1204 5 is_stmt 1 view .LVU572 + 1794 0130 2368 ldr r3, [r4] + 1795 0132 2022 movs r2, #32 + 1796 0134 DA61 str r2, [r3, #28] +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1797 .loc 1 1207 5 view .LVU573 + 1798 0136 2168 ldr r1, [r4] + 1799 0138 4B68 ldr r3, [r1, #4] + 1800 013a 23F0FF73 bic r3, r3, #33423360 + 1801 013e 23F48B33 bic r3, r3, #71168 + 1802 0142 23F4FF73 bic r3, r3, #510 + 1803 0146 23F00103 bic r3, r3, #1 + 1804 014a 4B60 str r3, [r1, #4] +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1805 .loc 1 1209 5 view .LVU574 +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1806 .loc 1 1209 17 is_stmt 0 view .LVU575 + 1807 014c 84F84120 strb r2, [r4, #65] +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1808 .loc 1 1210 5 is_stmt 1 view .LVU576 +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1809 .loc 1 1210 17 is_stmt 0 view .LVU577 + 1810 0150 0023 movs r3, #0 + 1811 0152 84F84230 strb r3, [r4, #66] +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1812 .loc 1 1213 5 is_stmt 1 view .LVU578 +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1813 .loc 1 1213 5 view .LVU579 + 1814 0156 84F84030 strb r3, [r4, #64] +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1815 .loc 1 1213 5 view .LVU580 +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1816 .loc 1 1215 5 view .LVU581 +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1817 .loc 1 1215 12 is_stmt 0 view .LVU582 + 1818 015a 00E0 b .L134 + 1819 .LVL102: + ARM GAS /tmp/ccE2rRGE.s page 160 + + + 1820 .L141: +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1821 .loc 1 1219 12 view .LVU583 + 1822 015c 0220 movs r0, #2 + 1823 .LVL103: + 1824 .L134: +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1825 .loc 1 1221 1 view .LVU584 + 1826 015e 02B0 add sp, sp, #8 + 1827 .cfi_remember_state + 1828 .cfi_def_cfa_offset 32 + 1829 @ sp needed + 1830 0160 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 1831 .LVL104: + 1832 .L142: + 1833 .cfi_restore_state +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1834 .loc 1 1123 5 view .LVU585 + 1835 0164 0220 movs r0, #2 + 1836 .LVL105: +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1837 .loc 1 1123 5 view .LVU586 + 1838 0166 FAE7 b .L134 + 1839 .LVL106: + 1840 .L143: +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1841 .loc 1 1130 14 view .LVU587 + 1842 0168 0120 movs r0, #1 + 1843 016a F8E7 b .L134 + 1844 .L144: +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1845 .loc 1 1162 16 view .LVU588 + 1846 016c 0120 movs r0, #1 + 1847 016e F6E7 b .L134 + 1848 .L145: +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1849 .loc 1 1178 18 view .LVU589 + 1850 0170 0120 movs r0, #1 + 1851 0172 F4E7 b .L134 + 1852 .L146: +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1853 .loc 1 1200 14 view .LVU590 + 1854 0174 0120 movs r0, #1 + 1855 0176 F2E7 b .L134 + 1856 .L150: + 1857 .align 2 + 1858 .L149: + 1859 0178 00200080 .word -2147475456 + 1860 .cfi_endproc + 1861 .LFE134: + 1863 .section .text.HAL_I2C_Master_Receive,"ax",%progbits + 1864 .align 1 + 1865 .global HAL_I2C_Master_Receive + 1866 .syntax unified + 1867 .thumb + 1868 .thumb_func + 1870 HAL_I2C_Master_Receive: + ARM GAS /tmp/ccE2rRGE.s page 161 + + + 1871 .LVL107: + 1872 .LFB135: +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 1873 .loc 1 1236 1 is_stmt 1 view -0 + 1874 .cfi_startproc + 1875 @ args = 4, pretend = 0, frame = 0 + 1876 @ frame_needed = 0, uses_anonymous_args = 0 +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 1877 .loc 1 1236 1 is_stmt 0 view .LVU592 + 1878 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 1879 .cfi_def_cfa_offset 32 + 1880 .cfi_offset 4, -32 + 1881 .cfi_offset 5, -28 + 1882 .cfi_offset 6, -24 + 1883 .cfi_offset 7, -20 + 1884 .cfi_offset 8, -16 + 1885 .cfi_offset 9, -12 + 1886 .cfi_offset 10, -8 + 1887 .cfi_offset 14, -4 + 1888 0004 82B0 sub sp, sp, #8 + 1889 .cfi_def_cfa_offset 40 + 1890 0006 0F46 mov r7, r1 + 1891 0008 0A9E ldr r6, [sp, #40] +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1892 .loc 1 1237 3 is_stmt 1 view .LVU593 +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1893 .loc 1 1239 3 view .LVU594 +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1894 .loc 1 1239 11 is_stmt 0 view .LVU595 + 1895 000a 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 1896 .LVL108: +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1897 .loc 1 1239 11 view .LVU596 + 1898 000e C9B2 uxtb r1, r1 +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1899 .loc 1 1239 6 view .LVU597 + 1900 0010 2029 cmp r1, #32 + 1901 0012 40F0A280 bne .L159 + 1902 0016 0446 mov r4, r0 + 1903 0018 9046 mov r8, r2 + 1904 001a 9946 mov r9, r3 +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1905 .loc 1 1242 5 is_stmt 1 view .LVU598 +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1906 .loc 1 1242 5 view .LVU599 + 1907 001c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 1908 .LVL109: +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1909 .loc 1 1242 5 is_stmt 0 view .LVU600 + 1910 0020 012B cmp r3, #1 + 1911 0022 00F09E80 beq .L160 +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1912 .loc 1 1242 5 is_stmt 1 discriminator 2 view .LVU601 + 1913 0026 4FF0010A mov r10, #1 + 1914 002a 80F840A0 strb r10, [r0, #64] +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1915 .loc 1 1242 5 discriminator 2 view .LVU602 + ARM GAS /tmp/ccE2rRGE.s page 162 + + +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1916 .loc 1 1245 5 discriminator 2 view .LVU603 +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1917 .loc 1 1245 17 is_stmt 0 discriminator 2 view .LVU604 + 1918 002e FFF7FEFF bl HAL_GetTick + 1919 .LVL110: +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1920 .loc 1 1245 17 discriminator 2 view .LVU605 + 1921 0032 0546 mov r5, r0 + 1922 .LVL111: +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1923 .loc 1 1247 5 is_stmt 1 discriminator 2 view .LVU606 +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1924 .loc 1 1247 9 is_stmt 0 discriminator 2 view .LVU607 + 1925 0034 0090 str r0, [sp] + 1926 0036 1923 movs r3, #25 + 1927 0038 5246 mov r2, r10 + 1928 003a 4FF40041 mov r1, #32768 + 1929 003e 2046 mov r0, r4 + 1930 .LVL112: +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1931 .loc 1 1247 9 discriminator 2 view .LVU608 + 1932 0040 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1933 .LVL113: +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1934 .loc 1 1247 8 discriminator 2 view .LVU609 + 1935 0044 0028 cmp r0, #0 + 1936 0046 40F08E80 bne .L161 +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1937 .loc 1 1252 5 is_stmt 1 view .LVU610 +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1938 .loc 1 1252 21 is_stmt 0 view .LVU611 + 1939 004a 2223 movs r3, #34 + 1940 004c 84F84130 strb r3, [r4, #65] +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1941 .loc 1 1253 5 is_stmt 1 view .LVU612 +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1942 .loc 1 1253 21 is_stmt 0 view .LVU613 + 1943 0050 1023 movs r3, #16 + 1944 0052 84F84230 strb r3, [r4, #66] +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1945 .loc 1 1254 5 is_stmt 1 view .LVU614 +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1946 .loc 1 1254 21 is_stmt 0 view .LVU615 + 1947 0056 0023 movs r3, #0 + 1948 0058 6364 str r3, [r4, #68] +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 1949 .loc 1 1257 5 is_stmt 1 view .LVU616 +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 1950 .loc 1 1257 21 is_stmt 0 view .LVU617 + 1951 005a C4F82480 str r8, [r4, #36] +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1952 .loc 1 1258 5 is_stmt 1 view .LVU618 +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1953 .loc 1 1258 21 is_stmt 0 view .LVU619 + 1954 005e A4F82A90 strh r9, [r4, #42] @ movhi +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 163 + + + 1955 .loc 1 1259 5 is_stmt 1 view .LVU620 +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 1956 .loc 1 1259 21 is_stmt 0 view .LVU621 + 1957 0062 6363 str r3, [r4, #52] +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1958 .loc 1 1263 5 is_stmt 1 view .LVU622 +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1959 .loc 1 1263 13 is_stmt 0 view .LVU623 + 1960 0064 638D ldrh r3, [r4, #42] + 1961 0066 9BB2 uxth r3, r3 +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1962 .loc 1 1263 8 view .LVU624 + 1963 0068 FF2B cmp r3, #255 + 1964 006a 0AD9 bls .L153 +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1965 .loc 1 1265 7 is_stmt 1 view .LVU625 +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1966 .loc 1 1265 22 is_stmt 0 view .LVU626 + 1967 006c FF22 movs r2, #255 + 1968 006e 2285 strh r2, [r4, #40] @ movhi +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 1969 .loc 1 1266 7 is_stmt 1 view .LVU627 + 1970 0070 414B ldr r3, .L167 + 1971 0072 0093 str r3, [sp] + 1972 0074 4FF08073 mov r3, #16777216 + 1973 0078 3946 mov r1, r7 + 1974 007a 2046 mov r0, r4 + 1975 007c FFF7FEFF bl I2C_TransferConfig + 1976 .LVL114: + 1977 0080 18E0 b .L155 + 1978 .L153: +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1979 .loc 1 1271 7 view .LVU628 +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1980 .loc 1 1271 28 is_stmt 0 view .LVU629 + 1981 0082 628D ldrh r2, [r4, #42] + 1982 0084 92B2 uxth r2, r2 +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1983 .loc 1 1271 22 view .LVU630 + 1984 0086 2285 strh r2, [r4, #40] @ movhi +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 1985 .loc 1 1272 7 is_stmt 1 view .LVU631 + 1986 0088 3B4B ldr r3, .L167 + 1987 008a 0093 str r3, [sp] + 1988 008c 4FF00073 mov r3, #33554432 + 1989 0090 D2B2 uxtb r2, r2 + 1990 0092 3946 mov r1, r7 + 1991 0094 2046 mov r0, r4 + 1992 0096 FFF7FEFF bl I2C_TransferConfig + 1993 .LVL115: + 1994 009a 0BE0 b .L155 + 1995 .L157: +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1996 .loc 1 1309 11 view .LVU632 +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1997 .loc 1 1309 32 is_stmt 0 view .LVU633 + 1998 009c 628D ldrh r2, [r4, #42] + ARM GAS /tmp/ccE2rRGE.s page 164 + + + 1999 009e 92B2 uxth r2, r2 +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2000 .loc 1 1309 26 view .LVU634 + 2001 00a0 2285 strh r2, [r4, #40] @ movhi +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 2002 .loc 1 1310 11 is_stmt 1 view .LVU635 + 2003 00a2 0023 movs r3, #0 + 2004 00a4 0093 str r3, [sp] + 2005 00a6 4FF00073 mov r3, #33554432 + 2006 00aa D2B2 uxtb r2, r2 + 2007 00ac 3946 mov r1, r7 + 2008 00ae 2046 mov r0, r4 + 2009 00b0 FFF7FEFF bl I2C_TransferConfig + 2010 .LVL116: + 2011 .L155: +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2012 .loc 1 1276 28 view .LVU636 +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2013 .loc 1 1276 16 is_stmt 0 view .LVU637 + 2014 00b4 638D ldrh r3, [r4, #42] + 2015 00b6 9BB2 uxth r3, r3 +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2016 .loc 1 1276 28 view .LVU638 + 2017 00b8 002B cmp r3, #0 + 2018 00ba 32D0 beq .L166 +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2019 .loc 1 1279 7 is_stmt 1 view .LVU639 +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2020 .loc 1 1279 11 is_stmt 0 view .LVU640 + 2021 00bc 2A46 mov r2, r5 + 2022 00be 3146 mov r1, r6 + 2023 00c0 2046 mov r0, r4 + 2024 00c2 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2025 .LVL117: +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2026 .loc 1 1279 10 view .LVU641 + 2027 00c6 0028 cmp r0, #0 + 2028 00c8 4FD1 bne .L162 +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2029 .loc 1 1285 7 is_stmt 1 view .LVU642 +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2030 .loc 1 1285 38 is_stmt 0 view .LVU643 + 2031 00ca 2368 ldr r3, [r4] +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2032 .loc 1 1285 48 view .LVU644 + 2033 00cc 5A6A ldr r2, [r3, #36] +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2034 .loc 1 1285 12 view .LVU645 + 2035 00ce 636A ldr r3, [r4, #36] +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2036 .loc 1 1285 23 view .LVU646 + 2037 00d0 1A70 strb r2, [r3] +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2038 .loc 1 1288 7 is_stmt 1 view .LVU647 +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2039 .loc 1 1288 11 is_stmt 0 view .LVU648 + 2040 00d2 636A ldr r3, [r4, #36] + ARM GAS /tmp/ccE2rRGE.s page 165 + + +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2041 .loc 1 1288 21 view .LVU649 + 2042 00d4 0133 adds r3, r3, #1 + 2043 00d6 6362 str r3, [r4, #36] +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 2044 .loc 1 1290 7 is_stmt 1 view .LVU650 +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 2045 .loc 1 1290 11 is_stmt 0 view .LVU651 + 2046 00d8 228D ldrh r2, [r4, #40] +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 2047 .loc 1 1290 21 view .LVU652 + 2048 00da 013A subs r2, r2, #1 + 2049 00dc 92B2 uxth r2, r2 + 2050 00de 2285 strh r2, [r4, #40] @ movhi +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2051 .loc 1 1291 7 is_stmt 1 view .LVU653 +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2052 .loc 1 1291 11 is_stmt 0 view .LVU654 + 2053 00e0 638D ldrh r3, [r4, #42] + 2054 00e2 9BB2 uxth r3, r3 +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2055 .loc 1 1291 22 view .LVU655 + 2056 00e4 013B subs r3, r3, #1 + 2057 00e6 9BB2 uxth r3, r3 + 2058 00e8 6385 strh r3, [r4, #42] @ movhi +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2059 .loc 1 1293 7 is_stmt 1 view .LVU656 +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2060 .loc 1 1293 16 is_stmt 0 view .LVU657 + 2061 00ea 638D ldrh r3, [r4, #42] + 2062 00ec 9BB2 uxth r3, r3 +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2063 .loc 1 1293 10 view .LVU658 + 2064 00ee 002B cmp r3, #0 + 2065 00f0 E0D0 beq .L155 +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2066 .loc 1 1293 35 discriminator 1 view .LVU659 + 2067 00f2 002A cmp r2, #0 + 2068 00f4 DED1 bne .L155 +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2069 .loc 1 1296 9 is_stmt 1 view .LVU660 +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2070 .loc 1 1296 13 is_stmt 0 view .LVU661 + 2071 00f6 0095 str r5, [sp] + 2072 00f8 3346 mov r3, r6 + 2073 00fa 8021 movs r1, #128 + 2074 00fc 2046 mov r0, r4 + 2075 00fe FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2076 .LVL118: +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2077 .loc 1 1296 12 view .LVU662 + 2078 0102 A0BB cbnz r0, .L163 +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2079 .loc 1 1301 9 is_stmt 1 view .LVU663 +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2080 .loc 1 1301 17 is_stmt 0 view .LVU664 + 2081 0104 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccE2rRGE.s page 166 + + + 2082 0106 9BB2 uxth r3, r3 +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2083 .loc 1 1301 12 view .LVU665 + 2084 0108 FF2B cmp r3, #255 + 2085 010a C7D9 bls .L157 +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2086 .loc 1 1303 11 is_stmt 1 view .LVU666 +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2087 .loc 1 1303 26 is_stmt 0 view .LVU667 + 2088 010c FF22 movs r2, #255 + 2089 010e 2285 strh r2, [r4, #40] @ movhi +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 2090 .loc 1 1304 11 is_stmt 1 view .LVU668 + 2091 0110 0023 movs r3, #0 + 2092 0112 0093 str r3, [sp] + 2093 0114 4FF08073 mov r3, #16777216 + 2094 0118 3946 mov r1, r7 + 2095 011a 2046 mov r0, r4 + 2096 011c FFF7FEFF bl I2C_TransferConfig + 2097 .LVL119: + 2098 0120 C8E7 b .L155 + 2099 .L166: +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2100 .loc 1 1318 5 view .LVU669 +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2101 .loc 1 1318 9 is_stmt 0 view .LVU670 + 2102 0122 2A46 mov r2, r5 + 2103 0124 3146 mov r1, r6 + 2104 0126 2046 mov r0, r4 + 2105 0128 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2106 .LVL120: +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2107 .loc 1 1318 8 view .LVU671 + 2108 012c 08BB cbnz r0, .L164 +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2109 .loc 1 1324 5 is_stmt 1 view .LVU672 + 2110 012e 2368 ldr r3, [r4] + 2111 0130 2022 movs r2, #32 + 2112 0132 DA61 str r2, [r3, #28] +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2113 .loc 1 1327 5 view .LVU673 + 2114 0134 2168 ldr r1, [r4] + 2115 0136 4B68 ldr r3, [r1, #4] + 2116 0138 23F0FF73 bic r3, r3, #33423360 + 2117 013c 23F48B33 bic r3, r3, #71168 + 2118 0140 23F4FF73 bic r3, r3, #510 + 2119 0144 23F00103 bic r3, r3, #1 + 2120 0148 4B60 str r3, [r1, #4] +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2121 .loc 1 1329 5 view .LVU674 +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2122 .loc 1 1329 17 is_stmt 0 view .LVU675 + 2123 014a 84F84120 strb r2, [r4, #65] +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2124 .loc 1 1330 5 is_stmt 1 view .LVU676 +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2125 .loc 1 1330 17 is_stmt 0 view .LVU677 + ARM GAS /tmp/ccE2rRGE.s page 167 + + + 2126 014e 0023 movs r3, #0 + 2127 0150 84F84230 strb r3, [r4, #66] +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2128 .loc 1 1333 5 is_stmt 1 view .LVU678 +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2129 .loc 1 1333 5 view .LVU679 + 2130 0154 84F84030 strb r3, [r4, #64] +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2131 .loc 1 1333 5 view .LVU680 +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2132 .loc 1 1335 5 view .LVU681 +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2133 .loc 1 1335 12 is_stmt 0 view .LVU682 + 2134 0158 00E0 b .L152 + 2135 .LVL121: + 2136 .L159: +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2137 .loc 1 1339 12 view .LVU683 + 2138 015a 0220 movs r0, #2 + 2139 .LVL122: + 2140 .L152: +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2141 .loc 1 1341 1 view .LVU684 + 2142 015c 02B0 add sp, sp, #8 + 2143 .cfi_remember_state + 2144 .cfi_def_cfa_offset 32 + 2145 @ sp needed + 2146 015e BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 2147 .LVL123: + 2148 .L160: + 2149 .cfi_restore_state +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2150 .loc 1 1242 5 view .LVU685 + 2151 0162 0220 movs r0, #2 + 2152 .LVL124: +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2153 .loc 1 1242 5 view .LVU686 + 2154 0164 FAE7 b .L152 + 2155 .LVL125: + 2156 .L161: +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2157 .loc 1 1249 14 view .LVU687 + 2158 0166 0120 movs r0, #1 + 2159 0168 F8E7 b .L152 + 2160 .L162: +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2161 .loc 1 1281 16 view .LVU688 + 2162 016a 0120 movs r0, #1 + 2163 016c F6E7 b .L152 + 2164 .L163: +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2165 .loc 1 1298 18 view .LVU689 + 2166 016e 0120 movs r0, #1 + 2167 0170 F4E7 b .L152 + 2168 .L164: +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2169 .loc 1 1320 14 view .LVU690 + ARM GAS /tmp/ccE2rRGE.s page 168 + + + 2170 0172 0120 movs r0, #1 + 2171 0174 F2E7 b .L152 + 2172 .L168: + 2173 0176 00BF .align 2 + 2174 .L167: + 2175 0178 00240080 .word -2147474432 + 2176 .cfi_endproc + 2177 .LFE135: + 2179 .section .text.HAL_I2C_Slave_Transmit,"ax",%progbits + 2180 .align 1 + 2181 .global HAL_I2C_Slave_Transmit + 2182 .syntax unified + 2183 .thumb + 2184 .thumb_func + 2186 HAL_I2C_Slave_Transmit: + 2187 .LVL126: + 2188 .LFB136: +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 2189 .loc 1 1354 1 is_stmt 1 view -0 + 2190 .cfi_startproc + 2191 @ args = 0, pretend = 0, frame = 0 + 2192 @ frame_needed = 0, uses_anonymous_args = 0 +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 2193 .loc 1 1354 1 is_stmt 0 view .LVU692 + 2194 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2195 .cfi_def_cfa_offset 24 + 2196 .cfi_offset 4, -24 + 2197 .cfi_offset 5, -20 + 2198 .cfi_offset 6, -16 + 2199 .cfi_offset 7, -12 + 2200 .cfi_offset 8, -8 + 2201 .cfi_offset 14, -4 + 2202 0004 82B0 sub sp, sp, #8 + 2203 .cfi_def_cfa_offset 32 + 2204 0006 1D46 mov r5, r3 +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2205 .loc 1 1355 3 is_stmt 1 view .LVU693 +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2206 .loc 1 1357 3 view .LVU694 +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2207 .loc 1 1357 11 is_stmt 0 view .LVU695 + 2208 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 2209 .LVL127: +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2210 .loc 1 1357 11 view .LVU696 + 2211 000c DBB2 uxtb r3, r3 +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2212 .loc 1 1357 6 view .LVU697 + 2213 000e 202B cmp r3, #32 + 2214 0010 40F0B680 bne .L181 + 2215 0014 0446 mov r4, r0 + 2216 0016 0F46 mov r7, r1 + 2217 0018 9046 mov r8, r2 +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2218 .loc 1 1359 5 is_stmt 1 view .LVU698 +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2219 .loc 1 1359 8 is_stmt 0 view .LVU699 + ARM GAS /tmp/ccE2rRGE.s page 169 + + + 2220 001a 0029 cmp r1, #0 + 2221 001c 52D0 beq .L171 +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2222 .loc 1 1359 25 discriminator 1 view .LVU700 + 2223 001e 002A cmp r2, #0 + 2224 0020 50D0 beq .L171 +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2225 .loc 1 1365 5 is_stmt 1 view .LVU701 +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2226 .loc 1 1365 5 view .LVU702 + 2227 0022 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 2228 0026 012B cmp r3, #1 + 2229 0028 00F0AE80 beq .L182 +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2230 .loc 1 1365 5 discriminator 2 view .LVU703 + 2231 002c 0123 movs r3, #1 + 2232 002e 80F84030 strb r3, [r0, #64] +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2233 .loc 1 1365 5 discriminator 2 view .LVU704 +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2234 .loc 1 1368 5 discriminator 2 view .LVU705 +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2235 .loc 1 1368 17 is_stmt 0 discriminator 2 view .LVU706 + 2236 0032 FFF7FEFF bl HAL_GetTick + 2237 .LVL128: +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2238 .loc 1 1368 17 discriminator 2 view .LVU707 + 2239 0036 0646 mov r6, r0 + 2240 .LVL129: +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2241 .loc 1 1370 5 is_stmt 1 discriminator 2 view .LVU708 +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2242 .loc 1 1370 21 is_stmt 0 discriminator 2 view .LVU709 + 2243 0038 2123 movs r3, #33 + 2244 003a 84F84130 strb r3, [r4, #65] +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2245 .loc 1 1371 5 is_stmt 1 discriminator 2 view .LVU710 +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2246 .loc 1 1371 21 is_stmt 0 discriminator 2 view .LVU711 + 2247 003e 2023 movs r3, #32 + 2248 0040 84F84230 strb r3, [r4, #66] +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2249 .loc 1 1372 5 is_stmt 1 discriminator 2 view .LVU712 +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2250 .loc 1 1372 21 is_stmt 0 discriminator 2 view .LVU713 + 2251 0044 0022 movs r2, #0 + 2252 0046 6264 str r2, [r4, #68] +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2253 .loc 1 1375 5 is_stmt 1 discriminator 2 view .LVU714 +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2254 .loc 1 1375 21 is_stmt 0 discriminator 2 view .LVU715 + 2255 0048 6762 str r7, [r4, #36] +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2256 .loc 1 1376 5 is_stmt 1 discriminator 2 view .LVU716 +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2257 .loc 1 1376 21 is_stmt 0 discriminator 2 view .LVU717 + 2258 004a A4F82A80 strh r8, [r4, #42] @ movhi + ARM GAS /tmp/ccE2rRGE.s page 170 + + +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2259 .loc 1 1377 5 is_stmt 1 discriminator 2 view .LVU718 +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2260 .loc 1 1377 21 is_stmt 0 discriminator 2 view .LVU719 + 2261 004e 6263 str r2, [r4, #52] +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2262 .loc 1 1380 5 is_stmt 1 discriminator 2 view .LVU720 +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2263 .loc 1 1380 9 is_stmt 0 discriminator 2 view .LVU721 + 2264 0050 2168 ldr r1, [r4] +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2265 .loc 1 1380 19 discriminator 2 view .LVU722 + 2266 0052 4B68 ldr r3, [r1, #4] +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2267 .loc 1 1380 25 discriminator 2 view .LVU723 + 2268 0054 23F40043 bic r3, r3, #32768 + 2269 0058 4B60 str r3, [r1, #4] +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2270 .loc 1 1383 5 is_stmt 1 discriminator 2 view .LVU724 +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2271 .loc 1 1383 9 is_stmt 0 discriminator 2 view .LVU725 + 2272 005a 0090 str r0, [sp] + 2273 005c 2B46 mov r3, r5 + 2274 005e 0821 movs r1, #8 + 2275 0060 2046 mov r0, r4 + 2276 .LVL130: +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2277 .loc 1 1383 9 discriminator 2 view .LVU726 + 2278 0062 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2279 .LVL131: +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2280 .loc 1 1383 8 discriminator 2 view .LVU727 + 2281 0066 0028 cmp r0, #0 + 2282 0068 31D1 bne .L185 +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2283 .loc 1 1391 5 is_stmt 1 view .LVU728 + 2284 006a 2368 ldr r3, [r4] + 2285 006c 0822 movs r2, #8 + 2286 006e DA61 str r2, [r3, #28] +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2287 .loc 1 1394 5 view .LVU729 +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2288 .loc 1 1394 19 is_stmt 0 view .LVU730 + 2289 0070 E368 ldr r3, [r4, #12] +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2290 .loc 1 1394 8 view .LVU731 + 2291 0072 022B cmp r3, #2 + 2292 0074 32D0 beq .L186 + 2293 .L174: +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2294 .loc 1 1409 5 is_stmt 1 view .LVU732 +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2295 .loc 1 1409 9 is_stmt 0 view .LVU733 + 2296 0076 0096 str r6, [sp] + 2297 0078 2B46 mov r3, r5 + 2298 007a 0022 movs r2, #0 + 2299 007c 4FF48031 mov r1, #65536 + ARM GAS /tmp/ccE2rRGE.s page 171 + + + 2300 0080 2046 mov r0, r4 + 2301 0082 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2302 .LVL132: +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2303 .loc 1 1409 8 view .LVU734 + 2304 0086 0028 cmp r0, #0 + 2305 0088 3BD1 bne .L187 + 2306 .L176: +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2307 .loc 1 1416 28 is_stmt 1 view .LVU735 +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2308 .loc 1 1416 16 is_stmt 0 view .LVU736 + 2309 008a 638D ldrh r3, [r4, #42] + 2310 008c 9BB2 uxth r3, r3 +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2311 .loc 1 1416 28 view .LVU737 + 2312 008e 002B cmp r3, #0 + 2313 0090 45D0 beq .L188 +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2314 .loc 1 1419 7 is_stmt 1 view .LVU738 +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2315 .loc 1 1419 11 is_stmt 0 view .LVU739 + 2316 0092 3246 mov r2, r6 + 2317 0094 2946 mov r1, r5 + 2318 0096 2046 mov r0, r4 + 2319 0098 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 2320 .LVL133: +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2321 .loc 1 1419 10 view .LVU740 + 2322 009c 0028 cmp r0, #0 + 2323 009e 37D1 bne .L189 +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2324 .loc 1 1427 7 is_stmt 1 view .LVU741 +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2325 .loc 1 1427 35 is_stmt 0 view .LVU742 + 2326 00a0 626A ldr r2, [r4, #36] +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2327 .loc 1 1427 11 view .LVU743 + 2328 00a2 2368 ldr r3, [r4] +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2329 .loc 1 1427 30 view .LVU744 + 2330 00a4 1278 ldrb r2, [r2] @ zero_extendqisi2 +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2331 .loc 1 1427 28 view .LVU745 + 2332 00a6 9A62 str r2, [r3, #40] +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2333 .loc 1 1430 7 is_stmt 1 view .LVU746 +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2334 .loc 1 1430 11 is_stmt 0 view .LVU747 + 2335 00a8 636A ldr r3, [r4, #36] +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2336 .loc 1 1430 21 view .LVU748 + 2337 00aa 0133 adds r3, r3, #1 + 2338 00ac 6362 str r3, [r4, #36] +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2339 .loc 1 1432 7 is_stmt 1 view .LVU749 +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 172 + + + 2340 .loc 1 1432 11 is_stmt 0 view .LVU750 + 2341 00ae B4F82AC0 ldrh ip, [r4, #42] + 2342 00b2 1FFA8CFC uxth ip, ip +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2343 .loc 1 1432 22 view .LVU751 + 2344 00b6 0CF1FF3C add ip, ip, #-1 + 2345 00ba 1FFA8CFC uxth ip, ip + 2346 00be A4F82AC0 strh ip, [r4, #42] @ movhi + 2347 00c2 E2E7 b .L176 + 2348 .LVL134: + 2349 .L171: +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2350 .loc 1 1361 7 is_stmt 1 view .LVU752 +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2351 .loc 1 1361 23 is_stmt 0 view .LVU753 + 2352 00c4 4FF40073 mov r3, #512 + 2353 00c8 6364 str r3, [r4, #68] +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2354 .loc 1 1362 7 is_stmt 1 view .LVU754 +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2355 .loc 1 1362 15 is_stmt 0 view .LVU755 + 2356 00ca 0120 movs r0, #1 + 2357 .LVL135: +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2358 .loc 1 1362 15 view .LVU756 + 2359 00cc 59E0 b .L170 + 2360 .LVL136: + 2361 .L185: +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2362 .loc 1 1386 7 is_stmt 1 view .LVU757 +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2363 .loc 1 1386 11 is_stmt 0 view .LVU758 + 2364 00ce 2268 ldr r2, [r4] +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2365 .loc 1 1386 21 view .LVU759 + 2366 00d0 5368 ldr r3, [r2, #4] +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2367 .loc 1 1386 27 view .LVU760 + 2368 00d2 43F40043 orr r3, r3, #32768 + 2369 00d6 5360 str r3, [r2, #4] +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2370 .loc 1 1387 7 is_stmt 1 view .LVU761 +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2371 .loc 1 1387 14 is_stmt 0 view .LVU762 + 2372 00d8 0120 movs r0, #1 + 2373 00da 52E0 b .L170 + 2374 .L186: +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2375 .loc 1 1397 7 is_stmt 1 view .LVU763 +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2376 .loc 1 1397 11 is_stmt 0 view .LVU764 + 2377 00dc 0096 str r6, [sp] + 2378 00de 2B46 mov r3, r5 + 2379 00e0 0022 movs r2, #0 + 2380 00e2 0821 movs r1, #8 + 2381 00e4 2046 mov r0, r4 + 2382 00e6 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + ARM GAS /tmp/ccE2rRGE.s page 173 + + + 2383 .LVL137: +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2384 .loc 1 1397 10 view .LVU765 + 2385 00ea 18B9 cbnz r0, .L190 +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2386 .loc 1 1405 7 is_stmt 1 view .LVU766 + 2387 00ec 2368 ldr r3, [r4] + 2388 00ee 0822 movs r2, #8 + 2389 00f0 DA61 str r2, [r3, #28] + 2390 00f2 C0E7 b .L174 + 2391 .L190: +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2392 .loc 1 1400 9 view .LVU767 +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2393 .loc 1 1400 13 is_stmt 0 view .LVU768 + 2394 00f4 2268 ldr r2, [r4] +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2395 .loc 1 1400 23 view .LVU769 + 2396 00f6 5368 ldr r3, [r2, #4] +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2397 .loc 1 1400 29 view .LVU770 + 2398 00f8 43F40043 orr r3, r3, #32768 + 2399 00fc 5360 str r3, [r2, #4] +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2400 .loc 1 1401 9 is_stmt 1 view .LVU771 +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2401 .loc 1 1401 16 is_stmt 0 view .LVU772 + 2402 00fe 0120 movs r0, #1 + 2403 0100 3FE0 b .L170 + 2404 .L187: +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2405 .loc 1 1412 7 is_stmt 1 view .LVU773 +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2406 .loc 1 1412 11 is_stmt 0 view .LVU774 + 2407 0102 2268 ldr r2, [r4] +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2408 .loc 1 1412 21 view .LVU775 + 2409 0104 5368 ldr r3, [r2, #4] +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2410 .loc 1 1412 27 view .LVU776 + 2411 0106 43F40043 orr r3, r3, #32768 + 2412 010a 5360 str r3, [r2, #4] +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2413 .loc 1 1413 7 is_stmt 1 view .LVU777 +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2414 .loc 1 1413 14 is_stmt 0 view .LVU778 + 2415 010c 0120 movs r0, #1 + 2416 010e 38E0 b .L170 + 2417 .L189: +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2418 .loc 1 1422 9 is_stmt 1 view .LVU779 +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2419 .loc 1 1422 13 is_stmt 0 view .LVU780 + 2420 0110 2268 ldr r2, [r4] +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2421 .loc 1 1422 23 view .LVU781 + 2422 0112 5368 ldr r3, [r2, #4] + ARM GAS /tmp/ccE2rRGE.s page 174 + + +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2423 .loc 1 1422 29 view .LVU782 + 2424 0114 43F40043 orr r3, r3, #32768 + 2425 0118 5360 str r3, [r2, #4] +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2426 .loc 1 1423 9 is_stmt 1 view .LVU783 +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2427 .loc 1 1423 16 is_stmt 0 view .LVU784 + 2428 011a 0120 movs r0, #1 + 2429 011c 31E0 b .L170 + 2430 .L188: +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2431 .loc 1 1436 5 is_stmt 1 view .LVU785 +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2432 .loc 1 1436 9 is_stmt 0 view .LVU786 + 2433 011e 3246 mov r2, r6 + 2434 0120 2946 mov r1, r5 + 2435 0122 2046 mov r0, r4 + 2436 0124 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2437 .LVL138: +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2438 .loc 1 1436 8 view .LVU787 + 2439 0128 48B1 cbz r0, .L179 +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2440 .loc 1 1439 7 is_stmt 1 view .LVU788 +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2441 .loc 1 1439 11 is_stmt 0 view .LVU789 + 2442 012a 2268 ldr r2, [r4] +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2443 .loc 1 1439 21 view .LVU790 + 2444 012c 5368 ldr r3, [r2, #4] +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2445 .loc 1 1439 27 view .LVU791 + 2446 012e 43F40043 orr r3, r3, #32768 + 2447 0132 5360 str r3, [r2, #4] +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2448 .loc 1 1441 7 is_stmt 1 view .LVU792 +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2449 .loc 1 1441 15 is_stmt 0 view .LVU793 + 2450 0134 636C ldr r3, [r4, #68] +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2451 .loc 1 1441 10 view .LVU794 + 2452 0136 042B cmp r3, #4 + 2453 0138 28D1 bne .L183 +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2454 .loc 1 1445 9 is_stmt 1 view .LVU795 +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2455 .loc 1 1445 25 is_stmt 0 view .LVU796 + 2456 013a 0023 movs r3, #0 + 2457 013c 6364 str r3, [r4, #68] + 2458 .L179: +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2459 .loc 1 1454 5 is_stmt 1 view .LVU797 + 2460 013e 2368 ldr r3, [r4] + 2461 0140 2022 movs r2, #32 + 2462 0142 DA61 str r2, [r3, #28] +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 175 + + + 2463 .loc 1 1457 5 view .LVU798 +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2464 .loc 1 1457 9 is_stmt 0 view .LVU799 + 2465 0144 0096 str r6, [sp] + 2466 0146 2B46 mov r3, r5 + 2467 0148 0122 movs r2, #1 + 2468 014a 4FF40041 mov r1, #32768 + 2469 014e 2046 mov r0, r4 + 2470 0150 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2471 .LVL139: +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2472 .loc 1 1457 8 view .LVU800 + 2473 0154 30B1 cbz r0, .L180 +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2474 .loc 1 1460 7 is_stmt 1 view .LVU801 +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2475 .loc 1 1460 11 is_stmt 0 view .LVU802 + 2476 0156 2268 ldr r2, [r4] +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2477 .loc 1 1460 21 view .LVU803 + 2478 0158 5368 ldr r3, [r2, #4] +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2479 .loc 1 1460 27 view .LVU804 + 2480 015a 43F40043 orr r3, r3, #32768 + 2481 015e 5360 str r3, [r2, #4] +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2482 .loc 1 1461 7 is_stmt 1 view .LVU805 +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2483 .loc 1 1461 14 is_stmt 0 view .LVU806 + 2484 0160 0120 movs r0, #1 + 2485 0162 0EE0 b .L170 + 2486 .L180: +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2487 .loc 1 1465 5 is_stmt 1 view .LVU807 +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2488 .loc 1 1465 9 is_stmt 0 view .LVU808 + 2489 0164 2268 ldr r2, [r4] +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2490 .loc 1 1465 19 view .LVU809 + 2491 0166 5368 ldr r3, [r2, #4] +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2492 .loc 1 1465 25 view .LVU810 + 2493 0168 43F40043 orr r3, r3, #32768 + 2494 016c 5360 str r3, [r2, #4] +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2495 .loc 1 1467 5 is_stmt 1 view .LVU811 +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2496 .loc 1 1467 17 is_stmt 0 view .LVU812 + 2497 016e 2023 movs r3, #32 + 2498 0170 84F84130 strb r3, [r4, #65] +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2499 .loc 1 1468 5 is_stmt 1 view .LVU813 +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2500 .loc 1 1468 17 is_stmt 0 view .LVU814 + 2501 0174 0023 movs r3, #0 + 2502 0176 84F84230 strb r3, [r4, #66] +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 176 + + + 2503 .loc 1 1471 5 is_stmt 1 view .LVU815 +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2504 .loc 1 1471 5 view .LVU816 + 2505 017a 84F84030 strb r3, [r4, #64] +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2506 .loc 1 1471 5 view .LVU817 +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2507 .loc 1 1473 5 view .LVU818 +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2508 .loc 1 1473 12 is_stmt 0 view .LVU819 + 2509 017e 00E0 b .L170 + 2510 .LVL140: + 2511 .L181: +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2512 .loc 1 1477 12 view .LVU820 + 2513 0180 0220 movs r0, #2 + 2514 .LVL141: + 2515 .L170: +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2516 .loc 1 1479 1 view .LVU821 + 2517 0182 02B0 add sp, sp, #8 + 2518 .cfi_remember_state + 2519 .cfi_def_cfa_offset 24 + 2520 @ sp needed + 2521 0184 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2522 .LVL142: + 2523 .L182: + 2524 .cfi_restore_state +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2525 .loc 1 1365 5 view .LVU822 + 2526 0188 0220 movs r0, #2 + 2527 .LVL143: +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2528 .loc 1 1365 5 view .LVU823 + 2529 018a FAE7 b .L170 + 2530 .LVL144: + 2531 .L183: +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2532 .loc 1 1449 16 view .LVU824 + 2533 018c 0120 movs r0, #1 + 2534 018e F8E7 b .L170 + 2535 .cfi_endproc + 2536 .LFE136: + 2538 .section .text.HAL_I2C_Slave_Receive,"ax",%progbits + 2539 .align 1 + 2540 .global HAL_I2C_Slave_Receive + 2541 .syntax unified + 2542 .thumb + 2543 .thumb_func + 2545 HAL_I2C_Slave_Receive: + 2546 .LVL145: + 2547 .LFB137: +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 2548 .loc 1 1492 1 is_stmt 1 view -0 + 2549 .cfi_startproc + 2550 @ args = 0, pretend = 0, frame = 0 + 2551 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccE2rRGE.s page 177 + + +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 2552 .loc 1 1492 1 is_stmt 0 view .LVU826 + 2553 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 2554 .cfi_def_cfa_offset 24 + 2555 .cfi_offset 4, -24 + 2556 .cfi_offset 5, -20 + 2557 .cfi_offset 6, -16 + 2558 .cfi_offset 7, -12 + 2559 .cfi_offset 8, -8 + 2560 .cfi_offset 14, -4 + 2561 0004 82B0 sub sp, sp, #8 + 2562 .cfi_def_cfa_offset 32 + 2563 0006 1D46 mov r5, r3 +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2564 .loc 1 1493 3 is_stmt 1 view .LVU827 +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2565 .loc 1 1495 3 view .LVU828 +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2566 .loc 1 1495 11 is_stmt 0 view .LVU829 + 2567 0008 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 2568 .LVL146: +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2569 .loc 1 1495 11 view .LVU830 + 2570 000c DBB2 uxtb r3, r3 +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2571 .loc 1 1495 6 view .LVU831 + 2572 000e 202B cmp r3, #32 + 2573 0010 40F0A780 bne .L202 + 2574 0014 0446 mov r4, r0 + 2575 0016 0E46 mov r6, r1 + 2576 0018 9046 mov r8, r2 +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2577 .loc 1 1497 5 is_stmt 1 view .LVU832 +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2578 .loc 1 1497 8 is_stmt 0 view .LVU833 + 2579 001a 51B3 cbz r1, .L193 +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2580 .loc 1 1497 25 discriminator 1 view .LVU834 + 2581 001c 4AB3 cbz r2, .L193 +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2582 .loc 1 1503 5 is_stmt 1 view .LVU835 +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2583 .loc 1 1503 5 view .LVU836 + 2584 001e 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 2585 0022 012B cmp r3, #1 + 2586 0024 00F0A180 beq .L203 +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2587 .loc 1 1503 5 discriminator 2 view .LVU837 + 2588 0028 0123 movs r3, #1 + 2589 002a 80F84030 strb r3, [r0, #64] +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2590 .loc 1 1503 5 discriminator 2 view .LVU838 +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2591 .loc 1 1506 5 discriminator 2 view .LVU839 +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2592 .loc 1 1506 17 is_stmt 0 discriminator 2 view .LVU840 + 2593 002e FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccE2rRGE.s page 178 + + + 2594 .LVL147: +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2595 .loc 1 1506 17 discriminator 2 view .LVU841 + 2596 0032 0746 mov r7, r0 + 2597 .LVL148: +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2598 .loc 1 1508 5 is_stmt 1 discriminator 2 view .LVU842 +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2599 .loc 1 1508 21 is_stmt 0 discriminator 2 view .LVU843 + 2600 0034 2223 movs r3, #34 + 2601 0036 84F84130 strb r3, [r4, #65] +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2602 .loc 1 1509 5 is_stmt 1 discriminator 2 view .LVU844 +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2603 .loc 1 1509 21 is_stmt 0 discriminator 2 view .LVU845 + 2604 003a 2023 movs r3, #32 + 2605 003c 84F84230 strb r3, [r4, #66] +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2606 .loc 1 1510 5 is_stmt 1 discriminator 2 view .LVU846 +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2607 .loc 1 1510 21 is_stmt 0 discriminator 2 view .LVU847 + 2608 0040 0022 movs r2, #0 + 2609 0042 6264 str r2, [r4, #68] +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2610 .loc 1 1513 5 is_stmt 1 discriminator 2 view .LVU848 +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2611 .loc 1 1513 21 is_stmt 0 discriminator 2 view .LVU849 + 2612 0044 6662 str r6, [r4, #36] +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2613 .loc 1 1514 5 is_stmt 1 discriminator 2 view .LVU850 +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2614 .loc 1 1514 21 is_stmt 0 discriminator 2 view .LVU851 + 2615 0046 A4F82A80 strh r8, [r4, #42] @ movhi +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2616 .loc 1 1515 5 is_stmt 1 discriminator 2 view .LVU852 +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2617 .loc 1 1515 21 is_stmt 0 discriminator 2 view .LVU853 + 2618 004a 6263 str r2, [r4, #52] +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2619 .loc 1 1518 5 is_stmt 1 discriminator 2 view .LVU854 +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2620 .loc 1 1518 9 is_stmt 0 discriminator 2 view .LVU855 + 2621 004c 2168 ldr r1, [r4] +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2622 .loc 1 1518 19 discriminator 2 view .LVU856 + 2623 004e 4B68 ldr r3, [r1, #4] +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2624 .loc 1 1518 25 discriminator 2 view .LVU857 + 2625 0050 23F40043 bic r3, r3, #32768 + 2626 0054 4B60 str r3, [r1, #4] +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2627 .loc 1 1521 5 is_stmt 1 discriminator 2 view .LVU858 +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2628 .loc 1 1521 9 is_stmt 0 discriminator 2 view .LVU859 + 2629 0056 0090 str r0, [sp] + 2630 0058 2B46 mov r3, r5 + 2631 005a 0821 movs r1, #8 + ARM GAS /tmp/ccE2rRGE.s page 179 + + + 2632 005c 2046 mov r0, r4 + 2633 .LVL149: +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2634 .loc 1 1521 9 discriminator 2 view .LVU860 + 2635 005e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2636 .LVL150: +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2637 .loc 1 1521 8 discriminator 2 view .LVU861 + 2638 0062 58B1 cbz r0, .L195 +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2639 .loc 1 1524 7 is_stmt 1 view .LVU862 +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2640 .loc 1 1524 11 is_stmt 0 view .LVU863 + 2641 0064 2268 ldr r2, [r4] +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2642 .loc 1 1524 21 view .LVU864 + 2643 0066 5368 ldr r3, [r2, #4] +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2644 .loc 1 1524 27 view .LVU865 + 2645 0068 43F40043 orr r3, r3, #32768 + 2646 006c 5360 str r3, [r2, #4] +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2647 .loc 1 1525 7 is_stmt 1 view .LVU866 +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2648 .loc 1 1525 14 is_stmt 0 view .LVU867 + 2649 006e 0120 movs r0, #1 + 2650 0070 78E0 b .L192 + 2651 .LVL151: + 2652 .L193: +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2653 .loc 1 1499 7 is_stmt 1 view .LVU868 +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2654 .loc 1 1499 23 is_stmt 0 view .LVU869 + 2655 0072 4FF40073 mov r3, #512 + 2656 0076 6364 str r3, [r4, #68] +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2657 .loc 1 1500 7 is_stmt 1 view .LVU870 +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2658 .loc 1 1500 15 is_stmt 0 view .LVU871 + 2659 0078 0120 movs r0, #1 + 2660 .LVL152: +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2661 .loc 1 1500 15 view .LVU872 + 2662 007a 73E0 b .L192 + 2663 .LVL153: + 2664 .L195: +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2665 .loc 1 1529 5 is_stmt 1 view .LVU873 + 2666 007c 2368 ldr r3, [r4] + 2667 007e 0822 movs r2, #8 + 2668 0080 DA61 str r2, [r3, #28] +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2669 .loc 1 1532 5 view .LVU874 +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2670 .loc 1 1532 9 is_stmt 0 view .LVU875 + 2671 0082 0097 str r7, [sp] + 2672 0084 2B46 mov r3, r5 + ARM GAS /tmp/ccE2rRGE.s page 180 + + + 2673 0086 0122 movs r2, #1 + 2674 0088 4FF48031 mov r1, #65536 + 2675 008c 2046 mov r0, r4 + 2676 008e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2677 .LVL154: +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2678 .loc 1 1532 8 view .LVU876 + 2679 0092 B8B1 cbz r0, .L196 +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2680 .loc 1 1535 7 is_stmt 1 view .LVU877 +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2681 .loc 1 1535 11 is_stmt 0 view .LVU878 + 2682 0094 2268 ldr r2, [r4] +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2683 .loc 1 1535 21 view .LVU879 + 2684 0096 5368 ldr r3, [r2, #4] +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2685 .loc 1 1535 27 view .LVU880 + 2686 0098 43F40043 orr r3, r3, #32768 + 2687 009c 5360 str r3, [r2, #4] +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2688 .loc 1 1536 7 is_stmt 1 view .LVU881 +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2689 .loc 1 1536 14 is_stmt 0 view .LVU882 + 2690 009e 0120 movs r0, #1 + 2691 00a0 60E0 b .L192 + 2692 .L197: +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2693 .loc 1 1563 7 is_stmt 1 view .LVU883 +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2694 .loc 1 1563 38 is_stmt 0 view .LVU884 + 2695 00a2 2368 ldr r3, [r4] +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2696 .loc 1 1563 48 view .LVU885 + 2697 00a4 5A6A ldr r2, [r3, #36] +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2698 .loc 1 1563 12 view .LVU886 + 2699 00a6 636A ldr r3, [r4, #36] +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2700 .loc 1 1563 23 view .LVU887 + 2701 00a8 1A70 strb r2, [r3] +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2702 .loc 1 1566 7 is_stmt 1 view .LVU888 +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2703 .loc 1 1566 11 is_stmt 0 view .LVU889 + 2704 00aa 636A ldr r3, [r4, #36] +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2705 .loc 1 1566 21 view .LVU890 + 2706 00ac 0133 adds r3, r3, #1 + 2707 00ae 6362 str r3, [r4, #36] +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2708 .loc 1 1568 7 is_stmt 1 view .LVU891 +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2709 .loc 1 1568 11 is_stmt 0 view .LVU892 + 2710 00b0 B4F82AC0 ldrh ip, [r4, #42] + 2711 00b4 1FFA8CFC uxth ip, ip +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 181 + + + 2712 .loc 1 1568 22 view .LVU893 + 2713 00b8 0CF1FF3C add ip, ip, #-1 + 2714 00bc 1FFA8CFC uxth ip, ip + 2715 00c0 A4F82AC0 strh ip, [r4, #42] @ movhi + 2716 .L196: +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2717 .loc 1 1539 28 is_stmt 1 view .LVU894 +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2718 .loc 1 1539 16 is_stmt 0 view .LVU895 + 2719 00c4 638D ldrh r3, [r4, #42] + 2720 00c6 9BB2 uxth r3, r3 +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2721 .loc 1 1539 28 view .LVU896 + 2722 00c8 EBB1 cbz r3, .L205 +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2723 .loc 1 1542 7 is_stmt 1 view .LVU897 +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2724 .loc 1 1542 11 is_stmt 0 view .LVU898 + 2725 00ca 3A46 mov r2, r7 + 2726 00cc 2946 mov r1, r5 + 2727 00ce 2046 mov r0, r4 + 2728 00d0 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2729 .LVL155: +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2730 .loc 1 1542 10 view .LVU899 + 2731 00d4 0028 cmp r0, #0 + 2732 00d6 E4D0 beq .L197 +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2733 .loc 1 1545 9 is_stmt 1 view .LVU900 +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2734 .loc 1 1545 13 is_stmt 0 view .LVU901 + 2735 00d8 2268 ldr r2, [r4] +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2736 .loc 1 1545 23 view .LVU902 + 2737 00da 5368 ldr r3, [r2, #4] +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2738 .loc 1 1545 29 view .LVU903 + 2739 00dc 43F40043 orr r3, r3, #32768 + 2740 00e0 5360 str r3, [r2, #4] +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2741 .loc 1 1548 9 is_stmt 1 view .LVU904 +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2742 .loc 1 1548 13 is_stmt 0 view .LVU905 + 2743 00e2 2368 ldr r3, [r4] + 2744 00e4 9A69 ldr r2, [r3, #24] +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2745 .loc 1 1548 12 view .LVU906 + 2746 00e6 12F0040F tst r2, #4 + 2747 00ea 0AD0 beq .L198 +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2748 .loc 1 1551 11 is_stmt 1 view .LVU907 +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2749 .loc 1 1551 52 is_stmt 0 view .LVU908 + 2750 00ec 5A6A ldr r2, [r3, #36] +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2751 .loc 1 1551 16 view .LVU909 + 2752 00ee 636A ldr r3, [r4, #36] + ARM GAS /tmp/ccE2rRGE.s page 182 + + +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2753 .loc 1 1551 27 view .LVU910 + 2754 00f0 1A70 strb r2, [r3] +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2755 .loc 1 1554 11 is_stmt 1 view .LVU911 +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2756 .loc 1 1554 15 is_stmt 0 view .LVU912 + 2757 00f2 636A ldr r3, [r4, #36] +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2758 .loc 1 1554 25 view .LVU913 + 2759 00f4 0133 adds r3, r3, #1 + 2760 00f6 6362 str r3, [r4, #36] +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2761 .loc 1 1556 11 is_stmt 1 view .LVU914 +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2762 .loc 1 1556 15 is_stmt 0 view .LVU915 + 2763 00f8 638D ldrh r3, [r4, #42] + 2764 00fa 9BB2 uxth r3, r3 +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2765 .loc 1 1556 26 view .LVU916 + 2766 00fc 013B subs r3, r3, #1 + 2767 00fe 9BB2 uxth r3, r3 + 2768 0100 6385 strh r3, [r4, #42] @ movhi + 2769 .L198: +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2770 .loc 1 1559 9 is_stmt 1 view .LVU917 +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2771 .loc 1 1559 16 is_stmt 0 view .LVU918 + 2772 0102 0120 movs r0, #1 + 2773 0104 2EE0 b .L192 + 2774 .L205: +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2775 .loc 1 1572 5 is_stmt 1 view .LVU919 +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2776 .loc 1 1572 9 is_stmt 0 view .LVU920 + 2777 0106 3A46 mov r2, r7 + 2778 0108 2946 mov r1, r5 + 2779 010a 2046 mov r0, r4 + 2780 010c FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2781 .LVL156: +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2782 .loc 1 1572 8 view .LVU921 + 2783 0110 30B1 cbz r0, .L200 +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2784 .loc 1 1575 7 is_stmt 1 view .LVU922 +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2785 .loc 1 1575 11 is_stmt 0 view .LVU923 + 2786 0112 2268 ldr r2, [r4] +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2787 .loc 1 1575 21 view .LVU924 + 2788 0114 5368 ldr r3, [r2, #4] +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2789 .loc 1 1575 27 view .LVU925 + 2790 0116 43F40043 orr r3, r3, #32768 + 2791 011a 5360 str r3, [r2, #4] +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2792 .loc 1 1576 7 is_stmt 1 view .LVU926 + ARM GAS /tmp/ccE2rRGE.s page 183 + + +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2793 .loc 1 1576 14 is_stmt 0 view .LVU927 + 2794 011c 0120 movs r0, #1 + 2795 011e 21E0 b .L192 + 2796 .L200: +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2797 .loc 1 1580 5 is_stmt 1 view .LVU928 + 2798 0120 2368 ldr r3, [r4] + 2799 0122 2022 movs r2, #32 + 2800 0124 DA61 str r2, [r3, #28] +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2801 .loc 1 1583 5 view .LVU929 +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2802 .loc 1 1583 9 is_stmt 0 view .LVU930 + 2803 0126 0097 str r7, [sp] + 2804 0128 2B46 mov r3, r5 + 2805 012a 0122 movs r2, #1 + 2806 012c 4FF40041 mov r1, #32768 + 2807 0130 2046 mov r0, r4 + 2808 0132 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2809 .LVL157: +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2810 .loc 1 1583 8 view .LVU931 + 2811 0136 30B1 cbz r0, .L201 +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2812 .loc 1 1586 7 is_stmt 1 view .LVU932 +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2813 .loc 1 1586 11 is_stmt 0 view .LVU933 + 2814 0138 2268 ldr r2, [r4] +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2815 .loc 1 1586 21 view .LVU934 + 2816 013a 5368 ldr r3, [r2, #4] +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2817 .loc 1 1586 27 view .LVU935 + 2818 013c 43F40043 orr r3, r3, #32768 + 2819 0140 5360 str r3, [r2, #4] +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2820 .loc 1 1587 7 is_stmt 1 view .LVU936 +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2821 .loc 1 1587 14 is_stmt 0 view .LVU937 + 2822 0142 0120 movs r0, #1 + 2823 0144 0EE0 b .L192 + 2824 .L201: +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2825 .loc 1 1591 5 is_stmt 1 view .LVU938 +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2826 .loc 1 1591 9 is_stmt 0 view .LVU939 + 2827 0146 2268 ldr r2, [r4] +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2828 .loc 1 1591 19 view .LVU940 + 2829 0148 5368 ldr r3, [r2, #4] +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2830 .loc 1 1591 25 view .LVU941 + 2831 014a 43F40043 orr r3, r3, #32768 + 2832 014e 5360 str r3, [r2, #4] +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2833 .loc 1 1593 5 is_stmt 1 view .LVU942 + ARM GAS /tmp/ccE2rRGE.s page 184 + + +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2834 .loc 1 1593 17 is_stmt 0 view .LVU943 + 2835 0150 2023 movs r3, #32 + 2836 0152 84F84130 strb r3, [r4, #65] +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2837 .loc 1 1594 5 is_stmt 1 view .LVU944 +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2838 .loc 1 1594 17 is_stmt 0 view .LVU945 + 2839 0156 0023 movs r3, #0 + 2840 0158 84F84230 strb r3, [r4, #66] +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2841 .loc 1 1597 5 is_stmt 1 view .LVU946 +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2842 .loc 1 1597 5 view .LVU947 + 2843 015c 84F84030 strb r3, [r4, #64] +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2844 .loc 1 1597 5 view .LVU948 +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2845 .loc 1 1599 5 view .LVU949 +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2846 .loc 1 1599 12 is_stmt 0 view .LVU950 + 2847 0160 00E0 b .L192 + 2848 .LVL158: + 2849 .L202: +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2850 .loc 1 1603 12 view .LVU951 + 2851 0162 0220 movs r0, #2 + 2852 .LVL159: + 2853 .L192: +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2854 .loc 1 1605 1 view .LVU952 + 2855 0164 02B0 add sp, sp, #8 + 2856 .cfi_remember_state + 2857 .cfi_def_cfa_offset 24 + 2858 @ sp needed + 2859 0166 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 2860 .LVL160: + 2861 .L203: + 2862 .cfi_restore_state +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2863 .loc 1 1503 5 view .LVU953 + 2864 016a 0220 movs r0, #2 + 2865 .LVL161: +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2866 .loc 1 1503 5 view .LVU954 + 2867 016c FAE7 b .L192 + 2868 .cfi_endproc + 2869 .LFE137: + 2871 .section .text.HAL_I2C_Master_Transmit_IT,"ax",%progbits + 2872 .align 1 + 2873 .global HAL_I2C_Master_Transmit_IT + 2874 .syntax unified + 2875 .thumb + 2876 .thumb_func + 2878 HAL_I2C_Master_Transmit_IT: + 2879 .LVL162: + 2880 .LFB138: + ARM GAS /tmp/ccE2rRGE.s page 185 + + +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 2881 .loc 1 1619 1 is_stmt 1 view -0 + 2882 .cfi_startproc + 2883 @ args = 0, pretend = 0, frame = 0 + 2884 @ frame_needed = 0, uses_anonymous_args = 0 +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 2885 .loc 1 1619 1 is_stmt 0 view .LVU956 + 2886 0000 30B5 push {r4, r5, lr} + 2887 .cfi_def_cfa_offset 12 + 2888 .cfi_offset 4, -12 + 2889 .cfi_offset 5, -8 + 2890 .cfi_offset 14, -4 + 2891 0002 83B0 sub sp, sp, #12 + 2892 .cfi_def_cfa_offset 24 + 2893 0004 0446 mov r4, r0 +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2894 .loc 1 1620 3 is_stmt 1 view .LVU957 +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2895 .loc 1 1622 3 view .LVU958 +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2896 .loc 1 1622 11 is_stmt 0 view .LVU959 + 2897 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 2898 .LVL163: +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2899 .loc 1 1622 11 view .LVU960 + 2900 000a C0B2 uxtb r0, r0 +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2901 .loc 1 1622 6 view .LVU961 + 2902 000c 2028 cmp r0, #32 + 2903 000e 37D1 bne .L210 +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2904 .loc 1 1624 5 is_stmt 1 view .LVU962 +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2905 .loc 1 1624 9 is_stmt 0 view .LVU963 + 2906 0010 2068 ldr r0, [r4] + 2907 0012 8069 ldr r0, [r0, #24] +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2908 .loc 1 1624 8 view .LVU964 + 2909 0014 10F4004F tst r0, #32768 + 2910 0018 34D1 bne .L211 +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2911 .loc 1 1630 5 is_stmt 1 view .LVU965 +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2912 .loc 1 1630 5 view .LVU966 + 2913 001a 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 2914 001e 0128 cmp r0, #1 + 2915 0020 32D0 beq .L212 +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2916 .loc 1 1630 5 discriminator 2 view .LVU967 + 2917 0022 0120 movs r0, #1 + 2918 0024 84F84000 strb r0, [r4, #64] +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2919 .loc 1 1630 5 discriminator 2 view .LVU968 +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2920 .loc 1 1632 5 discriminator 2 view .LVU969 +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2921 .loc 1 1632 23 is_stmt 0 discriminator 2 view .LVU970 + ARM GAS /tmp/ccE2rRGE.s page 186 + + + 2922 0028 2120 movs r0, #33 + 2923 002a 84F84100 strb r0, [r4, #65] +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2924 .loc 1 1633 5 is_stmt 1 discriminator 2 view .LVU971 +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2925 .loc 1 1633 23 is_stmt 0 discriminator 2 view .LVU972 + 2926 002e 1020 movs r0, #16 + 2927 0030 84F84200 strb r0, [r4, #66] +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2928 .loc 1 1634 5 is_stmt 1 discriminator 2 view .LVU973 +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2929 .loc 1 1634 23 is_stmt 0 discriminator 2 view .LVU974 + 2930 0034 0020 movs r0, #0 + 2931 0036 6064 str r0, [r4, #68] +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2932 .loc 1 1637 5 is_stmt 1 discriminator 2 view .LVU975 +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2933 .loc 1 1637 23 is_stmt 0 discriminator 2 view .LVU976 + 2934 0038 6262 str r2, [r4, #36] +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2935 .loc 1 1638 5 is_stmt 1 discriminator 2 view .LVU977 +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2936 .loc 1 1638 23 is_stmt 0 discriminator 2 view .LVU978 + 2937 003a 6385 strh r3, [r4, #42] @ movhi +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2938 .loc 1 1639 5 is_stmt 1 discriminator 2 view .LVU979 +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2939 .loc 1 1639 23 is_stmt 0 discriminator 2 view .LVU980 + 2940 003c 134B ldr r3, .L214 + 2941 .LVL164: +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2942 .loc 1 1639 23 discriminator 2 view .LVU981 + 2943 003e E362 str r3, [r4, #44] + 2944 .LVL165: +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2945 .loc 1 1640 5 is_stmt 1 discriminator 2 view .LVU982 +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2946 .loc 1 1640 23 is_stmt 0 discriminator 2 view .LVU983 + 2947 0040 134B ldr r3, .L214+4 + 2948 0042 6363 str r3, [r4, #52] +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2949 .loc 1 1642 5 is_stmt 1 discriminator 2 view .LVU984 +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2950 .loc 1 1642 13 is_stmt 0 discriminator 2 view .LVU985 + 2951 0044 638D ldrh r3, [r4, #42] + 2952 0046 9BB2 uxth r3, r3 +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2953 .loc 1 1642 8 discriminator 2 view .LVU986 + 2954 0048 FF2B cmp r3, #255 + 2955 004a 14D9 bls .L208 +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 2956 .loc 1 1644 7 is_stmt 1 view .LVU987 +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 2957 .loc 1 1644 22 is_stmt 0 view .LVU988 + 2958 004c FF23 movs r3, #255 + 2959 004e 2385 strh r3, [r4, #40] @ movhi +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 187 + + + 2960 .loc 1 1645 7 is_stmt 1 view .LVU989 + 2961 .LVL166: +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2962 .loc 1 1645 16 is_stmt 0 view .LVU990 + 2963 0050 4FF08073 mov r3, #16777216 + 2964 .LVL167: + 2965 .L209: +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2966 .loc 1 1655 5 is_stmt 1 view .LVU991 + 2967 0054 0F4A ldr r2, .L214+8 + 2968 .LVL168: +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2969 .loc 1 1655 5 is_stmt 0 view .LVU992 + 2970 0056 0092 str r2, [sp] + 2971 .LVL169: +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2972 .loc 1 1655 5 view .LVU993 + 2973 0058 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 2974 005c 2046 mov r0, r4 + 2975 005e FFF7FEFF bl I2C_TransferConfig + 2976 .LVL170: +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2977 .loc 1 1658 5 is_stmt 1 view .LVU994 +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2978 .loc 1 1658 5 view .LVU995 + 2979 0062 0025 movs r5, #0 + 2980 0064 84F84050 strb r5, [r4, #64] +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2981 .loc 1 1658 5 view .LVU996 +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2982 .loc 1 1668 5 view .LVU997 + 2983 0068 0121 movs r1, #1 + 2984 006a 2046 mov r0, r4 + 2985 006c FFF7FEFF bl I2C_Enable_IRQ + 2986 .LVL171: +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2987 .loc 1 1670 5 view .LVU998 +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2988 .loc 1 1670 12 is_stmt 0 view .LVU999 + 2989 0070 2846 mov r0, r5 + 2990 .LVL172: + 2991 .L207: +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2992 .loc 1 1676 1 view .LVU1000 + 2993 0072 03B0 add sp, sp, #12 + 2994 .cfi_remember_state + 2995 .cfi_def_cfa_offset 12 + 2996 @ sp needed + 2997 0074 30BD pop {r4, r5, pc} + 2998 .LVL173: + 2999 .L208: + 3000 .cfi_restore_state +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3001 .loc 1 1649 7 is_stmt 1 view .LVU1001 +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3002 .loc 1 1649 28 is_stmt 0 view .LVU1002 + 3003 0076 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccE2rRGE.s page 188 + + +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3004 .loc 1 1649 22 view .LVU1003 + 3005 0078 2385 strh r3, [r4, #40] @ movhi +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3006 .loc 1 1650 7 is_stmt 1 view .LVU1004 + 3007 .LVL174: +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3008 .loc 1 1650 16 is_stmt 0 view .LVU1005 + 3009 007a 4FF00073 mov r3, #33554432 + 3010 007e E9E7 b .L209 + 3011 .LVL175: + 3012 .L210: +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3013 .loc 1 1674 12 view .LVU1006 + 3014 0080 0220 movs r0, #2 + 3015 0082 F6E7 b .L207 + 3016 .L211: +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3017 .loc 1 1626 14 view .LVU1007 + 3018 0084 0220 movs r0, #2 + 3019 0086 F4E7 b .L207 + 3020 .L212: +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3021 .loc 1 1630 5 view .LVU1008 + 3022 0088 0220 movs r0, #2 + 3023 008a F2E7 b .L207 + 3024 .L215: + 3025 .align 2 + 3026 .L214: + 3027 008c 0000FFFF .word -65536 + 3028 0090 00000000 .word I2C_Master_ISR_IT + 3029 0094 00200080 .word -2147475456 + 3030 .cfi_endproc + 3031 .LFE138: + 3033 .section .text.HAL_I2C_Master_Receive_IT,"ax",%progbits + 3034 .align 1 + 3035 .global HAL_I2C_Master_Receive_IT + 3036 .syntax unified + 3037 .thumb + 3038 .thumb_func + 3040 HAL_I2C_Master_Receive_IT: + 3041 .LVL176: + 3042 .LFB139: +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 3043 .loc 1 1690 1 is_stmt 1 view -0 + 3044 .cfi_startproc + 3045 @ args = 0, pretend = 0, frame = 0 + 3046 @ frame_needed = 0, uses_anonymous_args = 0 +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 3047 .loc 1 1690 1 is_stmt 0 view .LVU1010 + 3048 0000 30B5 push {r4, r5, lr} + 3049 .cfi_def_cfa_offset 12 + 3050 .cfi_offset 4, -12 + 3051 .cfi_offset 5, -8 + 3052 .cfi_offset 14, -4 + 3053 0002 83B0 sub sp, sp, #12 + 3054 .cfi_def_cfa_offset 24 + ARM GAS /tmp/ccE2rRGE.s page 189 + + + 3055 0004 0446 mov r4, r0 +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3056 .loc 1 1691 3 is_stmt 1 view .LVU1011 +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3057 .loc 1 1693 3 view .LVU1012 +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3058 .loc 1 1693 11 is_stmt 0 view .LVU1013 + 3059 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3060 .LVL177: +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3061 .loc 1 1693 11 view .LVU1014 + 3062 000a C0B2 uxtb r0, r0 +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3063 .loc 1 1693 6 view .LVU1015 + 3064 000c 2028 cmp r0, #32 + 3065 000e 37D1 bne .L220 +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3066 .loc 1 1695 5 is_stmt 1 view .LVU1016 +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3067 .loc 1 1695 9 is_stmt 0 view .LVU1017 + 3068 0010 2068 ldr r0, [r4] + 3069 0012 8069 ldr r0, [r0, #24] +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3070 .loc 1 1695 8 view .LVU1018 + 3071 0014 10F4004F tst r0, #32768 + 3072 0018 34D1 bne .L221 +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3073 .loc 1 1701 5 is_stmt 1 view .LVU1019 +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3074 .loc 1 1701 5 view .LVU1020 + 3075 001a 94F84000 ldrb r0, [r4, #64] @ zero_extendqisi2 + 3076 001e 0128 cmp r0, #1 + 3077 0020 32D0 beq .L222 +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3078 .loc 1 1701 5 discriminator 2 view .LVU1021 + 3079 0022 0120 movs r0, #1 + 3080 0024 84F84000 strb r0, [r4, #64] +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3081 .loc 1 1701 5 discriminator 2 view .LVU1022 +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3082 .loc 1 1703 5 discriminator 2 view .LVU1023 +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3083 .loc 1 1703 23 is_stmt 0 discriminator 2 view .LVU1024 + 3084 0028 2220 movs r0, #34 + 3085 002a 84F84100 strb r0, [r4, #65] +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3086 .loc 1 1704 5 is_stmt 1 discriminator 2 view .LVU1025 +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3087 .loc 1 1704 23 is_stmt 0 discriminator 2 view .LVU1026 + 3088 002e 1020 movs r0, #16 + 3089 0030 84F84200 strb r0, [r4, #66] +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3090 .loc 1 1705 5 is_stmt 1 discriminator 2 view .LVU1027 +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3091 .loc 1 1705 23 is_stmt 0 discriminator 2 view .LVU1028 + 3092 0034 0020 movs r0, #0 + 3093 0036 6064 str r0, [r4, #68] + ARM GAS /tmp/ccE2rRGE.s page 190 + + +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3094 .loc 1 1708 5 is_stmt 1 discriminator 2 view .LVU1029 +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3095 .loc 1 1708 23 is_stmt 0 discriminator 2 view .LVU1030 + 3096 0038 6262 str r2, [r4, #36] +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3097 .loc 1 1709 5 is_stmt 1 discriminator 2 view .LVU1031 +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3098 .loc 1 1709 23 is_stmt 0 discriminator 2 view .LVU1032 + 3099 003a 6385 strh r3, [r4, #42] @ movhi +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3100 .loc 1 1710 5 is_stmt 1 discriminator 2 view .LVU1033 +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3101 .loc 1 1710 23 is_stmt 0 discriminator 2 view .LVU1034 + 3102 003c 134B ldr r3, .L224 + 3103 .LVL178: +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3104 .loc 1 1710 23 discriminator 2 view .LVU1035 + 3105 003e E362 str r3, [r4, #44] + 3106 .LVL179: +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3107 .loc 1 1711 5 is_stmt 1 discriminator 2 view .LVU1036 +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3108 .loc 1 1711 23 is_stmt 0 discriminator 2 view .LVU1037 + 3109 0040 134B ldr r3, .L224+4 + 3110 0042 6363 str r3, [r4, #52] +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3111 .loc 1 1713 5 is_stmt 1 discriminator 2 view .LVU1038 +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3112 .loc 1 1713 13 is_stmt 0 discriminator 2 view .LVU1039 + 3113 0044 638D ldrh r3, [r4, #42] + 3114 0046 9BB2 uxth r3, r3 +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3115 .loc 1 1713 8 discriminator 2 view .LVU1040 + 3116 0048 FF2B cmp r3, #255 + 3117 004a 14D9 bls .L218 +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3118 .loc 1 1715 7 is_stmt 1 view .LVU1041 +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3119 .loc 1 1715 22 is_stmt 0 view .LVU1042 + 3120 004c FF23 movs r3, #255 + 3121 004e 2385 strh r3, [r4, #40] @ movhi +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3122 .loc 1 1716 7 is_stmt 1 view .LVU1043 + 3123 .LVL180: +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3124 .loc 1 1716 16 is_stmt 0 view .LVU1044 + 3125 0050 4FF08073 mov r3, #16777216 + 3126 .LVL181: + 3127 .L219: +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3128 .loc 1 1726 5 is_stmt 1 view .LVU1045 + 3129 0054 0F4A ldr r2, .L224+8 + 3130 .LVL182: +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3131 .loc 1 1726 5 is_stmt 0 view .LVU1046 + 3132 0056 0092 str r2, [sp] + ARM GAS /tmp/ccE2rRGE.s page 191 + + + 3133 .LVL183: +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3134 .loc 1 1726 5 view .LVU1047 + 3135 0058 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 3136 005c 2046 mov r0, r4 + 3137 005e FFF7FEFF bl I2C_TransferConfig + 3138 .LVL184: +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3139 .loc 1 1729 5 is_stmt 1 view .LVU1048 +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3140 .loc 1 1729 5 view .LVU1049 + 3141 0062 0025 movs r5, #0 + 3142 0064 84F84050 strb r5, [r4, #64] +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3143 .loc 1 1729 5 view .LVU1050 +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3144 .loc 1 1739 5 view .LVU1051 + 3145 0068 0221 movs r1, #2 + 3146 006a 2046 mov r0, r4 + 3147 006c FFF7FEFF bl I2C_Enable_IRQ + 3148 .LVL185: +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3149 .loc 1 1741 5 view .LVU1052 +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3150 .loc 1 1741 12 is_stmt 0 view .LVU1053 + 3151 0070 2846 mov r0, r5 + 3152 .LVL186: + 3153 .L217: +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3154 .loc 1 1747 1 view .LVU1054 + 3155 0072 03B0 add sp, sp, #12 + 3156 .cfi_remember_state + 3157 .cfi_def_cfa_offset 12 + 3158 @ sp needed + 3159 0074 30BD pop {r4, r5, pc} + 3160 .LVL187: + 3161 .L218: + 3162 .cfi_restore_state +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3163 .loc 1 1720 7 is_stmt 1 view .LVU1055 +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3164 .loc 1 1720 28 is_stmt 0 view .LVU1056 + 3165 0076 638D ldrh r3, [r4, #42] +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3166 .loc 1 1720 22 view .LVU1057 + 3167 0078 2385 strh r3, [r4, #40] @ movhi +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3168 .loc 1 1721 7 is_stmt 1 view .LVU1058 + 3169 .LVL188: +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3170 .loc 1 1721 16 is_stmt 0 view .LVU1059 + 3171 007a 4FF00073 mov r3, #33554432 + 3172 007e E9E7 b .L219 + 3173 .LVL189: + 3174 .L220: +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3175 .loc 1 1745 12 view .LVU1060 + ARM GAS /tmp/ccE2rRGE.s page 192 + + + 3176 0080 0220 movs r0, #2 + 3177 0082 F6E7 b .L217 + 3178 .L221: +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3179 .loc 1 1697 14 view .LVU1061 + 3180 0084 0220 movs r0, #2 + 3181 0086 F4E7 b .L217 + 3182 .L222: +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3183 .loc 1 1701 5 view .LVU1062 + 3184 0088 0220 movs r0, #2 + 3185 008a F2E7 b .L217 + 3186 .L225: + 3187 .align 2 + 3188 .L224: + 3189 008c 0000FFFF .word -65536 + 3190 0090 00000000 .word I2C_Master_ISR_IT + 3191 0094 00240080 .word -2147474432 + 3192 .cfi_endproc + 3193 .LFE139: + 3195 .section .text.HAL_I2C_Slave_Transmit_IT,"ax",%progbits + 3196 .align 1 + 3197 .global HAL_I2C_Slave_Transmit_IT + 3198 .syntax unified + 3199 .thumb + 3200 .thumb_func + 3202 HAL_I2C_Slave_Transmit_IT: + 3203 .LVL190: + 3204 .LFB140: +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3205 .loc 1 1758 1 is_stmt 1 view -0 + 3206 .cfi_startproc + 3207 @ args = 0, pretend = 0, frame = 0 + 3208 @ frame_needed = 0, uses_anonymous_args = 0 +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3209 .loc 1 1758 1 is_stmt 0 view .LVU1064 + 3210 0000 38B5 push {r3, r4, r5, lr} + 3211 .cfi_def_cfa_offset 16 + 3212 .cfi_offset 3, -16 + 3213 .cfi_offset 4, -12 + 3214 .cfi_offset 5, -8 + 3215 .cfi_offset 14, -4 +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3216 .loc 1 1759 3 is_stmt 1 view .LVU1065 +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3217 .loc 1 1759 11 is_stmt 0 view .LVU1066 + 3218 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 3219 0006 DBB2 uxtb r3, r3 +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3220 .loc 1 1759 6 view .LVU1067 + 3221 0008 202B cmp r3, #32 + 3222 000a 23D1 bne .L228 +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3223 .loc 1 1762 5 is_stmt 1 view .LVU1068 +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3224 .loc 1 1762 5 view .LVU1069 + 3225 000c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + ARM GAS /tmp/ccE2rRGE.s page 193 + + + 3226 0010 012B cmp r3, #1 + 3227 0012 21D0 beq .L229 +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3228 .loc 1 1762 5 discriminator 2 view .LVU1070 + 3229 0014 0123 movs r3, #1 + 3230 0016 80F84030 strb r3, [r0, #64] +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3231 .loc 1 1762 5 discriminator 2 view .LVU1071 +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3232 .loc 1 1764 5 discriminator 2 view .LVU1072 +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3233 .loc 1 1764 23 is_stmt 0 discriminator 2 view .LVU1073 + 3234 001a 2123 movs r3, #33 + 3235 001c 80F84130 strb r3, [r0, #65] +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3236 .loc 1 1765 5 is_stmt 1 discriminator 2 view .LVU1074 +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3237 .loc 1 1765 23 is_stmt 0 discriminator 2 view .LVU1075 + 3238 0020 2023 movs r3, #32 + 3239 0022 80F84230 strb r3, [r0, #66] +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3240 .loc 1 1766 5 is_stmt 1 discriminator 2 view .LVU1076 +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3241 .loc 1 1766 23 is_stmt 0 discriminator 2 view .LVU1077 + 3242 0026 0024 movs r4, #0 + 3243 0028 4464 str r4, [r0, #68] +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3244 .loc 1 1769 5 is_stmt 1 discriminator 2 view .LVU1078 +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3245 .loc 1 1769 9 is_stmt 0 discriminator 2 view .LVU1079 + 3246 002a 0568 ldr r5, [r0] +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3247 .loc 1 1769 19 discriminator 2 view .LVU1080 + 3248 002c 6B68 ldr r3, [r5, #4] +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3249 .loc 1 1769 25 discriminator 2 view .LVU1081 + 3250 002e 23F40043 bic r3, r3, #32768 + 3251 0032 6B60 str r3, [r5, #4] +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3252 .loc 1 1772 5 is_stmt 1 discriminator 2 view .LVU1082 +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3253 .loc 1 1772 23 is_stmt 0 discriminator 2 view .LVU1083 + 3254 0034 4162 str r1, [r0, #36] +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3255 .loc 1 1773 5 is_stmt 1 discriminator 2 view .LVU1084 +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3256 .loc 1 1773 23 is_stmt 0 discriminator 2 view .LVU1085 + 3257 0036 4285 strh r2, [r0, #42] @ movhi +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3258 .loc 1 1774 5 is_stmt 1 discriminator 2 view .LVU1086 +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3259 .loc 1 1774 29 is_stmt 0 discriminator 2 view .LVU1087 + 3260 0038 438D ldrh r3, [r0, #42] +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3261 .loc 1 1774 23 discriminator 2 view .LVU1088 + 3262 003a 0385 strh r3, [r0, #40] @ movhi +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + ARM GAS /tmp/ccE2rRGE.s page 194 + + + 3263 .loc 1 1775 5 is_stmt 1 discriminator 2 view .LVU1089 +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3264 .loc 1 1775 23 is_stmt 0 discriminator 2 view .LVU1090 + 3265 003c 074B ldr r3, .L231 + 3266 003e C362 str r3, [r0, #44] +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3267 .loc 1 1776 5 is_stmt 1 discriminator 2 view .LVU1091 +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3268 .loc 1 1776 23 is_stmt 0 discriminator 2 view .LVU1092 + 3269 0040 074B ldr r3, .L231+4 + 3270 0042 4363 str r3, [r0, #52] +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3271 .loc 1 1779 5 is_stmt 1 discriminator 2 view .LVU1093 +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3272 .loc 1 1779 5 discriminator 2 view .LVU1094 + 3273 0044 80F84040 strb r4, [r0, #64] +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3274 .loc 1 1779 5 discriminator 2 view .LVU1095 +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3275 .loc 1 1789 5 discriminator 2 view .LVU1096 + 3276 0048 48F20101 movw r1, #32769 + 3277 .LVL191: +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3278 .loc 1 1789 5 is_stmt 0 discriminator 2 view .LVU1097 + 3279 004c FFF7FEFF bl I2C_Enable_IRQ + 3280 .LVL192: +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3281 .loc 1 1791 5 is_stmt 1 discriminator 2 view .LVU1098 +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3282 .loc 1 1791 12 is_stmt 0 discriminator 2 view .LVU1099 + 3283 0050 2046 mov r0, r4 + 3284 .L227: +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3285 .loc 1 1797 1 view .LVU1100 + 3286 0052 38BD pop {r3, r4, r5, pc} + 3287 .LVL193: + 3288 .L228: +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3289 .loc 1 1795 12 view .LVU1101 + 3290 0054 0220 movs r0, #2 + 3291 .LVL194: +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3292 .loc 1 1795 12 view .LVU1102 + 3293 0056 FCE7 b .L227 + 3294 .LVL195: + 3295 .L229: +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3296 .loc 1 1762 5 view .LVU1103 + 3297 0058 0220 movs r0, #2 + 3298 .LVL196: +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3299 .loc 1 1762 5 view .LVU1104 + 3300 005a FAE7 b .L227 + 3301 .L232: + 3302 .align 2 + 3303 .L231: + 3304 005c 0000FFFF .word -65536 + ARM GAS /tmp/ccE2rRGE.s page 195 + + + 3305 0060 00000000 .word I2C_Slave_ISR_IT + 3306 .cfi_endproc + 3307 .LFE140: + 3309 .section .text.HAL_I2C_Slave_Receive_IT,"ax",%progbits + 3310 .align 1 + 3311 .global HAL_I2C_Slave_Receive_IT + 3312 .syntax unified + 3313 .thumb + 3314 .thumb_func + 3316 HAL_I2C_Slave_Receive_IT: + 3317 .LVL197: + 3318 .LFB141: +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3319 .loc 1 1808 1 is_stmt 1 view -0 + 3320 .cfi_startproc + 3321 @ args = 0, pretend = 0, frame = 0 + 3322 @ frame_needed = 0, uses_anonymous_args = 0 +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3323 .loc 1 1808 1 is_stmt 0 view .LVU1106 + 3324 0000 38B5 push {r3, r4, r5, lr} + 3325 .cfi_def_cfa_offset 16 + 3326 .cfi_offset 3, -16 + 3327 .cfi_offset 4, -12 + 3328 .cfi_offset 5, -8 + 3329 .cfi_offset 14, -4 +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3330 .loc 1 1809 3 is_stmt 1 view .LVU1107 +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3331 .loc 1 1809 11 is_stmt 0 view .LVU1108 + 3332 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 3333 0006 DBB2 uxtb r3, r3 +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3334 .loc 1 1809 6 view .LVU1109 + 3335 0008 202B cmp r3, #32 + 3336 000a 23D1 bne .L235 +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3337 .loc 1 1812 5 is_stmt 1 view .LVU1110 +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3338 .loc 1 1812 5 view .LVU1111 + 3339 000c 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 3340 0010 012B cmp r3, #1 + 3341 0012 21D0 beq .L236 +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3342 .loc 1 1812 5 discriminator 2 view .LVU1112 + 3343 0014 0123 movs r3, #1 + 3344 0016 80F84030 strb r3, [r0, #64] +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3345 .loc 1 1812 5 discriminator 2 view .LVU1113 +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3346 .loc 1 1814 5 discriminator 2 view .LVU1114 +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3347 .loc 1 1814 23 is_stmt 0 discriminator 2 view .LVU1115 + 3348 001a 2223 movs r3, #34 + 3349 001c 80F84130 strb r3, [r0, #65] +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3350 .loc 1 1815 5 is_stmt 1 discriminator 2 view .LVU1116 +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + ARM GAS /tmp/ccE2rRGE.s page 196 + + + 3351 .loc 1 1815 23 is_stmt 0 discriminator 2 view .LVU1117 + 3352 0020 2023 movs r3, #32 + 3353 0022 80F84230 strb r3, [r0, #66] +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3354 .loc 1 1816 5 is_stmt 1 discriminator 2 view .LVU1118 +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3355 .loc 1 1816 23 is_stmt 0 discriminator 2 view .LVU1119 + 3356 0026 0024 movs r4, #0 + 3357 0028 4464 str r4, [r0, #68] +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3358 .loc 1 1819 5 is_stmt 1 discriminator 2 view .LVU1120 +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3359 .loc 1 1819 9 is_stmt 0 discriminator 2 view .LVU1121 + 3360 002a 0568 ldr r5, [r0] +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3361 .loc 1 1819 19 discriminator 2 view .LVU1122 + 3362 002c 6B68 ldr r3, [r5, #4] +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3363 .loc 1 1819 25 discriminator 2 view .LVU1123 + 3364 002e 23F40043 bic r3, r3, #32768 + 3365 0032 6B60 str r3, [r5, #4] +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3366 .loc 1 1822 5 is_stmt 1 discriminator 2 view .LVU1124 +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3367 .loc 1 1822 23 is_stmt 0 discriminator 2 view .LVU1125 + 3368 0034 4162 str r1, [r0, #36] +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3369 .loc 1 1823 5 is_stmt 1 discriminator 2 view .LVU1126 +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3370 .loc 1 1823 23 is_stmt 0 discriminator 2 view .LVU1127 + 3371 0036 4285 strh r2, [r0, #42] @ movhi +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3372 .loc 1 1824 5 is_stmt 1 discriminator 2 view .LVU1128 +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3373 .loc 1 1824 29 is_stmt 0 discriminator 2 view .LVU1129 + 3374 0038 438D ldrh r3, [r0, #42] +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3375 .loc 1 1824 23 discriminator 2 view .LVU1130 + 3376 003a 0385 strh r3, [r0, #40] @ movhi +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3377 .loc 1 1825 5 is_stmt 1 discriminator 2 view .LVU1131 +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3378 .loc 1 1825 23 is_stmt 0 discriminator 2 view .LVU1132 + 3379 003c 074B ldr r3, .L238 + 3380 003e C362 str r3, [r0, #44] +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3381 .loc 1 1826 5 is_stmt 1 discriminator 2 view .LVU1133 +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3382 .loc 1 1826 23 is_stmt 0 discriminator 2 view .LVU1134 + 3383 0040 074B ldr r3, .L238+4 + 3384 0042 4363 str r3, [r0, #52] +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3385 .loc 1 1829 5 is_stmt 1 discriminator 2 view .LVU1135 +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3386 .loc 1 1829 5 discriminator 2 view .LVU1136 + 3387 0044 80F84040 strb r4, [r0, #64] +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 197 + + + 3388 .loc 1 1829 5 discriminator 2 view .LVU1137 +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3389 .loc 1 1839 5 discriminator 2 view .LVU1138 + 3390 0048 48F20201 movw r1, #32770 + 3391 .LVL198: +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3392 .loc 1 1839 5 is_stmt 0 discriminator 2 view .LVU1139 + 3393 004c FFF7FEFF bl I2C_Enable_IRQ + 3394 .LVL199: +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3395 .loc 1 1841 5 is_stmt 1 discriminator 2 view .LVU1140 +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3396 .loc 1 1841 12 is_stmt 0 discriminator 2 view .LVU1141 + 3397 0050 2046 mov r0, r4 + 3398 .L234: +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3399 .loc 1 1847 1 view .LVU1142 + 3400 0052 38BD pop {r3, r4, r5, pc} + 3401 .LVL200: + 3402 .L235: +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3403 .loc 1 1845 12 view .LVU1143 + 3404 0054 0220 movs r0, #2 + 3405 .LVL201: +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3406 .loc 1 1845 12 view .LVU1144 + 3407 0056 FCE7 b .L234 + 3408 .LVL202: + 3409 .L236: +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3410 .loc 1 1812 5 view .LVU1145 + 3411 0058 0220 movs r0, #2 + 3412 .LVL203: +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3413 .loc 1 1812 5 view .LVU1146 + 3414 005a FAE7 b .L234 + 3415 .L239: + 3416 .align 2 + 3417 .L238: + 3418 005c 0000FFFF .word -65536 + 3419 0060 00000000 .word I2C_Slave_ISR_IT + 3420 .cfi_endproc + 3421 .LFE141: + 3423 .section .text.HAL_I2C_Master_Transmit_DMA,"ax",%progbits + 3424 .align 1 + 3425 .global HAL_I2C_Master_Transmit_DMA + 3426 .syntax unified + 3427 .thumb + 3428 .thumb_func + 3430 HAL_I2C_Master_Transmit_DMA: + 3431 .LVL204: + 3432 .LFB142: +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 3433 .loc 1 1861 1 is_stmt 1 view -0 + 3434 .cfi_startproc + 3435 @ args = 0, pretend = 0, frame = 0 + 3436 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccE2rRGE.s page 198 + + +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 3437 .loc 1 1861 1 is_stmt 0 view .LVU1148 + 3438 0000 70B5 push {r4, r5, r6, lr} + 3439 .cfi_def_cfa_offset 16 + 3440 .cfi_offset 4, -16 + 3441 .cfi_offset 5, -12 + 3442 .cfi_offset 6, -8 + 3443 .cfi_offset 14, -4 + 3444 0002 82B0 sub sp, sp, #8 + 3445 .cfi_def_cfa_offset 24 + 3446 0004 0446 mov r4, r0 +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 3447 .loc 1 1862 3 is_stmt 1 view .LVU1149 +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3448 .loc 1 1863 3 view .LVU1150 +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3449 .loc 1 1865 3 view .LVU1151 +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3450 .loc 1 1865 11 is_stmt 0 view .LVU1152 + 3451 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3452 .LVL205: +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3453 .loc 1 1865 11 view .LVU1153 + 3454 000a C0B2 uxtb r0, r0 +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3455 .loc 1 1865 6 view .LVU1154 + 3456 000c 2028 cmp r0, #32 + 3457 000e 40F08D80 bne .L249 + 3458 0012 0D46 mov r5, r1 + 3459 0014 1146 mov r1, r2 + 3460 .LVL206: +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3461 .loc 1 1867 5 is_stmt 1 view .LVU1155 +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3462 .loc 1 1867 9 is_stmt 0 view .LVU1156 + 3463 0016 2268 ldr r2, [r4] + 3464 .LVL207: +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3465 .loc 1 1867 9 view .LVU1157 + 3466 0018 9269 ldr r2, [r2, #24] +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3467 .loc 1 1867 8 view .LVU1158 + 3468 001a 12F4004F tst r2, #32768 + 3469 001e 40F08880 bne .L250 +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3470 .loc 1 1873 5 is_stmt 1 view .LVU1159 +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3471 .loc 1 1873 5 view .LVU1160 + 3472 0022 94F84020 ldrb r2, [r4, #64] @ zero_extendqisi2 + 3473 0026 012A cmp r2, #1 + 3474 0028 00F08580 beq .L251 +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3475 .loc 1 1873 5 discriminator 2 view .LVU1161 + 3476 002c 0122 movs r2, #1 + 3477 002e 84F84020 strb r2, [r4, #64] +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3478 .loc 1 1873 5 discriminator 2 view .LVU1162 + ARM GAS /tmp/ccE2rRGE.s page 199 + + +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3479 .loc 1 1875 5 discriminator 2 view .LVU1163 +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3480 .loc 1 1875 23 is_stmt 0 discriminator 2 view .LVU1164 + 3481 0032 2122 movs r2, #33 + 3482 0034 84F84120 strb r2, [r4, #65] +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3483 .loc 1 1876 5 is_stmt 1 discriminator 2 view .LVU1165 +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3484 .loc 1 1876 23 is_stmt 0 discriminator 2 view .LVU1166 + 3485 0038 1022 movs r2, #16 + 3486 003a 84F84220 strb r2, [r4, #66] +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3487 .loc 1 1877 5 is_stmt 1 discriminator 2 view .LVU1167 +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3488 .loc 1 1877 23 is_stmt 0 discriminator 2 view .LVU1168 + 3489 003e 0022 movs r2, #0 + 3490 0040 6264 str r2, [r4, #68] +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3491 .loc 1 1880 5 is_stmt 1 discriminator 2 view .LVU1169 +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3492 .loc 1 1880 23 is_stmt 0 discriminator 2 view .LVU1170 + 3493 0042 6162 str r1, [r4, #36] +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3494 .loc 1 1881 5 is_stmt 1 discriminator 2 view .LVU1171 +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3495 .loc 1 1881 23 is_stmt 0 discriminator 2 view .LVU1172 + 3496 0044 6385 strh r3, [r4, #42] @ movhi +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3497 .loc 1 1882 5 is_stmt 1 discriminator 2 view .LVU1173 +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3498 .loc 1 1882 23 is_stmt 0 discriminator 2 view .LVU1174 + 3499 0046 3D4B ldr r3, .L255 + 3500 .LVL208: +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3501 .loc 1 1882 23 discriminator 2 view .LVU1175 + 3502 0048 E362 str r3, [r4, #44] + 3503 .LVL209: +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3504 .loc 1 1883 5 is_stmt 1 discriminator 2 view .LVU1176 +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3505 .loc 1 1883 23 is_stmt 0 discriminator 2 view .LVU1177 + 3506 004a 3D4B ldr r3, .L255+4 + 3507 004c 6363 str r3, [r4, #52] +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3508 .loc 1 1885 5 is_stmt 1 discriminator 2 view .LVU1178 +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3509 .loc 1 1885 13 is_stmt 0 discriminator 2 view .LVU1179 + 3510 004e 638D ldrh r3, [r4, #42] + 3511 0050 9BB2 uxth r3, r3 +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3512 .loc 1 1885 8 discriminator 2 view .LVU1180 + 3513 0052 FF2B cmp r3, #255 + 3514 0054 27D9 bls .L242 +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3515 .loc 1 1887 7 is_stmt 1 view .LVU1181 +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + ARM GAS /tmp/ccE2rRGE.s page 200 + + + 3516 .loc 1 1887 22 is_stmt 0 view .LVU1182 + 3517 0056 FF23 movs r3, #255 + 3518 0058 2385 strh r3, [r4, #40] @ movhi +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3519 .loc 1 1888 7 is_stmt 1 view .LVU1183 + 3520 .LVL210: +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3521 .loc 1 1888 16 is_stmt 0 view .LVU1184 + 3522 005a 4FF08076 mov r6, #16777216 + 3523 .LVL211: + 3524 .L243: +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3525 .loc 1 1896 5 is_stmt 1 view .LVU1185 +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3526 .loc 1 1896 13 is_stmt 0 view .LVU1186 + 3527 005e 228D ldrh r2, [r4, #40] +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3528 .loc 1 1896 8 view .LVU1187 + 3529 0060 002A cmp r2, #0 + 3530 0062 4FD0 beq .L244 +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3531 .loc 1 1898 7 is_stmt 1 view .LVU1188 +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3532 .loc 1 1898 15 is_stmt 0 view .LVU1189 + 3533 0064 A36B ldr r3, [r4, #56] +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3534 .loc 1 1898 10 view .LVU1190 + 3535 0066 1BB3 cbz r3, .L245 +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3536 .loc 1 1901 9 is_stmt 1 view .LVU1191 +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3537 .loc 1 1901 40 is_stmt 0 view .LVU1192 + 3538 0068 364A ldr r2, .L255+8 + 3539 006a 9A62 str r2, [r3, #40] +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3540 .loc 1 1904 9 is_stmt 1 view .LVU1193 +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3541 .loc 1 1904 13 is_stmt 0 view .LVU1194 + 3542 006c A36B ldr r3, [r4, #56] +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3543 .loc 1 1904 41 view .LVU1195 + 3544 006e 364A ldr r2, .L255+12 + 3545 0070 1A63 str r2, [r3, #48] +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3546 .loc 1 1907 9 is_stmt 1 view .LVU1196 +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3547 .loc 1 1907 13 is_stmt 0 view .LVU1197 + 3548 0072 A26B ldr r2, [r4, #56] +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3549 .loc 1 1907 44 view .LVU1198 + 3550 0074 0023 movs r3, #0 + 3551 0076 D362 str r3, [r2, #44] +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3552 .loc 1 1908 9 is_stmt 1 view .LVU1199 +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3553 .loc 1 1908 13 is_stmt 0 view .LVU1200 + 3554 0078 A26B ldr r2, [r4, #56] + ARM GAS /tmp/ccE2rRGE.s page 201 + + +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3555 .loc 1 1908 41 view .LVU1201 + 3556 007a 5363 str r3, [r2, #52] +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3557 .loc 1 1911 9 is_stmt 1 view .LVU1202 +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3558 .loc 1 1911 88 is_stmt 0 view .LVU1203 + 3559 007c 2268 ldr r2, [r4] +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3560 .loc 1 1911 25 view .LVU1204 + 3561 007e 238D ldrh r3, [r4, #40] + 3562 0080 2832 adds r2, r2, #40 + 3563 0082 A06B ldr r0, [r4, #56] + 3564 0084 FFF7FEFF bl HAL_DMA_Start_IT + 3565 .LVL212: +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3566 .loc 1 1929 7 is_stmt 1 view .LVU1205 +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3567 .loc 1 1929 10 is_stmt 0 view .LVU1206 + 3568 0088 00B3 cbz r0, .L254 +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3569 .loc 1 1953 9 is_stmt 1 view .LVU1207 +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3570 .loc 1 1953 25 is_stmt 0 view .LVU1208 + 3571 008a 2023 movs r3, #32 + 3572 008c 84F84130 strb r3, [r4, #65] +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3573 .loc 1 1954 9 is_stmt 1 view .LVU1209 +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3574 .loc 1 1954 25 is_stmt 0 view .LVU1210 + 3575 0090 0022 movs r2, #0 + 3576 0092 84F84220 strb r2, [r4, #66] +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3577 .loc 1 1957 9 is_stmt 1 view .LVU1211 +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3578 .loc 1 1957 13 is_stmt 0 view .LVU1212 + 3579 0096 636C ldr r3, [r4, #68] +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3580 .loc 1 1957 25 view .LVU1213 + 3581 0098 43F01003 orr r3, r3, #16 + 3582 009c 6364 str r3, [r4, #68] +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3583 .loc 1 1960 9 is_stmt 1 view .LVU1214 +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3584 .loc 1 1960 9 view .LVU1215 + 3585 009e 84F84020 strb r2, [r4, #64] +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3586 .loc 1 1960 9 view .LVU1216 +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3587 .loc 1 1962 9 view .LVU1217 +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3588 .loc 1 1962 16 is_stmt 0 view .LVU1218 + 3589 00a2 0120 movs r0, #1 + 3590 .LVL213: +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3591 .loc 1 1962 16 view .LVU1219 + 3592 00a4 43E0 b .L241 + ARM GAS /tmp/ccE2rRGE.s page 202 + + + 3593 .LVL214: + 3594 .L242: +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3595 .loc 1 1892 7 is_stmt 1 view .LVU1220 +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3596 .loc 1 1892 28 is_stmt 0 view .LVU1221 + 3597 00a6 638D ldrh r3, [r4, #42] +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3598 .loc 1 1892 22 view .LVU1222 + 3599 00a8 2385 strh r3, [r4, #40] @ movhi +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3600 .loc 1 1893 7 is_stmt 1 view .LVU1223 + 3601 .LVL215: +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3602 .loc 1 1893 16 is_stmt 0 view .LVU1224 + 3603 00aa 4FF00076 mov r6, #33554432 + 3604 00ae D6E7 b .L243 + 3605 .LVL216: + 3606 .L245: +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3607 .loc 1 1917 9 is_stmt 1 view .LVU1225 +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3608 .loc 1 1917 25 is_stmt 0 view .LVU1226 + 3609 00b0 2023 movs r3, #32 + 3610 00b2 84F84130 strb r3, [r4, #65] +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3611 .loc 1 1918 9 is_stmt 1 view .LVU1227 +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3612 .loc 1 1918 25 is_stmt 0 view .LVU1228 + 3613 00b6 0022 movs r2, #0 + 3614 00b8 84F84220 strb r2, [r4, #66] +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3615 .loc 1 1921 9 is_stmt 1 view .LVU1229 +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3616 .loc 1 1921 13 is_stmt 0 view .LVU1230 + 3617 00bc 636C ldr r3, [r4, #68] +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3618 .loc 1 1921 25 view .LVU1231 + 3619 00be 43F08003 orr r3, r3, #128 + 3620 00c2 6364 str r3, [r4, #68] +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3621 .loc 1 1924 9 is_stmt 1 view .LVU1232 +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3622 .loc 1 1924 9 view .LVU1233 + 3623 00c4 84F84020 strb r2, [r4, #64] +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3624 .loc 1 1924 9 view .LVU1234 +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3625 .loc 1 1926 9 view .LVU1235 +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3626 .loc 1 1926 16 is_stmt 0 view .LVU1236 + 3627 00c8 0120 movs r0, #1 + 3628 00ca 30E0 b .L241 + 3629 .LVL217: + 3630 .L254: +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3631 .loc 1 1933 9 is_stmt 1 view .LVU1237 + ARM GAS /tmp/ccE2rRGE.s page 203 + + + 3632 00cc 1F4B ldr r3, .L255+16 + 3633 00ce 0093 str r3, [sp] + 3634 00d0 3346 mov r3, r6 + 3635 00d2 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 3636 00d6 2946 mov r1, r5 + 3637 00d8 2046 mov r0, r4 + 3638 .LVL218: +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3639 .loc 1 1933 9 is_stmt 0 view .LVU1238 + 3640 00da FFF7FEFF bl I2C_TransferConfig + 3641 .LVL219: +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3642 .loc 1 1936 9 is_stmt 1 view .LVU1239 +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3643 .loc 1 1936 13 is_stmt 0 view .LVU1240 + 3644 00de 638D ldrh r3, [r4, #42] + 3645 00e0 9BB2 uxth r3, r3 +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3646 .loc 1 1936 32 view .LVU1241 + 3647 00e2 228D ldrh r2, [r4, #40] +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3648 .loc 1 1936 25 view .LVU1242 + 3649 00e4 9B1A subs r3, r3, r2 + 3650 00e6 9BB2 uxth r3, r3 + 3651 00e8 6385 strh r3, [r4, #42] @ movhi +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3652 .loc 1 1939 9 is_stmt 1 view .LVU1243 +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3653 .loc 1 1939 9 view .LVU1244 + 3654 00ea 0023 movs r3, #0 + 3655 00ec 84F84030 strb r3, [r4, #64] +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3656 .loc 1 1939 9 view .LVU1245 +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3657 .loc 1 1945 9 view .LVU1246 + 3658 00f0 1021 movs r1, #16 + 3659 00f2 2046 mov r0, r4 + 3660 00f4 FFF7FEFF bl I2C_Enable_IRQ + 3661 .LVL220: +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3662 .loc 1 1948 9 view .LVU1247 +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3663 .loc 1 1948 13 is_stmt 0 view .LVU1248 + 3664 00f8 2268 ldr r2, [r4] +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3665 .loc 1 1948 23 view .LVU1249 + 3666 00fa 1368 ldr r3, [r2] +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3667 .loc 1 1948 29 view .LVU1250 + 3668 00fc 43F48043 orr r3, r3, #16384 + 3669 0100 1360 str r3, [r2] + 3670 0102 11E0 b .L248 + 3671 .LVL221: + 3672 .L244: +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3673 .loc 1 1968 7 is_stmt 1 view .LVU1251 +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 204 + + + 3674 .loc 1 1968 21 is_stmt 0 view .LVU1252 + 3675 0104 124B ldr r3, .L255+20 + 3676 0106 6363 str r3, [r4, #52] +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 3677 .loc 1 1972 7 is_stmt 1 view .LVU1253 + 3678 0108 104B ldr r3, .L255+16 + 3679 010a 0093 str r3, [sp] + 3680 010c 4FF00073 mov r3, #33554432 + 3681 0110 D2B2 uxtb r2, r2 + 3682 0112 2946 mov r1, r5 + 3683 .LVL222: +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 3684 .loc 1 1972 7 is_stmt 0 view .LVU1254 + 3685 0114 2046 mov r0, r4 + 3686 0116 FFF7FEFF bl I2C_TransferConfig + 3687 .LVL223: +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3688 .loc 1 1976 7 is_stmt 1 view .LVU1255 +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3689 .loc 1 1976 7 view .LVU1256 + 3690 011a 0023 movs r3, #0 + 3691 011c 84F84030 strb r3, [r4, #64] +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3692 .loc 1 1976 7 view .LVU1257 +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3693 .loc 1 1985 7 view .LVU1258 + 3694 0120 0121 movs r1, #1 + 3695 0122 2046 mov r0, r4 + 3696 0124 FFF7FEFF bl I2C_Enable_IRQ + 3697 .LVL224: + 3698 .L248: +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3699 .loc 1 1988 5 view .LVU1259 +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3700 .loc 1 1988 12 is_stmt 0 view .LVU1260 + 3701 0128 0020 movs r0, #0 + 3702 012a 00E0 b .L241 + 3703 .LVL225: + 3704 .L249: +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3705 .loc 1 1992 12 view .LVU1261 + 3706 012c 0220 movs r0, #2 + 3707 .LVL226: + 3708 .L241: +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3709 .loc 1 1994 1 view .LVU1262 + 3710 012e 02B0 add sp, sp, #8 + 3711 .cfi_remember_state + 3712 .cfi_def_cfa_offset 16 + 3713 @ sp needed + 3714 0130 70BD pop {r4, r5, r6, pc} + 3715 .LVL227: + 3716 .L250: + 3717 .cfi_restore_state +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3718 .loc 1 1869 14 view .LVU1263 + 3719 0132 0220 movs r0, #2 + ARM GAS /tmp/ccE2rRGE.s page 205 + + + 3720 0134 FBE7 b .L241 + 3721 .L251: +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3722 .loc 1 1873 5 view .LVU1264 + 3723 0136 0220 movs r0, #2 + 3724 0138 F9E7 b .L241 + 3725 .L256: + 3726 013a 00BF .align 2 + 3727 .L255: + 3728 013c 0000FFFF .word -65536 + 3729 0140 00000000 .word I2C_Master_ISR_DMA + 3730 0144 00000000 .word I2C_DMAMasterTransmitCplt + 3731 0148 00000000 .word I2C_DMAError + 3732 014c 00200080 .word -2147475456 + 3733 0150 00000000 .word I2C_Master_ISR_IT + 3734 .cfi_endproc + 3735 .LFE142: + 3737 .section .text.HAL_I2C_Master_Receive_DMA,"ax",%progbits + 3738 .align 1 + 3739 .global HAL_I2C_Master_Receive_DMA + 3740 .syntax unified + 3741 .thumb + 3742 .thumb_func + 3744 HAL_I2C_Master_Receive_DMA: + 3745 .LVL228: + 3746 .LFB143: +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 3747 .loc 1 2008 1 is_stmt 1 view -0 + 3748 .cfi_startproc + 3749 @ args = 0, pretend = 0, frame = 0 + 3750 @ frame_needed = 0, uses_anonymous_args = 0 +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 3751 .loc 1 2008 1 is_stmt 0 view .LVU1266 + 3752 0000 70B5 push {r4, r5, r6, lr} + 3753 .cfi_def_cfa_offset 16 + 3754 .cfi_offset 4, -16 + 3755 .cfi_offset 5, -12 + 3756 .cfi_offset 6, -8 + 3757 .cfi_offset 14, -4 + 3758 0002 82B0 sub sp, sp, #8 + 3759 .cfi_def_cfa_offset 24 + 3760 0004 0446 mov r4, r0 +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 3761 .loc 1 2009 3 is_stmt 1 view .LVU1267 +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3762 .loc 1 2010 3 view .LVU1268 +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3763 .loc 1 2012 3 view .LVU1269 +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3764 .loc 1 2012 11 is_stmt 0 view .LVU1270 + 3765 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 3766 .LVL229: +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3767 .loc 1 2012 11 view .LVU1271 + 3768 000a C0B2 uxtb r0, r0 +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3769 .loc 1 2012 6 view .LVU1272 + ARM GAS /tmp/ccE2rRGE.s page 206 + + + 3770 000c 2028 cmp r0, #32 + 3771 000e 40F08C80 bne .L266 + 3772 0012 0D46 mov r5, r1 +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3773 .loc 1 2014 5 is_stmt 1 view .LVU1273 +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3774 .loc 1 2014 9 is_stmt 0 view .LVU1274 + 3775 0014 2168 ldr r1, [r4] + 3776 .LVL230: +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3777 .loc 1 2014 9 view .LVU1275 + 3778 0016 8969 ldr r1, [r1, #24] +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3779 .loc 1 2014 8 view .LVU1276 + 3780 0018 11F4004F tst r1, #32768 + 3781 001c 40F08880 bne .L267 +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3782 .loc 1 2020 5 is_stmt 1 view .LVU1277 +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3783 .loc 1 2020 5 view .LVU1278 + 3784 0020 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 3785 0024 0129 cmp r1, #1 + 3786 0026 00F08580 beq .L268 +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3787 .loc 1 2020 5 discriminator 2 view .LVU1279 + 3788 002a 0121 movs r1, #1 + 3789 002c 84F84010 strb r1, [r4, #64] +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3790 .loc 1 2020 5 discriminator 2 view .LVU1280 +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3791 .loc 1 2022 5 discriminator 2 view .LVU1281 +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3792 .loc 1 2022 23 is_stmt 0 discriminator 2 view .LVU1282 + 3793 0030 2221 movs r1, #34 + 3794 0032 84F84110 strb r1, [r4, #65] +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3795 .loc 1 2023 5 is_stmt 1 discriminator 2 view .LVU1283 +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3796 .loc 1 2023 23 is_stmt 0 discriminator 2 view .LVU1284 + 3797 0036 1021 movs r1, #16 + 3798 0038 84F84210 strb r1, [r4, #66] +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3799 .loc 1 2024 5 is_stmt 1 discriminator 2 view .LVU1285 +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3800 .loc 1 2024 23 is_stmt 0 discriminator 2 view .LVU1286 + 3801 003c 0021 movs r1, #0 + 3802 003e 6164 str r1, [r4, #68] +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3803 .loc 1 2027 5 is_stmt 1 discriminator 2 view .LVU1287 +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3804 .loc 1 2027 23 is_stmt 0 discriminator 2 view .LVU1288 + 3805 0040 6262 str r2, [r4, #36] +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3806 .loc 1 2028 5 is_stmt 1 discriminator 2 view .LVU1289 +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3807 .loc 1 2028 23 is_stmt 0 discriminator 2 view .LVU1290 + 3808 0042 6385 strh r3, [r4, #42] @ movhi + ARM GAS /tmp/ccE2rRGE.s page 207 + + +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3809 .loc 1 2029 5 is_stmt 1 discriminator 2 view .LVU1291 +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3810 .loc 1 2029 23 is_stmt 0 discriminator 2 view .LVU1292 + 3811 0044 3C4B ldr r3, .L272 + 3812 .LVL231: +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3813 .loc 1 2029 23 discriminator 2 view .LVU1293 + 3814 0046 E362 str r3, [r4, #44] + 3815 .LVL232: +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3816 .loc 1 2030 5 is_stmt 1 discriminator 2 view .LVU1294 +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3817 .loc 1 2030 23 is_stmt 0 discriminator 2 view .LVU1295 + 3818 0048 3C4B ldr r3, .L272+4 + 3819 004a 6363 str r3, [r4, #52] +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3820 .loc 1 2032 5 is_stmt 1 discriminator 2 view .LVU1296 +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3821 .loc 1 2032 13 is_stmt 0 discriminator 2 view .LVU1297 + 3822 004c 638D ldrh r3, [r4, #42] + 3823 004e 9BB2 uxth r3, r3 +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3824 .loc 1 2032 8 discriminator 2 view .LVU1298 + 3825 0050 FF2B cmp r3, #255 + 3826 0052 27D9 bls .L259 +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3827 .loc 1 2034 7 is_stmt 1 view .LVU1299 +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3828 .loc 1 2034 22 is_stmt 0 view .LVU1300 + 3829 0054 FF23 movs r3, #255 + 3830 0056 2385 strh r3, [r4, #40] @ movhi +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3831 .loc 1 2035 7 is_stmt 1 view .LVU1301 + 3832 .LVL233: +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3833 .loc 1 2035 16 is_stmt 0 view .LVU1302 + 3834 0058 4FF08076 mov r6, #16777216 + 3835 .LVL234: + 3836 .L260: +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3837 .loc 1 2043 5 is_stmt 1 view .LVU1303 +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3838 .loc 1 2043 13 is_stmt 0 view .LVU1304 + 3839 005c 218D ldrh r1, [r4, #40] +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3840 .loc 1 2043 8 view .LVU1305 + 3841 005e 0029 cmp r1, #0 + 3842 0060 4FD0 beq .L261 +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3843 .loc 1 2045 7 is_stmt 1 view .LVU1306 +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3844 .loc 1 2045 15 is_stmt 0 view .LVU1307 + 3845 0062 E36B ldr r3, [r4, #60] +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3846 .loc 1 2045 10 view .LVU1308 + 3847 0064 1BB3 cbz r3, .L262 + ARM GAS /tmp/ccE2rRGE.s page 208 + + +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3848 .loc 1 2048 9 is_stmt 1 view .LVU1309 +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3849 .loc 1 2048 40 is_stmt 0 view .LVU1310 + 3850 0066 3649 ldr r1, .L272+8 + 3851 0068 9962 str r1, [r3, #40] +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3852 .loc 1 2051 9 is_stmt 1 view .LVU1311 +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3853 .loc 1 2051 13 is_stmt 0 view .LVU1312 + 3854 006a E36B ldr r3, [r4, #60] +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3855 .loc 1 2051 41 view .LVU1313 + 3856 006c 3549 ldr r1, .L272+12 + 3857 006e 1963 str r1, [r3, #48] +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 3858 .loc 1 2054 9 is_stmt 1 view .LVU1314 +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 3859 .loc 1 2054 13 is_stmt 0 view .LVU1315 + 3860 0070 E16B ldr r1, [r4, #60] +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 3861 .loc 1 2054 44 view .LVU1316 + 3862 0072 0023 movs r3, #0 + 3863 0074 CB62 str r3, [r1, #44] +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3864 .loc 1 2055 9 is_stmt 1 view .LVU1317 +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3865 .loc 1 2055 13 is_stmt 0 view .LVU1318 + 3866 0076 E16B ldr r1, [r4, #60] +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3867 .loc 1 2055 41 view .LVU1319 + 3868 0078 4B63 str r3, [r1, #52] +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3869 .loc 1 2058 9 is_stmt 1 view .LVU1320 +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3870 .loc 1 2058 71 is_stmt 0 view .LVU1321 + 3871 007a 2168 ldr r1, [r4] +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3872 .loc 1 2058 25 view .LVU1322 + 3873 007c 238D ldrh r3, [r4, #40] + 3874 007e 2431 adds r1, r1, #36 + 3875 0080 E06B ldr r0, [r4, #60] + 3876 0082 FFF7FEFF bl HAL_DMA_Start_IT + 3877 .LVL235: +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3878 .loc 1 2076 7 is_stmt 1 view .LVU1323 +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3879 .loc 1 2076 10 is_stmt 0 view .LVU1324 + 3880 0086 00B3 cbz r0, .L271 +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3881 .loc 1 2100 9 is_stmt 1 view .LVU1325 +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3882 .loc 1 2100 25 is_stmt 0 view .LVU1326 + 3883 0088 2023 movs r3, #32 + 3884 008a 84F84130 strb r3, [r4, #65] +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3885 .loc 1 2101 9 is_stmt 1 view .LVU1327 + ARM GAS /tmp/ccE2rRGE.s page 209 + + +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3886 .loc 1 2101 25 is_stmt 0 view .LVU1328 + 3887 008e 0022 movs r2, #0 + 3888 0090 84F84220 strb r2, [r4, #66] +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3889 .loc 1 2104 9 is_stmt 1 view .LVU1329 +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3890 .loc 1 2104 13 is_stmt 0 view .LVU1330 + 3891 0094 636C ldr r3, [r4, #68] +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3892 .loc 1 2104 25 view .LVU1331 + 3893 0096 43F01003 orr r3, r3, #16 + 3894 009a 6364 str r3, [r4, #68] +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3895 .loc 1 2107 9 is_stmt 1 view .LVU1332 +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3896 .loc 1 2107 9 view .LVU1333 + 3897 009c 84F84020 strb r2, [r4, #64] +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3898 .loc 1 2107 9 view .LVU1334 +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3899 .loc 1 2109 9 view .LVU1335 +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3900 .loc 1 2109 16 is_stmt 0 view .LVU1336 + 3901 00a0 0120 movs r0, #1 + 3902 .LVL236: +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3903 .loc 1 2109 16 view .LVU1337 + 3904 00a2 43E0 b .L258 + 3905 .LVL237: + 3906 .L259: +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3907 .loc 1 2039 7 is_stmt 1 view .LVU1338 +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3908 .loc 1 2039 28 is_stmt 0 view .LVU1339 + 3909 00a4 638D ldrh r3, [r4, #42] +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3910 .loc 1 2039 22 view .LVU1340 + 3911 00a6 2385 strh r3, [r4, #40] @ movhi +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3912 .loc 1 2040 7 is_stmt 1 view .LVU1341 + 3913 .LVL238: +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3914 .loc 1 2040 16 is_stmt 0 view .LVU1342 + 3915 00a8 4FF00076 mov r6, #33554432 + 3916 00ac D6E7 b .L260 + 3917 .LVL239: + 3918 .L262: +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3919 .loc 1 2064 9 is_stmt 1 view .LVU1343 +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3920 .loc 1 2064 25 is_stmt 0 view .LVU1344 + 3921 00ae 2023 movs r3, #32 + 3922 00b0 84F84130 strb r3, [r4, #65] +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3923 .loc 1 2065 9 is_stmt 1 view .LVU1345 +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 210 + + + 3924 .loc 1 2065 25 is_stmt 0 view .LVU1346 + 3925 00b4 0022 movs r2, #0 + 3926 .LVL240: +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3927 .loc 1 2065 25 view .LVU1347 + 3928 00b6 84F84220 strb r2, [r4, #66] +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3929 .loc 1 2068 9 is_stmt 1 view .LVU1348 +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3930 .loc 1 2068 13 is_stmt 0 view .LVU1349 + 3931 00ba 636C ldr r3, [r4, #68] +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3932 .loc 1 2068 25 view .LVU1350 + 3933 00bc 43F08003 orr r3, r3, #128 + 3934 00c0 6364 str r3, [r4, #68] +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3935 .loc 1 2071 9 is_stmt 1 view .LVU1351 +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3936 .loc 1 2071 9 view .LVU1352 + 3937 00c2 84F84020 strb r2, [r4, #64] +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3938 .loc 1 2071 9 view .LVU1353 +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3939 .loc 1 2073 9 view .LVU1354 +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3940 .loc 1 2073 16 is_stmt 0 view .LVU1355 + 3941 00c6 0120 movs r0, #1 + 3942 00c8 30E0 b .L258 + 3943 .LVL241: + 3944 .L271: +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3945 .loc 1 2080 9 is_stmt 1 view .LVU1356 + 3946 00ca 1F4B ldr r3, .L272+16 + 3947 00cc 0093 str r3, [sp] + 3948 00ce 3346 mov r3, r6 + 3949 00d0 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 3950 00d4 2946 mov r1, r5 + 3951 00d6 2046 mov r0, r4 + 3952 .LVL242: +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3953 .loc 1 2080 9 is_stmt 0 view .LVU1357 + 3954 00d8 FFF7FEFF bl I2C_TransferConfig + 3955 .LVL243: +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3956 .loc 1 2083 9 is_stmt 1 view .LVU1358 +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3957 .loc 1 2083 13 is_stmt 0 view .LVU1359 + 3958 00dc 638D ldrh r3, [r4, #42] + 3959 00de 9BB2 uxth r3, r3 +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3960 .loc 1 2083 32 view .LVU1360 + 3961 00e0 228D ldrh r2, [r4, #40] +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3962 .loc 1 2083 25 view .LVU1361 + 3963 00e2 9B1A subs r3, r3, r2 + 3964 00e4 9BB2 uxth r3, r3 + 3965 00e6 6385 strh r3, [r4, #42] @ movhi + ARM GAS /tmp/ccE2rRGE.s page 211 + + +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3966 .loc 1 2086 9 is_stmt 1 view .LVU1362 +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3967 .loc 1 2086 9 view .LVU1363 + 3968 00e8 0023 movs r3, #0 + 3969 00ea 84F84030 strb r3, [r4, #64] +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3970 .loc 1 2086 9 view .LVU1364 +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3971 .loc 1 2092 9 view .LVU1365 + 3972 00ee 1021 movs r1, #16 + 3973 00f0 2046 mov r0, r4 + 3974 00f2 FFF7FEFF bl I2C_Enable_IRQ + 3975 .LVL244: +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3976 .loc 1 2095 9 view .LVU1366 +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3977 .loc 1 2095 13 is_stmt 0 view .LVU1367 + 3978 00f6 2268 ldr r2, [r4] +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3979 .loc 1 2095 23 view .LVU1368 + 3980 00f8 1368 ldr r3, [r2] +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3981 .loc 1 2095 29 view .LVU1369 + 3982 00fa 43F40043 orr r3, r3, #32768 + 3983 00fe 1360 str r3, [r2] + 3984 0100 11E0 b .L265 + 3985 .LVL245: + 3986 .L261: +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3987 .loc 1 2115 7 is_stmt 1 view .LVU1370 +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3988 .loc 1 2115 21 is_stmt 0 view .LVU1371 + 3989 0102 124B ldr r3, .L272+20 + 3990 0104 6363 str r3, [r4, #52] +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 3991 .loc 1 2119 7 is_stmt 1 view .LVU1372 + 3992 0106 104B ldr r3, .L272+16 + 3993 0108 0093 str r3, [sp] + 3994 010a 4FF00073 mov r3, #33554432 + 3995 010e CAB2 uxtb r2, r1 + 3996 .LVL246: +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 3997 .loc 1 2119 7 is_stmt 0 view .LVU1373 + 3998 0110 2946 mov r1, r5 + 3999 0112 2046 mov r0, r4 + 4000 0114 FFF7FEFF bl I2C_TransferConfig + 4001 .LVL247: +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4002 .loc 1 2123 7 is_stmt 1 view .LVU1374 +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4003 .loc 1 2123 7 view .LVU1375 + 4004 0118 0023 movs r3, #0 + 4005 011a 84F84030 strb r3, [r4, #64] +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4006 .loc 1 2123 7 view .LVU1376 +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 212 + + + 4007 .loc 1 2132 7 view .LVU1377 + 4008 011e 0121 movs r1, #1 + 4009 0120 2046 mov r0, r4 + 4010 0122 FFF7FEFF bl I2C_Enable_IRQ + 4011 .LVL248: + 4012 .L265: +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4013 .loc 1 2135 5 view .LVU1378 +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4014 .loc 1 2135 12 is_stmt 0 view .LVU1379 + 4015 0126 0020 movs r0, #0 + 4016 0128 00E0 b .L258 + 4017 .LVL249: + 4018 .L266: +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4019 .loc 1 2139 12 view .LVU1380 + 4020 012a 0220 movs r0, #2 + 4021 .LVL250: + 4022 .L258: +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4023 .loc 1 2141 1 view .LVU1381 + 4024 012c 02B0 add sp, sp, #8 + 4025 .cfi_remember_state + 4026 .cfi_def_cfa_offset 16 + 4027 @ sp needed + 4028 012e 70BD pop {r4, r5, r6, pc} + 4029 .LVL251: + 4030 .L267: + 4031 .cfi_restore_state +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4032 .loc 1 2016 14 view .LVU1382 + 4033 0130 0220 movs r0, #2 + 4034 0132 FBE7 b .L258 + 4035 .L268: +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4036 .loc 1 2020 5 view .LVU1383 + 4037 0134 0220 movs r0, #2 + 4038 0136 F9E7 b .L258 + 4039 .L273: + 4040 .align 2 + 4041 .L272: + 4042 0138 0000FFFF .word -65536 + 4043 013c 00000000 .word I2C_Master_ISR_DMA + 4044 0140 00000000 .word I2C_DMAMasterReceiveCplt + 4045 0144 00000000 .word I2C_DMAError + 4046 0148 00240080 .word -2147474432 + 4047 014c 00000000 .word I2C_Master_ISR_IT + 4048 .cfi_endproc + 4049 .LFE143: + 4051 .section .text.HAL_I2C_Slave_Transmit_DMA,"ax",%progbits + 4052 .align 1 + 4053 .global HAL_I2C_Slave_Transmit_DMA + 4054 .syntax unified + 4055 .thumb + 4056 .thumb_func + 4058 HAL_I2C_Slave_Transmit_DMA: + 4059 .LVL252: + ARM GAS /tmp/ccE2rRGE.s page 213 + + + 4060 .LFB144: +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4061 .loc 1 2152 1 is_stmt 1 view -0 + 4062 .cfi_startproc + 4063 @ args = 0, pretend = 0, frame = 0 + 4064 @ frame_needed = 0, uses_anonymous_args = 0 +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4065 .loc 1 2152 1 is_stmt 0 view .LVU1385 + 4066 0000 38B5 push {r3, r4, r5, lr} + 4067 .cfi_def_cfa_offset 16 + 4068 .cfi_offset 3, -16 + 4069 .cfi_offset 4, -12 + 4070 .cfi_offset 5, -8 + 4071 .cfi_offset 14, -4 +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4072 .loc 1 2153 3 is_stmt 1 view .LVU1386 +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4073 .loc 1 2155 3 view .LVU1387 +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4074 .loc 1 2155 11 is_stmt 0 view .LVU1388 + 4075 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 4076 0006 DBB2 uxtb r3, r3 +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4077 .loc 1 2155 6 view .LVU1389 + 4078 0008 202B cmp r3, #32 + 4079 000a 63D1 bne .L281 + 4080 000c 0446 mov r4, r0 +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4081 .loc 1 2157 5 is_stmt 1 view .LVU1390 +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4082 .loc 1 2157 8 is_stmt 0 view .LVU1391 + 4083 000e 0029 cmp r1, #0 + 4084 0010 3AD0 beq .L276 +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4085 .loc 1 2157 25 discriminator 1 view .LVU1392 + 4086 0012 002A cmp r2, #0 + 4087 0014 38D0 beq .L276 +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4088 .loc 1 2163 5 is_stmt 1 view .LVU1393 +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4089 .loc 1 2163 5 view .LVU1394 + 4090 0016 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4091 001a 012B cmp r3, #1 + 4092 001c 5DD0 beq .L282 +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4093 .loc 1 2163 5 discriminator 2 view .LVU1395 + 4094 001e 0123 movs r3, #1 + 4095 0020 80F84030 strb r3, [r0, #64] +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4096 .loc 1 2163 5 discriminator 2 view .LVU1396 +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4097 .loc 1 2165 5 discriminator 2 view .LVU1397 +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4098 .loc 1 2165 23 is_stmt 0 discriminator 2 view .LVU1398 + 4099 0024 2123 movs r3, #33 + 4100 0026 80F84130 strb r3, [r0, #65] +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + ARM GAS /tmp/ccE2rRGE.s page 214 + + + 4101 .loc 1 2166 5 is_stmt 1 discriminator 2 view .LVU1399 +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4102 .loc 1 2166 23 is_stmt 0 discriminator 2 view .LVU1400 + 4103 002a 2023 movs r3, #32 + 4104 002c 80F84230 strb r3, [r0, #66] +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4105 .loc 1 2167 5 is_stmt 1 discriminator 2 view .LVU1401 +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4106 .loc 1 2167 23 is_stmt 0 discriminator 2 view .LVU1402 + 4107 0030 0023 movs r3, #0 + 4108 0032 4364 str r3, [r0, #68] +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4109 .loc 1 2170 5 is_stmt 1 discriminator 2 view .LVU1403 +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4110 .loc 1 2170 23 is_stmt 0 discriminator 2 view .LVU1404 + 4111 0034 4162 str r1, [r0, #36] +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4112 .loc 1 2171 5 is_stmt 1 discriminator 2 view .LVU1405 +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4113 .loc 1 2171 23 is_stmt 0 discriminator 2 view .LVU1406 + 4114 0036 4285 strh r2, [r0, #42] @ movhi +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4115 .loc 1 2172 5 is_stmt 1 discriminator 2 view .LVU1407 +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4116 .loc 1 2172 29 is_stmt 0 discriminator 2 view .LVU1408 + 4117 0038 438D ldrh r3, [r0, #42] +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4118 .loc 1 2172 23 discriminator 2 view .LVU1409 + 4119 003a 0385 strh r3, [r0, #40] @ movhi +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4120 .loc 1 2173 5 is_stmt 1 discriminator 2 view .LVU1410 +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4121 .loc 1 2173 23 is_stmt 0 discriminator 2 view .LVU1411 + 4122 003c 284B ldr r3, .L286 + 4123 003e C362 str r3, [r0, #44] +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4124 .loc 1 2174 5 is_stmt 1 discriminator 2 view .LVU1412 +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4125 .loc 1 2174 23 is_stmt 0 discriminator 2 view .LVU1413 + 4126 0040 284B ldr r3, .L286+4 + 4127 0042 4363 str r3, [r0, #52] +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4128 .loc 1 2176 5 is_stmt 1 discriminator 2 view .LVU1414 +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4129 .loc 1 2176 13 is_stmt 0 discriminator 2 view .LVU1415 + 4130 0044 836B ldr r3, [r0, #56] +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4131 .loc 1 2176 8 discriminator 2 view .LVU1416 + 4132 0046 23B3 cbz r3, .L278 +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4133 .loc 1 2179 7 is_stmt 1 view .LVU1417 +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4134 .loc 1 2179 38 is_stmt 0 view .LVU1418 + 4135 0048 274A ldr r2, .L286+8 + 4136 .LVL253: +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4137 .loc 1 2179 38 view .LVU1419 + ARM GAS /tmp/ccE2rRGE.s page 215 + + + 4138 004a 9A62 str r2, [r3, #40] +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4139 .loc 1 2182 7 is_stmt 1 view .LVU1420 +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4140 .loc 1 2182 11 is_stmt 0 view .LVU1421 + 4141 004c 836B ldr r3, [r0, #56] +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4142 .loc 1 2182 39 view .LVU1422 + 4143 004e 274A ldr r2, .L286+12 + 4144 0050 1A63 str r2, [r3, #48] +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4145 .loc 1 2185 7 is_stmt 1 view .LVU1423 +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4146 .loc 1 2185 11 is_stmt 0 view .LVU1424 + 4147 0052 826B ldr r2, [r0, #56] +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4148 .loc 1 2185 42 view .LVU1425 + 4149 0054 0023 movs r3, #0 + 4150 0056 D362 str r3, [r2, #44] +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4151 .loc 1 2186 7 is_stmt 1 view .LVU1426 +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4152 .loc 1 2186 11 is_stmt 0 view .LVU1427 + 4153 0058 826B ldr r2, [r0, #56] +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4154 .loc 1 2186 39 view .LVU1428 + 4155 005a 5363 str r3, [r2, #52] +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4156 .loc 1 2189 7 is_stmt 1 view .LVU1429 +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4157 .loc 1 2189 86 is_stmt 0 view .LVU1430 + 4158 005c 0268 ldr r2, [r0] +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4159 .loc 1 2189 23 view .LVU1431 + 4160 005e 038D ldrh r3, [r0, #40] + 4161 0060 2832 adds r2, r2, #40 + 4162 0062 806B ldr r0, [r0, #56] + 4163 .LVL254: +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4164 .loc 1 2189 23 view .LVU1432 + 4165 0064 FFF7FEFF bl HAL_DMA_Start_IT + 4166 .LVL255: +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4167 .loc 1 2207 5 is_stmt 1 view .LVU1433 +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4168 .loc 1 2207 8 is_stmt 0 view .LVU1434 + 4169 0068 0546 mov r5, r0 + 4170 006a 00B3 cbz r0, .L285 +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4171 .loc 1 2227 7 is_stmt 1 view .LVU1435 +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4172 .loc 1 2227 23 is_stmt 0 view .LVU1436 + 4173 006c 2823 movs r3, #40 + 4174 006e 84F84130 strb r3, [r4, #65] +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4175 .loc 1 2228 7 is_stmt 1 view .LVU1437 +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 216 + + + 4176 .loc 1 2228 23 is_stmt 0 view .LVU1438 + 4177 0072 0022 movs r2, #0 + 4178 0074 84F84220 strb r2, [r4, #66] +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4179 .loc 1 2231 7 is_stmt 1 view .LVU1439 +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4180 .loc 1 2231 11 is_stmt 0 view .LVU1440 + 4181 0078 636C ldr r3, [r4, #68] +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4182 .loc 1 2231 23 view .LVU1441 + 4183 007a 43F01003 orr r3, r3, #16 + 4184 007e 6364 str r3, [r4, #68] +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4185 .loc 1 2234 7 is_stmt 1 view .LVU1442 +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4186 .loc 1 2234 7 view .LVU1443 + 4187 0080 84F84020 strb r2, [r4, #64] +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4188 .loc 1 2234 7 view .LVU1444 +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4189 .loc 1 2236 7 view .LVU1445 +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4190 .loc 1 2236 14 is_stmt 0 view .LVU1446 + 4191 0084 0125 movs r5, #1 + 4192 0086 26E0 b .L275 + 4193 .LVL256: + 4194 .L276: +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4195 .loc 1 2159 7 is_stmt 1 view .LVU1447 +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4196 .loc 1 2159 23 is_stmt 0 view .LVU1448 + 4197 0088 4FF40073 mov r3, #512 + 4198 008c 6364 str r3, [r4, #68] +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4199 .loc 1 2160 7 is_stmt 1 view .LVU1449 +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4200 .loc 1 2160 15 is_stmt 0 view .LVU1450 + 4201 008e 0125 movs r5, #1 + 4202 0090 21E0 b .L275 + 4203 .L278: +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4204 .loc 1 2195 7 is_stmt 1 view .LVU1451 +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4205 .loc 1 2195 23 is_stmt 0 view .LVU1452 + 4206 0092 2823 movs r3, #40 + 4207 0094 80F84130 strb r3, [r0, #65] +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4208 .loc 1 2196 7 is_stmt 1 view .LVU1453 +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4209 .loc 1 2196 23 is_stmt 0 view .LVU1454 + 4210 0098 0022 movs r2, #0 + 4211 .LVL257: +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4212 .loc 1 2196 23 view .LVU1455 + 4213 009a 80F84220 strb r2, [r0, #66] +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4214 .loc 1 2199 7 is_stmt 1 view .LVU1456 + ARM GAS /tmp/ccE2rRGE.s page 217 + + +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4215 .loc 1 2199 11 is_stmt 0 view .LVU1457 + 4216 009e 436C ldr r3, [r0, #68] +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4217 .loc 1 2199 23 view .LVU1458 + 4218 00a0 43F08003 orr r3, r3, #128 + 4219 00a4 4364 str r3, [r0, #68] +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4220 .loc 1 2202 7 is_stmt 1 view .LVU1459 +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4221 .loc 1 2202 7 view .LVU1460 + 4222 00a6 80F84020 strb r2, [r0, #64] +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4223 .loc 1 2202 7 view .LVU1461 +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4224 .loc 1 2204 7 view .LVU1462 +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4225 .loc 1 2204 14 is_stmt 0 view .LVU1463 + 4226 00aa 0125 movs r5, #1 + 4227 00ac 13E0 b .L275 + 4228 .LVL258: + 4229 .L285: +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4230 .loc 1 2210 7 is_stmt 1 view .LVU1464 +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4231 .loc 1 2210 11 is_stmt 0 view .LVU1465 + 4232 00ae 2268 ldr r2, [r4] +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4233 .loc 1 2210 21 view .LVU1466 + 4234 00b0 5368 ldr r3, [r2, #4] +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4235 .loc 1 2210 27 view .LVU1467 + 4236 00b2 23F40043 bic r3, r3, #32768 + 4237 00b6 5360 str r3, [r2, #4] +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4238 .loc 1 2213 7 is_stmt 1 view .LVU1468 +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4239 .loc 1 2213 7 view .LVU1469 + 4240 00b8 0023 movs r3, #0 + 4241 00ba 84F84030 strb r3, [r4, #64] +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4242 .loc 1 2213 7 view .LVU1470 +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4243 .loc 1 2219 7 view .LVU1471 + 4244 00be 4FF40041 mov r1, #32768 + 4245 00c2 2046 mov r0, r4 + 4246 .LVL259: +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4247 .loc 1 2219 7 is_stmt 0 view .LVU1472 + 4248 00c4 FFF7FEFF bl I2C_Enable_IRQ + 4249 .LVL260: +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4250 .loc 1 2222 7 is_stmt 1 view .LVU1473 +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4251 .loc 1 2222 11 is_stmt 0 view .LVU1474 + 4252 00c8 2268 ldr r2, [r4] +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 218 + + + 4253 .loc 1 2222 21 view .LVU1475 + 4254 00ca 1368 ldr r3, [r2] +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4255 .loc 1 2222 27 view .LVU1476 + 4256 00cc 43F48043 orr r3, r3, #16384 + 4257 00d0 1360 str r3, [r2] +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4258 .loc 1 2239 5 is_stmt 1 view .LVU1477 +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4259 .loc 1 2239 12 is_stmt 0 view .LVU1478 + 4260 00d2 00E0 b .L275 + 4261 .LVL261: + 4262 .L281: +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4263 .loc 1 2243 12 view .LVU1479 + 4264 00d4 0225 movs r5, #2 + 4265 .LVL262: + 4266 .L275: +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4267 .loc 1 2245 1 view .LVU1480 + 4268 00d6 2846 mov r0, r5 + 4269 00d8 38BD pop {r3, r4, r5, pc} + 4270 .LVL263: + 4271 .L282: +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4272 .loc 1 2163 5 view .LVU1481 + 4273 00da 0225 movs r5, #2 + 4274 00dc FBE7 b .L275 + 4275 .L287: + 4276 00de 00BF .align 2 + 4277 .L286: + 4278 00e0 0000FFFF .word -65536 + 4279 00e4 00000000 .word I2C_Slave_ISR_DMA + 4280 00e8 00000000 .word I2C_DMASlaveTransmitCplt + 4281 00ec 00000000 .word I2C_DMAError + 4282 .cfi_endproc + 4283 .LFE144: + 4285 .section .text.HAL_I2C_Slave_Receive_DMA,"ax",%progbits + 4286 .align 1 + 4287 .global HAL_I2C_Slave_Receive_DMA + 4288 .syntax unified + 4289 .thumb + 4290 .thumb_func + 4292 HAL_I2C_Slave_Receive_DMA: + 4293 .LVL264: + 4294 .LFB145: +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4295 .loc 1 2256 1 is_stmt 1 view -0 + 4296 .cfi_startproc + 4297 @ args = 0, pretend = 0, frame = 0 + 4298 @ frame_needed = 0, uses_anonymous_args = 0 +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4299 .loc 1 2256 1 is_stmt 0 view .LVU1483 + 4300 0000 38B5 push {r3, r4, r5, lr} + 4301 .cfi_def_cfa_offset 16 + 4302 .cfi_offset 3, -16 + 4303 .cfi_offset 4, -12 + ARM GAS /tmp/ccE2rRGE.s page 219 + + + 4304 .cfi_offset 5, -8 + 4305 .cfi_offset 14, -4 +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4306 .loc 1 2257 3 is_stmt 1 view .LVU1484 +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4307 .loc 1 2259 3 view .LVU1485 +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4308 .loc 1 2259 11 is_stmt 0 view .LVU1486 + 4309 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 4310 0006 DBB2 uxtb r3, r3 +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4311 .loc 1 2259 6 view .LVU1487 + 4312 0008 202B cmp r3, #32 + 4313 000a 65D1 bne .L295 + 4314 000c 0446 mov r4, r0 +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4315 .loc 1 2261 5 is_stmt 1 view .LVU1488 +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4316 .loc 1 2261 8 is_stmt 0 view .LVU1489 + 4317 000e 0029 cmp r1, #0 + 4318 0010 3CD0 beq .L290 +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4319 .loc 1 2261 25 discriminator 1 view .LVU1490 + 4320 0012 002A cmp r2, #0 + 4321 0014 3AD0 beq .L290 +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4322 .loc 1 2267 5 is_stmt 1 view .LVU1491 +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4323 .loc 1 2267 5 view .LVU1492 + 4324 0016 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4325 001a 012B cmp r3, #1 + 4326 001c 5FD0 beq .L296 +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4327 .loc 1 2267 5 discriminator 2 view .LVU1493 + 4328 001e 0123 movs r3, #1 + 4329 0020 80F84030 strb r3, [r0, #64] +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4330 .loc 1 2267 5 discriminator 2 view .LVU1494 +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4331 .loc 1 2269 5 discriminator 2 view .LVU1495 +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4332 .loc 1 2269 23 is_stmt 0 discriminator 2 view .LVU1496 + 4333 0024 2223 movs r3, #34 + 4334 0026 80F84130 strb r3, [r0, #65] +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4335 .loc 1 2270 5 is_stmt 1 discriminator 2 view .LVU1497 +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4336 .loc 1 2270 23 is_stmt 0 discriminator 2 view .LVU1498 + 4337 002a 2023 movs r3, #32 + 4338 002c 80F84230 strb r3, [r0, #66] +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4339 .loc 1 2271 5 is_stmt 1 discriminator 2 view .LVU1499 +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4340 .loc 1 2271 23 is_stmt 0 discriminator 2 view .LVU1500 + 4341 0030 0023 movs r3, #0 + 4342 0032 4364 str r3, [r0, #68] +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + ARM GAS /tmp/ccE2rRGE.s page 220 + + + 4343 .loc 1 2274 5 is_stmt 1 discriminator 2 view .LVU1501 +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4344 .loc 1 2274 23 is_stmt 0 discriminator 2 view .LVU1502 + 4345 0034 4162 str r1, [r0, #36] +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4346 .loc 1 2275 5 is_stmt 1 discriminator 2 view .LVU1503 +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4347 .loc 1 2275 23 is_stmt 0 discriminator 2 view .LVU1504 + 4348 0036 4285 strh r2, [r0, #42] @ movhi +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4349 .loc 1 2276 5 is_stmt 1 discriminator 2 view .LVU1505 +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4350 .loc 1 2276 29 is_stmt 0 discriminator 2 view .LVU1506 + 4351 0038 438D ldrh r3, [r0, #42] +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4352 .loc 1 2276 23 discriminator 2 view .LVU1507 + 4353 003a 0385 strh r3, [r0, #40] @ movhi +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4354 .loc 1 2277 5 is_stmt 1 discriminator 2 view .LVU1508 +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4355 .loc 1 2277 23 is_stmt 0 discriminator 2 view .LVU1509 + 4356 003c 294B ldr r3, .L300 + 4357 003e C362 str r3, [r0, #44] +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4358 .loc 1 2278 5 is_stmt 1 discriminator 2 view .LVU1510 +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4359 .loc 1 2278 23 is_stmt 0 discriminator 2 view .LVU1511 + 4360 0040 294B ldr r3, .L300+4 + 4361 0042 4363 str r3, [r0, #52] +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4362 .loc 1 2280 5 is_stmt 1 discriminator 2 view .LVU1512 +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4363 .loc 1 2280 13 is_stmt 0 discriminator 2 view .LVU1513 + 4364 0044 C36B ldr r3, [r0, #60] +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4365 .loc 1 2280 8 discriminator 2 view .LVU1514 + 4366 0046 33B3 cbz r3, .L292 +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4367 .loc 1 2283 7 is_stmt 1 view .LVU1515 +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4368 .loc 1 2283 38 is_stmt 0 view .LVU1516 + 4369 0048 284A ldr r2, .L300+8 + 4370 .LVL265: +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4371 .loc 1 2283 38 view .LVU1517 + 4372 004a 9A62 str r2, [r3, #40] +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4373 .loc 1 2286 7 is_stmt 1 view .LVU1518 +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4374 .loc 1 2286 11 is_stmt 0 view .LVU1519 + 4375 004c C36B ldr r3, [r0, #60] +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4376 .loc 1 2286 39 view .LVU1520 + 4377 004e 284A ldr r2, .L300+12 + 4378 0050 1A63 str r2, [r3, #48] +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4379 .loc 1 2289 7 is_stmt 1 view .LVU1521 + ARM GAS /tmp/ccE2rRGE.s page 221 + + +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4380 .loc 1 2289 11 is_stmt 0 view .LVU1522 + 4381 0052 C26B ldr r2, [r0, #60] +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4382 .loc 1 2289 42 view .LVU1523 + 4383 0054 0023 movs r3, #0 + 4384 0056 D362 str r3, [r2, #44] +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4385 .loc 1 2290 7 is_stmt 1 view .LVU1524 +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4386 .loc 1 2290 11 is_stmt 0 view .LVU1525 + 4387 0058 C26B ldr r2, [r0, #60] +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4388 .loc 1 2290 39 view .LVU1526 + 4389 005a 5363 str r3, [r2, #52] +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4390 .loc 1 2293 7 is_stmt 1 view .LVU1527 +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4391 .loc 1 2293 69 is_stmt 0 view .LVU1528 + 4392 005c 0068 ldr r0, [r0] + 4393 .LVL266: +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4394 .loc 1 2293 23 view .LVU1529 + 4395 005e 238D ldrh r3, [r4, #40] + 4396 0060 0A46 mov r2, r1 + 4397 0062 00F12401 add r1, r0, #36 + 4398 .LVL267: +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4399 .loc 1 2293 23 view .LVU1530 + 4400 0066 E06B ldr r0, [r4, #60] + 4401 0068 FFF7FEFF bl HAL_DMA_Start_IT + 4402 .LVL268: +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4403 .loc 1 2311 5 is_stmt 1 view .LVU1531 +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4404 .loc 1 2311 8 is_stmt 0 view .LVU1532 + 4405 006c 0546 mov r5, r0 + 4406 006e 00B3 cbz r0, .L299 +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4407 .loc 1 2331 7 is_stmt 1 view .LVU1533 +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4408 .loc 1 2331 23 is_stmt 0 view .LVU1534 + 4409 0070 2823 movs r3, #40 + 4410 0072 84F84130 strb r3, [r4, #65] +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4411 .loc 1 2332 7 is_stmt 1 view .LVU1535 +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4412 .loc 1 2332 23 is_stmt 0 view .LVU1536 + 4413 0076 0022 movs r2, #0 + 4414 0078 84F84220 strb r2, [r4, #66] +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4415 .loc 1 2335 7 is_stmt 1 view .LVU1537 +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4416 .loc 1 2335 11 is_stmt 0 view .LVU1538 + 4417 007c 636C ldr r3, [r4, #68] +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4418 .loc 1 2335 23 view .LVU1539 + ARM GAS /tmp/ccE2rRGE.s page 222 + + + 4419 007e 43F01003 orr r3, r3, #16 + 4420 0082 6364 str r3, [r4, #68] +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4421 .loc 1 2338 7 is_stmt 1 view .LVU1540 +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4422 .loc 1 2338 7 view .LVU1541 + 4423 0084 84F84020 strb r2, [r4, #64] +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4424 .loc 1 2338 7 view .LVU1542 +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4425 .loc 1 2340 7 view .LVU1543 +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4426 .loc 1 2340 14 is_stmt 0 view .LVU1544 + 4427 0088 0125 movs r5, #1 + 4428 008a 26E0 b .L289 + 4429 .LVL269: + 4430 .L290: +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4431 .loc 1 2263 7 is_stmt 1 view .LVU1545 +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4432 .loc 1 2263 23 is_stmt 0 view .LVU1546 + 4433 008c 4FF40073 mov r3, #512 + 4434 0090 6364 str r3, [r4, #68] +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4435 .loc 1 2264 7 is_stmt 1 view .LVU1547 +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4436 .loc 1 2264 15 is_stmt 0 view .LVU1548 + 4437 0092 0125 movs r5, #1 + 4438 0094 21E0 b .L289 + 4439 .L292: +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4440 .loc 1 2299 7 is_stmt 1 view .LVU1549 +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4441 .loc 1 2299 23 is_stmt 0 view .LVU1550 + 4442 0096 2823 movs r3, #40 + 4443 0098 80F84130 strb r3, [r0, #65] +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4444 .loc 1 2300 7 is_stmt 1 view .LVU1551 +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4445 .loc 1 2300 23 is_stmt 0 view .LVU1552 + 4446 009c 0022 movs r2, #0 + 4447 .LVL270: +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4448 .loc 1 2300 23 view .LVU1553 + 4449 009e 80F84220 strb r2, [r0, #66] +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4450 .loc 1 2303 7 is_stmt 1 view .LVU1554 +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4451 .loc 1 2303 11 is_stmt 0 view .LVU1555 + 4452 00a2 436C ldr r3, [r0, #68] +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4453 .loc 1 2303 23 view .LVU1556 + 4454 00a4 43F08003 orr r3, r3, #128 + 4455 00a8 4364 str r3, [r0, #68] +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4456 .loc 1 2306 7 is_stmt 1 view .LVU1557 +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 223 + + + 4457 .loc 1 2306 7 view .LVU1558 + 4458 00aa 80F84020 strb r2, [r0, #64] +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4459 .loc 1 2306 7 view .LVU1559 +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4460 .loc 1 2308 7 view .LVU1560 +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4461 .loc 1 2308 14 is_stmt 0 view .LVU1561 + 4462 00ae 0125 movs r5, #1 + 4463 00b0 13E0 b .L289 + 4464 .LVL271: + 4465 .L299: +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4466 .loc 1 2314 7 is_stmt 1 view .LVU1562 +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4467 .loc 1 2314 11 is_stmt 0 view .LVU1563 + 4468 00b2 2268 ldr r2, [r4] +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4469 .loc 1 2314 21 view .LVU1564 + 4470 00b4 5368 ldr r3, [r2, #4] +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4471 .loc 1 2314 27 view .LVU1565 + 4472 00b6 23F40043 bic r3, r3, #32768 + 4473 00ba 5360 str r3, [r2, #4] +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4474 .loc 1 2317 7 is_stmt 1 view .LVU1566 +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4475 .loc 1 2317 7 view .LVU1567 + 4476 00bc 0023 movs r3, #0 + 4477 00be 84F84030 strb r3, [r4, #64] +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4478 .loc 1 2317 7 view .LVU1568 +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4479 .loc 1 2323 7 view .LVU1569 + 4480 00c2 4FF40041 mov r1, #32768 + 4481 00c6 2046 mov r0, r4 + 4482 .LVL272: +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4483 .loc 1 2323 7 is_stmt 0 view .LVU1570 + 4484 00c8 FFF7FEFF bl I2C_Enable_IRQ + 4485 .LVL273: +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4486 .loc 1 2326 7 is_stmt 1 view .LVU1571 +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4487 .loc 1 2326 11 is_stmt 0 view .LVU1572 + 4488 00cc 2268 ldr r2, [r4] +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4489 .loc 1 2326 21 view .LVU1573 + 4490 00ce 1368 ldr r3, [r2] +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4491 .loc 1 2326 27 view .LVU1574 + 4492 00d0 43F40043 orr r3, r3, #32768 + 4493 00d4 1360 str r3, [r2] +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4494 .loc 1 2343 5 is_stmt 1 view .LVU1575 +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4495 .loc 1 2343 12 is_stmt 0 view .LVU1576 + ARM GAS /tmp/ccE2rRGE.s page 224 + + + 4496 00d6 00E0 b .L289 + 4497 .LVL274: + 4498 .L295: +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4499 .loc 1 2347 12 view .LVU1577 + 4500 00d8 0225 movs r5, #2 + 4501 .LVL275: + 4502 .L289: +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 4503 .loc 1 2349 1 view .LVU1578 + 4504 00da 2846 mov r0, r5 + 4505 00dc 38BD pop {r3, r4, r5, pc} + 4506 .LVL276: + 4507 .L296: +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4508 .loc 1 2267 5 view .LVU1579 + 4509 00de 0225 movs r5, #2 + 4510 00e0 FBE7 b .L289 + 4511 .L301: + 4512 00e2 00BF .align 2 + 4513 .L300: + 4514 00e4 0000FFFF .word -65536 + 4515 00e8 00000000 .word I2C_Slave_ISR_DMA + 4516 00ec 00000000 .word I2C_DMASlaveReceiveCplt + 4517 00f0 00000000 .word I2C_DMAError + 4518 .cfi_endproc + 4519 .LFE145: + 4521 .section .text.HAL_I2C_Mem_Write,"ax",%progbits + 4522 .align 1 + 4523 .global HAL_I2C_Mem_Write + 4524 .syntax unified + 4525 .thumb + 4526 .thumb_func + 4528 HAL_I2C_Mem_Write: + 4529 .LVL277: + 4530 .LFB146: +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 4531 .loc 1 2365 1 is_stmt 1 view -0 + 4532 .cfi_startproc + 4533 @ args = 12, pretend = 0, frame = 0 + 4534 @ frame_needed = 0, uses_anonymous_args = 0 +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 4535 .loc 1 2365 1 is_stmt 0 view .LVU1581 + 4536 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 4537 .cfi_def_cfa_offset 36 + 4538 .cfi_offset 4, -36 + 4539 .cfi_offset 5, -32 + 4540 .cfi_offset 6, -28 + 4541 .cfi_offset 7, -24 + 4542 .cfi_offset 8, -20 + 4543 .cfi_offset 9, -16 + 4544 .cfi_offset 10, -12 + 4545 .cfi_offset 11, -8 + 4546 .cfi_offset 14, -4 + 4547 0004 83B0 sub sp, sp, #12 + 4548 .cfi_def_cfa_offset 48 + 4549 0006 0E46 mov r6, r1 + ARM GAS /tmp/ccE2rRGE.s page 225 + + + 4550 0008 BDF834A0 ldrh r10, [sp, #52] + 4551 000c 0E9D ldr r5, [sp, #56] +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4552 .loc 1 2366 3 is_stmt 1 view .LVU1582 +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4553 .loc 1 2369 3 view .LVU1583 +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4554 .loc 1 2371 3 view .LVU1584 +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4555 .loc 1 2371 11 is_stmt 0 view .LVU1585 + 4556 000e 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 4557 .LVL278: +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4558 .loc 1 2371 11 view .LVU1586 + 4559 0012 C9B2 uxtb r1, r1 +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4560 .loc 1 2371 6 view .LVU1587 + 4561 0014 2029 cmp r1, #32 + 4562 0016 40F0BB80 bne .L312 + 4563 001a 0446 mov r4, r0 + 4564 001c 9046 mov r8, r2 + 4565 001e 9946 mov r9, r3 +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4566 .loc 1 2373 5 is_stmt 1 view .LVU1588 +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4567 .loc 1 2373 8 is_stmt 0 view .LVU1589 + 4568 0020 0C9B ldr r3, [sp, #48] + 4569 .LVL279: +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4570 .loc 1 2373 8 view .LVU1590 + 4571 0022 CBB1 cbz r3, .L304 +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4572 .loc 1 2373 25 discriminator 1 view .LVU1591 + 4573 0024 BAF1000F cmp r10, #0 + 4574 0028 16D0 beq .L304 +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4575 .loc 1 2380 5 is_stmt 1 view .LVU1592 +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4576 .loc 1 2380 5 view .LVU1593 + 4577 002a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4578 002e 012B cmp r3, #1 + 4579 0030 00F0B280 beq .L313 +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4580 .loc 1 2380 5 discriminator 2 view .LVU1594 + 4581 0034 4FF0010B mov fp, #1 + 4582 0038 80F840B0 strb fp, [r0, #64] +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4583 .loc 1 2380 5 discriminator 2 view .LVU1595 +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4584 .loc 1 2383 5 discriminator 2 view .LVU1596 +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4585 .loc 1 2383 17 is_stmt 0 discriminator 2 view .LVU1597 + 4586 003c FFF7FEFF bl HAL_GetTick + 4587 .LVL280: +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4588 .loc 1 2383 17 discriminator 2 view .LVU1598 + 4589 0040 0746 mov r7, r0 + ARM GAS /tmp/ccE2rRGE.s page 226 + + + 4590 .LVL281: +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4591 .loc 1 2385 5 is_stmt 1 discriminator 2 view .LVU1599 +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4592 .loc 1 2385 9 is_stmt 0 discriminator 2 view .LVU1600 + 4593 0042 0090 str r0, [sp] + 4594 0044 1923 movs r3, #25 + 4595 0046 5A46 mov r2, fp + 4596 0048 4FF40041 mov r1, #32768 + 4597 004c 2046 mov r0, r4 + 4598 .LVL282: +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4599 .loc 1 2385 9 discriminator 2 view .LVU1601 + 4600 004e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4601 .LVL283: +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4602 .loc 1 2385 8 discriminator 2 view .LVU1602 + 4603 0052 30B1 cbz r0, .L319 +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4604 .loc 1 2387 14 view .LVU1603 + 4605 0054 0120 movs r0, #1 + 4606 0056 9CE0 b .L303 + 4607 .LVL284: + 4608 .L304: +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4609 .loc 1 2375 7 is_stmt 1 view .LVU1604 +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4610 .loc 1 2375 23 is_stmt 0 view .LVU1605 + 4611 0058 4FF40073 mov r3, #512 + 4612 005c 6364 str r3, [r4, #68] +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4613 .loc 1 2376 7 is_stmt 1 view .LVU1606 +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4614 .loc 1 2376 15 is_stmt 0 view .LVU1607 + 4615 005e 0120 movs r0, #1 + 4616 .LVL285: +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4617 .loc 1 2376 15 view .LVU1608 + 4618 0060 97E0 b .L303 + 4619 .LVL286: + 4620 .L319: +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4621 .loc 1 2390 5 is_stmt 1 view .LVU1609 +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4622 .loc 1 2390 21 is_stmt 0 view .LVU1610 + 4623 0062 2123 movs r3, #33 + 4624 0064 84F84130 strb r3, [r4, #65] +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4625 .loc 1 2391 5 is_stmt 1 view .LVU1611 +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4626 .loc 1 2391 21 is_stmt 0 view .LVU1612 + 4627 0068 4023 movs r3, #64 + 4628 006a 84F84230 strb r3, [r4, #66] +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4629 .loc 1 2392 5 is_stmt 1 view .LVU1613 +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4630 .loc 1 2392 21 is_stmt 0 view .LVU1614 + ARM GAS /tmp/ccE2rRGE.s page 227 + + + 4631 006e 0023 movs r3, #0 + 4632 0070 6364 str r3, [r4, #68] +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4633 .loc 1 2395 5 is_stmt 1 view .LVU1615 +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4634 .loc 1 2395 21 is_stmt 0 view .LVU1616 + 4635 0072 0C9A ldr r2, [sp, #48] + 4636 0074 6262 str r2, [r4, #36] +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 4637 .loc 1 2396 5 is_stmt 1 view .LVU1617 +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 4638 .loc 1 2396 21 is_stmt 0 view .LVU1618 + 4639 0076 A4F82AA0 strh r10, [r4, #42] @ movhi +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4640 .loc 1 2397 5 is_stmt 1 view .LVU1619 +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4641 .loc 1 2397 21 is_stmt 0 view .LVU1620 + 4642 007a 6363 str r3, [r4, #52] +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4643 .loc 1 2400 5 is_stmt 1 view .LVU1621 +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4644 .loc 1 2400 9 is_stmt 0 view .LVU1622 + 4645 007c 0197 str r7, [sp, #4] + 4646 007e 0095 str r5, [sp] + 4647 0080 4B46 mov r3, r9 + 4648 0082 4246 mov r2, r8 + 4649 0084 3146 mov r1, r6 + 4650 0086 2046 mov r0, r4 + 4651 0088 FFF7FEFF bl I2C_RequestMemoryWrite + 4652 .LVL287: +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4653 .loc 1 2400 8 view .LVU1623 + 4654 008c 70B9 cbnz r0, .L320 +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4655 .loc 1 2408 5 is_stmt 1 view .LVU1624 +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4656 .loc 1 2408 13 is_stmt 0 view .LVU1625 + 4657 008e 638D ldrh r3, [r4, #42] + 4658 0090 9BB2 uxth r3, r3 +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4659 .loc 1 2408 8 view .LVU1626 + 4660 0092 FF2B cmp r3, #255 + 4661 0094 0FD9 bls .L307 +2410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 4662 .loc 1 2410 7 is_stmt 1 view .LVU1627 +2410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 4663 .loc 1 2410 22 is_stmt 0 view .LVU1628 + 4664 0096 FF22 movs r2, #255 + 4665 0098 2285 strh r2, [r4, #40] @ movhi +2411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4666 .loc 1 2411 7 is_stmt 1 view .LVU1629 + 4667 009a 0023 movs r3, #0 + 4668 009c 0093 str r3, [sp] + 4669 009e 4FF08073 mov r3, #16777216 + 4670 00a2 3146 mov r1, r6 + 4671 00a4 2046 mov r0, r4 + 4672 00a6 FFF7FEFF bl I2C_TransferConfig + ARM GAS /tmp/ccE2rRGE.s page 228 + + + 4673 .LVL288: + 4674 00aa 21E0 b .L311 + 4675 .L320: +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4676 .loc 1 2403 7 view .LVU1630 +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4677 .loc 1 2403 7 view .LVU1631 + 4678 00ac 0023 movs r3, #0 + 4679 00ae 84F84030 strb r3, [r4, #64] +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4680 .loc 1 2403 7 view .LVU1632 +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4681 .loc 1 2404 7 view .LVU1633 +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4682 .loc 1 2404 14 is_stmt 0 view .LVU1634 + 4683 00b2 5846 mov r0, fp + 4684 00b4 6DE0 b .L303 + 4685 .L307: +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 4686 .loc 1 2415 7 is_stmt 1 view .LVU1635 +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 4687 .loc 1 2415 28 is_stmt 0 view .LVU1636 + 4688 00b6 628D ldrh r2, [r4, #42] + 4689 00b8 92B2 uxth r2, r2 +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 4690 .loc 1 2415 22 view .LVU1637 + 4691 00ba 2285 strh r2, [r4, #40] @ movhi +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4692 .loc 1 2416 7 is_stmt 1 view .LVU1638 + 4693 00bc 0023 movs r3, #0 + 4694 00be 0093 str r3, [sp] + 4695 00c0 4FF00073 mov r3, #33554432 + 4696 00c4 D2B2 uxtb r2, r2 + 4697 00c6 3146 mov r1, r6 + 4698 00c8 2046 mov r0, r4 + 4699 00ca FFF7FEFF bl I2C_TransferConfig + 4700 .LVL289: + 4701 00ce 0FE0 b .L311 + 4702 .L310: +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 4703 .loc 1 2452 11 view .LVU1639 +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 4704 .loc 1 2452 32 is_stmt 0 view .LVU1640 + 4705 00d0 628D ldrh r2, [r4, #42] + 4706 00d2 92B2 uxth r2, r2 +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 4707 .loc 1 2452 26 view .LVU1641 + 4708 00d4 2285 strh r2, [r4, #40] @ movhi +2453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 4709 .loc 1 2453 11 is_stmt 1 view .LVU1642 + 4710 00d6 0023 movs r3, #0 + 4711 00d8 0093 str r3, [sp] + 4712 00da 4FF00073 mov r3, #33554432 + 4713 00de D2B2 uxtb r2, r2 + 4714 00e0 3146 mov r1, r6 + 4715 00e2 2046 mov r0, r4 + 4716 00e4 FFF7FEFF bl I2C_TransferConfig + ARM GAS /tmp/ccE2rRGE.s page 229 + + + 4717 .LVL290: + 4718 .L309: +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4719 .loc 1 2458 30 view .LVU1643 +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4720 .loc 1 2458 18 is_stmt 0 view .LVU1644 + 4721 00e8 638D ldrh r3, [r4, #42] + 4722 00ea 9BB2 uxth r3, r3 +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4723 .loc 1 2458 30 view .LVU1645 + 4724 00ec 002B cmp r3, #0 + 4725 00ee 33D0 beq .L321 + 4726 .L311: +2419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4727 .loc 1 2419 5 is_stmt 1 view .LVU1646 +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4728 .loc 1 2422 7 view .LVU1647 +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4729 .loc 1 2422 11 is_stmt 0 view .LVU1648 + 4730 00f0 3A46 mov r2, r7 + 4731 00f2 2946 mov r1, r5 + 4732 00f4 2046 mov r0, r4 + 4733 00f6 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 4734 .LVL291: +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4735 .loc 1 2422 10 view .LVU1649 + 4736 00fa 0028 cmp r0, #0 + 4737 00fc 4ED1 bne .L315 +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4738 .loc 1 2428 7 is_stmt 1 view .LVU1650 +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4739 .loc 1 2428 35 is_stmt 0 view .LVU1651 + 4740 00fe 626A ldr r2, [r4, #36] +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4741 .loc 1 2428 11 view .LVU1652 + 4742 0100 2368 ldr r3, [r4] +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4743 .loc 1 2428 30 view .LVU1653 + 4744 0102 1278 ldrb r2, [r2] @ zero_extendqisi2 +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4745 .loc 1 2428 28 view .LVU1654 + 4746 0104 9A62 str r2, [r3, #40] +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4747 .loc 1 2431 7 is_stmt 1 view .LVU1655 +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4748 .loc 1 2431 11 is_stmt 0 view .LVU1656 + 4749 0106 636A ldr r3, [r4, #36] +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4750 .loc 1 2431 21 view .LVU1657 + 4751 0108 0133 adds r3, r3, #1 + 4752 010a 6362 str r3, [r4, #36] +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 4753 .loc 1 2433 7 is_stmt 1 view .LVU1658 +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 4754 .loc 1 2433 11 is_stmt 0 view .LVU1659 + 4755 010c 638D ldrh r3, [r4, #42] + 4756 010e 9BB2 uxth r3, r3 + ARM GAS /tmp/ccE2rRGE.s page 230 + + +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 4757 .loc 1 2433 22 view .LVU1660 + 4758 0110 013B subs r3, r3, #1 + 4759 0112 9BB2 uxth r3, r3 + 4760 0114 6385 strh r3, [r4, #42] @ movhi +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4761 .loc 1 2434 7 is_stmt 1 view .LVU1661 +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4762 .loc 1 2434 11 is_stmt 0 view .LVU1662 + 4763 0116 238D ldrh r3, [r4, #40] +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4764 .loc 1 2434 21 view .LVU1663 + 4765 0118 013B subs r3, r3, #1 + 4766 011a 9BB2 uxth r3, r3 + 4767 011c 2385 strh r3, [r4, #40] @ movhi +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4768 .loc 1 2436 7 is_stmt 1 view .LVU1664 +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4769 .loc 1 2436 16 is_stmt 0 view .LVU1665 + 4770 011e 628D ldrh r2, [r4, #42] + 4771 0120 92B2 uxth r2, r2 +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4772 .loc 1 2436 10 view .LVU1666 + 4773 0122 002A cmp r2, #0 + 4774 0124 E0D0 beq .L309 +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4775 .loc 1 2436 35 discriminator 1 view .LVU1667 + 4776 0126 002B cmp r3, #0 + 4777 0128 DED1 bne .L309 +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4778 .loc 1 2439 9 is_stmt 1 view .LVU1668 +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4779 .loc 1 2439 13 is_stmt 0 view .LVU1669 + 4780 012a 0097 str r7, [sp] + 4781 012c 2B46 mov r3, r5 + 4782 012e 0022 movs r2, #0 + 4783 0130 8021 movs r1, #128 + 4784 0132 2046 mov r0, r4 + 4785 0134 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4786 .LVL292: +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4787 .loc 1 2439 12 view .LVU1670 + 4788 0138 90BB cbnz r0, .L316 +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4789 .loc 1 2444 9 is_stmt 1 view .LVU1671 +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4790 .loc 1 2444 17 is_stmt 0 view .LVU1672 + 4791 013a 638D ldrh r3, [r4, #42] + 4792 013c 9BB2 uxth r3, r3 +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4793 .loc 1 2444 12 view .LVU1673 + 4794 013e FF2B cmp r3, #255 + 4795 0140 C6D9 bls .L310 +2446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 4796 .loc 1 2446 11 is_stmt 1 view .LVU1674 +2446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 4797 .loc 1 2446 26 is_stmt 0 view .LVU1675 + ARM GAS /tmp/ccE2rRGE.s page 231 + + + 4798 0142 FF22 movs r2, #255 + 4799 0144 2285 strh r2, [r4, #40] @ movhi +2447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 4800 .loc 1 2447 11 is_stmt 1 view .LVU1676 + 4801 0146 0023 movs r3, #0 + 4802 0148 0093 str r3, [sp] + 4803 014a 4FF08073 mov r3, #16777216 + 4804 014e 3146 mov r1, r6 + 4805 0150 2046 mov r0, r4 + 4806 0152 FFF7FEFF bl I2C_TransferConfig + 4807 .LVL293: + 4808 0156 C7E7 b .L309 + 4809 .L321: +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4810 .loc 1 2462 5 view .LVU1677 +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4811 .loc 1 2462 9 is_stmt 0 view .LVU1678 + 4812 0158 3A46 mov r2, r7 + 4813 015a 2946 mov r1, r5 + 4814 015c 2046 mov r0, r4 + 4815 015e FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 4816 .LVL294: +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4817 .loc 1 2462 8 view .LVU1679 + 4818 0162 F8B9 cbnz r0, .L317 +2468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4819 .loc 1 2468 5 is_stmt 1 view .LVU1680 + 4820 0164 2368 ldr r3, [r4] + 4821 0166 2022 movs r2, #32 + 4822 0168 DA61 str r2, [r3, #28] +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4823 .loc 1 2471 5 view .LVU1681 + 4824 016a 2168 ldr r1, [r4] + 4825 016c 4B68 ldr r3, [r1, #4] + 4826 016e 23F0FF73 bic r3, r3, #33423360 + 4827 0172 23F48B33 bic r3, r3, #71168 + 4828 0176 23F4FF73 bic r3, r3, #510 + 4829 017a 23F00103 bic r3, r3, #1 + 4830 017e 4B60 str r3, [r1, #4] +2473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4831 .loc 1 2473 5 view .LVU1682 +2473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4832 .loc 1 2473 17 is_stmt 0 view .LVU1683 + 4833 0180 84F84120 strb r2, [r4, #65] +2474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4834 .loc 1 2474 5 is_stmt 1 view .LVU1684 +2474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4835 .loc 1 2474 17 is_stmt 0 view .LVU1685 + 4836 0184 0023 movs r3, #0 + 4837 0186 84F84230 strb r3, [r4, #66] +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4838 .loc 1 2477 5 is_stmt 1 view .LVU1686 +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4839 .loc 1 2477 5 view .LVU1687 + 4840 018a 84F84030 strb r3, [r4, #64] +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4841 .loc 1 2477 5 view .LVU1688 + ARM GAS /tmp/ccE2rRGE.s page 232 + + +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4842 .loc 1 2479 5 view .LVU1689 +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4843 .loc 1 2479 12 is_stmt 0 view .LVU1690 + 4844 018e 00E0 b .L303 + 4845 .LVL295: + 4846 .L312: +2483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4847 .loc 1 2483 12 view .LVU1691 + 4848 0190 0220 movs r0, #2 + 4849 .LVL296: + 4850 .L303: +2485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4851 .loc 1 2485 1 view .LVU1692 + 4852 0192 03B0 add sp, sp, #12 + 4853 .cfi_remember_state + 4854 .cfi_def_cfa_offset 36 + 4855 @ sp needed + 4856 0194 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 4857 .LVL297: + 4858 .L313: + 4859 .cfi_restore_state +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4860 .loc 1 2380 5 view .LVU1693 + 4861 0198 0220 movs r0, #2 + 4862 .LVL298: +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4863 .loc 1 2380 5 view .LVU1694 + 4864 019a FAE7 b .L303 + 4865 .LVL299: + 4866 .L315: +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4867 .loc 1 2424 16 view .LVU1695 + 4868 019c 0120 movs r0, #1 + 4869 019e F8E7 b .L303 + 4870 .L316: +2441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4871 .loc 1 2441 18 view .LVU1696 + 4872 01a0 0120 movs r0, #1 + 4873 01a2 F6E7 b .L303 + 4874 .L317: +2464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4875 .loc 1 2464 14 view .LVU1697 + 4876 01a4 0120 movs r0, #1 + 4877 01a6 F4E7 b .L303 + 4878 .cfi_endproc + 4879 .LFE146: + 4881 .section .text.HAL_I2C_Mem_Read,"ax",%progbits + 4882 .align 1 + 4883 .global HAL_I2C_Mem_Read + 4884 .syntax unified + 4885 .thumb + 4886 .thumb_func + 4888 HAL_I2C_Mem_Read: + 4889 .LVL300: + 4890 .LFB147: +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + ARM GAS /tmp/ccE2rRGE.s page 233 + + + 4891 .loc 1 2502 1 is_stmt 1 view -0 + 4892 .cfi_startproc + 4893 @ args = 12, pretend = 0, frame = 0 + 4894 @ frame_needed = 0, uses_anonymous_args = 0 +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 4895 .loc 1 2502 1 is_stmt 0 view .LVU1699 + 4896 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 4897 .cfi_def_cfa_offset 36 + 4898 .cfi_offset 4, -36 + 4899 .cfi_offset 5, -32 + 4900 .cfi_offset 6, -28 + 4901 .cfi_offset 7, -24 + 4902 .cfi_offset 8, -20 + 4903 .cfi_offset 9, -16 + 4904 .cfi_offset 10, -12 + 4905 .cfi_offset 11, -8 + 4906 .cfi_offset 14, -4 + 4907 0004 83B0 sub sp, sp, #12 + 4908 .cfi_def_cfa_offset 48 + 4909 0006 0E46 mov r6, r1 + 4910 0008 BDF834A0 ldrh r10, [sp, #52] + 4911 000c 0E9D ldr r5, [sp, #56] +2503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4912 .loc 1 2503 3 is_stmt 1 view .LVU1700 +2506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4913 .loc 1 2506 3 view .LVU1701 +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4914 .loc 1 2508 3 view .LVU1702 +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4915 .loc 1 2508 11 is_stmt 0 view .LVU1703 + 4916 000e 90F84110 ldrb r1, [r0, #65] @ zero_extendqisi2 + 4917 .LVL301: +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4918 .loc 1 2508 11 view .LVU1704 + 4919 0012 C9B2 uxtb r1, r1 +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4920 .loc 1 2508 6 view .LVU1705 + 4921 0014 2029 cmp r1, #32 + 4922 0016 40F0BC80 bne .L332 + 4923 001a 0446 mov r4, r0 + 4924 001c 9046 mov r8, r2 + 4925 001e 9946 mov r9, r3 +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4926 .loc 1 2510 5 is_stmt 1 view .LVU1706 +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4927 .loc 1 2510 8 is_stmt 0 view .LVU1707 + 4928 0020 0C9B ldr r3, [sp, #48] + 4929 .LVL302: +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4930 .loc 1 2510 8 view .LVU1708 + 4931 0022 CBB1 cbz r3, .L324 +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4932 .loc 1 2510 25 discriminator 1 view .LVU1709 + 4933 0024 BAF1000F cmp r10, #0 + 4934 0028 16D0 beq .L324 +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4935 .loc 1 2517 5 is_stmt 1 view .LVU1710 + ARM GAS /tmp/ccE2rRGE.s page 234 + + +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4936 .loc 1 2517 5 view .LVU1711 + 4937 002a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 4938 002e 012B cmp r3, #1 + 4939 0030 00F0B380 beq .L333 +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4940 .loc 1 2517 5 discriminator 2 view .LVU1712 + 4941 0034 4FF0010B mov fp, #1 + 4942 0038 80F840B0 strb fp, [r0, #64] +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4943 .loc 1 2517 5 discriminator 2 view .LVU1713 +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4944 .loc 1 2520 5 discriminator 2 view .LVU1714 +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4945 .loc 1 2520 17 is_stmt 0 discriminator 2 view .LVU1715 + 4946 003c FFF7FEFF bl HAL_GetTick + 4947 .LVL303: +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4948 .loc 1 2520 17 discriminator 2 view .LVU1716 + 4949 0040 0746 mov r7, r0 + 4950 .LVL304: +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4951 .loc 1 2522 5 is_stmt 1 discriminator 2 view .LVU1717 +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4952 .loc 1 2522 9 is_stmt 0 discriminator 2 view .LVU1718 + 4953 0042 0090 str r0, [sp] + 4954 0044 1923 movs r3, #25 + 4955 0046 5A46 mov r2, fp + 4956 0048 4FF40041 mov r1, #32768 + 4957 004c 2046 mov r0, r4 + 4958 .LVL305: +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4959 .loc 1 2522 9 discriminator 2 view .LVU1719 + 4960 004e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4961 .LVL306: +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4962 .loc 1 2522 8 discriminator 2 view .LVU1720 + 4963 0052 30B1 cbz r0, .L339 +2524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4964 .loc 1 2524 14 view .LVU1721 + 4965 0054 0120 movs r0, #1 + 4966 0056 9DE0 b .L323 + 4967 .LVL307: + 4968 .L324: +2512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4969 .loc 1 2512 7 is_stmt 1 view .LVU1722 +2512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4970 .loc 1 2512 23 is_stmt 0 view .LVU1723 + 4971 0058 4FF40073 mov r3, #512 + 4972 005c 6364 str r3, [r4, #68] +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4973 .loc 1 2513 7 is_stmt 1 view .LVU1724 +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4974 .loc 1 2513 15 is_stmt 0 view .LVU1725 + 4975 005e 0120 movs r0, #1 + 4976 .LVL308: +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 235 + + + 4977 .loc 1 2513 15 view .LVU1726 + 4978 0060 98E0 b .L323 + 4979 .LVL309: + 4980 .L339: +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4981 .loc 1 2527 5 is_stmt 1 view .LVU1727 +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4982 .loc 1 2527 21 is_stmt 0 view .LVU1728 + 4983 0062 2223 movs r3, #34 + 4984 0064 84F84130 strb r3, [r4, #65] +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4985 .loc 1 2528 5 is_stmt 1 view .LVU1729 +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4986 .loc 1 2528 21 is_stmt 0 view .LVU1730 + 4987 0068 4023 movs r3, #64 + 4988 006a 84F84230 strb r3, [r4, #66] +2529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4989 .loc 1 2529 5 is_stmt 1 view .LVU1731 +2529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 4990 .loc 1 2529 21 is_stmt 0 view .LVU1732 + 4991 006e 0023 movs r3, #0 + 4992 0070 6364 str r3, [r4, #68] +2532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4993 .loc 1 2532 5 is_stmt 1 view .LVU1733 +2532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4994 .loc 1 2532 21 is_stmt 0 view .LVU1734 + 4995 0072 0C9A ldr r2, [sp, #48] + 4996 0074 6262 str r2, [r4, #36] +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 4997 .loc 1 2533 5 is_stmt 1 view .LVU1735 +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 4998 .loc 1 2533 21 is_stmt 0 view .LVU1736 + 4999 0076 A4F82AA0 strh r10, [r4, #42] @ movhi +2534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5000 .loc 1 2534 5 is_stmt 1 view .LVU1737 +2534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5001 .loc 1 2534 21 is_stmt 0 view .LVU1738 + 5002 007a 6363 str r3, [r4, #52] +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5003 .loc 1 2537 5 is_stmt 1 view .LVU1739 +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5004 .loc 1 2537 9 is_stmt 0 view .LVU1740 + 5005 007c 0197 str r7, [sp, #4] + 5006 007e 0095 str r5, [sp] + 5007 0080 4B46 mov r3, r9 + 5008 0082 4246 mov r2, r8 + 5009 0084 3146 mov r1, r6 + 5010 0086 2046 mov r0, r4 + 5011 0088 FFF7FEFF bl I2C_RequestMemoryRead + 5012 .LVL310: +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5013 .loc 1 2537 8 view .LVU1741 + 5014 008c 70B9 cbnz r0, .L340 +2546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5015 .loc 1 2546 5 is_stmt 1 view .LVU1742 +2546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5016 .loc 1 2546 13 is_stmt 0 view .LVU1743 + ARM GAS /tmp/ccE2rRGE.s page 236 + + + 5017 008e 638D ldrh r3, [r4, #42] + 5018 0090 9BB2 uxth r3, r3 +2546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5019 .loc 1 2546 8 view .LVU1744 + 5020 0092 FF2B cmp r3, #255 + 5021 0094 0FD9 bls .L327 +2548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5022 .loc 1 2548 7 is_stmt 1 view .LVU1745 +2548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5023 .loc 1 2548 22 is_stmt 0 view .LVU1746 + 5024 0096 FF22 movs r2, #255 + 5025 0098 2285 strh r2, [r4, #40] @ movhi +2549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 5026 .loc 1 2549 7 is_stmt 1 view .LVU1747 + 5027 009a 444B ldr r3, .L342 + 5028 009c 0093 str r3, [sp] + 5029 009e 4FF08073 mov r3, #16777216 + 5030 00a2 3146 mov r1, r6 + 5031 00a4 2046 mov r0, r4 + 5032 00a6 FFF7FEFF bl I2C_TransferConfig + 5033 .LVL311: + 5034 00aa 21E0 b .L331 + 5035 .L340: +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5036 .loc 1 2540 7 view .LVU1748 +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5037 .loc 1 2540 7 view .LVU1749 + 5038 00ac 0023 movs r3, #0 + 5039 00ae 84F84030 strb r3, [r4, #64] +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5040 .loc 1 2540 7 view .LVU1750 +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5041 .loc 1 2541 7 view .LVU1751 +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5042 .loc 1 2541 14 is_stmt 0 view .LVU1752 + 5043 00b2 5846 mov r0, fp + 5044 00b4 6EE0 b .L323 + 5045 .L327: +2554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5046 .loc 1 2554 7 is_stmt 1 view .LVU1753 +2554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5047 .loc 1 2554 28 is_stmt 0 view .LVU1754 + 5048 00b6 628D ldrh r2, [r4, #42] + 5049 00b8 92B2 uxth r2, r2 +2554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5050 .loc 1 2554 22 view .LVU1755 + 5051 00ba 2285 strh r2, [r4, #40] @ movhi +2555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 5052 .loc 1 2555 7 is_stmt 1 view .LVU1756 + 5053 00bc 3B4B ldr r3, .L342 + 5054 00be 0093 str r3, [sp] + 5055 00c0 4FF00073 mov r3, #33554432 + 5056 00c4 D2B2 uxtb r2, r2 + 5057 00c6 3146 mov r1, r6 + 5058 00c8 2046 mov r0, r4 + 5059 00ca FFF7FEFF bl I2C_TransferConfig + 5060 .LVL312: + ARM GAS /tmp/ccE2rRGE.s page 237 + + + 5061 00ce 0FE0 b .L331 + 5062 .L330: +2592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5063 .loc 1 2592 11 view .LVU1757 +2592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5064 .loc 1 2592 32 is_stmt 0 view .LVU1758 + 5065 00d0 628D ldrh r2, [r4, #42] + 5066 00d2 92B2 uxth r2, r2 +2592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5067 .loc 1 2592 26 view .LVU1759 + 5068 00d4 2285 strh r2, [r4, #40] @ movhi +2593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5069 .loc 1 2593 11 is_stmt 1 view .LVU1760 + 5070 00d6 0023 movs r3, #0 + 5071 00d8 0093 str r3, [sp] + 5072 00da 4FF00073 mov r3, #33554432 + 5073 00de D2B2 uxtb r2, r2 + 5074 00e0 3146 mov r1, r6 + 5075 00e2 2046 mov r0, r4 + 5076 00e4 FFF7FEFF bl I2C_TransferConfig + 5077 .LVL313: + 5078 .L329: +2597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5079 .loc 1 2597 30 view .LVU1761 +2597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5080 .loc 1 2597 18 is_stmt 0 view .LVU1762 + 5081 00e8 638D ldrh r3, [r4, #42] + 5082 00ea 9BB2 uxth r3, r3 +2597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5083 .loc 1 2597 30 view .LVU1763 + 5084 00ec 002B cmp r3, #0 + 5085 00ee 34D0 beq .L341 + 5086 .L331: +2559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5087 .loc 1 2559 5 is_stmt 1 view .LVU1764 +2562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5088 .loc 1 2562 7 view .LVU1765 +2562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5089 .loc 1 2562 11 is_stmt 0 view .LVU1766 + 5090 00f0 0097 str r7, [sp] + 5091 00f2 2B46 mov r3, r5 + 5092 00f4 0022 movs r2, #0 + 5093 00f6 0421 movs r1, #4 + 5094 00f8 2046 mov r0, r4 + 5095 00fa FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5096 .LVL314: +2562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5097 .loc 1 2562 10 view .LVU1767 + 5098 00fe 0028 cmp r0, #0 + 5099 0100 4DD1 bne .L335 +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5100 .loc 1 2568 7 is_stmt 1 view .LVU1768 +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5101 .loc 1 2568 38 is_stmt 0 view .LVU1769 + 5102 0102 2368 ldr r3, [r4] +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5103 .loc 1 2568 48 view .LVU1770 + ARM GAS /tmp/ccE2rRGE.s page 238 + + + 5104 0104 5A6A ldr r2, [r3, #36] +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5105 .loc 1 2568 12 view .LVU1771 + 5106 0106 636A ldr r3, [r4, #36] +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5107 .loc 1 2568 23 view .LVU1772 + 5108 0108 1A70 strb r2, [r3] +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5109 .loc 1 2571 7 is_stmt 1 view .LVU1773 +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5110 .loc 1 2571 11 is_stmt 0 view .LVU1774 + 5111 010a 636A ldr r3, [r4, #36] +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5112 .loc 1 2571 21 view .LVU1775 + 5113 010c 0133 adds r3, r3, #1 + 5114 010e 6362 str r3, [r4, #36] +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 5115 .loc 1 2573 7 is_stmt 1 view .LVU1776 +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 5116 .loc 1 2573 11 is_stmt 0 view .LVU1777 + 5117 0110 228D ldrh r2, [r4, #40] +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 5118 .loc 1 2573 21 view .LVU1778 + 5119 0112 013A subs r2, r2, #1 + 5120 0114 92B2 uxth r2, r2 + 5121 0116 2285 strh r2, [r4, #40] @ movhi +2574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5122 .loc 1 2574 7 is_stmt 1 view .LVU1779 +2574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5123 .loc 1 2574 11 is_stmt 0 view .LVU1780 + 5124 0118 638D ldrh r3, [r4, #42] + 5125 011a 9BB2 uxth r3, r3 +2574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5126 .loc 1 2574 22 view .LVU1781 + 5127 011c 013B subs r3, r3, #1 + 5128 011e 9BB2 uxth r3, r3 + 5129 0120 6385 strh r3, [r4, #42] @ movhi +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5130 .loc 1 2576 7 is_stmt 1 view .LVU1782 +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5131 .loc 1 2576 16 is_stmt 0 view .LVU1783 + 5132 0122 638D ldrh r3, [r4, #42] + 5133 0124 9BB2 uxth r3, r3 +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5134 .loc 1 2576 10 view .LVU1784 + 5135 0126 002B cmp r3, #0 + 5136 0128 DED0 beq .L329 +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5137 .loc 1 2576 35 discriminator 1 view .LVU1785 + 5138 012a 002A cmp r2, #0 + 5139 012c DCD1 bne .L329 +2579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5140 .loc 1 2579 9 is_stmt 1 view .LVU1786 +2579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5141 .loc 1 2579 13 is_stmt 0 view .LVU1787 + 5142 012e 0097 str r7, [sp] + 5143 0130 2B46 mov r3, r5 + ARM GAS /tmp/ccE2rRGE.s page 239 + + + 5144 0132 8021 movs r1, #128 + 5145 0134 2046 mov r0, r4 + 5146 0136 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5147 .LVL315: +2579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5148 .loc 1 2579 12 view .LVU1788 + 5149 013a 90BB cbnz r0, .L336 +2584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5150 .loc 1 2584 9 is_stmt 1 view .LVU1789 +2584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5151 .loc 1 2584 17 is_stmt 0 view .LVU1790 + 5152 013c 638D ldrh r3, [r4, #42] + 5153 013e 9BB2 uxth r3, r3 +2584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5154 .loc 1 2584 12 view .LVU1791 + 5155 0140 FF2B cmp r3, #255 + 5156 0142 C5D9 bls .L330 +2586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + 5157 .loc 1 2586 11 is_stmt 1 view .LVU1792 +2586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + 5158 .loc 1 2586 26 is_stmt 0 view .LVU1793 + 5159 0144 FF22 movs r2, #255 + 5160 0146 2285 strh r2, [r4, #40] @ movhi +2587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5161 .loc 1 2587 11 is_stmt 1 view .LVU1794 + 5162 0148 0023 movs r3, #0 + 5163 014a 0093 str r3, [sp] + 5164 014c 4FF08073 mov r3, #16777216 + 5165 0150 3146 mov r1, r6 + 5166 0152 2046 mov r0, r4 + 5167 0154 FFF7FEFF bl I2C_TransferConfig + 5168 .LVL316: + 5169 0158 C6E7 b .L329 + 5170 .L341: +2601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5171 .loc 1 2601 5 view .LVU1795 +2601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5172 .loc 1 2601 9 is_stmt 0 view .LVU1796 + 5173 015a 3A46 mov r2, r7 + 5174 015c 2946 mov r1, r5 + 5175 015e 2046 mov r0, r4 + 5176 0160 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 5177 .LVL317: +2601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5178 .loc 1 2601 8 view .LVU1797 + 5179 0164 F8B9 cbnz r0, .L337 +2607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5180 .loc 1 2607 5 is_stmt 1 view .LVU1798 + 5181 0166 2368 ldr r3, [r4] + 5182 0168 2022 movs r2, #32 + 5183 016a DA61 str r2, [r3, #28] +2610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5184 .loc 1 2610 5 view .LVU1799 + 5185 016c 2168 ldr r1, [r4] + 5186 016e 4B68 ldr r3, [r1, #4] + 5187 0170 23F0FF73 bic r3, r3, #33423360 + 5188 0174 23F48B33 bic r3, r3, #71168 + ARM GAS /tmp/ccE2rRGE.s page 240 + + + 5189 0178 23F4FF73 bic r3, r3, #510 + 5190 017c 23F00103 bic r3, r3, #1 + 5191 0180 4B60 str r3, [r1, #4] +2612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5192 .loc 1 2612 5 view .LVU1800 +2612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5193 .loc 1 2612 17 is_stmt 0 view .LVU1801 + 5194 0182 84F84120 strb r2, [r4, #65] +2613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5195 .loc 1 2613 5 is_stmt 1 view .LVU1802 +2613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5196 .loc 1 2613 17 is_stmt 0 view .LVU1803 + 5197 0186 0023 movs r3, #0 + 5198 0188 84F84230 strb r3, [r4, #66] +2616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5199 .loc 1 2616 5 is_stmt 1 view .LVU1804 +2616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5200 .loc 1 2616 5 view .LVU1805 + 5201 018c 84F84030 strb r3, [r4, #64] +2616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5202 .loc 1 2616 5 view .LVU1806 +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5203 .loc 1 2618 5 view .LVU1807 +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5204 .loc 1 2618 12 is_stmt 0 view .LVU1808 + 5205 0190 00E0 b .L323 + 5206 .LVL318: + 5207 .L332: +2622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5208 .loc 1 2622 12 view .LVU1809 + 5209 0192 0220 movs r0, #2 + 5210 .LVL319: + 5211 .L323: +2624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 5212 .loc 1 2624 1 view .LVU1810 + 5213 0194 03B0 add sp, sp, #12 + 5214 .cfi_remember_state + 5215 .cfi_def_cfa_offset 36 + 5216 @ sp needed + 5217 0196 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 5218 .LVL320: + 5219 .L333: + 5220 .cfi_restore_state +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5221 .loc 1 2517 5 view .LVU1811 + 5222 019a 0220 movs r0, #2 + 5223 .LVL321: +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5224 .loc 1 2517 5 view .LVU1812 + 5225 019c FAE7 b .L323 + 5226 .LVL322: + 5227 .L335: +2564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5228 .loc 1 2564 16 view .LVU1813 + 5229 019e 0120 movs r0, #1 + 5230 01a0 F8E7 b .L323 + 5231 .L336: + ARM GAS /tmp/ccE2rRGE.s page 241 + + +2581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5232 .loc 1 2581 18 view .LVU1814 + 5233 01a2 0120 movs r0, #1 + 5234 01a4 F6E7 b .L323 + 5235 .L337: +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5236 .loc 1 2603 14 view .LVU1815 + 5237 01a6 0120 movs r0, #1 + 5238 01a8 F4E7 b .L323 + 5239 .L343: + 5240 01aa 00BF .align 2 + 5241 .L342: + 5242 01ac 00240080 .word -2147474432 + 5243 .cfi_endproc + 5244 .LFE147: + 5246 .section .text.HAL_I2C_Mem_Write_IT,"ax",%progbits + 5247 .align 1 + 5248 .global HAL_I2C_Mem_Write_IT + 5249 .syntax unified + 5250 .thumb + 5251 .thumb_func + 5253 HAL_I2C_Mem_Write_IT: + 5254 .LVL323: + 5255 .LFB148: +2639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 5256 .loc 1 2639 1 is_stmt 1 view -0 + 5257 .cfi_startproc + 5258 @ args = 8, pretend = 0, frame = 0 + 5259 @ frame_needed = 0, uses_anonymous_args = 0 +2639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 5260 .loc 1 2639 1 is_stmt 0 view .LVU1817 + 5261 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 5262 .cfi_def_cfa_offset 24 + 5263 .cfi_offset 4, -24 + 5264 .cfi_offset 5, -20 + 5265 .cfi_offset 6, -16 + 5266 .cfi_offset 7, -12 + 5267 .cfi_offset 8, -8 + 5268 .cfi_offset 14, -4 + 5269 0004 82B0 sub sp, sp, #8 + 5270 .cfi_def_cfa_offset 32 + 5271 0006 0446 mov r4, r0 + 5272 0008 BDF82480 ldrh r8, [sp, #36] +2640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 5273 .loc 1 2640 3 is_stmt 1 view .LVU1818 +2641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5274 .loc 1 2641 3 view .LVU1819 +2644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5275 .loc 1 2644 3 view .LVU1820 +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5276 .loc 1 2646 3 view .LVU1821 +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5277 .loc 1 2646 11 is_stmt 0 view .LVU1822 + 5278 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 5279 .LVL324: +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5280 .loc 1 2646 11 view .LVU1823 + ARM GAS /tmp/ccE2rRGE.s page 242 + + + 5281 0010 C0B2 uxtb r0, r0 +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5282 .loc 1 2646 6 view .LVU1824 + 5283 0012 2028 cmp r0, #32 + 5284 0014 58D1 bne .L351 + 5285 0016 0D46 mov r5, r1 + 5286 0018 1746 mov r7, r2 + 5287 001a 1E46 mov r6, r3 +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5288 .loc 1 2648 5 is_stmt 1 view .LVU1825 +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5289 .loc 1 2648 8 is_stmt 0 view .LVU1826 + 5290 001c 089B ldr r3, [sp, #32] + 5291 .LVL325: +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5292 .loc 1 2648 8 view .LVU1827 + 5293 001e 002B cmp r3, #0 + 5294 0020 38D0 beq .L346 +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5295 .loc 1 2648 25 discriminator 1 view .LVU1828 + 5296 0022 B8F1000F cmp r8, #0 + 5297 0026 35D0 beq .L346 +2654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5298 .loc 1 2654 5 is_stmt 1 view .LVU1829 +2654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5299 .loc 1 2654 9 is_stmt 0 view .LVU1830 + 5300 0028 2368 ldr r3, [r4] + 5301 002a 9B69 ldr r3, [r3, #24] +2654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5302 .loc 1 2654 8 view .LVU1831 + 5303 002c 13F4004F tst r3, #32768 + 5304 0030 4FD1 bne .L352 +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5305 .loc 1 2660 5 is_stmt 1 view .LVU1832 +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5306 .loc 1 2660 5 view .LVU1833 + 5307 0032 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 5308 0036 012B cmp r3, #1 + 5309 0038 4DD0 beq .L353 +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5310 .loc 1 2660 5 discriminator 2 view .LVU1834 + 5311 003a 0123 movs r3, #1 + 5312 003c 84F84030 strb r3, [r4, #64] +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5313 .loc 1 2660 5 discriminator 2 view .LVU1835 +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5314 .loc 1 2663 5 discriminator 2 view .LVU1836 +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5315 .loc 1 2663 17 is_stmt 0 discriminator 2 view .LVU1837 + 5316 0040 FFF7FEFF bl HAL_GetTick + 5317 .LVL326: +2665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5318 .loc 1 2665 5 is_stmt 1 discriminator 2 view .LVU1838 +2665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5319 .loc 1 2665 23 is_stmt 0 discriminator 2 view .LVU1839 + 5320 0044 2123 movs r3, #33 + 5321 0046 84F84130 strb r3, [r4, #65] + ARM GAS /tmp/ccE2rRGE.s page 243 + + +2666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5322 .loc 1 2666 5 is_stmt 1 discriminator 2 view .LVU1840 +2666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5323 .loc 1 2666 23 is_stmt 0 discriminator 2 view .LVU1841 + 5324 004a 4023 movs r3, #64 + 5325 004c 84F84230 strb r3, [r4, #66] +2667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5326 .loc 1 2667 5 is_stmt 1 discriminator 2 view .LVU1842 +2667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5327 .loc 1 2667 23 is_stmt 0 discriminator 2 view .LVU1843 + 5328 0050 0023 movs r3, #0 + 5329 0052 6364 str r3, [r4, #68] +2670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 5330 .loc 1 2670 5 is_stmt 1 discriminator 2 view .LVU1844 +2670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 5331 .loc 1 2670 23 is_stmt 0 discriminator 2 view .LVU1845 + 5332 0054 089B ldr r3, [sp, #32] + 5333 0056 6362 str r3, [r4, #36] +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5334 .loc 1 2671 5 is_stmt 1 discriminator 2 view .LVU1846 +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5335 .loc 1 2671 23 is_stmt 0 discriminator 2 view .LVU1847 + 5336 0058 A4F82A80 strh r8, [r4, #42] @ movhi +2672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5337 .loc 1 2672 5 is_stmt 1 discriminator 2 view .LVU1848 +2672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5338 .loc 1 2672 23 is_stmt 0 discriminator 2 view .LVU1849 + 5339 005c 1F4B ldr r3, .L355 + 5340 005e E362 str r3, [r4, #44] +2673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5341 .loc 1 2673 5 is_stmt 1 discriminator 2 view .LVU1850 +2673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5342 .loc 1 2673 23 is_stmt 0 discriminator 2 view .LVU1851 + 5343 0060 1F4B ldr r3, .L355+4 + 5344 0062 6363 str r3, [r4, #52] +2675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5345 .loc 1 2675 5 is_stmt 1 discriminator 2 view .LVU1852 +2675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5346 .loc 1 2675 13 is_stmt 0 discriminator 2 view .LVU1853 + 5347 0064 638D ldrh r3, [r4, #42] + 5348 0066 9BB2 uxth r3, r3 +2675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5349 .loc 1 2675 8 discriminator 2 view .LVU1854 + 5350 0068 FF2B cmp r3, #255 + 5351 006a 18D9 bls .L348 +2677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5352 .loc 1 2677 7 is_stmt 1 view .LVU1855 +2677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5353 .loc 1 2677 22 is_stmt 0 view .LVU1856 + 5354 006c FF23 movs r3, #255 + 5355 006e 2385 strh r3, [r4, #40] @ movhi +2678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5356 .loc 1 2678 7 is_stmt 1 view .LVU1857 + 5357 .LVL327: +2678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5358 .loc 1 2678 16 is_stmt 0 view .LVU1858 + 5359 0070 4FF08078 mov r8, #16777216 + ARM GAS /tmp/ccE2rRGE.s page 244 + + + 5360 .LVL328: + 5361 .L349: +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) + 5362 .loc 1 2687 5 is_stmt 1 view .LVU1859 +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) + 5363 .loc 1 2687 9 is_stmt 0 view .LVU1860 + 5364 0074 0190 str r0, [sp, #4] + 5365 0076 1923 movs r3, #25 + 5366 0078 0093 str r3, [sp] + 5367 007a 3346 mov r3, r6 + 5368 007c 3A46 mov r2, r7 + 5369 007e 2946 mov r1, r5 + 5370 0080 2046 mov r0, r4 + 5371 .LVL329: +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) + 5372 .loc 1 2687 9 view .LVU1861 + 5373 0082 FFF7FEFF bl I2C_RequestMemoryWrite + 5374 .LVL330: +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) + 5375 .loc 1 2687 8 view .LVU1862 + 5376 0086 0646 mov r6, r0 + 5377 0088 70B1 cbz r0, .L350 +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5378 .loc 1 2691 7 is_stmt 1 view .LVU1863 +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5379 .loc 1 2691 7 view .LVU1864 + 5380 008a 0023 movs r3, #0 + 5381 008c 84F84030 strb r3, [r4, #64] +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5382 .loc 1 2691 7 view .LVU1865 +2692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5383 .loc 1 2692 7 view .LVU1866 +2692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5384 .loc 1 2692 14 is_stmt 0 view .LVU1867 + 5385 0090 0126 movs r6, #1 + 5386 0092 1AE0 b .L345 + 5387 .LVL331: + 5388 .L346: +2650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5389 .loc 1 2650 7 is_stmt 1 view .LVU1868 +2650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5390 .loc 1 2650 23 is_stmt 0 view .LVU1869 + 5391 0094 4FF40073 mov r3, #512 + 5392 0098 6364 str r3, [r4, #68] +2651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5393 .loc 1 2651 7 is_stmt 1 view .LVU1870 +2651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5394 .loc 1 2651 15 is_stmt 0 view .LVU1871 + 5395 009a 0126 movs r6, #1 + 5396 009c 15E0 b .L345 + 5397 .LVL332: + 5398 .L348: +2682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5399 .loc 1 2682 7 is_stmt 1 view .LVU1872 +2682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5400 .loc 1 2682 28 is_stmt 0 view .LVU1873 + 5401 009e 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccE2rRGE.s page 245 + + +2682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5402 .loc 1 2682 22 view .LVU1874 + 5403 00a0 2385 strh r3, [r4, #40] @ movhi +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5404 .loc 1 2683 7 is_stmt 1 view .LVU1875 + 5405 .LVL333: +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5406 .loc 1 2683 16 is_stmt 0 view .LVU1876 + 5407 00a2 4FF00078 mov r8, #33554432 + 5408 00a6 E5E7 b .L349 + 5409 .LVL334: + 5410 .L350: +2696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5411 .loc 1 2696 5 is_stmt 1 view .LVU1877 + 5412 00a8 0027 movs r7, #0 + 5413 00aa 0097 str r7, [sp] + 5414 00ac 4346 mov r3, r8 + 5415 00ae 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 5416 00b2 2946 mov r1, r5 + 5417 00b4 2046 mov r0, r4 + 5418 00b6 FFF7FEFF bl I2C_TransferConfig + 5419 .LVL335: +2699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5420 .loc 1 2699 5 view .LVU1878 +2699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5421 .loc 1 2699 5 view .LVU1879 + 5422 00ba 84F84070 strb r7, [r4, #64] +2699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5423 .loc 1 2699 5 view .LVU1880 +2709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5424 .loc 1 2709 5 view .LVU1881 + 5425 00be 0121 movs r1, #1 + 5426 00c0 2046 mov r0, r4 + 5427 00c2 FFF7FEFF bl I2C_Enable_IRQ + 5428 .LVL336: +2711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5429 .loc 1 2711 5 view .LVU1882 +2711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5430 .loc 1 2711 12 is_stmt 0 view .LVU1883 + 5431 00c6 00E0 b .L345 + 5432 .LVL337: + 5433 .L351: +2715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5434 .loc 1 2715 12 view .LVU1884 + 5435 00c8 0226 movs r6, #2 + 5436 .LVL338: + 5437 .L345: +2717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5438 .loc 1 2717 1 view .LVU1885 + 5439 00ca 3046 mov r0, r6 + 5440 00cc 02B0 add sp, sp, #8 + 5441 .cfi_remember_state + 5442 .cfi_def_cfa_offset 24 + 5443 @ sp needed + 5444 00ce BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 5445 .LVL339: + 5446 .L352: + ARM GAS /tmp/ccE2rRGE.s page 246 + + + 5447 .cfi_restore_state +2656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5448 .loc 1 2656 14 view .LVU1886 + 5449 00d2 0226 movs r6, #2 + 5450 00d4 F9E7 b .L345 + 5451 .L353: +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5452 .loc 1 2660 5 view .LVU1887 + 5453 00d6 0226 movs r6, #2 + 5454 00d8 F7E7 b .L345 + 5455 .L356: + 5456 00da 00BF .align 2 + 5457 .L355: + 5458 00dc 0000FFFF .word -65536 + 5459 00e0 00000000 .word I2C_Master_ISR_IT + 5460 .cfi_endproc + 5461 .LFE148: + 5463 .section .text.HAL_I2C_Mem_Read_IT,"ax",%progbits + 5464 .align 1 + 5465 .global HAL_I2C_Mem_Read_IT + 5466 .syntax unified + 5467 .thumb + 5468 .thumb_func + 5470 HAL_I2C_Mem_Read_IT: + 5471 .LVL340: + 5472 .LFB149: +2733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 5473 .loc 1 2733 1 is_stmt 1 view -0 + 5474 .cfi_startproc + 5475 @ args = 8, pretend = 0, frame = 0 + 5476 @ frame_needed = 0, uses_anonymous_args = 0 +2733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 5477 .loc 1 2733 1 is_stmt 0 view .LVU1889 + 5478 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 5479 .cfi_def_cfa_offset 24 + 5480 .cfi_offset 4, -24 + 5481 .cfi_offset 5, -20 + 5482 .cfi_offset 6, -16 + 5483 .cfi_offset 7, -12 + 5484 .cfi_offset 8, -8 + 5485 .cfi_offset 14, -4 + 5486 0004 82B0 sub sp, sp, #8 + 5487 .cfi_def_cfa_offset 32 + 5488 0006 0446 mov r4, r0 + 5489 0008 BDF82480 ldrh r8, [sp, #36] +2734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 5490 .loc 1 2734 3 is_stmt 1 view .LVU1890 +2735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5491 .loc 1 2735 3 view .LVU1891 +2738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5492 .loc 1 2738 3 view .LVU1892 +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5493 .loc 1 2740 3 view .LVU1893 +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5494 .loc 1 2740 11 is_stmt 0 view .LVU1894 + 5495 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 5496 .LVL341: + ARM GAS /tmp/ccE2rRGE.s page 247 + + +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5497 .loc 1 2740 11 view .LVU1895 + 5498 0010 C0B2 uxtb r0, r0 +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5499 .loc 1 2740 6 view .LVU1896 + 5500 0012 2028 cmp r0, #32 + 5501 0014 59D1 bne .L364 + 5502 0016 0D46 mov r5, r1 + 5503 0018 1746 mov r7, r2 + 5504 001a 1E46 mov r6, r3 +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5505 .loc 1 2742 5 is_stmt 1 view .LVU1897 +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5506 .loc 1 2742 8 is_stmt 0 view .LVU1898 + 5507 001c 089B ldr r3, [sp, #32] + 5508 .LVL342: +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5509 .loc 1 2742 8 view .LVU1899 + 5510 001e 002B cmp r3, #0 + 5511 0020 38D0 beq .L359 +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5512 .loc 1 2742 25 discriminator 1 view .LVU1900 + 5513 0022 B8F1000F cmp r8, #0 + 5514 0026 35D0 beq .L359 +2748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5515 .loc 1 2748 5 is_stmt 1 view .LVU1901 +2748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5516 .loc 1 2748 9 is_stmt 0 view .LVU1902 + 5517 0028 2368 ldr r3, [r4] + 5518 002a 9B69 ldr r3, [r3, #24] +2748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5519 .loc 1 2748 8 view .LVU1903 + 5520 002c 13F4004F tst r3, #32768 + 5521 0030 50D1 bne .L365 +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5522 .loc 1 2754 5 is_stmt 1 view .LVU1904 +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5523 .loc 1 2754 5 view .LVU1905 + 5524 0032 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 5525 0036 012B cmp r3, #1 + 5526 0038 4ED0 beq .L366 +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5527 .loc 1 2754 5 discriminator 2 view .LVU1906 + 5528 003a 0123 movs r3, #1 + 5529 003c 84F84030 strb r3, [r4, #64] +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5530 .loc 1 2754 5 discriminator 2 view .LVU1907 +2757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5531 .loc 1 2757 5 discriminator 2 view .LVU1908 +2757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5532 .loc 1 2757 17 is_stmt 0 discriminator 2 view .LVU1909 + 5533 0040 FFF7FEFF bl HAL_GetTick + 5534 .LVL343: +2759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5535 .loc 1 2759 5 is_stmt 1 discriminator 2 view .LVU1910 +2759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5536 .loc 1 2759 23 is_stmt 0 discriminator 2 view .LVU1911 + ARM GAS /tmp/ccE2rRGE.s page 248 + + + 5537 0044 2223 movs r3, #34 + 5538 0046 84F84130 strb r3, [r4, #65] +2760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5539 .loc 1 2760 5 is_stmt 1 discriminator 2 view .LVU1912 +2760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5540 .loc 1 2760 23 is_stmt 0 discriminator 2 view .LVU1913 + 5541 004a 4023 movs r3, #64 + 5542 004c 84F84230 strb r3, [r4, #66] +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5543 .loc 1 2761 5 is_stmt 1 discriminator 2 view .LVU1914 +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5544 .loc 1 2761 23 is_stmt 0 discriminator 2 view .LVU1915 + 5545 0050 0023 movs r3, #0 + 5546 0052 6364 str r3, [r4, #68] +2764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 5547 .loc 1 2764 5 is_stmt 1 discriminator 2 view .LVU1916 +2764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 5548 .loc 1 2764 23 is_stmt 0 discriminator 2 view .LVU1917 + 5549 0054 089B ldr r3, [sp, #32] + 5550 0056 6362 str r3, [r4, #36] +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5551 .loc 1 2765 5 is_stmt 1 discriminator 2 view .LVU1918 +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5552 .loc 1 2765 23 is_stmt 0 discriminator 2 view .LVU1919 + 5553 0058 A4F82A80 strh r8, [r4, #42] @ movhi +2766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5554 .loc 1 2766 5 is_stmt 1 discriminator 2 view .LVU1920 +2766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5555 .loc 1 2766 23 is_stmt 0 discriminator 2 view .LVU1921 + 5556 005c 1F4B ldr r3, .L368 + 5557 005e E362 str r3, [r4, #44] +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5558 .loc 1 2767 5 is_stmt 1 discriminator 2 view .LVU1922 +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5559 .loc 1 2767 23 is_stmt 0 discriminator 2 view .LVU1923 + 5560 0060 1F4B ldr r3, .L368+4 + 5561 0062 6363 str r3, [r4, #52] +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5562 .loc 1 2769 5 is_stmt 1 discriminator 2 view .LVU1924 +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5563 .loc 1 2769 13 is_stmt 0 discriminator 2 view .LVU1925 + 5564 0064 638D ldrh r3, [r4, #42] + 5565 0066 9BB2 uxth r3, r3 +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5566 .loc 1 2769 8 discriminator 2 view .LVU1926 + 5567 0068 FF2B cmp r3, #255 + 5568 006a 18D9 bls .L361 +2771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5569 .loc 1 2771 7 is_stmt 1 view .LVU1927 +2771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5570 .loc 1 2771 22 is_stmt 0 view .LVU1928 + 5571 006c FF23 movs r3, #255 + 5572 006e 2385 strh r3, [r4, #40] @ movhi +2772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5573 .loc 1 2772 7 is_stmt 1 view .LVU1929 + 5574 .LVL344: +2772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 249 + + + 5575 .loc 1 2772 16 is_stmt 0 view .LVU1930 + 5576 0070 4FF08078 mov r8, #16777216 + 5577 .LVL345: + 5578 .L362: +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5579 .loc 1 2781 5 is_stmt 1 view .LVU1931 +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5580 .loc 1 2781 9 is_stmt 0 view .LVU1932 + 5581 0074 0190 str r0, [sp, #4] + 5582 0076 1923 movs r3, #25 + 5583 0078 0093 str r3, [sp] + 5584 007a 3346 mov r3, r6 + 5585 007c 3A46 mov r2, r7 + 5586 007e 2946 mov r1, r5 + 5587 0080 2046 mov r0, r4 + 5588 .LVL346: +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5589 .loc 1 2781 9 view .LVU1933 + 5590 0082 FFF7FEFF bl I2C_RequestMemoryRead + 5591 .LVL347: +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5592 .loc 1 2781 8 view .LVU1934 + 5593 0086 0646 mov r6, r0 + 5594 0088 70B1 cbz r0, .L363 +2784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5595 .loc 1 2784 7 is_stmt 1 view .LVU1935 +2784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5596 .loc 1 2784 7 view .LVU1936 + 5597 008a 0023 movs r3, #0 + 5598 008c 84F84030 strb r3, [r4, #64] +2784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5599 .loc 1 2784 7 view .LVU1937 +2785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5600 .loc 1 2785 7 view .LVU1938 +2785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5601 .loc 1 2785 14 is_stmt 0 view .LVU1939 + 5602 0090 0126 movs r6, #1 + 5603 0092 1BE0 b .L358 + 5604 .LVL348: + 5605 .L359: +2744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5606 .loc 1 2744 7 is_stmt 1 view .LVU1940 +2744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5607 .loc 1 2744 23 is_stmt 0 view .LVU1941 + 5608 0094 4FF40073 mov r3, #512 + 5609 0098 6364 str r3, [r4, #68] +2745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5610 .loc 1 2745 7 is_stmt 1 view .LVU1942 +2745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5611 .loc 1 2745 15 is_stmt 0 view .LVU1943 + 5612 009a 0126 movs r6, #1 + 5613 009c 16E0 b .L358 + 5614 .LVL349: + 5615 .L361: +2776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5616 .loc 1 2776 7 is_stmt 1 view .LVU1944 +2776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + ARM GAS /tmp/ccE2rRGE.s page 250 + + + 5617 .loc 1 2776 28 is_stmt 0 view .LVU1945 + 5618 009e 638D ldrh r3, [r4, #42] +2776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5619 .loc 1 2776 22 view .LVU1946 + 5620 00a0 2385 strh r3, [r4, #40] @ movhi +2777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5621 .loc 1 2777 7 is_stmt 1 view .LVU1947 + 5622 .LVL350: +2777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5623 .loc 1 2777 16 is_stmt 0 view .LVU1948 + 5624 00a2 4FF00078 mov r8, #33554432 + 5625 00a6 E5E7 b .L362 + 5626 .LVL351: + 5627 .L363: +2789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5628 .loc 1 2789 5 is_stmt 1 view .LVU1949 + 5629 00a8 0E4B ldr r3, .L368+8 + 5630 00aa 0093 str r3, [sp] + 5631 00ac 4346 mov r3, r8 + 5632 00ae 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 5633 00b2 2946 mov r1, r5 + 5634 00b4 2046 mov r0, r4 + 5635 00b6 FFF7FEFF bl I2C_TransferConfig + 5636 .LVL352: +2792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5637 .loc 1 2792 5 view .LVU1950 +2792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5638 .loc 1 2792 5 view .LVU1951 + 5639 00ba 0023 movs r3, #0 + 5640 00bc 84F84030 strb r3, [r4, #64] +2792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5641 .loc 1 2792 5 view .LVU1952 +2802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5642 .loc 1 2802 5 view .LVU1953 + 5643 00c0 0221 movs r1, #2 + 5644 00c2 2046 mov r0, r4 + 5645 00c4 FFF7FEFF bl I2C_Enable_IRQ + 5646 .LVL353: +2804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5647 .loc 1 2804 5 view .LVU1954 +2804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5648 .loc 1 2804 12 is_stmt 0 view .LVU1955 + 5649 00c8 00E0 b .L358 + 5650 .LVL354: + 5651 .L364: +2808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5652 .loc 1 2808 12 view .LVU1956 + 5653 00ca 0226 movs r6, #2 + 5654 .LVL355: + 5655 .L358: +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 5656 .loc 1 2810 1 view .LVU1957 + 5657 00cc 3046 mov r0, r6 + 5658 00ce 02B0 add sp, sp, #8 + 5659 .cfi_remember_state + 5660 .cfi_def_cfa_offset 24 + 5661 @ sp needed + ARM GAS /tmp/ccE2rRGE.s page 251 + + + 5662 00d0 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 5663 .LVL356: + 5664 .L365: + 5665 .cfi_restore_state +2750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5666 .loc 1 2750 14 view .LVU1958 + 5667 00d4 0226 movs r6, #2 + 5668 00d6 F9E7 b .L358 + 5669 .L366: +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5670 .loc 1 2754 5 view .LVU1959 + 5671 00d8 0226 movs r6, #2 + 5672 00da F7E7 b .L358 + 5673 .L369: + 5674 .align 2 + 5675 .L368: + 5676 00dc 0000FFFF .word -65536 + 5677 00e0 00000000 .word I2C_Master_ISR_IT + 5678 00e4 00240080 .word -2147474432 + 5679 .cfi_endproc + 5680 .LFE149: + 5682 .section .text.HAL_I2C_Mem_Write_DMA,"ax",%progbits + 5683 .align 1 + 5684 .global HAL_I2C_Mem_Write_DMA + 5685 .syntax unified + 5686 .thumb + 5687 .thumb_func + 5689 HAL_I2C_Mem_Write_DMA: + 5690 .LVL357: + 5691 .LFB150: +2825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 5692 .loc 1 2825 1 is_stmt 1 view -0 + 5693 .cfi_startproc + 5694 @ args = 8, pretend = 0, frame = 0 + 5695 @ frame_needed = 0, uses_anonymous_args = 0 +2825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 5696 .loc 1 2825 1 is_stmt 0 view .LVU1961 + 5697 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 5698 .cfi_def_cfa_offset 24 + 5699 .cfi_offset 4, -24 + 5700 .cfi_offset 5, -20 + 5701 .cfi_offset 6, -16 + 5702 .cfi_offset 7, -12 + 5703 .cfi_offset 8, -8 + 5704 .cfi_offset 14, -4 + 5705 0004 82B0 sub sp, sp, #8 + 5706 .cfi_def_cfa_offset 32 + 5707 0006 0446 mov r4, r0 + 5708 0008 BDF82480 ldrh r8, [sp, #36] +2826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 5709 .loc 1 2826 3 is_stmt 1 view .LVU1962 +2827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 5710 .loc 1 2827 3 view .LVU1963 +2828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5711 .loc 1 2828 3 view .LVU1964 +2831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5712 .loc 1 2831 3 view .LVU1965 + ARM GAS /tmp/ccE2rRGE.s page 252 + + +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5713 .loc 1 2833 3 view .LVU1966 +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5714 .loc 1 2833 11 is_stmt 0 view .LVU1967 + 5715 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 5716 .LVL358: +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5717 .loc 1 2833 11 view .LVU1968 + 5718 0010 C0B2 uxtb r0, r0 +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5719 .loc 1 2833 6 view .LVU1969 + 5720 0012 2028 cmp r0, #32 + 5721 0014 40F09880 bne .L380 + 5722 0018 0D46 mov r5, r1 + 5723 001a 1746 mov r7, r2 + 5724 001c 1E46 mov r6, r3 +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5725 .loc 1 2835 5 is_stmt 1 view .LVU1970 +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5726 .loc 1 2835 8 is_stmt 0 view .LVU1971 + 5727 001e 089B ldr r3, [sp, #32] + 5728 .LVL359: +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5729 .loc 1 2835 8 view .LVU1972 + 5730 0020 002B cmp r3, #0 + 5731 0022 59D0 beq .L372 +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5732 .loc 1 2835 25 discriminator 1 view .LVU1973 + 5733 0024 B8F1000F cmp r8, #0 + 5734 0028 56D0 beq .L372 +2841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5735 .loc 1 2841 5 is_stmt 1 view .LVU1974 +2841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5736 .loc 1 2841 9 is_stmt 0 view .LVU1975 + 5737 002a 2368 ldr r3, [r4] + 5738 002c 9B69 ldr r3, [r3, #24] +2841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5739 .loc 1 2841 8 view .LVU1976 + 5740 002e 13F4004F tst r3, #32768 + 5741 0032 40F08E80 bne .L381 +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5742 .loc 1 2847 5 is_stmt 1 view .LVU1977 +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5743 .loc 1 2847 5 view .LVU1978 + 5744 0036 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 5745 003a 012B cmp r3, #1 + 5746 003c 00F08B80 beq .L382 +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5747 .loc 1 2847 5 discriminator 2 view .LVU1979 + 5748 0040 0123 movs r3, #1 + 5749 0042 84F84030 strb r3, [r4, #64] +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5750 .loc 1 2847 5 discriminator 2 view .LVU1980 +2850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5751 .loc 1 2850 5 discriminator 2 view .LVU1981 +2850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5752 .loc 1 2850 17 is_stmt 0 discriminator 2 view .LVU1982 + ARM GAS /tmp/ccE2rRGE.s page 253 + + + 5753 0046 FFF7FEFF bl HAL_GetTick + 5754 .LVL360: +2852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5755 .loc 1 2852 5 is_stmt 1 discriminator 2 view .LVU1983 +2852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5756 .loc 1 2852 23 is_stmt 0 discriminator 2 view .LVU1984 + 5757 004a 2123 movs r3, #33 + 5758 004c 84F84130 strb r3, [r4, #65] +2853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5759 .loc 1 2853 5 is_stmt 1 discriminator 2 view .LVU1985 +2853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5760 .loc 1 2853 23 is_stmt 0 discriminator 2 view .LVU1986 + 5761 0050 4023 movs r3, #64 + 5762 0052 84F84230 strb r3, [r4, #66] +2854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5763 .loc 1 2854 5 is_stmt 1 discriminator 2 view .LVU1987 +2854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5764 .loc 1 2854 23 is_stmt 0 discriminator 2 view .LVU1988 + 5765 0056 0023 movs r3, #0 + 5766 0058 6364 str r3, [r4, #68] +2857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 5767 .loc 1 2857 5 is_stmt 1 discriminator 2 view .LVU1989 +2857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 5768 .loc 1 2857 23 is_stmt 0 discriminator 2 view .LVU1990 + 5769 005a 089B ldr r3, [sp, #32] + 5770 005c 6362 str r3, [r4, #36] +2858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5771 .loc 1 2858 5 is_stmt 1 discriminator 2 view .LVU1991 +2858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5772 .loc 1 2858 23 is_stmt 0 discriminator 2 view .LVU1992 + 5773 005e A4F82A80 strh r8, [r4, #42] @ movhi +2859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 5774 .loc 1 2859 5 is_stmt 1 discriminator 2 view .LVU1993 +2859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 5775 .loc 1 2859 23 is_stmt 0 discriminator 2 view .LVU1994 + 5776 0062 3E4B ldr r3, .L387 + 5777 0064 E362 str r3, [r4, #44] +2860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5778 .loc 1 2860 5 is_stmt 1 discriminator 2 view .LVU1995 +2860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5779 .loc 1 2860 23 is_stmt 0 discriminator 2 view .LVU1996 + 5780 0066 3E4B ldr r3, .L387+4 + 5781 0068 6363 str r3, [r4, #52] +2862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5782 .loc 1 2862 5 is_stmt 1 discriminator 2 view .LVU1997 +2862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5783 .loc 1 2862 13 is_stmt 0 discriminator 2 view .LVU1998 + 5784 006a 638D ldrh r3, [r4, #42] + 5785 006c 9BB2 uxth r3, r3 +2862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5786 .loc 1 2862 8 discriminator 2 view .LVU1999 + 5787 006e FF2B cmp r3, #255 + 5788 0070 37D9 bls .L374 +2864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5789 .loc 1 2864 7 is_stmt 1 view .LVU2000 +2864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5790 .loc 1 2864 22 is_stmt 0 view .LVU2001 + ARM GAS /tmp/ccE2rRGE.s page 254 + + + 5791 0072 FF23 movs r3, #255 + 5792 0074 2385 strh r3, [r4, #40] @ movhi +2865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5793 .loc 1 2865 7 is_stmt 1 view .LVU2002 + 5794 .LVL361: +2865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5795 .loc 1 2865 16 is_stmt 0 view .LVU2003 + 5796 0076 4FF08078 mov r8, #16777216 + 5797 .LVL362: + 5798 .L375: +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) + 5799 .loc 1 2874 5 is_stmt 1 view .LVU2004 +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) + 5800 .loc 1 2874 9 is_stmt 0 view .LVU2005 + 5801 007a 0190 str r0, [sp, #4] + 5802 007c 1923 movs r3, #25 + 5803 007e 0093 str r3, [sp] + 5804 0080 3346 mov r3, r6 + 5805 0082 3A46 mov r2, r7 + 5806 0084 2946 mov r1, r5 + 5807 0086 2046 mov r0, r4 + 5808 .LVL363: +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) + 5809 .loc 1 2874 9 view .LVU2006 + 5810 0088 FFF7FEFF bl I2C_RequestMemoryWrite + 5811 .LVL364: +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** != HAL_OK) + 5812 .loc 1 2874 8 view .LVU2007 + 5813 008c 0028 cmp r0, #0 + 5814 008e 2DD1 bne .L385 +2883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5815 .loc 1 2883 5 is_stmt 1 view .LVU2008 +2883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5816 .loc 1 2883 13 is_stmt 0 view .LVU2009 + 5817 0090 A36B ldr r3, [r4, #56] +2883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5818 .loc 1 2883 8 view .LVU2010 + 5819 0092 002B cmp r3, #0 + 5820 0094 2FD0 beq .L377 +2886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5821 .loc 1 2886 7 is_stmt 1 view .LVU2011 +2886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5822 .loc 1 2886 38 is_stmt 0 view .LVU2012 + 5823 0096 334A ldr r2, .L387+8 + 5824 0098 9A62 str r2, [r3, #40] +2889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5825 .loc 1 2889 7 is_stmt 1 view .LVU2013 +2889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5826 .loc 1 2889 11 is_stmt 0 view .LVU2014 + 5827 009a A36B ldr r3, [r4, #56] +2889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5828 .loc 1 2889 39 view .LVU2015 + 5829 009c 324A ldr r2, .L387+12 + 5830 009e 1A63 str r2, [r3, #48] +2892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 5831 .loc 1 2892 7 is_stmt 1 view .LVU2016 +2892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + ARM GAS /tmp/ccE2rRGE.s page 255 + + + 5832 .loc 1 2892 11 is_stmt 0 view .LVU2017 + 5833 00a0 A26B ldr r2, [r4, #56] +2892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 5834 .loc 1 2892 42 view .LVU2018 + 5835 00a2 0023 movs r3, #0 + 5836 00a4 D362 str r3, [r2, #44] +2893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5837 .loc 1 2893 7 is_stmt 1 view .LVU2019 +2893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5838 .loc 1 2893 11 is_stmt 0 view .LVU2020 + 5839 00a6 A26B ldr r2, [r4, #56] +2893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5840 .loc 1 2893 39 view .LVU2021 + 5841 00a8 5363 str r3, [r2, #52] +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 5842 .loc 1 2896 7 is_stmt 1 view .LVU2022 +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 5843 .loc 1 2896 86 is_stmt 0 view .LVU2023 + 5844 00aa 2268 ldr r2, [r4] +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 5845 .loc 1 2896 23 view .LVU2024 + 5846 00ac 238D ldrh r3, [r4, #40] + 5847 00ae 2832 adds r2, r2, #40 + 5848 00b0 0899 ldr r1, [sp, #32] + 5849 00b2 A06B ldr r0, [r4, #56] + 5850 00b4 FFF7FEFF bl HAL_DMA_Start_IT + 5851 .LVL365: +2914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5852 .loc 1 2914 5 is_stmt 1 view .LVU2025 +2914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5853 .loc 1 2914 8 is_stmt 0 view .LVU2026 + 5854 00b8 0646 mov r6, r0 + 5855 00ba 50B3 cbz r0, .L386 +2938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5856 .loc 1 2938 7 is_stmt 1 view .LVU2027 +2938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5857 .loc 1 2938 23 is_stmt 0 view .LVU2028 + 5858 00bc 2023 movs r3, #32 + 5859 00be 84F84130 strb r3, [r4, #65] +2939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5860 .loc 1 2939 7 is_stmt 1 view .LVU2029 +2939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5861 .loc 1 2939 23 is_stmt 0 view .LVU2030 + 5862 00c2 0022 movs r2, #0 + 5863 00c4 84F84220 strb r2, [r4, #66] +2942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5864 .loc 1 2942 7 is_stmt 1 view .LVU2031 +2942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5865 .loc 1 2942 11 is_stmt 0 view .LVU2032 + 5866 00c8 636C ldr r3, [r4, #68] +2942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5867 .loc 1 2942 23 view .LVU2033 + 5868 00ca 43F01003 orr r3, r3, #16 + 5869 00ce 6364 str r3, [r4, #68] +2945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5870 .loc 1 2945 7 is_stmt 1 view .LVU2034 +2945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 256 + + + 5871 .loc 1 2945 7 view .LVU2035 + 5872 00d0 84F84020 strb r2, [r4, #64] +2945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5873 .loc 1 2945 7 view .LVU2036 +2947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5874 .loc 1 2947 7 view .LVU2037 +2947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5875 .loc 1 2947 14 is_stmt 0 view .LVU2038 + 5876 00d4 0126 movs r6, #1 + 5877 00d6 38E0 b .L371 + 5878 .LVL366: + 5879 .L372: +2837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5880 .loc 1 2837 7 is_stmt 1 view .LVU2039 +2837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5881 .loc 1 2837 23 is_stmt 0 view .LVU2040 + 5882 00d8 4FF40073 mov r3, #512 + 5883 00dc 6364 str r3, [r4, #68] +2838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5884 .loc 1 2838 7 is_stmt 1 view .LVU2041 +2838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5885 .loc 1 2838 15 is_stmt 0 view .LVU2042 + 5886 00de 0126 movs r6, #1 + 5887 00e0 33E0 b .L371 + 5888 .LVL367: + 5889 .L374: +2869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5890 .loc 1 2869 7 is_stmt 1 view .LVU2043 +2869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5891 .loc 1 2869 28 is_stmt 0 view .LVU2044 + 5892 00e2 638D ldrh r3, [r4, #42] +2869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5893 .loc 1 2869 22 view .LVU2045 + 5894 00e4 2385 strh r3, [r4, #40] @ movhi +2870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5895 .loc 1 2870 7 is_stmt 1 view .LVU2046 + 5896 .LVL368: +2870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5897 .loc 1 2870 16 is_stmt 0 view .LVU2047 + 5898 00e6 4FF00078 mov r8, #33554432 + 5899 00ea C6E7 b .L375 + 5900 .LVL369: + 5901 .L385: +2878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5902 .loc 1 2878 7 is_stmt 1 view .LVU2048 +2878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5903 .loc 1 2878 7 view .LVU2049 + 5904 00ec 0023 movs r3, #0 + 5905 00ee 84F84030 strb r3, [r4, #64] +2878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5906 .loc 1 2878 7 view .LVU2050 +2879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5907 .loc 1 2879 7 view .LVU2051 +2879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5908 .loc 1 2879 14 is_stmt 0 view .LVU2052 + 5909 00f2 0126 movs r6, #1 + 5910 00f4 29E0 b .L371 + ARM GAS /tmp/ccE2rRGE.s page 257 + + + 5911 .L377: +2902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5912 .loc 1 2902 7 is_stmt 1 view .LVU2053 +2902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5913 .loc 1 2902 23 is_stmt 0 view .LVU2054 + 5914 00f6 2023 movs r3, #32 + 5915 00f8 84F84130 strb r3, [r4, #65] +2903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5916 .loc 1 2903 7 is_stmt 1 view .LVU2055 +2903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5917 .loc 1 2903 23 is_stmt 0 view .LVU2056 + 5918 00fc 0022 movs r2, #0 + 5919 00fe 84F84220 strb r2, [r4, #66] +2906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5920 .loc 1 2906 7 is_stmt 1 view .LVU2057 +2906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5921 .loc 1 2906 11 is_stmt 0 view .LVU2058 + 5922 0102 636C ldr r3, [r4, #68] +2906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5923 .loc 1 2906 23 view .LVU2059 + 5924 0104 43F08003 orr r3, r3, #128 + 5925 0108 6364 str r3, [r4, #68] +2909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5926 .loc 1 2909 7 is_stmt 1 view .LVU2060 +2909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5927 .loc 1 2909 7 view .LVU2061 + 5928 010a 84F84020 strb r2, [r4, #64] +2909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5929 .loc 1 2909 7 view .LVU2062 +2911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5930 .loc 1 2911 7 view .LVU2063 +2911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5931 .loc 1 2911 14 is_stmt 0 view .LVU2064 + 5932 010e 0126 movs r6, #1 + 5933 0110 1BE0 b .L371 + 5934 .LVL370: + 5935 .L386: +2918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5936 .loc 1 2918 7 is_stmt 1 view .LVU2065 + 5937 0112 0027 movs r7, #0 + 5938 0114 0097 str r7, [sp] + 5939 0116 4346 mov r3, r8 + 5940 0118 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 5941 011c 2946 mov r1, r5 + 5942 011e 2046 mov r0, r4 + 5943 .LVL371: +2918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5944 .loc 1 2918 7 is_stmt 0 view .LVU2066 + 5945 0120 FFF7FEFF bl I2C_TransferConfig + 5946 .LVL372: +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5947 .loc 1 2921 7 is_stmt 1 view .LVU2067 +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5948 .loc 1 2921 11 is_stmt 0 view .LVU2068 + 5949 0124 638D ldrh r3, [r4, #42] + 5950 0126 9BB2 uxth r3, r3 +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 258 + + + 5951 .loc 1 2921 30 view .LVU2069 + 5952 0128 228D ldrh r2, [r4, #40] +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5953 .loc 1 2921 23 view .LVU2070 + 5954 012a 9B1A subs r3, r3, r2 + 5955 012c 9BB2 uxth r3, r3 + 5956 012e 6385 strh r3, [r4, #42] @ movhi +2924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5957 .loc 1 2924 7 is_stmt 1 view .LVU2071 +2924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5958 .loc 1 2924 7 view .LVU2072 + 5959 0130 84F84070 strb r7, [r4, #64] +2924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5960 .loc 1 2924 7 view .LVU2073 +2930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5961 .loc 1 2930 7 view .LVU2074 + 5962 0134 1021 movs r1, #16 + 5963 0136 2046 mov r0, r4 + 5964 0138 FFF7FEFF bl I2C_Enable_IRQ + 5965 .LVL373: +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5966 .loc 1 2933 7 view .LVU2075 +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5967 .loc 1 2933 11 is_stmt 0 view .LVU2076 + 5968 013c 2268 ldr r2, [r4] +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5969 .loc 1 2933 21 view .LVU2077 + 5970 013e 1368 ldr r3, [r2] +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5971 .loc 1 2933 27 view .LVU2078 + 5972 0140 43F48043 orr r3, r3, #16384 + 5973 0144 1360 str r3, [r2] +2950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5974 .loc 1 2950 5 is_stmt 1 view .LVU2079 +2950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5975 .loc 1 2950 12 is_stmt 0 view .LVU2080 + 5976 0146 00E0 b .L371 + 5977 .LVL374: + 5978 .L380: +2954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5979 .loc 1 2954 12 view .LVU2081 + 5980 0148 0226 movs r6, #2 + 5981 .LVL375: + 5982 .L371: +2956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5983 .loc 1 2956 1 view .LVU2082 + 5984 014a 3046 mov r0, r6 + 5985 014c 02B0 add sp, sp, #8 + 5986 .cfi_remember_state + 5987 .cfi_def_cfa_offset 24 + 5988 @ sp needed + 5989 014e BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 5990 .LVL376: + 5991 .L381: + 5992 .cfi_restore_state +2843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5993 .loc 1 2843 14 view .LVU2083 + ARM GAS /tmp/ccE2rRGE.s page 259 + + + 5994 0152 0226 movs r6, #2 + 5995 0154 F9E7 b .L371 + 5996 .L382: +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5997 .loc 1 2847 5 view .LVU2084 + 5998 0156 0226 movs r6, #2 + 5999 0158 F7E7 b .L371 + 6000 .L388: + 6001 015a 00BF .align 2 + 6002 .L387: + 6003 015c 0000FFFF .word -65536 + 6004 0160 00000000 .word I2C_Master_ISR_DMA + 6005 0164 00000000 .word I2C_DMAMasterTransmitCplt + 6006 0168 00000000 .word I2C_DMAError + 6007 .cfi_endproc + 6008 .LFE150: + 6010 .section .text.HAL_I2C_Mem_Read_DMA,"ax",%progbits + 6011 .align 1 + 6012 .global HAL_I2C_Mem_Read_DMA + 6013 .syntax unified + 6014 .thumb + 6015 .thumb_func + 6017 HAL_I2C_Mem_Read_DMA: + 6018 .LVL377: + 6019 .LFB151: +2972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 6020 .loc 1 2972 1 is_stmt 1 view -0 + 6021 .cfi_startproc + 6022 @ args = 8, pretend = 0, frame = 0 + 6023 @ frame_needed = 0, uses_anonymous_args = 0 +2972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 6024 .loc 1 2972 1 is_stmt 0 view .LVU2086 + 6025 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 6026 .cfi_def_cfa_offset 24 + 6027 .cfi_offset 4, -24 + 6028 .cfi_offset 5, -20 + 6029 .cfi_offset 6, -16 + 6030 .cfi_offset 7, -12 + 6031 .cfi_offset 8, -8 + 6032 .cfi_offset 14, -4 + 6033 0004 82B0 sub sp, sp, #8 + 6034 .cfi_def_cfa_offset 32 + 6035 0006 0446 mov r4, r0 + 6036 0008 BDF82480 ldrh r8, [sp, #36] +2973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 6037 .loc 1 2973 3 is_stmt 1 view .LVU2087 +2974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6038 .loc 1 2974 3 view .LVU2088 +2975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6039 .loc 1 2975 3 view .LVU2089 +2978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6040 .loc 1 2978 3 view .LVU2090 +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6041 .loc 1 2980 3 view .LVU2091 +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6042 .loc 1 2980 11 is_stmt 0 view .LVU2092 + 6043 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + ARM GAS /tmp/ccE2rRGE.s page 260 + + + 6044 .LVL378: +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6045 .loc 1 2980 11 view .LVU2093 + 6046 0010 C0B2 uxtb r0, r0 +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6047 .loc 1 2980 6 view .LVU2094 + 6048 0012 2028 cmp r0, #32 + 6049 0014 40F09980 bne .L399 + 6050 0018 0D46 mov r5, r1 + 6051 001a 1746 mov r7, r2 + 6052 001c 1E46 mov r6, r3 +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6053 .loc 1 2982 5 is_stmt 1 view .LVU2095 +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6054 .loc 1 2982 8 is_stmt 0 view .LVU2096 + 6055 001e 089B ldr r3, [sp, #32] + 6056 .LVL379: +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6057 .loc 1 2982 8 view .LVU2097 + 6058 0020 002B cmp r3, #0 + 6059 0022 59D0 beq .L391 +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6060 .loc 1 2982 25 discriminator 1 view .LVU2098 + 6061 0024 B8F1000F cmp r8, #0 + 6062 0028 56D0 beq .L391 +2988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6063 .loc 1 2988 5 is_stmt 1 view .LVU2099 +2988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6064 .loc 1 2988 9 is_stmt 0 view .LVU2100 + 6065 002a 2368 ldr r3, [r4] + 6066 002c 9B69 ldr r3, [r3, #24] +2988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6067 .loc 1 2988 8 view .LVU2101 + 6068 002e 13F4004F tst r3, #32768 + 6069 0032 40F08F80 bne .L400 +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6070 .loc 1 2994 5 is_stmt 1 view .LVU2102 +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6071 .loc 1 2994 5 view .LVU2103 + 6072 0036 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 6073 003a 012B cmp r3, #1 + 6074 003c 00F08C80 beq .L401 +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6075 .loc 1 2994 5 discriminator 2 view .LVU2104 + 6076 0040 0123 movs r3, #1 + 6077 0042 84F84030 strb r3, [r4, #64] +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6078 .loc 1 2994 5 discriminator 2 view .LVU2105 +2997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6079 .loc 1 2997 5 discriminator 2 view .LVU2106 +2997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6080 .loc 1 2997 17 is_stmt 0 discriminator 2 view .LVU2107 + 6081 0046 FFF7FEFF bl HAL_GetTick + 6082 .LVL380: +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6083 .loc 1 2999 5 is_stmt 1 discriminator 2 view .LVU2108 +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + ARM GAS /tmp/ccE2rRGE.s page 261 + + + 6084 .loc 1 2999 23 is_stmt 0 discriminator 2 view .LVU2109 + 6085 004a 2223 movs r3, #34 + 6086 004c 84F84130 strb r3, [r4, #65] +3000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6087 .loc 1 3000 5 is_stmt 1 discriminator 2 view .LVU2110 +3000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6088 .loc 1 3000 23 is_stmt 0 discriminator 2 view .LVU2111 + 6089 0050 4023 movs r3, #64 + 6090 0052 84F84230 strb r3, [r4, #66] +3001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6091 .loc 1 3001 5 is_stmt 1 discriminator 2 view .LVU2112 +3001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6092 .loc 1 3001 23 is_stmt 0 discriminator 2 view .LVU2113 + 6093 0056 0023 movs r3, #0 + 6094 0058 6364 str r3, [r4, #68] +3004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6095 .loc 1 3004 5 is_stmt 1 discriminator 2 view .LVU2114 +3004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6096 .loc 1 3004 23 is_stmt 0 discriminator 2 view .LVU2115 + 6097 005a 089B ldr r3, [sp, #32] + 6098 005c 6362 str r3, [r4, #36] +3005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6099 .loc 1 3005 5 is_stmt 1 discriminator 2 view .LVU2116 +3005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6100 .loc 1 3005 23 is_stmt 0 discriminator 2 view .LVU2117 + 6101 005e A4F82A80 strh r8, [r4, #42] @ movhi +3006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6102 .loc 1 3006 5 is_stmt 1 discriminator 2 view .LVU2118 +3006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6103 .loc 1 3006 23 is_stmt 0 discriminator 2 view .LVU2119 + 6104 0062 3E4B ldr r3, .L406 + 6105 0064 E362 str r3, [r4, #44] +3007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6106 .loc 1 3007 5 is_stmt 1 discriminator 2 view .LVU2120 +3007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6107 .loc 1 3007 23 is_stmt 0 discriminator 2 view .LVU2121 + 6108 0066 3E4B ldr r3, .L406+4 + 6109 0068 6363 str r3, [r4, #52] +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6110 .loc 1 3009 5 is_stmt 1 discriminator 2 view .LVU2122 +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6111 .loc 1 3009 13 is_stmt 0 discriminator 2 view .LVU2123 + 6112 006a 638D ldrh r3, [r4, #42] + 6113 006c 9BB2 uxth r3, r3 +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6114 .loc 1 3009 8 discriminator 2 view .LVU2124 + 6115 006e FF2B cmp r3, #255 + 6116 0070 37D9 bls .L393 +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6117 .loc 1 3011 7 is_stmt 1 view .LVU2125 +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6118 .loc 1 3011 22 is_stmt 0 view .LVU2126 + 6119 0072 FF23 movs r3, #255 + 6120 0074 2385 strh r3, [r4, #40] @ movhi +3012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6121 .loc 1 3012 7 is_stmt 1 view .LVU2127 + 6122 .LVL381: + ARM GAS /tmp/ccE2rRGE.s page 262 + + +3012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6123 .loc 1 3012 16 is_stmt 0 view .LVU2128 + 6124 0076 4FF08078 mov r8, #16777216 + 6125 .LVL382: + 6126 .L394: +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6127 .loc 1 3021 5 is_stmt 1 view .LVU2129 +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6128 .loc 1 3021 9 is_stmt 0 view .LVU2130 + 6129 007a 0190 str r0, [sp, #4] + 6130 007c 1923 movs r3, #25 + 6131 007e 0093 str r3, [sp] + 6132 0080 3346 mov r3, r6 + 6133 0082 3A46 mov r2, r7 + 6134 0084 2946 mov r1, r5 + 6135 0086 2046 mov r0, r4 + 6136 .LVL383: +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6137 .loc 1 3021 9 view .LVU2131 + 6138 0088 FFF7FEFF bl I2C_RequestMemoryRead + 6139 .LVL384: +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6140 .loc 1 3021 8 view .LVU2132 + 6141 008c 0028 cmp r0, #0 + 6142 008e 2DD1 bne .L404 +3028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6143 .loc 1 3028 5 is_stmt 1 view .LVU2133 +3028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6144 .loc 1 3028 13 is_stmt 0 view .LVU2134 + 6145 0090 E36B ldr r3, [r4, #60] +3028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6146 .loc 1 3028 8 view .LVU2135 + 6147 0092 002B cmp r3, #0 + 6148 0094 2FD0 beq .L396 +3031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6149 .loc 1 3031 7 is_stmt 1 view .LVU2136 +3031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6150 .loc 1 3031 38 is_stmt 0 view .LVU2137 + 6151 0096 334A ldr r2, .L406+8 + 6152 0098 9A62 str r2, [r3, #40] +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6153 .loc 1 3034 7 is_stmt 1 view .LVU2138 +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6154 .loc 1 3034 11 is_stmt 0 view .LVU2139 + 6155 009a E36B ldr r3, [r4, #60] +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6156 .loc 1 3034 39 view .LVU2140 + 6157 009c 324A ldr r2, .L406+12 + 6158 009e 1A63 str r2, [r3, #48] +3037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6159 .loc 1 3037 7 is_stmt 1 view .LVU2141 +3037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6160 .loc 1 3037 11 is_stmt 0 view .LVU2142 + 6161 00a0 E26B ldr r2, [r4, #60] +3037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6162 .loc 1 3037 42 view .LVU2143 + 6163 00a2 0023 movs r3, #0 + ARM GAS /tmp/ccE2rRGE.s page 263 + + + 6164 00a4 D362 str r3, [r2, #44] +3038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6165 .loc 1 3038 7 is_stmt 1 view .LVU2144 +3038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6166 .loc 1 3038 11 is_stmt 0 view .LVU2145 + 6167 00a6 E26B ldr r2, [r4, #60] +3038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6168 .loc 1 3038 39 view .LVU2146 + 6169 00a8 5363 str r3, [r2, #52] +3041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 6170 .loc 1 3041 7 is_stmt 1 view .LVU2147 +3041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 6171 .loc 1 3041 69 is_stmt 0 view .LVU2148 + 6172 00aa 2168 ldr r1, [r4] +3041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 6173 .loc 1 3041 23 view .LVU2149 + 6174 00ac 238D ldrh r3, [r4, #40] + 6175 00ae 089A ldr r2, [sp, #32] + 6176 00b0 2431 adds r1, r1, #36 + 6177 00b2 E06B ldr r0, [r4, #60] + 6178 00b4 FFF7FEFF bl HAL_DMA_Start_IT + 6179 .LVL385: +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6180 .loc 1 3059 5 is_stmt 1 view .LVU2150 +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6181 .loc 1 3059 8 is_stmt 0 view .LVU2151 + 6182 00b8 0646 mov r6, r0 + 6183 00ba 50B3 cbz r0, .L405 +3082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6184 .loc 1 3082 7 is_stmt 1 view .LVU2152 +3082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6185 .loc 1 3082 23 is_stmt 0 view .LVU2153 + 6186 00bc 2023 movs r3, #32 + 6187 00be 84F84130 strb r3, [r4, #65] +3083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6188 .loc 1 3083 7 is_stmt 1 view .LVU2154 +3083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6189 .loc 1 3083 23 is_stmt 0 view .LVU2155 + 6190 00c2 0022 movs r2, #0 + 6191 00c4 84F84220 strb r2, [r4, #66] +3086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6192 .loc 1 3086 7 is_stmt 1 view .LVU2156 +3086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6193 .loc 1 3086 11 is_stmt 0 view .LVU2157 + 6194 00c8 636C ldr r3, [r4, #68] +3086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6195 .loc 1 3086 23 view .LVU2158 + 6196 00ca 43F01003 orr r3, r3, #16 + 6197 00ce 6364 str r3, [r4, #68] +3089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6198 .loc 1 3089 7 is_stmt 1 view .LVU2159 +3089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6199 .loc 1 3089 7 view .LVU2160 + 6200 00d0 84F84020 strb r2, [r4, #64] +3089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6201 .loc 1 3089 7 view .LVU2161 +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 264 + + + 6202 .loc 1 3091 7 view .LVU2162 +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6203 .loc 1 3091 14 is_stmt 0 view .LVU2163 + 6204 00d4 0126 movs r6, #1 + 6205 00d6 39E0 b .L390 + 6206 .LVL386: + 6207 .L391: +2984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 6208 .loc 1 2984 7 is_stmt 1 view .LVU2164 +2984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 6209 .loc 1 2984 23 is_stmt 0 view .LVU2165 + 6210 00d8 4FF40073 mov r3, #512 + 6211 00dc 6364 str r3, [r4, #68] +2985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6212 .loc 1 2985 7 is_stmt 1 view .LVU2166 +2985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6213 .loc 1 2985 15 is_stmt 0 view .LVU2167 + 6214 00de 0126 movs r6, #1 + 6215 00e0 34E0 b .L390 + 6216 .LVL387: + 6217 .L393: +3016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6218 .loc 1 3016 7 is_stmt 1 view .LVU2168 +3016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6219 .loc 1 3016 28 is_stmt 0 view .LVU2169 + 6220 00e2 638D ldrh r3, [r4, #42] +3016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6221 .loc 1 3016 22 view .LVU2170 + 6222 00e4 2385 strh r3, [r4, #40] @ movhi +3017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6223 .loc 1 3017 7 is_stmt 1 view .LVU2171 + 6224 .LVL388: +3017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6225 .loc 1 3017 16 is_stmt 0 view .LVU2172 + 6226 00e6 4FF00078 mov r8, #33554432 + 6227 00ea C6E7 b .L394 + 6228 .LVL389: + 6229 .L404: +3024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 6230 .loc 1 3024 7 is_stmt 1 view .LVU2173 +3024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 6231 .loc 1 3024 7 view .LVU2174 + 6232 00ec 0023 movs r3, #0 + 6233 00ee 84F84030 strb r3, [r4, #64] +3024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 6234 .loc 1 3024 7 view .LVU2175 +3025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6235 .loc 1 3025 7 view .LVU2176 +3025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6236 .loc 1 3025 14 is_stmt 0 view .LVU2177 + 6237 00f2 0126 movs r6, #1 + 6238 00f4 2AE0 b .L390 + 6239 .L396: +3047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6240 .loc 1 3047 7 is_stmt 1 view .LVU2178 +3047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6241 .loc 1 3047 23 is_stmt 0 view .LVU2179 + ARM GAS /tmp/ccE2rRGE.s page 265 + + + 6242 00f6 2023 movs r3, #32 + 6243 00f8 84F84130 strb r3, [r4, #65] +3048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6244 .loc 1 3048 7 is_stmt 1 view .LVU2180 +3048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6245 .loc 1 3048 23 is_stmt 0 view .LVU2181 + 6246 00fc 0022 movs r2, #0 + 6247 00fe 84F84220 strb r2, [r4, #66] +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6248 .loc 1 3051 7 is_stmt 1 view .LVU2182 +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6249 .loc 1 3051 11 is_stmt 0 view .LVU2183 + 6250 0102 636C ldr r3, [r4, #68] +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6251 .loc 1 3051 23 view .LVU2184 + 6252 0104 43F08003 orr r3, r3, #128 + 6253 0108 6364 str r3, [r4, #68] +3054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6254 .loc 1 3054 7 is_stmt 1 view .LVU2185 +3054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6255 .loc 1 3054 7 view .LVU2186 + 6256 010a 84F84020 strb r2, [r4, #64] +3054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6257 .loc 1 3054 7 view .LVU2187 +3056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6258 .loc 1 3056 7 view .LVU2188 +3056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6259 .loc 1 3056 14 is_stmt 0 view .LVU2189 + 6260 010e 0126 movs r6, #1 + 6261 0110 1CE0 b .L390 + 6262 .LVL390: + 6263 .L405: +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6264 .loc 1 3062 7 is_stmt 1 view .LVU2190 + 6265 0112 164B ldr r3, .L406+16 + 6266 0114 0093 str r3, [sp] + 6267 0116 4346 mov r3, r8 + 6268 0118 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 6269 011c 2946 mov r1, r5 + 6270 011e 2046 mov r0, r4 + 6271 .LVL391: +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6272 .loc 1 3062 7 is_stmt 0 view .LVU2191 + 6273 0120 FFF7FEFF bl I2C_TransferConfig + 6274 .LVL392: +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6275 .loc 1 3065 7 is_stmt 1 view .LVU2192 +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6276 .loc 1 3065 11 is_stmt 0 view .LVU2193 + 6277 0124 638D ldrh r3, [r4, #42] + 6278 0126 9BB2 uxth r3, r3 +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6279 .loc 1 3065 30 view .LVU2194 + 6280 0128 228D ldrh r2, [r4, #40] +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6281 .loc 1 3065 23 view .LVU2195 + 6282 012a 9B1A subs r3, r3, r2 + ARM GAS /tmp/ccE2rRGE.s page 266 + + + 6283 012c 9BB2 uxth r3, r3 + 6284 012e 6385 strh r3, [r4, #42] @ movhi +3068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6285 .loc 1 3068 7 is_stmt 1 view .LVU2196 +3068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6286 .loc 1 3068 7 view .LVU2197 + 6287 0130 0023 movs r3, #0 + 6288 0132 84F84030 strb r3, [r4, #64] +3068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6289 .loc 1 3068 7 view .LVU2198 +3074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6290 .loc 1 3074 7 view .LVU2199 + 6291 0136 1021 movs r1, #16 + 6292 0138 2046 mov r0, r4 + 6293 013a FFF7FEFF bl I2C_Enable_IRQ + 6294 .LVL393: +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6295 .loc 1 3077 7 view .LVU2200 +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6296 .loc 1 3077 11 is_stmt 0 view .LVU2201 + 6297 013e 2268 ldr r2, [r4] +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6298 .loc 1 3077 21 view .LVU2202 + 6299 0140 1368 ldr r3, [r2] +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6300 .loc 1 3077 27 view .LVU2203 + 6301 0142 43F40043 orr r3, r3, #32768 + 6302 0146 1360 str r3, [r2] +3094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6303 .loc 1 3094 5 is_stmt 1 view .LVU2204 +3094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6304 .loc 1 3094 12 is_stmt 0 view .LVU2205 + 6305 0148 00E0 b .L390 + 6306 .LVL394: + 6307 .L399: +3098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6308 .loc 1 3098 12 view .LVU2206 + 6309 014a 0226 movs r6, #2 + 6310 .LVL395: + 6311 .L390: +3100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6312 .loc 1 3100 1 view .LVU2207 + 6313 014c 3046 mov r0, r6 + 6314 014e 02B0 add sp, sp, #8 + 6315 .cfi_remember_state + 6316 .cfi_def_cfa_offset 24 + 6317 @ sp needed + 6318 0150 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 6319 .LVL396: + 6320 .L400: + 6321 .cfi_restore_state +2990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6322 .loc 1 2990 14 view .LVU2208 + 6323 0154 0226 movs r6, #2 + 6324 0156 F9E7 b .L390 + 6325 .L401: +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 267 + + + 6326 .loc 1 2994 5 view .LVU2209 + 6327 0158 0226 movs r6, #2 + 6328 015a F7E7 b .L390 + 6329 .L407: + 6330 .align 2 + 6331 .L406: + 6332 015c 0000FFFF .word -65536 + 6333 0160 00000000 .word I2C_Master_ISR_DMA + 6334 0164 00000000 .word I2C_DMAMasterReceiveCplt + 6335 0168 00000000 .word I2C_DMAError + 6336 016c 00240080 .word -2147474432 + 6337 .cfi_endproc + 6338 .LFE151: + 6340 .section .text.HAL_I2C_IsDeviceReady,"ax",%progbits + 6341 .align 1 + 6342 .global HAL_I2C_IsDeviceReady + 6343 .syntax unified + 6344 .thumb + 6345 .thumb_func + 6347 HAL_I2C_IsDeviceReady: + 6348 .LVL397: + 6349 .LFB152: +3115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 6350 .loc 1 3115 1 is_stmt 1 view -0 + 6351 .cfi_startproc + 6352 @ args = 0, pretend = 0, frame = 8 + 6353 @ frame_needed = 0, uses_anonymous_args = 0 +3115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; + 6354 .loc 1 3115 1 is_stmt 0 view .LVU2211 + 6355 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 6356 .cfi_def_cfa_offset 28 + 6357 .cfi_offset 4, -28 + 6358 .cfi_offset 5, -24 + 6359 .cfi_offset 6, -20 + 6360 .cfi_offset 7, -16 + 6361 .cfi_offset 8, -12 + 6362 .cfi_offset 9, -8 + 6363 .cfi_offset 14, -4 + 6364 0004 85B0 sub sp, sp, #20 + 6365 .cfi_def_cfa_offset 48 + 6366 0006 1D46 mov r5, r3 +3116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6367 .loc 1 3116 3 is_stmt 1 view .LVU2212 +3118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6368 .loc 1 3118 3 view .LVU2213 +3118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6369 .loc 1 3118 17 is_stmt 0 view .LVU2214 + 6370 0008 0023 movs r3, #0 + 6371 .LVL398: +3118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6372 .loc 1 3118 17 view .LVU2215 + 6373 000a 0393 str r3, [sp, #12] +3120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp2; + 6374 .loc 1 3120 3 is_stmt 1 view .LVU2216 +3121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6375 .loc 1 3121 3 view .LVU2217 +3123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 268 + + + 6376 .loc 1 3123 3 view .LVU2218 +3123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6377 .loc 1 3123 11 is_stmt 0 view .LVU2219 + 6378 000c 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 6379 0010 DBB2 uxtb r3, r3 +3123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6380 .loc 1 3123 6 view .LVU2220 + 6381 0012 202B cmp r3, #32 + 6382 0014 40F09E80 bne .L420 + 6383 0018 0646 mov r6, r0 + 6384 001a 8946 mov r9, r1 + 6385 001c 9046 mov r8, r2 +3125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6386 .loc 1 3125 5 is_stmt 1 view .LVU2221 +3125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6387 .loc 1 3125 9 is_stmt 0 view .LVU2222 + 6388 001e 0368 ldr r3, [r0] + 6389 0020 9B69 ldr r3, [r3, #24] +3125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6390 .loc 1 3125 8 view .LVU2223 + 6391 0022 13F4004F tst r3, #32768 + 6392 0026 40F09780 bne .L421 +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6393 .loc 1 3131 5 is_stmt 1 view .LVU2224 +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6394 .loc 1 3131 5 view .LVU2225 + 6395 002a 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 6396 002e 012B cmp r3, #1 + 6397 0030 00F09480 beq .L422 +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6398 .loc 1 3131 5 discriminator 2 view .LVU2226 + 6399 0034 0123 movs r3, #1 + 6400 0036 80F84030 strb r3, [r0, #64] +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6401 .loc 1 3131 5 discriminator 2 view .LVU2227 +3133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6402 .loc 1 3133 5 discriminator 2 view .LVU2228 +3133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6403 .loc 1 3133 17 is_stmt 0 discriminator 2 view .LVU2229 + 6404 003a 2423 movs r3, #36 + 6405 003c 80F84130 strb r3, [r0, #65] +3134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6406 .loc 1 3134 5 is_stmt 1 discriminator 2 view .LVU2230 +3134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6407 .loc 1 3134 21 is_stmt 0 discriminator 2 view .LVU2231 + 6408 0040 0023 movs r3, #0 + 6409 0042 4364 str r3, [r0, #68] + 6410 0044 44E0 b .L419 + 6411 .LVL399: + 6412 .L430: +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6413 .loc 1 3139 29 discriminator 1 view .LVU2232 + 6414 0046 C9F30903 ubfx r3, r9, #0, #10 + 6415 004a 43F00073 orr r3, r3, #33554432 + 6416 004e 43F40053 orr r3, r3, #8192 + 6417 0052 44E0 b .L411 + 6418 .LVL400: + ARM GAS /tmp/ccE2rRGE.s page 269 + + + 6419 .L413: +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6420 .loc 1 3167 9 is_stmt 1 view .LVU2233 +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6421 .loc 1 3167 16 is_stmt 0 view .LVU2234 + 6422 0054 3368 ldr r3, [r6] + 6423 0056 9C69 ldr r4, [r3, #24] + 6424 .LVL401: +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6425 .loc 1 3167 16 view .LVU2235 + 6426 0058 C4F34014 ubfx r4, r4, #5, #1 + 6427 .LVL402: +3168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6428 .loc 1 3168 9 is_stmt 1 view .LVU2236 +3168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6429 .loc 1 3168 16 is_stmt 0 view .LVU2237 + 6430 005c 9B69 ldr r3, [r3, #24] + 6431 005e C3F30013 ubfx r3, r3, #4, #1 + 6432 .LVL403: + 6433 .L412: +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6434 .loc 1 3148 30 is_stmt 1 view .LVU2238 + 6435 0062 C4B9 cbnz r4, .L415 +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6436 .loc 1 3148 30 is_stmt 0 discriminator 1 view .LVU2239 + 6437 0064 BBB9 cbnz r3, .L415 +3150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6438 .loc 1 3150 9 is_stmt 1 view .LVU2240 +3150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6439 .loc 1 3150 12 is_stmt 0 view .LVU2241 + 6440 0066 B5F1FF3F cmp r5, #-1 + 6441 006a F3D0 beq .L413 +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6442 .loc 1 3152 11 is_stmt 1 view .LVU2242 +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6443 .loc 1 3152 17 is_stmt 0 view .LVU2243 + 6444 006c FFF7FEFF bl HAL_GetTick + 6445 .LVL404: +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6446 .loc 1 3152 31 view .LVU2244 + 6447 0070 C01B subs r0, r0, r7 +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6448 .loc 1 3152 14 view .LVU2245 + 6449 0072 A842 cmp r0, r5 + 6450 0074 01D8 bhi .L414 +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6451 .loc 1 3152 55 discriminator 1 view .LVU2246 + 6452 0076 002D cmp r5, #0 + 6453 0078 ECD1 bne .L413 + 6454 .L414: +3155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6455 .loc 1 3155 13 is_stmt 1 view .LVU2247 +3155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6456 .loc 1 3155 25 is_stmt 0 view .LVU2248 + 6457 007a 2023 movs r3, #32 + 6458 007c 86F84130 strb r3, [r6, #65] +3158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 270 + + + 6459 .loc 1 3158 13 is_stmt 1 view .LVU2249 +3158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6460 .loc 1 3158 17 is_stmt 0 view .LVU2250 + 6461 0080 736C ldr r3, [r6, #68] +3158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6462 .loc 1 3158 29 view .LVU2251 + 6463 0082 43F02003 orr r3, r3, #32 + 6464 0086 7364 str r3, [r6, #68] +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6465 .loc 1 3161 13 is_stmt 1 view .LVU2252 +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6466 .loc 1 3161 13 view .LVU2253 + 6467 0088 0023 movs r3, #0 + 6468 008a 86F84030 strb r3, [r6, #64] +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6469 .loc 1 3161 13 view .LVU2254 +3163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6470 .loc 1 3163 13 view .LVU2255 +3163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6471 .loc 1 3163 20 is_stmt 0 view .LVU2256 + 6472 008e 0120 movs r0, #1 + 6473 .LVL405: + 6474 .L409: +3241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6475 .loc 1 3241 1 view .LVU2257 + 6476 0090 05B0 add sp, sp, #20 + 6477 .cfi_remember_state + 6478 .cfi_def_cfa_offset 28 + 6479 @ sp needed + 6480 0092 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 6481 .LVL406: + 6482 .L415: + 6483 .cfi_restore_state +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6484 .loc 1 3172 7 is_stmt 1 view .LVU2258 +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6485 .loc 1 3172 11 is_stmt 0 view .LVU2259 + 6486 0096 3368 ldr r3, [r6] + 6487 .LVL407: +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6488 .loc 1 3172 11 view .LVU2260 + 6489 0098 9B69 ldr r3, [r3, #24] +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6490 .loc 1 3172 10 view .LVU2261 + 6491 009a 13F0100F tst r3, #16 + 6492 009e 2BD0 beq .L427 +3194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6493 .loc 1 3194 9 is_stmt 1 view .LVU2262 +3194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6494 .loc 1 3194 13 is_stmt 0 view .LVU2263 + 6495 00a0 0097 str r7, [sp] + 6496 00a2 2B46 mov r3, r5 + 6497 00a4 0022 movs r2, #0 + 6498 00a6 2021 movs r1, #32 + 6499 00a8 3046 mov r0, r6 + 6500 00aa FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6501 .LVL408: + ARM GAS /tmp/ccE2rRGE.s page 271 + + +3194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6502 .loc 1 3194 12 view .LVU2264 + 6503 00ae 0028 cmp r0, #0 + 6504 00b0 58D1 bne .L424 +3200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6505 .loc 1 3200 9 is_stmt 1 view .LVU2265 + 6506 00b2 3368 ldr r3, [r6] + 6507 00b4 1022 movs r2, #16 + 6508 00b6 DA61 str r2, [r3, #28] +3203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6509 .loc 1 3203 9 view .LVU2266 + 6510 00b8 3368 ldr r3, [r6] + 6511 00ba 2022 movs r2, #32 + 6512 00bc DA61 str r2, [r3, #28] +3207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6513 .loc 1 3207 7 view .LVU2267 +3207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6514 .loc 1 3207 22 is_stmt 0 view .LVU2268 + 6515 00be 039B ldr r3, [sp, #12] +3207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6516 .loc 1 3207 10 view .LVU2269 + 6517 00c0 4345 cmp r3, r8 + 6518 00c2 2AD0 beq .L428 + 6519 .L418: +3223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } while (I2C_Trials < Trials); + 6520 .loc 1 3223 7 is_stmt 1 view .LVU2270 +3223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } while (I2C_Trials < Trials); + 6521 .loc 1 3223 17 is_stmt 0 view .LVU2271 + 6522 00c4 039B ldr r3, [sp, #12] + 6523 00c6 0133 adds r3, r3, #1 + 6524 00c8 0393 str r3, [sp, #12] +3224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6525 .loc 1 3224 25 is_stmt 1 view .LVU2272 + 6526 00ca 039B ldr r3, [sp, #12] + 6527 00cc 4345 cmp r3, r8 + 6528 00ce 35D2 bcs .L429 + 6529 .LVL409: + 6530 .L419: +3136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6531 .loc 1 3136 5 view .LVU2273 +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6532 .loc 1 3139 7 view .LVU2274 +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6533 .loc 1 3139 29 is_stmt 0 view .LVU2275 + 6534 00d0 F368 ldr r3, [r6, #12] + 6535 00d2 012B cmp r3, #1 + 6536 00d4 B7D0 beq .L430 +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6537 .loc 1 3139 29 discriminator 2 view .LVU2276 + 6538 00d6 C9F30903 ubfx r3, r9, #0, #10 + 6539 00da 43F42053 orr r3, r3, #10240 + 6540 .L411: +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6541 .loc 1 3139 11 discriminator 4 view .LVU2277 + 6542 00de 3268 ldr r2, [r6] +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6543 .loc 1 3139 27 discriminator 4 view .LVU2278 + ARM GAS /tmp/ccE2rRGE.s page 272 + + + 6544 00e0 5360 str r3, [r2, #4] +3143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6545 .loc 1 3143 7 is_stmt 1 discriminator 4 view .LVU2279 +3143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6546 .loc 1 3143 19 is_stmt 0 discriminator 4 view .LVU2280 + 6547 00e2 FFF7FEFF bl HAL_GetTick + 6548 .LVL410: + 6549 00e6 0746 mov r7, r0 + 6550 .LVL411: +3145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6551 .loc 1 3145 7 is_stmt 1 discriminator 4 view .LVU2281 +3145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 6552 .loc 1 3145 14 is_stmt 0 discriminator 4 view .LVU2282 + 6553 00e8 3368 ldr r3, [r6] + 6554 00ea 9C69 ldr r4, [r3, #24] + 6555 00ec C4F34014 ubfx r4, r4, #5, #1 + 6556 .LVL412: +3146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6557 .loc 1 3146 7 is_stmt 1 discriminator 4 view .LVU2283 +3146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6558 .loc 1 3146 14 is_stmt 0 discriminator 4 view .LVU2284 + 6559 00f0 9B69 ldr r3, [r3, #24] + 6560 00f2 C3F30013 ubfx r3, r3, #4, #1 + 6561 .LVL413: +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6562 .loc 1 3148 7 is_stmt 1 discriminator 4 view .LVU2285 +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6563 .loc 1 3148 13 is_stmt 0 discriminator 4 view .LVU2286 + 6564 00f6 B4E7 b .L412 + 6565 .LVL414: + 6566 .L427: +3175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6567 .loc 1 3175 9 is_stmt 1 view .LVU2287 +3175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6568 .loc 1 3175 13 is_stmt 0 view .LVU2288 + 6569 00f8 0097 str r7, [sp] + 6570 00fa 2B46 mov r3, r5 + 6571 00fc 0022 movs r2, #0 + 6572 00fe 2021 movs r1, #32 + 6573 0100 3046 mov r0, r6 + 6574 0102 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6575 .LVL415: +3175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6576 .loc 1 3175 12 view .LVU2289 + 6577 0106 58BB cbnz r0, .L423 +3181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6578 .loc 1 3181 9 is_stmt 1 view .LVU2290 + 6579 0108 3268 ldr r2, [r6] + 6580 010a 2023 movs r3, #32 + 6581 010c D361 str r3, [r2, #28] +3184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6582 .loc 1 3184 9 view .LVU2291 +3184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6583 .loc 1 3184 21 is_stmt 0 view .LVU2292 + 6584 010e 86F84130 strb r3, [r6, #65] +3187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6585 .loc 1 3187 9 is_stmt 1 view .LVU2293 + ARM GAS /tmp/ccE2rRGE.s page 273 + + +3187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6586 .loc 1 3187 9 view .LVU2294 + 6587 0112 0023 movs r3, #0 + 6588 0114 86F84030 strb r3, [r6, #64] +3187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6589 .loc 1 3187 9 view .LVU2295 +3189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6590 .loc 1 3189 9 view .LVU2296 +3189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6591 .loc 1 3189 16 is_stmt 0 view .LVU2297 + 6592 0118 BAE7 b .L409 + 6593 .L428: +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6594 .loc 1 3210 9 is_stmt 1 view .LVU2298 +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6595 .loc 1 3210 13 is_stmt 0 view .LVU2299 + 6596 011a 3268 ldr r2, [r6] +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6597 .loc 1 3210 23 view .LVU2300 + 6598 011c 5368 ldr r3, [r2, #4] +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6599 .loc 1 3210 29 view .LVU2301 + 6600 011e 43F48043 orr r3, r3, #16384 + 6601 0122 5360 str r3, [r2, #4] +3213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6602 .loc 1 3213 9 is_stmt 1 view .LVU2302 +3213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6603 .loc 1 3213 13 is_stmt 0 view .LVU2303 + 6604 0124 0097 str r7, [sp] + 6605 0126 2B46 mov r3, r5 + 6606 0128 0022 movs r2, #0 + 6607 012a 2021 movs r1, #32 + 6608 012c 3046 mov r0, r6 + 6609 012e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 6610 .LVL416: +3213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6611 .loc 1 3213 12 view .LVU2304 + 6612 0132 C8B9 cbnz r0, .L425 +3219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6613 .loc 1 3219 9 is_stmt 1 view .LVU2305 + 6614 0134 3368 ldr r3, [r6] + 6615 0136 2022 movs r2, #32 + 6616 0138 DA61 str r2, [r3, #28] + 6617 013a C3E7 b .L418 + 6618 .L429: +3227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6619 .loc 1 3227 5 view .LVU2306 +3227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6620 .loc 1 3227 17 is_stmt 0 view .LVU2307 + 6621 013c 2023 movs r3, #32 + 6622 013e 86F84130 strb r3, [r6, #65] +3230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6623 .loc 1 3230 5 is_stmt 1 view .LVU2308 +3230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6624 .loc 1 3230 9 is_stmt 0 view .LVU2309 + 6625 0142 736C ldr r3, [r6, #68] +3230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 274 + + + 6626 .loc 1 3230 21 view .LVU2310 + 6627 0144 43F02003 orr r3, r3, #32 + 6628 0148 7364 str r3, [r6, #68] +3233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6629 .loc 1 3233 5 is_stmt 1 view .LVU2311 +3233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6630 .loc 1 3233 5 view .LVU2312 + 6631 014a 0023 movs r3, #0 + 6632 014c 86F84030 strb r3, [r6, #64] +3233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6633 .loc 1 3233 5 view .LVU2313 +3235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6634 .loc 1 3235 5 view .LVU2314 +3235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6635 .loc 1 3235 12 is_stmt 0 view .LVU2315 + 6636 0150 0120 movs r0, #1 + 6637 0152 9DE7 b .L409 + 6638 .LVL417: + 6639 .L420: +3239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6640 .loc 1 3239 12 view .LVU2316 + 6641 0154 0220 movs r0, #2 + 6642 .LVL418: +3239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6643 .loc 1 3239 12 view .LVU2317 + 6644 0156 9BE7 b .L409 + 6645 .LVL419: + 6646 .L421: +3127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6647 .loc 1 3127 14 view .LVU2318 + 6648 0158 0220 movs r0, #2 + 6649 .LVL420: +3127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6650 .loc 1 3127 14 view .LVU2319 + 6651 015a 99E7 b .L409 + 6652 .LVL421: + 6653 .L422: +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6654 .loc 1 3131 5 view .LVU2320 + 6655 015c 0220 movs r0, #2 + 6656 .LVL422: +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6657 .loc 1 3131 5 view .LVU2321 + 6658 015e 97E7 b .L409 + 6659 .LVL423: + 6660 .L423: +3177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6661 .loc 1 3177 18 view .LVU2322 + 6662 0160 0120 movs r0, #1 + 6663 0162 95E7 b .L409 + 6664 .L424: +3196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6665 .loc 1 3196 18 view .LVU2323 + 6666 0164 0120 movs r0, #1 + 6667 0166 93E7 b .L409 + 6668 .L425: +3215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 275 + + + 6669 .loc 1 3215 18 view .LVU2324 + 6670 0168 0120 movs r0, #1 + 6671 016a 91E7 b .L409 + 6672 .cfi_endproc + 6673 .LFE152: + 6675 .section .text.HAL_I2C_Master_Seq_Transmit_IT,"ax",%progbits + 6676 .align 1 + 6677 .global HAL_I2C_Master_Seq_Transmit_IT + 6678 .syntax unified + 6679 .thumb + 6680 .thumb_func + 6682 HAL_I2C_Master_Seq_Transmit_IT: + 6683 .LVL424: + 6684 .LFB153: +3257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 6685 .loc 1 3257 1 is_stmt 1 view -0 + 6686 .cfi_startproc + 6687 @ args = 4, pretend = 0, frame = 0 + 6688 @ frame_needed = 0, uses_anonymous_args = 0 +3257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 6689 .loc 1 3257 1 is_stmt 0 view .LVU2326 + 6690 0000 70B5 push {r4, r5, r6, lr} + 6691 .cfi_def_cfa_offset 16 + 6692 .cfi_offset 4, -16 + 6693 .cfi_offset 5, -12 + 6694 .cfi_offset 6, -8 + 6695 .cfi_offset 14, -4 + 6696 0002 82B0 sub sp, sp, #8 + 6697 .cfi_def_cfa_offset 24 + 6698 0004 0446 mov r4, r0 +3258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 6699 .loc 1 3258 3 is_stmt 1 view .LVU2327 +3259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6700 .loc 1 3259 3 view .LVU2328 + 6701 .LVL425: +3262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6702 .loc 1 3262 3 view .LVU2329 +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6703 .loc 1 3264 3 view .LVU2330 +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6704 .loc 1 3264 11 is_stmt 0 view .LVU2331 + 6705 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 6706 .LVL426: +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6707 .loc 1 3264 11 view .LVU2332 + 6708 000a C0B2 uxtb r0, r0 +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6709 .loc 1 3264 6 view .LVU2333 + 6710 000c 2028 cmp r0, #32 + 6711 000e 49D1 bne .L437 + 6712 0010 0D46 mov r5, r1 +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6713 .loc 1 3267 5 is_stmt 1 view .LVU2334 +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6714 .loc 1 3267 5 view .LVU2335 + 6715 0012 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 6716 .LVL427: + ARM GAS /tmp/ccE2rRGE.s page 276 + + +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6717 .loc 1 3267 5 is_stmt 0 view .LVU2336 + 6718 0016 0129 cmp r1, #1 + 6719 0018 46D0 beq .L438 +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6720 .loc 1 3267 5 is_stmt 1 discriminator 2 view .LVU2337 + 6721 001a 0121 movs r1, #1 + 6722 001c 84F84010 strb r1, [r4, #64] +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6723 .loc 1 3267 5 discriminator 2 view .LVU2338 +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6724 .loc 1 3269 5 discriminator 2 view .LVU2339 +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6725 .loc 1 3269 21 is_stmt 0 discriminator 2 view .LVU2340 + 6726 0020 2121 movs r1, #33 + 6727 0022 84F84110 strb r1, [r4, #65] +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6728 .loc 1 3270 5 is_stmt 1 discriminator 2 view .LVU2341 +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6729 .loc 1 3270 21 is_stmt 0 discriminator 2 view .LVU2342 + 6730 0026 1021 movs r1, #16 + 6731 0028 84F84210 strb r1, [r4, #66] +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6732 .loc 1 3271 5 is_stmt 1 discriminator 2 view .LVU2343 +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6733 .loc 1 3271 21 is_stmt 0 discriminator 2 view .LVU2344 + 6734 002c 0021 movs r1, #0 + 6735 002e 6164 str r1, [r4, #68] +3274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6736 .loc 1 3274 5 is_stmt 1 discriminator 2 view .LVU2345 +3274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6737 .loc 1 3274 23 is_stmt 0 discriminator 2 view .LVU2346 + 6738 0030 6262 str r2, [r4, #36] +3275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6739 .loc 1 3275 5 is_stmt 1 discriminator 2 view .LVU2347 +3275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6740 .loc 1 3275 23 is_stmt 0 discriminator 2 view .LVU2348 + 6741 0032 6385 strh r3, [r4, #42] @ movhi +3276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6742 .loc 1 3276 5 is_stmt 1 discriminator 2 view .LVU2349 +3276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6743 .loc 1 3276 23 is_stmt 0 discriminator 2 view .LVU2350 + 6744 0034 069B ldr r3, [sp, #24] + 6745 .LVL428: +3276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6746 .loc 1 3276 23 discriminator 2 view .LVU2351 + 6747 0036 E362 str r3, [r4, #44] + 6748 .LVL429: +3277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6749 .loc 1 3277 5 is_stmt 1 discriminator 2 view .LVU2352 +3277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6750 .loc 1 3277 23 is_stmt 0 discriminator 2 view .LVU2353 + 6751 0038 1C4B ldr r3, .L442 + 6752 003a 6363 str r3, [r4, #52] +3280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6753 .loc 1 3280 5 is_stmt 1 discriminator 2 view .LVU2354 +3280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 277 + + + 6754 .loc 1 3280 13 is_stmt 0 discriminator 2 view .LVU2355 + 6755 003c 638D ldrh r3, [r4, #42] + 6756 003e 9BB2 uxth r3, r3 +3280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6757 .loc 1 3280 8 discriminator 2 view .LVU2356 + 6758 0040 FF2B cmp r3, #255 + 6759 0042 0ED9 bls .L433 +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6760 .loc 1 3282 7 is_stmt 1 view .LVU2357 +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6761 .loc 1 3282 22 is_stmt 0 view .LVU2358 + 6762 0044 FF23 movs r3, #255 + 6763 0046 2385 strh r3, [r4, #40] @ movhi +3283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6764 .loc 1 3283 7 is_stmt 1 view .LVU2359 + 6765 .LVL430: +3283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6766 .loc 1 3283 16 is_stmt 0 view .LVU2360 + 6767 0048 4FF08076 mov r6, #16777216 + 6768 .LVL431: + 6769 .L434: +3294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6770 .loc 1 3294 5 is_stmt 1 view .LVU2361 +3294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6771 .loc 1 3294 14 is_stmt 0 view .LVU2362 + 6772 004c 236B ldr r3, [r4, #48] +3294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6773 .loc 1 3294 8 view .LVU2363 + 6774 004e 112B cmp r3, #17 + 6775 0050 0BD1 bne .L435 +3295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6776 .loc 1 3295 10 view .LVU2364 + 6777 0052 069B ldr r3, [sp, #24] + 6778 0054 AA2B cmp r3, #170 + 6779 0056 08D0 beq .L435 +3295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6780 .loc 1 3295 10 discriminator 2 view .LVU2365 + 6781 0058 B3F52A4F cmp r3, #43520 + 6782 005c 05D0 beq .L435 +3297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6783 .loc 1 3297 19 view .LVU2366 + 6784 005e 0023 movs r3, #0 + 6785 0060 0CE0 b .L436 + 6786 .LVL432: + 6787 .L433: +3287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6788 .loc 1 3287 7 is_stmt 1 view .LVU2367 +3287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6789 .loc 1 3287 28 is_stmt 0 view .LVU2368 + 6790 0062 638D ldrh r3, [r4, #42] +3287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6791 .loc 1 3287 22 view .LVU2369 + 6792 0064 2385 strh r3, [r4, #40] @ movhi +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6793 .loc 1 3288 7 is_stmt 1 view .LVU2370 +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6794 .loc 1 3288 16 is_stmt 0 view .LVU2371 + ARM GAS /tmp/ccE2rRGE.s page 278 + + + 6795 0066 E66A ldr r6, [r4, #44] + 6796 .LVL433: +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6797 .loc 1 3288 16 view .LVU2372 + 6798 0068 F0E7 b .L434 + 6799 .L435: +3302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6800 .loc 1 3302 7 is_stmt 1 view .LVU2373 + 6801 006a 2046 mov r0, r4 + 6802 006c FFF7FEFF bl I2C_ConvertOtherXferOptions + 6803 .LVL434: +3305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6804 .loc 1 3305 7 view .LVU2374 +3305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6805 .loc 1 3305 15 is_stmt 0 view .LVU2375 + 6806 0070 638D ldrh r3, [r4, #42] + 6807 0072 9BB2 uxth r3, r3 +3305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6808 .loc 1 3305 10 view .LVU2376 + 6809 0074 FF2B cmp r3, #255 + 6810 0076 13D8 bhi .L440 +3307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6811 .loc 1 3307 9 is_stmt 1 view .LVU2377 +3307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6812 .loc 1 3307 18 is_stmt 0 view .LVU2378 + 6813 0078 E66A ldr r6, [r4, #44] + 6814 .LVL435: +3259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6815 .loc 1 3259 12 view .LVU2379 + 6816 007a 0D4B ldr r3, .L442+4 + 6817 .L436: + 6818 .LVL436: +3312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6819 .loc 1 3312 5 is_stmt 1 view .LVU2380 + 6820 007c 0093 str r3, [sp] + 6821 007e 3346 mov r3, r6 + 6822 .LVL437: +3312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6823 .loc 1 3312 5 is_stmt 0 view .LVU2381 + 6824 0080 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 6825 0084 2946 mov r1, r5 + 6826 0086 2046 mov r0, r4 + 6827 0088 FFF7FEFF bl I2C_TransferConfig + 6828 .LVL438: +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6829 .loc 1 3315 5 is_stmt 1 view .LVU2382 +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6830 .loc 1 3315 5 view .LVU2383 + 6831 008c 0025 movs r5, #0 + 6832 008e 84F84050 strb r5, [r4, #64] +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6833 .loc 1 3315 5 view .LVU2384 +3320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6834 .loc 1 3320 5 view .LVU2385 + 6835 0092 0121 movs r1, #1 + 6836 0094 2046 mov r0, r4 + 6837 0096 FFF7FEFF bl I2C_Enable_IRQ + ARM GAS /tmp/ccE2rRGE.s page 279 + + + 6838 .LVL439: +3322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6839 .loc 1 3322 5 view .LVU2386 +3322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6840 .loc 1 3322 12 is_stmt 0 view .LVU2387 + 6841 009a 2846 mov r0, r5 + 6842 .LVL440: + 6843 .L432: +3328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6844 .loc 1 3328 1 view .LVU2388 + 6845 009c 02B0 add sp, sp, #8 + 6846 .cfi_remember_state + 6847 .cfi_def_cfa_offset 16 + 6848 @ sp needed + 6849 009e 70BD pop {r4, r5, r6, pc} + 6850 .LVL441: + 6851 .L440: + 6852 .cfi_restore_state +3259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6853 .loc 1 3259 12 view .LVU2389 + 6854 00a0 034B ldr r3, .L442+4 + 6855 00a2 EBE7 b .L436 + 6856 .LVL442: + 6857 .L437: +3326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6858 .loc 1 3326 12 view .LVU2390 + 6859 00a4 0220 movs r0, #2 + 6860 00a6 F9E7 b .L432 + 6861 .LVL443: + 6862 .L438: +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6863 .loc 1 3267 5 view .LVU2391 + 6864 00a8 0220 movs r0, #2 + 6865 00aa F7E7 b .L432 + 6866 .L443: + 6867 .align 2 + 6868 .L442: + 6869 00ac 00000000 .word I2C_Master_ISR_IT + 6870 00b0 00200080 .word -2147475456 + 6871 .cfi_endproc + 6872 .LFE153: + 6874 .section .text.HAL_I2C_Master_Seq_Transmit_DMA,"ax",%progbits + 6875 .align 1 + 6876 .global HAL_I2C_Master_Seq_Transmit_DMA + 6877 .syntax unified + 6878 .thumb + 6879 .thumb_func + 6881 HAL_I2C_Master_Seq_Transmit_DMA: + 6882 .LVL444: + 6883 .LFB154: +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 6884 .loc 1 3344 1 is_stmt 1 view -0 + 6885 .cfi_startproc + 6886 @ args = 4, pretend = 0, frame = 0 + 6887 @ frame_needed = 0, uses_anonymous_args = 0 +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 6888 .loc 1 3344 1 is_stmt 0 view .LVU2393 + ARM GAS /tmp/ccE2rRGE.s page 280 + + + 6889 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 6890 .cfi_def_cfa_offset 24 + 6891 .cfi_offset 4, -24 + 6892 .cfi_offset 5, -20 + 6893 .cfi_offset 6, -16 + 6894 .cfi_offset 7, -12 + 6895 .cfi_offset 8, -8 + 6896 .cfi_offset 14, -4 + 6897 0004 82B0 sub sp, sp, #8 + 6898 .cfi_def_cfa_offset 32 + 6899 0006 0446 mov r4, r0 + 6900 0008 1546 mov r5, r2 + 6901 000a 089A ldr r2, [sp, #32] + 6902 .LVL445: +3345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 6903 .loc 1 3345 3 is_stmt 1 view .LVU2394 +3346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6904 .loc 1 3346 3 view .LVU2395 +3347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6905 .loc 1 3347 3 view .LVU2396 +3350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6906 .loc 1 3350 3 view .LVU2397 +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6907 .loc 1 3352 3 view .LVU2398 +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6908 .loc 1 3352 11 is_stmt 0 view .LVU2399 + 6909 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 6910 .LVL446: +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6911 .loc 1 3352 11 view .LVU2400 + 6912 0010 C0B2 uxtb r0, r0 +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6913 .loc 1 3352 6 view .LVU2401 + 6914 0012 2028 cmp r0, #32 + 6915 0014 40F09D80 bne .L455 + 6916 0018 0E46 mov r6, r1 +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6917 .loc 1 3355 5 is_stmt 1 view .LVU2402 +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6918 .loc 1 3355 5 view .LVU2403 + 6919 001a 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 6920 .LVL447: +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6921 .loc 1 3355 5 is_stmt 0 view .LVU2404 + 6922 001e 0129 cmp r1, #1 + 6923 0020 00F09B80 beq .L456 +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6924 .loc 1 3355 5 is_stmt 1 discriminator 2 view .LVU2405 + 6925 0024 0121 movs r1, #1 + 6926 0026 84F84010 strb r1, [r4, #64] +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6927 .loc 1 3355 5 discriminator 2 view .LVU2406 +3357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6928 .loc 1 3357 5 discriminator 2 view .LVU2407 +3357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6929 .loc 1 3357 21 is_stmt 0 discriminator 2 view .LVU2408 + 6930 002a 2121 movs r1, #33 + ARM GAS /tmp/ccE2rRGE.s page 281 + + + 6931 002c 84F84110 strb r1, [r4, #65] +3358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6932 .loc 1 3358 5 is_stmt 1 discriminator 2 view .LVU2409 +3358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6933 .loc 1 3358 21 is_stmt 0 discriminator 2 view .LVU2410 + 6934 0030 1021 movs r1, #16 + 6935 0032 84F84210 strb r1, [r4, #66] +3359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6936 .loc 1 3359 5 is_stmt 1 discriminator 2 view .LVU2411 +3359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6937 .loc 1 3359 21 is_stmt 0 discriminator 2 view .LVU2412 + 6938 0036 0021 movs r1, #0 + 6939 0038 6164 str r1, [r4, #68] +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6940 .loc 1 3362 5 is_stmt 1 discriminator 2 view .LVU2413 +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6941 .loc 1 3362 23 is_stmt 0 discriminator 2 view .LVU2414 + 6942 003a 6562 str r5, [r4, #36] +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6943 .loc 1 3363 5 is_stmt 1 discriminator 2 view .LVU2415 +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6944 .loc 1 3363 23 is_stmt 0 discriminator 2 view .LVU2416 + 6945 003c 6385 strh r3, [r4, #42] @ movhi +3364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6946 .loc 1 3364 5 is_stmt 1 discriminator 2 view .LVU2417 +3364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6947 .loc 1 3364 23 is_stmt 0 discriminator 2 view .LVU2418 + 6948 003e E262 str r2, [r4, #44] +3365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6949 .loc 1 3365 5 is_stmt 1 discriminator 2 view .LVU2419 +3365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6950 .loc 1 3365 23 is_stmt 0 discriminator 2 view .LVU2420 + 6951 0040 474B ldr r3, .L462 + 6952 .LVL448: +3365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6953 .loc 1 3365 23 discriminator 2 view .LVU2421 + 6954 0042 6363 str r3, [r4, #52] +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6955 .loc 1 3368 5 is_stmt 1 discriminator 2 view .LVU2422 +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6956 .loc 1 3368 13 is_stmt 0 discriminator 2 view .LVU2423 + 6957 0044 638D ldrh r3, [r4, #42] + 6958 0046 9BB2 uxth r3, r3 +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6959 .loc 1 3368 8 discriminator 2 view .LVU2424 + 6960 0048 FF2B cmp r3, #255 + 6961 004a 0ED9 bls .L446 +3370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6962 .loc 1 3370 7 is_stmt 1 view .LVU2425 +3370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6963 .loc 1 3370 22 is_stmt 0 view .LVU2426 + 6964 004c FF23 movs r3, #255 + 6965 004e 2385 strh r3, [r4, #40] @ movhi +3371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6966 .loc 1 3371 7 is_stmt 1 view .LVU2427 + 6967 .LVL449: +3371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 282 + + + 6968 .loc 1 3371 16 is_stmt 0 view .LVU2428 + 6969 0050 4FF08077 mov r7, #16777216 + 6970 .LVL450: + 6971 .L447: +3382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6972 .loc 1 3382 5 is_stmt 1 view .LVU2429 +3382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6973 .loc 1 3382 14 is_stmt 0 view .LVU2430 + 6974 0054 236B ldr r3, [r4, #48] +3382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6975 .loc 1 3382 8 view .LVU2431 + 6976 0056 112B cmp r3, #17 + 6977 0058 0BD1 bne .L448 +3383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6978 .loc 1 3383 10 view .LVU2432 + 6979 005a AA2A cmp r2, #170 + 6980 005c 09D0 beq .L448 +3383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6981 .loc 1 3383 10 discriminator 2 view .LVU2433 + 6982 005e B2F52A4F cmp r2, #43520 + 6983 0062 06D0 beq .L448 +3385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6984 .loc 1 3385 19 view .LVU2434 + 6985 0064 4FF00008 mov r8, #0 + 6986 0068 0DE0 b .L449 + 6987 .LVL451: + 6988 .L446: +3375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6989 .loc 1 3375 7 is_stmt 1 view .LVU2435 +3375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6990 .loc 1 3375 28 is_stmt 0 view .LVU2436 + 6991 006a 638D ldrh r3, [r4, #42] +3375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6992 .loc 1 3375 22 view .LVU2437 + 6993 006c 2385 strh r3, [r4, #40] @ movhi +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6994 .loc 1 3376 7 is_stmt 1 view .LVU2438 +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6995 .loc 1 3376 16 is_stmt 0 view .LVU2439 + 6996 006e E76A ldr r7, [r4, #44] + 6997 .LVL452: +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6998 .loc 1 3376 16 view .LVU2440 + 6999 0070 F0E7 b .L447 + 7000 .L448: +3390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7001 .loc 1 3390 7 is_stmt 1 view .LVU2441 + 7002 0072 2046 mov r0, r4 + 7003 0074 FFF7FEFF bl I2C_ConvertOtherXferOptions + 7004 .LVL453: +3393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7005 .loc 1 3393 7 view .LVU2442 +3393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7006 .loc 1 3393 15 is_stmt 0 view .LVU2443 + 7007 0078 638D ldrh r3, [r4, #42] + 7008 007a 9BB2 uxth r3, r3 +3393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 283 + + + 7009 .loc 1 3393 10 view .LVU2444 + 7010 007c FF2B cmp r3, #255 + 7011 007e 27D8 bhi .L458 +3395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7012 .loc 1 3395 9 is_stmt 1 view .LVU2445 +3395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7013 .loc 1 3395 18 is_stmt 0 view .LVU2446 + 7014 0080 E76A ldr r7, [r4, #44] + 7015 .LVL454: +3346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7016 .loc 1 3346 12 view .LVU2447 + 7017 0082 DFF8EC80 ldr r8, .L462+16 + 7018 .L449: + 7019 .LVL455: +3399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7020 .loc 1 3399 5 is_stmt 1 view .LVU2448 +3399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7021 .loc 1 3399 13 is_stmt 0 view .LVU2449 + 7022 0086 228D ldrh r2, [r4, #40] +3399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7023 .loc 1 3399 8 view .LVU2450 + 7024 0088 002A cmp r2, #0 + 7025 008a 4ED0 beq .L450 +3401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7026 .loc 1 3401 7 is_stmt 1 view .LVU2451 +3401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7027 .loc 1 3401 15 is_stmt 0 view .LVU2452 + 7028 008c A36B ldr r3, [r4, #56] +3401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7029 .loc 1 3401 10 view .LVU2453 + 7030 008e 13B3 cbz r3, .L451 +3404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7031 .loc 1 3404 9 is_stmt 1 view .LVU2454 +3404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7032 .loc 1 3404 40 is_stmt 0 view .LVU2455 + 7033 0090 344A ldr r2, .L462+4 + 7034 0092 9A62 str r2, [r3, #40] +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7035 .loc 1 3407 9 is_stmt 1 view .LVU2456 +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7036 .loc 1 3407 13 is_stmt 0 view .LVU2457 + 7037 0094 A36B ldr r3, [r4, #56] +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7038 .loc 1 3407 41 view .LVU2458 + 7039 0096 344A ldr r2, .L462+8 + 7040 0098 1A63 str r2, [r3, #48] +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7041 .loc 1 3410 9 is_stmt 1 view .LVU2459 +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7042 .loc 1 3410 13 is_stmt 0 view .LVU2460 + 7043 009a A26B ldr r2, [r4, #56] +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7044 .loc 1 3410 44 view .LVU2461 + 7045 009c 0023 movs r3, #0 + 7046 009e D362 str r3, [r2, #44] +3411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7047 .loc 1 3411 9 is_stmt 1 view .LVU2462 + ARM GAS /tmp/ccE2rRGE.s page 284 + + +3411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7048 .loc 1 3411 13 is_stmt 0 view .LVU2463 + 7049 00a0 A26B ldr r2, [r4, #56] +3411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7050 .loc 1 3411 41 view .LVU2464 + 7051 00a2 5363 str r3, [r2, #52] +3414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 7052 .loc 1 3414 9 is_stmt 1 view .LVU2465 +3414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 7053 .loc 1 3414 88 is_stmt 0 view .LVU2466 + 7054 00a4 2268 ldr r2, [r4] +3414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 7055 .loc 1 3414 25 view .LVU2467 + 7056 00a6 238D ldrh r3, [r4, #40] + 7057 00a8 2832 adds r2, r2, #40 + 7058 00aa 2946 mov r1, r5 + 7059 00ac A06B ldr r0, [r4, #56] + 7060 00ae FFF7FEFF bl HAL_DMA_Start_IT + 7061 .LVL456: +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7062 .loc 1 3432 7 is_stmt 1 view .LVU2468 +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7063 .loc 1 3432 10 is_stmt 0 view .LVU2469 + 7064 00b2 F0B1 cbz r0, .L461 +3455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7065 .loc 1 3455 9 is_stmt 1 view .LVU2470 +3455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7066 .loc 1 3455 25 is_stmt 0 view .LVU2471 + 7067 00b4 2023 movs r3, #32 + 7068 00b6 84F84130 strb r3, [r4, #65] +3456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7069 .loc 1 3456 9 is_stmt 1 view .LVU2472 +3456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7070 .loc 1 3456 25 is_stmt 0 view .LVU2473 + 7071 00ba 0022 movs r2, #0 + 7072 00bc 84F84220 strb r2, [r4, #66] +3459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7073 .loc 1 3459 9 is_stmt 1 view .LVU2474 +3459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7074 .loc 1 3459 13 is_stmt 0 view .LVU2475 + 7075 00c0 636C ldr r3, [r4, #68] +3459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7076 .loc 1 3459 25 view .LVU2476 + 7077 00c2 43F01003 orr r3, r3, #16 + 7078 00c6 6364 str r3, [r4, #68] +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7079 .loc 1 3462 9 is_stmt 1 view .LVU2477 +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7080 .loc 1 3462 9 view .LVU2478 + 7081 00c8 84F84020 strb r2, [r4, #64] +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7082 .loc 1 3462 9 view .LVU2479 +3464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7083 .loc 1 3464 9 view .LVU2480 +3464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7084 .loc 1 3464 16 is_stmt 0 view .LVU2481 + 7085 00cc 0120 movs r0, #1 + ARM GAS /tmp/ccE2rRGE.s page 285 + + + 7086 .LVL457: +3464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7087 .loc 1 3464 16 view .LVU2482 + 7088 00ce 41E0 b .L445 + 7089 .LVL458: + 7090 .L458: +3346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7091 .loc 1 3346 12 view .LVU2483 + 7092 00d0 DFF89C80 ldr r8, .L462+16 + 7093 00d4 D7E7 b .L449 + 7094 .LVL459: + 7095 .L451: +3420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7096 .loc 1 3420 9 is_stmt 1 view .LVU2484 +3420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7097 .loc 1 3420 25 is_stmt 0 view .LVU2485 + 7098 00d6 2023 movs r3, #32 + 7099 00d8 84F84130 strb r3, [r4, #65] +3421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7100 .loc 1 3421 9 is_stmt 1 view .LVU2486 +3421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7101 .loc 1 3421 25 is_stmt 0 view .LVU2487 + 7102 00dc 0022 movs r2, #0 + 7103 00de 84F84220 strb r2, [r4, #66] +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7104 .loc 1 3424 9 is_stmt 1 view .LVU2488 +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7105 .loc 1 3424 13 is_stmt 0 view .LVU2489 + 7106 00e2 636C ldr r3, [r4, #68] +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7107 .loc 1 3424 25 view .LVU2490 + 7108 00e4 43F08003 orr r3, r3, #128 + 7109 00e8 6364 str r3, [r4, #68] +3427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7110 .loc 1 3427 9 is_stmt 1 view .LVU2491 +3427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7111 .loc 1 3427 9 view .LVU2492 + 7112 00ea 84F84020 strb r2, [r4, #64] +3427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7113 .loc 1 3427 9 view .LVU2493 +3429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7114 .loc 1 3429 9 view .LVU2494 +3429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7115 .loc 1 3429 16 is_stmt 0 view .LVU2495 + 7116 00ee 0120 movs r0, #1 + 7117 00f0 30E0 b .L445 + 7118 .LVL460: + 7119 .L461: +3435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7120 .loc 1 3435 9 is_stmt 1 view .LVU2496 + 7121 00f2 CDF80080 str r8, [sp] + 7122 00f6 3B46 mov r3, r7 + 7123 00f8 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 7124 00fc 3146 mov r1, r6 + 7125 00fe 2046 mov r0, r4 + 7126 .LVL461: +3435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 286 + + + 7127 .loc 1 3435 9 is_stmt 0 view .LVU2497 + 7128 0100 FFF7FEFF bl I2C_TransferConfig + 7129 .LVL462: +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7130 .loc 1 3438 9 is_stmt 1 view .LVU2498 +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7131 .loc 1 3438 13 is_stmt 0 view .LVU2499 + 7132 0104 638D ldrh r3, [r4, #42] + 7133 0106 9BB2 uxth r3, r3 +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7134 .loc 1 3438 32 view .LVU2500 + 7135 0108 228D ldrh r2, [r4, #40] +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7136 .loc 1 3438 25 view .LVU2501 + 7137 010a 9B1A subs r3, r3, r2 + 7138 010c 9BB2 uxth r3, r3 + 7139 010e 6385 strh r3, [r4, #42] @ movhi +3441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7140 .loc 1 3441 9 is_stmt 1 view .LVU2502 +3441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7141 .loc 1 3441 9 view .LVU2503 + 7142 0110 0023 movs r3, #0 + 7143 0112 84F84030 strb r3, [r4, #64] +3441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7144 .loc 1 3441 9 view .LVU2504 +3447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7145 .loc 1 3447 9 view .LVU2505 + 7146 0116 1021 movs r1, #16 + 7147 0118 2046 mov r0, r4 + 7148 011a FFF7FEFF bl I2C_Enable_IRQ + 7149 .LVL463: +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7150 .loc 1 3450 9 view .LVU2506 +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7151 .loc 1 3450 13 is_stmt 0 view .LVU2507 + 7152 011e 2268 ldr r2, [r4] +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7153 .loc 1 3450 23 view .LVU2508 + 7154 0120 1368 ldr r3, [r2] +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7155 .loc 1 3450 29 view .LVU2509 + 7156 0122 43F48043 orr r3, r3, #16384 + 7157 0126 1360 str r3, [r2] + 7158 0128 11E0 b .L454 + 7159 .LVL464: + 7160 .L450: +3470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7161 .loc 1 3470 7 is_stmt 1 view .LVU2510 +3470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7162 .loc 1 3470 21 is_stmt 0 view .LVU2511 + 7163 012a 104B ldr r3, .L462+12 + 7164 012c 6363 str r3, [r4, #52] +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 7165 .loc 1 3474 7 is_stmt 1 view .LVU2512 + 7166 012e 104B ldr r3, .L462+16 + 7167 0130 0093 str r3, [sp] + 7168 0132 4FF00073 mov r3, #33554432 + ARM GAS /tmp/ccE2rRGE.s page 287 + + + 7169 0136 D2B2 uxtb r2, r2 + 7170 0138 3146 mov r1, r6 + 7171 013a 2046 mov r0, r4 + 7172 013c FFF7FEFF bl I2C_TransferConfig + 7173 .LVL465: +3478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7174 .loc 1 3478 7 view .LVU2513 +3478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7175 .loc 1 3478 7 view .LVU2514 + 7176 0140 0023 movs r3, #0 + 7177 0142 84F84030 strb r3, [r4, #64] +3478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7178 .loc 1 3478 7 view .LVU2515 +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7179 .loc 1 3487 7 view .LVU2516 + 7180 0146 0121 movs r1, #1 + 7181 0148 2046 mov r0, r4 + 7182 014a FFF7FEFF bl I2C_Enable_IRQ + 7183 .LVL466: + 7184 .L454: +3490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7185 .loc 1 3490 5 view .LVU2517 +3490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7186 .loc 1 3490 12 is_stmt 0 view .LVU2518 + 7187 014e 0020 movs r0, #0 + 7188 0150 00E0 b .L445 + 7189 .LVL467: + 7190 .L455: +3494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7191 .loc 1 3494 12 view .LVU2519 + 7192 0152 0220 movs r0, #2 + 7193 .LVL468: + 7194 .L445: +3496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7195 .loc 1 3496 1 view .LVU2520 + 7196 0154 02B0 add sp, sp, #8 + 7197 .cfi_remember_state + 7198 .cfi_def_cfa_offset 24 + 7199 @ sp needed + 7200 0156 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 7201 .LVL469: + 7202 .L456: + 7203 .cfi_restore_state +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7204 .loc 1 3355 5 view .LVU2521 + 7205 015a 0220 movs r0, #2 + 7206 015c FAE7 b .L445 + 7207 .L463: + 7208 015e 00BF .align 2 + 7209 .L462: + 7210 0160 00000000 .word I2C_Master_ISR_DMA + 7211 0164 00000000 .word I2C_DMAMasterTransmitCplt + 7212 0168 00000000 .word I2C_DMAError + 7213 016c 00000000 .word I2C_Master_ISR_IT + 7214 0170 00200080 .word -2147475456 + 7215 .cfi_endproc + 7216 .LFE154: + ARM GAS /tmp/ccE2rRGE.s page 288 + + + 7218 .section .text.HAL_I2C_Master_Seq_Receive_IT,"ax",%progbits + 7219 .align 1 + 7220 .global HAL_I2C_Master_Seq_Receive_IT + 7221 .syntax unified + 7222 .thumb + 7223 .thumb_func + 7225 HAL_I2C_Master_Seq_Receive_IT: + 7226 .LVL470: + 7227 .LFB155: +3512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 7228 .loc 1 3512 1 is_stmt 1 view -0 + 7229 .cfi_startproc + 7230 @ args = 4, pretend = 0, frame = 0 + 7231 @ frame_needed = 0, uses_anonymous_args = 0 +3512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 7232 .loc 1 3512 1 is_stmt 0 view .LVU2523 + 7233 0000 70B5 push {r4, r5, r6, lr} + 7234 .cfi_def_cfa_offset 16 + 7235 .cfi_offset 4, -16 + 7236 .cfi_offset 5, -12 + 7237 .cfi_offset 6, -8 + 7238 .cfi_offset 14, -4 + 7239 0002 82B0 sub sp, sp, #8 + 7240 .cfi_def_cfa_offset 24 + 7241 0004 0446 mov r4, r0 +3513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 7242 .loc 1 3513 3 is_stmt 1 view .LVU2524 +3514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7243 .loc 1 3514 3 view .LVU2525 + 7244 .LVL471: +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7245 .loc 1 3517 3 view .LVU2526 +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7246 .loc 1 3519 3 view .LVU2527 +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7247 .loc 1 3519 11 is_stmt 0 view .LVU2528 + 7248 0006 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7249 .LVL472: +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7250 .loc 1 3519 11 view .LVU2529 + 7251 000a C0B2 uxtb r0, r0 +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7252 .loc 1 3519 6 view .LVU2530 + 7253 000c 2028 cmp r0, #32 + 7254 000e 49D1 bne .L470 + 7255 0010 0D46 mov r5, r1 +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7256 .loc 1 3522 5 is_stmt 1 view .LVU2531 +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7257 .loc 1 3522 5 view .LVU2532 + 7258 0012 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 7259 .LVL473: +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7260 .loc 1 3522 5 is_stmt 0 view .LVU2533 + 7261 0016 0129 cmp r1, #1 + 7262 0018 46D0 beq .L471 +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 289 + + + 7263 .loc 1 3522 5 is_stmt 1 discriminator 2 view .LVU2534 + 7264 001a 0121 movs r1, #1 + 7265 001c 84F84010 strb r1, [r4, #64] +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7266 .loc 1 3522 5 discriminator 2 view .LVU2535 +3524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7267 .loc 1 3524 5 discriminator 2 view .LVU2536 +3524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7268 .loc 1 3524 21 is_stmt 0 discriminator 2 view .LVU2537 + 7269 0020 2221 movs r1, #34 + 7270 0022 84F84110 strb r1, [r4, #65] +3525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7271 .loc 1 3525 5 is_stmt 1 discriminator 2 view .LVU2538 +3525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7272 .loc 1 3525 21 is_stmt 0 discriminator 2 view .LVU2539 + 7273 0026 1021 movs r1, #16 + 7274 0028 84F84210 strb r1, [r4, #66] +3526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7275 .loc 1 3526 5 is_stmt 1 discriminator 2 view .LVU2540 +3526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7276 .loc 1 3526 21 is_stmt 0 discriminator 2 view .LVU2541 + 7277 002c 0021 movs r1, #0 + 7278 002e 6164 str r1, [r4, #68] +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7279 .loc 1 3529 5 is_stmt 1 discriminator 2 view .LVU2542 +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7280 .loc 1 3529 23 is_stmt 0 discriminator 2 view .LVU2543 + 7281 0030 6262 str r2, [r4, #36] +3530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7282 .loc 1 3530 5 is_stmt 1 discriminator 2 view .LVU2544 +3530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7283 .loc 1 3530 23 is_stmt 0 discriminator 2 view .LVU2545 + 7284 0032 6385 strh r3, [r4, #42] @ movhi +3531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7285 .loc 1 3531 5 is_stmt 1 discriminator 2 view .LVU2546 +3531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7286 .loc 1 3531 23 is_stmt 0 discriminator 2 view .LVU2547 + 7287 0034 069B ldr r3, [sp, #24] + 7288 .LVL474: +3531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7289 .loc 1 3531 23 discriminator 2 view .LVU2548 + 7290 0036 E362 str r3, [r4, #44] + 7291 .LVL475: +3532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7292 .loc 1 3532 5 is_stmt 1 discriminator 2 view .LVU2549 +3532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7293 .loc 1 3532 23 is_stmt 0 discriminator 2 view .LVU2550 + 7294 0038 1C4B ldr r3, .L475 + 7295 003a 6363 str r3, [r4, #52] +3535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7296 .loc 1 3535 5 is_stmt 1 discriminator 2 view .LVU2551 +3535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7297 .loc 1 3535 13 is_stmt 0 discriminator 2 view .LVU2552 + 7298 003c 638D ldrh r3, [r4, #42] + 7299 003e 9BB2 uxth r3, r3 +3535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7300 .loc 1 3535 8 discriminator 2 view .LVU2553 + ARM GAS /tmp/ccE2rRGE.s page 290 + + + 7301 0040 FF2B cmp r3, #255 + 7302 0042 0ED9 bls .L466 +3537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7303 .loc 1 3537 7 is_stmt 1 view .LVU2554 +3537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7304 .loc 1 3537 22 is_stmt 0 view .LVU2555 + 7305 0044 FF23 movs r3, #255 + 7306 0046 2385 strh r3, [r4, #40] @ movhi +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7307 .loc 1 3538 7 is_stmt 1 view .LVU2556 + 7308 .LVL476: +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7309 .loc 1 3538 16 is_stmt 0 view .LVU2557 + 7310 0048 4FF08076 mov r6, #16777216 + 7311 .LVL477: + 7312 .L467: +3549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7313 .loc 1 3549 5 is_stmt 1 view .LVU2558 +3549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7314 .loc 1 3549 14 is_stmt 0 view .LVU2559 + 7315 004c 236B ldr r3, [r4, #48] +3549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7316 .loc 1 3549 8 view .LVU2560 + 7317 004e 122B cmp r3, #18 + 7318 0050 0BD1 bne .L468 +3550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7319 .loc 1 3550 10 view .LVU2561 + 7320 0052 069B ldr r3, [sp, #24] + 7321 0054 AA2B cmp r3, #170 + 7322 0056 08D0 beq .L468 +3550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7323 .loc 1 3550 10 discriminator 2 view .LVU2562 + 7324 0058 B3F52A4F cmp r3, #43520 + 7325 005c 05D0 beq .L468 +3552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7326 .loc 1 3552 19 view .LVU2563 + 7327 005e 0023 movs r3, #0 + 7328 0060 0CE0 b .L469 + 7329 .LVL478: + 7330 .L466: +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7331 .loc 1 3542 7 is_stmt 1 view .LVU2564 +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7332 .loc 1 3542 28 is_stmt 0 view .LVU2565 + 7333 0062 638D ldrh r3, [r4, #42] +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7334 .loc 1 3542 22 view .LVU2566 + 7335 0064 2385 strh r3, [r4, #40] @ movhi +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7336 .loc 1 3543 7 is_stmt 1 view .LVU2567 +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7337 .loc 1 3543 16 is_stmt 0 view .LVU2568 + 7338 0066 E66A ldr r6, [r4, #44] + 7339 .LVL479: +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7340 .loc 1 3543 16 view .LVU2569 + 7341 0068 F0E7 b .L467 + ARM GAS /tmp/ccE2rRGE.s page 291 + + + 7342 .L468: +3557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7343 .loc 1 3557 7 is_stmt 1 view .LVU2570 + 7344 006a 2046 mov r0, r4 + 7345 006c FFF7FEFF bl I2C_ConvertOtherXferOptions + 7346 .LVL480: +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7347 .loc 1 3560 7 view .LVU2571 +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7348 .loc 1 3560 15 is_stmt 0 view .LVU2572 + 7349 0070 638D ldrh r3, [r4, #42] + 7350 0072 9BB2 uxth r3, r3 +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7351 .loc 1 3560 10 view .LVU2573 + 7352 0074 FF2B cmp r3, #255 + 7353 0076 13D8 bhi .L473 +3562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7354 .loc 1 3562 9 is_stmt 1 view .LVU2574 +3562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7355 .loc 1 3562 18 is_stmt 0 view .LVU2575 + 7356 0078 E66A ldr r6, [r4, #44] + 7357 .LVL481: +3514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7358 .loc 1 3514 12 view .LVU2576 + 7359 007a 0D4B ldr r3, .L475+4 + 7360 .L469: + 7361 .LVL482: +3567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7362 .loc 1 3567 5 is_stmt 1 view .LVU2577 + 7363 007c 0093 str r3, [sp] + 7364 007e 3346 mov r3, r6 + 7365 .LVL483: +3567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7366 .loc 1 3567 5 is_stmt 0 view .LVU2578 + 7367 0080 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 7368 0084 2946 mov r1, r5 + 7369 0086 2046 mov r0, r4 + 7370 0088 FFF7FEFF bl I2C_TransferConfig + 7371 .LVL484: +3570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7372 .loc 1 3570 5 is_stmt 1 view .LVU2579 +3570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7373 .loc 1 3570 5 view .LVU2580 + 7374 008c 0025 movs r5, #0 + 7375 008e 84F84050 strb r5, [r4, #64] +3570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7376 .loc 1 3570 5 view .LVU2581 +3575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7377 .loc 1 3575 5 view .LVU2582 + 7378 0092 0221 movs r1, #2 + 7379 0094 2046 mov r0, r4 + 7380 0096 FFF7FEFF bl I2C_Enable_IRQ + 7381 .LVL485: +3577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7382 .loc 1 3577 5 view .LVU2583 +3577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7383 .loc 1 3577 12 is_stmt 0 view .LVU2584 + ARM GAS /tmp/ccE2rRGE.s page 292 + + + 7384 009a 2846 mov r0, r5 + 7385 .LVL486: + 7386 .L465: +3583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7387 .loc 1 3583 1 view .LVU2585 + 7388 009c 02B0 add sp, sp, #8 + 7389 .cfi_remember_state + 7390 .cfi_def_cfa_offset 16 + 7391 @ sp needed + 7392 009e 70BD pop {r4, r5, r6, pc} + 7393 .LVL487: + 7394 .L473: + 7395 .cfi_restore_state +3514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7396 .loc 1 3514 12 view .LVU2586 + 7397 00a0 034B ldr r3, .L475+4 + 7398 00a2 EBE7 b .L469 + 7399 .LVL488: + 7400 .L470: +3581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7401 .loc 1 3581 12 view .LVU2587 + 7402 00a4 0220 movs r0, #2 + 7403 00a6 F9E7 b .L465 + 7404 .LVL489: + 7405 .L471: +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7406 .loc 1 3522 5 view .LVU2588 + 7407 00a8 0220 movs r0, #2 + 7408 00aa F7E7 b .L465 + 7409 .L476: + 7410 .align 2 + 7411 .L475: + 7412 00ac 00000000 .word I2C_Master_ISR_IT + 7413 00b0 00240080 .word -2147474432 + 7414 .cfi_endproc + 7415 .LFE155: + 7417 .section .text.HAL_I2C_Master_Seq_Receive_DMA,"ax",%progbits + 7418 .align 1 + 7419 .global HAL_I2C_Master_Seq_Receive_DMA + 7420 .syntax unified + 7421 .thumb + 7422 .thumb_func + 7424 HAL_I2C_Master_Seq_Receive_DMA: + 7425 .LVL490: + 7426 .LFB156: +3599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 7427 .loc 1 3599 1 is_stmt 1 view -0 + 7428 .cfi_startproc + 7429 @ args = 4, pretend = 0, frame = 0 + 7430 @ frame_needed = 0, uses_anonymous_args = 0 +3599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 7431 .loc 1 3599 1 is_stmt 0 view .LVU2590 + 7432 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 7433 .cfi_def_cfa_offset 24 + 7434 .cfi_offset 4, -24 + 7435 .cfi_offset 5, -20 + 7436 .cfi_offset 6, -16 + ARM GAS /tmp/ccE2rRGE.s page 293 + + + 7437 .cfi_offset 7, -12 + 7438 .cfi_offset 8, -8 + 7439 .cfi_offset 14, -4 + 7440 0004 82B0 sub sp, sp, #8 + 7441 .cfi_def_cfa_offset 32 + 7442 0006 0446 mov r4, r0 + 7443 0008 1546 mov r5, r2 + 7444 000a 089A ldr r2, [sp, #32] + 7445 .LVL491: +3600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 7446 .loc 1 3600 3 is_stmt 1 view .LVU2591 +3601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7447 .loc 1 3601 3 view .LVU2592 +3602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7448 .loc 1 3602 3 view .LVU2593 +3605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7449 .loc 1 3605 3 view .LVU2594 +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7450 .loc 1 3607 3 view .LVU2595 +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7451 .loc 1 3607 11 is_stmt 0 view .LVU2596 + 7452 000c 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7453 .LVL492: +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7454 .loc 1 3607 11 view .LVU2597 + 7455 0010 C0B2 uxtb r0, r0 +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7456 .loc 1 3607 6 view .LVU2598 + 7457 0012 2028 cmp r0, #32 + 7458 0014 40F09D80 bne .L488 + 7459 0018 0E46 mov r6, r1 +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7460 .loc 1 3610 5 is_stmt 1 view .LVU2599 +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7461 .loc 1 3610 5 view .LVU2600 + 7462 001a 94F84010 ldrb r1, [r4, #64] @ zero_extendqisi2 + 7463 .LVL493: +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7464 .loc 1 3610 5 is_stmt 0 view .LVU2601 + 7465 001e 0129 cmp r1, #1 + 7466 0020 00F09B80 beq .L489 +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7467 .loc 1 3610 5 is_stmt 1 discriminator 2 view .LVU2602 + 7468 0024 0121 movs r1, #1 + 7469 0026 84F84010 strb r1, [r4, #64] +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7470 .loc 1 3610 5 discriminator 2 view .LVU2603 +3612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7471 .loc 1 3612 5 discriminator 2 view .LVU2604 +3612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7472 .loc 1 3612 21 is_stmt 0 discriminator 2 view .LVU2605 + 7473 002a 2221 movs r1, #34 + 7474 002c 84F84110 strb r1, [r4, #65] +3613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7475 .loc 1 3613 5 is_stmt 1 discriminator 2 view .LVU2606 +3613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7476 .loc 1 3613 21 is_stmt 0 discriminator 2 view .LVU2607 + ARM GAS /tmp/ccE2rRGE.s page 294 + + + 7477 0030 1021 movs r1, #16 + 7478 0032 84F84210 strb r1, [r4, #66] +3614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7479 .loc 1 3614 5 is_stmt 1 discriminator 2 view .LVU2608 +3614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7480 .loc 1 3614 21 is_stmt 0 discriminator 2 view .LVU2609 + 7481 0036 0021 movs r1, #0 + 7482 0038 6164 str r1, [r4, #68] +3617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7483 .loc 1 3617 5 is_stmt 1 discriminator 2 view .LVU2610 +3617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7484 .loc 1 3617 23 is_stmt 0 discriminator 2 view .LVU2611 + 7485 003a 6562 str r5, [r4, #36] +3618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7486 .loc 1 3618 5 is_stmt 1 discriminator 2 view .LVU2612 +3618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7487 .loc 1 3618 23 is_stmt 0 discriminator 2 view .LVU2613 + 7488 003c 6385 strh r3, [r4, #42] @ movhi +3619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7489 .loc 1 3619 5 is_stmt 1 discriminator 2 view .LVU2614 +3619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7490 .loc 1 3619 23 is_stmt 0 discriminator 2 view .LVU2615 + 7491 003e E262 str r2, [r4, #44] +3620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7492 .loc 1 3620 5 is_stmt 1 discriminator 2 view .LVU2616 +3620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7493 .loc 1 3620 23 is_stmt 0 discriminator 2 view .LVU2617 + 7494 0040 474B ldr r3, .L495 + 7495 .LVL494: +3620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7496 .loc 1 3620 23 discriminator 2 view .LVU2618 + 7497 0042 6363 str r3, [r4, #52] +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7498 .loc 1 3623 5 is_stmt 1 discriminator 2 view .LVU2619 +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7499 .loc 1 3623 13 is_stmt 0 discriminator 2 view .LVU2620 + 7500 0044 638D ldrh r3, [r4, #42] + 7501 0046 9BB2 uxth r3, r3 +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7502 .loc 1 3623 8 discriminator 2 view .LVU2621 + 7503 0048 FF2B cmp r3, #255 + 7504 004a 0ED9 bls .L479 +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7505 .loc 1 3625 7 is_stmt 1 view .LVU2622 +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7506 .loc 1 3625 22 is_stmt 0 view .LVU2623 + 7507 004c FF23 movs r3, #255 + 7508 004e 2385 strh r3, [r4, #40] @ movhi +3626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7509 .loc 1 3626 7 is_stmt 1 view .LVU2624 + 7510 .LVL495: +3626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7511 .loc 1 3626 16 is_stmt 0 view .LVU2625 + 7512 0050 4FF08077 mov r7, #16777216 + 7513 .LVL496: + 7514 .L480: +3637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + ARM GAS /tmp/ccE2rRGE.s page 295 + + + 7515 .loc 1 3637 5 is_stmt 1 view .LVU2626 +3637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7516 .loc 1 3637 14 is_stmt 0 view .LVU2627 + 7517 0054 236B ldr r3, [r4, #48] +3637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7518 .loc 1 3637 8 view .LVU2628 + 7519 0056 122B cmp r3, #18 + 7520 0058 0BD1 bne .L481 +3638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7521 .loc 1 3638 10 view .LVU2629 + 7522 005a AA2A cmp r2, #170 + 7523 005c 09D0 beq .L481 +3638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7524 .loc 1 3638 10 discriminator 2 view .LVU2630 + 7525 005e B2F52A4F cmp r2, #43520 + 7526 0062 06D0 beq .L481 +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7527 .loc 1 3640 19 view .LVU2631 + 7528 0064 4FF00008 mov r8, #0 + 7529 0068 0DE0 b .L482 + 7530 .LVL497: + 7531 .L479: +3630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7532 .loc 1 3630 7 is_stmt 1 view .LVU2632 +3630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7533 .loc 1 3630 28 is_stmt 0 view .LVU2633 + 7534 006a 638D ldrh r3, [r4, #42] +3630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7535 .loc 1 3630 22 view .LVU2634 + 7536 006c 2385 strh r3, [r4, #40] @ movhi +3631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7537 .loc 1 3631 7 is_stmt 1 view .LVU2635 +3631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7538 .loc 1 3631 16 is_stmt 0 view .LVU2636 + 7539 006e E76A ldr r7, [r4, #44] + 7540 .LVL498: +3631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7541 .loc 1 3631 16 view .LVU2637 + 7542 0070 F0E7 b .L480 + 7543 .L481: +3645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7544 .loc 1 3645 7 is_stmt 1 view .LVU2638 + 7545 0072 2046 mov r0, r4 + 7546 0074 FFF7FEFF bl I2C_ConvertOtherXferOptions + 7547 .LVL499: +3648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7548 .loc 1 3648 7 view .LVU2639 +3648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7549 .loc 1 3648 15 is_stmt 0 view .LVU2640 + 7550 0078 638D ldrh r3, [r4, #42] + 7551 007a 9BB2 uxth r3, r3 +3648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7552 .loc 1 3648 10 view .LVU2641 + 7553 007c FF2B cmp r3, #255 + 7554 007e 27D8 bhi .L491 +3650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7555 .loc 1 3650 9 is_stmt 1 view .LVU2642 + ARM GAS /tmp/ccE2rRGE.s page 296 + + +3650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7556 .loc 1 3650 18 is_stmt 0 view .LVU2643 + 7557 0080 E76A ldr r7, [r4, #44] + 7558 .LVL500: +3601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7559 .loc 1 3601 12 view .LVU2644 + 7560 0082 DFF8EC80 ldr r8, .L495+16 + 7561 .L482: + 7562 .LVL501: +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7563 .loc 1 3654 5 is_stmt 1 view .LVU2645 +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7564 .loc 1 3654 13 is_stmt 0 view .LVU2646 + 7565 0086 228D ldrh r2, [r4, #40] +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7566 .loc 1 3654 8 view .LVU2647 + 7567 0088 002A cmp r2, #0 + 7568 008a 4ED0 beq .L483 +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7569 .loc 1 3656 7 is_stmt 1 view .LVU2648 +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7570 .loc 1 3656 15 is_stmt 0 view .LVU2649 + 7571 008c E36B ldr r3, [r4, #60] +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7572 .loc 1 3656 10 view .LVU2650 + 7573 008e 13B3 cbz r3, .L484 +3659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7574 .loc 1 3659 9 is_stmt 1 view .LVU2651 +3659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7575 .loc 1 3659 40 is_stmt 0 view .LVU2652 + 7576 0090 344A ldr r2, .L495+4 + 7577 0092 9A62 str r2, [r3, #40] +3662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7578 .loc 1 3662 9 is_stmt 1 view .LVU2653 +3662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7579 .loc 1 3662 13 is_stmt 0 view .LVU2654 + 7580 0094 E36B ldr r3, [r4, #60] +3662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7581 .loc 1 3662 41 view .LVU2655 + 7582 0096 344A ldr r2, .L495+8 + 7583 0098 1A63 str r2, [r3, #48] +3665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 7584 .loc 1 3665 9 is_stmt 1 view .LVU2656 +3665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 7585 .loc 1 3665 13 is_stmt 0 view .LVU2657 + 7586 009a E26B ldr r2, [r4, #60] +3665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 7587 .loc 1 3665 44 view .LVU2658 + 7588 009c 0023 movs r3, #0 + 7589 009e D362 str r3, [r2, #44] +3666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7590 .loc 1 3666 9 is_stmt 1 view .LVU2659 +3666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7591 .loc 1 3666 13 is_stmt 0 view .LVU2660 + 7592 00a0 E26B ldr r2, [r4, #60] +3666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7593 .loc 1 3666 41 view .LVU2661 + ARM GAS /tmp/ccE2rRGE.s page 297 + + + 7594 00a2 5363 str r3, [r2, #52] +3669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 7595 .loc 1 3669 9 is_stmt 1 view .LVU2662 +3669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 7596 .loc 1 3669 71 is_stmt 0 view .LVU2663 + 7597 00a4 2168 ldr r1, [r4] +3669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 7598 .loc 1 3669 25 view .LVU2664 + 7599 00a6 238D ldrh r3, [r4, #40] + 7600 00a8 2A46 mov r2, r5 + 7601 00aa 2431 adds r1, r1, #36 + 7602 00ac E06B ldr r0, [r4, #60] + 7603 00ae FFF7FEFF bl HAL_DMA_Start_IT + 7604 .LVL502: +3687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7605 .loc 1 3687 7 is_stmt 1 view .LVU2665 +3687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7606 .loc 1 3687 10 is_stmt 0 view .LVU2666 + 7607 00b2 F0B1 cbz r0, .L494 +3710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7608 .loc 1 3710 9 is_stmt 1 view .LVU2667 +3710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7609 .loc 1 3710 25 is_stmt 0 view .LVU2668 + 7610 00b4 2023 movs r3, #32 + 7611 00b6 84F84130 strb r3, [r4, #65] +3711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7612 .loc 1 3711 9 is_stmt 1 view .LVU2669 +3711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7613 .loc 1 3711 25 is_stmt 0 view .LVU2670 + 7614 00ba 0022 movs r2, #0 + 7615 00bc 84F84220 strb r2, [r4, #66] +3714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7616 .loc 1 3714 9 is_stmt 1 view .LVU2671 +3714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7617 .loc 1 3714 13 is_stmt 0 view .LVU2672 + 7618 00c0 636C ldr r3, [r4, #68] +3714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7619 .loc 1 3714 25 view .LVU2673 + 7620 00c2 43F01003 orr r3, r3, #16 + 7621 00c6 6364 str r3, [r4, #68] +3717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7622 .loc 1 3717 9 is_stmt 1 view .LVU2674 +3717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7623 .loc 1 3717 9 view .LVU2675 + 7624 00c8 84F84020 strb r2, [r4, #64] +3717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7625 .loc 1 3717 9 view .LVU2676 +3719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7626 .loc 1 3719 9 view .LVU2677 +3719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7627 .loc 1 3719 16 is_stmt 0 view .LVU2678 + 7628 00cc 0120 movs r0, #1 + 7629 .LVL503: +3719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7630 .loc 1 3719 16 view .LVU2679 + 7631 00ce 41E0 b .L478 + 7632 .LVL504: + ARM GAS /tmp/ccE2rRGE.s page 298 + + + 7633 .L491: +3601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7634 .loc 1 3601 12 view .LVU2680 + 7635 00d0 DFF89C80 ldr r8, .L495+16 + 7636 00d4 D7E7 b .L482 + 7637 .LVL505: + 7638 .L484: +3675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7639 .loc 1 3675 9 is_stmt 1 view .LVU2681 +3675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7640 .loc 1 3675 25 is_stmt 0 view .LVU2682 + 7641 00d6 2023 movs r3, #32 + 7642 00d8 84F84130 strb r3, [r4, #65] +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7643 .loc 1 3676 9 is_stmt 1 view .LVU2683 +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7644 .loc 1 3676 25 is_stmt 0 view .LVU2684 + 7645 00dc 0022 movs r2, #0 + 7646 00de 84F84220 strb r2, [r4, #66] +3679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7647 .loc 1 3679 9 is_stmt 1 view .LVU2685 +3679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7648 .loc 1 3679 13 is_stmt 0 view .LVU2686 + 7649 00e2 636C ldr r3, [r4, #68] +3679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7650 .loc 1 3679 25 view .LVU2687 + 7651 00e4 43F08003 orr r3, r3, #128 + 7652 00e8 6364 str r3, [r4, #68] +3682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7653 .loc 1 3682 9 is_stmt 1 view .LVU2688 +3682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7654 .loc 1 3682 9 view .LVU2689 + 7655 00ea 84F84020 strb r2, [r4, #64] +3682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7656 .loc 1 3682 9 view .LVU2690 +3684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7657 .loc 1 3684 9 view .LVU2691 +3684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7658 .loc 1 3684 16 is_stmt 0 view .LVU2692 + 7659 00ee 0120 movs r0, #1 + 7660 00f0 30E0 b .L478 + 7661 .LVL506: + 7662 .L494: +3690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7663 .loc 1 3690 9 is_stmt 1 view .LVU2693 + 7664 00f2 CDF80080 str r8, [sp] + 7665 00f6 3B46 mov r3, r7 + 7666 00f8 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 7667 00fc 3146 mov r1, r6 + 7668 00fe 2046 mov r0, r4 + 7669 .LVL507: +3690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7670 .loc 1 3690 9 is_stmt 0 view .LVU2694 + 7671 0100 FFF7FEFF bl I2C_TransferConfig + 7672 .LVL508: +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7673 .loc 1 3693 9 is_stmt 1 view .LVU2695 + ARM GAS /tmp/ccE2rRGE.s page 299 + + +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7674 .loc 1 3693 13 is_stmt 0 view .LVU2696 + 7675 0104 638D ldrh r3, [r4, #42] + 7676 0106 9BB2 uxth r3, r3 +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7677 .loc 1 3693 32 view .LVU2697 + 7678 0108 228D ldrh r2, [r4, #40] +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7679 .loc 1 3693 25 view .LVU2698 + 7680 010a 9B1A subs r3, r3, r2 + 7681 010c 9BB2 uxth r3, r3 + 7682 010e 6385 strh r3, [r4, #42] @ movhi +3696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7683 .loc 1 3696 9 is_stmt 1 view .LVU2699 +3696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7684 .loc 1 3696 9 view .LVU2700 + 7685 0110 0023 movs r3, #0 + 7686 0112 84F84030 strb r3, [r4, #64] +3696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7687 .loc 1 3696 9 view .LVU2701 +3702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7688 .loc 1 3702 9 view .LVU2702 + 7689 0116 1021 movs r1, #16 + 7690 0118 2046 mov r0, r4 + 7691 011a FFF7FEFF bl I2C_Enable_IRQ + 7692 .LVL509: +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7693 .loc 1 3705 9 view .LVU2703 +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7694 .loc 1 3705 13 is_stmt 0 view .LVU2704 + 7695 011e 2268 ldr r2, [r4] +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7696 .loc 1 3705 23 view .LVU2705 + 7697 0120 1368 ldr r3, [r2] +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7698 .loc 1 3705 29 view .LVU2706 + 7699 0122 43F40043 orr r3, r3, #32768 + 7700 0126 1360 str r3, [r2] + 7701 0128 11E0 b .L487 + 7702 .LVL510: + 7703 .L483: +3725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7704 .loc 1 3725 7 is_stmt 1 view .LVU2707 +3725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7705 .loc 1 3725 21 is_stmt 0 view .LVU2708 + 7706 012a 104B ldr r3, .L495+12 + 7707 012c 6363 str r3, [r4, #52] +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 7708 .loc 1 3729 7 is_stmt 1 view .LVU2709 + 7709 012e 104B ldr r3, .L495+16 + 7710 0130 0093 str r3, [sp] + 7711 0132 4FF00073 mov r3, #33554432 + 7712 0136 D2B2 uxtb r2, r2 + 7713 0138 3146 mov r1, r6 + 7714 013a 2046 mov r0, r4 + 7715 013c FFF7FEFF bl I2C_TransferConfig + 7716 .LVL511: + ARM GAS /tmp/ccE2rRGE.s page 300 + + +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7717 .loc 1 3733 7 view .LVU2710 +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7718 .loc 1 3733 7 view .LVU2711 + 7719 0140 0023 movs r3, #0 + 7720 0142 84F84030 strb r3, [r4, #64] +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7721 .loc 1 3733 7 view .LVU2712 +3742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7722 .loc 1 3742 7 view .LVU2713 + 7723 0146 0121 movs r1, #1 + 7724 0148 2046 mov r0, r4 + 7725 014a FFF7FEFF bl I2C_Enable_IRQ + 7726 .LVL512: + 7727 .L487: +3745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7728 .loc 1 3745 5 view .LVU2714 +3745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7729 .loc 1 3745 12 is_stmt 0 view .LVU2715 + 7730 014e 0020 movs r0, #0 + 7731 0150 00E0 b .L478 + 7732 .LVL513: + 7733 .L488: +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7734 .loc 1 3749 12 view .LVU2716 + 7735 0152 0220 movs r0, #2 + 7736 .LVL514: + 7737 .L478: +3751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7738 .loc 1 3751 1 view .LVU2717 + 7739 0154 02B0 add sp, sp, #8 + 7740 .cfi_remember_state + 7741 .cfi_def_cfa_offset 24 + 7742 @ sp needed + 7743 0156 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 7744 .LVL515: + 7745 .L489: + 7746 .cfi_restore_state +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7747 .loc 1 3610 5 view .LVU2718 + 7748 015a 0220 movs r0, #2 + 7749 015c FAE7 b .L478 + 7750 .L496: + 7751 015e 00BF .align 2 + 7752 .L495: + 7753 0160 00000000 .word I2C_Master_ISR_DMA + 7754 0164 00000000 .word I2C_DMAMasterReceiveCplt + 7755 0168 00000000 .word I2C_DMAError + 7756 016c 00000000 .word I2C_Master_ISR_IT + 7757 0170 00240080 .word -2147474432 + 7758 .cfi_endproc + 7759 .LFE156: + 7761 .section .text.HAL_I2C_Slave_Seq_Transmit_IT,"ax",%progbits + 7762 .align 1 + 7763 .global HAL_I2C_Slave_Seq_Transmit_IT + 7764 .syntax unified + 7765 .thumb + ARM GAS /tmp/ccE2rRGE.s page 301 + + + 7766 .thumb_func + 7768 HAL_I2C_Slave_Seq_Transmit_IT: + 7769 .LVL516: + 7770 .LFB157: +3765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + 7771 .loc 1 3765 1 is_stmt 1 view -0 + 7772 .cfi_startproc + 7773 @ args = 0, pretend = 0, frame = 0 + 7774 @ frame_needed = 0, uses_anonymous_args = 0 +3765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + 7775 .loc 1 3765 1 is_stmt 0 view .LVU2720 + 7776 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 7777 .cfi_def_cfa_offset 24 + 7778 .cfi_offset 3, -24 + 7779 .cfi_offset 4, -20 + 7780 .cfi_offset 5, -16 + 7781 .cfi_offset 6, -12 + 7782 .cfi_offset 7, -8 + 7783 .cfi_offset 14, -4 + 7784 0002 0446 mov r4, r0 +3767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7785 .loc 1 3767 3 is_stmt 1 view .LVU2721 +3769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7786 .loc 1 3769 3 view .LVU2722 +3769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7787 .loc 1 3769 22 is_stmt 0 view .LVU2723 + 7788 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 7789 .LVL517: +3769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7790 .loc 1 3769 6 view .LVU2724 + 7791 0008 00F02800 and r0, r0, #40 + 7792 000c 2828 cmp r0, #40 + 7793 000e 5AD1 bne .L503 + 7794 0010 0F46 mov r7, r1 + 7795 0012 1646 mov r6, r2 + 7796 0014 1D46 mov r5, r3 +3771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7797 .loc 1 3771 5 is_stmt 1 view .LVU2725 +3771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7798 .loc 1 3771 8 is_stmt 0 view .LVU2726 + 7799 0016 01B1 cbz r1, .L499 +3771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7800 .loc 1 3771 25 discriminator 1 view .LVU2727 + 7801 0018 22B9 cbnz r2, .L500 + 7802 .L499: +3773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7803 .loc 1 3773 7 is_stmt 1 view .LVU2728 +3773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7804 .loc 1 3773 23 is_stmt 0 view .LVU2729 + 7805 001a 4FF40073 mov r3, #512 + 7806 .LVL518: +3773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7807 .loc 1 3773 23 view .LVU2730 + 7808 001e 6364 str r3, [r4, #68] +3774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7809 .loc 1 3774 7 is_stmt 1 view .LVU2731 +3774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 302 + + + 7810 .loc 1 3774 15 is_stmt 0 view .LVU2732 + 7811 0020 0120 movs r0, #1 + 7812 0022 51E0 b .L498 + 7813 .LVL519: + 7814 .L500: +3778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7815 .loc 1 3778 5 is_stmt 1 view .LVU2733 + 7816 0024 48F20101 movw r1, #32769 + 7817 .LVL520: +3778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7818 .loc 1 3778 5 is_stmt 0 view .LVU2734 + 7819 0028 2046 mov r0, r4 + 7820 002a FFF7FEFF bl I2C_Disable_IRQ + 7821 .LVL521: +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7822 .loc 1 3781 5 is_stmt 1 view .LVU2735 +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7823 .loc 1 3781 5 view .LVU2736 + 7824 002e 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 7825 0032 012B cmp r3, #1 + 7826 0034 49D0 beq .L504 +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7827 .loc 1 3781 5 discriminator 2 view .LVU2737 + 7828 0036 0123 movs r3, #1 + 7829 0038 84F84030 strb r3, [r4, #64] +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7830 .loc 1 3781 5 discriminator 2 view .LVU2738 +3785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7831 .loc 1 3785 5 discriminator 2 view .LVU2739 +3785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7832 .loc 1 3785 13 is_stmt 0 discriminator 2 view .LVU2740 + 7833 003c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 7834 0040 DBB2 uxtb r3, r3 +3785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7835 .loc 1 3785 8 discriminator 2 view .LVU2741 + 7836 0042 2A2B cmp r3, #42 + 7837 0044 24D0 beq .L506 + 7838 .L501: +3811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7839 .loc 1 3811 5 is_stmt 1 view .LVU2742 +3811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7840 .loc 1 3811 21 is_stmt 0 view .LVU2743 + 7841 0046 2923 movs r3, #41 + 7842 0048 84F84130 strb r3, [r4, #65] +3812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7843 .loc 1 3812 5 is_stmt 1 view .LVU2744 +3812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7844 .loc 1 3812 21 is_stmt 0 view .LVU2745 + 7845 004c 2023 movs r3, #32 + 7846 004e 84F84230 strb r3, [r4, #66] +3813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7847 .loc 1 3813 5 is_stmt 1 view .LVU2746 +3813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7848 .loc 1 3813 21 is_stmt 0 view .LVU2747 + 7849 0052 0023 movs r3, #0 + 7850 0054 6364 str r3, [r4, #68] +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 303 + + + 7851 .loc 1 3816 5 is_stmt 1 view .LVU2748 +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7852 .loc 1 3816 9 is_stmt 0 view .LVU2749 + 7853 0056 2268 ldr r2, [r4] +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7854 .loc 1 3816 19 view .LVU2750 + 7855 0058 5368 ldr r3, [r2, #4] +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7856 .loc 1 3816 25 view .LVU2751 + 7857 005a 23F40043 bic r3, r3, #32768 + 7858 005e 5360 str r3, [r2, #4] +3819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7859 .loc 1 3819 5 is_stmt 1 view .LVU2752 +3819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7860 .loc 1 3819 23 is_stmt 0 view .LVU2753 + 7861 0060 6762 str r7, [r4, #36] +3820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7862 .loc 1 3820 5 is_stmt 1 view .LVU2754 +3820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7863 .loc 1 3820 23 is_stmt 0 view .LVU2755 + 7864 0062 6685 strh r6, [r4, #42] @ movhi +3821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7865 .loc 1 3821 5 is_stmt 1 view .LVU2756 +3821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7866 .loc 1 3821 29 is_stmt 0 view .LVU2757 + 7867 0064 638D ldrh r3, [r4, #42] +3821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7868 .loc 1 3821 23 view .LVU2758 + 7869 0066 2385 strh r3, [r4, #40] @ movhi +3822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 7870 .loc 1 3822 5 is_stmt 1 view .LVU2759 +3822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 7871 .loc 1 3822 23 is_stmt 0 view .LVU2760 + 7872 0068 E562 str r5, [r4, #44] +3823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7873 .loc 1 3823 5 is_stmt 1 view .LVU2761 +3823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7874 .loc 1 3823 23 is_stmt 0 view .LVU2762 + 7875 006a 194B ldr r3, .L507 + 7876 006c 6363 str r3, [r4, #52] +3825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7877 .loc 1 3825 5 is_stmt 1 view .LVU2763 +3825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7878 .loc 1 3825 9 is_stmt 0 view .LVU2764 + 7879 006e 2368 ldr r3, [r4] + 7880 0070 9A69 ldr r2, [r3, #24] +3825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7881 .loc 1 3825 8 view .LVU2765 + 7882 0072 12F4803F tst r2, #65536 + 7883 0076 01D0 beq .L502 +3829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7884 .loc 1 3829 7 is_stmt 1 view .LVU2766 + 7885 0078 0822 movs r2, #8 + 7886 007a DA61 str r2, [r3, #28] + 7887 .L502: +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7888 .loc 1 3833 5 view .LVU2767 + ARM GAS /tmp/ccE2rRGE.s page 304 + + +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7889 .loc 1 3833 5 view .LVU2768 + 7890 007c 0025 movs r5, #0 + 7891 .LVL522: +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7892 .loc 1 3833 5 is_stmt 0 view .LVU2769 + 7893 007e 84F84050 strb r5, [r4, #64] +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7894 .loc 1 3833 5 is_stmt 1 view .LVU2770 +3839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7895 .loc 1 3839 5 view .LVU2771 + 7896 0082 48F20101 movw r1, #32769 + 7897 0086 2046 mov r0, r4 + 7898 0088 FFF7FEFF bl I2C_Enable_IRQ + 7899 .LVL523: +3841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7900 .loc 1 3841 5 view .LVU2772 +3841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7901 .loc 1 3841 12 is_stmt 0 view .LVU2773 + 7902 008c 2846 mov r0, r5 + 7903 008e 1BE0 b .L498 + 7904 .LVL524: + 7905 .L506: +3788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7906 .loc 1 3788 7 is_stmt 1 view .LVU2774 + 7907 0090 0221 movs r1, #2 + 7908 0092 2046 mov r0, r4 + 7909 0094 FFF7FEFF bl I2C_Disable_IRQ + 7910 .LVL525: +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7911 .loc 1 3791 7 view .LVU2775 +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7912 .loc 1 3791 16 is_stmt 0 view .LVU2776 + 7913 0098 2368 ldr r3, [r4] +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7914 .loc 1 3791 26 view .LVU2777 + 7915 009a 1A68 ldr r2, [r3] +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7916 .loc 1 3791 10 view .LVU2778 + 7917 009c 12F4004F tst r2, #32768 + 7918 00a0 D1D0 beq .L501 +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7919 .loc 1 3793 9 is_stmt 1 view .LVU2779 +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7920 .loc 1 3793 23 is_stmt 0 view .LVU2780 + 7921 00a2 1A68 ldr r2, [r3] +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7922 .loc 1 3793 29 view .LVU2781 + 7923 00a4 22F40042 bic r2, r2, #32768 + 7924 00a8 1A60 str r2, [r3] +3795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7925 .loc 1 3795 9 is_stmt 1 view .LVU2782 +3795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7926 .loc 1 3795 17 is_stmt 0 view .LVU2783 + 7927 00aa E36B ldr r3, [r4, #60] +3795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7928 .loc 1 3795 12 view .LVU2784 + ARM GAS /tmp/ccE2rRGE.s page 305 + + + 7929 00ac 002B cmp r3, #0 + 7930 00ae CAD0 beq .L501 +3799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7931 .loc 1 3799 11 is_stmt 1 view .LVU2785 +3799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7932 .loc 1 3799 43 is_stmt 0 view .LVU2786 + 7933 00b0 084A ldr r2, .L507+4 + 7934 00b2 5A63 str r2, [r3, #52] +3802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7935 .loc 1 3802 11 is_stmt 1 view .LVU2787 +3802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7936 .loc 1 3802 15 is_stmt 0 view .LVU2788 + 7937 00b4 E06B ldr r0, [r4, #60] + 7938 00b6 FFF7FEFF bl HAL_DMA_Abort_IT + 7939 .LVL526: +3802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7940 .loc 1 3802 14 view .LVU2789 + 7941 00ba 0028 cmp r0, #0 + 7942 00bc C3D0 beq .L501 +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7943 .loc 1 3805 13 is_stmt 1 view .LVU2790 +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7944 .loc 1 3805 17 is_stmt 0 view .LVU2791 + 7945 00be E06B ldr r0, [r4, #60] +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7946 .loc 1 3805 25 view .LVU2792 + 7947 00c0 436B ldr r3, [r0, #52] +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7948 .loc 1 3805 13 view .LVU2793 + 7949 00c2 9847 blx r3 + 7950 .LVL527: + 7951 00c4 BFE7 b .L501 + 7952 .LVL528: + 7953 .L503: +3845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7954 .loc 1 3845 12 view .LVU2794 + 7955 00c6 0120 movs r0, #1 + 7956 .LVL529: + 7957 .L498: +3847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7958 .loc 1 3847 1 view .LVU2795 + 7959 00c8 F8BD pop {r3, r4, r5, r6, r7, pc} + 7960 .LVL530: + 7961 .L504: +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7962 .loc 1 3781 5 view .LVU2796 + 7963 00ca 0220 movs r0, #2 + 7964 00cc FCE7 b .L498 + 7965 .L508: + 7966 00ce 00BF .align 2 + 7967 .L507: + 7968 00d0 00000000 .word I2C_Slave_ISR_IT + 7969 00d4 00000000 .word I2C_DMAAbort + 7970 .cfi_endproc + 7971 .LFE157: + 7973 .section .text.HAL_I2C_Slave_Seq_Transmit_DMA,"ax",%progbits + 7974 .align 1 + ARM GAS /tmp/ccE2rRGE.s page 306 + + + 7975 .global HAL_I2C_Slave_Seq_Transmit_DMA + 7976 .syntax unified + 7977 .thumb + 7978 .thumb_func + 7980 HAL_I2C_Slave_Seq_Transmit_DMA: + 7981 .LVL531: + 7982 .LFB158: +3861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7983 .loc 1 3861 1 is_stmt 1 view -0 + 7984 .cfi_startproc + 7985 @ args = 0, pretend = 0, frame = 0 + 7986 @ frame_needed = 0, uses_anonymous_args = 0 +3861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7987 .loc 1 3861 1 is_stmt 0 view .LVU2798 + 7988 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 7989 .cfi_def_cfa_offset 24 + 7990 .cfi_offset 3, -24 + 7991 .cfi_offset 4, -20 + 7992 .cfi_offset 5, -16 + 7993 .cfi_offset 6, -12 + 7994 .cfi_offset 7, -8 + 7995 .cfi_offset 14, -4 + 7996 0002 0446 mov r4, r0 +3862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7997 .loc 1 3862 3 is_stmt 1 view .LVU2799 +3865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7998 .loc 1 3865 3 view .LVU2800 +3867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7999 .loc 1 3867 3 view .LVU2801 +3867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8000 .loc 1 3867 22 is_stmt 0 view .LVU2802 + 8001 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8002 .LVL532: +3867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8003 .loc 1 3867 6 view .LVU2803 + 8004 0008 00F02800 and r0, r0, #40 + 8005 000c 2828 cmp r0, #40 + 8006 000e 40F0BB80 bne .L520 + 8007 0012 0F46 mov r7, r1 + 8008 0014 1646 mov r6, r2 + 8009 0016 1D46 mov r5, r3 +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8010 .loc 1 3869 5 is_stmt 1 view .LVU2804 +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8011 .loc 1 3869 8 is_stmt 0 view .LVU2805 + 8012 0018 0029 cmp r1, #0 + 8013 001a 51D0 beq .L511 +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8014 .loc 1 3869 25 discriminator 1 view .LVU2806 + 8015 001c 002A cmp r2, #0 + 8016 001e 4FD0 beq .L511 +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8017 .loc 1 3876 5 is_stmt 1 view .LVU2807 +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8018 .loc 1 3876 5 view .LVU2808 + 8019 0020 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 8020 .LVL533: + ARM GAS /tmp/ccE2rRGE.s page 307 + + +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8021 .loc 1 3876 5 is_stmt 0 view .LVU2809 + 8022 0024 012B cmp r3, #1 + 8023 0026 00F0B280 beq .L521 +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8024 .loc 1 3876 5 is_stmt 1 discriminator 2 view .LVU2810 + 8025 002a 0123 movs r3, #1 + 8026 002c 84F84030 strb r3, [r4, #64] +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8027 .loc 1 3876 5 discriminator 2 view .LVU2811 +3879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8028 .loc 1 3879 5 discriminator 2 view .LVU2812 + 8029 0030 48F20101 movw r1, #32769 + 8030 .LVL534: +3879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8031 .loc 1 3879 5 is_stmt 0 discriminator 2 view .LVU2813 + 8032 0034 2046 mov r0, r4 + 8033 0036 FFF7FEFF bl I2C_Disable_IRQ + 8034 .LVL535: +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8035 .loc 1 3883 5 is_stmt 1 discriminator 2 view .LVU2814 +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8036 .loc 1 3883 13 is_stmt 0 discriminator 2 view .LVU2815 + 8037 003a 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8038 003e DBB2 uxtb r3, r3 +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8039 .loc 1 3883 8 discriminator 2 view .LVU2816 + 8040 0040 2A2B cmp r3, #42 + 8041 0042 42D0 beq .L524 +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8042 .loc 1 3908 10 is_stmt 1 view .LVU2817 +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8043 .loc 1 3908 18 is_stmt 0 view .LVU2818 + 8044 0044 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8045 0048 DBB2 uxtb r3, r3 +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8046 .loc 1 3908 13 view .LVU2819 + 8047 004a 292B cmp r3, #41 + 8048 004c 59D0 beq .L525 + 8049 .L514: +3933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8050 .loc 1 3933 5 is_stmt 1 view .LVU2820 +3935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8051 .loc 1 3935 5 view .LVU2821 +3935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8052 .loc 1 3935 21 is_stmt 0 view .LVU2822 + 8053 004e 2923 movs r3, #41 + 8054 0050 84F84130 strb r3, [r4, #65] +3936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8055 .loc 1 3936 5 is_stmt 1 view .LVU2823 +3936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8056 .loc 1 3936 21 is_stmt 0 view .LVU2824 + 8057 0054 2023 movs r3, #32 + 8058 0056 84F84230 strb r3, [r4, #66] +3937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8059 .loc 1 3937 5 is_stmt 1 view .LVU2825 +3937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 308 + + + 8060 .loc 1 3937 21 is_stmt 0 view .LVU2826 + 8061 005a 0023 movs r3, #0 + 8062 005c 6364 str r3, [r4, #68] +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8063 .loc 1 3940 5 is_stmt 1 view .LVU2827 +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8064 .loc 1 3940 9 is_stmt 0 view .LVU2828 + 8065 005e 2268 ldr r2, [r4] +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8066 .loc 1 3940 19 view .LVU2829 + 8067 0060 5368 ldr r3, [r2, #4] +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8068 .loc 1 3940 25 view .LVU2830 + 8069 0062 23F40043 bic r3, r3, #32768 + 8070 0066 5360 str r3, [r2, #4] +3943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 8071 .loc 1 3943 5 is_stmt 1 view .LVU2831 +3943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 8072 .loc 1 3943 23 is_stmt 0 view .LVU2832 + 8073 0068 6762 str r7, [r4, #36] +3944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8074 .loc 1 3944 5 is_stmt 1 view .LVU2833 +3944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8075 .loc 1 3944 23 is_stmt 0 view .LVU2834 + 8076 006a 6685 strh r6, [r4, #42] @ movhi +3945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8077 .loc 1 3945 5 is_stmt 1 view .LVU2835 +3945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8078 .loc 1 3945 29 is_stmt 0 view .LVU2836 + 8079 006c 638D ldrh r3, [r4, #42] +3945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8080 .loc 1 3945 23 view .LVU2837 + 8081 006e 2385 strh r3, [r4, #40] @ movhi +3946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8082 .loc 1 3946 5 is_stmt 1 view .LVU2838 +3946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8083 .loc 1 3946 23 is_stmt 0 view .LVU2839 + 8084 0070 E562 str r5, [r4, #44] +3947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8085 .loc 1 3947 5 is_stmt 1 view .LVU2840 +3947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8086 .loc 1 3947 23 is_stmt 0 view .LVU2841 + 8087 0072 484B ldr r3, .L526 + 8088 0074 6363 str r3, [r4, #52] +3949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8089 .loc 1 3949 5 is_stmt 1 view .LVU2842 +3949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8090 .loc 1 3949 13 is_stmt 0 view .LVU2843 + 8091 0076 A36B ldr r3, [r4, #56] +3949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8092 .loc 1 3949 8 view .LVU2844 + 8093 0078 002B cmp r3, #0 + 8094 007a 59D0 beq .L515 +3952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8095 .loc 1 3952 7 is_stmt 1 view .LVU2845 +3952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8096 .loc 1 3952 38 is_stmt 0 view .LVU2846 + ARM GAS /tmp/ccE2rRGE.s page 309 + + + 8097 007c 464A ldr r2, .L526+4 + 8098 007e 9A62 str r2, [r3, #40] +3955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8099 .loc 1 3955 7 is_stmt 1 view .LVU2847 +3955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8100 .loc 1 3955 11 is_stmt 0 view .LVU2848 + 8101 0080 A36B ldr r3, [r4, #56] +3955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8102 .loc 1 3955 39 view .LVU2849 + 8103 0082 464A ldr r2, .L526+8 + 8104 0084 1A63 str r2, [r3, #48] +3958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8105 .loc 1 3958 7 is_stmt 1 view .LVU2850 +3958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8106 .loc 1 3958 11 is_stmt 0 view .LVU2851 + 8107 0086 A26B ldr r2, [r4, #56] +3958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8108 .loc 1 3958 42 view .LVU2852 + 8109 0088 0023 movs r3, #0 + 8110 008a D362 str r3, [r2, #44] +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8111 .loc 1 3959 7 is_stmt 1 view .LVU2853 +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8112 .loc 1 3959 11 is_stmt 0 view .LVU2854 + 8113 008c A26B ldr r2, [r4, #56] +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8114 .loc 1 3959 39 view .LVU2855 + 8115 008e 5363 str r3, [r2, #52] +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 8116 .loc 1 3962 7 is_stmt 1 view .LVU2856 +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 8117 .loc 1 3962 86 is_stmt 0 view .LVU2857 + 8118 0090 2268 ldr r2, [r4] +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 8119 .loc 1 3962 23 view .LVU2858 + 8120 0092 238D ldrh r3, [r4, #40] + 8121 0094 2832 adds r2, r2, #40 + 8122 0096 3946 mov r1, r7 + 8123 0098 A06B ldr r0, [r4, #56] + 8124 009a FFF7FEFF bl HAL_DMA_Start_IT + 8125 .LVL536: +3980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8126 .loc 1 3980 5 is_stmt 1 view .LVU2859 +3980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8127 .loc 1 3980 8 is_stmt 0 view .LVU2860 + 8128 009e 0546 mov r5, r0 + 8129 .LVL537: +3980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8130 .loc 1 3980 8 view .LVU2861 + 8131 00a0 0028 cmp r0, #0 + 8132 00a2 53D0 beq .L516 +3991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8133 .loc 1 3991 7 is_stmt 1 view .LVU2862 +3991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8134 .loc 1 3991 23 is_stmt 0 view .LVU2863 + 8135 00a4 2823 movs r3, #40 + 8136 00a6 84F84130 strb r3, [r4, #65] + ARM GAS /tmp/ccE2rRGE.s page 310 + + +3992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8137 .loc 1 3992 7 is_stmt 1 view .LVU2864 +3992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8138 .loc 1 3992 23 is_stmt 0 view .LVU2865 + 8139 00aa 0022 movs r2, #0 + 8140 00ac 84F84220 strb r2, [r4, #66] +3995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8141 .loc 1 3995 7 is_stmt 1 view .LVU2866 +3995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8142 .loc 1 3995 11 is_stmt 0 view .LVU2867 + 8143 00b0 636C ldr r3, [r4, #68] +3995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8144 .loc 1 3995 23 view .LVU2868 + 8145 00b2 43F01003 orr r3, r3, #16 + 8146 00b6 6364 str r3, [r4, #68] +3998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8147 .loc 1 3998 7 is_stmt 1 view .LVU2869 +3998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8148 .loc 1 3998 7 view .LVU2870 + 8149 00b8 84F84020 strb r2, [r4, #64] +3998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8150 .loc 1 3998 7 view .LVU2871 +4000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8151 .loc 1 4000 7 view .LVU2872 +4000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8152 .loc 1 4000 14 is_stmt 0 view .LVU2873 + 8153 00bc 0125 movs r5, #1 + 8154 00be 64E0 b .L510 + 8155 .LVL538: + 8156 .L511: +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8157 .loc 1 3871 7 is_stmt 1 view .LVU2874 +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8158 .loc 1 3871 23 is_stmt 0 view .LVU2875 + 8159 00c0 4FF40073 mov r3, #512 + 8160 .LVL539: +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8161 .loc 1 3871 23 view .LVU2876 + 8162 00c4 6364 str r3, [r4, #68] +3872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8163 .loc 1 3872 7 is_stmt 1 view .LVU2877 +3872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8164 .loc 1 3872 15 is_stmt 0 view .LVU2878 + 8165 00c6 0125 movs r5, #1 + 8166 .LVL540: +3872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8167 .loc 1 3872 15 view .LVU2879 + 8168 00c8 5FE0 b .L510 + 8169 .LVL541: + 8170 .L524: +3886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8171 .loc 1 3886 7 is_stmt 1 view .LVU2880 + 8172 00ca 0221 movs r1, #2 + 8173 00cc 2046 mov r0, r4 + 8174 00ce FFF7FEFF bl I2C_Disable_IRQ + 8175 .LVL542: +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 311 + + + 8176 .loc 1 3888 7 view .LVU2881 +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8177 .loc 1 3888 16 is_stmt 0 view .LVU2882 + 8178 00d2 2368 ldr r3, [r4] +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8179 .loc 1 3888 26 view .LVU2883 + 8180 00d4 1A68 ldr r2, [r3] +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8181 .loc 1 3888 10 view .LVU2884 + 8182 00d6 12F4004F tst r2, #32768 + 8183 00da B8D0 beq .L514 +3891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8184 .loc 1 3891 9 is_stmt 1 view .LVU2885 +3891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8185 .loc 1 3891 17 is_stmt 0 view .LVU2886 + 8186 00dc E26B ldr r2, [r4, #60] +3891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8187 .loc 1 3891 12 view .LVU2887 + 8188 00de 002A cmp r2, #0 + 8189 00e0 B5D0 beq .L514 +3893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8190 .loc 1 3893 11 is_stmt 1 view .LVU2888 +3893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8191 .loc 1 3893 25 is_stmt 0 view .LVU2889 + 8192 00e2 1A68 ldr r2, [r3] +3893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8193 .loc 1 3893 31 view .LVU2890 + 8194 00e4 22F40042 bic r2, r2, #32768 + 8195 00e8 1A60 str r2, [r3] +3897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8196 .loc 1 3897 11 is_stmt 1 view .LVU2891 +3897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8197 .loc 1 3897 15 is_stmt 0 view .LVU2892 + 8198 00ea E36B ldr r3, [r4, #60] +3897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8199 .loc 1 3897 43 view .LVU2893 + 8200 00ec 2C4A ldr r2, .L526+12 + 8201 00ee 5A63 str r2, [r3, #52] +3900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8202 .loc 1 3900 11 is_stmt 1 view .LVU2894 +3900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8203 .loc 1 3900 15 is_stmt 0 view .LVU2895 + 8204 00f0 E06B ldr r0, [r4, #60] + 8205 00f2 FFF7FEFF bl HAL_DMA_Abort_IT + 8206 .LVL543: +3900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8207 .loc 1 3900 14 view .LVU2896 + 8208 00f6 0028 cmp r0, #0 + 8209 00f8 A9D0 beq .L514 +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8210 .loc 1 3903 13 is_stmt 1 view .LVU2897 +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8211 .loc 1 3903 17 is_stmt 0 view .LVU2898 + 8212 00fa E06B ldr r0, [r4, #60] +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8213 .loc 1 3903 25 view .LVU2899 + 8214 00fc 436B ldr r3, [r0, #52] + ARM GAS /tmp/ccE2rRGE.s page 312 + + +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8215 .loc 1 3903 13 view .LVU2900 + 8216 00fe 9847 blx r3 + 8217 .LVL544: + 8218 0100 A5E7 b .L514 + 8219 .L525: +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8220 .loc 1 3910 7 is_stmt 1 view .LVU2901 +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8221 .loc 1 3910 16 is_stmt 0 view .LVU2902 + 8222 0102 2368 ldr r3, [r4] +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8223 .loc 1 3910 26 view .LVU2903 + 8224 0104 1A68 ldr r2, [r3] +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8225 .loc 1 3910 10 view .LVU2904 + 8226 0106 12F4804F tst r2, #16384 + 8227 010a A0D0 beq .L514 +3912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8228 .loc 1 3912 9 is_stmt 1 view .LVU2905 +3912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8229 .loc 1 3912 23 is_stmt 0 view .LVU2906 + 8230 010c 1A68 ldr r2, [r3] +3912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8231 .loc 1 3912 29 view .LVU2907 + 8232 010e 22F48042 bic r2, r2, #16384 + 8233 0112 1A60 str r2, [r3] +3915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8234 .loc 1 3915 9 is_stmt 1 view .LVU2908 +3915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8235 .loc 1 3915 17 is_stmt 0 view .LVU2909 + 8236 0114 A36B ldr r3, [r4, #56] +3915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8237 .loc 1 3915 12 view .LVU2910 + 8238 0116 002B cmp r3, #0 + 8239 0118 99D0 beq .L514 +3919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8240 .loc 1 3919 11 is_stmt 1 view .LVU2911 +3919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8241 .loc 1 3919 43 is_stmt 0 view .LVU2912 + 8242 011a 214A ldr r2, .L526+12 + 8243 011c 5A63 str r2, [r3, #52] +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8244 .loc 1 3922 11 is_stmt 1 view .LVU2913 +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8245 .loc 1 3922 15 is_stmt 0 view .LVU2914 + 8246 011e A06B ldr r0, [r4, #56] + 8247 0120 FFF7FEFF bl HAL_DMA_Abort_IT + 8248 .LVL545: +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8249 .loc 1 3922 14 view .LVU2915 + 8250 0124 0028 cmp r0, #0 + 8251 0126 92D0 beq .L514 +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8252 .loc 1 3925 13 is_stmt 1 view .LVU2916 +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8253 .loc 1 3925 17 is_stmt 0 view .LVU2917 + ARM GAS /tmp/ccE2rRGE.s page 313 + + + 8254 0128 A06B ldr r0, [r4, #56] +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8255 .loc 1 3925 25 view .LVU2918 + 8256 012a 436B ldr r3, [r0, #52] +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8257 .loc 1 3925 13 view .LVU2919 + 8258 012c 9847 blx r3 + 8259 .LVL546: + 8260 012e 8EE7 b .L514 + 8261 .L515: +3968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8262 .loc 1 3968 7 is_stmt 1 view .LVU2920 +3968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8263 .loc 1 3968 23 is_stmt 0 view .LVU2921 + 8264 0130 2823 movs r3, #40 + 8265 0132 84F84130 strb r3, [r4, #65] +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8266 .loc 1 3969 7 is_stmt 1 view .LVU2922 +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8267 .loc 1 3969 23 is_stmt 0 view .LVU2923 + 8268 0136 0022 movs r2, #0 + 8269 0138 84F84220 strb r2, [r4, #66] +3972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8270 .loc 1 3972 7 is_stmt 1 view .LVU2924 +3972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8271 .loc 1 3972 11 is_stmt 0 view .LVU2925 + 8272 013c 636C ldr r3, [r4, #68] +3972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8273 .loc 1 3972 23 view .LVU2926 + 8274 013e 43F08003 orr r3, r3, #128 + 8275 0142 6364 str r3, [r4, #68] +3975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8276 .loc 1 3975 7 is_stmt 1 view .LVU2927 +3975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8277 .loc 1 3975 7 view .LVU2928 + 8278 0144 84F84020 strb r2, [r4, #64] +3975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8279 .loc 1 3975 7 view .LVU2929 +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8280 .loc 1 3977 7 view .LVU2930 +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8281 .loc 1 3977 14 is_stmt 0 view .LVU2931 + 8282 0148 0125 movs r5, #1 + 8283 .LVL547: +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8284 .loc 1 3977 14 view .LVU2932 + 8285 014a 1EE0 b .L510 + 8286 .LVL548: + 8287 .L516: +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8288 .loc 1 3983 7 is_stmt 1 view .LVU2933 +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8289 .loc 1 3983 11 is_stmt 0 view .LVU2934 + 8290 014c 638D ldrh r3, [r4, #42] + 8291 014e 9BB2 uxth r3, r3 +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8292 .loc 1 3983 30 view .LVU2935 + ARM GAS /tmp/ccE2rRGE.s page 314 + + + 8293 0150 228D ldrh r2, [r4, #40] +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8294 .loc 1 3983 23 view .LVU2936 + 8295 0152 9B1A subs r3, r3, r2 + 8296 0154 9BB2 uxth r3, r3 + 8297 0156 6385 strh r3, [r4, #42] @ movhi +3986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8298 .loc 1 3986 7 is_stmt 1 view .LVU2937 +3986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8299 .loc 1 3986 22 is_stmt 0 view .LVU2938 + 8300 0158 0023 movs r3, #0 + 8301 015a 2385 strh r3, [r4, #40] @ movhi +4003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8302 .loc 1 4003 5 is_stmt 1 view .LVU2939 +4003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8303 .loc 1 4003 9 is_stmt 0 view .LVU2940 + 8304 015c 2368 ldr r3, [r4] + 8305 015e 9A69 ldr r2, [r3, #24] +4003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8306 .loc 1 4003 8 view .LVU2941 + 8307 0160 12F4803F tst r2, #65536 + 8308 0164 0DD1 bne .L518 + 8309 .L519: +4011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8310 .loc 1 4011 5 is_stmt 1 view .LVU2942 +4011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8311 .loc 1 4011 5 view .LVU2943 + 8312 0166 0023 movs r3, #0 + 8313 0168 84F84030 strb r3, [r4, #64] +4011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8314 .loc 1 4011 5 view .LVU2944 +4017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8315 .loc 1 4017 5 view .LVU2945 + 8316 016c 4FF40041 mov r1, #32768 + 8317 0170 2046 mov r0, r4 + 8318 .LVL549: +4017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8319 .loc 1 4017 5 is_stmt 0 view .LVU2946 + 8320 0172 FFF7FEFF bl I2C_Enable_IRQ + 8321 .LVL550: +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8322 .loc 1 4020 5 is_stmt 1 view .LVU2947 +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8323 .loc 1 4020 9 is_stmt 0 view .LVU2948 + 8324 0176 2268 ldr r2, [r4] +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8325 .loc 1 4020 19 view .LVU2949 + 8326 0178 1368 ldr r3, [r2] +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8327 .loc 1 4020 25 view .LVU2950 + 8328 017a 43F48043 orr r3, r3, #16384 + 8329 017e 1360 str r3, [r2] +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8330 .loc 1 4022 5 is_stmt 1 view .LVU2951 +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8331 .loc 1 4022 12 is_stmt 0 view .LVU2952 + 8332 0180 03E0 b .L510 + ARM GAS /tmp/ccE2rRGE.s page 315 + + + 8333 .LVL551: + 8334 .L518: +4007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8335 .loc 1 4007 7 is_stmt 1 view .LVU2953 + 8336 0182 0822 movs r2, #8 + 8337 0184 DA61 str r2, [r3, #28] + 8338 0186 EEE7 b .L519 + 8339 .LVL552: + 8340 .L520: +4026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8341 .loc 1 4026 12 is_stmt 0 view .LVU2954 + 8342 0188 0125 movs r5, #1 + 8343 .LVL553: + 8344 .L510: +4028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8345 .loc 1 4028 1 view .LVU2955 + 8346 018a 2846 mov r0, r5 + 8347 018c F8BD pop {r3, r4, r5, r6, r7, pc} + 8348 .LVL554: + 8349 .L521: +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8350 .loc 1 3876 5 view .LVU2956 + 8351 018e 0225 movs r5, #2 + 8352 .LVL555: +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8353 .loc 1 3876 5 view .LVU2957 + 8354 0190 FBE7 b .L510 + 8355 .L527: + 8356 0192 00BF .align 2 + 8357 .L526: + 8358 0194 00000000 .word I2C_Slave_ISR_DMA + 8359 0198 00000000 .word I2C_DMASlaveTransmitCplt + 8360 019c 00000000 .word I2C_DMAError + 8361 01a0 00000000 .word I2C_DMAAbort + 8362 .cfi_endproc + 8363 .LFE158: + 8365 .section .text.HAL_I2C_Slave_Seq_Receive_IT,"ax",%progbits + 8366 .align 1 + 8367 .global HAL_I2C_Slave_Seq_Receive_IT + 8368 .syntax unified + 8369 .thumb + 8370 .thumb_func + 8372 HAL_I2C_Slave_Seq_Receive_IT: + 8373 .LVL556: + 8374 .LFB159: +4042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + 8375 .loc 1 4042 1 is_stmt 1 view -0 + 8376 .cfi_startproc + 8377 @ args = 0, pretend = 0, frame = 0 + 8378 @ frame_needed = 0, uses_anonymous_args = 0 +4042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + 8379 .loc 1 4042 1 is_stmt 0 view .LVU2959 + 8380 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8381 .cfi_def_cfa_offset 24 + 8382 .cfi_offset 3, -24 + 8383 .cfi_offset 4, -20 + 8384 .cfi_offset 5, -16 + ARM GAS /tmp/ccE2rRGE.s page 316 + + + 8385 .cfi_offset 6, -12 + 8386 .cfi_offset 7, -8 + 8387 .cfi_offset 14, -4 + 8388 0002 0446 mov r4, r0 +4044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8389 .loc 1 4044 3 is_stmt 1 view .LVU2960 +4046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8390 .loc 1 4046 3 view .LVU2961 +4046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8391 .loc 1 4046 22 is_stmt 0 view .LVU2962 + 8392 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8393 .LVL557: +4046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8394 .loc 1 4046 6 view .LVU2963 + 8395 0008 00F02800 and r0, r0, #40 + 8396 000c 2828 cmp r0, #40 + 8397 000e 5AD1 bne .L534 + 8398 0010 0F46 mov r7, r1 + 8399 0012 1646 mov r6, r2 + 8400 0014 1D46 mov r5, r3 +4048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8401 .loc 1 4048 5 is_stmt 1 view .LVU2964 +4048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8402 .loc 1 4048 8 is_stmt 0 view .LVU2965 + 8403 0016 01B1 cbz r1, .L530 +4048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8404 .loc 1 4048 25 discriminator 1 view .LVU2966 + 8405 0018 22B9 cbnz r2, .L531 + 8406 .L530: +4050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8407 .loc 1 4050 7 is_stmt 1 view .LVU2967 +4050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8408 .loc 1 4050 23 is_stmt 0 view .LVU2968 + 8409 001a 4FF40073 mov r3, #512 + 8410 .LVL558: +4050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8411 .loc 1 4050 23 view .LVU2969 + 8412 001e 6364 str r3, [r4, #68] +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8413 .loc 1 4051 7 is_stmt 1 view .LVU2970 +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8414 .loc 1 4051 15 is_stmt 0 view .LVU2971 + 8415 0020 0120 movs r0, #1 + 8416 0022 51E0 b .L529 + 8417 .LVL559: + 8418 .L531: +4055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8419 .loc 1 4055 5 is_stmt 1 view .LVU2972 + 8420 0024 48F20201 movw r1, #32770 + 8421 .LVL560: +4055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8422 .loc 1 4055 5 is_stmt 0 view .LVU2973 + 8423 0028 2046 mov r0, r4 + 8424 002a FFF7FEFF bl I2C_Disable_IRQ + 8425 .LVL561: +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8426 .loc 1 4058 5 is_stmt 1 view .LVU2974 + ARM GAS /tmp/ccE2rRGE.s page 317 + + +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8427 .loc 1 4058 5 view .LVU2975 + 8428 002e 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 8429 0032 012B cmp r3, #1 + 8430 0034 49D0 beq .L535 +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8431 .loc 1 4058 5 discriminator 2 view .LVU2976 + 8432 0036 0123 movs r3, #1 + 8433 0038 84F84030 strb r3, [r4, #64] +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8434 .loc 1 4058 5 discriminator 2 view .LVU2977 +4062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8435 .loc 1 4062 5 discriminator 2 view .LVU2978 +4062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8436 .loc 1 4062 13 is_stmt 0 discriminator 2 view .LVU2979 + 8437 003c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8438 0040 DBB2 uxtb r3, r3 +4062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8439 .loc 1 4062 8 discriminator 2 view .LVU2980 + 8440 0042 292B cmp r3, #41 + 8441 0044 24D0 beq .L537 + 8442 .L532: +4088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8443 .loc 1 4088 5 is_stmt 1 view .LVU2981 +4088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8444 .loc 1 4088 21 is_stmt 0 view .LVU2982 + 8445 0046 2A23 movs r3, #42 + 8446 0048 84F84130 strb r3, [r4, #65] +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8447 .loc 1 4089 5 is_stmt 1 view .LVU2983 +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8448 .loc 1 4089 21 is_stmt 0 view .LVU2984 + 8449 004c 2023 movs r3, #32 + 8450 004e 84F84230 strb r3, [r4, #66] +4090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8451 .loc 1 4090 5 is_stmt 1 view .LVU2985 +4090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8452 .loc 1 4090 21 is_stmt 0 view .LVU2986 + 8453 0052 0023 movs r3, #0 + 8454 0054 6364 str r3, [r4, #68] +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8455 .loc 1 4093 5 is_stmt 1 view .LVU2987 +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8456 .loc 1 4093 9 is_stmt 0 view .LVU2988 + 8457 0056 2268 ldr r2, [r4] +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8458 .loc 1 4093 19 view .LVU2989 + 8459 0058 5368 ldr r3, [r2, #4] +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8460 .loc 1 4093 25 view .LVU2990 + 8461 005a 23F40043 bic r3, r3, #32768 + 8462 005e 5360 str r3, [r2, #4] +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 8463 .loc 1 4096 5 is_stmt 1 view .LVU2991 +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 8464 .loc 1 4096 23 is_stmt 0 view .LVU2992 + 8465 0060 6762 str r7, [r4, #36] + ARM GAS /tmp/ccE2rRGE.s page 318 + + +4097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8466 .loc 1 4097 5 is_stmt 1 view .LVU2993 +4097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8467 .loc 1 4097 23 is_stmt 0 view .LVU2994 + 8468 0062 6685 strh r6, [r4, #42] @ movhi +4098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8469 .loc 1 4098 5 is_stmt 1 view .LVU2995 +4098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8470 .loc 1 4098 29 is_stmt 0 view .LVU2996 + 8471 0064 638D ldrh r3, [r4, #42] +4098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8472 .loc 1 4098 23 view .LVU2997 + 8473 0066 2385 strh r3, [r4, #40] @ movhi +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8474 .loc 1 4099 5 is_stmt 1 view .LVU2998 +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8475 .loc 1 4099 23 is_stmt 0 view .LVU2999 + 8476 0068 E562 str r5, [r4, #44] +4100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8477 .loc 1 4100 5 is_stmt 1 view .LVU3000 +4100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8478 .loc 1 4100 23 is_stmt 0 view .LVU3001 + 8479 006a 194B ldr r3, .L538 + 8480 006c 6363 str r3, [r4, #52] +4102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8481 .loc 1 4102 5 is_stmt 1 view .LVU3002 +4102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8482 .loc 1 4102 9 is_stmt 0 view .LVU3003 + 8483 006e 2368 ldr r3, [r4] + 8484 0070 9A69 ldr r2, [r3, #24] +4102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8485 .loc 1 4102 8 view .LVU3004 + 8486 0072 12F4803F tst r2, #65536 + 8487 0076 01D1 bne .L533 +4106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8488 .loc 1 4106 7 is_stmt 1 view .LVU3005 + 8489 0078 0822 movs r2, #8 + 8490 007a DA61 str r2, [r3, #28] + 8491 .L533: +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8492 .loc 1 4110 5 view .LVU3006 +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8493 .loc 1 4110 5 view .LVU3007 + 8494 007c 0025 movs r5, #0 + 8495 .LVL562: +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8496 .loc 1 4110 5 is_stmt 0 view .LVU3008 + 8497 007e 84F84050 strb r5, [r4, #64] +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8498 .loc 1 4110 5 is_stmt 1 view .LVU3009 +4116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8499 .loc 1 4116 5 view .LVU3010 + 8500 0082 48F20201 movw r1, #32770 + 8501 0086 2046 mov r0, r4 + 8502 0088 FFF7FEFF bl I2C_Enable_IRQ + 8503 .LVL563: +4118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 319 + + + 8504 .loc 1 4118 5 view .LVU3011 +4118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8505 .loc 1 4118 12 is_stmt 0 view .LVU3012 + 8506 008c 2846 mov r0, r5 + 8507 008e 1BE0 b .L529 + 8508 .LVL564: + 8509 .L537: +4065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8510 .loc 1 4065 7 is_stmt 1 view .LVU3013 + 8511 0090 0121 movs r1, #1 + 8512 0092 2046 mov r0, r4 + 8513 0094 FFF7FEFF bl I2C_Disable_IRQ + 8514 .LVL565: +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8515 .loc 1 4067 7 view .LVU3014 +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8516 .loc 1 4067 16 is_stmt 0 view .LVU3015 + 8517 0098 2368 ldr r3, [r4] +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8518 .loc 1 4067 26 view .LVU3016 + 8519 009a 1A68 ldr r2, [r3] +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8520 .loc 1 4067 10 view .LVU3017 + 8521 009c 12F4804F tst r2, #16384 + 8522 00a0 D1D0 beq .L532 +4069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8523 .loc 1 4069 9 is_stmt 1 view .LVU3018 +4069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8524 .loc 1 4069 23 is_stmt 0 view .LVU3019 + 8525 00a2 1A68 ldr r2, [r3] +4069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8526 .loc 1 4069 29 view .LVU3020 + 8527 00a4 22F48042 bic r2, r2, #16384 + 8528 00a8 1A60 str r2, [r3] +4072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8529 .loc 1 4072 9 is_stmt 1 view .LVU3021 +4072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8530 .loc 1 4072 17 is_stmt 0 view .LVU3022 + 8531 00aa A36B ldr r3, [r4, #56] +4072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8532 .loc 1 4072 12 view .LVU3023 + 8533 00ac 002B cmp r3, #0 + 8534 00ae CAD0 beq .L532 +4076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8535 .loc 1 4076 11 is_stmt 1 view .LVU3024 +4076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8536 .loc 1 4076 43 is_stmt 0 view .LVU3025 + 8537 00b0 084A ldr r2, .L538+4 + 8538 00b2 5A63 str r2, [r3, #52] +4079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8539 .loc 1 4079 11 is_stmt 1 view .LVU3026 +4079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8540 .loc 1 4079 15 is_stmt 0 view .LVU3027 + 8541 00b4 A06B ldr r0, [r4, #56] + 8542 00b6 FFF7FEFF bl HAL_DMA_Abort_IT + 8543 .LVL566: +4079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 320 + + + 8544 .loc 1 4079 14 view .LVU3028 + 8545 00ba 0028 cmp r0, #0 + 8546 00bc C3D0 beq .L532 +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8547 .loc 1 4082 13 is_stmt 1 view .LVU3029 +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8548 .loc 1 4082 17 is_stmt 0 view .LVU3030 + 8549 00be A06B ldr r0, [r4, #56] +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8550 .loc 1 4082 25 view .LVU3031 + 8551 00c0 436B ldr r3, [r0, #52] +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8552 .loc 1 4082 13 view .LVU3032 + 8553 00c2 9847 blx r3 + 8554 .LVL567: + 8555 00c4 BFE7 b .L532 + 8556 .LVL568: + 8557 .L534: +4122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8558 .loc 1 4122 12 view .LVU3033 + 8559 00c6 0120 movs r0, #1 + 8560 .LVL569: + 8561 .L529: +4124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8562 .loc 1 4124 1 view .LVU3034 + 8563 00c8 F8BD pop {r3, r4, r5, r6, r7, pc} + 8564 .LVL570: + 8565 .L535: +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8566 .loc 1 4058 5 view .LVU3035 + 8567 00ca 0220 movs r0, #2 + 8568 00cc FCE7 b .L529 + 8569 .L539: + 8570 00ce 00BF .align 2 + 8571 .L538: + 8572 00d0 00000000 .word I2C_Slave_ISR_IT + 8573 00d4 00000000 .word I2C_DMAAbort + 8574 .cfi_endproc + 8575 .LFE159: + 8577 .section .text.HAL_I2C_Slave_Seq_Receive_DMA,"ax",%progbits + 8578 .align 1 + 8579 .global HAL_I2C_Slave_Seq_Receive_DMA + 8580 .syntax unified + 8581 .thumb + 8582 .thumb_func + 8584 HAL_I2C_Slave_Seq_Receive_DMA: + 8585 .LVL571: + 8586 .LFB160: +4138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8587 .loc 1 4138 1 is_stmt 1 view -0 + 8588 .cfi_startproc + 8589 @ args = 0, pretend = 0, frame = 0 + 8590 @ frame_needed = 0, uses_anonymous_args = 0 +4138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8591 .loc 1 4138 1 is_stmt 0 view .LVU3037 + 8592 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8593 .cfi_def_cfa_offset 24 + ARM GAS /tmp/ccE2rRGE.s page 321 + + + 8594 .cfi_offset 3, -24 + 8595 .cfi_offset 4, -20 + 8596 .cfi_offset 5, -16 + 8597 .cfi_offset 6, -12 + 8598 .cfi_offset 7, -8 + 8599 .cfi_offset 14, -4 + 8600 0002 0446 mov r4, r0 +4139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8601 .loc 1 4139 3 is_stmt 1 view .LVU3038 +4142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8602 .loc 1 4142 3 view .LVU3039 +4144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8603 .loc 1 4144 3 view .LVU3040 +4144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8604 .loc 1 4144 22 is_stmt 0 view .LVU3041 + 8605 0004 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 8606 .LVL572: +4144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8607 .loc 1 4144 6 view .LVU3042 + 8608 0008 00F02800 and r0, r0, #40 + 8609 000c 2828 cmp r0, #40 + 8610 000e 40F0B980 bne .L551 + 8611 0012 0F46 mov r7, r1 + 8612 0014 1646 mov r6, r2 + 8613 0016 1D46 mov r5, r3 +4146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8614 .loc 1 4146 5 is_stmt 1 view .LVU3043 +4146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8615 .loc 1 4146 8 is_stmt 0 view .LVU3044 + 8616 0018 01B1 cbz r1, .L542 +4146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8617 .loc 1 4146 25 discriminator 1 view .LVU3045 + 8618 001a 22B9 cbnz r2, .L543 + 8619 .L542: +4148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8620 .loc 1 4148 7 is_stmt 1 view .LVU3046 +4148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8621 .loc 1 4148 23 is_stmt 0 view .LVU3047 + 8622 001c 4FF40073 mov r3, #512 + 8623 .LVL573: +4148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8624 .loc 1 4148 23 view .LVU3048 + 8625 0020 6364 str r3, [r4, #68] +4149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8626 .loc 1 4149 7 is_stmt 1 view .LVU3049 +4149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8627 .loc 1 4149 15 is_stmt 0 view .LVU3050 + 8628 0022 0125 movs r5, #1 + 8629 .LVL574: +4149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8630 .loc 1 4149 15 view .LVU3051 + 8631 0024 AFE0 b .L541 + 8632 .LVL575: + 8633 .L543: +4153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8634 .loc 1 4153 5 is_stmt 1 view .LVU3052 + 8635 0026 48F20201 movw r1, #32770 + ARM GAS /tmp/ccE2rRGE.s page 322 + + + 8636 .LVL576: +4153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8637 .loc 1 4153 5 is_stmt 0 view .LVU3053 + 8638 002a 2046 mov r0, r4 + 8639 002c FFF7FEFF bl I2C_Disable_IRQ + 8640 .LVL577: +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8641 .loc 1 4156 5 is_stmt 1 view .LVU3054 +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8642 .loc 1 4156 5 view .LVU3055 + 8643 0030 94F84030 ldrb r3, [r4, #64] @ zero_extendqisi2 + 8644 0034 012B cmp r3, #1 + 8645 0036 00F0A880 beq .L552 +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8646 .loc 1 4156 5 discriminator 2 view .LVU3056 + 8647 003a 0123 movs r3, #1 + 8648 003c 84F84030 strb r3, [r4, #64] +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8649 .loc 1 4156 5 discriminator 2 view .LVU3057 +4160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8650 .loc 1 4160 5 discriminator 2 view .LVU3058 +4160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8651 .loc 1 4160 13 is_stmt 0 discriminator 2 view .LVU3059 + 8652 0040 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8653 0044 DBB2 uxtb r3, r3 +4160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8654 .loc 1 4160 8 discriminator 2 view .LVU3060 + 8655 0046 292B cmp r3, #41 + 8656 0048 3DD0 beq .L555 +4185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8657 .loc 1 4185 10 is_stmt 1 view .LVU3061 +4185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8658 .loc 1 4185 18 is_stmt 0 view .LVU3062 + 8659 004a 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 8660 004e DBB2 uxtb r3, r3 +4185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8661 .loc 1 4185 13 view .LVU3063 + 8662 0050 2A2B cmp r3, #42 + 8663 0052 54D0 beq .L556 + 8664 .L545: +4210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8665 .loc 1 4210 5 is_stmt 1 view .LVU3064 +4212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8666 .loc 1 4212 5 view .LVU3065 +4212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8667 .loc 1 4212 21 is_stmt 0 view .LVU3066 + 8668 0054 2A23 movs r3, #42 + 8669 0056 84F84130 strb r3, [r4, #65] +4213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8670 .loc 1 4213 5 is_stmt 1 view .LVU3067 +4213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8671 .loc 1 4213 21 is_stmt 0 view .LVU3068 + 8672 005a 2023 movs r3, #32 + 8673 005c 84F84230 strb r3, [r4, #66] +4214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8674 .loc 1 4214 5 is_stmt 1 view .LVU3069 +4214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 323 + + + 8675 .loc 1 4214 21 is_stmt 0 view .LVU3070 + 8676 0060 0023 movs r3, #0 + 8677 0062 6364 str r3, [r4, #68] +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8678 .loc 1 4217 5 is_stmt 1 view .LVU3071 +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8679 .loc 1 4217 9 is_stmt 0 view .LVU3072 + 8680 0064 2268 ldr r2, [r4] +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8681 .loc 1 4217 19 view .LVU3073 + 8682 0066 5368 ldr r3, [r2, #4] +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8683 .loc 1 4217 25 view .LVU3074 + 8684 0068 23F40043 bic r3, r3, #32768 + 8685 006c 5360 str r3, [r2, #4] +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 8686 .loc 1 4220 5 is_stmt 1 view .LVU3075 +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 8687 .loc 1 4220 23 is_stmt 0 view .LVU3076 + 8688 006e 6762 str r7, [r4, #36] +4221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8689 .loc 1 4221 5 is_stmt 1 view .LVU3077 +4221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8690 .loc 1 4221 23 is_stmt 0 view .LVU3078 + 8691 0070 6685 strh r6, [r4, #42] @ movhi +4222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8692 .loc 1 4222 5 is_stmt 1 view .LVU3079 +4222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8693 .loc 1 4222 29 is_stmt 0 view .LVU3080 + 8694 0072 638D ldrh r3, [r4, #42] +4222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8695 .loc 1 4222 23 view .LVU3081 + 8696 0074 2385 strh r3, [r4, #40] @ movhi +4223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8697 .loc 1 4223 5 is_stmt 1 view .LVU3082 +4223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8698 .loc 1 4223 23 is_stmt 0 view .LVU3083 + 8699 0076 E562 str r5, [r4, #44] +4224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8700 .loc 1 4224 5 is_stmt 1 view .LVU3084 +4224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8701 .loc 1 4224 23 is_stmt 0 view .LVU3085 + 8702 0078 454B ldr r3, .L557 + 8703 007a 6363 str r3, [r4, #52] +4226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8704 .loc 1 4226 5 is_stmt 1 view .LVU3086 +4226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8705 .loc 1 4226 13 is_stmt 0 view .LVU3087 + 8706 007c E36B ldr r3, [r4, #60] +4226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8707 .loc 1 4226 8 view .LVU3088 + 8708 007e 002B cmp r3, #0 + 8709 0080 54D0 beq .L546 +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8710 .loc 1 4229 7 is_stmt 1 view .LVU3089 +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8711 .loc 1 4229 38 is_stmt 0 view .LVU3090 + ARM GAS /tmp/ccE2rRGE.s page 324 + + + 8712 0082 444A ldr r2, .L557+4 + 8713 0084 9A62 str r2, [r3, #40] +4232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8714 .loc 1 4232 7 is_stmt 1 view .LVU3091 +4232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8715 .loc 1 4232 11 is_stmt 0 view .LVU3092 + 8716 0086 E36B ldr r3, [r4, #60] +4232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8717 .loc 1 4232 39 view .LVU3093 + 8718 0088 434A ldr r2, .L557+8 + 8719 008a 1A63 str r2, [r3, #48] +4235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8720 .loc 1 4235 7 is_stmt 1 view .LVU3094 +4235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8721 .loc 1 4235 11 is_stmt 0 view .LVU3095 + 8722 008c E26B ldr r2, [r4, #60] +4235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8723 .loc 1 4235 42 view .LVU3096 + 8724 008e 0023 movs r3, #0 + 8725 0090 D362 str r3, [r2, #44] +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8726 .loc 1 4236 7 is_stmt 1 view .LVU3097 +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8727 .loc 1 4236 11 is_stmt 0 view .LVU3098 + 8728 0092 E26B ldr r2, [r4, #60] +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8729 .loc 1 4236 39 view .LVU3099 + 8730 0094 5363 str r3, [r2, #52] +4239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 8731 .loc 1 4239 7 is_stmt 1 view .LVU3100 +4239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 8732 .loc 1 4239 69 is_stmt 0 view .LVU3101 + 8733 0096 2168 ldr r1, [r4] +4239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 8734 .loc 1 4239 23 view .LVU3102 + 8735 0098 238D ldrh r3, [r4, #40] + 8736 009a 3A46 mov r2, r7 + 8737 009c 2431 adds r1, r1, #36 + 8738 009e E06B ldr r0, [r4, #60] + 8739 00a0 FFF7FEFF bl HAL_DMA_Start_IT + 8740 .LVL578: +4257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8741 .loc 1 4257 5 is_stmt 1 view .LVU3103 +4257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8742 .loc 1 4257 8 is_stmt 0 view .LVU3104 + 8743 00a4 0546 mov r5, r0 + 8744 .LVL579: +4257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8745 .loc 1 4257 8 view .LVU3105 + 8746 00a6 0028 cmp r0, #0 + 8747 00a8 4ED0 beq .L547 +4268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8748 .loc 1 4268 7 is_stmt 1 view .LVU3106 +4268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8749 .loc 1 4268 23 is_stmt 0 view .LVU3107 + 8750 00aa 2823 movs r3, #40 + 8751 00ac 84F84130 strb r3, [r4, #65] + ARM GAS /tmp/ccE2rRGE.s page 325 + + +4269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8752 .loc 1 4269 7 is_stmt 1 view .LVU3108 +4269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8753 .loc 1 4269 23 is_stmt 0 view .LVU3109 + 8754 00b0 0022 movs r2, #0 + 8755 00b2 84F84220 strb r2, [r4, #66] +4272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8756 .loc 1 4272 7 is_stmt 1 view .LVU3110 +4272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8757 .loc 1 4272 11 is_stmt 0 view .LVU3111 + 8758 00b6 636C ldr r3, [r4, #68] +4272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8759 .loc 1 4272 23 view .LVU3112 + 8760 00b8 43F01003 orr r3, r3, #16 + 8761 00bc 6364 str r3, [r4, #68] +4275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8762 .loc 1 4275 7 is_stmt 1 view .LVU3113 +4275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8763 .loc 1 4275 7 view .LVU3114 + 8764 00be 84F84020 strb r2, [r4, #64] +4275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8765 .loc 1 4275 7 view .LVU3115 +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8766 .loc 1 4277 7 view .LVU3116 +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8767 .loc 1 4277 14 is_stmt 0 view .LVU3117 + 8768 00c2 0125 movs r5, #1 + 8769 00c4 5FE0 b .L541 + 8770 .LVL580: + 8771 .L555: +4163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8772 .loc 1 4163 7 is_stmt 1 view .LVU3118 + 8773 00c6 0121 movs r1, #1 + 8774 00c8 2046 mov r0, r4 + 8775 00ca FFF7FEFF bl I2C_Disable_IRQ + 8776 .LVL581: +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8777 .loc 1 4165 7 view .LVU3119 +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8778 .loc 1 4165 16 is_stmt 0 view .LVU3120 + 8779 00ce 2368 ldr r3, [r4] +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8780 .loc 1 4165 26 view .LVU3121 + 8781 00d0 1A68 ldr r2, [r3] +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8782 .loc 1 4165 10 view .LVU3122 + 8783 00d2 12F4804F tst r2, #16384 + 8784 00d6 BDD0 beq .L545 +4168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8785 .loc 1 4168 9 is_stmt 1 view .LVU3123 +4168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8786 .loc 1 4168 17 is_stmt 0 view .LVU3124 + 8787 00d8 A26B ldr r2, [r4, #56] +4168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8788 .loc 1 4168 12 view .LVU3125 + 8789 00da 002A cmp r2, #0 + 8790 00dc BAD0 beq .L545 + ARM GAS /tmp/ccE2rRGE.s page 326 + + +4170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8791 .loc 1 4170 11 is_stmt 1 view .LVU3126 +4170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8792 .loc 1 4170 25 is_stmt 0 view .LVU3127 + 8793 00de 1A68 ldr r2, [r3] +4170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8794 .loc 1 4170 31 view .LVU3128 + 8795 00e0 22F48042 bic r2, r2, #16384 + 8796 00e4 1A60 str r2, [r3] +4174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8797 .loc 1 4174 11 is_stmt 1 view .LVU3129 +4174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8798 .loc 1 4174 15 is_stmt 0 view .LVU3130 + 8799 00e6 A36B ldr r3, [r4, #56] +4174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8800 .loc 1 4174 43 view .LVU3131 + 8801 00e8 2C4A ldr r2, .L557+12 + 8802 00ea 5A63 str r2, [r3, #52] +4177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8803 .loc 1 4177 11 is_stmt 1 view .LVU3132 +4177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8804 .loc 1 4177 15 is_stmt 0 view .LVU3133 + 8805 00ec A06B ldr r0, [r4, #56] + 8806 00ee FFF7FEFF bl HAL_DMA_Abort_IT + 8807 .LVL582: +4177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8808 .loc 1 4177 14 view .LVU3134 + 8809 00f2 0028 cmp r0, #0 + 8810 00f4 AED0 beq .L545 +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8811 .loc 1 4180 13 is_stmt 1 view .LVU3135 +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8812 .loc 1 4180 17 is_stmt 0 view .LVU3136 + 8813 00f6 A06B ldr r0, [r4, #56] +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8814 .loc 1 4180 25 view .LVU3137 + 8815 00f8 436B ldr r3, [r0, #52] +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8816 .loc 1 4180 13 view .LVU3138 + 8817 00fa 9847 blx r3 + 8818 .LVL583: + 8819 00fc AAE7 b .L545 + 8820 .L556: +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8821 .loc 1 4187 7 is_stmt 1 view .LVU3139 +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8822 .loc 1 4187 16 is_stmt 0 view .LVU3140 + 8823 00fe 2368 ldr r3, [r4] +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8824 .loc 1 4187 26 view .LVU3141 + 8825 0100 1A68 ldr r2, [r3] +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8826 .loc 1 4187 10 view .LVU3142 + 8827 0102 12F4004F tst r2, #32768 + 8828 0106 A5D0 beq .L545 +4189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8829 .loc 1 4189 9 is_stmt 1 view .LVU3143 + ARM GAS /tmp/ccE2rRGE.s page 327 + + +4189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8830 .loc 1 4189 23 is_stmt 0 view .LVU3144 + 8831 0108 1A68 ldr r2, [r3] +4189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8832 .loc 1 4189 29 view .LVU3145 + 8833 010a 22F40042 bic r2, r2, #32768 + 8834 010e 1A60 str r2, [r3] +4192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8835 .loc 1 4192 9 is_stmt 1 view .LVU3146 +4192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8836 .loc 1 4192 17 is_stmt 0 view .LVU3147 + 8837 0110 E36B ldr r3, [r4, #60] +4192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8838 .loc 1 4192 12 view .LVU3148 + 8839 0112 002B cmp r3, #0 + 8840 0114 9ED0 beq .L545 +4196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8841 .loc 1 4196 11 is_stmt 1 view .LVU3149 +4196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8842 .loc 1 4196 43 is_stmt 0 view .LVU3150 + 8843 0116 214A ldr r2, .L557+12 + 8844 0118 5A63 str r2, [r3, #52] +4199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8845 .loc 1 4199 11 is_stmt 1 view .LVU3151 +4199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8846 .loc 1 4199 15 is_stmt 0 view .LVU3152 + 8847 011a E06B ldr r0, [r4, #60] + 8848 011c FFF7FEFF bl HAL_DMA_Abort_IT + 8849 .LVL584: +4199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8850 .loc 1 4199 14 view .LVU3153 + 8851 0120 0028 cmp r0, #0 + 8852 0122 97D0 beq .L545 +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8853 .loc 1 4202 13 is_stmt 1 view .LVU3154 +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8854 .loc 1 4202 17 is_stmt 0 view .LVU3155 + 8855 0124 E06B ldr r0, [r4, #60] +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8856 .loc 1 4202 25 view .LVU3156 + 8857 0126 436B ldr r3, [r0, #52] +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8858 .loc 1 4202 13 view .LVU3157 + 8859 0128 9847 blx r3 + 8860 .LVL585: + 8861 012a 93E7 b .L545 + 8862 .L546: +4245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8863 .loc 1 4245 7 is_stmt 1 view .LVU3158 +4245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8864 .loc 1 4245 23 is_stmt 0 view .LVU3159 + 8865 012c 2823 movs r3, #40 + 8866 012e 84F84130 strb r3, [r4, #65] +4246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8867 .loc 1 4246 7 is_stmt 1 view .LVU3160 +4246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8868 .loc 1 4246 23 is_stmt 0 view .LVU3161 + ARM GAS /tmp/ccE2rRGE.s page 328 + + + 8869 0132 0022 movs r2, #0 + 8870 0134 84F84220 strb r2, [r4, #66] +4249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8871 .loc 1 4249 7 is_stmt 1 view .LVU3162 +4249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8872 .loc 1 4249 11 is_stmt 0 view .LVU3163 + 8873 0138 636C ldr r3, [r4, #68] +4249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8874 .loc 1 4249 23 view .LVU3164 + 8875 013a 43F08003 orr r3, r3, #128 + 8876 013e 6364 str r3, [r4, #68] +4252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8877 .loc 1 4252 7 is_stmt 1 view .LVU3165 +4252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8878 .loc 1 4252 7 view .LVU3166 + 8879 0140 84F84020 strb r2, [r4, #64] +4252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8880 .loc 1 4252 7 view .LVU3167 +4254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8881 .loc 1 4254 7 view .LVU3168 +4254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8882 .loc 1 4254 14 is_stmt 0 view .LVU3169 + 8883 0144 0125 movs r5, #1 + 8884 .LVL586: +4254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8885 .loc 1 4254 14 view .LVU3170 + 8886 0146 1EE0 b .L541 + 8887 .LVL587: + 8888 .L547: +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8889 .loc 1 4260 7 is_stmt 1 view .LVU3171 +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8890 .loc 1 4260 11 is_stmt 0 view .LVU3172 + 8891 0148 638D ldrh r3, [r4, #42] + 8892 014a 9BB2 uxth r3, r3 +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8893 .loc 1 4260 30 view .LVU3173 + 8894 014c 228D ldrh r2, [r4, #40] +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8895 .loc 1 4260 23 view .LVU3174 + 8896 014e 9B1A subs r3, r3, r2 + 8897 0150 9BB2 uxth r3, r3 + 8898 0152 6385 strh r3, [r4, #42] @ movhi +4263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8899 .loc 1 4263 7 is_stmt 1 view .LVU3175 +4263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8900 .loc 1 4263 22 is_stmt 0 view .LVU3176 + 8901 0154 0023 movs r3, #0 + 8902 0156 2385 strh r3, [r4, #40] @ movhi +4280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8903 .loc 1 4280 5 is_stmt 1 view .LVU3177 +4280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8904 .loc 1 4280 9 is_stmt 0 view .LVU3178 + 8905 0158 2368 ldr r3, [r4] + 8906 015a 9A69 ldr r2, [r3, #24] +4280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8907 .loc 1 4280 8 view .LVU3179 + ARM GAS /tmp/ccE2rRGE.s page 329 + + + 8908 015c 12F4803F tst r2, #65536 + 8909 0160 0DD0 beq .L549 + 8910 .L550: +4288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8911 .loc 1 4288 5 is_stmt 1 view .LVU3180 +4288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8912 .loc 1 4288 5 view .LVU3181 + 8913 0162 0023 movs r3, #0 + 8914 0164 84F84030 strb r3, [r4, #64] +4288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8915 .loc 1 4288 5 view .LVU3182 +4294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8916 .loc 1 4294 5 view .LVU3183 + 8917 0168 48F20201 movw r1, #32770 + 8918 016c 2046 mov r0, r4 + 8919 .LVL588: +4294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8920 .loc 1 4294 5 is_stmt 0 view .LVU3184 + 8921 016e FFF7FEFF bl I2C_Enable_IRQ + 8922 .LVL589: +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8923 .loc 1 4297 5 is_stmt 1 view .LVU3185 +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8924 .loc 1 4297 9 is_stmt 0 view .LVU3186 + 8925 0172 2268 ldr r2, [r4] +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8926 .loc 1 4297 19 view .LVU3187 + 8927 0174 1368 ldr r3, [r2] +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8928 .loc 1 4297 25 view .LVU3188 + 8929 0176 43F40043 orr r3, r3, #32768 + 8930 017a 1360 str r3, [r2] +4299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8931 .loc 1 4299 5 is_stmt 1 view .LVU3189 +4299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8932 .loc 1 4299 12 is_stmt 0 view .LVU3190 + 8933 017c 03E0 b .L541 + 8934 .LVL590: + 8935 .L549: +4284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8936 .loc 1 4284 7 is_stmt 1 view .LVU3191 + 8937 017e 0822 movs r2, #8 + 8938 0180 DA61 str r2, [r3, #28] + 8939 0182 EEE7 b .L550 + 8940 .LVL591: + 8941 .L551: +4303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8942 .loc 1 4303 12 is_stmt 0 view .LVU3192 + 8943 0184 0125 movs r5, #1 + 8944 .LVL592: + 8945 .L541: +4305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8946 .loc 1 4305 1 view .LVU3193 + 8947 0186 2846 mov r0, r5 + 8948 0188 F8BD pop {r3, r4, r5, r6, r7, pc} + 8949 .LVL593: + 8950 .L552: + ARM GAS /tmp/ccE2rRGE.s page 330 + + +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8951 .loc 1 4156 5 view .LVU3194 + 8952 018a 0225 movs r5, #2 + 8953 .LVL594: +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8954 .loc 1 4156 5 view .LVU3195 + 8955 018c FBE7 b .L541 + 8956 .L558: + 8957 018e 00BF .align 2 + 8958 .L557: + 8959 0190 00000000 .word I2C_Slave_ISR_DMA + 8960 0194 00000000 .word I2C_DMASlaveReceiveCplt + 8961 0198 00000000 .word I2C_DMAError + 8962 019c 00000000 .word I2C_DMAAbort + 8963 .cfi_endproc + 8964 .LFE160: + 8966 .section .text.HAL_I2C_EnableListen_IT,"ax",%progbits + 8967 .align 1 + 8968 .global HAL_I2C_EnableListen_IT + 8969 .syntax unified + 8970 .thumb + 8971 .thumb_func + 8973 HAL_I2C_EnableListen_IT: + 8974 .LVL595: + 8975 .LFB161: +4314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 8976 .loc 1 4314 1 is_stmt 1 view -0 + 8977 .cfi_startproc + 8978 @ args = 0, pretend = 0, frame = 0 + 8979 @ frame_needed = 0, uses_anonymous_args = 0 +4314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 8980 .loc 1 4314 1 is_stmt 0 view .LVU3197 + 8981 0000 08B5 push {r3, lr} + 8982 .cfi_def_cfa_offset 8 + 8983 .cfi_offset 3, -8 + 8984 .cfi_offset 14, -4 +4315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8985 .loc 1 4315 3 is_stmt 1 view .LVU3198 +4315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8986 .loc 1 4315 11 is_stmt 0 view .LVU3199 + 8987 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 8988 0006 DBB2 uxtb r3, r3 +4315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8989 .loc 1 4315 6 view .LVU3200 + 8990 0008 202B cmp r3, #32 + 8991 000a 01D0 beq .L563 +4327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8992 .loc 1 4327 12 view .LVU3201 + 8993 000c 0220 movs r0, #2 + 8994 .LVL596: + 8995 .L560: +4329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8996 .loc 1 4329 1 view .LVU3202 + 8997 000e 08BD pop {r3, pc} + 8998 .LVL597: + 8999 .L563: +4317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + ARM GAS /tmp/ccE2rRGE.s page 331 + + + 9000 .loc 1 4317 5 is_stmt 1 view .LVU3203 +4317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9001 .loc 1 4317 17 is_stmt 0 view .LVU3204 + 9002 0010 2823 movs r3, #40 + 9003 0012 80F84130 strb r3, [r0, #65] +4318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9004 .loc 1 4318 5 is_stmt 1 view .LVU3205 +4318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9005 .loc 1 4318 19 is_stmt 0 view .LVU3206 + 9006 0016 044B ldr r3, .L564 + 9007 0018 4363 str r3, [r0, #52] +4321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9008 .loc 1 4321 5 is_stmt 1 view .LVU3207 + 9009 001a 4FF40041 mov r1, #32768 + 9010 001e FFF7FEFF bl I2C_Enable_IRQ + 9011 .LVL598: +4323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9012 .loc 1 4323 5 view .LVU3208 +4323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9013 .loc 1 4323 12 is_stmt 0 view .LVU3209 + 9014 0022 0020 movs r0, #0 + 9015 0024 F3E7 b .L560 + 9016 .L565: + 9017 0026 00BF .align 2 + 9018 .L564: + 9019 0028 00000000 .word I2C_Slave_ISR_IT + 9020 .cfi_endproc + 9021 .LFE161: + 9023 .section .text.HAL_I2C_DisableListen_IT,"ax",%progbits + 9024 .align 1 + 9025 .global HAL_I2C_DisableListen_IT + 9026 .syntax unified + 9027 .thumb + 9028 .thumb_func + 9030 HAL_I2C_DisableListen_IT: + 9031 .LVL599: + 9032 .LFB162: +4338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9033 .loc 1 4338 1 is_stmt 1 view -0 + 9034 .cfi_startproc + 9035 @ args = 0, pretend = 0, frame = 0 + 9036 @ frame_needed = 0, uses_anonymous_args = 0 +4340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9037 .loc 1 4340 3 view .LVU3211 +4343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9038 .loc 1 4343 3 view .LVU3212 +4343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9039 .loc 1 4343 11 is_stmt 0 view .LVU3213 + 9040 0000 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9041 0004 DBB2 uxtb r3, r3 +4343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9042 .loc 1 4343 6 view .LVU3214 + 9043 0006 282B cmp r3, #40 + 9044 0008 01D0 beq .L573 +4358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9045 .loc 1 4358 12 view .LVU3215 + 9046 000a 0220 movs r0, #2 + ARM GAS /tmp/ccE2rRGE.s page 332 + + + 9047 .LVL600: +4360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9048 .loc 1 4360 1 view .LVU3216 + 9049 000c 7047 bx lr + 9050 .LVL601: + 9051 .L573: +4338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9052 .loc 1 4338 1 view .LVU3217 + 9053 000e 10B5 push {r4, lr} + 9054 .cfi_def_cfa_offset 8 + 9055 .cfi_offset 4, -8 + 9056 .cfi_offset 14, -4 +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 9057 .loc 1 4345 5 is_stmt 1 view .LVU3218 +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 9058 .loc 1 4345 26 is_stmt 0 view .LVU3219 + 9059 0010 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 9060 .LVL602: +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9061 .loc 1 4346 5 is_stmt 1 view .LVU3220 +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9062 .loc 1 4346 48 is_stmt 0 view .LVU3221 + 9063 0014 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9064 .loc 1 4346 31 view .LVU3222 + 9065 0018 02F00302 and r2, r2, #3 + 9066 .LVL603: +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9067 .loc 1 4346 31 view .LVU3223 + 9068 001c 1343 orrs r3, r3, r2 +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9069 .loc 1 4346 25 view .LVU3224 + 9070 001e 0363 str r3, [r0, #48] +4347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9071 .loc 1 4347 5 is_stmt 1 view .LVU3225 +4347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9072 .loc 1 4347 17 is_stmt 0 view .LVU3226 + 9073 0020 2023 movs r3, #32 + 9074 0022 80F84130 strb r3, [r0, #65] +4348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9075 .loc 1 4348 5 is_stmt 1 view .LVU3227 +4348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9076 .loc 1 4348 16 is_stmt 0 view .LVU3228 + 9077 0026 0024 movs r4, #0 + 9078 0028 80F84240 strb r4, [r0, #66] +4349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9079 .loc 1 4349 5 is_stmt 1 view .LVU3229 +4349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9080 .loc 1 4349 19 is_stmt 0 view .LVU3230 + 9081 002c 4463 str r4, [r0, #52] +4352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9082 .loc 1 4352 5 is_stmt 1 view .LVU3231 + 9083 002e 4FF40041 mov r1, #32768 + 9084 0032 FFF7FEFF bl I2C_Disable_IRQ + 9085 .LVL604: +4354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9086 .loc 1 4354 5 view .LVU3232 + ARM GAS /tmp/ccE2rRGE.s page 333 + + +4354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9087 .loc 1 4354 12 is_stmt 0 view .LVU3233 + 9088 0036 2046 mov r0, r4 +4360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9089 .loc 1 4360 1 view .LVU3234 + 9090 0038 10BD pop {r4, pc} + 9091 .cfi_endproc + 9092 .LFE162: + 9094 .section .text.HAL_I2C_Master_Abort_IT,"ax",%progbits + 9095 .align 1 + 9096 .global HAL_I2C_Master_Abort_IT + 9097 .syntax unified + 9098 .thumb + 9099 .thumb_func + 9101 HAL_I2C_Master_Abort_IT: + 9102 .LVL605: + 9103 .LFB163: +4371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) + 9104 .loc 1 4371 1 is_stmt 1 view -0 + 9105 .cfi_startproc + 9106 @ args = 0, pretend = 0, frame = 0 + 9107 @ frame_needed = 0, uses_anonymous_args = 0 +4372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9108 .loc 1 4372 3 view .LVU3236 +4372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9109 .loc 1 4372 11 is_stmt 0 view .LVU3237 + 9110 0000 90F84230 ldrb r3, [r0, #66] @ zero_extendqisi2 + 9111 0004 DBB2 uxtb r3, r3 +4372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9112 .loc 1 4372 6 view .LVU3238 + 9113 0006 102B cmp r3, #16 + 9114 0008 36D1 bne .L578 +4371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) + 9115 .loc 1 4371 1 view .LVU3239 + 9116 000a 30B5 push {r4, r5, lr} + 9117 .cfi_def_cfa_offset 12 + 9118 .cfi_offset 4, -12 + 9119 .cfi_offset 5, -8 + 9120 .cfi_offset 14, -4 + 9121 000c 83B0 sub sp, sp, #12 + 9122 .cfi_def_cfa_offset 24 + 9123 000e 0446 mov r4, r0 + 9124 0010 0D46 mov r5, r1 +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9125 .loc 1 4375 5 is_stmt 1 view .LVU3240 +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9126 .loc 1 4375 5 view .LVU3241 + 9127 0012 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 9128 0016 012B cmp r3, #1 + 9129 0018 30D0 beq .L579 +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9130 .loc 1 4375 5 discriminator 2 view .LVU3242 + 9131 001a 0123 movs r3, #1 + 9132 001c 80F84030 strb r3, [r0, #64] +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9133 .loc 1 4375 5 discriminator 2 view .LVU3243 +4378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 334 + + + 9134 .loc 1 4378 5 discriminator 2 view .LVU3244 +4378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9135 .loc 1 4378 13 is_stmt 0 discriminator 2 view .LVU3245 + 9136 0020 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9137 0024 DBB2 uxtb r3, r3 +4378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9138 .loc 1 4378 8 discriminator 2 view .LVU3246 + 9139 0026 212B cmp r3, #33 + 9140 0028 1AD0 beq .L584 +4383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9141 .loc 1 4383 10 is_stmt 1 view .LVU3247 +4383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9142 .loc 1 4383 18 is_stmt 0 view .LVU3248 + 9143 002a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9144 002e DBB2 uxtb r3, r3 +4383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9145 .loc 1 4383 13 view .LVU3249 + 9146 0030 222B cmp r3, #34 + 9147 0032 1BD0 beq .L585 + 9148 .LVL606: + 9149 .L577: +4391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9150 .loc 1 4391 5 is_stmt 1 view .LVU3250 +4394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9151 .loc 1 4394 5 view .LVU3251 +4394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9152 .loc 1 4394 17 is_stmt 0 view .LVU3252 + 9153 0034 6023 movs r3, #96 + 9154 0036 84F84130 strb r3, [r4, #65] +4398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9155 .loc 1 4398 5 is_stmt 1 view .LVU3253 + 9156 003a 114B ldr r3, .L586 + 9157 003c 0093 str r3, [sp] + 9158 003e 4FF00073 mov r3, #33554432 + 9159 0042 0122 movs r2, #1 + 9160 0044 2946 mov r1, r5 + 9161 0046 2046 mov r0, r4 + 9162 0048 FFF7FEFF bl I2C_TransferConfig + 9163 .LVL607: +4401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9164 .loc 1 4401 5 view .LVU3254 +4401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9165 .loc 1 4401 5 view .LVU3255 + 9166 004c 0025 movs r5, #0 + 9167 004e 84F84050 strb r5, [r4, #64] +4401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9168 .loc 1 4401 5 view .LVU3256 +4406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9169 .loc 1 4406 5 view .LVU3257 + 9170 0052 2021 movs r1, #32 + 9171 0054 2046 mov r0, r4 + 9172 0056 FFF7FEFF bl I2C_Enable_IRQ + 9173 .LVL608: +4408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9174 .loc 1 4408 5 view .LVU3258 +4408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9175 .loc 1 4408 12 is_stmt 0 view .LVU3259 + ARM GAS /tmp/ccE2rRGE.s page 335 + + + 9176 005a 2846 mov r0, r5 + 9177 .L575: +4416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9178 .loc 1 4416 1 view .LVU3260 + 9179 005c 03B0 add sp, sp, #12 + 9180 .cfi_remember_state + 9181 .cfi_def_cfa_offset 12 + 9182 @ sp needed + 9183 005e 30BD pop {r4, r5, pc} + 9184 .LVL609: + 9185 .L584: + 9186 .cfi_restore_state +4380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9187 .loc 1 4380 7 is_stmt 1 view .LVU3261 + 9188 0060 0121 movs r1, #1 + 9189 .LVL610: +4380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9190 .loc 1 4380 7 is_stmt 0 view .LVU3262 + 9191 0062 FFF7FEFF bl I2C_Disable_IRQ + 9192 .LVL611: +4381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9193 .loc 1 4381 7 is_stmt 1 view .LVU3263 +4381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9194 .loc 1 4381 27 is_stmt 0 view .LVU3264 + 9195 0066 1123 movs r3, #17 + 9196 0068 2363 str r3, [r4, #48] + 9197 006a E3E7 b .L577 + 9198 .LVL612: + 9199 .L585: +4385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 9200 .loc 1 4385 7 is_stmt 1 view .LVU3265 + 9201 006c 0221 movs r1, #2 + 9202 .LVL613: +4385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 9203 .loc 1 4385 7 is_stmt 0 view .LVU3266 + 9204 006e FFF7FEFF bl I2C_Disable_IRQ + 9205 .LVL614: +4386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9206 .loc 1 4386 7 is_stmt 1 view .LVU3267 +4386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9207 .loc 1 4386 27 is_stmt 0 view .LVU3268 + 9208 0072 1223 movs r3, #18 + 9209 0074 2363 str r3, [r4, #48] + 9210 0076 DDE7 b .L577 + 9211 .LVL615: + 9212 .L578: + 9213 .cfi_def_cfa_offset 0 + 9214 .cfi_restore 4 + 9215 .cfi_restore 5 + 9216 .cfi_restore 14 +4414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9217 .loc 1 4414 12 view .LVU3269 + 9218 0078 0120 movs r0, #1 + 9219 .LVL616: +4416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9220 .loc 1 4416 1 view .LVU3270 + 9221 007a 7047 bx lr + ARM GAS /tmp/ccE2rRGE.s page 336 + + + 9222 .LVL617: + 9223 .L579: + 9224 .cfi_def_cfa_offset 24 + 9225 .cfi_offset 4, -12 + 9226 .cfi_offset 5, -8 + 9227 .cfi_offset 14, -4 +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9228 .loc 1 4375 5 view .LVU3271 + 9229 007c 0220 movs r0, #2 + 9230 .LVL618: +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9231 .loc 1 4375 5 view .LVU3272 + 9232 007e EDE7 b .L575 + 9233 .L587: + 9234 .align 2 + 9235 .L586: + 9236 0080 00400080 .word -2147467264 + 9237 .cfi_endproc + 9238 .LFE163: + 9240 .section .text.HAL_I2C_EV_IRQHandler,"ax",%progbits + 9241 .align 1 + 9242 .global HAL_I2C_EV_IRQHandler + 9243 .syntax unified + 9244 .thumb + 9245 .thumb_func + 9247 HAL_I2C_EV_IRQHandler: + 9248 .LVL619: + 9249 .LFB164: +4433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 9250 .loc 1 4433 1 is_stmt 1 view -0 + 9251 .cfi_startproc + 9252 @ args = 0, pretend = 0, frame = 0 + 9253 @ frame_needed = 0, uses_anonymous_args = 0 +4433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 9254 .loc 1 4433 1 is_stmt 0 view .LVU3274 + 9255 0000 08B5 push {r3, lr} + 9256 .cfi_def_cfa_offset 8 + 9257 .cfi_offset 3, -8 + 9258 .cfi_offset 14, -4 +4435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 9259 .loc 1 4435 3 is_stmt 1 view .LVU3275 +4435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 9260 .loc 1 4435 24 is_stmt 0 view .LVU3276 + 9261 0002 0368 ldr r3, [r0] +4435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 9262 .loc 1 4435 12 view .LVU3277 + 9263 0004 9969 ldr r1, [r3, #24] + 9264 .LVL620: +4436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9265 .loc 1 4436 3 is_stmt 1 view .LVU3278 +4436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9266 .loc 1 4436 12 is_stmt 0 view .LVU3279 + 9267 0006 1A68 ldr r2, [r3] + 9268 .LVL621: +4439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9269 .loc 1 4439 3 is_stmt 1 view .LVU3280 +4439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 337 + + + 9270 .loc 1 4439 11 is_stmt 0 view .LVU3281 + 9271 0008 436B ldr r3, [r0, #52] +4439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9272 .loc 1 4439 6 view .LVU3282 + 9273 000a 03B1 cbz r3, .L588 +4441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9274 .loc 1 4441 5 is_stmt 1 view .LVU3283 + 9275 000c 9847 blx r3 + 9276 .LVL622: + 9277 .L588: +4443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9278 .loc 1 4443 1 is_stmt 0 view .LVU3284 + 9279 000e 08BD pop {r3, pc} + 9280 .cfi_endproc + 9281 .LFE164: + 9283 .section .text.HAL_I2C_MasterTxCpltCallback,"ax",%progbits + 9284 .align 1 + 9285 .weak HAL_I2C_MasterTxCpltCallback + 9286 .syntax unified + 9287 .thumb + 9288 .thumb_func + 9290 HAL_I2C_MasterTxCpltCallback: + 9291 .LVL623: + 9292 .LFB166: +4504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9293 .loc 1 4504 1 is_stmt 1 view -0 + 9294 .cfi_startproc + 9295 @ args = 0, pretend = 0, frame = 0 + 9296 @ frame_needed = 0, uses_anonymous_args = 0 + 9297 @ link register save eliminated. +4506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9298 .loc 1 4506 3 view .LVU3286 +4511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9299 .loc 1 4511 1 is_stmt 0 view .LVU3287 + 9300 0000 7047 bx lr + 9301 .cfi_endproc + 9302 .LFE166: + 9304 .section .text.HAL_I2C_MasterRxCpltCallback,"ax",%progbits + 9305 .align 1 + 9306 .weak HAL_I2C_MasterRxCpltCallback + 9307 .syntax unified + 9308 .thumb + 9309 .thumb_func + 9311 HAL_I2C_MasterRxCpltCallback: + 9312 .LVL624: + 9313 .LFB167: +4520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9314 .loc 1 4520 1 is_stmt 1 view -0 + 9315 .cfi_startproc + 9316 @ args = 0, pretend = 0, frame = 0 + 9317 @ frame_needed = 0, uses_anonymous_args = 0 + 9318 @ link register save eliminated. +4522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9319 .loc 1 4522 3 view .LVU3289 +4527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9320 .loc 1 4527 1 is_stmt 0 view .LVU3290 + 9321 0000 7047 bx lr + ARM GAS /tmp/ccE2rRGE.s page 338 + + + 9322 .cfi_endproc + 9323 .LFE167: + 9325 .section .text.I2C_ITMasterSeqCplt,"ax",%progbits + 9326 .align 1 + 9327 .syntax unified + 9328 .thumb + 9329 .thumb_func + 9331 I2C_ITMasterSeqCplt: + 9332 .LVL625: + 9333 .LFB186: +5505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset I2C handle mode */ + 9334 .loc 1 5505 1 is_stmt 1 view -0 + 9335 .cfi_startproc + 9336 @ args = 0, pretend = 0, frame = 0 + 9337 @ frame_needed = 0, uses_anonymous_args = 0 +5505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset I2C handle mode */ + 9338 .loc 1 5505 1 is_stmt 0 view .LVU3292 + 9339 0000 38B5 push {r3, r4, r5, lr} + 9340 .cfi_def_cfa_offset 16 + 9341 .cfi_offset 3, -16 + 9342 .cfi_offset 4, -12 + 9343 .cfi_offset 5, -8 + 9344 .cfi_offset 14, -4 + 9345 0002 0446 mov r4, r0 +5507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9346 .loc 1 5507 3 is_stmt 1 view .LVU3293 +5507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9347 .loc 1 5507 14 is_stmt 0 view .LVU3294 + 9348 0004 0023 movs r3, #0 + 9349 0006 80F84230 strb r3, [r0, #66] +5511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9350 .loc 1 5511 3 is_stmt 1 view .LVU3295 +5511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9351 .loc 1 5511 11 is_stmt 0 view .LVU3296 + 9352 000a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 9353 000e DBB2 uxtb r3, r3 +5511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9354 .loc 1 5511 6 view .LVU3297 + 9355 0010 212B cmp r3, #33 + 9356 0012 0FD0 beq .L597 +5533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 9357 .loc 1 5533 5 is_stmt 1 view .LVU3298 +5533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 9358 .loc 1 5533 25 is_stmt 0 view .LVU3299 + 9359 0014 2023 movs r3, #32 + 9360 0016 80F84130 strb r3, [r0, #65] +5534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9361 .loc 1 5534 5 is_stmt 1 view .LVU3300 +5534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9362 .loc 1 5534 25 is_stmt 0 view .LVU3301 + 9363 001a 1223 movs r3, #18 + 9364 001c 0363 str r3, [r0, #48] +5535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9365 .loc 1 5535 5 is_stmt 1 view .LVU3302 +5535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9366 .loc 1 5535 25 is_stmt 0 view .LVU3303 + 9367 001e 0025 movs r5, #0 + ARM GAS /tmp/ccE2rRGE.s page 339 + + + 9368 0020 4563 str r5, [r0, #52] +5538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9369 .loc 1 5538 5 is_stmt 1 view .LVU3304 + 9370 0022 0221 movs r1, #2 + 9371 0024 FFF7FEFF bl I2C_Disable_IRQ + 9372 .LVL626: +5541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9373 .loc 1 5541 5 view .LVU3305 +5541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9374 .loc 1 5541 5 view .LVU3306 + 9375 0028 84F84050 strb r5, [r4, #64] +5541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9376 .loc 1 5541 5 view .LVU3307 +5547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9377 .loc 1 5547 5 view .LVU3308 + 9378 002c 2046 mov r0, r4 + 9379 002e FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 9380 .LVL627: + 9381 .L593: +5550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9382 .loc 1 5550 1 is_stmt 0 view .LVU3309 + 9383 0032 38BD pop {r3, r4, r5, pc} + 9384 .LVL628: + 9385 .L597: +5513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9386 .loc 1 5513 5 is_stmt 1 view .LVU3310 +5513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 9387 .loc 1 5513 25 is_stmt 0 view .LVU3311 + 9388 0034 2023 movs r3, #32 + 9389 0036 80F84130 strb r3, [r0, #65] +5514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9390 .loc 1 5514 5 is_stmt 1 view .LVU3312 +5514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9391 .loc 1 5514 25 is_stmt 0 view .LVU3313 + 9392 003a 1123 movs r3, #17 + 9393 003c 0363 str r3, [r0, #48] +5515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9394 .loc 1 5515 5 is_stmt 1 view .LVU3314 +5515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9395 .loc 1 5515 25 is_stmt 0 view .LVU3315 + 9396 003e 0025 movs r5, #0 + 9397 0040 4563 str r5, [r0, #52] +5518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9398 .loc 1 5518 5 is_stmt 1 view .LVU3316 + 9399 0042 0121 movs r1, #1 + 9400 0044 FFF7FEFF bl I2C_Disable_IRQ + 9401 .LVL629: +5521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9402 .loc 1 5521 5 view .LVU3317 +5521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9403 .loc 1 5521 5 view .LVU3318 + 9404 0048 84F84050 strb r5, [r4, #64] +5521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9405 .loc 1 5521 5 view .LVU3319 +5527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9406 .loc 1 5527 5 view .LVU3320 + 9407 004c 2046 mov r0, r4 + ARM GAS /tmp/ccE2rRGE.s page 340 + + + 9408 004e FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 9409 .LVL630: + 9410 0052 EEE7 b .L593 + 9411 .cfi_endproc + 9412 .LFE186: + 9414 .section .text.HAL_I2C_SlaveTxCpltCallback,"ax",%progbits + 9415 .align 1 + 9416 .weak HAL_I2C_SlaveTxCpltCallback + 9417 .syntax unified + 9418 .thumb + 9419 .thumb_func + 9421 HAL_I2C_SlaveTxCpltCallback: + 9422 .LVL631: + 9423 .LFB168: +4535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9424 .loc 1 4535 1 view -0 + 9425 .cfi_startproc + 9426 @ args = 0, pretend = 0, frame = 0 + 9427 @ frame_needed = 0, uses_anonymous_args = 0 + 9428 @ link register save eliminated. +4537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9429 .loc 1 4537 3 view .LVU3322 +4542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9430 .loc 1 4542 1 is_stmt 0 view .LVU3323 + 9431 0000 7047 bx lr + 9432 .cfi_endproc + 9433 .LFE168: + 9435 .section .text.HAL_I2C_SlaveRxCpltCallback,"ax",%progbits + 9436 .align 1 + 9437 .weak HAL_I2C_SlaveRxCpltCallback + 9438 .syntax unified + 9439 .thumb + 9440 .thumb_func + 9442 HAL_I2C_SlaveRxCpltCallback: + 9443 .LVL632: + 9444 .LFB169: +4551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9445 .loc 1 4551 1 is_stmt 1 view -0 + 9446 .cfi_startproc + 9447 @ args = 0, pretend = 0, frame = 0 + 9448 @ frame_needed = 0, uses_anonymous_args = 0 + 9449 @ link register save eliminated. +4553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9450 .loc 1 4553 3 view .LVU3325 +4558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9451 .loc 1 4558 1 is_stmt 0 view .LVU3326 + 9452 0000 7047 bx lr + 9453 .cfi_endproc + 9454 .LFE169: + 9456 .section .text.I2C_ITSlaveSeqCplt,"ax",%progbits + 9457 .align 1 + 9458 .syntax unified + 9459 .thumb + 9460 .thumb_func + 9462 I2C_ITSlaveSeqCplt: + 9463 .LVL633: + 9464 .LFB187: + ARM GAS /tmp/ccE2rRGE.s page 341 + + +5558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 9465 .loc 1 5558 1 is_stmt 1 view -0 + 9466 .cfi_startproc + 9467 @ args = 0, pretend = 0, frame = 0 + 9468 @ frame_needed = 0, uses_anonymous_args = 0 +5558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 9469 .loc 1 5558 1 is_stmt 0 view .LVU3328 + 9470 0000 10B5 push {r4, lr} + 9471 .cfi_def_cfa_offset 8 + 9472 .cfi_offset 4, -8 + 9473 .cfi_offset 14, -4 + 9474 0002 0446 mov r4, r0 +5559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9475 .loc 1 5559 3 is_stmt 1 view .LVU3329 +5559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9476 .loc 1 5559 26 is_stmt 0 view .LVU3330 + 9477 0004 0368 ldr r3, [r0] +5559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9478 .loc 1 5559 12 view .LVU3331 + 9479 0006 1A68 ldr r2, [r3] + 9480 .LVL634: +5562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9481 .loc 1 5562 3 is_stmt 1 view .LVU3332 +5562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9482 .loc 1 5562 14 is_stmt 0 view .LVU3333 + 9483 0008 0021 movs r1, #0 + 9484 000a 80F84210 strb r1, [r0, #66] +5565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9485 .loc 1 5565 3 is_stmt 1 view .LVU3334 +5565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9486 .loc 1 5565 6 is_stmt 0 view .LVU3335 + 9487 000e 12F4804F tst r2, #16384 + 9488 0012 0ED0 beq .L601 +5568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9489 .loc 1 5568 5 is_stmt 1 view .LVU3336 +5568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9490 .loc 1 5568 19 is_stmt 0 view .LVU3337 + 9491 0014 1A68 ldr r2, [r3] + 9492 .LVL635: +5568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9493 .loc 1 5568 25 view .LVU3338 + 9494 0016 22F48042 bic r2, r2, #16384 + 9495 001a 1A60 str r2, [r3] + 9496 .L602: +5578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9497 .loc 1 5578 3 is_stmt 1 view .LVU3339 +5580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9498 .loc 1 5580 3 view .LVU3340 +5580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9499 .loc 1 5580 11 is_stmt 0 view .LVU3341 + 9500 001c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 9501 0020 DBB2 uxtb r3, r3 +5580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9502 .loc 1 5580 6 view .LVU3342 + 9503 0022 292B cmp r3, #41 + 9504 0024 0DD0 beq .L606 +5600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 342 + + + 9505 .loc 1 5600 8 is_stmt 1 view .LVU3343 +5600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9506 .loc 1 5600 16 is_stmt 0 view .LVU3344 + 9507 0026 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 9508 002a DBB2 uxtb r3, r3 +5600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9509 .loc 1 5600 11 view .LVU3345 + 9510 002c 2A2B cmp r3, #42 + 9511 002e 18D0 beq .L607 + 9512 .LVL636: + 9513 .L600: +5623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9514 .loc 1 5623 1 view .LVU3346 + 9515 0030 10BD pop {r4, pc} + 9516 .LVL637: + 9517 .L601: +5570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9518 .loc 1 5570 8 is_stmt 1 view .LVU3347 +5570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9519 .loc 1 5570 11 is_stmt 0 view .LVU3348 + 9520 0032 12F4004F tst r2, #32768 + 9521 0036 F1D0 beq .L602 +5573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9522 .loc 1 5573 5 is_stmt 1 view .LVU3349 +5573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9523 .loc 1 5573 19 is_stmt 0 view .LVU3350 + 9524 0038 1A68 ldr r2, [r3] + 9525 .LVL638: +5573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9526 .loc 1 5573 25 view .LVU3351 + 9527 003a 22F40042 bic r2, r2, #32768 + 9528 003e 1A60 str r2, [r3] + 9529 0040 ECE7 b .L602 + 9530 .L606: +5583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 9531 .loc 1 5583 5 is_stmt 1 view .LVU3352 +5583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 9532 .loc 1 5583 25 is_stmt 0 view .LVU3353 + 9533 0042 2823 movs r3, #40 + 9534 0044 84F84130 strb r3, [r4, #65] +5584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9535 .loc 1 5584 5 is_stmt 1 view .LVU3354 +5584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9536 .loc 1 5584 25 is_stmt 0 view .LVU3355 + 9537 0048 2123 movs r3, #33 + 9538 004a 2363 str r3, [r4, #48] +5587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9539 .loc 1 5587 5 is_stmt 1 view .LVU3356 + 9540 004c 0121 movs r1, #1 + 9541 004e 2046 mov r0, r4 + 9542 .LVL639: +5587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9543 .loc 1 5587 5 is_stmt 0 view .LVU3357 + 9544 0050 FFF7FEFF bl I2C_Disable_IRQ + 9545 .LVL640: +5590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9546 .loc 1 5590 5 is_stmt 1 view .LVU3358 + ARM GAS /tmp/ccE2rRGE.s page 343 + + +5590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9547 .loc 1 5590 5 view .LVU3359 + 9548 0054 0023 movs r3, #0 + 9549 0056 84F84030 strb r3, [r4, #64] +5590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9550 .loc 1 5590 5 view .LVU3360 +5596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9551 .loc 1 5596 5 view .LVU3361 + 9552 005a 2046 mov r0, r4 + 9553 005c FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 9554 .LVL641: + 9555 0060 E6E7 b .L600 + 9556 .LVL642: + 9557 .L607: +5603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 9558 .loc 1 5603 5 view .LVU3362 +5603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 9559 .loc 1 5603 25 is_stmt 0 view .LVU3363 + 9560 0062 2823 movs r3, #40 + 9561 0064 84F84130 strb r3, [r4, #65] +5604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9562 .loc 1 5604 5 is_stmt 1 view .LVU3364 +5604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9563 .loc 1 5604 25 is_stmt 0 view .LVU3365 + 9564 0068 2223 movs r3, #34 + 9565 006a 2363 str r3, [r4, #48] +5607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9566 .loc 1 5607 5 is_stmt 1 view .LVU3366 + 9567 006c 0221 movs r1, #2 + 9568 006e 2046 mov r0, r4 + 9569 .LVL643: +5607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9570 .loc 1 5607 5 is_stmt 0 view .LVU3367 + 9571 0070 FFF7FEFF bl I2C_Disable_IRQ + 9572 .LVL644: +5610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9573 .loc 1 5610 5 is_stmt 1 view .LVU3368 +5610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9574 .loc 1 5610 5 view .LVU3369 + 9575 0074 0023 movs r3, #0 + 9576 0076 84F84030 strb r3, [r4, #64] +5610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9577 .loc 1 5610 5 view .LVU3370 +5616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9578 .loc 1 5616 5 view .LVU3371 + 9579 007a 2046 mov r0, r4 + 9580 007c FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 9581 .LVL645: +5622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9582 .loc 1 5622 3 view .LVU3372 +5623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9583 .loc 1 5623 1 is_stmt 0 view .LVU3373 + 9584 0080 D6E7 b .L600 + 9585 .cfi_endproc + 9586 .LFE187: + 9588 .section .text.I2C_DMASlaveTransmitCplt,"ax",%progbits + 9589 .align 1 + ARM GAS /tmp/ccE2rRGE.s page 344 + + + 9590 .syntax unified + 9591 .thumb + 9592 .thumb_func + 9594 I2C_DMASlaveTransmitCplt: + 9595 .LVL646: + 9596 .LFB195: +6206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 9597 .loc 1 6206 1 is_stmt 1 view -0 + 9598 .cfi_startproc + 9599 @ args = 0, pretend = 0, frame = 0 + 9600 @ frame_needed = 0, uses_anonymous_args = 0 +6206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 9601 .loc 1 6206 1 is_stmt 0 view .LVU3375 + 9602 0000 08B5 push {r3, lr} + 9603 .cfi_def_cfa_offset 8 + 9604 .cfi_offset 3, -8 + 9605 .cfi_offset 14, -4 +6208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9606 .loc 1 6208 3 is_stmt 1 view .LVU3376 +6208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9607 .loc 1 6208 22 is_stmt 0 view .LVU3377 + 9608 0002 406A ldr r0, [r0, #36] + 9609 .LVL647: +6209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9610 .loc 1 6209 3 is_stmt 1 view .LVU3378 +6209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9611 .loc 1 6209 12 is_stmt 0 view .LVU3379 + 9612 0004 C36A ldr r3, [r0, #44] + 9613 .LVL648: +6211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9614 .loc 1 6211 3 is_stmt 1 view .LVU3380 +6211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9615 .loc 1 6211 6 is_stmt 0 view .LVU3381 + 9616 0006 B3F1807F cmp r3, #16777216 + 9617 000a 00D0 beq .L609 +6211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9618 .loc 1 6211 38 discriminator 1 view .LVU3382 + 9619 000c 33B9 cbnz r3, .L608 + 9620 .L609: +6214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9621 .loc 1 6214 5 is_stmt 1 view .LVU3383 +6214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9622 .loc 1 6214 9 is_stmt 0 view .LVU3384 + 9623 000e 0268 ldr r2, [r0] +6214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9624 .loc 1 6214 19 view .LVU3385 + 9625 0010 1368 ldr r3, [r2] + 9626 .LVL649: +6214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9627 .loc 1 6214 25 view .LVU3386 + 9628 0012 23F48043 bic r3, r3, #16384 + 9629 0016 1360 str r3, [r2] +6218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9630 .loc 1 6218 5 is_stmt 1 view .LVU3387 + 9631 0018 FFF7FEFF bl I2C_ITSlaveSeqCplt + 9632 .LVL650: + 9633 .L608: + ARM GAS /tmp/ccE2rRGE.s page 345 + + +6226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9634 .loc 1 6226 1 is_stmt 0 view .LVU3388 + 9635 001c 08BD pop {r3, pc} + 9636 .cfi_endproc + 9637 .LFE195: + 9639 .section .text.I2C_DMASlaveReceiveCplt,"ax",%progbits + 9640 .align 1 + 9641 .syntax unified + 9642 .thumb + 9643 .thumb_func + 9645 I2C_DMASlaveReceiveCplt: + 9646 .LVL651: + 9647 .LFB197: +6284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 9648 .loc 1 6284 1 is_stmt 1 view -0 + 9649 .cfi_startproc + 9650 @ args = 0, pretend = 0, frame = 0 + 9651 @ frame_needed = 0, uses_anonymous_args = 0 +6284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 9652 .loc 1 6284 1 is_stmt 0 view .LVU3390 + 9653 0000 08B5 push {r3, lr} + 9654 .cfi_def_cfa_offset 8 + 9655 .cfi_offset 3, -8 + 9656 .cfi_offset 14, -4 +6286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9657 .loc 1 6286 3 is_stmt 1 view .LVU3391 +6286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9658 .loc 1 6286 22 is_stmt 0 view .LVU3392 + 9659 0002 406A ldr r0, [r0, #36] + 9660 .LVL652: +6287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9661 .loc 1 6287 3 is_stmt 1 view .LVU3393 +6287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9662 .loc 1 6287 12 is_stmt 0 view .LVU3394 + 9663 0004 C26A ldr r2, [r0, #44] + 9664 .LVL653: +6289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9665 .loc 1 6289 3 is_stmt 1 view .LVU3395 +6289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9666 .loc 1 6289 8 is_stmt 0 view .LVU3396 + 9667 0006 C36B ldr r3, [r0, #60] + 9668 0008 1B68 ldr r3, [r3] + 9669 000a 5B68 ldr r3, [r3, #4] +6289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9670 .loc 1 6289 6 view .LVU3397 + 9671 000c 13B9 cbnz r3, .L612 +6289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 9672 .loc 1 6289 51 discriminator 1 view .LVU3398 + 9673 000e 12F5803F cmn r2, #65536 + 9674 0012 00D1 bne .L615 + 9675 .LVL654: + 9676 .L612: +6304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9677 .loc 1 6304 1 view .LVU3399 + 9678 0014 08BD pop {r3, pc} + 9679 .LVL655: + 9680 .L615: + ARM GAS /tmp/ccE2rRGE.s page 346 + + +6293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9681 .loc 1 6293 5 is_stmt 1 view .LVU3400 +6293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9682 .loc 1 6293 9 is_stmt 0 view .LVU3401 + 9683 0016 0268 ldr r2, [r0] + 9684 .LVL656: +6293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9685 .loc 1 6293 19 view .LVU3402 + 9686 0018 1368 ldr r3, [r2] +6293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9687 .loc 1 6293 25 view .LVU3403 + 9688 001a 23F40043 bic r3, r3, #32768 + 9689 001e 1360 str r3, [r2] +6296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9690 .loc 1 6296 5 is_stmt 1 view .LVU3404 + 9691 0020 FFF7FEFF bl I2C_ITSlaveSeqCplt + 9692 .LVL657: +6303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9693 .loc 1 6303 3 view .LVU3405 +6304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9694 .loc 1 6304 1 is_stmt 0 view .LVU3406 + 9695 0024 F6E7 b .L612 + 9696 .cfi_endproc + 9697 .LFE197: + 9699 .section .text.HAL_I2C_AddrCallback,"ax",%progbits + 9700 .align 1 + 9701 .weak HAL_I2C_AddrCallback + 9702 .syntax unified + 9703 .thumb + 9704 .thumb_func + 9706 HAL_I2C_AddrCallback: + 9707 .LVL658: + 9708 .LFB170: +4569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9709 .loc 1 4569 1 is_stmt 1 view -0 + 9710 .cfi_startproc + 9711 @ args = 0, pretend = 0, frame = 0 + 9712 @ frame_needed = 0, uses_anonymous_args = 0 + 9713 @ link register save eliminated. +4571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(TransferDirection); + 9714 .loc 1 4571 3 view .LVU3408 +4572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(AddrMatchCode); + 9715 .loc 1 4572 3 view .LVU3409 +4573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9716 .loc 1 4573 3 view .LVU3410 +4578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9717 .loc 1 4578 1 is_stmt 0 view .LVU3411 + 9718 0000 7047 bx lr + 9719 .cfi_endproc + 9720 .LFE170: + 9722 .section .text.I2C_ITAddrCplt,"ax",%progbits + 9723 .align 1 + 9724 .syntax unified + 9725 .thumb + 9726 .thumb_func + 9728 I2C_ITAddrCplt: + 9729 .LVL659: + ARM GAS /tmp/ccE2rRGE.s page 347 + + + 9730 .LFB185: +5410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint8_t transferdirection; + 9731 .loc 1 5410 1 is_stmt 1 view -0 + 9732 .cfi_startproc + 9733 @ args = 0, pretend = 0, frame = 0 + 9734 @ frame_needed = 0, uses_anonymous_args = 0 +5410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint8_t transferdirection; + 9735 .loc 1 5410 1 is_stmt 0 view .LVU3413 + 9736 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 9737 .cfi_def_cfa_offset 24 + 9738 .cfi_offset 3, -24 + 9739 .cfi_offset 4, -20 + 9740 .cfi_offset 5, -16 + 9741 .cfi_offset 6, -12 + 9742 .cfi_offset 7, -8 + 9743 .cfi_offset 14, -4 + 9744 0002 0446 mov r4, r0 +5411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t slaveaddrcode; + 9745 .loc 1 5411 3 is_stmt 1 view .LVU3414 +5412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t ownadd1code; + 9746 .loc 1 5412 3 view .LVU3415 +5413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t ownadd2code; + 9747 .loc 1 5413 3 view .LVU3416 +5414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9748 .loc 1 5414 3 view .LVU3417 +5417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9749 .loc 1 5417 3 view .LVU3418 +5420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9750 .loc 1 5420 3 view .LVU3419 +5420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9751 .loc 1 5420 22 is_stmt 0 view .LVU3420 + 9752 0004 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 +5420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9753 .loc 1 5420 6 view .LVU3421 + 9754 0008 03F02803 and r3, r3, #40 + 9755 000c 282B cmp r3, #40 + 9756 000e 06D0 beq .L623 +5492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9757 .loc 1 5492 5 is_stmt 1 view .LVU3422 + 9758 0010 0368 ldr r3, [r0] + 9759 0012 0822 movs r2, #8 + 9760 0014 DA61 str r2, [r3, #28] +5495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9761 .loc 1 5495 5 view .LVU3423 +5495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9762 .loc 1 5495 5 view .LVU3424 + 9763 0016 0023 movs r3, #0 + 9764 0018 80F84030 strb r3, [r0, #64] +5495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9765 .loc 1 5495 5 view .LVU3425 + 9766 .LVL660: + 9767 .L617: +5497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9768 .loc 1 5497 1 is_stmt 0 view .LVU3426 + 9769 001c F8BD pop {r3, r4, r5, r6, r7, pc} + 9770 .LVL661: + 9771 .L623: + ARM GAS /tmp/ccE2rRGE.s page 348 + + +5422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 9772 .loc 1 5422 5 is_stmt 1 view .LVU3427 +5422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 9773 .loc 1 5422 25 is_stmt 0 view .LVU3428 + 9774 001e 0368 ldr r3, [r0] + 9775 0020 9E69 ldr r6, [r3, #24] +5422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 9776 .loc 1 5422 23 view .LVU3429 + 9777 0022 C6F30046 ubfx r6, r6, #16, #1 + 9778 .LVL662: +5423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 9779 .loc 1 5423 5 is_stmt 1 view .LVU3430 +5423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 9780 .loc 1 5423 25 is_stmt 0 view .LVU3431 + 9781 0026 9A69 ldr r2, [r3, #24] + 9782 0028 120C lsrs r2, r2, #16 +5423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 9783 .loc 1 5423 23 view .LVU3432 + 9784 002a 02F0FE05 and r5, r2, #254 + 9785 .LVL663: +5424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 9786 .loc 1 5424 5 is_stmt 1 view .LVU3433 +5424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 9787 .loc 1 5424 25 is_stmt 0 view .LVU3434 + 9788 002e 9A68 ldr r2, [r3, #8] +5424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 9789 .loc 1 5424 23 view .LVU3435 + 9790 0030 C2F30902 ubfx r2, r2, #0, #10 + 9791 .LVL664: +5425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9792 .loc 1 5425 5 is_stmt 1 view .LVU3436 +5425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9793 .loc 1 5425 25 is_stmt 0 view .LVU3437 + 9794 0034 DF68 ldr r7, [r3, #12] +5425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9795 .loc 1 5425 23 view .LVU3438 + 9796 0036 07F0FE07 and r7, r7, #254 + 9797 .LVL665: +5428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9798 .loc 1 5428 5 is_stmt 1 view .LVU3439 +5428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9799 .loc 1 5428 19 is_stmt 0 view .LVU3440 + 9800 003a C168 ldr r1, [r0, #12] + 9801 .LVL666: +5428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9802 .loc 1 5428 8 view .LVU3441 + 9803 003c 0229 cmp r1, #2 + 9804 003e 22D1 bne .L619 +5430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9805 .loc 1 5430 7 is_stmt 1 view .LVU3442 +5430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9806 .loc 1 5430 44 is_stmt 0 view .LVU3443 + 9807 0040 85EAD215 eor r5, r5, r2, lsr #7 + 9808 .LVL667: +5430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9809 .loc 1 5430 10 view .LVU3444 + 9810 0044 15F0060F tst r5, #6 + ARM GAS /tmp/ccE2rRGE.s page 349 + + + 9811 0048 10D1 bne .L620 +5432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrEventCount++; + 9812 .loc 1 5432 9 is_stmt 1 view .LVU3445 + 9813 .LVL668: +5433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 9814 .loc 1 5433 9 view .LVU3446 +5433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 9815 .loc 1 5433 13 is_stmt 0 view .LVU3447 + 9816 004a 816C ldr r1, [r0, #72] +5433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 9817 .loc 1 5433 29 view .LVU3448 + 9818 004c 0131 adds r1, r1, #1 + 9819 004e 8164 str r1, [r0, #72] +5434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9820 .loc 1 5434 9 is_stmt 1 view .LVU3449 +5434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9821 .loc 1 5434 17 is_stmt 0 view .LVU3450 + 9822 0050 816C ldr r1, [r0, #72] +5434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9823 .loc 1 5434 12 view .LVU3451 + 9824 0052 0229 cmp r1, #2 + 9825 0054 E2D1 bne .L617 +5437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9826 .loc 1 5437 11 is_stmt 1 view .LVU3452 +5437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9827 .loc 1 5437 32 is_stmt 0 view .LVU3453 + 9828 0056 0021 movs r1, #0 + 9829 0058 8164 str r1, [r0, #72] +5440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9830 .loc 1 5440 11 is_stmt 1 view .LVU3454 + 9831 005a 0820 movs r0, #8 + 9832 .LVL669: +5440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9833 .loc 1 5440 11 is_stmt 0 view .LVU3455 + 9834 005c D861 str r0, [r3, #28] +5443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9835 .loc 1 5443 11 is_stmt 1 view .LVU3456 +5443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9836 .loc 1 5443 11 view .LVU3457 + 9837 005e 84F84010 strb r1, [r4, #64] +5443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9838 .loc 1 5443 11 view .LVU3458 +5449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9839 .loc 1 5449 11 view .LVU3459 + 9840 0062 3146 mov r1, r6 + 9841 0064 2046 mov r0, r4 + 9842 0066 FFF7FEFF bl HAL_I2C_AddrCallback + 9843 .LVL670: +5449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9844 .loc 1 5449 11 is_stmt 0 view .LVU3460 + 9845 006a D7E7 b .L617 + 9846 .LVL671: + 9847 .L620: +5455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9848 .loc 1 5455 9 is_stmt 1 view .LVU3461 +5458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9849 .loc 1 5458 9 view .LVU3462 + ARM GAS /tmp/ccE2rRGE.s page 350 + + + 9850 006c 4FF40041 mov r1, #32768 + 9851 0070 FFF7FEFF bl I2C_Disable_IRQ + 9852 .LVL672: +5461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9853 .loc 1 5461 9 view .LVU3463 +5461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9854 .loc 1 5461 9 view .LVU3464 + 9855 0074 0023 movs r3, #0 + 9856 0076 84F84030 strb r3, [r4, #64] +5461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9857 .loc 1 5461 9 view .LVU3465 +5467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9858 .loc 1 5467 9 view .LVU3466 + 9859 007a 3A46 mov r2, r7 + 9860 007c 3146 mov r1, r6 + 9861 007e 2046 mov r0, r4 + 9862 0080 FFF7FEFF bl HAL_I2C_AddrCallback + 9863 .LVL673: + 9864 0084 CAE7 b .L617 + 9865 .LVL674: + 9866 .L619: +5475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9867 .loc 1 5475 7 view .LVU3467 + 9868 0086 4FF40041 mov r1, #32768 + 9869 008a FFF7FEFF bl I2C_Disable_IRQ + 9870 .LVL675: +5478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9871 .loc 1 5478 7 view .LVU3468 +5478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9872 .loc 1 5478 7 view .LVU3469 + 9873 008e 0023 movs r3, #0 + 9874 0090 84F84030 strb r3, [r4, #64] +5478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9875 .loc 1 5478 7 view .LVU3470 +5484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 9876 .loc 1 5484 7 view .LVU3471 + 9877 0094 2A46 mov r2, r5 + 9878 0096 3146 mov r1, r6 + 9879 0098 2046 mov r0, r4 + 9880 009a FFF7FEFF bl HAL_I2C_AddrCallback + 9881 .LVL676: + 9882 009e BDE7 b .L617 + 9883 .cfi_endproc + 9884 .LFE185: + 9886 .section .text.HAL_I2C_ListenCpltCallback,"ax",%progbits + 9887 .align 1 + 9888 .weak HAL_I2C_ListenCpltCallback + 9889 .syntax unified + 9890 .thumb + 9891 .thumb_func + 9893 HAL_I2C_ListenCpltCallback: + 9894 .LVL677: + 9895 .LFB171: +4587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 9896 .loc 1 4587 1 view -0 + 9897 .cfi_startproc + 9898 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccE2rRGE.s page 351 + + + 9899 @ frame_needed = 0, uses_anonymous_args = 0 + 9900 @ link register save eliminated. +4589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9901 .loc 1 4589 3 view .LVU3473 +4594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9902 .loc 1 4594 1 is_stmt 0 view .LVU3474 + 9903 0000 7047 bx lr + 9904 .cfi_endproc + 9905 .LFE171: + 9907 .section .text.I2C_ITListenCplt,"ax",%progbits + 9908 .align 1 + 9909 .syntax unified + 9910 .thumb + 9911 .thumb_func + 9913 I2C_ITListenCplt: + 9914 .LVL678: + 9915 .LFB190: +5934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset handle parameters */ + 9916 .loc 1 5934 1 is_stmt 1 view -0 + 9917 .cfi_startproc + 9918 @ args = 0, pretend = 0, frame = 0 + 9919 @ frame_needed = 0, uses_anonymous_args = 0 +5934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset handle parameters */ + 9920 .loc 1 5934 1 is_stmt 0 view .LVU3476 + 9921 0000 10B5 push {r4, lr} + 9922 .cfi_def_cfa_offset 8 + 9923 .cfi_offset 4, -8 + 9924 .cfi_offset 14, -4 + 9925 0002 0446 mov r4, r0 +5936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 9926 .loc 1 5936 3 is_stmt 1 view .LVU3477 +5936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 9927 .loc 1 5936 21 is_stmt 0 view .LVU3478 + 9928 0004 174B ldr r3, .L628 + 9929 0006 C362 str r3, [r0, #44] +5937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9930 .loc 1 5937 3 is_stmt 1 view .LVU3479 +5937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9931 .loc 1 5937 23 is_stmt 0 view .LVU3480 + 9932 0008 0023 movs r3, #0 + 9933 000a 0363 str r3, [r0, #48] +5938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9934 .loc 1 5938 3 is_stmt 1 view .LVU3481 +5938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9935 .loc 1 5938 15 is_stmt 0 view .LVU3482 + 9936 000c 2022 movs r2, #32 + 9937 000e 80F84120 strb r2, [r0, #65] +5939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9938 .loc 1 5939 3 is_stmt 1 view .LVU3483 +5939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9939 .loc 1 5939 14 is_stmt 0 view .LVU3484 + 9940 0012 80F84230 strb r3, [r0, #66] +5940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9941 .loc 1 5940 3 is_stmt 1 view .LVU3485 +5940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9942 .loc 1 5940 17 is_stmt 0 view .LVU3486 + 9943 0016 4363 str r3, [r0, #52] + ARM GAS /tmp/ccE2rRGE.s page 352 + + +5943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9944 .loc 1 5943 3 is_stmt 1 view .LVU3487 +5943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9945 .loc 1 5943 6 is_stmt 0 view .LVU3488 + 9946 0018 11F0040F tst r1, #4 + 9947 001c 13D0 beq .L626 +5946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9948 .loc 1 5946 5 is_stmt 1 view .LVU3489 +5946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9949 .loc 1 5946 36 is_stmt 0 view .LVU3490 + 9950 001e 0368 ldr r3, [r0] +5946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9951 .loc 1 5946 46 view .LVU3491 + 9952 0020 5A6A ldr r2, [r3, #36] +5946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9953 .loc 1 5946 10 view .LVU3492 + 9954 0022 436A ldr r3, [r0, #36] +5946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9955 .loc 1 5946 21 view .LVU3493 + 9956 0024 1A70 strb r2, [r3] +5949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9957 .loc 1 5949 5 is_stmt 1 view .LVU3494 +5949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9958 .loc 1 5949 9 is_stmt 0 view .LVU3495 + 9959 0026 436A ldr r3, [r0, #36] +5949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9960 .loc 1 5949 19 view .LVU3496 + 9961 0028 0133 adds r3, r3, #1 + 9962 002a 4362 str r3, [r0, #36] +5951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9963 .loc 1 5951 5 is_stmt 1 view .LVU3497 +5951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9964 .loc 1 5951 14 is_stmt 0 view .LVU3498 + 9965 002c 038D ldrh r3, [r0, #40] +5951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9966 .loc 1 5951 8 view .LVU3499 + 9967 002e 53B1 cbz r3, .L626 +5953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 9968 .loc 1 5953 7 is_stmt 1 view .LVU3500 +5953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 9969 .loc 1 5953 21 is_stmt 0 view .LVU3501 + 9970 0030 013B subs r3, r3, #1 + 9971 0032 0385 strh r3, [r0, #40] @ movhi +5954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9972 .loc 1 5954 7 is_stmt 1 view .LVU3502 +5954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9973 .loc 1 5954 11 is_stmt 0 view .LVU3503 + 9974 0034 438D ldrh r3, [r0, #42] + 9975 0036 9BB2 uxth r3, r3 +5954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9976 .loc 1 5954 22 view .LVU3504 + 9977 0038 013B subs r3, r3, #1 + 9978 003a 9BB2 uxth r3, r3 + 9979 003c 4385 strh r3, [r0, #42] @ movhi +5957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9980 .loc 1 5957 7 is_stmt 1 view .LVU3505 +5957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 353 + + + 9981 .loc 1 5957 11 is_stmt 0 view .LVU3506 + 9982 003e 436C ldr r3, [r0, #68] +5957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9983 .loc 1 5957 23 view .LVU3507 + 9984 0040 43F00403 orr r3, r3, #4 + 9985 0044 4364 str r3, [r0, #68] + 9986 .L626: +5962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9987 .loc 1 5962 3 is_stmt 1 view .LVU3508 + 9988 0046 48F20301 movw r1, #32771 + 9989 .LVL679: +5962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9990 .loc 1 5962 3 is_stmt 0 view .LVU3509 + 9991 004a 2046 mov r0, r4 + 9992 .LVL680: +5962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9993 .loc 1 5962 3 view .LVU3510 + 9994 004c FFF7FEFF bl I2C_Disable_IRQ + 9995 .LVL681: +5965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 9996 .loc 1 5965 3 is_stmt 1 view .LVU3511 + 9997 0050 2368 ldr r3, [r4] + 9998 0052 1022 movs r2, #16 + 9999 0054 DA61 str r2, [r3, #28] +5968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10000 .loc 1 5968 3 view .LVU3512 +5968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10001 .loc 1 5968 3 view .LVU3513 + 10002 0056 0023 movs r3, #0 + 10003 0058 84F84030 strb r3, [r4, #64] +5968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10004 .loc 1 5968 3 view .LVU3514 +5974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10005 .loc 1 5974 3 view .LVU3515 + 10006 005c 2046 mov r0, r4 + 10007 005e FFF7FEFF bl HAL_I2C_ListenCpltCallback + 10008 .LVL682: +5976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10009 .loc 1 5976 1 is_stmt 0 view .LVU3516 + 10010 0062 10BD pop {r4, pc} + 10011 .LVL683: + 10012 .L629: +5976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10013 .loc 1 5976 1 view .LVU3517 + 10014 .align 2 + 10015 .L628: + 10016 0064 0000FFFF .word -65536 + 10017 .cfi_endproc + 10018 .LFE190: + 10020 .section .text.HAL_I2C_MemTxCpltCallback,"ax",%progbits + 10021 .align 1 + 10022 .weak HAL_I2C_MemTxCpltCallback + 10023 .syntax unified + 10024 .thumb + 10025 .thumb_func + 10027 HAL_I2C_MemTxCpltCallback: + 10028 .LVL684: + ARM GAS /tmp/ccE2rRGE.s page 354 + + + 10029 .LFB172: +4603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10030 .loc 1 4603 1 is_stmt 1 view -0 + 10031 .cfi_startproc + 10032 @ args = 0, pretend = 0, frame = 0 + 10033 @ frame_needed = 0, uses_anonymous_args = 0 + 10034 @ link register save eliminated. +4605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10035 .loc 1 4605 3 view .LVU3519 +4610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10036 .loc 1 4610 1 is_stmt 0 view .LVU3520 + 10037 0000 7047 bx lr + 10038 .cfi_endproc + 10039 .LFE172: + 10041 .section .text.HAL_I2C_MemRxCpltCallback,"ax",%progbits + 10042 .align 1 + 10043 .weak HAL_I2C_MemRxCpltCallback + 10044 .syntax unified + 10045 .thumb + 10046 .thumb_func + 10048 HAL_I2C_MemRxCpltCallback: + 10049 .LVL685: + 10050 .LFB173: +4619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10051 .loc 1 4619 1 is_stmt 1 view -0 + 10052 .cfi_startproc + 10053 @ args = 0, pretend = 0, frame = 0 + 10054 @ frame_needed = 0, uses_anonymous_args = 0 + 10055 @ link register save eliminated. +4621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10056 .loc 1 4621 3 view .LVU3522 +4626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10057 .loc 1 4626 1 is_stmt 0 view .LVU3523 + 10058 0000 7047 bx lr + 10059 .cfi_endproc + 10060 .LFE173: + 10062 .section .text.HAL_I2C_ErrorCallback,"ax",%progbits + 10063 .align 1 + 10064 .weak HAL_I2C_ErrorCallback + 10065 .syntax unified + 10066 .thumb + 10067 .thumb_func + 10069 HAL_I2C_ErrorCallback: + 10070 .LVL686: + 10071 .LFB174: +4635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10072 .loc 1 4635 1 is_stmt 1 view -0 + 10073 .cfi_startproc + 10074 @ args = 0, pretend = 0, frame = 0 + 10075 @ frame_needed = 0, uses_anonymous_args = 0 + 10076 @ link register save eliminated. +4637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10077 .loc 1 4637 3 view .LVU3525 +4642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10078 .loc 1 4642 1 is_stmt 0 view .LVU3526 + 10079 0000 7047 bx lr + 10080 .cfi_endproc + ARM GAS /tmp/ccE2rRGE.s page 355 + + + 10081 .LFE174: + 10083 .section .text.HAL_I2C_AbortCpltCallback,"ax",%progbits + 10084 .align 1 + 10085 .weak HAL_I2C_AbortCpltCallback + 10086 .syntax unified + 10087 .thumb + 10088 .thumb_func + 10090 HAL_I2C_AbortCpltCallback: + 10091 .LVL687: + 10092 .LFB175: +4651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10093 .loc 1 4651 1 is_stmt 1 view -0 + 10094 .cfi_startproc + 10095 @ args = 0, pretend = 0, frame = 0 + 10096 @ frame_needed = 0, uses_anonymous_args = 0 + 10097 @ link register save eliminated. +4653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10098 .loc 1 4653 3 view .LVU3528 +4658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10099 .loc 1 4658 1 is_stmt 0 view .LVU3529 + 10100 0000 7047 bx lr + 10101 .cfi_endproc + 10102 .LFE175: + 10104 .section .text.I2C_TreatErrorCallback,"ax",%progbits + 10105 .align 1 + 10106 .syntax unified + 10107 .thumb + 10108 .thumb_func + 10110 I2C_TreatErrorCallback: + 10111 .LVL688: + 10112 .LFB192: +6097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 10113 .loc 1 6097 1 is_stmt 1 view -0 + 10114 .cfi_startproc + 10115 @ args = 0, pretend = 0, frame = 0 + 10116 @ frame_needed = 0, uses_anonymous_args = 0 +6097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 10117 .loc 1 6097 1 is_stmt 0 view .LVU3531 + 10118 0000 08B5 push {r3, lr} + 10119 .cfi_def_cfa_offset 8 + 10120 .cfi_offset 3, -8 + 10121 .cfi_offset 14, -4 +6098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10122 .loc 1 6098 3 is_stmt 1 view .LVU3532 +6098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10123 .loc 1 6098 11 is_stmt 0 view .LVU3533 + 10124 0002 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10125 0006 DBB2 uxtb r3, r3 +6098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10126 .loc 1 6098 6 view .LVU3534 + 10127 0008 602B cmp r3, #96 + 10128 000a 06D0 beq .L638 +6115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10129 .loc 1 6115 5 is_stmt 1 view .LVU3535 +6115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10130 .loc 1 6115 25 is_stmt 0 view .LVU3536 + 10131 000c 0023 movs r3, #0 + ARM GAS /tmp/ccE2rRGE.s page 356 + + + 10132 000e 0363 str r3, [r0, #48] +6118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10133 .loc 1 6118 5 is_stmt 1 view .LVU3537 +6118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10134 .loc 1 6118 5 view .LVU3538 + 10135 0010 80F84030 strb r3, [r0, #64] +6118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10136 .loc 1 6118 5 view .LVU3539 +6124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10137 .loc 1 6124 5 view .LVU3540 + 10138 0014 FFF7FEFF bl HAL_I2C_ErrorCallback + 10139 .LVL689: + 10140 .L634: +6127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10141 .loc 1 6127 1 is_stmt 0 view .LVU3541 + 10142 0018 08BD pop {r3, pc} + 10143 .LVL690: + 10144 .L638: +6100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10145 .loc 1 6100 5 is_stmt 1 view .LVU3542 +6100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10146 .loc 1 6100 17 is_stmt 0 view .LVU3543 + 10147 001a 2023 movs r3, #32 + 10148 001c 80F84130 strb r3, [r0, #65] +6101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10149 .loc 1 6101 5 is_stmt 1 view .LVU3544 +6101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10150 .loc 1 6101 25 is_stmt 0 view .LVU3545 + 10151 0020 0023 movs r3, #0 + 10152 0022 0363 str r3, [r0, #48] +6104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10153 .loc 1 6104 5 is_stmt 1 view .LVU3546 +6104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10154 .loc 1 6104 5 view .LVU3547 + 10155 0024 80F84030 strb r3, [r0, #64] +6104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10156 .loc 1 6104 5 view .LVU3548 +6110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10157 .loc 1 6110 5 view .LVU3549 + 10158 0028 FFF7FEFF bl HAL_I2C_AbortCpltCallback + 10159 .LVL691: +6110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10160 .loc 1 6110 5 is_stmt 0 view .LVU3550 + 10161 002c F4E7 b .L634 + 10162 .cfi_endproc + 10163 .LFE192: + 10165 .section .text.I2C_ITError,"ax",%progbits + 10166 .align 1 + 10167 .syntax unified + 10168 .thumb + 10169 .thumb_func + 10171 I2C_ITError: + 10172 .LVL692: + 10173 .LFB191: +5985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 10174 .loc 1 5985 1 is_stmt 1 view -0 + 10175 .cfi_startproc + ARM GAS /tmp/ccE2rRGE.s page 357 + + + 10176 @ args = 0, pretend = 0, frame = 0 + 10177 @ frame_needed = 0, uses_anonymous_args = 0 +5985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 10178 .loc 1 5985 1 is_stmt 0 view .LVU3552 + 10179 0000 10B5 push {r4, lr} + 10180 .cfi_def_cfa_offset 8 + 10181 .cfi_offset 4, -8 + 10182 .cfi_offset 14, -4 + 10183 0002 0446 mov r4, r0 +5986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmppreviousstate; + 10184 .loc 1 5986 3 is_stmt 1 view .LVU3553 +5986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmppreviousstate; + 10185 .loc 1 5986 24 is_stmt 0 view .LVU3554 + 10186 0004 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10187 .LVL693: +5987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10188 .loc 1 5987 3 is_stmt 1 view .LVU3555 +5990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 10189 .loc 1 5990 3 view .LVU3556 +5990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 10190 .loc 1 5990 23 is_stmt 0 view .LVU3557 + 10191 0008 0022 movs r2, #0 + 10192 000a 80F84220 strb r2, [r0, #66] +5991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = 0U; + 10193 .loc 1 5991 3 is_stmt 1 view .LVU3558 +5991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = 0U; + 10194 .loc 1 5991 23 is_stmt 0 view .LVU3559 + 10195 000e 3B48 ldr r0, .L653 + 10196 .LVL694: +5991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = 0U; + 10197 .loc 1 5991 23 view .LVU3560 + 10198 0010 E062 str r0, [r4, #44] +5992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10199 .loc 1 5992 3 is_stmt 1 view .LVU3561 +5992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10200 .loc 1 5992 23 is_stmt 0 view .LVU3562 + 10201 0012 6285 strh r2, [r4, #42] @ movhi +5995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10202 .loc 1 5995 3 is_stmt 1 view .LVU3563 +5995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10203 .loc 1 5995 7 is_stmt 0 view .LVU3564 + 10204 0014 626C ldr r2, [r4, #68] +5995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10205 .loc 1 5995 19 view .LVU3565 + 10206 0016 0A43 orrs r2, r2, r1 + 10207 0018 6264 str r2, [r4, #68] +5998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 10208 .loc 1 5998 3 is_stmt 1 view .LVU3566 +5999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 10209 .loc 1 5999 50 is_stmt 0 view .LVU3567 + 10210 001a 283B subs r3, r3, #40 + 10211 .LVL695: +5999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 10212 .loc 1 5999 50 view .LVU3568 + 10213 001c DBB2 uxtb r3, r3 +5998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 10214 .loc 1 5998 6 view .LVU3569 + ARM GAS /tmp/ccE2rRGE.s page 358 + + + 10215 001e 022B cmp r3, #2 + 10216 0020 19D8 bhi .L640 +6003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10217 .loc 1 6003 5 is_stmt 1 view .LVU3570 + 10218 0022 0321 movs r1, #3 + 10219 .LVL696: +6003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10220 .loc 1 6003 5 is_stmt 0 view .LVU3571 + 10221 0024 2046 mov r0, r4 + 10222 0026 FFF7FEFF bl I2C_Disable_IRQ + 10223 .LVL697: +6006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 10224 .loc 1 6006 5 is_stmt 1 view .LVU3572 +6006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 10225 .loc 1 6006 25 is_stmt 0 view .LVU3573 + 10226 002a 2823 movs r3, #40 + 10227 002c 84F84130 strb r3, [r4, #65] +6007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10228 .loc 1 6007 5 is_stmt 1 view .LVU3574 +6007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10229 .loc 1 6007 25 is_stmt 0 view .LVU3575 + 10230 0030 334B ldr r3, .L653+4 + 10231 0032 6363 str r3, [r4, #52] + 10232 .L641: +6025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + 10233 .loc 1 6025 3 is_stmt 1 view .LVU3576 +6025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + 10234 .loc 1 6025 20 is_stmt 0 view .LVU3577 + 10235 0034 236B ldr r3, [r4, #48] + 10236 .LVL698: +6026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 10237 .loc 1 6026 3 is_stmt 1 view .LVU3578 +6026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 10238 .loc 1 6026 12 is_stmt 0 view .LVU3579 + 10239 0036 A26B ldr r2, [r4, #56] +6026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 10240 .loc 1 6026 6 view .LVU3580 + 10241 0038 1AB1 cbz r2, .L643 +6026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 10242 .loc 1 6026 30 discriminator 1 view .LVU3581 + 10243 003a 112B cmp r3, #17 + 10244 003c 1BD0 beq .L644 +6026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 10245 .loc 1 6026 81 discriminator 2 view .LVU3582 + 10246 003e 212B cmp r3, #33 + 10247 0040 19D0 beq .L644 + 10248 .L643: +6056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 10249 .loc 1 6056 8 is_stmt 1 view .LVU3583 +6056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 10250 .loc 1 6056 17 is_stmt 0 view .LVU3584 + 10251 0042 E26B ldr r2, [r4, #60] +6056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 10252 .loc 1 6056 11 view .LVU3585 + 10253 0044 1AB1 cbz r2, .L648 +6056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 10254 .loc 1 6056 35 discriminator 1 view .LVU3586 + ARM GAS /tmp/ccE2rRGE.s page 359 + + + 10255 0046 122B cmp r3, #18 + 10256 0048 36D0 beq .L649 +6056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 10257 .loc 1 6056 86 discriminator 2 view .LVU3587 + 10258 004a 222B cmp r3, #34 + 10259 004c 34D0 beq .L649 + 10260 .L648: +6087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10261 .loc 1 6087 5 is_stmt 1 view .LVU3588 + 10262 004e 2046 mov r0, r4 + 10263 0050 FFF7FEFF bl I2C_TreatErrorCallback + 10264 .LVL699: + 10265 .L639: +6089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10266 .loc 1 6089 1 is_stmt 0 view .LVU3589 + 10267 0054 10BD pop {r4, pc} + 10268 .LVL700: + 10269 .L640: +6012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10270 .loc 1 6012 5 is_stmt 1 view .LVU3590 + 10271 0056 48F20301 movw r1, #32771 + 10272 .LVL701: +6012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10273 .loc 1 6012 5 is_stmt 0 view .LVU3591 + 10274 005a 2046 mov r0, r4 + 10275 005c FFF7FEFF bl I2C_Disable_IRQ + 10276 .LVL702: +6016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10277 .loc 1 6016 5 is_stmt 1 view .LVU3592 +6016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10278 .loc 1 6016 13 is_stmt 0 view .LVU3593 + 10279 0060 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10280 0064 DBB2 uxtb r3, r3 +6016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10281 .loc 1 6016 8 view .LVU3594 + 10282 0066 602B cmp r3, #96 + 10283 0068 02D0 beq .L642 +6019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10284 .loc 1 6019 7 is_stmt 1 view .LVU3595 +6019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10285 .loc 1 6019 27 is_stmt 0 view .LVU3596 + 10286 006a 2023 movs r3, #32 + 10287 006c 84F84130 strb r3, [r4, #65] + 10288 .L642: +6021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10289 .loc 1 6021 5 is_stmt 1 view .LVU3597 +6021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10290 .loc 1 6021 25 is_stmt 0 view .LVU3598 + 10291 0070 0023 movs r3, #0 + 10292 0072 6363 str r3, [r4, #52] + 10293 0074 DEE7 b .L641 + 10294 .LVL703: + 10295 .L644: +6029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10296 .loc 1 6029 5 is_stmt 1 view .LVU3599 +6029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10297 .loc 1 6029 14 is_stmt 0 view .LVU3600 + ARM GAS /tmp/ccE2rRGE.s page 360 + + + 10298 0076 2368 ldr r3, [r4] + 10299 .LVL704: +6029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10300 .loc 1 6029 24 view .LVU3601 + 10301 0078 1A68 ldr r2, [r3] +6029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10302 .loc 1 6029 8 view .LVU3602 + 10303 007a 12F4804F tst r2, #16384 + 10304 007e 03D0 beq .L645 +6031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10305 .loc 1 6031 7 is_stmt 1 view .LVU3603 +6031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10306 .loc 1 6031 21 is_stmt 0 view .LVU3604 + 10307 0080 1A68 ldr r2, [r3] +6031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10308 .loc 1 6031 27 view .LVU3605 + 10309 0082 22F48042 bic r2, r2, #16384 + 10310 0086 1A60 str r2, [r3] + 10311 .L645: +6034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10312 .loc 1 6034 5 is_stmt 1 view .LVU3606 +6034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10313 .loc 1 6034 9 is_stmt 0 view .LVU3607 + 10314 0088 A06B ldr r0, [r4, #56] + 10315 008a FFF7FEFF bl HAL_DMA_GetState + 10316 .LVL705: +6034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10317 .loc 1 6034 8 view .LVU3608 + 10318 008e 0128 cmp r0, #1 + 10319 0090 0ED0 beq .L646 +6038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10320 .loc 1 6038 7 is_stmt 1 view .LVU3609 +6038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10321 .loc 1 6038 11 is_stmt 0 view .LVU3610 + 10322 0092 A36B ldr r3, [r4, #56] +6038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10323 .loc 1 6038 39 view .LVU3611 + 10324 0094 1B4A ldr r2, .L653+8 + 10325 0096 5A63 str r2, [r3, #52] +6041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10326 .loc 1 6041 7 is_stmt 1 view .LVU3612 +6041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10327 .loc 1 6041 7 view .LVU3613 + 10328 0098 0023 movs r3, #0 + 10329 009a 84F84030 strb r3, [r4, #64] +6041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10330 .loc 1 6041 7 view .LVU3614 +6044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10331 .loc 1 6044 7 view .LVU3615 +6044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10332 .loc 1 6044 11 is_stmt 0 view .LVU3616 + 10333 009e A06B ldr r0, [r4, #56] + 10334 00a0 FFF7FEFF bl HAL_DMA_Abort_IT + 10335 .LVL706: +6044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10336 .loc 1 6044 10 view .LVU3617 + 10337 00a4 0028 cmp r0, #0 + ARM GAS /tmp/ccE2rRGE.s page 361 + + + 10338 00a6 D5D0 beq .L639 +6047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10339 .loc 1 6047 9 is_stmt 1 view .LVU3618 +6047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10340 .loc 1 6047 13 is_stmt 0 view .LVU3619 + 10341 00a8 A06B ldr r0, [r4, #56] +6047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10342 .loc 1 6047 21 view .LVU3620 + 10343 00aa 436B ldr r3, [r0, #52] +6047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10344 .loc 1 6047 9 view .LVU3621 + 10345 00ac 9847 blx r3 + 10346 .LVL707: + 10347 00ae D1E7 b .L639 + 10348 .L646: +6052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10349 .loc 1 6052 7 is_stmt 1 view .LVU3622 + 10350 00b0 2046 mov r0, r4 + 10351 00b2 FFF7FEFF bl I2C_TreatErrorCallback + 10352 .LVL708: + 10353 00b6 CDE7 b .L639 + 10354 .LVL709: + 10355 .L649: +6059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10356 .loc 1 6059 5 view .LVU3623 +6059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10357 .loc 1 6059 14 is_stmt 0 view .LVU3624 + 10358 00b8 2368 ldr r3, [r4] + 10359 .LVL710: +6059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10360 .loc 1 6059 24 view .LVU3625 + 10361 00ba 1A68 ldr r2, [r3] +6059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10362 .loc 1 6059 8 view .LVU3626 + 10363 00bc 12F4004F tst r2, #32768 + 10364 00c0 03D0 beq .L650 +6061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10365 .loc 1 6061 7 is_stmt 1 view .LVU3627 +6061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10366 .loc 1 6061 21 is_stmt 0 view .LVU3628 + 10367 00c2 1A68 ldr r2, [r3] +6061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10368 .loc 1 6061 27 view .LVU3629 + 10369 00c4 22F40042 bic r2, r2, #32768 + 10370 00c8 1A60 str r2, [r3] + 10371 .L650: +6064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10372 .loc 1 6064 5 is_stmt 1 view .LVU3630 +6064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10373 .loc 1 6064 9 is_stmt 0 view .LVU3631 + 10374 00ca E06B ldr r0, [r4, #60] + 10375 00cc FFF7FEFF bl HAL_DMA_GetState + 10376 .LVL711: +6064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10377 .loc 1 6064 8 view .LVU3632 + 10378 00d0 0128 cmp r0, #1 + 10379 00d2 0ED0 beq .L651 + ARM GAS /tmp/ccE2rRGE.s page 362 + + +6068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10380 .loc 1 6068 7 is_stmt 1 view .LVU3633 +6068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10381 .loc 1 6068 11 is_stmt 0 view .LVU3634 + 10382 00d4 E36B ldr r3, [r4, #60] +6068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10383 .loc 1 6068 39 view .LVU3635 + 10384 00d6 0B4A ldr r2, .L653+8 + 10385 00d8 5A63 str r2, [r3, #52] +6071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10386 .loc 1 6071 7 is_stmt 1 view .LVU3636 +6071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10387 .loc 1 6071 7 view .LVU3637 + 10388 00da 0023 movs r3, #0 + 10389 00dc 84F84030 strb r3, [r4, #64] +6071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10390 .loc 1 6071 7 view .LVU3638 +6074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10391 .loc 1 6074 7 view .LVU3639 +6074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10392 .loc 1 6074 11 is_stmt 0 view .LVU3640 + 10393 00e0 E06B ldr r0, [r4, #60] + 10394 00e2 FFF7FEFF bl HAL_DMA_Abort_IT + 10395 .LVL712: +6074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10396 .loc 1 6074 10 view .LVU3641 + 10397 00e6 0028 cmp r0, #0 + 10398 00e8 B4D0 beq .L639 +6077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10399 .loc 1 6077 9 is_stmt 1 view .LVU3642 +6077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10400 .loc 1 6077 13 is_stmt 0 view .LVU3643 + 10401 00ea E06B ldr r0, [r4, #60] +6077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10402 .loc 1 6077 21 view .LVU3644 + 10403 00ec 436B ldr r3, [r0, #52] +6077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10404 .loc 1 6077 9 view .LVU3645 + 10405 00ee 9847 blx r3 + 10406 .LVL713: + 10407 00f0 B0E7 b .L639 + 10408 .L651: +6082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10409 .loc 1 6082 7 is_stmt 1 view .LVU3646 + 10410 00f2 2046 mov r0, r4 + 10411 00f4 FFF7FEFF bl I2C_TreatErrorCallback + 10412 .LVL714: + 10413 00f8 ACE7 b .L639 + 10414 .L654: + 10415 00fa 00BF .align 2 + 10416 .L653: + 10417 00fc 0000FFFF .word -65536 + 10418 0100 00000000 .word I2C_Slave_ISR_IT + 10419 0104 00000000 .word I2C_DMAAbort + 10420 .cfi_endproc + 10421 .LFE191: + 10423 .section .text.I2C_ITSlaveCplt,"ax",%progbits + ARM GAS /tmp/ccE2rRGE.s page 363 + + + 10424 .align 1 + 10425 .syntax unified + 10426 .thumb + 10427 .thumb_func + 10429 I2C_ITSlaveCplt: + 10430 .LVL715: + 10431 .LFB189: +5775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 10432 .loc 1 5775 1 view -0 + 10433 .cfi_startproc + 10434 @ args = 0, pretend = 0, frame = 0 + 10435 @ frame_needed = 0, uses_anonymous_args = 0 +5775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 10436 .loc 1 5775 1 is_stmt 0 view .LVU3648 + 10437 0000 70B5 push {r4, r5, r6, lr} + 10438 .cfi_def_cfa_offset 16 + 10439 .cfi_offset 4, -16 + 10440 .cfi_offset 5, -12 + 10441 .cfi_offset 6, -8 + 10442 .cfi_offset 14, -4 + 10443 0002 0446 mov r4, r0 + 10444 0004 0D46 mov r5, r1 +5776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10445 .loc 1 5776 3 is_stmt 1 view .LVU3649 +5776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10446 .loc 1 5776 26 is_stmt 0 view .LVU3650 + 10447 0006 0268 ldr r2, [r0] +5776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10448 .loc 1 5776 12 view .LVU3651 + 10449 0008 1668 ldr r6, [r2] + 10450 .LVL716: +5777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 10451 .loc 1 5777 3 is_stmt 1 view .LVU3652 +5778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10452 .loc 1 5778 3 view .LVU3653 +5778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10453 .loc 1 5778 24 is_stmt 0 view .LVU3654 + 10454 000a 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 10455 000e DBB2 uxtb r3, r3 + 10456 .LVL717: +5781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10457 .loc 1 5781 3 is_stmt 1 view .LVU3655 + 10458 0010 2021 movs r1, #32 + 10459 .LVL718: +5781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10460 .loc 1 5781 3 is_stmt 0 view .LVU3656 + 10461 0012 D161 str r1, [r2, #28] +5784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10462 .loc 1 5784 3 is_stmt 1 view .LVU3657 +5784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10463 .loc 1 5784 6 is_stmt 0 view .LVU3658 + 10464 0014 212B cmp r3, #33 + 10465 0016 0DD0 beq .L656 +5784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10466 .loc 1 5784 43 discriminator 1 view .LVU3659 + 10467 0018 292B cmp r3, #41 + 10468 001a 0BD0 beq .L656 + ARM GAS /tmp/ccE2rRGE.s page 364 + + +5789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10469 .loc 1 5789 8 is_stmt 1 view .LVU3660 +5789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10470 .loc 1 5789 11 is_stmt 0 view .LVU3661 + 10471 001c 222B cmp r3, #34 + 10472 001e 01D0 beq .L659 +5789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10473 .loc 1 5789 48 discriminator 1 view .LVU3662 + 10474 0020 2A2B cmp r3, #42 + 10475 0022 0ED1 bne .L658 + 10476 .L659: +5791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 10477 .loc 1 5791 5 is_stmt 1 view .LVU3663 + 10478 0024 48F20201 movw r1, #32770 + 10479 0028 2046 mov r0, r4 + 10480 .LVL719: +5791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 10481 .loc 1 5791 5 is_stmt 0 view .LVU3664 + 10482 002a FFF7FEFF bl I2C_Disable_IRQ + 10483 .LVL720: +5792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10484 .loc 1 5792 5 is_stmt 1 view .LVU3665 +5792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10485 .loc 1 5792 25 is_stmt 0 view .LVU3666 + 10486 002e 2223 movs r3, #34 + 10487 0030 2363 str r3, [r4, #48] + 10488 0032 06E0 b .L658 + 10489 .LVL721: + 10490 .L656: +5786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 10491 .loc 1 5786 5 is_stmt 1 view .LVU3667 + 10492 0034 48F20101 movw r1, #32769 + 10493 0038 2046 mov r0, r4 + 10494 .LVL722: +5786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 10495 .loc 1 5786 5 is_stmt 0 view .LVU3668 + 10496 003a FFF7FEFF bl I2C_Disable_IRQ + 10497 .LVL723: +5787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10498 .loc 1 5787 5 is_stmt 1 view .LVU3669 +5787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10499 .loc 1 5787 25 is_stmt 0 view .LVU3670 + 10500 003e 2123 movs r3, #33 + 10501 0040 2363 str r3, [r4, #48] + 10502 .L658: +5800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10503 .loc 1 5800 3 is_stmt 1 view .LVU3671 +5800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10504 .loc 1 5800 7 is_stmt 0 view .LVU3672 + 10505 0042 2268 ldr r2, [r4] +5800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10506 .loc 1 5800 17 view .LVU3673 + 10507 0044 5368 ldr r3, [r2, #4] +5800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10508 .loc 1 5800 23 view .LVU3674 + 10509 0046 43F40043 orr r3, r3, #32768 + 10510 004a 5360 str r3, [r2, #4] + ARM GAS /tmp/ccE2rRGE.s page 365 + + +5803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10511 .loc 1 5803 3 is_stmt 1 view .LVU3675 + 10512 004c 2268 ldr r2, [r4] + 10513 004e 5368 ldr r3, [r2, #4] + 10514 0050 23F0FF73 bic r3, r3, #33423360 + 10515 0054 23F48B33 bic r3, r3, #71168 + 10516 0058 23F4FF73 bic r3, r3, #510 + 10517 005c 23F00103 bic r3, r3, #1 + 10518 0060 5360 str r3, [r2, #4] +5806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10519 .loc 1 5806 3 view .LVU3676 + 10520 0062 2046 mov r0, r4 + 10521 0064 FFF7FEFF bl I2C_Flush_TXDR + 10522 .LVL724: +5809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10523 .loc 1 5809 3 view .LVU3677 +5809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10524 .loc 1 5809 6 is_stmt 0 view .LVU3678 + 10525 0068 16F4804F tst r6, #16384 + 10526 006c 40D0 beq .L660 +5812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10527 .loc 1 5812 5 is_stmt 1 view .LVU3679 +5812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10528 .loc 1 5812 9 is_stmt 0 view .LVU3680 + 10529 006e 2268 ldr r2, [r4] +5812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10530 .loc 1 5812 19 view .LVU3681 + 10531 0070 1368 ldr r3, [r2] +5812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10532 .loc 1 5812 25 view .LVU3682 + 10533 0072 23F48043 bic r3, r3, #16384 + 10534 0076 1360 str r3, [r2] +5814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10535 .loc 1 5814 5 is_stmt 1 view .LVU3683 +5814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10536 .loc 1 5814 13 is_stmt 0 view .LVU3684 + 10537 0078 A36B ldr r3, [r4, #56] +5814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10538 .loc 1 5814 8 view .LVU3685 + 10539 007a 1BB1 cbz r3, .L661 +5816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10540 .loc 1 5816 7 is_stmt 1 view .LVU3686 +5816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10541 .loc 1 5816 35 is_stmt 0 view .LVU3687 + 10542 007c 1B68 ldr r3, [r3] + 10543 007e 5B68 ldr r3, [r3, #4] +5816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10544 .loc 1 5816 25 view .LVU3688 + 10545 0080 9BB2 uxth r3, r3 +5816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10546 .loc 1 5816 23 view .LVU3689 + 10547 0082 6385 strh r3, [r4, #42] @ movhi + 10548 .L661: +5832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10549 .loc 1 5832 3 is_stmt 1 view .LVU3690 +5835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10550 .loc 1 5835 3 view .LVU3691 + ARM GAS /tmp/ccE2rRGE.s page 366 + + +5835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10551 .loc 1 5835 6 is_stmt 0 view .LVU3692 + 10552 0084 15F0040F tst r5, #4 + 10553 0088 11D0 beq .L662 +5838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10554 .loc 1 5838 5 is_stmt 1 view .LVU3693 +5838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10555 .loc 1 5838 16 is_stmt 0 view .LVU3694 + 10556 008a 25F00405 bic r5, r5, #4 + 10557 .LVL725: +5841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10558 .loc 1 5841 5 is_stmt 1 view .LVU3695 +5841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10559 .loc 1 5841 36 is_stmt 0 view .LVU3696 + 10560 008e 2368 ldr r3, [r4] +5841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10561 .loc 1 5841 46 view .LVU3697 + 10562 0090 5A6A ldr r2, [r3, #36] +5841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10563 .loc 1 5841 10 view .LVU3698 + 10564 0092 636A ldr r3, [r4, #36] +5841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10565 .loc 1 5841 21 view .LVU3699 + 10566 0094 1A70 strb r2, [r3] +5844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10567 .loc 1 5844 5 is_stmt 1 view .LVU3700 +5844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10568 .loc 1 5844 9 is_stmt 0 view .LVU3701 + 10569 0096 636A ldr r3, [r4, #36] +5844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10570 .loc 1 5844 19 view .LVU3702 + 10571 0098 0133 adds r3, r3, #1 + 10572 009a 6362 str r3, [r4, #36] +5846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10573 .loc 1 5846 5 is_stmt 1 view .LVU3703 +5846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10574 .loc 1 5846 14 is_stmt 0 view .LVU3704 + 10575 009c 238D ldrh r3, [r4, #40] +5846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10576 .loc 1 5846 8 view .LVU3705 + 10577 009e 33B1 cbz r3, .L662 +5848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 10578 .loc 1 5848 7 is_stmt 1 view .LVU3706 +5848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 10579 .loc 1 5848 21 is_stmt 0 view .LVU3707 + 10580 00a0 013B subs r3, r3, #1 + 10581 00a2 2385 strh r3, [r4, #40] @ movhi +5849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10582 .loc 1 5849 7 is_stmt 1 view .LVU3708 +5849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10583 .loc 1 5849 11 is_stmt 0 view .LVU3709 + 10584 00a4 638D ldrh r3, [r4, #42] + 10585 00a6 9BB2 uxth r3, r3 +5849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10586 .loc 1 5849 22 view .LVU3710 + 10587 00a8 013B subs r3, r3, #1 + 10588 00aa 9BB2 uxth r3, r3 + ARM GAS /tmp/ccE2rRGE.s page 367 + + + 10589 00ac 6385 strh r3, [r4, #42] @ movhi + 10590 .L662: +5854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10591 .loc 1 5854 3 is_stmt 1 view .LVU3711 +5854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10592 .loc 1 5854 11 is_stmt 0 view .LVU3712 + 10593 00ae 638D ldrh r3, [r4, #42] + 10594 00b0 9BB2 uxth r3, r3 +5854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10595 .loc 1 5854 6 view .LVU3713 + 10596 00b2 1BB1 cbz r3, .L663 +5857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10597 .loc 1 5857 5 is_stmt 1 view .LVU3714 +5857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10598 .loc 1 5857 9 is_stmt 0 view .LVU3715 + 10599 00b4 636C ldr r3, [r4, #68] +5857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10600 .loc 1 5857 21 view .LVU3716 + 10601 00b6 43F00403 orr r3, r3, #4 + 10602 00ba 6364 str r3, [r4, #68] + 10603 .L663: +5860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10604 .loc 1 5860 3 is_stmt 1 view .LVU3717 +5860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10605 .loc 1 5860 14 is_stmt 0 view .LVU3718 + 10606 00bc 0023 movs r3, #0 + 10607 00be 84F84230 strb r3, [r4, #66] +5861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10608 .loc 1 5861 3 is_stmt 1 view .LVU3719 +5861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10609 .loc 1 5861 17 is_stmt 0 view .LVU3720 + 10610 00c2 6363 str r3, [r4, #52] +5863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10611 .loc 1 5863 3 is_stmt 1 view .LVU3721 +5863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10612 .loc 1 5863 11 is_stmt 0 view .LVU3722 + 10613 00c4 636C ldr r3, [r4, #68] +5863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10614 .loc 1 5863 6 view .LVU3723 + 10615 00c6 1BBB cbnz r3, .L669 +5875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10616 .loc 1 5875 8 is_stmt 1 view .LVU3724 +5875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10617 .loc 1 5875 16 is_stmt 0 view .LVU3725 + 10618 00c8 E36A ldr r3, [r4, #44] +5875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10619 .loc 1 5875 11 view .LVU3726 + 10620 00ca 13F5803F cmn r3, #65536 + 10621 00ce 2DD1 bne .L670 +5895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10622 .loc 1 5895 8 is_stmt 1 view .LVU3727 +5895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10623 .loc 1 5895 16 is_stmt 0 view .LVU3728 + 10624 00d0 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10625 00d4 DBB2 uxtb r3, r3 +5895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10626 .loc 1 5895 11 view .LVU3729 + ARM GAS /tmp/ccE2rRGE.s page 368 + + + 10627 00d6 222B cmp r3, #34 + 10628 00d8 38D0 beq .L671 +5912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10629 .loc 1 5912 5 is_stmt 1 view .LVU3730 +5912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10630 .loc 1 5912 17 is_stmt 0 view .LVU3731 + 10631 00da 2023 movs r3, #32 + 10632 00dc 84F84130 strb r3, [r4, #65] +5913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10633 .loc 1 5913 5 is_stmt 1 view .LVU3732 +5913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10634 .loc 1 5913 25 is_stmt 0 view .LVU3733 + 10635 00e0 0023 movs r3, #0 + 10636 00e2 2363 str r3, [r4, #48] +5916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10637 .loc 1 5916 5 is_stmt 1 view .LVU3734 +5916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10638 .loc 1 5916 5 view .LVU3735 + 10639 00e4 84F84030 strb r3, [r4, #64] +5916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10640 .loc 1 5916 5 view .LVU3736 +5922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10641 .loc 1 5922 5 view .LVU3737 + 10642 00e8 2046 mov r0, r4 + 10643 00ea FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 10644 .LVL726: +5925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10645 .loc 1 5925 1 is_stmt 0 view .LVU3738 + 10646 00ee 2CE0 b .L655 + 10647 .LVL727: + 10648 .L660: +5819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10649 .loc 1 5819 8 is_stmt 1 view .LVU3739 +5819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10650 .loc 1 5819 11 is_stmt 0 view .LVU3740 + 10651 00f0 16F4004F tst r6, #32768 + 10652 00f4 C6D0 beq .L661 +5822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10653 .loc 1 5822 5 is_stmt 1 view .LVU3741 +5822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10654 .loc 1 5822 9 is_stmt 0 view .LVU3742 + 10655 00f6 2268 ldr r2, [r4] +5822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10656 .loc 1 5822 19 view .LVU3743 + 10657 00f8 1368 ldr r3, [r2] +5822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10658 .loc 1 5822 25 view .LVU3744 + 10659 00fa 23F40043 bic r3, r3, #32768 + 10660 00fe 1360 str r3, [r2] +5824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10661 .loc 1 5824 5 is_stmt 1 view .LVU3745 +5824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10662 .loc 1 5824 13 is_stmt 0 view .LVU3746 + 10663 0100 E36B ldr r3, [r4, #60] +5824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10664 .loc 1 5824 8 view .LVU3747 + 10665 0102 002B cmp r3, #0 + ARM GAS /tmp/ccE2rRGE.s page 369 + + + 10666 0104 BED0 beq .L661 +5826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10667 .loc 1 5826 7 is_stmt 1 view .LVU3748 +5826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10668 .loc 1 5826 35 is_stmt 0 view .LVU3749 + 10669 0106 1B68 ldr r3, [r3] + 10670 0108 5B68 ldr r3, [r3, #4] +5826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10671 .loc 1 5826 25 view .LVU3750 + 10672 010a 9BB2 uxth r3, r3 +5826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10673 .loc 1 5826 23 view .LVU3751 + 10674 010c 6385 strh r3, [r4, #42] @ movhi + 10675 010e B9E7 b .L661 + 10676 .LVL728: + 10677 .L669: +5866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10678 .loc 1 5866 5 is_stmt 1 view .LVU3752 +5866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10679 .loc 1 5866 27 is_stmt 0 view .LVU3753 + 10680 0110 616C ldr r1, [r4, #68] +5866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10681 .loc 1 5866 5 view .LVU3754 + 10682 0112 2046 mov r0, r4 + 10683 0114 FFF7FEFF bl I2C_ITError + 10684 .LVL729: +5869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10685 .loc 1 5869 5 is_stmt 1 view .LVU3755 +5869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10686 .loc 1 5869 13 is_stmt 0 view .LVU3756 + 10687 0118 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10688 011c DBB2 uxtb r3, r3 +5869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10689 .loc 1 5869 8 view .LVU3757 + 10690 011e 282B cmp r3, #40 + 10691 0120 13D1 bne .L655 +5872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10692 .loc 1 5872 7 is_stmt 1 view .LVU3758 + 10693 0122 2946 mov r1, r5 + 10694 0124 2046 mov r0, r4 + 10695 0126 FFF7FEFF bl I2C_ITListenCplt + 10696 .LVL730: + 10697 012a 0EE0 b .L655 + 10698 .L670: +5878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10699 .loc 1 5878 5 view .LVU3759 + 10700 012c 2046 mov r0, r4 + 10701 012e FFF7FEFF bl I2C_ITSlaveSeqCplt + 10702 .LVL731: +5880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 10703 .loc 1 5880 5 view .LVU3760 +5880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 10704 .loc 1 5880 23 is_stmt 0 view .LVU3761 + 10705 0132 0C4B ldr r3, .L672 + 10706 0134 E362 str r3, [r4, #44] +5881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10707 .loc 1 5881 5 is_stmt 1 view .LVU3762 + ARM GAS /tmp/ccE2rRGE.s page 370 + + +5881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10708 .loc 1 5881 17 is_stmt 0 view .LVU3763 + 10709 0136 2023 movs r3, #32 + 10710 0138 84F84130 strb r3, [r4, #65] +5882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10711 .loc 1 5882 5 is_stmt 1 view .LVU3764 +5882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10712 .loc 1 5882 25 is_stmt 0 view .LVU3765 + 10713 013c 0023 movs r3, #0 + 10714 013e 2363 str r3, [r4, #48] +5885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10715 .loc 1 5885 5 is_stmt 1 view .LVU3766 +5885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10716 .loc 1 5885 5 view .LVU3767 + 10717 0140 84F84030 strb r3, [r4, #64] +5885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10718 .loc 1 5885 5 view .LVU3768 +5891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10719 .loc 1 5891 5 view .LVU3769 + 10720 0144 2046 mov r0, r4 + 10721 0146 FFF7FEFF bl HAL_I2C_ListenCpltCallback + 10722 .LVL732: + 10723 .L655: +5925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10724 .loc 1 5925 1 is_stmt 0 view .LVU3770 + 10725 014a 70BD pop {r4, r5, r6, pc} + 10726 .LVL733: + 10727 .L671: +5897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10728 .loc 1 5897 5 is_stmt 1 view .LVU3771 +5897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10729 .loc 1 5897 17 is_stmt 0 view .LVU3772 + 10730 014c 2023 movs r3, #32 + 10731 014e 84F84130 strb r3, [r4, #65] +5898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10732 .loc 1 5898 5 is_stmt 1 view .LVU3773 +5898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10733 .loc 1 5898 25 is_stmt 0 view .LVU3774 + 10734 0152 0023 movs r3, #0 + 10735 0154 2363 str r3, [r4, #48] +5901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10736 .loc 1 5901 5 is_stmt 1 view .LVU3775 +5901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10737 .loc 1 5901 5 view .LVU3776 + 10738 0156 84F84030 strb r3, [r4, #64] +5901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10739 .loc 1 5901 5 view .LVU3777 +5907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10740 .loc 1 5907 5 view .LVU3778 + 10741 015a 2046 mov r0, r4 + 10742 015c FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 10743 .LVL734: + 10744 0160 F3E7 b .L655 + 10745 .L673: + 10746 0162 00BF .align 2 + 10747 .L672: + 10748 0164 0000FFFF .word -65536 + ARM GAS /tmp/ccE2rRGE.s page 371 + + + 10749 .cfi_endproc + 10750 .LFE189: + 10752 .section .text.I2C_Slave_ISR_IT,"ax",%progbits + 10753 .align 1 + 10754 .syntax unified + 10755 .thumb + 10756 .thumb_func + 10758 I2C_Slave_ISR_IT: + 10759 .LVL735: + 10760 .LFB180: +4881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10761 .loc 1 4881 1 view -0 + 10762 .cfi_startproc + 10763 @ args = 0, pretend = 0, frame = 0 + 10764 @ frame_needed = 0, uses_anonymous_args = 0 +4881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10765 .loc 1 4881 1 is_stmt 0 view .LVU3780 + 10766 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 10767 .cfi_def_cfa_offset 24 + 10768 .cfi_offset 3, -24 + 10769 .cfi_offset 4, -20 + 10770 .cfi_offset 5, -16 + 10771 .cfi_offset 6, -12 + 10772 .cfi_offset 7, -8 + 10773 .cfi_offset 14, -4 +4882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10774 .loc 1 4882 3 is_stmt 1 view .LVU3781 +4882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10775 .loc 1 4882 12 is_stmt 0 view .LVU3782 + 10776 0002 C76A ldr r7, [r0, #44] + 10777 .LVL736: +4883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10778 .loc 1 4883 3 is_stmt 1 view .LVU3783 +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10779 .loc 1 4886 3 view .LVU3784 +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10780 .loc 1 4886 3 view .LVU3785 + 10781 0004 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 10782 0008 012B cmp r3, #1 + 10783 000a 00F09E80 beq .L688 + 10784 000e 0446 mov r4, r0 + 10785 0010 0D46 mov r5, r1 + 10786 0012 1646 mov r6, r2 +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10787 .loc 1 4886 3 discriminator 2 view .LVU3786 + 10788 0014 0123 movs r3, #1 + 10789 0016 80F84030 strb r3, [r0, #64] +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10790 .loc 1 4886 3 discriminator 2 view .LVU3787 +4889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 10791 .loc 1 4889 3 discriminator 2 view .LVU3788 +4889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 10792 .loc 1 4889 6 is_stmt 0 discriminator 2 view .LVU3789 + 10793 001a 11F0200F tst r1, #32 + 10794 001e 02D0 beq .L676 +4889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 10795 .loc 1 4889 61 discriminator 1 view .LVU3790 + ARM GAS /tmp/ccE2rRGE.s page 372 + + + 10796 0020 12F0200F tst r2, #32 + 10797 0024 19D1 bne .L690 + 10798 .LVL737: + 10799 .L676: +4896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10800 .loc 1 4896 3 is_stmt 1 view .LVU3791 +4896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10801 .loc 1 4896 6 is_stmt 0 view .LVU3792 + 10802 0026 15F0100F tst r5, #16 + 10803 002a 3ED0 beq .L677 +4896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10804 .loc 1 4896 58 discriminator 1 view .LVU3793 + 10805 002c 16F0100F tst r6, #16 + 10806 0030 3BD0 beq .L677 +4903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10807 .loc 1 4903 5 is_stmt 1 view .LVU3794 +4903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10808 .loc 1 4903 13 is_stmt 0 view .LVU3795 + 10809 0032 638D ldrh r3, [r4, #42] + 10810 0034 9BB2 uxth r3, r3 +4903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10811 .loc 1 4903 8 view .LVU3796 + 10812 0036 43BB cbnz r3, .L678 +4905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 10813 .loc 1 4905 7 is_stmt 1 view .LVU3797 +4905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 10814 .loc 1 4905 16 is_stmt 0 view .LVU3798 + 10815 0038 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10816 003c DBB2 uxtb r3, r3 +4905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 10817 .loc 1 4905 10 view .LVU3799 + 10818 003e 282B cmp r3, #40 + 10819 0040 0ED0 beq .L691 + 10820 .L679: +4912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10821 .loc 1 4912 12 is_stmt 1 view .LVU3800 +4912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10822 .loc 1 4912 21 is_stmt 0 view .LVU3801 + 10823 0042 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 10824 0046 DBB2 uxtb r3, r3 +4912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10825 .loc 1 4912 15 view .LVU3802 + 10826 0048 292B cmp r3, #41 + 10827 004a 11D0 beq .L692 + 10828 .L681: +4927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10829 .loc 1 4927 9 is_stmt 1 view .LVU3803 + 10830 004c 2368 ldr r3, [r4] + 10831 004e 1022 movs r2, #16 + 10832 0050 DA61 str r2, [r3, #28] + 10833 .L680: +5004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10834 .loc 1 5004 3 view .LVU3804 +5007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10835 .loc 1 5007 3 view .LVU3805 +5007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10836 .loc 1 5007 3 view .LVU3806 + ARM GAS /tmp/ccE2rRGE.s page 373 + + + 10837 0052 0020 movs r0, #0 + 10838 0054 84F84000 strb r0, [r4, #64] +5007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10839 .loc 1 5007 3 view .LVU3807 +5009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10840 .loc 1 5009 3 view .LVU3808 + 10841 .LVL738: + 10842 .L675: +5010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10843 .loc 1 5010 1 is_stmt 0 view .LVU3809 + 10844 0058 F8BD pop {r3, r4, r5, r6, r7, pc} + 10845 .LVL739: + 10846 .L690: +4893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10847 .loc 1 4893 5 is_stmt 1 view .LVU3810 + 10848 005a FFF7FEFF bl I2C_ITSlaveCplt + 10849 .LVL740: +4893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10850 .loc 1 4893 5 is_stmt 0 view .LVU3811 + 10851 005e E2E7 b .L676 + 10852 .L691: +4905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 10853 .loc 1 4905 49 discriminator 1 view .LVU3812 + 10854 0060 B7F1007F cmp r7, #33554432 + 10855 0064 EDD1 bne .L679 +4910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10856 .loc 1 4910 9 is_stmt 1 view .LVU3813 + 10857 0066 2946 mov r1, r5 + 10858 0068 2046 mov r0, r4 + 10859 006a FFF7FEFF bl I2C_ITListenCplt + 10860 .LVL741: + 10861 006e F0E7 b .L680 + 10862 .L692: +4912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10863 .loc 1 4912 62 is_stmt 0 discriminator 1 view .LVU3814 + 10864 0070 17F5803F cmn r7, #65536 + 10865 0074 EAD0 beq .L681 +4915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10866 .loc 1 4915 9 is_stmt 1 view .LVU3815 + 10867 0076 2368 ldr r3, [r4] + 10868 0078 1022 movs r2, #16 + 10869 007a DA61 str r2, [r3, #28] +4918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10870 .loc 1 4918 9 view .LVU3816 + 10871 007c 2046 mov r0, r4 + 10872 007e FFF7FEFF bl I2C_Flush_TXDR + 10873 .LVL742: +4922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10874 .loc 1 4922 9 view .LVU3817 + 10875 0082 2046 mov r0, r4 + 10876 0084 FFF7FEFF bl I2C_ITSlaveSeqCplt + 10877 .LVL743: + 10878 0088 E3E7 b .L680 + 10879 .L678: +4934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10880 .loc 1 4934 7 view .LVU3818 + 10881 008a 2368 ldr r3, [r4] + ARM GAS /tmp/ccE2rRGE.s page 374 + + + 10882 008c 1022 movs r2, #16 + 10883 008e DA61 str r2, [r3, #28] +4937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10884 .loc 1 4937 7 view .LVU3819 +4937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10885 .loc 1 4937 11 is_stmt 0 view .LVU3820 + 10886 0090 636C ldr r3, [r4, #68] +4937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10887 .loc 1 4937 23 view .LVU3821 + 10888 0092 43F00403 orr r3, r3, #4 + 10889 0096 6364 str r3, [r4, #68] +4939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10890 .loc 1 4939 7 is_stmt 1 view .LVU3822 +4939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10891 .loc 1 4939 10 is_stmt 0 view .LVU3823 + 10892 0098 17B1 cbz r7, .L682 +4939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10893 .loc 1 4939 43 discriminator 1 view .LVU3824 + 10894 009a B7F1807F cmp r7, #16777216 + 10895 009e D8D1 bne .L680 + 10896 .L682: +4942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10897 .loc 1 4942 9 is_stmt 1 view .LVU3825 +4942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10898 .loc 1 4942 31 is_stmt 0 view .LVU3826 + 10899 00a0 616C ldr r1, [r4, #68] +4942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10900 .loc 1 4942 9 view .LVU3827 + 10901 00a2 2046 mov r0, r4 + 10902 00a4 FFF7FEFF bl I2C_ITError + 10903 .LVL744: + 10904 00a8 D3E7 b .L680 + 10905 .L677: +4946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 10906 .loc 1 4946 8 is_stmt 1 view .LVU3828 +4946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 10907 .loc 1 4946 11 is_stmt 0 view .LVU3829 + 10908 00aa 15F0040F tst r5, #4 + 10909 00ae 1FD0 beq .L683 +4946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 10910 .loc 1 4946 65 discriminator 1 view .LVU3830 + 10911 00b0 16F0040F tst r6, #4 + 10912 00b4 1CD0 beq .L683 +4949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10913 .loc 1 4949 5 is_stmt 1 view .LVU3831 +4949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10914 .loc 1 4949 13 is_stmt 0 view .LVU3832 + 10915 00b6 638D ldrh r3, [r4, #42] + 10916 00b8 9BB2 uxth r3, r3 +4949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10917 .loc 1 4949 8 view .LVU3833 + 10918 00ba 73B1 cbz r3, .L684 +4952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10919 .loc 1 4952 7 is_stmt 1 view .LVU3834 +4952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10920 .loc 1 4952 38 is_stmt 0 view .LVU3835 + 10921 00bc 2368 ldr r3, [r4] + ARM GAS /tmp/ccE2rRGE.s page 375 + + +4952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10922 .loc 1 4952 48 view .LVU3836 + 10923 00be 5A6A ldr r2, [r3, #36] +4952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10924 .loc 1 4952 12 view .LVU3837 + 10925 00c0 636A ldr r3, [r4, #36] +4952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10926 .loc 1 4952 23 view .LVU3838 + 10927 00c2 1A70 strb r2, [r3] +4955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10928 .loc 1 4955 7 is_stmt 1 view .LVU3839 +4955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10929 .loc 1 4955 11 is_stmt 0 view .LVU3840 + 10930 00c4 636A ldr r3, [r4, #36] +4955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10931 .loc 1 4955 21 view .LVU3841 + 10932 00c6 0133 adds r3, r3, #1 + 10933 00c8 6362 str r3, [r4, #36] +4957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 10934 .loc 1 4957 7 is_stmt 1 view .LVU3842 +4957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 10935 .loc 1 4957 11 is_stmt 0 view .LVU3843 + 10936 00ca 238D ldrh r3, [r4, #40] +4957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 10937 .loc 1 4957 21 view .LVU3844 + 10938 00cc 013B subs r3, r3, #1 + 10939 00ce 2385 strh r3, [r4, #40] @ movhi +4958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10940 .loc 1 4958 7 is_stmt 1 view .LVU3845 +4958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10941 .loc 1 4958 11 is_stmt 0 view .LVU3846 + 10942 00d0 638D ldrh r3, [r4, #42] + 10943 00d2 9BB2 uxth r3, r3 +4958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10944 .loc 1 4958 22 view .LVU3847 + 10945 00d4 013B subs r3, r3, #1 + 10946 00d6 9BB2 uxth r3, r3 + 10947 00d8 6385 strh r3, [r4, #42] @ movhi + 10948 .L684: +4961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10949 .loc 1 4961 5 is_stmt 1 view .LVU3848 +4961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10950 .loc 1 4961 14 is_stmt 0 view .LVU3849 + 10951 00da 638D ldrh r3, [r4, #42] + 10952 00dc 9BB2 uxth r3, r3 +4961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10953 .loc 1 4961 8 view .LVU3850 + 10954 00de 002B cmp r3, #0 + 10955 00e0 B7D1 bne .L680 +4961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10956 .loc 1 4961 33 discriminator 1 view .LVU3851 + 10957 00e2 17F5803F cmn r7, #65536 + 10958 00e6 B4D0 beq .L680 +4965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10959 .loc 1 4965 7 is_stmt 1 view .LVU3852 + 10960 00e8 2046 mov r0, r4 + 10961 00ea FFF7FEFF bl I2C_ITSlaveSeqCplt + ARM GAS /tmp/ccE2rRGE.s page 376 + + + 10962 .LVL745: + 10963 00ee B0E7 b .L680 + 10964 .L683: +4968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 10965 .loc 1 4968 8 view .LVU3853 +4968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 10966 .loc 1 4968 11 is_stmt 0 view .LVU3854 + 10967 00f0 15F0080F tst r5, #8 + 10968 00f4 02D0 beq .L685 +4968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 10969 .loc 1 4968 65 discriminator 1 view .LVU3855 + 10970 00f6 16F0080F tst r6, #8 + 10971 00fa 18D1 bne .L693 + 10972 .L685: +4973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 10973 .loc 1 4973 8 is_stmt 1 view .LVU3856 +4973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 10974 .loc 1 4973 11 is_stmt 0 view .LVU3857 + 10975 00fc 15F0020F tst r5, #2 + 10976 0100 A7D0 beq .L680 +4973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 10977 .loc 1 4973 65 discriminator 1 view .LVU3858 + 10978 0102 16F0020F tst r6, #2 + 10979 0106 A4D0 beq .L680 +4980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10980 .loc 1 4980 5 is_stmt 1 view .LVU3859 +4980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10981 .loc 1 4980 13 is_stmt 0 view .LVU3860 + 10982 0108 638D ldrh r3, [r4, #42] + 10983 010a 9BB2 uxth r3, r3 +4980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10984 .loc 1 4980 8 view .LVU3861 + 10985 010c A3B1 cbz r3, .L686 +4983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10986 .loc 1 4983 7 is_stmt 1 view .LVU3862 +4983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10987 .loc 1 4983 35 is_stmt 0 view .LVU3863 + 10988 010e 626A ldr r2, [r4, #36] +4983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10989 .loc 1 4983 11 view .LVU3864 + 10990 0110 2368 ldr r3, [r4] +4983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10991 .loc 1 4983 30 view .LVU3865 + 10992 0112 1278 ldrb r2, [r2] @ zero_extendqisi2 +4983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10993 .loc 1 4983 28 view .LVU3866 + 10994 0114 9A62 str r2, [r3, #40] +4986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10995 .loc 1 4986 7 is_stmt 1 view .LVU3867 +4986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10996 .loc 1 4986 11 is_stmt 0 view .LVU3868 + 10997 0116 636A ldr r3, [r4, #36] +4986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 10998 .loc 1 4986 21 view .LVU3869 + 10999 0118 0133 adds r3, r3, #1 + 11000 011a 6362 str r3, [r4, #36] +4988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + ARM GAS /tmp/ccE2rRGE.s page 377 + + + 11001 .loc 1 4988 7 is_stmt 1 view .LVU3870 +4988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 11002 .loc 1 4988 11 is_stmt 0 view .LVU3871 + 11003 011c 638D ldrh r3, [r4, #42] + 11004 011e 9BB2 uxth r3, r3 +4988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 11005 .loc 1 4988 22 view .LVU3872 + 11006 0120 013B subs r3, r3, #1 + 11007 0122 9BB2 uxth r3, r3 + 11008 0124 6385 strh r3, [r4, #42] @ movhi +4989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11009 .loc 1 4989 7 is_stmt 1 view .LVU3873 +4989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11010 .loc 1 4989 11 is_stmt 0 view .LVU3874 + 11011 0126 238D ldrh r3, [r4, #40] +4989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11012 .loc 1 4989 21 view .LVU3875 + 11013 0128 013B subs r3, r3, #1 + 11014 012a 2385 strh r3, [r4, #40] @ movhi + 11015 012c 91E7 b .L680 + 11016 .L693: +4971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11017 .loc 1 4971 5 is_stmt 1 view .LVU3876 + 11018 012e 2946 mov r1, r5 + 11019 0130 2046 mov r0, r4 + 11020 0132 FFF7FEFF bl I2C_ITAddrCplt + 11021 .LVL746: + 11022 0136 8CE7 b .L680 + 11023 .L686: +4993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11024 .loc 1 4993 7 view .LVU3877 +4993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11025 .loc 1 4993 10 is_stmt 0 view .LVU3878 + 11026 0138 B7F1807F cmp r7, #16777216 + 11027 013c 01D0 beq .L687 +4993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11028 .loc 1 4993 42 discriminator 1 view .LVU3879 + 11029 013e 002F cmp r7, #0 + 11030 0140 87D1 bne .L680 + 11031 .L687: +4997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11032 .loc 1 4997 9 is_stmt 1 view .LVU3880 + 11033 0142 2046 mov r0, r4 + 11034 0144 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11035 .LVL747: + 11036 0148 83E7 b .L680 + 11037 .LVL748: + 11038 .L688: +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11039 .loc 1 4886 3 is_stmt 0 view .LVU3881 + 11040 014a 0220 movs r0, #2 + 11041 .LVL749: +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11042 .loc 1 4886 3 view .LVU3882 + 11043 014c 84E7 b .L675 + 11044 .cfi_endproc + 11045 .LFE180: + ARM GAS /tmp/ccE2rRGE.s page 378 + + + 11047 .section .text.I2C_ITMasterCplt,"ax",%progbits + 11048 .align 1 + 11049 .syntax unified + 11050 .thumb + 11051 .thumb_func + 11053 I2C_ITMasterCplt: + 11054 .LVL750: + 11055 .LFB188: +5632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmperror; + 11056 .loc 1 5632 1 is_stmt 1 view -0 + 11057 .cfi_startproc + 11058 @ args = 0, pretend = 0, frame = 8 + 11059 @ frame_needed = 0, uses_anonymous_args = 0 +5632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmperror; + 11060 .loc 1 5632 1 is_stmt 0 view .LVU3884 + 11061 0000 30B5 push {r4, r5, lr} + 11062 .cfi_def_cfa_offset 12 + 11063 .cfi_offset 4, -12 + 11064 .cfi_offset 5, -8 + 11065 .cfi_offset 14, -4 + 11066 0002 83B0 sub sp, sp, #12 + 11067 .cfi_def_cfa_offset 24 + 11068 0004 0446 mov r4, r0 + 11069 0006 0D46 mov r5, r1 +5633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11070 .loc 1 5633 3 is_stmt 1 view .LVU3885 +5634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __IO uint32_t tmpreg; + 11071 .loc 1 5634 3 view .LVU3886 + 11072 .LVL751: +5635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11073 .loc 1 5635 3 view .LVU3887 +5638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11074 .loc 1 5638 3 view .LVU3888 + 11075 0008 0368 ldr r3, [r0] + 11076 000a 2022 movs r2, #32 + 11077 000c DA61 str r2, [r3, #28] +5641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11078 .loc 1 5641 3 view .LVU3889 +5641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11079 .loc 1 5641 11 is_stmt 0 view .LVU3890 + 11080 000e 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 11081 0012 DBB2 uxtb r3, r3 +5641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11082 .loc 1 5641 6 view .LVU3891 + 11083 0014 212B cmp r3, #33 + 11084 0016 33D0 beq .L706 +5646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11085 .loc 1 5646 8 is_stmt 1 view .LVU3892 +5646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11086 .loc 1 5646 16 is_stmt 0 view .LVU3893 + 11087 0018 90F84130 ldrb r3, [r0, #65] @ zero_extendqisi2 + 11088 001c DBB2 uxtb r3, r3 +5646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11089 .loc 1 5646 11 view .LVU3894 + 11090 001e 222B cmp r3, #34 + 11091 0020 34D0 beq .L707 + 11092 .LVL752: + ARM GAS /tmp/ccE2rRGE.s page 379 + + + 11093 .L696: +5654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11094 .loc 1 5654 3 is_stmt 1 view .LVU3895 +5657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11095 .loc 1 5657 3 view .LVU3896 + 11096 0022 2268 ldr r2, [r4] + 11097 0024 5368 ldr r3, [r2, #4] + 11098 0026 23F0FF73 bic r3, r3, #33423360 + 11099 002a 23F48B33 bic r3, r3, #71168 + 11100 002e 23F4FF73 bic r3, r3, #510 + 11101 0032 23F00103 bic r3, r3, #1 + 11102 0036 5360 str r3, [r2, #4] +5660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11103 .loc 1 5660 3 view .LVU3897 +5660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11104 .loc 1 5660 23 is_stmt 0 view .LVU3898 + 11105 0038 0023 movs r3, #0 + 11106 003a 6363 str r3, [r4, #52] +5661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11107 .loc 1 5661 3 is_stmt 1 view .LVU3899 +5661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11108 .loc 1 5661 23 is_stmt 0 view .LVU3900 + 11109 003c A3F58033 sub r3, r3, #65536 + 11110 0040 E362 str r3, [r4, #44] +5663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11111 .loc 1 5663 3 is_stmt 1 view .LVU3901 +5663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11112 .loc 1 5663 6 is_stmt 0 view .LVU3902 + 11113 0042 15F0100F tst r5, #16 + 11114 0046 06D0 beq .L697 +5666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11115 .loc 1 5666 5 is_stmt 1 view .LVU3903 + 11116 0048 2368 ldr r3, [r4] + 11117 004a 1022 movs r2, #16 + 11118 004c DA61 str r2, [r3, #28] +5669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11119 .loc 1 5669 5 view .LVU3904 +5669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11120 .loc 1 5669 9 is_stmt 0 view .LVU3905 + 11121 004e 636C ldr r3, [r4, #68] +5669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11122 .loc 1 5669 21 view .LVU3906 + 11123 0050 43F00403 orr r3, r3, #4 + 11124 0054 6364 str r3, [r4, #68] + 11125 .L697: +5673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11126 .loc 1 5673 3 is_stmt 1 view .LVU3907 +5673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11127 .loc 1 5673 12 is_stmt 0 view .LVU3908 + 11128 0056 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11129 005a DBB2 uxtb r3, r3 +5673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11130 .loc 1 5673 6 view .LVU3909 + 11131 005c 602B cmp r3, #96 + 11132 005e 1BD0 beq .L708 + 11133 .L698: +5681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 380 + + + 11134 .loc 1 5681 3 is_stmt 1 view .LVU3910 + 11135 0060 2046 mov r0, r4 + 11136 0062 FFF7FEFF bl I2C_Flush_TXDR + 11137 .LVL753: +5684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11138 .loc 1 5684 3 view .LVU3911 +5684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11139 .loc 1 5684 12 is_stmt 0 view .LVU3912 + 11140 0066 626C ldr r2, [r4, #68] + 11141 .LVL754: +5687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11142 .loc 1 5687 3 is_stmt 1 view .LVU3913 +5687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11143 .loc 1 5687 12 is_stmt 0 view .LVU3914 + 11144 0068 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11145 006c DBB2 uxtb r3, r3 +5687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11146 .loc 1 5687 6 view .LVU3915 + 11147 006e 602B cmp r3, #96 + 11148 0070 00D0 beq .L699 +5687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11149 .loc 1 5687 44 discriminator 1 view .LVU3916 + 11150 0072 D2B1 cbz r2, .L700 + 11151 .L699: +5690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11152 .loc 1 5690 5 is_stmt 1 view .LVU3917 +5690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11153 .loc 1 5690 27 is_stmt 0 view .LVU3918 + 11154 0074 616C ldr r1, [r4, #68] +5690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11155 .loc 1 5690 5 view .LVU3919 + 11156 0076 2046 mov r0, r4 + 11157 0078 FFF7FEFF bl I2C_ITError + 11158 .LVL755: + 11159 .L694: +5766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11160 .loc 1 5766 1 view .LVU3920 + 11161 007c 03B0 add sp, sp, #12 + 11162 .cfi_remember_state + 11163 .cfi_def_cfa_offset 12 + 11164 @ sp needed + 11165 007e 30BD pop {r4, r5, pc} + 11166 .LVL756: + 11167 .L706: + 11168 .cfi_restore_state +5643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 11169 .loc 1 5643 5 is_stmt 1 view .LVU3921 + 11170 0080 0121 movs r1, #1 + 11171 .LVL757: +5643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 11172 .loc 1 5643 5 is_stmt 0 view .LVU3922 + 11173 0082 FFF7FEFF bl I2C_Disable_IRQ + 11174 .LVL758: +5644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11175 .loc 1 5644 5 is_stmt 1 view .LVU3923 +5644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11176 .loc 1 5644 25 is_stmt 0 view .LVU3924 + ARM GAS /tmp/ccE2rRGE.s page 381 + + + 11177 0086 1123 movs r3, #17 + 11178 0088 2363 str r3, [r4, #48] + 11179 008a CAE7 b .L696 + 11180 .LVL759: + 11181 .L707: +5648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 11182 .loc 1 5648 5 is_stmt 1 view .LVU3925 + 11183 008c 0221 movs r1, #2 + 11184 .LVL760: +5648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 11185 .loc 1 5648 5 is_stmt 0 view .LVU3926 + 11186 008e FFF7FEFF bl I2C_Disable_IRQ + 11187 .LVL761: +5649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11188 .loc 1 5649 5 is_stmt 1 view .LVU3927 +5649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11189 .loc 1 5649 25 is_stmt 0 view .LVU3928 + 11190 0092 1223 movs r3, #18 + 11191 0094 2363 str r3, [r4, #48] + 11192 0096 C4E7 b .L696 + 11193 .L708: +5673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11194 .loc 1 5673 44 discriminator 1 view .LVU3929 + 11195 0098 15F0040F tst r5, #4 + 11196 009c E0D0 beq .L698 +5676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(tmpreg); + 11197 .loc 1 5676 5 is_stmt 1 view .LVU3930 +5676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(tmpreg); + 11198 .loc 1 5676 27 is_stmt 0 view .LVU3931 + 11199 009e 2368 ldr r3, [r4] +5676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(tmpreg); + 11200 .loc 1 5676 37 view .LVU3932 + 11201 00a0 5B6A ldr r3, [r3, #36] + 11202 00a2 DBB2 uxtb r3, r3 +5676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(tmpreg); + 11203 .loc 1 5676 12 view .LVU3933 + 11204 00a4 0193 str r3, [sp, #4] +5677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11205 .loc 1 5677 5 is_stmt 1 view .LVU3934 + 11206 00a6 019B ldr r3, [sp, #4] + 11207 00a8 DAE7 b .L698 + 11208 .LVL762: + 11209 .L700: +5693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11210 .loc 1 5693 8 view .LVU3935 +5693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11211 .loc 1 5693 16 is_stmt 0 view .LVU3936 + 11212 00aa 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11213 00ae DBB2 uxtb r3, r3 +5693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11214 .loc 1 5693 11 view .LVU3937 + 11215 00b0 212B cmp r3, #33 + 11216 00b2 17D0 beq .L709 +5728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11217 .loc 1 5728 8 is_stmt 1 view .LVU3938 +5728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11218 .loc 1 5728 16 is_stmt 0 view .LVU3939 + ARM GAS /tmp/ccE2rRGE.s page 382 + + + 11219 00b4 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11220 00b8 DBB2 uxtb r3, r3 +5728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11221 .loc 1 5728 11 view .LVU3940 + 11222 00ba 222B cmp r3, #34 + 11223 00bc DED1 bne .L694 +5730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11224 .loc 1 5730 5 is_stmt 1 view .LVU3941 +5730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11225 .loc 1 5730 17 is_stmt 0 view .LVU3942 + 11226 00be 2023 movs r3, #32 + 11227 00c0 84F84130 strb r3, [r4, #65] +5731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11228 .loc 1 5731 5 is_stmt 1 view .LVU3943 +5731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11229 .loc 1 5731 25 is_stmt 0 view .LVU3944 + 11230 00c4 0023 movs r3, #0 + 11231 00c6 2363 str r3, [r4, #48] +5733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11232 .loc 1 5733 5 is_stmt 1 view .LVU3945 +5733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11233 .loc 1 5733 13 is_stmt 0 view .LVU3946 + 11234 00c8 94F84230 ldrb r3, [r4, #66] @ zero_extendqisi2 + 11235 00cc DBB2 uxtb r3, r3 +5733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11236 .loc 1 5733 8 view .LVU3947 + 11237 00ce 402B cmp r3, #64 + 11238 00d0 24D0 beq .L710 +5749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11239 .loc 1 5749 7 is_stmt 1 view .LVU3948 +5749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11240 .loc 1 5749 18 is_stmt 0 view .LVU3949 + 11241 00d2 0023 movs r3, #0 + 11242 00d4 84F84230 strb r3, [r4, #66] +5752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11243 .loc 1 5752 7 is_stmt 1 view .LVU3950 +5752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11244 .loc 1 5752 7 view .LVU3951 + 11245 00d8 84F84030 strb r3, [r4, #64] +5752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11246 .loc 1 5752 7 view .LVU3952 +5758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11247 .loc 1 5758 7 view .LVU3953 + 11248 00dc 2046 mov r0, r4 + 11249 00de FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 11250 .LVL763: +5765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11251 .loc 1 5765 3 view .LVU3954 +5766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11252 .loc 1 5766 1 is_stmt 0 view .LVU3955 + 11253 00e2 CBE7 b .L694 + 11254 .LVL764: + 11255 .L709: +5695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11256 .loc 1 5695 5 is_stmt 1 view .LVU3956 +5695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11257 .loc 1 5695 17 is_stmt 0 view .LVU3957 + ARM GAS /tmp/ccE2rRGE.s page 383 + + + 11258 00e4 2023 movs r3, #32 + 11259 00e6 84F84130 strb r3, [r4, #65] +5696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11260 .loc 1 5696 5 is_stmt 1 view .LVU3958 +5696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11261 .loc 1 5696 25 is_stmt 0 view .LVU3959 + 11262 00ea 0023 movs r3, #0 + 11263 00ec 2363 str r3, [r4, #48] +5698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11264 .loc 1 5698 5 is_stmt 1 view .LVU3960 +5698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11265 .loc 1 5698 13 is_stmt 0 view .LVU3961 + 11266 00ee 94F84230 ldrb r3, [r4, #66] @ zero_extendqisi2 + 11267 00f2 DBB2 uxtb r3, r3 +5698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11268 .loc 1 5698 8 view .LVU3962 + 11269 00f4 402B cmp r3, #64 + 11270 00f6 08D0 beq .L711 +5714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11271 .loc 1 5714 7 is_stmt 1 view .LVU3963 +5714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11272 .loc 1 5714 18 is_stmt 0 view .LVU3964 + 11273 00f8 0023 movs r3, #0 + 11274 00fa 84F84230 strb r3, [r4, #66] +5717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11275 .loc 1 5717 7 is_stmt 1 view .LVU3965 +5717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11276 .loc 1 5717 7 view .LVU3966 + 11277 00fe 84F84030 strb r3, [r4, #64] +5717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11278 .loc 1 5717 7 view .LVU3967 +5723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11279 .loc 1 5723 7 view .LVU3968 + 11280 0102 2046 mov r0, r4 + 11281 0104 FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 11282 .LVL765: +5723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11283 .loc 1 5723 7 is_stmt 0 view .LVU3969 + 11284 0108 B8E7 b .L694 + 11285 .LVL766: + 11286 .L711: +5700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11287 .loc 1 5700 7 is_stmt 1 view .LVU3970 +5700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11288 .loc 1 5700 18 is_stmt 0 view .LVU3971 + 11289 010a 0023 movs r3, #0 + 11290 010c 84F84230 strb r3, [r4, #66] +5703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11291 .loc 1 5703 7 is_stmt 1 view .LVU3972 +5703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11292 .loc 1 5703 7 view .LVU3973 + 11293 0110 84F84030 strb r3, [r4, #64] +5703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11294 .loc 1 5703 7 view .LVU3974 +5709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11295 .loc 1 5709 7 view .LVU3975 + 11296 0114 2046 mov r0, r4 + ARM GAS /tmp/ccE2rRGE.s page 384 + + + 11297 0116 FFF7FEFF bl HAL_I2C_MemTxCpltCallback + 11298 .LVL767: +5709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11299 .loc 1 5709 7 is_stmt 0 view .LVU3976 + 11300 011a AFE7 b .L694 + 11301 .LVL768: + 11302 .L710: +5735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11303 .loc 1 5735 7 is_stmt 1 view .LVU3977 +5735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11304 .loc 1 5735 18 is_stmt 0 view .LVU3978 + 11305 011c 0023 movs r3, #0 + 11306 011e 84F84230 strb r3, [r4, #66] +5738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11307 .loc 1 5738 7 is_stmt 1 view .LVU3979 +5738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11308 .loc 1 5738 7 view .LVU3980 + 11309 0122 84F84030 strb r3, [r4, #64] +5738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11310 .loc 1 5738 7 view .LVU3981 +5744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11311 .loc 1 5744 7 view .LVU3982 + 11312 0126 2046 mov r0, r4 + 11313 0128 FFF7FEFF bl HAL_I2C_MemRxCpltCallback + 11314 .LVL769: +5744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11315 .loc 1 5744 7 is_stmt 0 view .LVU3983 + 11316 012c A6E7 b .L694 + 11317 .cfi_endproc + 11318 .LFE188: + 11320 .section .text.I2C_Master_ISR_IT,"ax",%progbits + 11321 .align 1 + 11322 .syntax unified + 11323 .thumb + 11324 .thumb_func + 11326 I2C_Master_ISR_IT: + 11327 .LVL770: + 11328 .LFB179: +4735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t devaddress; + 11329 .loc 1 4735 1 is_stmt 1 view -0 + 11330 .cfi_startproc + 11331 @ args = 0, pretend = 0, frame = 0 + 11332 @ frame_needed = 0, uses_anonymous_args = 0 +4736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11333 .loc 1 4736 3 view .LVU3985 +4737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11334 .loc 1 4737 3 view .LVU3986 +4740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11335 .loc 1 4740 3 view .LVU3987 +4740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11336 .loc 1 4740 3 view .LVU3988 + 11337 0000 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 11338 0004 012B cmp r3, #1 + 11339 0006 00F0B980 beq .L726 +4735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t devaddress; + 11340 .loc 1 4735 1 is_stmt 0 discriminator 2 view .LVU3989 + 11341 000a 70B5 push {r4, r5, r6, lr} + ARM GAS /tmp/ccE2rRGE.s page 385 + + + 11342 .cfi_def_cfa_offset 16 + 11343 .cfi_offset 4, -16 + 11344 .cfi_offset 5, -12 + 11345 .cfi_offset 6, -8 + 11346 .cfi_offset 14, -4 + 11347 000c 82B0 sub sp, sp, #8 + 11348 .cfi_def_cfa_offset 24 + 11349 000e 0446 mov r4, r0 + 11350 0010 0D46 mov r5, r1 + 11351 0012 1646 mov r6, r2 +4740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11352 .loc 1 4740 3 is_stmt 1 discriminator 2 view .LVU3990 + 11353 0014 0123 movs r3, #1 + 11354 0016 80F84030 strb r3, [r0, #64] +4740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11355 .loc 1 4740 3 discriminator 2 view .LVU3991 +4742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11356 .loc 1 4742 3 discriminator 2 view .LVU3992 +4742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11357 .loc 1 4742 6 is_stmt 0 discriminator 2 view .LVU3993 + 11358 001a 11F0100F tst r1, #16 + 11359 001e 02D0 beq .L714 +4742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11360 .loc 1 4742 58 discriminator 1 view .LVU3994 + 11361 0020 12F0100F tst r2, #16 + 11362 0024 22D1 bne .L731 + 11363 .L714: +4756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11364 .loc 1 4756 8 is_stmt 1 view .LVU3995 +4756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11365 .loc 1 4756 11 is_stmt 0 view .LVU3996 + 11366 0026 15F0040F tst r5, #4 + 11367 002a 29D0 beq .L716 +4756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11368 .loc 1 4756 65 discriminator 1 view .LVU3997 + 11369 002c 16F0040F tst r6, #4 + 11370 0030 26D0 beq .L716 +4760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11371 .loc 1 4760 5 is_stmt 1 view .LVU3998 +4760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11372 .loc 1 4760 16 is_stmt 0 view .LVU3999 + 11373 0032 25F00405 bic r5, r5, #4 + 11374 .LVL771: +4763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11375 .loc 1 4763 5 is_stmt 1 view .LVU4000 +4763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11376 .loc 1 4763 36 is_stmt 0 view .LVU4001 + 11377 0036 2368 ldr r3, [r4] +4763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11378 .loc 1 4763 46 view .LVU4002 + 11379 0038 5A6A ldr r2, [r3, #36] + 11380 .LVL772: +4763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11381 .loc 1 4763 10 view .LVU4003 + 11382 003a 636A ldr r3, [r4, #36] +4763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11383 .loc 1 4763 21 view .LVU4004 + ARM GAS /tmp/ccE2rRGE.s page 386 + + + 11384 003c 1A70 strb r2, [r3] +4766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11385 .loc 1 4766 5 is_stmt 1 view .LVU4005 +4766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11386 .loc 1 4766 9 is_stmt 0 view .LVU4006 + 11387 003e 636A ldr r3, [r4, #36] +4766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11388 .loc 1 4766 19 view .LVU4007 + 11389 0040 0133 adds r3, r3, #1 + 11390 0042 6362 str r3, [r4, #36] +4768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 11391 .loc 1 4768 5 is_stmt 1 view .LVU4008 +4768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 11392 .loc 1 4768 9 is_stmt 0 view .LVU4009 + 11393 0044 238D ldrh r3, [r4, #40] +4768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 11394 .loc 1 4768 19 view .LVU4010 + 11395 0046 013B subs r3, r3, #1 + 11396 0048 2385 strh r3, [r4, #40] @ movhi +4769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11397 .loc 1 4769 5 is_stmt 1 view .LVU4011 +4769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11398 .loc 1 4769 9 is_stmt 0 view .LVU4012 + 11399 004a 638D ldrh r3, [r4, #42] + 11400 004c 9BB2 uxth r3, r3 +4769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11401 .loc 1 4769 20 view .LVU4013 + 11402 004e 013B subs r3, r3, #1 + 11403 0050 9BB2 uxth r3, r3 + 11404 0052 6385 strh r3, [r4, #42] @ movhi + 11405 .LVL773: + 11406 .L715: +4856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11407 .loc 1 4856 3 is_stmt 1 view .LVU4014 +4858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11408 .loc 1 4858 3 view .LVU4015 +4858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11409 .loc 1 4858 6 is_stmt 0 view .LVU4016 + 11410 0054 15F0200F tst r5, #32 + 11411 0058 03D0 beq .L725 +4858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11412 .loc 1 4858 61 discriminator 1 view .LVU4017 + 11413 005a 16F0200F tst r6, #32 + 11414 005e 40F08880 bne .L732 + 11415 .L725: +4866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11416 .loc 1 4866 3 is_stmt 1 view .LVU4018 +4866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11417 .loc 1 4866 3 view .LVU4019 + 11418 0062 0020 movs r0, #0 + 11419 0064 84F84000 strb r0, [r4, #64] +4866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11420 .loc 1 4866 3 view .LVU4020 +4868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11421 .loc 1 4868 3 view .LVU4021 +4869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11422 .loc 1 4869 1 is_stmt 0 view .LVU4022 + ARM GAS /tmp/ccE2rRGE.s page 387 + + + 11423 0068 02B0 add sp, sp, #8 + 11424 .cfi_remember_state + 11425 .cfi_def_cfa_offset 16 + 11426 @ sp needed + 11427 006a 70BD pop {r4, r5, r6, pc} + 11428 .LVL774: + 11429 .L731: + 11430 .cfi_restore_state +4746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11431 .loc 1 4746 5 is_stmt 1 view .LVU4023 + 11432 006c 0368 ldr r3, [r0] + 11433 006e 1022 movs r2, #16 + 11434 .LVL775: +4746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11435 .loc 1 4746 5 is_stmt 0 view .LVU4024 + 11436 0070 DA61 str r2, [r3, #28] +4751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11437 .loc 1 4751 5 is_stmt 1 view .LVU4025 +4751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11438 .loc 1 4751 9 is_stmt 0 view .LVU4026 + 11439 0072 436C ldr r3, [r0, #68] +4751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11440 .loc 1 4751 21 view .LVU4027 + 11441 0074 43F00403 orr r3, r3, #4 + 11442 0078 4364 str r3, [r0, #68] +4754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11443 .loc 1 4754 5 is_stmt 1 view .LVU4028 + 11444 007a FFF7FEFF bl I2C_Flush_TXDR + 11445 .LVL776: +4754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11446 .loc 1 4754 5 is_stmt 0 view .LVU4029 + 11447 007e E9E7 b .L715 + 11448 .LVL777: + 11449 .L716: +4771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 11450 .loc 1 4771 8 is_stmt 1 view .LVU4030 +4771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 11451 .loc 1 4771 11 is_stmt 0 view .LVU4031 + 11452 0080 15F0020F tst r5, #2 + 11453 0084 12D0 beq .L717 +4771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 11454 .loc 1 4771 65 discriminator 1 view .LVU4032 + 11455 0086 16F0020F tst r6, #2 + 11456 008a 0FD0 beq .L717 +4775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11457 .loc 1 4775 5 is_stmt 1 view .LVU4033 +4775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11458 .loc 1 4775 33 is_stmt 0 view .LVU4034 + 11459 008c 626A ldr r2, [r4, #36] + 11460 .LVL778: +4775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11461 .loc 1 4775 9 view .LVU4035 + 11462 008e 2368 ldr r3, [r4] +4775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11463 .loc 1 4775 28 view .LVU4036 + 11464 0090 1278 ldrb r2, [r2] @ zero_extendqisi2 +4775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 388 + + + 11465 .loc 1 4775 26 view .LVU4037 + 11466 0092 9A62 str r2, [r3, #40] +4778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11467 .loc 1 4778 5 is_stmt 1 view .LVU4038 +4778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11468 .loc 1 4778 9 is_stmt 0 view .LVU4039 + 11469 0094 636A ldr r3, [r4, #36] +4778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11470 .loc 1 4778 19 view .LVU4040 + 11471 0096 0133 adds r3, r3, #1 + 11472 0098 6362 str r3, [r4, #36] +4780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 11473 .loc 1 4780 5 is_stmt 1 view .LVU4041 +4780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 11474 .loc 1 4780 9 is_stmt 0 view .LVU4042 + 11475 009a 238D ldrh r3, [r4, #40] +4780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 11476 .loc 1 4780 19 view .LVU4043 + 11477 009c 013B subs r3, r3, #1 + 11478 009e 2385 strh r3, [r4, #40] @ movhi +4781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11479 .loc 1 4781 5 is_stmt 1 view .LVU4044 +4781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11480 .loc 1 4781 9 is_stmt 0 view .LVU4045 + 11481 00a0 638D ldrh r3, [r4, #42] + 11482 00a2 9BB2 uxth r3, r3 +4781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11483 .loc 1 4781 20 view .LVU4046 + 11484 00a4 013B subs r3, r3, #1 + 11485 00a6 9BB2 uxth r3, r3 + 11486 00a8 6385 strh r3, [r4, #42] @ movhi + 11487 00aa D3E7 b .L715 + 11488 .LVL779: + 11489 .L717: +4783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 11490 .loc 1 4783 8 is_stmt 1 view .LVU4047 +4783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 11491 .loc 1 4783 11 is_stmt 0 view .LVU4048 + 11492 00ac 15F0800F tst r5, #128 + 11493 00b0 3FD0 beq .L718 +4783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 11494 .loc 1 4783 64 discriminator 1 view .LVU4049 + 11495 00b2 16F0400F tst r6, #64 + 11496 00b6 3CD0 beq .L718 +4786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11497 .loc 1 4786 5 is_stmt 1 view .LVU4050 +4786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11498 .loc 1 4786 14 is_stmt 0 view .LVU4051 + 11499 00b8 638D ldrh r3, [r4, #42] + 11500 00ba 9BB2 uxth r3, r3 +4786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11501 .loc 1 4786 8 view .LVU4052 + 11502 00bc 5BB3 cbz r3, .L719 +4786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11503 .loc 1 4786 41 discriminator 1 view .LVU4053 + 11504 00be 238D ldrh r3, [r4, #40] +4786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 389 + + + 11505 .loc 1 4786 33 discriminator 1 view .LVU4054 + 11506 00c0 4BBB cbnz r3, .L719 +4788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11507 .loc 1 4788 7 is_stmt 1 view .LVU4055 +4788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11508 .loc 1 4788 35 is_stmt 0 view .LVU4056 + 11509 00c2 2368 ldr r3, [r4] +4788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11510 .loc 1 4788 45 view .LVU4057 + 11511 00c4 5968 ldr r1, [r3, #4] + 11512 .LVL780: +4788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11513 .loc 1 4788 18 view .LVU4058 + 11514 00c6 C1F30901 ubfx r1, r1, #0, #10 + 11515 .LVL781: +4790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11516 .loc 1 4790 7 is_stmt 1 view .LVU4059 +4790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11517 .loc 1 4790 15 is_stmt 0 view .LVU4060 + 11518 00ca 638D ldrh r3, [r4, #42] + 11519 00cc 9BB2 uxth r3, r3 +4790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11520 .loc 1 4790 10 view .LVU4061 + 11521 00ce FF2B cmp r3, #255 + 11522 00d0 0ED8 bhi .L733 +4797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 11523 .loc 1 4797 9 is_stmt 1 view .LVU4062 +4797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 11524 .loc 1 4797 30 is_stmt 0 view .LVU4063 + 11525 00d2 628D ldrh r2, [r4, #42] + 11526 .LVL782: +4797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 11527 .loc 1 4797 30 view .LVU4064 + 11528 00d4 92B2 uxth r2, r2 +4797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 11529 .loc 1 4797 24 view .LVU4065 + 11530 00d6 2285 strh r2, [r4, #40] @ movhi +4798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11531 .loc 1 4798 9 is_stmt 1 view .LVU4066 +4798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11532 .loc 1 4798 17 is_stmt 0 view .LVU4067 + 11533 00d8 E36A ldr r3, [r4, #44] +4798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11534 .loc 1 4798 12 view .LVU4068 + 11535 00da 13F5803F cmn r3, #65536 + 11536 00de 11D0 beq .L721 +4800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 11537 .loc 1 4800 11 is_stmt 1 view .LVU4069 +4801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11538 .loc 1 4801 34 is_stmt 0 view .LVU4070 + 11539 00e0 E36A ldr r3, [r4, #44] +4800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 11540 .loc 1 4800 11 view .LVU4071 + 11541 00e2 0020 movs r0, #0 + 11542 .LVL783: +4800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 11543 .loc 1 4800 11 view .LVU4072 + ARM GAS /tmp/ccE2rRGE.s page 390 + + + 11544 00e4 0090 str r0, [sp] + 11545 00e6 D2B2 uxtb r2, r2 + 11546 00e8 2046 mov r0, r4 + 11547 00ea FFF7FEFF bl I2C_TransferConfig + 11548 .LVL784: +4800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 11549 .loc 1 4800 11 view .LVU4073 + 11550 00ee B1E7 b .L715 + 11551 .LVL785: + 11552 .L733: +4792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 11553 .loc 1 4792 9 is_stmt 1 view .LVU4074 +4792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 11554 .loc 1 4792 24 is_stmt 0 view .LVU4075 + 11555 00f0 FF22 movs r2, #255 + 11556 .LVL786: +4792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 11557 .loc 1 4792 24 view .LVU4076 + 11558 00f2 2285 strh r2, [r4, #40] @ movhi +4793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11559 .loc 1 4793 9 is_stmt 1 view .LVU4077 + 11560 00f4 0023 movs r3, #0 + 11561 00f6 0093 str r3, [sp] + 11562 00f8 4FF08073 mov r3, #16777216 + 11563 00fc 2046 mov r0, r4 + 11564 .LVL787: +4793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11565 .loc 1 4793 9 is_stmt 0 view .LVU4078 + 11566 00fe FFF7FEFF bl I2C_TransferConfig + 11567 .LVL788: +4793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11568 .loc 1 4793 9 view .LVU4079 + 11569 0102 A7E7 b .L715 + 11570 .LVL789: + 11571 .L721: +4805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 11572 .loc 1 4805 11 is_stmt 1 view .LVU4080 + 11573 0104 0023 movs r3, #0 + 11574 0106 0093 str r3, [sp] + 11575 0108 4FF00073 mov r3, #33554432 + 11576 010c D2B2 uxtb r2, r2 + 11577 010e 2046 mov r0, r4 + 11578 .LVL790: +4805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 11579 .loc 1 4805 11 is_stmt 0 view .LVU4081 + 11580 0110 FFF7FEFF bl I2C_TransferConfig + 11581 .LVL791: +4805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 11582 .loc 1 4805 11 view .LVU4082 + 11583 0114 9EE7 b .L715 + 11584 .LVL792: + 11585 .L719: +4813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11586 .loc 1 4813 7 is_stmt 1 view .LVU4083 +4813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11587 .loc 1 4813 11 is_stmt 0 view .LVU4084 + 11588 0116 2368 ldr r3, [r4] + ARM GAS /tmp/ccE2rRGE.s page 391 + + + 11589 0118 5B68 ldr r3, [r3, #4] +4813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11590 .loc 1 4813 10 view .LVU4085 + 11591 011a 13F0007F tst r3, #33554432 + 11592 011e 03D1 bne .L722 +4816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11593 .loc 1 4816 9 is_stmt 1 view .LVU4086 + 11594 0120 2046 mov r0, r4 + 11595 .LVL793: +4816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11596 .loc 1 4816 9 is_stmt 0 view .LVU4087 + 11597 0122 FFF7FEFF bl I2C_ITMasterSeqCplt + 11598 .LVL794: +4816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11599 .loc 1 4816 9 view .LVU4088 + 11600 0126 95E7 b .L715 + 11601 .LVL795: + 11602 .L722: +4822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11603 .loc 1 4822 9 is_stmt 1 view .LVU4089 + 11604 0128 4021 movs r1, #64 + 11605 .LVL796: +4822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11606 .loc 1 4822 9 is_stmt 0 view .LVU4090 + 11607 012a 2046 mov r0, r4 + 11608 .LVL797: +4822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11609 .loc 1 4822 9 view .LVU4091 + 11610 012c FFF7FEFF bl I2C_ITError + 11611 .LVL798: +4822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11612 .loc 1 4822 9 view .LVU4092 + 11613 0130 90E7 b .L715 + 11614 .LVL799: + 11615 .L718: +4826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 11616 .loc 1 4826 8 is_stmt 1 view .LVU4093 +4826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 11617 .loc 1 4826 11 is_stmt 0 view .LVU4094 + 11618 0132 15F0400F tst r5, #64 + 11619 0136 8DD0 beq .L715 +4826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 11620 .loc 1 4826 63 discriminator 1 view .LVU4095 + 11621 0138 16F0400F tst r6, #64 + 11622 013c 8AD0 beq .L715 +4829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11623 .loc 1 4829 5 is_stmt 1 view .LVU4096 +4829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11624 .loc 1 4829 13 is_stmt 0 view .LVU4097 + 11625 013e 638D ldrh r3, [r4, #42] + 11626 0140 9BB2 uxth r3, r3 +4829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11627 .loc 1 4829 8 view .LVU4098 + 11628 0142 8BB9 cbnz r3, .L723 +4831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11629 .loc 1 4831 7 is_stmt 1 view .LVU4099 +4831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/ccE2rRGE.s page 392 + + + 11630 .loc 1 4831 11 is_stmt 0 view .LVU4100 + 11631 0144 2368 ldr r3, [r4] + 11632 0146 5A68 ldr r2, [r3, #4] + 11633 .LVL800: +4831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11634 .loc 1 4831 10 view .LVU4101 + 11635 0148 12F0007F tst r2, #33554432 + 11636 014c 82D1 bne .L715 +4834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11637 .loc 1 4834 9 is_stmt 1 view .LVU4102 +4834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11638 .loc 1 4834 17 is_stmt 0 view .LVU4103 + 11639 014e E26A ldr r2, [r4, #44] +4834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11640 .loc 1 4834 12 view .LVU4104 + 11641 0150 12F5803F cmn r2, #65536 + 11642 0154 04D1 bne .L724 +4837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11643 .loc 1 4837 11 is_stmt 1 view .LVU4105 +4837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11644 .loc 1 4837 25 is_stmt 0 view .LVU4106 + 11645 0156 5A68 ldr r2, [r3, #4] +4837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11646 .loc 1 4837 31 view .LVU4107 + 11647 0158 42F48042 orr r2, r2, #16384 + 11648 015c 5A60 str r2, [r3, #4] + 11649 015e 79E7 b .L715 + 11650 .L724: +4842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11651 .loc 1 4842 11 is_stmt 1 view .LVU4108 + 11652 0160 2046 mov r0, r4 + 11653 .LVL801: +4842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11654 .loc 1 4842 11 is_stmt 0 view .LVU4109 + 11655 0162 FFF7FEFF bl I2C_ITMasterSeqCplt + 11656 .LVL802: +4842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11657 .loc 1 4842 11 view .LVU4110 + 11658 0166 75E7 b .L715 + 11659 .LVL803: + 11660 .L723: +4850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11661 .loc 1 4850 7 is_stmt 1 view .LVU4111 + 11662 0168 4021 movs r1, #64 + 11663 .LVL804: +4850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11664 .loc 1 4850 7 is_stmt 0 view .LVU4112 + 11665 016a 2046 mov r0, r4 + 11666 .LVL805: +4850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11667 .loc 1 4850 7 view .LVU4113 + 11668 016c FFF7FEFF bl I2C_ITError + 11669 .LVL806: +4850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11670 .loc 1 4850 7 view .LVU4114 + 11671 0170 70E7 b .L715 + 11672 .LVL807: + ARM GAS /tmp/ccE2rRGE.s page 393 + + + 11673 .L732: +4862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11674 .loc 1 4862 5 is_stmt 1 view .LVU4115 + 11675 0172 2946 mov r1, r5 + 11676 0174 2046 mov r0, r4 + 11677 0176 FFF7FEFF bl I2C_ITMasterCplt + 11678 .LVL808: + 11679 017a 72E7 b .L725 + 11680 .LVL809: + 11681 .L726: + 11682 .cfi_def_cfa_offset 0 + 11683 .cfi_restore 4 + 11684 .cfi_restore 5 + 11685 .cfi_restore 6 + 11686 .cfi_restore 14 +4740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11687 .loc 1 4740 3 is_stmt 0 view .LVU4116 + 11688 017c 0220 movs r0, #2 + 11689 .LVL810: +4869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11690 .loc 1 4869 1 view .LVU4117 + 11691 017e 7047 bx lr + 11692 .cfi_endproc + 11693 .LFE179: + 11695 .section .text.I2C_Slave_ISR_DMA,"ax",%progbits + 11696 .align 1 + 11697 .syntax unified + 11698 .thumb + 11699 .thumb_func + 11701 I2C_Slave_ISR_DMA: + 11702 .LVL811: + 11703 .LFB182: +5162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11704 .loc 1 5162 1 is_stmt 1 view -0 + 11705 .cfi_startproc + 11706 @ args = 0, pretend = 0, frame = 0 + 11707 @ frame_needed = 0, uses_anonymous_args = 0 +5162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11708 .loc 1 5162 1 is_stmt 0 view .LVU4119 + 11709 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 11710 .cfi_def_cfa_offset 24 + 11711 .cfi_offset 3, -24 + 11712 .cfi_offset 4, -20 + 11713 .cfi_offset 5, -16 + 11714 .cfi_offset 6, -12 + 11715 .cfi_offset 7, -8 + 11716 .cfi_offset 14, -4 +5163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 11717 .loc 1 5163 3 is_stmt 1 view .LVU4120 +5163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 11718 .loc 1 5163 12 is_stmt 0 view .LVU4121 + 11719 0002 C76A ldr r7, [r0, #44] + 11720 .LVL812: +5164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 11721 .loc 1 5164 3 is_stmt 1 view .LVU4122 +5165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11722 .loc 1 5165 3 view .LVU4123 + ARM GAS /tmp/ccE2rRGE.s page 394 + + +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11723 .loc 1 5168 3 view .LVU4124 +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11724 .loc 1 5168 3 view .LVU4125 + 11725 0004 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 11726 0008 012B cmp r3, #1 + 11727 000a 00F08780 beq .L751 + 11728 000e 0446 mov r4, r0 + 11729 0010 0D46 mov r5, r1 + 11730 0012 1646 mov r6, r2 +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11731 .loc 1 5168 3 discriminator 2 view .LVU4126 + 11732 0014 0123 movs r3, #1 + 11733 0016 80F84030 strb r3, [r0, #64] +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11734 .loc 1 5168 3 discriminator 2 view .LVU4127 +5171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11735 .loc 1 5171 3 discriminator 2 view .LVU4128 +5171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11736 .loc 1 5171 6 is_stmt 0 discriminator 2 view .LVU4129 + 11737 001a 11F0200F tst r1, #32 + 11738 001e 02D0 beq .L736 +5171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11739 .loc 1 5171 58 discriminator 1 view .LVU4130 + 11740 0020 12F0200F tst r2, #32 + 11741 0024 12D1 bne .L756 + 11742 .LVL813: + 11743 .L736: +5178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11744 .loc 1 5178 3 is_stmt 1 view .LVU4131 +5178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11745 .loc 1 5178 6 is_stmt 0 view .LVU4132 + 11746 0026 15F0100F tst r5, #16 + 11747 002a 68D0 beq .L737 +5178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11748 .loc 1 5178 55 discriminator 1 view .LVU4133 + 11749 002c 16F0100F tst r6, #16 + 11750 0030 65D0 beq .L737 +5185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 11751 .loc 1 5185 5 is_stmt 1 view .LVU4134 +5185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 11752 .loc 1 5185 8 is_stmt 0 view .LVU4135 + 11753 0032 16F4404F tst r6, #49152 + 11754 0036 5ED0 beq .L738 +5189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11755 .loc 1 5189 7 is_stmt 1 view .LVU4136 +5189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11756 .loc 1 5189 15 is_stmt 0 view .LVU4137 + 11757 0038 E36B ldr r3, [r4, #60] +5189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11758 .loc 1 5189 10 view .LVU4138 + 11759 003a 53B1 cbz r3, .L752 +5191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11760 .loc 1 5191 9 is_stmt 1 view .LVU4139 +5191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11761 .loc 1 5191 12 is_stmt 0 view .LVU4140 + 11762 003c 16F40042 ands r2, r6, #32768 + ARM GAS /tmp/ccE2rRGE.s page 395 + + + 11763 0040 08D0 beq .L739 +5193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11764 .loc 1 5193 11 is_stmt 1 view .LVU4141 +5193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11765 .loc 1 5193 15 is_stmt 0 view .LVU4142 + 11766 0042 1B68 ldr r3, [r3] + 11767 0044 5B68 ldr r3, [r3, #4] +5193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11768 .loc 1 5193 14 view .LVU4143 + 11769 0046 3BB3 cbz r3, .L753 +5164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 11770 .loc 1 5164 12 view .LVU4144 + 11771 0048 0022 movs r2, #0 + 11772 004a 03E0 b .L739 + 11773 .LVL814: + 11774 .L756: +5175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11775 .loc 1 5175 5 is_stmt 1 view .LVU4145 + 11776 004c FFF7FEFF bl I2C_ITSlaveCplt + 11777 .LVL815: +5175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11778 .loc 1 5175 5 is_stmt 0 view .LVU4146 + 11779 0050 E9E7 b .L736 + 11780 .L752: +5164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 11781 .loc 1 5164 12 view .LVU4147 + 11782 0052 0022 movs r2, #0 + 11783 .L739: + 11784 .LVL816: +5201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11785 .loc 1 5201 7 is_stmt 1 view .LVU4148 +5201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11786 .loc 1 5201 15 is_stmt 0 view .LVU4149 + 11787 0054 A36B ldr r3, [r4, #56] +5201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11788 .loc 1 5201 10 view .LVU4150 + 11789 0056 2BB1 cbz r3, .L740 +5203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11790 .loc 1 5203 9 is_stmt 1 view .LVU4151 +5203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11791 .loc 1 5203 12 is_stmt 0 view .LVU4152 + 11792 0058 16F4804F tst r6, #16384 + 11793 005c 02D0 beq .L740 +5205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11794 .loc 1 5205 11 is_stmt 1 view .LVU4153 +5205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11795 .loc 1 5205 15 is_stmt 0 view .LVU4154 + 11796 005e 1B68 ldr r3, [r3] + 11797 0060 5B68 ldr r3, [r3, #4] +5205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11798 .loc 1 5205 14 view .LVU4155 + 11799 0062 DBB1 cbz r3, .L741 + 11800 .L740: +5212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11801 .loc 1 5212 7 is_stmt 1 view .LVU4156 +5212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11802 .loc 1 5212 10 is_stmt 0 view .LVU4157 + ARM GAS /tmp/ccE2rRGE.s page 396 + + + 11803 0064 012A cmp r2, #1 + 11804 0066 19D0 beq .L741 +5243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11805 .loc 1 5243 9 is_stmt 1 view .LVU4158 + 11806 0068 2368 ldr r3, [r4] + 11807 006a 1022 movs r2, #16 + 11808 .LVL817: +5243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11809 .loc 1 5243 9 is_stmt 0 view .LVU4159 + 11810 006c DA61 str r2, [r3, #28] +5246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11811 .loc 1 5246 9 is_stmt 1 view .LVU4160 +5246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11812 .loc 1 5246 13 is_stmt 0 view .LVU4161 + 11813 006e 636C ldr r3, [r4, #68] +5246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11814 .loc 1 5246 25 view .LVU4162 + 11815 0070 43F00403 orr r3, r3, #4 + 11816 0074 6364 str r3, [r4, #68] +5249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11817 .loc 1 5249 9 is_stmt 1 view .LVU4163 +5249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11818 .loc 1 5249 18 is_stmt 0 view .LVU4164 + 11819 0076 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11820 007a DBB2 uxtb r3, r3 + 11821 .LVL818: +5251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11822 .loc 1 5251 9 is_stmt 1 view .LVU4165 +5251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11823 .loc 1 5251 12 is_stmt 0 view .LVU4166 + 11824 007c 17B1 cbz r7, .L746 +5251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11825 .loc 1 5251 45 discriminator 1 view .LVU4167 + 11826 007e B7F1807F cmp r7, #16777216 + 11827 0082 42D1 bne .L744 + 11828 .L746: +5253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11829 .loc 1 5253 11 is_stmt 1 view .LVU4168 + 11830 0084 213B subs r3, r3, #33 + 11831 .LVL819: +5253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11832 .loc 1 5253 11 is_stmt 0 view .LVU4169 + 11833 0086 092B cmp r3, #9 + 11834 0088 2DD8 bhi .L747 + 11835 008a DFE803F0 tbb [pc, r3] + 11836 .L749: + 11837 008e 2A .byte (.L750-.L749)/2 + 11838 008f 31 .byte (.L748-.L749)/2 + 11839 0090 2C .byte (.L747-.L749)/2 + 11840 0091 2C .byte (.L747-.L749)/2 + 11841 0092 2C .byte (.L747-.L749)/2 + 11842 0093 2C .byte (.L747-.L749)/2 + 11843 0094 2C .byte (.L747-.L749)/2 + 11844 0095 2C .byte (.L747-.L749)/2 + 11845 0096 2A .byte (.L750-.L749)/2 + 11846 0097 31 .byte (.L748-.L749)/2 + 11847 .LVL820: + ARM GAS /tmp/ccE2rRGE.s page 397 + + + 11848 .p2align 1 + 11849 .L753: +5195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11850 .loc 1 5195 26 view .LVU4170 + 11851 0098 0122 movs r2, #1 + 11852 009a DBE7 b .L739 + 11853 .LVL821: + 11854 .L741: +5214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11855 .loc 1 5214 9 is_stmt 1 view .LVU4171 +5214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11856 .loc 1 5214 18 is_stmt 0 view .LVU4172 + 11857 009c 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11858 00a0 DBB2 uxtb r3, r3 +5214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11859 .loc 1 5214 12 view .LVU4173 + 11860 00a2 282B cmp r3, #40 + 11861 00a4 08D0 beq .L757 + 11862 .L743: +5221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11863 .loc 1 5221 14 is_stmt 1 view .LVU4174 +5221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11864 .loc 1 5221 23 is_stmt 0 view .LVU4175 + 11865 00a6 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 11866 00aa DBB2 uxtb r3, r3 +5221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11867 .loc 1 5221 17 view .LVU4176 + 11868 00ac 292B cmp r3, #41 + 11869 00ae 0BD0 beq .L758 + 11870 .L745: +5236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11871 .loc 1 5236 11 is_stmt 1 view .LVU4177 + 11872 00b0 2368 ldr r3, [r4] + 11873 00b2 1022 movs r2, #16 + 11874 00b4 DA61 str r2, [r3, #28] + 11875 00b6 28E0 b .L744 + 11876 .L757: +5214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11877 .loc 1 5214 51 is_stmt 0 discriminator 1 view .LVU4178 + 11878 00b8 B7F1007F cmp r7, #33554432 + 11879 00bc F3D1 bne .L743 +5219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11880 .loc 1 5219 11 is_stmt 1 view .LVU4179 + 11881 00be 2946 mov r1, r5 + 11882 00c0 2046 mov r0, r4 + 11883 00c2 FFF7FEFF bl I2C_ITListenCplt + 11884 .LVL822: + 11885 00c6 20E0 b .L744 + 11886 .L758: +5221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11887 .loc 1 5221 64 is_stmt 0 discriminator 1 view .LVU4180 + 11888 00c8 17F5803F cmn r7, #65536 + 11889 00cc F0D0 beq .L745 +5224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11890 .loc 1 5224 11 is_stmt 1 view .LVU4181 + 11891 00ce 2368 ldr r3, [r4] + 11892 00d0 1022 movs r2, #16 + ARM GAS /tmp/ccE2rRGE.s page 398 + + + 11893 00d2 DA61 str r2, [r3, #28] +5227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11894 .loc 1 5227 11 view .LVU4182 + 11895 00d4 2046 mov r0, r4 + 11896 00d6 FFF7FEFF bl I2C_Flush_TXDR + 11897 .LVL823: +5231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11898 .loc 1 5231 11 view .LVU4183 + 11899 00da 2046 mov r0, r4 + 11900 00dc FFF7FEFF bl I2C_ITSlaveSeqCplt + 11901 .LVL824: + 11902 00e0 13E0 b .L744 + 11903 .LVL825: + 11904 .L750: +5255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11905 .loc 1 5255 13 view .LVU4184 +5255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11906 .loc 1 5255 33 is_stmt 0 view .LVU4185 + 11907 00e2 2123 movs r3, #33 + 11908 .LVL826: +5255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11909 .loc 1 5255 33 view .LVU4186 + 11910 00e4 2363 str r3, [r4, #48] + 11911 .L747: +5267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11912 .loc 1 5267 11 is_stmt 1 view .LVU4187 +5267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11913 .loc 1 5267 33 is_stmt 0 view .LVU4188 + 11914 00e6 616C ldr r1, [r4, #68] +5267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11915 .loc 1 5267 11 view .LVU4189 + 11916 00e8 2046 mov r0, r4 + 11917 00ea FFF7FEFF bl I2C_ITError + 11918 .LVL827: + 11919 00ee 0CE0 b .L744 + 11920 .LVL828: + 11921 .L748: +5259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11922 .loc 1 5259 13 is_stmt 1 view .LVU4190 +5259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11923 .loc 1 5259 33 is_stmt 0 view .LVU4191 + 11924 00f0 2223 movs r3, #34 + 11925 .LVL829: +5259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11926 .loc 1 5259 33 view .LVU4192 + 11927 00f2 2363 str r3, [r4, #48] + 11928 00f4 F7E7 b .L747 + 11929 .LVL830: + 11930 .L738: +5274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11931 .loc 1 5274 7 is_stmt 1 view .LVU4193 + 11932 00f6 2368 ldr r3, [r4] + 11933 00f8 1022 movs r2, #16 + 11934 00fa DA61 str r2, [r3, #28] + 11935 00fc 05E0 b .L744 + 11936 .L737: +5277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + ARM GAS /tmp/ccE2rRGE.s page 399 + + + 11937 .loc 1 5277 8 view .LVU4194 +5277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 11938 .loc 1 5277 11 is_stmt 0 view .LVU4195 + 11939 00fe 15F0080F tst r5, #8 + 11940 0102 02D0 beq .L744 +5277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 11941 .loc 1 5277 62 discriminator 1 view .LVU4196 + 11942 0104 16F0080F tst r6, #8 + 11943 0108 03D1 bne .L759 + 11944 .LVL831: + 11945 .L744: +5285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11946 .loc 1 5285 3 is_stmt 1 view .LVU4197 +5288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11947 .loc 1 5288 3 view .LVU4198 +5288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11948 .loc 1 5288 3 view .LVU4199 + 11949 010a 0020 movs r0, #0 + 11950 010c 84F84000 strb r0, [r4, #64] +5288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11951 .loc 1 5288 3 view .LVU4200 +5290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11952 .loc 1 5290 3 view .LVU4201 + 11953 .LVL832: + 11954 .L735: +5291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11955 .loc 1 5291 1 is_stmt 0 view .LVU4202 + 11956 0110 F8BD pop {r3, r4, r5, r6, r7, pc} + 11957 .LVL833: + 11958 .L759: +5280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11959 .loc 1 5280 5 is_stmt 1 view .LVU4203 + 11960 0112 2946 mov r1, r5 + 11961 0114 2046 mov r0, r4 + 11962 0116 FFF7FEFF bl I2C_ITAddrCplt + 11963 .LVL834: + 11964 011a F6E7 b .L744 + 11965 .LVL835: + 11966 .L751: +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11967 .loc 1 5168 3 is_stmt 0 view .LVU4204 + 11968 011c 0220 movs r0, #2 + 11969 .LVL836: +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11970 .loc 1 5168 3 view .LVU4205 + 11971 011e F7E7 b .L735 + 11972 .cfi_endproc + 11973 .LFE182: + 11975 .section .text.I2C_Master_ISR_DMA,"ax",%progbits + 11976 .align 1 + 11977 .syntax unified + 11978 .thumb + 11979 .thumb_func + 11981 I2C_Master_ISR_DMA: + 11982 .LVL837: + 11983 .LFB181: +5022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t devaddress; + ARM GAS /tmp/ccE2rRGE.s page 400 + + + 11984 .loc 1 5022 1 is_stmt 1 view -0 + 11985 .cfi_startproc + 11986 @ args = 0, pretend = 0, frame = 0 + 11987 @ frame_needed = 0, uses_anonymous_args = 0 +5023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; + 11988 .loc 1 5023 3 view .LVU4207 +5024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11989 .loc 1 5024 3 view .LVU4208 +5027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11990 .loc 1 5027 3 view .LVU4209 +5027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11991 .loc 1 5027 3 view .LVU4210 + 11992 0000 90F84030 ldrb r3, [r0, #64] @ zero_extendqisi2 + 11993 0004 012B cmp r3, #1 + 11994 0006 00F09A80 beq .L773 +5022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t devaddress; + 11995 .loc 1 5022 1 is_stmt 0 discriminator 2 view .LVU4211 + 11996 000a 10B5 push {r4, lr} + 11997 .cfi_def_cfa_offset 8 + 11998 .cfi_offset 4, -8 + 11999 .cfi_offset 14, -4 + 12000 000c 82B0 sub sp, sp, #8 + 12001 .cfi_def_cfa_offset 16 + 12002 000e 0446 mov r4, r0 +5027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12003 .loc 1 5027 3 is_stmt 1 discriminator 2 view .LVU4212 + 12004 0010 0123 movs r3, #1 + 12005 0012 80F84030 strb r3, [r0, #64] +5027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12006 .loc 1 5027 3 discriminator 2 view .LVU4213 +5029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12007 .loc 1 5029 3 discriminator 2 view .LVU4214 +5029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12008 .loc 1 5029 6 is_stmt 0 discriminator 2 view .LVU4215 + 12009 0016 11F0100F tst r1, #16 + 12010 001a 02D0 beq .L762 +5029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12011 .loc 1 5029 55 discriminator 1 view .LVU4216 + 12012 001c 12F0100F tst r2, #16 + 12013 0020 32D1 bne .L779 + 12014 .L762: +5046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12015 .loc 1 5046 8 is_stmt 1 view .LVU4217 +5046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12016 .loc 1 5046 11 is_stmt 0 view .LVU4218 + 12017 0022 11F0800F tst r1, #128 + 12018 0026 60D0 beq .L764 +5046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12019 .loc 1 5046 61 discriminator 1 view .LVU4219 + 12020 0028 12F0400F tst r2, #64 + 12021 002c 5DD0 beq .L764 +5050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12022 .loc 1 5050 5 is_stmt 1 view .LVU4220 + 12023 002e 2268 ldr r2, [r4] + 12024 .LVL838: +5050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12025 .loc 1 5050 5 is_stmt 0 view .LVU4221 + ARM GAS /tmp/ccE2rRGE.s page 401 + + + 12026 0030 1368 ldr r3, [r2] + 12027 0032 23F04003 bic r3, r3, #64 + 12028 0036 1360 str r3, [r2] +5052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12029 .loc 1 5052 5 is_stmt 1 view .LVU4222 +5052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12030 .loc 1 5052 13 is_stmt 0 view .LVU4223 + 12031 0038 638D ldrh r3, [r4, #42] + 12032 003a 9BB2 uxth r3, r3 +5052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12033 .loc 1 5052 8 view .LVU4224 + 12034 003c 002B cmp r3, #0 + 12035 003e 46D0 beq .L765 +5055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12036 .loc 1 5055 7 is_stmt 1 view .LVU4225 +5055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12037 .loc 1 5055 35 is_stmt 0 view .LVU4226 + 12038 0040 2368 ldr r3, [r4] +5055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12039 .loc 1 5055 45 view .LVU4227 + 12040 0042 5968 ldr r1, [r3, #4] + 12041 .LVL839: +5055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12042 .loc 1 5055 18 view .LVU4228 + 12043 0044 C1F30901 ubfx r1, r1, #0, #10 + 12044 .LVL840: +5058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12045 .loc 1 5058 7 is_stmt 1 view .LVU4229 +5058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12046 .loc 1 5058 15 is_stmt 0 view .LVU4230 + 12047 0048 638D ldrh r3, [r4, #42] + 12048 004a 9BB2 uxth r3, r3 +5058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12049 .loc 1 5058 10 view .LVU4231 + 12050 004c FF2B cmp r3, #255 + 12051 004e 2DD9 bls .L766 +5060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 12052 .loc 1 5060 9 is_stmt 1 view .LVU4232 +5060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 12053 .loc 1 5060 24 is_stmt 0 view .LVU4233 + 12054 0050 FF23 movs r3, #255 + 12055 0052 2385 strh r3, [r4, #40] @ movhi +5061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12056 .loc 1 5061 9 is_stmt 1 view .LVU4234 + 12057 .LVL841: +5061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12058 .loc 1 5061 18 is_stmt 0 view .LVU4235 + 12059 0054 4FF08073 mov r3, #16777216 + 12060 .LVL842: + 12061 .L767: +5077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12062 .loc 1 5077 7 is_stmt 1 view .LVU4236 + 12063 0058 0022 movs r2, #0 + 12064 005a 0092 str r2, [sp] + 12065 005c 94F82820 ldrb r2, [r4, #40] @ zero_extendqisi2 + 12066 0060 2046 mov r0, r4 + 12067 .LVL843: + ARM GAS /tmp/ccE2rRGE.s page 402 + + +5077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12068 .loc 1 5077 7 is_stmt 0 view .LVU4237 + 12069 0062 FFF7FEFF bl I2C_TransferConfig + 12070 .LVL844: +5080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12071 .loc 1 5080 7 is_stmt 1 view .LVU4238 +5080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12072 .loc 1 5080 11 is_stmt 0 view .LVU4239 + 12073 0066 638D ldrh r3, [r4, #42] + 12074 0068 9BB2 uxth r3, r3 +5080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12075 .loc 1 5080 30 view .LVU4240 + 12076 006a 228D ldrh r2, [r4, #40] +5080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12077 .loc 1 5080 23 view .LVU4241 + 12078 006c 9B1A subs r3, r3, r2 + 12079 006e 9BB2 uxth r3, r3 + 12080 0070 6385 strh r3, [r4, #42] @ movhi +5083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12081 .loc 1 5083 7 is_stmt 1 view .LVU4242 +5083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12082 .loc 1 5083 15 is_stmt 0 view .LVU4243 + 12083 0072 94F84130 ldrb r3, [r4, #65] @ zero_extendqisi2 + 12084 0076 DBB2 uxtb r3, r3 +5083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12085 .loc 1 5083 10 view .LVU4244 + 12086 0078 222B cmp r3, #34 + 12087 007a 22D0 beq .L780 +5089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12088 .loc 1 5089 9 is_stmt 1 view .LVU4245 +5089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12089 .loc 1 5089 13 is_stmt 0 view .LVU4246 + 12090 007c 2268 ldr r2, [r4] +5089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12091 .loc 1 5089 23 view .LVU4247 + 12092 007e 1368 ldr r3, [r2] +5089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12093 .loc 1 5089 29 view .LVU4248 + 12094 0080 43F48043 orr r3, r3, #16384 + 12095 0084 1360 str r3, [r2] + 12096 0086 0CE0 b .L763 + 12097 .LVL845: + 12098 .L779: +5033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12099 .loc 1 5033 5 is_stmt 1 view .LVU4249 + 12100 0088 0368 ldr r3, [r0] + 12101 008a 1022 movs r2, #16 + 12102 .LVL846: +5033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12103 .loc 1 5033 5 is_stmt 0 view .LVU4250 + 12104 008c DA61 str r2, [r3, #28] +5036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12105 .loc 1 5036 5 is_stmt 1 view .LVU4251 +5036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12106 .loc 1 5036 9 is_stmt 0 view .LVU4252 + 12107 008e 436C ldr r3, [r0, #68] +5036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/ccE2rRGE.s page 403 + + + 12108 .loc 1 5036 21 view .LVU4253 + 12109 0090 43F00403 orr r3, r3, #4 + 12110 0094 4364 str r3, [r0, #68] +5041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12111 .loc 1 5041 5 is_stmt 1 view .LVU4254 + 12112 0096 2021 movs r1, #32 + 12113 .LVL847: +5041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12114 .loc 1 5041 5 is_stmt 0 view .LVU4255 + 12115 0098 FFF7FEFF bl I2C_Enable_IRQ + 12116 .LVL848: +5044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12117 .loc 1 5044 5 is_stmt 1 view .LVU4256 + 12118 009c 2046 mov r0, r4 + 12119 009e FFF7FEFF bl I2C_Flush_TXDR + 12120 .LVL849: + 12121 .L763: +5144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12122 .loc 1 5144 3 view .LVU4257 +5147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12123 .loc 1 5147 3 view .LVU4258 +5147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12124 .loc 1 5147 3 view .LVU4259 + 12125 00a2 0020 movs r0, #0 + 12126 00a4 84F84000 strb r0, [r4, #64] +5147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12127 .loc 1 5147 3 view .LVU4260 +5149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12128 .loc 1 5149 3 view .LVU4261 +5150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12129 .loc 1 5150 1 is_stmt 0 view .LVU4262 + 12130 00a8 02B0 add sp, sp, #8 + 12131 .cfi_remember_state + 12132 .cfi_def_cfa_offset 8 + 12133 @ sp needed + 12134 00aa 10BD pop {r4, pc} + 12135 .LVL850: + 12136 .L766: + 12137 .cfi_restore_state +5065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12138 .loc 1 5065 9 is_stmt 1 view .LVU4263 +5065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12139 .loc 1 5065 30 is_stmt 0 view .LVU4264 + 12140 00ac 638D ldrh r3, [r4, #42] +5065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12141 .loc 1 5065 24 view .LVU4265 + 12142 00ae 2385 strh r3, [r4, #40] @ movhi +5066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12143 .loc 1 5066 9 is_stmt 1 view .LVU4266 +5066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12144 .loc 1 5066 17 is_stmt 0 view .LVU4267 + 12145 00b0 E36A ldr r3, [r4, #44] +5066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12146 .loc 1 5066 12 view .LVU4268 + 12147 00b2 13F5803F cmn r3, #65536 + 12148 00b6 01D0 beq .L774 +5068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 404 + + + 12149 .loc 1 5068 11 is_stmt 1 view .LVU4269 +5068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12150 .loc 1 5068 20 is_stmt 0 view .LVU4270 + 12151 00b8 E36A ldr r3, [r4, #44] + 12152 .LVL851: +5068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12153 .loc 1 5068 20 view .LVU4271 + 12154 00ba CDE7 b .L767 + 12155 .LVL852: + 12156 .L774: +5072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12157 .loc 1 5072 20 view .LVU4272 + 12158 00bc 4FF00073 mov r3, #33554432 + 12159 00c0 CAE7 b .L767 + 12160 .LVL853: + 12161 .L780: +5085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12162 .loc 1 5085 9 is_stmt 1 view .LVU4273 +5085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12163 .loc 1 5085 13 is_stmt 0 view .LVU4274 + 12164 00c2 2268 ldr r2, [r4] +5085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12165 .loc 1 5085 23 view .LVU4275 + 12166 00c4 1368 ldr r3, [r2] +5085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12167 .loc 1 5085 29 view .LVU4276 + 12168 00c6 43F40043 orr r3, r3, #32768 + 12169 00ca 1360 str r3, [r2] + 12170 00cc E9E7 b .L763 + 12171 .LVL854: + 12172 .L765: +5095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12173 .loc 1 5095 7 is_stmt 1 view .LVU4277 +5095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12174 .loc 1 5095 11 is_stmt 0 view .LVU4278 + 12175 00ce 2368 ldr r3, [r4] + 12176 00d0 5B68 ldr r3, [r3, #4] +5095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12177 .loc 1 5095 10 view .LVU4279 + 12178 00d2 13F0007F tst r3, #33554432 + 12179 00d6 03D1 bne .L769 +5098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12180 .loc 1 5098 9 is_stmt 1 view .LVU4280 + 12181 00d8 2046 mov r0, r4 + 12182 .LVL855: +5098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12183 .loc 1 5098 9 is_stmt 0 view .LVU4281 + 12184 00da FFF7FEFF bl I2C_ITMasterSeqCplt + 12185 .LVL856: +5098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12186 .loc 1 5098 9 view .LVU4282 + 12187 00de E0E7 b .L763 + 12188 .LVL857: + 12189 .L769: +5104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12190 .loc 1 5104 9 is_stmt 1 view .LVU4283 + 12191 00e0 4021 movs r1, #64 + ARM GAS /tmp/ccE2rRGE.s page 405 + + + 12192 .LVL858: +5104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12193 .loc 1 5104 9 is_stmt 0 view .LVU4284 + 12194 00e2 2046 mov r0, r4 + 12195 .LVL859: +5104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12196 .loc 1 5104 9 view .LVU4285 + 12197 00e4 FFF7FEFF bl I2C_ITError + 12198 .LVL860: + 12199 00e8 DBE7 b .L763 + 12200 .LVL861: + 12201 .L764: +5108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12202 .loc 1 5108 8 is_stmt 1 view .LVU4286 +5108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12203 .loc 1 5108 11 is_stmt 0 view .LVU4287 + 12204 00ea 11F0400F tst r1, #64 + 12205 00ee 1CD0 beq .L770 +5108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12206 .loc 1 5108 60 discriminator 1 view .LVU4288 + 12207 00f0 12F0400F tst r2, #64 + 12208 00f4 19D0 beq .L770 +5111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12209 .loc 1 5111 5 is_stmt 1 view .LVU4289 +5111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12210 .loc 1 5111 13 is_stmt 0 view .LVU4290 + 12211 00f6 638D ldrh r3, [r4, #42] + 12212 00f8 9BB2 uxth r3, r3 +5111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12213 .loc 1 5111 8 view .LVU4291 + 12214 00fa 8BB9 cbnz r3, .L771 +5113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12215 .loc 1 5113 7 is_stmt 1 view .LVU4292 +5113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12216 .loc 1 5113 11 is_stmt 0 view .LVU4293 + 12217 00fc 2368 ldr r3, [r4] + 12218 00fe 5A68 ldr r2, [r3, #4] + 12219 .LVL862: +5113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12220 .loc 1 5113 10 view .LVU4294 + 12221 0100 12F0007F tst r2, #33554432 + 12222 0104 CDD1 bne .L763 +5116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12223 .loc 1 5116 9 is_stmt 1 view .LVU4295 +5116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12224 .loc 1 5116 17 is_stmt 0 view .LVU4296 + 12225 0106 E26A ldr r2, [r4, #44] +5116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12226 .loc 1 5116 12 view .LVU4297 + 12227 0108 12F5803F cmn r2, #65536 + 12228 010c 04D1 bne .L772 +5119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12229 .loc 1 5119 11 is_stmt 1 view .LVU4298 +5119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12230 .loc 1 5119 25 is_stmt 0 view .LVU4299 + 12231 010e 5A68 ldr r2, [r3, #4] +5119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 406 + + + 12232 .loc 1 5119 31 view .LVU4300 + 12233 0110 42F48042 orr r2, r2, #16384 + 12234 0114 5A60 str r2, [r3, #4] + 12235 0116 C4E7 b .L763 + 12236 .L772: +5124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12237 .loc 1 5124 11 is_stmt 1 view .LVU4301 + 12238 0118 2046 mov r0, r4 + 12239 .LVL863: +5124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12240 .loc 1 5124 11 is_stmt 0 view .LVU4302 + 12241 011a FFF7FEFF bl I2C_ITMasterSeqCplt + 12242 .LVL864: +5124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12243 .loc 1 5124 11 view .LVU4303 + 12244 011e C0E7 b .L763 + 12245 .LVL865: + 12246 .L771: +5132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12247 .loc 1 5132 7 is_stmt 1 view .LVU4304 + 12248 0120 4021 movs r1, #64 + 12249 .LVL866: +5132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12250 .loc 1 5132 7 is_stmt 0 view .LVU4305 + 12251 0122 2046 mov r0, r4 + 12252 .LVL867: +5132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12253 .loc 1 5132 7 view .LVU4306 + 12254 0124 FFF7FEFF bl I2C_ITError + 12255 .LVL868: +5132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12256 .loc 1 5132 7 view .LVU4307 + 12257 0128 BBE7 b .L763 + 12258 .LVL869: + 12259 .L770: +5135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12260 .loc 1 5135 8 is_stmt 1 view .LVU4308 +5135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12261 .loc 1 5135 11 is_stmt 0 view .LVU4309 + 12262 012a 11F0200F tst r1, #32 + 12263 012e B8D0 beq .L763 +5135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12264 .loc 1 5135 63 discriminator 1 view .LVU4310 + 12265 0130 12F0200F tst r2, #32 + 12266 0134 B5D0 beq .L763 +5139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12267 .loc 1 5139 5 is_stmt 1 view .LVU4311 + 12268 0136 2046 mov r0, r4 + 12269 .LVL870: +5139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12270 .loc 1 5139 5 is_stmt 0 view .LVU4312 + 12271 0138 FFF7FEFF bl I2C_ITMasterCplt + 12272 .LVL871: +5139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12273 .loc 1 5139 5 view .LVU4313 + 12274 013c B1E7 b .L763 + 12275 .LVL872: + ARM GAS /tmp/ccE2rRGE.s page 407 + + + 12276 .L773: + 12277 .cfi_def_cfa_offset 0 + 12278 .cfi_restore 4 + 12279 .cfi_restore 14 +5027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12280 .loc 1 5027 3 view .LVU4314 + 12281 013e 0220 movs r0, #2 + 12282 .LVL873: +5150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12283 .loc 1 5150 1 view .LVU4315 + 12284 0140 7047 bx lr + 12285 .cfi_endproc + 12286 .LFE181: + 12288 .section .text.I2C_DMAError,"ax",%progbits + 12289 .align 1 + 12290 .syntax unified + 12291 .thumb + 12292 .thumb_func + 12294 I2C_DMAError: + 12295 .LVL874: + 12296 .LFB198: +6312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 12297 .loc 1 6312 1 is_stmt 1 view -0 + 12298 .cfi_startproc + 12299 @ args = 0, pretend = 0, frame = 0 + 12300 @ frame_needed = 0, uses_anonymous_args = 0 +6312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 12301 .loc 1 6312 1 is_stmt 0 view .LVU4317 + 12302 0000 08B5 push {r3, lr} + 12303 .cfi_def_cfa_offset 8 + 12304 .cfi_offset 3, -8 + 12305 .cfi_offset 14, -4 +6314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12306 .loc 1 6314 3 is_stmt 1 view .LVU4318 +6314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12307 .loc 1 6314 22 is_stmt 0 view .LVU4319 + 12308 0002 406A ldr r0, [r0, #36] + 12309 .LVL875: +6317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12310 .loc 1 6317 3 is_stmt 1 view .LVU4320 +6317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12311 .loc 1 6317 7 is_stmt 0 view .LVU4321 + 12312 0004 0268 ldr r2, [r0] +6317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12313 .loc 1 6317 17 view .LVU4322 + 12314 0006 5368 ldr r3, [r2, #4] +6317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12315 .loc 1 6317 23 view .LVU4323 + 12316 0008 43F40043 orr r3, r3, #32768 + 12317 000c 5360 str r3, [r2, #4] +6320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12318 .loc 1 6320 3 is_stmt 1 view .LVU4324 + 12319 000e 1021 movs r1, #16 + 12320 0010 FFF7FEFF bl I2C_ITError + 12321 .LVL876: +6321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12322 .loc 1 6321 1 is_stmt 0 view .LVU4325 + ARM GAS /tmp/ccE2rRGE.s page 408 + + + 12323 0014 08BD pop {r3, pc} + 12324 .cfi_endproc + 12325 .LFE198: + 12327 .section .text.I2C_DMAMasterTransmitCplt,"ax",%progbits + 12328 .align 1 + 12329 .syntax unified + 12330 .thumb + 12331 .thumb_func + 12333 I2C_DMAMasterTransmitCplt: + 12334 .LVL877: + 12335 .LFB194: +6156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 12336 .loc 1 6156 1 is_stmt 1 view -0 + 12337 .cfi_startproc + 12338 @ args = 0, pretend = 0, frame = 0 + 12339 @ frame_needed = 0, uses_anonymous_args = 0 +6156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 12340 .loc 1 6156 1 is_stmt 0 view .LVU4327 + 12341 0000 10B5 push {r4, lr} + 12342 .cfi_def_cfa_offset 8 + 12343 .cfi_offset 4, -8 + 12344 .cfi_offset 14, -4 +6158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12345 .loc 1 6158 3 is_stmt 1 view .LVU4328 +6158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12346 .loc 1 6158 22 is_stmt 0 view .LVU4329 + 12347 0002 446A ldr r4, [r0, #36] + 12348 .LVL878: +6161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12349 .loc 1 6161 3 is_stmt 1 view .LVU4330 +6161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12350 .loc 1 6161 7 is_stmt 0 view .LVU4331 + 12351 0004 2268 ldr r2, [r4] +6161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12352 .loc 1 6161 17 view .LVU4332 + 12353 0006 1368 ldr r3, [r2] +6161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12354 .loc 1 6161 23 view .LVU4333 + 12355 0008 23F48043 bic r3, r3, #16384 + 12356 000c 1360 str r3, [r2] +6164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12357 .loc 1 6164 3 is_stmt 1 view .LVU4334 +6164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12358 .loc 1 6164 11 is_stmt 0 view .LVU4335 + 12359 000e 638D ldrh r3, [r4, #42] + 12360 0010 9BB2 uxth r3, r3 +6164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12361 .loc 1 6164 6 view .LVU4336 + 12362 0012 ABB1 cbz r3, .L790 +6173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12363 .loc 1 6173 5 is_stmt 1 view .LVU4337 +6173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12364 .loc 1 6173 9 is_stmt 0 view .LVU4338 + 12365 0014 616A ldr r1, [r4, #36] +6173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12366 .loc 1 6173 27 view .LVU4339 + 12367 0016 238D ldrh r3, [r4, #40] + ARM GAS /tmp/ccE2rRGE.s page 409 + + +6173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12368 .loc 1 6173 20 view .LVU4340 + 12369 0018 1944 add r1, r1, r3 + 12370 001a 6162 str r1, [r4, #36] +6176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12371 .loc 1 6176 5 is_stmt 1 view .LVU4341 +6176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12372 .loc 1 6176 13 is_stmt 0 view .LVU4342 + 12373 001c 638D ldrh r3, [r4, #42] + 12374 001e 9BB2 uxth r3, r3 +6176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12375 .loc 1 6176 8 view .LVU4343 + 12376 0020 FF2B cmp r3, #255 + 12377 0022 12D9 bls .L786 +6178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12378 .loc 1 6178 7 is_stmt 1 view .LVU4344 +6178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12379 .loc 1 6178 22 is_stmt 0 view .LVU4345 + 12380 0024 FF23 movs r3, #255 + 12381 0026 2385 strh r3, [r4, #40] @ movhi + 12382 .L787: +6186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12383 .loc 1 6186 5 is_stmt 1 view .LVU4346 +6186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12384 .loc 1 6186 81 is_stmt 0 view .LVU4347 + 12385 0028 2268 ldr r2, [r4] +6186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12386 .loc 1 6186 9 view .LVU4348 + 12387 002a 238D ldrh r3, [r4, #40] + 12388 002c 2832 adds r2, r2, #40 + 12389 002e A06B ldr r0, [r4, #56] + 12390 .LVL879: +6186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12391 .loc 1 6186 9 view .LVU4349 + 12392 0030 FFF7FEFF bl HAL_DMA_Start_IT + 12393 .LVL880: +6186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12394 .loc 1 6186 8 view .LVU4350 + 12395 0034 60B1 cbz r0, .L788 +6190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12396 .loc 1 6190 7 is_stmt 1 view .LVU4351 + 12397 0036 1021 movs r1, #16 + 12398 0038 2046 mov r0, r4 + 12399 003a FFF7FEFF bl I2C_ITError + 12400 .LVL881: + 12401 .L783: +6198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12402 .loc 1 6198 1 is_stmt 0 view .LVU4352 + 12403 003e 10BD pop {r4, pc} + 12404 .LVL882: + 12405 .L790: +6167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12406 .loc 1 6167 5 is_stmt 1 view .LVU4353 + 12407 0040 2021 movs r1, #32 + 12408 0042 2046 mov r0, r4 + 12409 .LVL883: +6167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/ccE2rRGE.s page 410 + + + 12410 .loc 1 6167 5 is_stmt 0 view .LVU4354 + 12411 0044 FFF7FEFF bl I2C_Enable_IRQ + 12412 .LVL884: + 12413 0048 F9E7 b .L783 + 12414 .LVL885: + 12415 .L786: +6182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12416 .loc 1 6182 7 is_stmt 1 view .LVU4355 +6182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12417 .loc 1 6182 28 is_stmt 0 view .LVU4356 + 12418 004a 638D ldrh r3, [r4, #42] +6182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12419 .loc 1 6182 22 view .LVU4357 + 12420 004c 2385 strh r3, [r4, #40] @ movhi + 12421 004e EBE7 b .L787 + 12422 .LVL886: + 12423 .L788: +6195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12424 .loc 1 6195 7 is_stmt 1 view .LVU4358 + 12425 0050 4021 movs r1, #64 + 12426 0052 2046 mov r0, r4 + 12427 0054 FFF7FEFF bl I2C_Enable_IRQ + 12428 .LVL887: +6198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12429 .loc 1 6198 1 is_stmt 0 view .LVU4359 + 12430 0058 F1E7 b .L783 + 12431 .cfi_endproc + 12432 .LFE194: + 12434 .section .text.I2C_DMAMasterReceiveCplt,"ax",%progbits + 12435 .align 1 + 12436 .syntax unified + 12437 .thumb + 12438 .thumb_func + 12440 I2C_DMAMasterReceiveCplt: + 12441 .LVL888: + 12442 .LFB196: +6234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 12443 .loc 1 6234 1 is_stmt 1 view -0 + 12444 .cfi_startproc + 12445 @ args = 0, pretend = 0, frame = 0 + 12446 @ frame_needed = 0, uses_anonymous_args = 0 +6234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 12447 .loc 1 6234 1 is_stmt 0 view .LVU4361 + 12448 0000 10B5 push {r4, lr} + 12449 .cfi_def_cfa_offset 8 + 12450 .cfi_offset 4, -8 + 12451 .cfi_offset 14, -4 +6236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12452 .loc 1 6236 3 is_stmt 1 view .LVU4362 +6236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12453 .loc 1 6236 22 is_stmt 0 view .LVU4363 + 12454 0002 446A ldr r4, [r0, #36] + 12455 .LVL889: +6239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12456 .loc 1 6239 3 is_stmt 1 view .LVU4364 +6239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12457 .loc 1 6239 7 is_stmt 0 view .LVU4365 + ARM GAS /tmp/ccE2rRGE.s page 411 + + + 12458 0004 2268 ldr r2, [r4] +6239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12459 .loc 1 6239 17 view .LVU4366 + 12460 0006 1368 ldr r3, [r2] +6239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12461 .loc 1 6239 23 view .LVU4367 + 12462 0008 23F40043 bic r3, r3, #32768 + 12463 000c 1360 str r3, [r2] +6242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12464 .loc 1 6242 3 is_stmt 1 view .LVU4368 +6242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12465 .loc 1 6242 11 is_stmt 0 view .LVU4369 + 12466 000e 638D ldrh r3, [r4, #42] + 12467 0010 9BB2 uxth r3, r3 +6242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12468 .loc 1 6242 6 view .LVU4370 + 12469 0012 ABB1 cbz r3, .L798 +6251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12470 .loc 1 6251 5 is_stmt 1 view .LVU4371 +6251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12471 .loc 1 6251 9 is_stmt 0 view .LVU4372 + 12472 0014 626A ldr r2, [r4, #36] +6251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12473 .loc 1 6251 27 view .LVU4373 + 12474 0016 238D ldrh r3, [r4, #40] +6251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12475 .loc 1 6251 20 view .LVU4374 + 12476 0018 1A44 add r2, r2, r3 + 12477 001a 6262 str r2, [r4, #36] +6254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12478 .loc 1 6254 5 is_stmt 1 view .LVU4375 +6254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12479 .loc 1 6254 13 is_stmt 0 view .LVU4376 + 12480 001c 638D ldrh r3, [r4, #42] + 12481 001e 9BB2 uxth r3, r3 +6254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12482 .loc 1 6254 8 view .LVU4377 + 12483 0020 FF2B cmp r3, #255 + 12484 0022 12D9 bls .L794 +6256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12485 .loc 1 6256 7 is_stmt 1 view .LVU4378 +6256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12486 .loc 1 6256 22 is_stmt 0 view .LVU4379 + 12487 0024 FF23 movs r3, #255 + 12488 0026 2385 strh r3, [r4, #40] @ movhi + 12489 .L795: +6264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12490 .loc 1 6264 5 is_stmt 1 view .LVU4380 +6264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12491 .loc 1 6264 55 is_stmt 0 view .LVU4381 + 12492 0028 2168 ldr r1, [r4] +6264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12493 .loc 1 6264 9 view .LVU4382 + 12494 002a 238D ldrh r3, [r4, #40] + 12495 002c 2431 adds r1, r1, #36 + 12496 002e E06B ldr r0, [r4, #60] + 12497 .LVL890: + ARM GAS /tmp/ccE2rRGE.s page 412 + + +6264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12498 .loc 1 6264 9 view .LVU4383 + 12499 0030 FFF7FEFF bl HAL_DMA_Start_IT + 12500 .LVL891: +6264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 12501 .loc 1 6264 8 view .LVU4384 + 12502 0034 60B1 cbz r0, .L796 +6268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12503 .loc 1 6268 7 is_stmt 1 view .LVU4385 + 12504 0036 1021 movs r1, #16 + 12505 0038 2046 mov r0, r4 + 12506 003a FFF7FEFF bl I2C_ITError + 12507 .LVL892: + 12508 .L791: +6276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12509 .loc 1 6276 1 is_stmt 0 view .LVU4386 + 12510 003e 10BD pop {r4, pc} + 12511 .LVL893: + 12512 .L798: +6245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12513 .loc 1 6245 5 is_stmt 1 view .LVU4387 + 12514 0040 2021 movs r1, #32 + 12515 0042 2046 mov r0, r4 + 12516 .LVL894: +6245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12517 .loc 1 6245 5 is_stmt 0 view .LVU4388 + 12518 0044 FFF7FEFF bl I2C_Enable_IRQ + 12519 .LVL895: + 12520 0048 F9E7 b .L791 + 12521 .LVL896: + 12522 .L794: +6260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12523 .loc 1 6260 7 is_stmt 1 view .LVU4389 +6260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12524 .loc 1 6260 28 is_stmt 0 view .LVU4390 + 12525 004a 638D ldrh r3, [r4, #42] +6260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12526 .loc 1 6260 22 view .LVU4391 + 12527 004c 2385 strh r3, [r4, #40] @ movhi + 12528 004e EBE7 b .L795 + 12529 .LVL897: + 12530 .L796: +6273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12531 .loc 1 6273 7 is_stmt 1 view .LVU4392 + 12532 0050 4021 movs r1, #64 + 12533 0052 2046 mov r0, r4 + 12534 0054 FFF7FEFF bl I2C_Enable_IRQ + 12535 .LVL898: +6276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12536 .loc 1 6276 1 is_stmt 0 view .LVU4393 + 12537 0058 F1E7 b .L791 + 12538 .cfi_endproc + 12539 .LFE196: + 12541 .section .text.HAL_I2C_ER_IRQHandler,"ax",%progbits + 12542 .align 1 + 12543 .global HAL_I2C_ER_IRQHandler + 12544 .syntax unified + ARM GAS /tmp/ccE2rRGE.s page 413 + + + 12545 .thumb + 12546 .thumb_func + 12548 HAL_I2C_ER_IRQHandler: + 12549 .LVL899: + 12550 .LFB165: +4452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 12551 .loc 1 4452 1 is_stmt 1 view -0 + 12552 .cfi_startproc + 12553 @ args = 0, pretend = 0, frame = 0 + 12554 @ frame_needed = 0, uses_anonymous_args = 0 +4452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 12555 .loc 1 4452 1 is_stmt 0 view .LVU4395 + 12556 0000 10B5 push {r4, lr} + 12557 .cfi_def_cfa_offset 8 + 12558 .cfi_offset 4, -8 + 12559 .cfi_offset 14, -4 +4453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 12560 .loc 1 4453 3 is_stmt 1 view .LVU4396 +4453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 12561 .loc 1 4453 24 is_stmt 0 view .LVU4397 + 12562 0002 0268 ldr r2, [r0] +4453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 12563 .loc 1 4453 12 view .LVU4398 + 12564 0004 9369 ldr r3, [r2, #24] + 12565 .LVL900: +4454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmperror; + 12566 .loc 1 4454 3 is_stmt 1 view .LVU4399 +4454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmperror; + 12567 .loc 1 4454 12 is_stmt 0 view .LVU4400 + 12568 0006 1168 ldr r1, [r2] + 12569 .LVL901: +4455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12570 .loc 1 4455 3 is_stmt 1 view .LVU4401 +4458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12571 .loc 1 4458 3 view .LVU4402 +4458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12572 .loc 1 4458 6 is_stmt 0 view .LVU4403 + 12573 0008 13F4807F tst r3, #256 + 12574 000c 09D0 beq .L800 +4458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12575 .loc 1 4458 57 discriminator 1 view .LVU4404 + 12576 000e 11F0800F tst r1, #128 + 12577 0012 06D0 beq .L800 +4461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12578 .loc 1 4461 5 is_stmt 1 view .LVU4405 +4461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12579 .loc 1 4461 9 is_stmt 0 view .LVU4406 + 12580 0014 446C ldr r4, [r0, #68] +4461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12581 .loc 1 4461 21 view .LVU4407 + 12582 0016 44F00104 orr r4, r4, #1 + 12583 001a 4464 str r4, [r0, #68] +4464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12584 .loc 1 4464 5 is_stmt 1 view .LVU4408 + 12585 001c 4FF48074 mov r4, #256 + 12586 0020 D461 str r4, [r2, #28] + 12587 .L800: + ARM GAS /tmp/ccE2rRGE.s page 414 + + +4468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12588 .loc 1 4468 3 view .LVU4409 +4468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12589 .loc 1 4468 6 is_stmt 0 view .LVU4410 + 12590 0022 13F4806F tst r3, #1024 + 12591 0026 0AD0 beq .L801 +4468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12592 .loc 1 4468 56 discriminator 1 view .LVU4411 + 12593 0028 11F0800F tst r1, #128 + 12594 002c 07D0 beq .L801 +4471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12595 .loc 1 4471 5 is_stmt 1 view .LVU4412 +4471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12596 .loc 1 4471 9 is_stmt 0 view .LVU4413 + 12597 002e 426C ldr r2, [r0, #68] +4471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12598 .loc 1 4471 21 view .LVU4414 + 12599 0030 42F00802 orr r2, r2, #8 + 12600 0034 4264 str r2, [r0, #68] +4474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12601 .loc 1 4474 5 is_stmt 1 view .LVU4415 + 12602 0036 0268 ldr r2, [r0] + 12603 0038 4FF48064 mov r4, #1024 + 12604 003c D461 str r4, [r2, #28] + 12605 .L801: +4478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12606 .loc 1 4478 3 view .LVU4416 +4478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12607 .loc 1 4478 6 is_stmt 0 view .LVU4417 + 12608 003e 13F4007F tst r3, #512 + 12609 0042 0AD0 beq .L802 +4478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 12610 .loc 1 4478 57 discriminator 1 view .LVU4418 + 12611 0044 11F0800F tst r1, #128 + 12612 0048 07D0 beq .L802 +4481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12613 .loc 1 4481 5 is_stmt 1 view .LVU4419 +4481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12614 .loc 1 4481 9 is_stmt 0 view .LVU4420 + 12615 004a 436C ldr r3, [r0, #68] + 12616 .LVL902: +4481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12617 .loc 1 4481 21 view .LVU4421 + 12618 004c 43F00203 orr r3, r3, #2 + 12619 0050 4364 str r3, [r0, #68] +4484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12620 .loc 1 4484 5 is_stmt 1 view .LVU4422 + 12621 0052 0368 ldr r3, [r0] + 12622 0054 4FF40072 mov r2, #512 + 12623 0058 DA61 str r2, [r3, #28] + 12624 .L802: +4488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12625 .loc 1 4488 3 view .LVU4423 +4488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12626 .loc 1 4488 12 is_stmt 0 view .LVU4424 + 12627 005a 416C ldr r1, [r0, #68] + 12628 .LVL903: + ARM GAS /tmp/ccE2rRGE.s page 415 + + +4491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12629 .loc 1 4491 3 is_stmt 1 view .LVU4425 +4491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12630 .loc 1 4491 6 is_stmt 0 view .LVU4426 + 12631 005c 11F00B0F tst r1, #11 + 12632 0060 00D1 bne .L805 + 12633 .LVL904: + 12634 .L799: +4495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12635 .loc 1 4495 1 view .LVU4427 + 12636 0062 10BD pop {r4, pc} + 12637 .LVL905: + 12638 .L805: +4493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12639 .loc 1 4493 5 is_stmt 1 view .LVU4428 + 12640 0064 FFF7FEFF bl I2C_ITError + 12641 .LVL906: +4495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12642 .loc 1 4495 1 is_stmt 0 view .LVU4429 + 12643 0068 FBE7 b .L799 + 12644 .cfi_endproc + 12645 .LFE165: + 12647 .section .text.I2C_DMAAbort,"ax",%progbits + 12648 .align 1 + 12649 .syntax unified + 12650 .thumb + 12651 .thumb_func + 12653 I2C_DMAAbort: + 12654 .LVL907: + 12655 .LFB199: +6330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 12656 .loc 1 6330 1 is_stmt 1 view -0 + 12657 .cfi_startproc + 12658 @ args = 0, pretend = 0, frame = 0 + 12659 @ frame_needed = 0, uses_anonymous_args = 0 +6330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 12660 .loc 1 6330 1 is_stmt 0 view .LVU4431 + 12661 0000 08B5 push {r3, lr} + 12662 .cfi_def_cfa_offset 8 + 12663 .cfi_offset 3, -8 + 12664 .cfi_offset 14, -4 +6332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12665 .loc 1 6332 3 is_stmt 1 view .LVU4432 +6332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12666 .loc 1 6332 22 is_stmt 0 view .LVU4433 + 12667 0002 406A ldr r0, [r0, #36] + 12668 .LVL908: +6335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12669 .loc 1 6335 3 is_stmt 1 view .LVU4434 +6335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12670 .loc 1 6335 11 is_stmt 0 view .LVU4435 + 12671 0004 836B ldr r3, [r0, #56] +6335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12672 .loc 1 6335 6 view .LVU4436 + 12673 0006 0BB1 cbz r3, .L807 +6337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12674 .loc 1 6337 5 is_stmt 1 view .LVU4437 + ARM GAS /tmp/ccE2rRGE.s page 416 + + +6337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12675 .loc 1 6337 37 is_stmt 0 view .LVU4438 + 12676 0008 0022 movs r2, #0 + 12677 000a 5A63 str r2, [r3, #52] + 12678 .L807: +6339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12679 .loc 1 6339 3 is_stmt 1 view .LVU4439 +6339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12680 .loc 1 6339 11 is_stmt 0 view .LVU4440 + 12681 000c C36B ldr r3, [r0, #60] +6339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12682 .loc 1 6339 6 view .LVU4441 + 12683 000e 0BB1 cbz r3, .L808 +6341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12684 .loc 1 6341 5 is_stmt 1 view .LVU4442 +6341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12685 .loc 1 6341 37 is_stmt 0 view .LVU4443 + 12686 0010 0022 movs r2, #0 + 12687 0012 5A63 str r2, [r3, #52] + 12688 .L808: +6344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12689 .loc 1 6344 3 is_stmt 1 view .LVU4444 + 12690 0014 FFF7FEFF bl I2C_TreatErrorCallback + 12691 .LVL909: +6345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12692 .loc 1 6345 1 is_stmt 0 view .LVU4445 + 12693 0018 08BD pop {r3, pc} + 12694 .cfi_endproc + 12695 .LFE199: + 12697 .section .text.HAL_I2C_GetState,"ax",%progbits + 12698 .align 1 + 12699 .global HAL_I2C_GetState + 12700 .syntax unified + 12701 .thumb + 12702 .thumb_func + 12704 HAL_I2C_GetState: + 12705 .LVL910: + 12706 .LFB176: +4686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return I2C handle state */ + 12707 .loc 1 4686 1 is_stmt 1 view -0 + 12708 .cfi_startproc + 12709 @ args = 0, pretend = 0, frame = 0 + 12710 @ frame_needed = 0, uses_anonymous_args = 0 + 12711 @ link register save eliminated. +4688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12712 .loc 1 4688 3 view .LVU4447 +4688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12713 .loc 1 4688 14 is_stmt 0 view .LVU4448 + 12714 0000 90F84100 ldrb r0, [r0, #65] @ zero_extendqisi2 + 12715 .LVL911: +4689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12716 .loc 1 4689 1 view .LVU4449 + 12717 0004 7047 bx lr + 12718 .cfi_endproc + 12719 .LFE176: + 12721 .section .text.HAL_I2C_GetMode,"ax",%progbits + 12722 .align 1 + ARM GAS /tmp/ccE2rRGE.s page 417 + + + 12723 .global HAL_I2C_GetMode + 12724 .syntax unified + 12725 .thumb + 12726 .thumb_func + 12728 HAL_I2C_GetMode: + 12729 .LVL912: + 12730 .LFB177: +4698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return hi2c->Mode; + 12731 .loc 1 4698 1 is_stmt 1 view -0 + 12732 .cfi_startproc + 12733 @ args = 0, pretend = 0, frame = 0 + 12734 @ frame_needed = 0, uses_anonymous_args = 0 + 12735 @ link register save eliminated. +4699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12736 .loc 1 4699 3 view .LVU4451 +4699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12737 .loc 1 4699 14 is_stmt 0 view .LVU4452 + 12738 0000 90F84200 ldrb r0, [r0, #66] @ zero_extendqisi2 + 12739 .LVL913: +4700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12740 .loc 1 4700 1 view .LVU4453 + 12741 0004 7047 bx lr + 12742 .cfi_endproc + 12743 .LFE177: + 12745 .section .text.HAL_I2C_GetError,"ax",%progbits + 12746 .align 1 + 12747 .global HAL_I2C_GetError + 12748 .syntax unified + 12749 .thumb + 12750 .thumb_func + 12752 HAL_I2C_GetError: + 12753 .LVL914: + 12754 .LFB178: +4709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return hi2c->ErrorCode; + 12755 .loc 1 4709 1 is_stmt 1 view -0 + 12756 .cfi_startproc + 12757 @ args = 0, pretend = 0, frame = 0 + 12758 @ frame_needed = 0, uses_anonymous_args = 0 + 12759 @ link register save eliminated. +4710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12760 .loc 1 4710 3 view .LVU4455 +4710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12761 .loc 1 4710 14 is_stmt 0 view .LVU4456 + 12762 0000 406C ldr r0, [r0, #68] + 12763 .LVL915: +4711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12764 .loc 1 4711 1 view .LVU4457 + 12765 0002 7047 bx lr + 12766 .cfi_endproc + 12767 .LFE178: + 12769 .text + 12770 .Letext0: + 12771 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 12772 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 12773 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 12774 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 12775 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + ARM GAS /tmp/ccE2rRGE.s page 418 + + + 12776 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 12777 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + 12778 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccE2rRGE.s page 419 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_i2c.c + /tmp/ccE2rRGE.s:21 .text.I2C_Flush_TXDR:0000000000000000 $t + /tmp/ccE2rRGE.s:26 .text.I2C_Flush_TXDR:0000000000000000 I2C_Flush_TXDR + /tmp/ccE2rRGE.s:64 .text.I2C_TransferConfig:0000000000000000 $t + /tmp/ccE2rRGE.s:69 .text.I2C_TransferConfig:0000000000000000 I2C_TransferConfig + /tmp/ccE2rRGE.s:118 .text.I2C_Enable_IRQ:0000000000000000 $t + /tmp/ccE2rRGE.s:123 .text.I2C_Enable_IRQ:0000000000000000 I2C_Enable_IRQ + /tmp/ccE2rRGE.s:246 .text.I2C_Enable_IRQ:000000000000006c $d + /tmp/ccE2rRGE.s:11981 .text.I2C_Master_ISR_DMA:0000000000000000 I2C_Master_ISR_DMA + /tmp/ccE2rRGE.s:11701 .text.I2C_Slave_ISR_DMA:0000000000000000 I2C_Slave_ISR_DMA + /tmp/ccE2rRGE.s:252 .text.I2C_Disable_IRQ:0000000000000000 $t + /tmp/ccE2rRGE.s:257 .text.I2C_Disable_IRQ:0000000000000000 I2C_Disable_IRQ + /tmp/ccE2rRGE.s:381 .text.I2C_ConvertOtherXferOptions:0000000000000000 $t + /tmp/ccE2rRGE.s:386 .text.I2C_ConvertOtherXferOptions:0000000000000000 I2C_ConvertOtherXferOptions + /tmp/ccE2rRGE.s:427 .text.I2C_IsAcknowledgeFailed:0000000000000000 $t + /tmp/ccE2rRGE.s:432 .text.I2C_IsAcknowledgeFailed:0000000000000000 I2C_IsAcknowledgeFailed + /tmp/ccE2rRGE.s:574 .text.I2C_WaitOnTXISFlagUntilTimeout:0000000000000000 $t + /tmp/ccE2rRGE.s:579 .text.I2C_WaitOnTXISFlagUntilTimeout:0000000000000000 I2C_WaitOnTXISFlagUntilTimeout + /tmp/ccE2rRGE.s:669 .text.I2C_WaitOnFlagUntilTimeout:0000000000000000 $t + /tmp/ccE2rRGE.s:674 .text.I2C_WaitOnFlagUntilTimeout:0000000000000000 I2C_WaitOnFlagUntilTimeout + /tmp/ccE2rRGE.s:759 .text.I2C_RequestMemoryWrite:0000000000000000 $t + /tmp/ccE2rRGE.s:764 .text.I2C_RequestMemoryWrite:0000000000000000 I2C_RequestMemoryWrite + /tmp/ccE2rRGE.s:879 .text.I2C_RequestMemoryWrite:0000000000000078 $d + /tmp/ccE2rRGE.s:884 .text.I2C_RequestMemoryRead:0000000000000000 $t + /tmp/ccE2rRGE.s:889 .text.I2C_RequestMemoryRead:0000000000000000 I2C_RequestMemoryRead + /tmp/ccE2rRGE.s:1004 .text.I2C_RequestMemoryRead:0000000000000074 $d + /tmp/ccE2rRGE.s:1009 .text.I2C_WaitOnSTOPFlagUntilTimeout:0000000000000000 $t + /tmp/ccE2rRGE.s:1014 .text.I2C_WaitOnSTOPFlagUntilTimeout:0000000000000000 I2C_WaitOnSTOPFlagUntilTimeout + /tmp/ccE2rRGE.s:1100 .text.I2C_WaitOnRXNEFlagUntilTimeout:0000000000000000 $t + /tmp/ccE2rRGE.s:1105 .text.I2C_WaitOnRXNEFlagUntilTimeout:0000000000000000 I2C_WaitOnRXNEFlagUntilTimeout + /tmp/ccE2rRGE.s:1240 .text.HAL_I2C_MspInit:0000000000000000 $t + /tmp/ccE2rRGE.s:1246 .text.HAL_I2C_MspInit:0000000000000000 HAL_I2C_MspInit + /tmp/ccE2rRGE.s:1261 .text.HAL_I2C_Init:0000000000000000 $t + /tmp/ccE2rRGE.s:1267 .text.HAL_I2C_Init:0000000000000000 HAL_I2C_Init + /tmp/ccE2rRGE.s:1457 .text.HAL_I2C_MspDeInit:0000000000000000 $t + /tmp/ccE2rRGE.s:1463 .text.HAL_I2C_MspDeInit:0000000000000000 HAL_I2C_MspDeInit + /tmp/ccE2rRGE.s:1478 .text.HAL_I2C_DeInit:0000000000000000 $t + /tmp/ccE2rRGE.s:1484 .text.HAL_I2C_DeInit:0000000000000000 HAL_I2C_DeInit + /tmp/ccE2rRGE.s:1547 .text.HAL_I2C_Master_Transmit:0000000000000000 $t + /tmp/ccE2rRGE.s:1553 .text.HAL_I2C_Master_Transmit:0000000000000000 HAL_I2C_Master_Transmit + /tmp/ccE2rRGE.s:1859 .text.HAL_I2C_Master_Transmit:0000000000000178 $d + /tmp/ccE2rRGE.s:1864 .text.HAL_I2C_Master_Receive:0000000000000000 $t + /tmp/ccE2rRGE.s:1870 .text.HAL_I2C_Master_Receive:0000000000000000 HAL_I2C_Master_Receive + /tmp/ccE2rRGE.s:2175 .text.HAL_I2C_Master_Receive:0000000000000178 $d + /tmp/ccE2rRGE.s:2180 .text.HAL_I2C_Slave_Transmit:0000000000000000 $t + /tmp/ccE2rRGE.s:2186 .text.HAL_I2C_Slave_Transmit:0000000000000000 HAL_I2C_Slave_Transmit + /tmp/ccE2rRGE.s:2539 .text.HAL_I2C_Slave_Receive:0000000000000000 $t + /tmp/ccE2rRGE.s:2545 .text.HAL_I2C_Slave_Receive:0000000000000000 HAL_I2C_Slave_Receive + /tmp/ccE2rRGE.s:2872 .text.HAL_I2C_Master_Transmit_IT:0000000000000000 $t + /tmp/ccE2rRGE.s:2878 .text.HAL_I2C_Master_Transmit_IT:0000000000000000 HAL_I2C_Master_Transmit_IT + /tmp/ccE2rRGE.s:3027 .text.HAL_I2C_Master_Transmit_IT:000000000000008c $d + /tmp/ccE2rRGE.s:11326 .text.I2C_Master_ISR_IT:0000000000000000 I2C_Master_ISR_IT + /tmp/ccE2rRGE.s:3034 .text.HAL_I2C_Master_Receive_IT:0000000000000000 $t + /tmp/ccE2rRGE.s:3040 .text.HAL_I2C_Master_Receive_IT:0000000000000000 HAL_I2C_Master_Receive_IT + /tmp/ccE2rRGE.s:3189 .text.HAL_I2C_Master_Receive_IT:000000000000008c $d + /tmp/ccE2rRGE.s:3196 .text.HAL_I2C_Slave_Transmit_IT:0000000000000000 $t + ARM GAS /tmp/ccE2rRGE.s page 420 + + + /tmp/ccE2rRGE.s:3202 .text.HAL_I2C_Slave_Transmit_IT:0000000000000000 HAL_I2C_Slave_Transmit_IT + /tmp/ccE2rRGE.s:3304 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/dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c_ex.d @@ -0,0 +1,58 @@ +build/stm32f3xx_hal_i2c_ex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c_ex.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c_ex.lst new file mode 100644 index 0000000..77ebc57 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c_ex.lst @@ -0,0 +1,916 @@ +ARM GAS /tmp/cchPdkSO.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_i2c_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c" + 20 .section .text.HAL_I2CEx_ConfigAnalogFilter,"ax",%progbits + 21 .align 1 + 22 .global HAL_I2CEx_ConfigAnalogFilter + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_I2CEx_ConfigAnalogFilter: + 28 .LVL0: + 29 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @file stm32f3xx_hal_i2c_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * functionalities of I2C Extended peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + Filter Mode Functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + WakeUp Mode Functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + FastModePlus Functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ============================================================================== + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### I2C peripheral Extended features ##### + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ============================================================================== + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] Comparing to other previous devices, the I2C interface for STM32F3xx + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** devices contains the following additional features + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Possibility to disable or enable Analog Noise Filter + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Use of a configured Digital Noise Filter + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Disable or enable wakeup from Stop mode(s) + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Disable or enable Fast Mode Plus + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### How to use this driver ##### + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ============================================================================== + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This driver provides functions to configure Noise Filter and Wake Up Feature + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + ARM GAS /tmp/cchPdkSO.s page 2 + + + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableWakeUp() + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableWakeUp() + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure the enable or disable of fast mode plus driving capability using the functions : + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableFastModePlus() + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableFastModePlus() + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ****************************************************************************** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @attention + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * All rights reserved.

    + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the "License"; You may not use this file except in compliance with the + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * License. You may obtain a copy of the License at: + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * opensource.org/licenses/BSD-3-Clause + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ****************************************************************************** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/ + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** #include "stm32f3xx_hal.h" + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/ + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/ + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/ + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/ + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Filter Mode Functions + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### Filter Mode Functions ##### + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Noise Filters + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim + ARM GAS /tmp/cchPdkSO.s page 3 + + + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Configure I2C Analog noise filter. + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param AnalogFilter New state of the Analog filter. + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 30 .loc 1 98 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 @ link register save eliminated. + 35 .loc 1 98 1 is_stmt 0 view .LVU1 + 36 0000 0346 mov r3, r0 + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */ + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 37 .loc 1 100 3 is_stmt 1 view .LVU2 + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + 38 .loc 1 101 3 view .LVU3 + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 39 .loc 1 103 3 view .LVU4 + 40 .loc 1 103 11 is_stmt 0 view .LVU5 + 41 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 42 0006 D2B2 uxtb r2, r2 + 43 .loc 1 103 6 view .LVU6 + 44 0008 202A cmp r2, #32 + 45 000a 23D1 bne .L3 + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 46 .loc 1 106 5 is_stmt 1 view .LVU7 + 47 .loc 1 106 5 view .LVU8 + 48 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 49 0010 012A cmp r2, #1 + 50 0012 21D0 beq .L4 + 51 .loc 1 106 5 discriminator 2 view .LVU9 + 52 0014 0122 movs r2, #1 + 53 0016 80F84020 strb r2, [r0, #64] + 54 .loc 1 106 5 discriminator 2 view .LVU10 + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 55 .loc 1 108 5 discriminator 2 view .LVU11 + 56 .loc 1 108 17 is_stmt 0 discriminator 2 view .LVU12 + 57 001a 2422 movs r2, #36 + 58 001c 80F84120 strb r2, [r0, #65] + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 59 .loc 1 111 5 is_stmt 1 discriminator 2 view .LVU13 + 60 0020 0068 ldr r0, [r0] + 61 .LVL1: + ARM GAS /tmp/cchPdkSO.s page 4 + + + 62 .loc 1 111 5 is_stmt 0 discriminator 2 view .LVU14 + 63 0022 0268 ldr r2, [r0] + 64 0024 22F00102 bic r2, r2, #1 + 65 0028 0260 str r2, [r0] + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Reset I2Cx ANOFF bit */ + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 66 .loc 1 114 5 is_stmt 1 discriminator 2 view .LVU15 + 67 .loc 1 114 9 is_stmt 0 discriminator 2 view .LVU16 + 68 002a 1868 ldr r0, [r3] + 69 .loc 1 114 19 discriminator 2 view .LVU17 + 70 002c 0268 ldr r2, [r0] + 71 .loc 1 114 25 discriminator 2 view .LVU18 + 72 002e 22F48052 bic r2, r2, #4096 + 73 0032 0260 str r2, [r0] + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Set analog filter bit*/ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= AnalogFilter; + 74 .loc 1 117 5 is_stmt 1 discriminator 2 view .LVU19 + 75 .loc 1 117 9 is_stmt 0 discriminator 2 view .LVU20 + 76 0034 1868 ldr r0, [r3] + 77 .loc 1 117 19 discriminator 2 view .LVU21 + 78 0036 0268 ldr r2, [r0] + 79 .loc 1 117 25 discriminator 2 view .LVU22 + 80 0038 1143 orrs r1, r1, r2 + 81 .LVL2: + 82 .loc 1 117 25 discriminator 2 view .LVU23 + 83 003a 0160 str r1, [r0] + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 84 .loc 1 119 5 is_stmt 1 discriminator 2 view .LVU24 + 85 003c 1968 ldr r1, [r3] + 86 003e 0A68 ldr r2, [r1] + 87 0040 42F00102 orr r2, r2, #1 + 88 0044 0A60 str r2, [r1] + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 89 .loc 1 121 5 discriminator 2 view .LVU25 + 90 .loc 1 121 17 is_stmt 0 discriminator 2 view .LVU26 + 91 0046 2022 movs r2, #32 + 92 0048 83F84120 strb r2, [r3, #65] + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */ + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 93 .loc 1 124 5 is_stmt 1 discriminator 2 view .LVU27 + 94 .loc 1 124 5 discriminator 2 view .LVU28 + 95 004c 0020 movs r0, #0 + 96 004e 83F84000 strb r0, [r3, #64] + 97 .loc 1 124 5 discriminator 2 view .LVU29 + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK; + 98 .loc 1 126 5 discriminator 2 view .LVU30 + 99 .loc 1 126 12 is_stmt 0 discriminator 2 view .LVU31 + 100 0052 7047 bx lr + 101 .LVL3: + 102 .L3: + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + ARM GAS /tmp/cchPdkSO.s page 5 + + + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY; + 103 .loc 1 130 12 view .LVU32 + 104 0054 0220 movs r0, #2 + 105 .LVL4: + 106 .loc 1 130 12 view .LVU33 + 107 0056 7047 bx lr + 108 .LVL5: + 109 .L4: + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 110 .loc 1 106 5 view .LVU34 + 111 0058 0220 movs r0, #2 + 112 .LVL6: + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 113 .loc 1 132 1 view .LVU35 + 114 005a 7047 bx lr + 115 .cfi_endproc + 116 .LFE130: + 118 .section .text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits + 119 .align 1 + 120 .global HAL_I2CEx_ConfigDigitalFilter + 121 .syntax unified + 122 .thumb + 123 .thumb_func + 125 HAL_I2CEx_ConfigDigitalFilter: + 126 .LVL7: + 127 .LFB131: + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Configure I2C Digital noise filter. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 128 .loc 1 142 1 is_stmt 1 view -0 + 129 .cfi_startproc + 130 @ args = 0, pretend = 0, frame = 0 + 131 @ frame_needed = 0, uses_anonymous_args = 0 + 132 @ link register save eliminated. + 133 .loc 1 142 1 is_stmt 0 view .LVU37 + 134 0000 0346 mov r3, r0 + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** uint32_t tmpreg; + 135 .loc 1 143 3 is_stmt 1 view .LVU38 + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */ + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 136 .loc 1 146 3 view .LVU39 + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + 137 .loc 1 147 3 view .LVU40 + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 138 .loc 1 149 3 view .LVU41 + ARM GAS /tmp/cchPdkSO.s page 6 + + + 139 .loc 1 149 11 is_stmt 0 view .LVU42 + 140 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 141 0006 D2B2 uxtb r2, r2 + 142 .loc 1 149 6 view .LVU43 + 143 0008 202A cmp r2, #32 + 144 000a 21D1 bne .L7 + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */ + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 145 .loc 1 152 5 is_stmt 1 view .LVU44 + 146 .loc 1 152 5 view .LVU45 + 147 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 148 0010 012A cmp r2, #1 + 149 0012 1FD0 beq .L8 + 150 .loc 1 152 5 discriminator 2 view .LVU46 + 151 0014 0122 movs r2, #1 + 152 0016 80F84020 strb r2, [r0, #64] + 153 .loc 1 152 5 discriminator 2 view .LVU47 + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 154 .loc 1 154 5 discriminator 2 view .LVU48 + 155 .loc 1 154 17 is_stmt 0 discriminator 2 view .LVU49 + 156 001a 2422 movs r2, #36 + 157 001c 80F84120 strb r2, [r0, #65] + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 158 .loc 1 157 5 is_stmt 1 discriminator 2 view .LVU50 + 159 0020 0068 ldr r0, [r0] + 160 .LVL8: + 161 .loc 1 157 5 is_stmt 0 discriminator 2 view .LVU51 + 162 0022 0268 ldr r2, [r0] + 163 0024 22F00102 bic r2, r2, #1 + 164 0028 0260 str r2, [r0] + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Get the old register value */ + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg = hi2c->Instance->CR1; + 165 .loc 1 160 5 is_stmt 1 discriminator 2 view .LVU52 + 166 .loc 1 160 18 is_stmt 0 discriminator 2 view .LVU53 + 167 002a 1868 ldr r0, [r3] + 168 .loc 1 160 12 discriminator 2 view .LVU54 + 169 002c 0268 ldr r2, [r0] + 170 .LVL9: + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Reset I2Cx DNF bits [11:8] */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg &= ~(I2C_CR1_DNF); + 171 .loc 1 163 5 is_stmt 1 discriminator 2 view .LVU55 + 172 .loc 1 163 12 is_stmt 0 discriminator 2 view .LVU56 + 173 002e 22F47062 bic r2, r2, #3840 + 174 .LVL10: + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Set I2Cx DNF coefficient */ + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg |= DigitalFilter << 8U; + 175 .loc 1 166 5 is_stmt 1 discriminator 2 view .LVU57 + 176 .loc 1 166 12 is_stmt 0 discriminator 2 view .LVU58 + 177 0032 42EA0122 orr r2, r2, r1, lsl #8 + 178 .LVL11: + ARM GAS /tmp/cchPdkSO.s page 7 + + + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Store the new register value */ + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 = tmpreg; + 179 .loc 1 169 5 is_stmt 1 discriminator 2 view .LVU59 + 180 .loc 1 169 25 is_stmt 0 discriminator 2 view .LVU60 + 181 0036 0260 str r2, [r0] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 182 .loc 1 171 5 is_stmt 1 discriminator 2 view .LVU61 + 183 0038 1968 ldr r1, [r3] + 184 .LVL12: + 185 .loc 1 171 5 is_stmt 0 discriminator 2 view .LVU62 + 186 003a 0A68 ldr r2, [r1] + 187 .LVL13: + 188 .loc 1 171 5 discriminator 2 view .LVU63 + 189 003c 42F00102 orr r2, r2, #1 + 190 0040 0A60 str r2, [r1] + 191 .LVL14: + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 192 .loc 1 173 5 is_stmt 1 discriminator 2 view .LVU64 + 193 .loc 1 173 17 is_stmt 0 discriminator 2 view .LVU65 + 194 0042 2022 movs r2, #32 + 195 0044 83F84120 strb r2, [r3, #65] + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */ + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 196 .loc 1 176 5 is_stmt 1 discriminator 2 view .LVU66 + 197 .loc 1 176 5 discriminator 2 view .LVU67 + 198 0048 0020 movs r0, #0 + 199 004a 83F84000 strb r0, [r3, #64] + 200 .loc 1 176 5 discriminator 2 view .LVU68 + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK; + 201 .loc 1 178 5 discriminator 2 view .LVU69 + 202 .loc 1 178 12 is_stmt 0 discriminator 2 view .LVU70 + 203 004e 7047 bx lr + 204 .LVL15: + 205 .L7: + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY; + 206 .loc 1 182 12 view .LVU71 + 207 0050 0220 movs r0, #2 + 208 .LVL16: + 209 .loc 1 182 12 view .LVU72 + 210 0052 7047 bx lr + 211 .LVL17: + 212 .L8: + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 213 .loc 1 152 5 view .LVU73 + 214 0054 0220 movs r0, #2 + 215 .LVL18: + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 216 .loc 1 184 1 view .LVU74 + ARM GAS /tmp/cchPdkSO.s page 8 + + + 217 0056 7047 bx lr + 218 .cfi_endproc + 219 .LFE131: + 221 .section .text.HAL_I2CEx_EnableWakeUp,"ax",%progbits + 222 .align 1 + 223 .global HAL_I2CEx_EnableWakeUp + 224 .syntax unified + 225 .thumb + 226 .thumb_func + 228 HAL_I2CEx_EnableWakeUp: + 229 .LVL19: + 230 .LFB132: + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @} + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief WakeUp Mode Functions + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### WakeUp Mode Functions ##### + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Wake Up Feature + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Enable I2C wakeup from Stop mode(s). + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 231 .loc 1 210 1 is_stmt 1 view -0 + 232 .cfi_startproc + 233 @ args = 0, pretend = 0, frame = 0 + 234 @ frame_needed = 0, uses_anonymous_args = 0 + 235 @ link register save eliminated. + 236 .loc 1 210 1 is_stmt 0 view .LVU76 + 237 0000 0346 mov r3, r0 + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */ + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 238 .loc 1 212 3 is_stmt 1 view .LVU77 + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 239 .loc 1 214 3 view .LVU78 + 240 .loc 1 214 11 is_stmt 0 view .LVU79 + 241 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 242 0006 D2B2 uxtb r2, r2 + 243 .loc 1 214 6 view .LVU80 + 244 0008 202A cmp r2, #32 + 245 000a 1FD1 bne .L11 + ARM GAS /tmp/cchPdkSO.s page 9 + + + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */ + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 246 .loc 1 217 5 is_stmt 1 view .LVU81 + 247 .loc 1 217 5 view .LVU82 + 248 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 249 0010 012A cmp r2, #1 + 250 0012 1DD0 beq .L12 + 251 .loc 1 217 5 discriminator 2 view .LVU83 + 252 0014 0122 movs r2, #1 + 253 0016 80F84020 strb r2, [r0, #64] + 254 .loc 1 217 5 discriminator 2 view .LVU84 + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 255 .loc 1 219 5 discriminator 2 view .LVU85 + 256 .loc 1 219 17 is_stmt 0 discriminator 2 view .LVU86 + 257 001a 2422 movs r2, #36 + 258 001c 80F84120 strb r2, [r0, #65] + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 259 .loc 1 222 5 is_stmt 1 discriminator 2 view .LVU87 + 260 0020 0168 ldr r1, [r0] + 261 0022 0A68 ldr r2, [r1] + 262 0024 22F00102 bic r2, r2, #1 + 263 0028 0A60 str r2, [r1] + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + 264 .loc 1 225 5 discriminator 2 view .LVU88 + 265 .loc 1 225 9 is_stmt 0 discriminator 2 view .LVU89 + 266 002a 0168 ldr r1, [r0] + 267 .loc 1 225 19 discriminator 2 view .LVU90 + 268 002c 0A68 ldr r2, [r1] + 269 .loc 1 225 25 discriminator 2 view .LVU91 + 270 002e 42F48022 orr r2, r2, #262144 + 271 0032 0A60 str r2, [r1] + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 272 .loc 1 227 5 is_stmt 1 discriminator 2 view .LVU92 + 273 0034 0168 ldr r1, [r0] + 274 0036 0A68 ldr r2, [r1] + 275 0038 42F00102 orr r2, r2, #1 + 276 003c 0A60 str r2, [r1] + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 277 .loc 1 229 5 discriminator 2 view .LVU93 + 278 .loc 1 229 17 is_stmt 0 discriminator 2 view .LVU94 + 279 003e 2022 movs r2, #32 + 280 0040 80F84120 strb r2, [r0, #65] + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */ + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 281 .loc 1 232 5 is_stmt 1 discriminator 2 view .LVU95 + 282 .loc 1 232 5 discriminator 2 view .LVU96 + 283 0044 0020 movs r0, #0 + 284 .LVL20: + ARM GAS /tmp/cchPdkSO.s page 10 + + + 285 .loc 1 232 5 is_stmt 0 discriminator 2 view .LVU97 + 286 0046 83F84000 strb r0, [r3, #64] + 287 .loc 1 232 5 is_stmt 1 discriminator 2 view .LVU98 + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK; + 288 .loc 1 234 5 discriminator 2 view .LVU99 + 289 .loc 1 234 12 is_stmt 0 discriminator 2 view .LVU100 + 290 004a 7047 bx lr + 291 .LVL21: + 292 .L11: + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY; + 293 .loc 1 238 12 view .LVU101 + 294 004c 0220 movs r0, #2 + 295 .LVL22: + 296 .loc 1 238 12 view .LVU102 + 297 004e 7047 bx lr + 298 .LVL23: + 299 .L12: + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 300 .loc 1 217 5 view .LVU103 + 301 0050 0220 movs r0, #2 + 302 .LVL24: + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 303 .loc 1 240 1 view .LVU104 + 304 0052 7047 bx lr + 305 .cfi_endproc + 306 .LFE132: + 308 .section .text.HAL_I2CEx_DisableWakeUp,"ax",%progbits + 309 .align 1 + 310 .global HAL_I2CEx_DisableWakeUp + 311 .syntax unified + 312 .thumb + 313 .thumb_func + 315 HAL_I2CEx_DisableWakeUp: + 316 .LVL25: + 317 .LFB133: + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Disable I2C wakeup from Stop mode(s). + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 318 .loc 1 249 1 is_stmt 1 view -0 + 319 .cfi_startproc + 320 @ args = 0, pretend = 0, frame = 0 + 321 @ frame_needed = 0, uses_anonymous_args = 0 + 322 @ link register save eliminated. + 323 .loc 1 249 1 is_stmt 0 view .LVU106 + 324 0000 0346 mov r3, r0 + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */ + ARM GAS /tmp/cchPdkSO.s page 11 + + + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 325 .loc 1 251 3 is_stmt 1 view .LVU107 + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 326 .loc 1 253 3 view .LVU108 + 327 .loc 1 253 11 is_stmt 0 view .LVU109 + 328 0002 90F84120 ldrb r2, [r0, #65] @ zero_extendqisi2 + 329 0006 D2B2 uxtb r2, r2 + 330 .loc 1 253 6 view .LVU110 + 331 0008 202A cmp r2, #32 + 332 000a 1FD1 bne .L15 + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */ + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 333 .loc 1 256 5 is_stmt 1 view .LVU111 + 334 .loc 1 256 5 view .LVU112 + 335 000c 90F84020 ldrb r2, [r0, #64] @ zero_extendqisi2 + 336 0010 012A cmp r2, #1 + 337 0012 1DD0 beq .L16 + 338 .loc 1 256 5 discriminator 2 view .LVU113 + 339 0014 0122 movs r2, #1 + 340 0016 80F84020 strb r2, [r0, #64] + 341 .loc 1 256 5 discriminator 2 view .LVU114 + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 342 .loc 1 258 5 discriminator 2 view .LVU115 + 343 .loc 1 258 17 is_stmt 0 discriminator 2 view .LVU116 + 344 001a 2422 movs r2, #36 + 345 001c 80F84120 strb r2, [r0, #65] + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 346 .loc 1 261 5 is_stmt 1 discriminator 2 view .LVU117 + 347 0020 0168 ldr r1, [r0] + 348 0022 0A68 ldr r2, [r1] + 349 0024 22F00102 bic r2, r2, #1 + 350 0028 0A60 str r2, [r1] + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + 351 .loc 1 264 5 discriminator 2 view .LVU118 + 352 .loc 1 264 9 is_stmt 0 discriminator 2 view .LVU119 + 353 002a 0168 ldr r1, [r0] + 354 .loc 1 264 19 discriminator 2 view .LVU120 + 355 002c 0A68 ldr r2, [r1] + 356 .loc 1 264 25 discriminator 2 view .LVU121 + 357 002e 22F48022 bic r2, r2, #262144 + 358 0032 0A60 str r2, [r1] + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 359 .loc 1 266 5 is_stmt 1 discriminator 2 view .LVU122 + 360 0034 0168 ldr r1, [r0] + 361 0036 0A68 ldr r2, [r1] + 362 0038 42F00102 orr r2, r2, #1 + 363 003c 0A60 str r2, [r1] + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + ARM GAS /tmp/cchPdkSO.s page 12 + + + 364 .loc 1 268 5 discriminator 2 view .LVU123 + 365 .loc 1 268 17 is_stmt 0 discriminator 2 view .LVU124 + 366 003e 2022 movs r2, #32 + 367 0040 80F84120 strb r2, [r0, #65] + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */ + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 368 .loc 1 271 5 is_stmt 1 discriminator 2 view .LVU125 + 369 .loc 1 271 5 discriminator 2 view .LVU126 + 370 0044 0020 movs r0, #0 + 371 .LVL26: + 372 .loc 1 271 5 is_stmt 0 discriminator 2 view .LVU127 + 373 0046 83F84000 strb r0, [r3, #64] + 374 .loc 1 271 5 is_stmt 1 discriminator 2 view .LVU128 + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK; + 375 .loc 1 273 5 discriminator 2 view .LVU129 + 376 .loc 1 273 12 is_stmt 0 discriminator 2 view .LVU130 + 377 004a 7047 bx lr + 378 .LVL27: + 379 .L15: + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY; + 380 .loc 1 277 12 view .LVU131 + 381 004c 0220 movs r0, #2 + 382 .LVL28: + 383 .loc 1 277 12 view .LVU132 + 384 004e 7047 bx lr + 385 .LVL29: + 386 .L16: + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 387 .loc 1 256 5 view .LVU133 + 388 0050 0220 movs r0, #2 + 389 .LVL30: + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 390 .loc 1 279 1 view .LVU134 + 391 0052 7047 bx lr + 392 .cfi_endproc + 393 .LFE133: + 395 .section .text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits + 396 .align 1 + 397 .global HAL_I2CEx_EnableFastModePlus + 398 .syntax unified + 399 .thumb + 400 .thumb_func + 402 HAL_I2CEx_EnableFastModePlus: + 403 .LVL31: + 404 .LFB134: + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @} + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Fast Mode Plus Functions + ARM GAS /tmp/cchPdkSO.s page 13 + + + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### Fast Mode Plus Functions ##### + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Fast Mode Plus + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Enable the I2C fast mode plus driving capability. + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be enabled on all selected + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be enabled + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be enabled + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval None + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 405 .loc 1 314 1 is_stmt 1 view -0 + 406 .cfi_startproc + 407 @ args = 0, pretend = 0, frame = 8 + 408 @ frame_needed = 0, uses_anonymous_args = 0 + 409 @ link register save eliminated. + 410 .loc 1 314 1 is_stmt 0 view .LVU136 + 411 0000 82B0 sub sp, sp, #8 + 412 .cfi_def_cfa_offset 8 + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameter */ + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 413 .loc 1 316 3 is_stmt 1 view .LVU137 + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 414 .loc 1 319 3 view .LVU138 + 415 .LBB2: + 416 .loc 1 319 3 view .LVU139 + 417 .loc 1 319 3 view .LVU140 + 418 0002 084B ldr r3, .L19 + 419 0004 9A69 ldr r2, [r3, #24] + 420 0006 42F00102 orr r2, r2, #1 + 421 000a 9A61 str r2, [r3, #24] + 422 .loc 1 319 3 view .LVU141 + 423 000c 9B69 ldr r3, [r3, #24] + 424 000e 03F00103 and r3, r3, #1 + 425 0012 0193 str r3, [sp, #4] + 426 .loc 1 319 3 view .LVU142 + 427 0014 019B ldr r3, [sp, #4] + ARM GAS /tmp/cchPdkSO.s page 14 + + + 428 .LBE2: + 429 .loc 1 319 3 view .LVU143 + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable fast mode plus driving capability for selected pin */ + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); + 430 .loc 1 322 3 view .LVU144 + 431 0016 044A ldr r2, .L19+4 + 432 0018 1368 ldr r3, [r2] + 433 001a 0343 orrs r3, r3, r0 + 434 001c 1360 str r3, [r2] + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 435 .loc 1 323 1 is_stmt 0 view .LVU145 + 436 001e 02B0 add sp, sp, #8 + 437 .cfi_def_cfa_offset 0 + 438 @ sp needed + 439 0020 7047 bx lr + 440 .L20: + 441 0022 00BF .align 2 + 442 .L19: + 443 0024 00100240 .word 1073876992 + 444 0028 00000140 .word 1073807360 + 445 .cfi_endproc + 446 .LFE134: + 448 .section .text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits + 449 .align 1 + 450 .global HAL_I2CEx_DisableFastModePlus + 451 .syntax unified + 452 .thumb + 453 .thumb_func + 455 HAL_I2CEx_DisableFastModePlus: + 456 .LVL32: + 457 .LFB135: + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Disable the I2C fast mode plus driving capability. + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be disabled on all selected + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be disabled + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be disabled + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval None + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 458 .loc 1 341 1 is_stmt 1 view -0 + 459 .cfi_startproc + 460 @ args = 0, pretend = 0, frame = 8 + 461 @ frame_needed = 0, uses_anonymous_args = 0 + 462 @ link register save eliminated. + 463 .loc 1 341 1 is_stmt 0 view .LVU147 + 464 0000 82B0 sub sp, sp, #8 + ARM GAS /tmp/cchPdkSO.s page 15 + + + 465 .cfi_def_cfa_offset 8 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameter */ + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 466 .loc 1 343 3 is_stmt 1 view .LVU148 + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 467 .loc 1 346 3 view .LVU149 + 468 .LBB3: + 469 .loc 1 346 3 view .LVU150 + 470 .loc 1 346 3 view .LVU151 + 471 0002 084B ldr r3, .L23 + 472 0004 9A69 ldr r2, [r3, #24] + 473 0006 42F00102 orr r2, r2, #1 + 474 000a 9A61 str r2, [r3, #24] + 475 .loc 1 346 3 view .LVU152 + 476 000c 9B69 ldr r3, [r3, #24] + 477 000e 03F00103 and r3, r3, #1 + 478 0012 0193 str r3, [sp, #4] + 479 .loc 1 346 3 view .LVU153 + 480 0014 019B ldr r3, [sp, #4] + 481 .LBE3: + 482 .loc 1 346 3 view .LVU154 + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable fast mode plus driving capability for selected pin */ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); + 483 .loc 1 349 3 view .LVU155 + 484 0016 044A ldr r2, .L23+4 + 485 0018 1368 ldr r3, [r2] + 486 001a 23EA0003 bic r3, r3, r0 + 487 001e 1360 str r3, [r2] + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 488 .loc 1 350 1 is_stmt 0 view .LVU156 + 489 0020 02B0 add sp, sp, #8 + 490 .cfi_def_cfa_offset 0 + 491 @ sp needed + 492 0022 7047 bx lr + 493 .L24: + 494 .align 2 + 495 .L23: + 496 0024 00100240 .word 1073876992 + 497 0028 00000140 .word 1073807360 + 498 .cfi_endproc + 499 .LFE135: + 501 .text + 502 .Letext0: + 503 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 504 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 505 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 506 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 507 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 508 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + ARM GAS /tmp/cchPdkSO.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_i2c_ex.c + /tmp/cchPdkSO.s:21 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 $t + /tmp/cchPdkSO.s:27 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 HAL_I2CEx_ConfigAnalogFilter + /tmp/cchPdkSO.s:119 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 $t + /tmp/cchPdkSO.s:125 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 HAL_I2CEx_ConfigDigitalFilter + /tmp/cchPdkSO.s:222 .text.HAL_I2CEx_EnableWakeUp:0000000000000000 $t + /tmp/cchPdkSO.s:228 .text.HAL_I2CEx_EnableWakeUp:0000000000000000 HAL_I2CEx_EnableWakeUp + /tmp/cchPdkSO.s:309 .text.HAL_I2CEx_DisableWakeUp:0000000000000000 $t + /tmp/cchPdkSO.s:315 .text.HAL_I2CEx_DisableWakeUp:0000000000000000 HAL_I2CEx_DisableWakeUp + /tmp/cchPdkSO.s:396 .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 $t + /tmp/cchPdkSO.s:402 .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 HAL_I2CEx_EnableFastModePlus + /tmp/cchPdkSO.s:443 .text.HAL_I2CEx_EnableFastModePlus:0000000000000024 $d + /tmp/cchPdkSO.s:449 .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 $t + /tmp/cchPdkSO.s:455 .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 HAL_I2CEx_DisableFastModePlus + /tmp/cchPdkSO.s:496 .text.HAL_I2CEx_DisableFastModePlus:0000000000000024 $d + +NO UNDEFINED SYMBOLS diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c_ex.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_i2c_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..08810fb2f77435ca80f56dbf517ad9c6f8ded97c GIT binary patch literal 11076 zcmdT~eRN#Kb)R`}zbx6ZY{|A{%l1kZMSxddHvYmGuXb0Ku=U~HwIhS+`f2w`yY+tP z?5>1N67UIWO49hmgqEblIpM$wCq0xv8wjO92oOG+gc3t2E#Wlu(2@jbN{DGqdkFpA zdG|?g*CK`d)y~m-zkBc8xpU{v%zba(>bl6jekrA}ixeGVo)hAs-%~a2%?diiTG1l( z{*z~e{^$P6f8mDHC(rKo%L`k7B-@UIYR5h37ilfs_LkJNBTYn|IUcpBWg&T_IbD

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z&4@&%?9tDcWVeZNE8_^`m5h^&CC2L*|CsT1#=99GWPFQ_f6jO}<9&<|GCs!mcZ@GF{*3VqBmGiN{?#$A zVeDYMn6Zy>gz+$AhVjdccQXDp;}eX}G5(bCO~!W_JxHtMMW_+Caf3YMdtsN`Cl^s8%7r%Gx$wIG!UZSR^~5ceg|WS z5TE0t%+tqR4Jn;|{v$lf@-iV(>-Ef^;QAXGzr^xe331)c`~!rr^DyIMEdL?%KVp1= z<*zXRFO09V{2fBXm=Yt6r-l%A>lhnYzLxn`MyRUs4HCltV}!7EJL4maFB8JPhw=#_ z@p#lB)QYEPIJNT=!cGSv;?_-wIBz3_vdY(JPftnGSN%hOJ?o#x`WLbOUdj{DUqSm3 z`fn3LU+pK@--SA|uhuc_)BBc&}Hvt zB7}X>Svr<08{@!o(ZaM%;S60Copjn2o#Qy+caorU{y}CvGAo{^3#(LqZ>ZL>-s$-n zT3uQBgsrY!;5bmNve3tj&Z3#^Oqt`;lZi}zqJS|f+87_lkw`ddvxQ_fQz~QV^DT^` zk)JdxM8*8%Iciz@8G#KWpaQ>cD%f-z2G>+?-lMh+wy%Eb- ztzBwDYr$Et)KqE3o%FEORH@dZIx6Sm!Z!L}_2@mUx?g&?vy0vD2n0^Oli+C`+QrtR zAv^Vc4xZMnU2HvS@6_7~W+6R#S8?jmKdX?>cEKY^mD9L8^&a{Fy?0s9Y9;VbM2Hmy ziVNAG@(wO+L9rVbm3#2wJAge)?{4%~PW@6d{6L`k1*ytXR6c1Nfy5?PRq4He{k+z$ zbm%oe=Ir|KZW*~PXuTxIXe4ttb`ZF|4Z_NXr^uj8fqRpd;& zkUhHSKiLRvy=UOq4qJ(JsD6g^>?$8N;BlJ)QomG+&~whm)9~*IInstance==CAN) + 107 .loc 1 88 3 is_stmt 1 view .LVU18 + 108 .loc 1 88 10 is_stmt 0 view .LVU19 + 109 0010 0268 ldr r2, [r0] + 110 .loc 1 88 5 view .LVU20 + 111 0012 184B ldr r3, .L9 + 112 0014 9A42 cmp r2, r3 + 113 0016 02D0 beq .L8 + 114 .LVL1: + 115 .L5: + 89:Core/Src/stm32f3xx_hal_msp.c **** { + 90:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 0 */ + 91:Core/Src/stm32f3xx_hal_msp.c **** + 92:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspInit 0 */ + 93:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 94:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_ENABLE(); + 95:Core/Src/stm32f3xx_hal_msp.c **** + 96:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 97:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 98:Core/Src/stm32f3xx_hal_msp.c **** PA11 ------> CAN_RX + 99:Core/Src/stm32f3xx_hal_msp.c **** PA12 ------> CAN_TX + 100:Core/Src/stm32f3xx_hal_msp.c **** */ + 101:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 102:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 103:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 104:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 105:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_CAN; + 106:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 107:Core/Src/stm32f3xx_hal_msp.c **** + 108:Core/Src/stm32f3xx_hal_msp.c **** /* CAN interrupt Init */ + 109:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); + 110:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); + 111:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 1 */ + 112:Core/Src/stm32f3xx_hal_msp.c **** + 113:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspInit 1 */ + 114:Core/Src/stm32f3xx_hal_msp.c **** } + 115:Core/Src/stm32f3xx_hal_msp.c **** + 116:Core/Src/stm32f3xx_hal_msp.c **** } + ARM GAS /tmp/ccBY67LK.s page 5 + + + 116 .loc 1 116 1 view .LVU21 + 117 0018 09B0 add sp, sp, #36 + 118 .cfi_remember_state + 119 .cfi_def_cfa_offset 4 + 120 @ sp needed + 121 001a 5DF804FB ldr pc, [sp], #4 + 122 .LVL2: + 123 .L8: + 124 .cfi_restore_state + 94:Core/Src/stm32f3xx_hal_msp.c **** + 125 .loc 1 94 5 is_stmt 1 view .LVU22 + 126 .LBB4: + 94:Core/Src/stm32f3xx_hal_msp.c **** + 127 .loc 1 94 5 view .LVU23 + 94:Core/Src/stm32f3xx_hal_msp.c **** + 128 .loc 1 94 5 view .LVU24 + 129 001e 03F5D633 add r3, r3, #109568 + 130 0022 DA69 ldr r2, [r3, #28] + 131 0024 42F00072 orr r2, r2, #33554432 + 132 0028 DA61 str r2, [r3, #28] + 94:Core/Src/stm32f3xx_hal_msp.c **** + 133 .loc 1 94 5 view .LVU25 + 134 002a DA69 ldr r2, [r3, #28] + 135 002c 02F00072 and r2, r2, #33554432 + 136 0030 0192 str r2, [sp, #4] + 94:Core/Src/stm32f3xx_hal_msp.c **** + 137 .loc 1 94 5 view .LVU26 + 138 0032 019A ldr r2, [sp, #4] + 139 .LBE4: + 94:Core/Src/stm32f3xx_hal_msp.c **** + 140 .loc 1 94 5 view .LVU27 + 96:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 141 .loc 1 96 5 view .LVU28 + 142 .LBB5: + 96:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 143 .loc 1 96 5 view .LVU29 + 96:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 144 .loc 1 96 5 view .LVU30 + 145 0034 5A69 ldr r2, [r3, #20] + 146 0036 42F40032 orr r2, r2, #131072 + 147 003a 5A61 str r2, [r3, #20] + 96:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 148 .loc 1 96 5 view .LVU31 + 149 003c 5B69 ldr r3, [r3, #20] + 150 003e 03F40033 and r3, r3, #131072 + 151 0042 0293 str r3, [sp, #8] + 96:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 152 .loc 1 96 5 view .LVU32 + 153 0044 029B ldr r3, [sp, #8] + 154 .LBE5: + 96:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 155 .loc 1 96 5 view .LVU33 + 101:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 156 .loc 1 101 5 view .LVU34 + 101:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 157 .loc 1 101 25 is_stmt 0 view .LVU35 + 158 0046 4FF4C053 mov r3, #6144 + ARM GAS /tmp/ccBY67LK.s page 6 + + + 159 004a 0393 str r3, [sp, #12] + 102:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 160 .loc 1 102 5 is_stmt 1 view .LVU36 + 102:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 161 .loc 1 102 26 is_stmt 0 view .LVU37 + 162 004c 0223 movs r3, #2 + 163 004e 0493 str r3, [sp, #16] + 103:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 164 .loc 1 103 5 is_stmt 1 view .LVU38 + 104:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_CAN; + 165 .loc 1 104 5 view .LVU39 + 104:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_CAN; + 166 .loc 1 104 27 is_stmt 0 view .LVU40 + 167 0050 0323 movs r3, #3 + 168 0052 0693 str r3, [sp, #24] + 105:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 169 .loc 1 105 5 is_stmt 1 view .LVU41 + 105:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 170 .loc 1 105 31 is_stmt 0 view .LVU42 + 171 0054 0923 movs r3, #9 + 172 0056 0793 str r3, [sp, #28] + 106:Core/Src/stm32f3xx_hal_msp.c **** + 173 .loc 1 106 5 is_stmt 1 view .LVU43 + 174 0058 03A9 add r1, sp, #12 + 175 005a 4FF09040 mov r0, #1207959552 + 176 .LVL3: + 106:Core/Src/stm32f3xx_hal_msp.c **** + 177 .loc 1 106 5 is_stmt 0 view .LVU44 + 178 005e FFF7FEFF bl HAL_GPIO_Init + 179 .LVL4: + 109:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); + 180 .loc 1 109 5 is_stmt 1 view .LVU45 + 181 0062 0022 movs r2, #0 + 182 0064 1146 mov r1, r2 + 183 0066 1420 movs r0, #20 + 184 0068 FFF7FEFF bl HAL_NVIC_SetPriority + 185 .LVL5: + 110:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 1 */ + 186 .loc 1 110 5 view .LVU46 + 187 006c 1420 movs r0, #20 + 188 006e FFF7FEFF bl HAL_NVIC_EnableIRQ + 189 .LVL6: + 190 .loc 1 116 1 is_stmt 0 view .LVU47 + 191 0072 D1E7 b .L5 + 192 .L10: + 193 .align 2 + 194 .L9: + 195 0074 00640040 .word 1073767424 + 196 .cfi_endproc + 197 .LFE131: + 199 .section .text.HAL_CAN_MspDeInit,"ax",%progbits + 200 .align 1 + 201 .global HAL_CAN_MspDeInit + 202 .syntax unified + 203 .thumb + 204 .thumb_func + 206 HAL_CAN_MspDeInit: + ARM GAS /tmp/ccBY67LK.s page 7 + + + 207 .LVL7: + 208 .LFB132: + 117:Core/Src/stm32f3xx_hal_msp.c **** + 118:Core/Src/stm32f3xx_hal_msp.c **** /** + 119:Core/Src/stm32f3xx_hal_msp.c **** * @brief CAN MSP De-Initialization + 120:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 121:Core/Src/stm32f3xx_hal_msp.c **** * @param hcan: CAN handle pointer + 122:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 123:Core/Src/stm32f3xx_hal_msp.c **** */ + 124:Core/Src/stm32f3xx_hal_msp.c **** void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) + 125:Core/Src/stm32f3xx_hal_msp.c **** { + 209 .loc 1 125 1 is_stmt 1 view -0 + 210 .cfi_startproc + 211 @ args = 0, pretend = 0, frame = 0 + 212 @ frame_needed = 0, uses_anonymous_args = 0 + 213 .loc 1 125 1 is_stmt 0 view .LVU49 + 214 0000 08B5 push {r3, lr} + 215 .cfi_def_cfa_offset 8 + 216 .cfi_offset 3, -8 + 217 .cfi_offset 14, -4 + 126:Core/Src/stm32f3xx_hal_msp.c **** if(hcan->Instance==CAN) + 218 .loc 1 126 3 is_stmt 1 view .LVU50 + 219 .loc 1 126 10 is_stmt 0 view .LVU51 + 220 0002 0268 ldr r2, [r0] + 221 .loc 1 126 5 view .LVU52 + 222 0004 094B ldr r3, .L15 + 223 0006 9A42 cmp r2, r3 + 224 0008 00D0 beq .L14 + 225 .LVL8: + 226 .L11: + 127:Core/Src/stm32f3xx_hal_msp.c **** { + 128:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 0 */ + 129:Core/Src/stm32f3xx_hal_msp.c **** + 130:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspDeInit 0 */ + 131:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 132:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_DISABLE(); + 133:Core/Src/stm32f3xx_hal_msp.c **** + 134:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 135:Core/Src/stm32f3xx_hal_msp.c **** PA11 ------> CAN_RX + 136:Core/Src/stm32f3xx_hal_msp.c **** PA12 ------> CAN_TX + 137:Core/Src/stm32f3xx_hal_msp.c **** */ + 138:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + 139:Core/Src/stm32f3xx_hal_msp.c **** + 140:Core/Src/stm32f3xx_hal_msp.c **** /* CAN interrupt DeInit */ + 141:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn); + 142:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 1 */ + 143:Core/Src/stm32f3xx_hal_msp.c **** + 144:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspDeInit 1 */ + 145:Core/Src/stm32f3xx_hal_msp.c **** } + 146:Core/Src/stm32f3xx_hal_msp.c **** + 147:Core/Src/stm32f3xx_hal_msp.c **** } + 227 .loc 1 147 1 view .LVU53 + 228 000a 08BD pop {r3, pc} + 229 .LVL9: + 230 .L14: + 132:Core/Src/stm32f3xx_hal_msp.c **** + 231 .loc 1 132 5 is_stmt 1 view .LVU54 + ARM GAS /tmp/ccBY67LK.s page 8 + + + 232 000c 084A ldr r2, .L15+4 + 233 000e D369 ldr r3, [r2, #28] + 234 0010 23F00073 bic r3, r3, #33554432 + 235 0014 D361 str r3, [r2, #28] + 138:Core/Src/stm32f3xx_hal_msp.c **** + 236 .loc 1 138 5 view .LVU55 + 237 0016 4FF4C051 mov r1, #6144 + 238 001a 4FF09040 mov r0, #1207959552 + 239 .LVL10: + 138:Core/Src/stm32f3xx_hal_msp.c **** + 240 .loc 1 138 5 is_stmt 0 view .LVU56 + 241 001e FFF7FEFF bl HAL_GPIO_DeInit + 242 .LVL11: + 141:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 1 */ + 243 .loc 1 141 5 is_stmt 1 view .LVU57 + 244 0022 1420 movs r0, #20 + 245 0024 FFF7FEFF bl HAL_NVIC_DisableIRQ + 246 .LVL12: + 247 .loc 1 147 1 is_stmt 0 view .LVU58 + 248 0028 EFE7 b .L11 + 249 .L16: + 250 002a 00BF .align 2 + 251 .L15: + 252 002c 00640040 .word 1073767424 + 253 0030 00100240 .word 1073876992 + 254 .cfi_endproc + 255 .LFE132: + 257 .section .text.HAL_I2C_MspInit,"ax",%progbits + 258 .align 1 + 259 .global HAL_I2C_MspInit + 260 .syntax unified + 261 .thumb + 262 .thumb_func + 264 HAL_I2C_MspInit: + 265 .LVL13: + 266 .LFB133: + 148:Core/Src/stm32f3xx_hal_msp.c **** + 149:Core/Src/stm32f3xx_hal_msp.c **** /** + 150:Core/Src/stm32f3xx_hal_msp.c **** * @brief I2C MSP Initialization + 151:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example + 152:Core/Src/stm32f3xx_hal_msp.c **** * @param hi2c: I2C handle pointer + 153:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 154:Core/Src/stm32f3xx_hal_msp.c **** */ + 155:Core/Src/stm32f3xx_hal_msp.c **** void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) + 156:Core/Src/stm32f3xx_hal_msp.c **** { + 267 .loc 1 156 1 is_stmt 1 view -0 + 268 .cfi_startproc + 269 @ args = 0, pretend = 0, frame = 40 + 270 @ frame_needed = 0, uses_anonymous_args = 0 + 271 .loc 1 156 1 is_stmt 0 view .LVU60 + 272 0000 F0B5 push {r4, r5, r6, r7, lr} + 273 .cfi_def_cfa_offset 20 + 274 .cfi_offset 4, -20 + 275 .cfi_offset 5, -16 + 276 .cfi_offset 6, -12 + 277 .cfi_offset 7, -8 + 278 .cfi_offset 14, -4 + ARM GAS /tmp/ccBY67LK.s page 9 + + + 279 0002 8BB0 sub sp, sp, #44 + 280 .cfi_def_cfa_offset 64 + 157:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 281 .loc 1 157 3 is_stmt 1 view .LVU61 + 282 .loc 1 157 20 is_stmt 0 view .LVU62 + 283 0004 0023 movs r3, #0 + 284 0006 0593 str r3, [sp, #20] + 285 0008 0693 str r3, [sp, #24] + 286 000a 0793 str r3, [sp, #28] + 287 000c 0893 str r3, [sp, #32] + 288 000e 0993 str r3, [sp, #36] + 158:Core/Src/stm32f3xx_hal_msp.c **** if(hi2c->Instance==I2C1) + 289 .loc 1 158 3 is_stmt 1 view .LVU63 + 290 .loc 1 158 10 is_stmt 0 view .LVU64 + 291 0010 0368 ldr r3, [r0] + 292 .loc 1 158 5 view .LVU65 + 293 0012 304A ldr r2, .L23 + 294 0014 9342 cmp r3, r2 + 295 0016 04D0 beq .L21 + 159:Core/Src/stm32f3xx_hal_msp.c **** { + 160:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 0 */ + 161:Core/Src/stm32f3xx_hal_msp.c **** + 162:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspInit 0 */ + 163:Core/Src/stm32f3xx_hal_msp.c **** + 164:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 165:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 166:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 167:Core/Src/stm32f3xx_hal_msp.c **** PA15 ------> I2C1_SCL + 168:Core/Src/stm32f3xx_hal_msp.c **** PB7 ------> I2C1_SDA + 169:Core/Src/stm32f3xx_hal_msp.c **** */ + 170:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = TMP_SCL_Pin; + 171:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 172:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 173:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 174:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 175:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SCL_GPIO_Port, &GPIO_InitStruct); + 176:Core/Src/stm32f3xx_hal_msp.c **** + 177:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = TMP_SDA_Pin; + 178:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 179:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 180:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 181:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 182:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SDA_GPIO_Port, &GPIO_InitStruct); + 183:Core/Src/stm32f3xx_hal_msp.c **** + 184:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 185:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C1_CLK_ENABLE(); + 186:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 187:Core/Src/stm32f3xx_hal_msp.c **** + 188:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspInit 1 */ + 189:Core/Src/stm32f3xx_hal_msp.c **** } + 190:Core/Src/stm32f3xx_hal_msp.c **** else if(hi2c->Instance==I2C2) + 296 .loc 1 190 8 is_stmt 1 view .LVU66 + 297 .loc 1 190 10 is_stmt 0 view .LVU67 + 298 0018 2F4A ldr r2, .L23+4 + 299 001a 9342 cmp r3, r2 + 300 001c 37D0 beq .L22 + 301 .LVL14: + ARM GAS /tmp/ccBY67LK.s page 10 + + + 302 .L17: + 191:Core/Src/stm32f3xx_hal_msp.c **** { + 192:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 0 */ + 193:Core/Src/stm32f3xx_hal_msp.c **** + 194:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 0 */ + 195:Core/Src/stm32f3xx_hal_msp.c **** + 196:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 197:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 198:Core/Src/stm32f3xx_hal_msp.c **** PA9 ------> I2C2_SCL + 199:Core/Src/stm32f3xx_hal_msp.c **** PA10 ------> I2C2_SDA + 200:Core/Src/stm32f3xx_hal_msp.c **** */ + 201:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + 202:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 203:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 204:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 205:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + 206:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 207:Core/Src/stm32f3xx_hal_msp.c **** + 208:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 209:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_ENABLE(); + 210:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 211:Core/Src/stm32f3xx_hal_msp.c **** + 212:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 1 */ + 213:Core/Src/stm32f3xx_hal_msp.c **** } + 214:Core/Src/stm32f3xx_hal_msp.c **** + 215:Core/Src/stm32f3xx_hal_msp.c **** } + 303 .loc 1 215 1 view .LVU68 + 304 001e 0BB0 add sp, sp, #44 + 305 .cfi_remember_state + 306 .cfi_def_cfa_offset 20 + 307 @ sp needed + 308 0020 F0BD pop {r4, r5, r6, r7, pc} + 309 .LVL15: + 310 .L21: + 311 .cfi_restore_state + 164:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 312 .loc 1 164 5 is_stmt 1 view .LVU69 + 313 .LBB6: + 164:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 314 .loc 1 164 5 view .LVU70 + 164:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 315 .loc 1 164 5 view .LVU71 + 316 0022 2E4C ldr r4, .L23+8 + 317 0024 6369 ldr r3, [r4, #20] + 318 0026 43F40033 orr r3, r3, #131072 + 319 002a 6361 str r3, [r4, #20] + 164:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 320 .loc 1 164 5 view .LVU72 + 321 002c 6369 ldr r3, [r4, #20] + 322 002e 03F40033 and r3, r3, #131072 + 323 0032 0093 str r3, [sp] + 164:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 324 .loc 1 164 5 view .LVU73 + 325 0034 009B ldr r3, [sp] + 326 .LBE6: + 164:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 327 .loc 1 164 5 view .LVU74 + ARM GAS /tmp/ccBY67LK.s page 11 + + + 165:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 328 .loc 1 165 5 view .LVU75 + 329 .LBB7: + 165:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 330 .loc 1 165 5 view .LVU76 + 165:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 331 .loc 1 165 5 view .LVU77 + 332 0036 6369 ldr r3, [r4, #20] + 333 0038 43F48023 orr r3, r3, #262144 + 334 003c 6361 str r3, [r4, #20] + 165:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 335 .loc 1 165 5 view .LVU78 + 336 003e 6369 ldr r3, [r4, #20] + 337 0040 03F48023 and r3, r3, #262144 + 338 0044 0193 str r3, [sp, #4] + 165:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 339 .loc 1 165 5 view .LVU79 + 340 0046 019B ldr r3, [sp, #4] + 341 .LBE7: + 165:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 342 .loc 1 165 5 view .LVU80 + 170:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 343 .loc 1 170 5 view .LVU81 + 170:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 344 .loc 1 170 25 is_stmt 0 view .LVU82 + 345 0048 4FF40043 mov r3, #32768 + 346 004c 0593 str r3, [sp, #20] + 171:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 347 .loc 1 171 5 is_stmt 1 view .LVU83 + 171:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 348 .loc 1 171 26 is_stmt 0 view .LVU84 + 349 004e 1227 movs r7, #18 + 350 0050 0697 str r7, [sp, #24] + 172:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 351 .loc 1 172 5 is_stmt 1 view .LVU85 + 173:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 352 .loc 1 173 5 view .LVU86 + 173:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 353 .loc 1 173 27 is_stmt 0 view .LVU87 + 354 0052 0326 movs r6, #3 + 355 0054 0896 str r6, [sp, #32] + 174:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SCL_GPIO_Port, &GPIO_InitStruct); + 356 .loc 1 174 5 is_stmt 1 view .LVU88 + 174:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SCL_GPIO_Port, &GPIO_InitStruct); + 357 .loc 1 174 31 is_stmt 0 view .LVU89 + 358 0056 0425 movs r5, #4 + 359 0058 0995 str r5, [sp, #36] + 175:Core/Src/stm32f3xx_hal_msp.c **** + 360 .loc 1 175 5 is_stmt 1 view .LVU90 + 361 005a 05A9 add r1, sp, #20 + 362 005c 4FF09040 mov r0, #1207959552 + 363 .LVL16: + 175:Core/Src/stm32f3xx_hal_msp.c **** + 364 .loc 1 175 5 is_stmt 0 view .LVU91 + 365 0060 FFF7FEFF bl HAL_GPIO_Init + 366 .LVL17: + 177:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + ARM GAS /tmp/ccBY67LK.s page 12 + + + 367 .loc 1 177 5 is_stmt 1 view .LVU92 + 177:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 368 .loc 1 177 25 is_stmt 0 view .LVU93 + 369 0064 8023 movs r3, #128 + 370 0066 0593 str r3, [sp, #20] + 178:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 371 .loc 1 178 5 is_stmt 1 view .LVU94 + 178:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 372 .loc 1 178 26 is_stmt 0 view .LVU95 + 373 0068 0697 str r7, [sp, #24] + 179:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 374 .loc 1 179 5 is_stmt 1 view .LVU96 + 179:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 375 .loc 1 179 26 is_stmt 0 view .LVU97 + 376 006a 0023 movs r3, #0 + 377 006c 0793 str r3, [sp, #28] + 180:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 378 .loc 1 180 5 is_stmt 1 view .LVU98 + 180:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 379 .loc 1 180 27 is_stmt 0 view .LVU99 + 380 006e 0896 str r6, [sp, #32] + 181:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SDA_GPIO_Port, &GPIO_InitStruct); + 381 .loc 1 181 5 is_stmt 1 view .LVU100 + 181:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SDA_GPIO_Port, &GPIO_InitStruct); + 382 .loc 1 181 31 is_stmt 0 view .LVU101 + 383 0070 0995 str r5, [sp, #36] + 182:Core/Src/stm32f3xx_hal_msp.c **** + 384 .loc 1 182 5 is_stmt 1 view .LVU102 + 385 0072 05A9 add r1, sp, #20 + 386 0074 1A48 ldr r0, .L23+12 + 387 0076 FFF7FEFF bl HAL_GPIO_Init + 388 .LVL18: + 185:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 389 .loc 1 185 5 view .LVU103 + 390 .LBB8: + 185:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 391 .loc 1 185 5 view .LVU104 + 185:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 392 .loc 1 185 5 view .LVU105 + 393 007a E369 ldr r3, [r4, #28] + 394 007c 43F40013 orr r3, r3, #2097152 + 395 0080 E361 str r3, [r4, #28] + 185:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 396 .loc 1 185 5 view .LVU106 + 397 0082 E369 ldr r3, [r4, #28] + 398 0084 03F40013 and r3, r3, #2097152 + 399 0088 0293 str r3, [sp, #8] + 185:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 400 .loc 1 185 5 view .LVU107 + 401 008a 029B ldr r3, [sp, #8] + 402 .LBE8: + 185:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 403 .loc 1 185 5 view .LVU108 + 404 008c C7E7 b .L17 + 405 .LVL19: + 406 .L22: + 196:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + ARM GAS /tmp/ccBY67LK.s page 13 + + + 407 .loc 1 196 5 view .LVU109 + 408 .LBB9: + 196:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 409 .loc 1 196 5 view .LVU110 + 196:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 410 .loc 1 196 5 view .LVU111 + 411 008e 134C ldr r4, .L23+8 + 412 0090 6369 ldr r3, [r4, #20] + 413 0092 43F40033 orr r3, r3, #131072 + 414 0096 6361 str r3, [r4, #20] + 196:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 415 .loc 1 196 5 view .LVU112 + 416 0098 6369 ldr r3, [r4, #20] + 417 009a 03F40033 and r3, r3, #131072 + 418 009e 0393 str r3, [sp, #12] + 196:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 419 .loc 1 196 5 view .LVU113 + 420 00a0 039B ldr r3, [sp, #12] + 421 .LBE9: + 196:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 422 .loc 1 196 5 view .LVU114 + 201:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 423 .loc 1 201 5 view .LVU115 + 201:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 424 .loc 1 201 25 is_stmt 0 view .LVU116 + 425 00a2 4FF4C063 mov r3, #1536 + 426 00a6 0593 str r3, [sp, #20] + 202:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 427 .loc 1 202 5 is_stmt 1 view .LVU117 + 202:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 428 .loc 1 202 26 is_stmt 0 view .LVU118 + 429 00a8 1223 movs r3, #18 + 430 00aa 0693 str r3, [sp, #24] + 203:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 431 .loc 1 203 5 is_stmt 1 view .LVU119 + 204:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + 432 .loc 1 204 5 view .LVU120 + 204:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + 433 .loc 1 204 27 is_stmt 0 view .LVU121 + 434 00ac 0323 movs r3, #3 + 435 00ae 0893 str r3, [sp, #32] + 205:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 436 .loc 1 205 5 is_stmt 1 view .LVU122 + 205:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 437 .loc 1 205 31 is_stmt 0 view .LVU123 + 438 00b0 0423 movs r3, #4 + 439 00b2 0993 str r3, [sp, #36] + 206:Core/Src/stm32f3xx_hal_msp.c **** + 440 .loc 1 206 5 is_stmt 1 view .LVU124 + 441 00b4 05A9 add r1, sp, #20 + 442 00b6 4FF09040 mov r0, #1207959552 + 443 .LVL20: + 206:Core/Src/stm32f3xx_hal_msp.c **** + 444 .loc 1 206 5 is_stmt 0 view .LVU125 + 445 00ba FFF7FEFF bl HAL_GPIO_Init + 446 .LVL21: + 209:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + ARM GAS /tmp/ccBY67LK.s page 14 + + + 447 .loc 1 209 5 is_stmt 1 view .LVU126 + 448 .LBB10: + 209:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 449 .loc 1 209 5 view .LVU127 + 209:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 450 .loc 1 209 5 view .LVU128 + 451 00be E369 ldr r3, [r4, #28] + 452 00c0 43F48003 orr r3, r3, #4194304 + 453 00c4 E361 str r3, [r4, #28] + 209:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 454 .loc 1 209 5 view .LVU129 + 455 00c6 E369 ldr r3, [r4, #28] + 456 00c8 03F48003 and r3, r3, #4194304 + 457 00cc 0493 str r3, [sp, #16] + 209:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 458 .loc 1 209 5 view .LVU130 + 459 00ce 049B ldr r3, [sp, #16] + 460 .LBE10: + 209:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 461 .loc 1 209 5 view .LVU131 + 462 .loc 1 215 1 is_stmt 0 view .LVU132 + 463 00d0 A5E7 b .L17 + 464 .L24: + 465 00d2 00BF .align 2 + 466 .L23: + 467 00d4 00540040 .word 1073763328 + 468 00d8 00580040 .word 1073764352 + 469 00dc 00100240 .word 1073876992 + 470 00e0 00040048 .word 1207960576 + 471 .cfi_endproc + 472 .LFE133: + 474 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 475 .align 1 + 476 .global HAL_I2C_MspDeInit + 477 .syntax unified + 478 .thumb + 479 .thumb_func + 481 HAL_I2C_MspDeInit: + 482 .LVL22: + 483 .LFB134: + 216:Core/Src/stm32f3xx_hal_msp.c **** + 217:Core/Src/stm32f3xx_hal_msp.c **** /** + 218:Core/Src/stm32f3xx_hal_msp.c **** * @brief I2C MSP De-Initialization + 219:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 220:Core/Src/stm32f3xx_hal_msp.c **** * @param hi2c: I2C handle pointer + 221:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 222:Core/Src/stm32f3xx_hal_msp.c **** */ + 223:Core/Src/stm32f3xx_hal_msp.c **** void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) + 224:Core/Src/stm32f3xx_hal_msp.c **** { + 484 .loc 1 224 1 is_stmt 1 view -0 + 485 .cfi_startproc + 486 @ args = 0, pretend = 0, frame = 0 + 487 @ frame_needed = 0, uses_anonymous_args = 0 + 488 .loc 1 224 1 is_stmt 0 view .LVU134 + 489 0000 08B5 push {r3, lr} + 490 .cfi_def_cfa_offset 8 + 491 .cfi_offset 3, -8 + ARM GAS /tmp/ccBY67LK.s page 15 + + + 492 .cfi_offset 14, -4 + 225:Core/Src/stm32f3xx_hal_msp.c **** if(hi2c->Instance==I2C1) + 493 .loc 1 225 3 is_stmt 1 view .LVU135 + 494 .loc 1 225 10 is_stmt 0 view .LVU136 + 495 0002 0368 ldr r3, [r0] + 496 .loc 1 225 5 view .LVU137 + 497 0004 154A ldr r2, .L31 + 498 0006 9342 cmp r3, r2 + 499 0008 03D0 beq .L29 + 226:Core/Src/stm32f3xx_hal_msp.c **** { + 227:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspDeInit 0 */ + 228:Core/Src/stm32f3xx_hal_msp.c **** + 229:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspDeInit 0 */ + 230:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 231:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C1_CLK_DISABLE(); + 232:Core/Src/stm32f3xx_hal_msp.c **** + 233:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 234:Core/Src/stm32f3xx_hal_msp.c **** PA15 ------> I2C1_SCL + 235:Core/Src/stm32f3xx_hal_msp.c **** PB7 ------> I2C1_SDA + 236:Core/Src/stm32f3xx_hal_msp.c **** */ + 237:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(TMP_SCL_GPIO_Port, TMP_SCL_Pin); + 238:Core/Src/stm32f3xx_hal_msp.c **** + 239:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(TMP_SDA_GPIO_Port, TMP_SDA_Pin); + 240:Core/Src/stm32f3xx_hal_msp.c **** + 241:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspDeInit 1 */ + 242:Core/Src/stm32f3xx_hal_msp.c **** + 243:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspDeInit 1 */ + 244:Core/Src/stm32f3xx_hal_msp.c **** } + 245:Core/Src/stm32f3xx_hal_msp.c **** else if(hi2c->Instance==I2C2) + 500 .loc 1 245 8 is_stmt 1 view .LVU138 + 501 .loc 1 245 10 is_stmt 0 view .LVU139 + 502 000a 154A ldr r2, .L31+4 + 503 000c 9342 cmp r3, r2 + 504 000e 11D0 beq .L30 + 505 .LVL23: + 506 .L25: + 246:Core/Src/stm32f3xx_hal_msp.c **** { + 247:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 0 */ + 248:Core/Src/stm32f3xx_hal_msp.c **** + 249:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 0 */ + 250:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 251:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_DISABLE(); + 252:Core/Src/stm32f3xx_hal_msp.c **** + 253:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 254:Core/Src/stm32f3xx_hal_msp.c **** PA9 ------> I2C2_SCL + 255:Core/Src/stm32f3xx_hal_msp.c **** PA10 ------> I2C2_SDA + 256:Core/Src/stm32f3xx_hal_msp.c **** */ + 257:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9); + 258:Core/Src/stm32f3xx_hal_msp.c **** + 259:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10); + 260:Core/Src/stm32f3xx_hal_msp.c **** + 261:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 1 */ + 262:Core/Src/stm32f3xx_hal_msp.c **** + 263:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 1 */ + 264:Core/Src/stm32f3xx_hal_msp.c **** } + 265:Core/Src/stm32f3xx_hal_msp.c **** + 266:Core/Src/stm32f3xx_hal_msp.c **** } + ARM GAS /tmp/ccBY67LK.s page 16 + + + 507 .loc 1 266 1 view .LVU140 + 508 0010 08BD pop {r3, pc} + 509 .LVL24: + 510 .L29: + 231:Core/Src/stm32f3xx_hal_msp.c **** + 511 .loc 1 231 5 is_stmt 1 view .LVU141 + 512 0012 02F5DE32 add r2, r2, #113664 + 513 0016 D369 ldr r3, [r2, #28] + 514 0018 23F40013 bic r3, r3, #2097152 + 515 001c D361 str r3, [r2, #28] + 237:Core/Src/stm32f3xx_hal_msp.c **** + 516 .loc 1 237 5 view .LVU142 + 517 001e 4FF40041 mov r1, #32768 + 518 0022 4FF09040 mov r0, #1207959552 + 519 .LVL25: + 237:Core/Src/stm32f3xx_hal_msp.c **** + 520 .loc 1 237 5 is_stmt 0 view .LVU143 + 521 0026 FFF7FEFF bl HAL_GPIO_DeInit + 522 .LVL26: + 239:Core/Src/stm32f3xx_hal_msp.c **** + 523 .loc 1 239 5 is_stmt 1 view .LVU144 + 524 002a 8021 movs r1, #128 + 525 002c 0D48 ldr r0, .L31+8 + 526 002e FFF7FEFF bl HAL_GPIO_DeInit + 527 .LVL27: + 528 0032 EDE7 b .L25 + 529 .LVL28: + 530 .L30: + 251:Core/Src/stm32f3xx_hal_msp.c **** + 531 .loc 1 251 5 view .LVU145 + 532 0034 02F5DC32 add r2, r2, #112640 + 533 0038 D369 ldr r3, [r2, #28] + 534 003a 23F48003 bic r3, r3, #4194304 + 535 003e D361 str r3, [r2, #28] + 257:Core/Src/stm32f3xx_hal_msp.c **** + 536 .loc 1 257 5 view .LVU146 + 537 0040 4FF40071 mov r1, #512 + 538 0044 4FF09040 mov r0, #1207959552 + 539 .LVL29: + 257:Core/Src/stm32f3xx_hal_msp.c **** + 540 .loc 1 257 5 is_stmt 0 view .LVU147 + 541 0048 FFF7FEFF bl HAL_GPIO_DeInit + 542 .LVL30: + 259:Core/Src/stm32f3xx_hal_msp.c **** + 543 .loc 1 259 5 is_stmt 1 view .LVU148 + 544 004c 4FF48061 mov r1, #1024 + 545 0050 4FF09040 mov r0, #1207959552 + 546 0054 FFF7FEFF bl HAL_GPIO_DeInit + 547 .LVL31: + 548 .loc 1 266 1 is_stmt 0 view .LVU149 + 549 0058 DAE7 b .L25 + 550 .L32: + 551 005a 00BF .align 2 + 552 .L31: + 553 005c 00540040 .word 1073763328 + 554 0060 00580040 .word 1073764352 + 555 0064 00040048 .word 1207960576 + ARM GAS /tmp/ccBY67LK.s page 17 + + + 556 .cfi_endproc + 557 .LFE134: + 559 .section .text.HAL_SPI_MspInit,"ax",%progbits + 560 .align 1 + 561 .global HAL_SPI_MspInit + 562 .syntax unified + 563 .thumb + 564 .thumb_func + 566 HAL_SPI_MspInit: + 567 .LVL32: + 568 .LFB135: + 267:Core/Src/stm32f3xx_hal_msp.c **** + 268:Core/Src/stm32f3xx_hal_msp.c **** /** + 269:Core/Src/stm32f3xx_hal_msp.c **** * @brief SPI MSP Initialization + 270:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example + 271:Core/Src/stm32f3xx_hal_msp.c **** * @param hspi: SPI handle pointer + 272:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 273:Core/Src/stm32f3xx_hal_msp.c **** */ + 274:Core/Src/stm32f3xx_hal_msp.c **** void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) + 275:Core/Src/stm32f3xx_hal_msp.c **** { + 569 .loc 1 275 1 is_stmt 1 view -0 + 570 .cfi_startproc + 571 @ args = 0, pretend = 0, frame = 32 + 572 @ frame_needed = 0, uses_anonymous_args = 0 + 573 .loc 1 275 1 is_stmt 0 view .LVU151 + 574 0000 00B5 push {lr} + 575 .cfi_def_cfa_offset 4 + 576 .cfi_offset 14, -4 + 577 0002 89B0 sub sp, sp, #36 + 578 .cfi_def_cfa_offset 40 + 276:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 579 .loc 1 276 3 is_stmt 1 view .LVU152 + 580 .loc 1 276 20 is_stmt 0 view .LVU153 + 581 0004 0023 movs r3, #0 + 582 0006 0393 str r3, [sp, #12] + 583 0008 0493 str r3, [sp, #16] + 584 000a 0593 str r3, [sp, #20] + 585 000c 0693 str r3, [sp, #24] + 586 000e 0793 str r3, [sp, #28] + 277:Core/Src/stm32f3xx_hal_msp.c **** if(hspi->Instance==SPI1) + 587 .loc 1 277 3 is_stmt 1 view .LVU154 + 588 .loc 1 277 10 is_stmt 0 view .LVU155 + 589 0010 0268 ldr r2, [r0] + 590 .loc 1 277 5 view .LVU156 + 591 0012 144B ldr r3, .L37 + 592 0014 9A42 cmp r2, r3 + 593 0016 02D0 beq .L36 + 594 .LVL33: + 595 .L33: + 278:Core/Src/stm32f3xx_hal_msp.c **** { + 279:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspInit 0 */ + 280:Core/Src/stm32f3xx_hal_msp.c **** + 281:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspInit 0 */ + 282:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 283:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_SPI1_CLK_ENABLE(); + 284:Core/Src/stm32f3xx_hal_msp.c **** + 285:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + ARM GAS /tmp/ccBY67LK.s page 18 + + + 286:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 287:Core/Src/stm32f3xx_hal_msp.c **** PA5 ------> SPI1_SCK + 288:Core/Src/stm32f3xx_hal_msp.c **** PA6 ------> SPI1_MISO + 289:Core/Src/stm32f3xx_hal_msp.c **** PA7 ------> SPI1_MOSI + 290:Core/Src/stm32f3xx_hal_msp.c **** */ + 291:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 292:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 293:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 294:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 295:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 296:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 297:Core/Src/stm32f3xx_hal_msp.c **** + 298:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspInit 1 */ + 299:Core/Src/stm32f3xx_hal_msp.c **** + 300:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspInit 1 */ + 301:Core/Src/stm32f3xx_hal_msp.c **** } + 302:Core/Src/stm32f3xx_hal_msp.c **** + 303:Core/Src/stm32f3xx_hal_msp.c **** } + 596 .loc 1 303 1 view .LVU157 + 597 0018 09B0 add sp, sp, #36 + 598 .cfi_remember_state + 599 .cfi_def_cfa_offset 4 + 600 @ sp needed + 601 001a 5DF804FB ldr pc, [sp], #4 + 602 .LVL34: + 603 .L36: + 604 .cfi_restore_state + 283:Core/Src/stm32f3xx_hal_msp.c **** + 605 .loc 1 283 5 is_stmt 1 view .LVU158 + 606 .LBB11: + 283:Core/Src/stm32f3xx_hal_msp.c **** + 607 .loc 1 283 5 view .LVU159 + 283:Core/Src/stm32f3xx_hal_msp.c **** + 608 .loc 1 283 5 view .LVU160 + 609 001e 03F56043 add r3, r3, #57344 + 610 0022 9A69 ldr r2, [r3, #24] + 611 0024 42F48052 orr r2, r2, #4096 + 612 0028 9A61 str r2, [r3, #24] + 283:Core/Src/stm32f3xx_hal_msp.c **** + 613 .loc 1 283 5 view .LVU161 + 614 002a 9A69 ldr r2, [r3, #24] + 615 002c 02F48052 and r2, r2, #4096 + 616 0030 0192 str r2, [sp, #4] + 283:Core/Src/stm32f3xx_hal_msp.c **** + 617 .loc 1 283 5 view .LVU162 + 618 0032 019A ldr r2, [sp, #4] + 619 .LBE11: + 283:Core/Src/stm32f3xx_hal_msp.c **** + 620 .loc 1 283 5 view .LVU163 + 285:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 621 .loc 1 285 5 view .LVU164 + 622 .LBB12: + 285:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 623 .loc 1 285 5 view .LVU165 + 285:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 624 .loc 1 285 5 view .LVU166 + 625 0034 5A69 ldr r2, [r3, #20] + ARM GAS /tmp/ccBY67LK.s page 19 + + + 626 0036 42F40032 orr r2, r2, #131072 + 627 003a 5A61 str r2, [r3, #20] + 285:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 628 .loc 1 285 5 view .LVU167 + 629 003c 5B69 ldr r3, [r3, #20] + 630 003e 03F40033 and r3, r3, #131072 + 631 0042 0293 str r3, [sp, #8] + 285:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 632 .loc 1 285 5 view .LVU168 + 633 0044 029B ldr r3, [sp, #8] + 634 .LBE12: + 285:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 635 .loc 1 285 5 view .LVU169 + 291:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 636 .loc 1 291 5 view .LVU170 + 291:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 637 .loc 1 291 25 is_stmt 0 view .LVU171 + 638 0046 E023 movs r3, #224 + 639 0048 0393 str r3, [sp, #12] + 292:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 640 .loc 1 292 5 is_stmt 1 view .LVU172 + 292:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 641 .loc 1 292 26 is_stmt 0 view .LVU173 + 642 004a 0223 movs r3, #2 + 643 004c 0493 str r3, [sp, #16] + 293:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 644 .loc 1 293 5 is_stmt 1 view .LVU174 + 294:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 645 .loc 1 294 5 view .LVU175 + 294:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 646 .loc 1 294 27 is_stmt 0 view .LVU176 + 647 004e 0323 movs r3, #3 + 648 0050 0693 str r3, [sp, #24] + 295:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 649 .loc 1 295 5 is_stmt 1 view .LVU177 + 295:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 650 .loc 1 295 31 is_stmt 0 view .LVU178 + 651 0052 0523 movs r3, #5 + 652 0054 0793 str r3, [sp, #28] + 296:Core/Src/stm32f3xx_hal_msp.c **** + 653 .loc 1 296 5 is_stmt 1 view .LVU179 + 654 0056 03A9 add r1, sp, #12 + 655 0058 4FF09040 mov r0, #1207959552 + 656 .LVL35: + 296:Core/Src/stm32f3xx_hal_msp.c **** + 657 .loc 1 296 5 is_stmt 0 view .LVU180 + 658 005c FFF7FEFF bl HAL_GPIO_Init + 659 .LVL36: + 660 .loc 1 303 1 view .LVU181 + 661 0060 DAE7 b .L33 + 662 .L38: + 663 0062 00BF .align 2 + 664 .L37: + 665 0064 00300140 .word 1073819648 + 666 .cfi_endproc + 667 .LFE135: + 669 .section .text.HAL_SPI_MspDeInit,"ax",%progbits + ARM GAS /tmp/ccBY67LK.s page 20 + + + 670 .align 1 + 671 .global HAL_SPI_MspDeInit + 672 .syntax unified + 673 .thumb + 674 .thumb_func + 676 HAL_SPI_MspDeInit: + 677 .LVL37: + 678 .LFB136: + 304:Core/Src/stm32f3xx_hal_msp.c **** + 305:Core/Src/stm32f3xx_hal_msp.c **** /** + 306:Core/Src/stm32f3xx_hal_msp.c **** * @brief SPI MSP De-Initialization + 307:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 308:Core/Src/stm32f3xx_hal_msp.c **** * @param hspi: SPI handle pointer + 309:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 310:Core/Src/stm32f3xx_hal_msp.c **** */ + 311:Core/Src/stm32f3xx_hal_msp.c **** void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) + 312:Core/Src/stm32f3xx_hal_msp.c **** { + 679 .loc 1 312 1 is_stmt 1 view -0 + 680 .cfi_startproc + 681 @ args = 0, pretend = 0, frame = 0 + 682 @ frame_needed = 0, uses_anonymous_args = 0 + 683 .loc 1 312 1 is_stmt 0 view .LVU183 + 684 0000 08B5 push {r3, lr} + 685 .cfi_def_cfa_offset 8 + 686 .cfi_offset 3, -8 + 687 .cfi_offset 14, -4 + 313:Core/Src/stm32f3xx_hal_msp.c **** if(hspi->Instance==SPI1) + 688 .loc 1 313 3 is_stmt 1 view .LVU184 + 689 .loc 1 313 10 is_stmt 0 view .LVU185 + 690 0002 0268 ldr r2, [r0] + 691 .loc 1 313 5 view .LVU186 + 692 0004 074B ldr r3, .L43 + 693 0006 9A42 cmp r2, r3 + 694 0008 00D0 beq .L42 + 695 .LVL38: + 696 .L39: + 314:Core/Src/stm32f3xx_hal_msp.c **** { + 315:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspDeInit 0 */ + 316:Core/Src/stm32f3xx_hal_msp.c **** + 317:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspDeInit 0 */ + 318:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 319:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_SPI1_CLK_DISABLE(); + 320:Core/Src/stm32f3xx_hal_msp.c **** + 321:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 322:Core/Src/stm32f3xx_hal_msp.c **** PA5 ------> SPI1_SCK + 323:Core/Src/stm32f3xx_hal_msp.c **** PA6 ------> SPI1_MISO + 324:Core/Src/stm32f3xx_hal_msp.c **** PA7 ------> SPI1_MOSI + 325:Core/Src/stm32f3xx_hal_msp.c **** */ + 326:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + 327:Core/Src/stm32f3xx_hal_msp.c **** + 328:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspDeInit 1 */ + 329:Core/Src/stm32f3xx_hal_msp.c **** + 330:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspDeInit 1 */ + 331:Core/Src/stm32f3xx_hal_msp.c **** } + 332:Core/Src/stm32f3xx_hal_msp.c **** + 333:Core/Src/stm32f3xx_hal_msp.c **** } + 697 .loc 1 333 1 view .LVU187 + ARM GAS /tmp/ccBY67LK.s page 21 + + + 698 000a 08BD pop {r3, pc} + 699 .LVL39: + 700 .L42: + 319:Core/Src/stm32f3xx_hal_msp.c **** + 701 .loc 1 319 5 is_stmt 1 view .LVU188 + 702 000c 064A ldr r2, .L43+4 + 703 000e 9369 ldr r3, [r2, #24] + 704 0010 23F48053 bic r3, r3, #4096 + 705 0014 9361 str r3, [r2, #24] + 326:Core/Src/stm32f3xx_hal_msp.c **** + 706 .loc 1 326 5 view .LVU189 + 707 0016 E021 movs r1, #224 + 708 0018 4FF09040 mov r0, #1207959552 + 709 .LVL40: + 326:Core/Src/stm32f3xx_hal_msp.c **** + 710 .loc 1 326 5 is_stmt 0 view .LVU190 + 711 001c FFF7FEFF bl HAL_GPIO_DeInit + 712 .LVL41: + 713 .loc 1 333 1 view .LVU191 + 714 0020 F3E7 b .L39 + 715 .L44: + 716 0022 00BF .align 2 + 717 .L43: + 718 0024 00300140 .word 1073819648 + 719 0028 00100240 .word 1073876992 + 720 .cfi_endproc + 721 .LFE136: + 723 .text + 724 .Letext0: + 725 .file 2 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 726 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 727 .file 4 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 728 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 729 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 730 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 731 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 732 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 733 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + 734 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 735 .file 12 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h" + ARM GAS /tmp/ccBY67LK.s page 22 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_msp.c + /tmp/ccBY67LK.s:21 .text.HAL_MspInit:0000000000000000 $t + /tmp/ccBY67LK.s:27 .text.HAL_MspInit:0000000000000000 HAL_MspInit + /tmp/ccBY67LK.s:75 .text.HAL_MspInit:000000000000002c $d + /tmp/ccBY67LK.s:80 .text.HAL_CAN_MspInit:0000000000000000 $t + /tmp/ccBY67LK.s:86 .text.HAL_CAN_MspInit:0000000000000000 HAL_CAN_MspInit + /tmp/ccBY67LK.s:195 .text.HAL_CAN_MspInit:0000000000000074 $d + /tmp/ccBY67LK.s:200 .text.HAL_CAN_MspDeInit:0000000000000000 $t + /tmp/ccBY67LK.s:206 .text.HAL_CAN_MspDeInit:0000000000000000 HAL_CAN_MspDeInit + /tmp/ccBY67LK.s:252 .text.HAL_CAN_MspDeInit:000000000000002c $d + /tmp/ccBY67LK.s:258 .text.HAL_I2C_MspInit:0000000000000000 $t + /tmp/ccBY67LK.s:264 .text.HAL_I2C_MspInit:0000000000000000 HAL_I2C_MspInit + /tmp/ccBY67LK.s:467 .text.HAL_I2C_MspInit:00000000000000d4 $d + /tmp/ccBY67LK.s:475 .text.HAL_I2C_MspDeInit:0000000000000000 $t + /tmp/ccBY67LK.s:481 .text.HAL_I2C_MspDeInit:0000000000000000 HAL_I2C_MspDeInit + /tmp/ccBY67LK.s:553 .text.HAL_I2C_MspDeInit:000000000000005c $d + /tmp/ccBY67LK.s:560 .text.HAL_SPI_MspInit:0000000000000000 $t + /tmp/ccBY67LK.s:566 .text.HAL_SPI_MspInit:0000000000000000 HAL_SPI_MspInit + /tmp/ccBY67LK.s:665 .text.HAL_SPI_MspInit:0000000000000064 $d + /tmp/ccBY67LK.s:670 .text.HAL_SPI_MspDeInit:0000000000000000 $t + /tmp/ccBY67LK.s:676 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    © Copyright (c) 2016 STMicroelectronics. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * All rights reserved.
    + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license, + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * License. You may obtain a copy of the License at: + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ****************************************************************************** + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #include "stm32f3xx_hal.h" + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @addtogroup STM32F3xx_HAL_Driver + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + ARM GAS /tmp/ccVidTYQ.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Initialization and de-initialization functions + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================================================== + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================================================== + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** write accesses. + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values. + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DeInit(void) + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 29 .loc 1 76 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); + 34 .loc 1 77 3 view .LVU1 + 35 0000 044B ldr r3, .L2 + 36 0002 1A69 ldr r2, [r3, #16] + 37 0004 42F08052 orr r2, r2, #268435456 + 38 0008 1A61 str r2, [r3, #16] + ARM GAS /tmp/ccVidTYQ.s page 3 + + + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); + 39 .loc 1 78 3 view .LVU2 + 40 000a 1A69 ldr r2, [r3, #16] + 41 000c 22F08052 bic r2, r2, #268435456 + 42 0010 1A61 str r2, [r3, #16] + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 43 .loc 1 79 1 is_stmt 0 view .LVU3 + 44 0012 7047 bx lr + 45 .L3: + 46 .align 2 + 47 .L2: + 48 0014 00100240 .word 1073876992 + 49 .cfi_endproc + 50 .LFE130: + 52 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits + 53 .align 1 + 54 .global HAL_PWR_EnableBkUpAccess + 55 .syntax unified + 56 .thumb + 57 .thumb_func + 59 HAL_PWR_EnableBkUpAccess: + 60 .LFB131: + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM). + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 61 .loc 1 89 1 is_stmt 1 view -0 + 62 .cfi_startproc + 63 @ args = 0, pretend = 0, frame = 0 + 64 @ frame_needed = 0, uses_anonymous_args = 0 + 65 @ link register save eliminated. + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 66 .loc 1 90 3 view .LVU5 + 67 0000 024A ldr r2, .L5 + 68 0002 1368 ldr r3, [r2] + 69 0004 43F48073 orr r3, r3, #256 + 70 0008 1360 str r3, [r2] + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 71 .loc 1 91 1 is_stmt 0 view .LVU6 + 72 000a 7047 bx lr + 73 .L6: + 74 .align 2 + 75 .L5: + 76 000c 00700040 .word 1073770496 + 77 .cfi_endproc + 78 .LFE131: + 80 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits + 81 .align 1 + 82 .global HAL_PWR_DisableBkUpAccess + 83 .syntax unified + 84 .thumb + ARM GAS /tmp/ccVidTYQ.s page 4 + + + 85 .thumb_func + 87 HAL_PWR_DisableBkUpAccess: + 88 .LFB132: + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM). + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 89 .loc 1 101 1 is_stmt 1 view -0 + 90 .cfi_startproc + 91 @ args = 0, pretend = 0, frame = 0 + 92 @ frame_needed = 0, uses_anonymous_args = 0 + 93 @ link register save eliminated. + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP); + 94 .loc 1 102 3 view .LVU8 + 95 0000 024A ldr r2, .L8 + 96 0002 1368 ldr r3, [r2] + 97 0004 23F48073 bic r3, r3, #256 + 98 0008 1360 str r3, [r2] + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 99 .loc 1 103 1 is_stmt 0 view .LVU9 + 100 000a 7047 bx lr + 101 .L9: + 102 .align 2 + 103 .L8: + 104 000c 00700040 .word 1073770496 + 105 .cfi_endproc + 106 .LFE132: + 108 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits + 109 .align 1 + 110 .global HAL_PWR_EnableWakeUpPin + 111 .syntax unified + 112 .thumb + 113 .thumb_func + 115 HAL_PWR_EnableWakeUpPin: + 116 .LVL0: + 117 .LFB133: + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @} + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Low Power modes configuration functions + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================================================== + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Peripheral Control functions ##### + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================================================== + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** WakeUp pin configuration *** + ARM GAS /tmp/ccVidTYQ.s page 5 + + + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================ + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** forced in input pull down configuration and is active on rising edges. + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) There are up to three WakeUp pins: + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 1 on PA.00. + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only). + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 3 on PE.06. + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Main and Backup Regulators configuration *** + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================================ + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** save battery life. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** protected to prevent confidential data, such as cryptographic private + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** key, from being accessed. The backup SRAM can be erased only through + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the Flash interface when a protection level change from level 1 to + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** level 0 is requested. + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** -@- Refer to the description of Read protection (RDP) in the Flash + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programming manual. + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Refer to the datasheets for more details. + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Low Power modes configuration *** + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===================================== + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The devices feature 3 low-power modes: + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** in low power mode + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices). + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Sleep mode *** + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================== + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry: + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** functions with + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit: + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Stop mode *** + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================= + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** are preserved. + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode to minimize the co + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry: + ARM GAS /tmp/ccVidTYQ.s page 6 + + + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** function with: + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Main regulator ON or + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Low Power regulator ON. + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit: + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** when programmed in wakeup mode (the peripheral must be + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programmed in wakeup mode and the corresponding interrupt vector + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** must be enabled in the NVIC). + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Standby mode *** + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ==================== + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** circuitry. + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator is OFF. + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry: + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit: + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode *** + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ============================================= + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event, + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode). + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function. + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the comparator to generate the event. + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim + ARM GAS /tmp/ccVidTYQ.s page 7 + + + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality. + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be value of : + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 118 .loc 1 244 1 is_stmt 1 view -0 + 119 .cfi_startproc + 120 @ args = 0, pretend = 0, frame = 0 + 121 @ frame_needed = 0, uses_anonymous_args = 0 + 122 @ link register save eliminated. + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */ + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + 123 .loc 1 246 3 view .LVU11 + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Enable the EWUPx pin */ + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx); + 124 .loc 1 248 3 view .LVU12 + 125 0000 024A ldr r2, .L11 + 126 0002 5368 ldr r3, [r2, #4] + 127 0004 0343 orrs r3, r3, r0 + 128 0006 5360 str r3, [r2, #4] + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 129 .loc 1 249 1 is_stmt 0 view .LVU13 + 130 0008 7047 bx lr + 131 .L12: + 132 000a 00BF .align 2 + 133 .L11: + 134 000c 00700040 .word 1073770496 + 135 .cfi_endproc + 136 .LFE133: + 138 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits + 139 .align 1 + 140 .global HAL_PWR_DisableWakeUpPin + 141 .syntax unified + 142 .thumb + 143 .thumb_func + 145 HAL_PWR_DisableWakeUpPin: + 146 .LVL1: + 147 .LFB134: + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality. + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be values of : + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 148 .loc 1 259 1 is_stmt 1 view -0 + 149 .cfi_startproc + ARM GAS /tmp/ccVidTYQ.s page 8 + + + 150 @ args = 0, pretend = 0, frame = 0 + 151 @ frame_needed = 0, uses_anonymous_args = 0 + 152 @ link register save eliminated. + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */ + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + 153 .loc 1 261 3 view .LVU15 + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Disable the EWUPx pin */ + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx); + 154 .loc 1 263 3 view .LVU16 + 155 0000 024A ldr r2, .L14 + 156 0002 5368 ldr r3, [r2, #4] + 157 0004 23EA0003 bic r3, r3, r0 + 158 0008 5360 str r3, [r2, #4] + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 159 .loc 1 264 1 is_stmt 0 view .LVU17 + 160 000a 7047 bx lr + 161 .L15: + 162 .align 2 + 163 .L14: + 164 000c 00700040 .word 1073770496 + 165 .cfi_endproc + 166 .LFE134: + 168 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits + 169 .align 1 + 170 .global HAL_PWR_EnterSLEEPMode + 171 .syntax unified + 172 .thumb + 173 .thumb_func + 175 HAL_PWR_EnterSLEEPMode: + 176 .LVL2: + 177 .LFB135: + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters Sleep mode. + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode. + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values: + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note This parameter has no effect in F3 family and is just maintained to + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * offer full portability of other STM32 families softwares. + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the interrupt wake up source. + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values: + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 178 .loc 1 284 1 is_stmt 1 view -0 + 179 .cfi_startproc + 180 @ args = 0, pretend = 0, frame = 0 + 181 @ frame_needed = 0, uses_anonymous_args = 0 + 182 @ link register save eliminated. + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */ + ARM GAS /tmp/ccVidTYQ.s page 9 + + + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + 183 .loc 1 286 3 view .LVU19 + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + 184 .loc 1 289 3 view .LVU20 + 185 .loc 1 289 6 is_stmt 0 view .LVU21 + 186 0000 064A ldr r2, .L20 + 187 0002 1369 ldr r3, [r2, #16] + 188 .loc 1 289 12 view .LVU22 + 189 0004 23F00403 bic r3, r3, #4 + 190 0008 1361 str r3, [r2, #16] + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + 191 .loc 1 292 3 is_stmt 1 view .LVU23 + 192 .loc 1 292 5 is_stmt 0 view .LVU24 + 193 000a 0129 cmp r1, #1 + 194 000c 03D0 beq .L19 + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI(); + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */ + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV(); + 195 .loc 1 300 5 is_stmt 1 view .LVU25 + 196 .syntax unified + 197 @ 300 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 198 000e 40BF sev + 199 @ 0 "" 2 + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 200 .loc 1 301 5 view .LVU26 + 201 @ 301 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 202 0010 20BF wfe + 203 @ 0 "" 2 + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 204 .loc 1 302 5 view .LVU27 + 205 @ 302 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 206 0012 20BF wfe + 207 @ 0 "" 2 + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 208 .loc 1 304 1 is_stmt 0 view .LVU28 + 209 .thumb + 210 .syntax unified + 211 0014 7047 bx lr + 212 .L19: + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 213 .loc 1 295 5 is_stmt 1 view .LVU29 + 214 .syntax unified + 215 @ 295 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 216 0016 30BF wfi + 217 @ 0 "" 2 + 218 .thumb + 219 .syntax unified + ARM GAS /tmp/ccVidTYQ.s page 10 + + + 220 0018 7047 bx lr + 221 .L21: + 222 001a 00BF .align 2 + 223 .L20: + 224 001c 00ED00E0 .word -536810240 + 225 .cfi_endproc + 226 .LFE135: + 228 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits + 229 .align 1 + 230 .global HAL_PWR_EnterSTOPMode + 231 .syntax unified + 232 .thumb + 233 .thumb_func + 235 HAL_PWR_EnterSTOPMode: + 236 .LVL3: + 237 .LFB136: + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STOP mode. + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock. + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * is higher although the startup time is reduced. + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in STOP mode. + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values: + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values: + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 238 .loc 1 326 1 view -0 + 239 .cfi_startproc + 240 @ args = 0, pretend = 0, frame = 0 + 241 @ frame_needed = 0, uses_anonymous_args = 0 + 242 @ link register save eliminated. + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** uint32_t tmpreg = 0U; + 243 .loc 1 327 3 view .LVU31 + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */ + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); + 244 .loc 1 330 3 view .LVU32 + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + 245 .loc 1 331 3 view .LVU33 + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select the regulator state in STOP mode ---------------------------------*/ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg = PWR->CR; + 246 .loc 1 334 3 view .LVU34 + 247 .loc 1 334 10 is_stmt 0 view .LVU35 + 248 0000 0B4A ldr r2, .L26 + ARM GAS /tmp/ccVidTYQ.s page 11 + + + 249 0002 1368 ldr r3, [r2] + 250 .LVL4: + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */ + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); + 251 .loc 1 337 3 is_stmt 1 view .LVU36 + 252 .loc 1 337 10 is_stmt 0 view .LVU37 + 253 0004 23F00303 bic r3, r3, #3 + 254 .LVL5: + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set LPDS bit according to Regulator value */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg |= Regulator; + 255 .loc 1 340 3 is_stmt 1 view .LVU38 + 256 .loc 1 340 10 is_stmt 0 view .LVU39 + 257 0008 0343 orrs r3, r3, r0 + 258 .LVL6: + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Store the new value */ + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR = tmpreg; + 259 .loc 1 343 3 is_stmt 1 view .LVU40 + 260 .loc 1 343 11 is_stmt 0 view .LVU41 + 261 000a 1360 str r3, [r2] + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + 262 .loc 1 346 3 is_stmt 1 view .LVU42 + 263 .loc 1 346 6 is_stmt 0 view .LVU43 + 264 000c 094A ldr r2, .L26+4 + 265 000e 1369 ldr r3, [r2, #16] + 266 .LVL7: + 267 .loc 1 346 12 view .LVU44 + 268 0010 43F00403 orr r3, r3, #4 + 269 0014 1361 str r3, [r2, #16] + 270 .LVL8: + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STOP mode entry --------------------------------------------------*/ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) + 271 .loc 1 349 3 is_stmt 1 view .LVU45 + 272 .loc 1 349 5 is_stmt 0 view .LVU46 + 273 0016 0129 cmp r1, #1 + 274 0018 08D0 beq .L25 + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI(); + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */ + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV(); + 275 .loc 1 357 5 is_stmt 1 view .LVU47 + 276 .syntax unified + 277 @ 357 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 278 001a 40BF sev + 279 @ 0 "" 2 + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 280 .loc 1 358 5 view .LVU48 + 281 @ 358 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + ARM GAS /tmp/ccVidTYQ.s page 12 + + + 282 001c 20BF wfe + 283 @ 0 "" 2 + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 284 .loc 1 359 5 view .LVU49 + 285 @ 359 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 286 001e 20BF wfe + 287 @ 0 "" 2 + 288 .thumb + 289 .syntax unified + 290 .L24: + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + 291 .loc 1 363 3 view .LVU50 + 292 .loc 1 363 6 is_stmt 0 view .LVU51 + 293 0020 044A ldr r2, .L26+4 + 294 0022 1369 ldr r3, [r2, #16] + 295 .loc 1 363 12 view .LVU52 + 296 0024 23F00403 bic r3, r3, #4 + 297 0028 1361 str r3, [r2, #16] + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 298 .loc 1 364 1 view .LVU53 + 299 002a 7047 bx lr + 300 .L25: + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 301 .loc 1 352 5 is_stmt 1 view .LVU54 + 302 .syntax unified + 303 @ 352 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 304 002c 30BF wfi + 305 @ 0 "" 2 + 306 .thumb + 307 .syntax unified + 308 002e F7E7 b .L24 + 309 .L27: + 310 .align 2 + 311 .L26: + 312 0030 00700040 .word 1073770496 + 313 0034 00ED00E0 .word -536810240 + 314 .cfi_endproc + 315 .LFE136: + 317 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits + 318 .align 1 + 319 .global HAL_PWR_EnterSTANDBYMode + 320 .syntax unified + 321 .thumb + 322 .thumb_func + 324 HAL_PWR_EnterSTANDBYMode: + 325 .LFB137: + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STANDBY mode. + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - Reset pad (still available), + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - RTC alternate function pins if configured for tamper, time-stamp, RTC + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out, + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - WKUP pins if enabled. + ARM GAS /tmp/ccVidTYQ.s page 13 + + + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 326 .loc 1 376 1 view -0 + 327 .cfi_startproc + 328 @ args = 0, pretend = 0, frame = 0 + 329 @ frame_needed = 0, uses_anonymous_args = 0 + 330 @ link register save eliminated. + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STANDBY mode */ + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR |= PWR_CR_PDDS; + 331 .loc 1 378 3 view .LVU56 + 332 .loc 1 378 6 is_stmt 0 view .LVU57 + 333 0000 054A ldr r2, .L29 + 334 0002 1368 ldr r3, [r2] + 335 .loc 1 378 11 view .LVU58 + 336 0004 43F00203 orr r3, r3, #2 + 337 0008 1360 str r3, [r2] + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + 338 .loc 1 381 3 is_stmt 1 view .LVU59 + 339 .loc 1 381 6 is_stmt 0 view .LVU60 + 340 000a 044A ldr r2, .L29+4 + 341 000c 1369 ldr r3, [r2, #16] + 342 .loc 1 381 12 view .LVU61 + 343 000e 43F00403 orr r3, r3, #4 + 344 0012 1361 str r3, [r2, #16] + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #if defined ( __CC_ARM) + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __force_stores(); + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #endif + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI(); + 345 .loc 1 388 3 is_stmt 1 view .LVU62 + 346 .syntax unified + 347 @ 388 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 348 0014 30BF wfi + 349 @ 0 "" 2 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 350 .loc 1 389 1 is_stmt 0 view .LVU63 + 351 .thumb + 352 .syntax unified + 353 0016 7047 bx lr + 354 .L30: + 355 .align 2 + 356 .L29: + 357 0018 00700040 .word 1073770496 + 358 001c 00ED00E0 .word -536810240 + 359 .cfi_endproc + 360 .LFE137: + 362 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits + 363 .align 1 + 364 .global HAL_PWR_EnableSleepOnExit + 365 .syntax unified + 366 .thumb + ARM GAS /tmp/ccVidTYQ.s page 14 + + + 367 .thumb_func + 369 HAL_PWR_EnableSleepOnExit: + 370 .LFB138: + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * interruptions handling. + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 371 .loc 1 400 1 is_stmt 1 view -0 + 372 .cfi_startproc + 373 @ args = 0, pretend = 0, frame = 0 + 374 @ frame_needed = 0, uses_anonymous_args = 0 + 375 @ link register save eliminated. + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 376 .loc 1 402 3 view .LVU65 + 377 0000 024A ldr r2, .L32 + 378 0002 1369 ldr r3, [r2, #16] + 379 0004 43F00203 orr r3, r3, #2 + 380 0008 1361 str r3, [r2, #16] + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 381 .loc 1 403 1 is_stmt 0 view .LVU66 + 382 000a 7047 bx lr + 383 .L33: + 384 .align 2 + 385 .L32: + 386 000c 00ED00E0 .word -536810240 + 387 .cfi_endproc + 388 .LFE138: + 390 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits + 391 .align 1 + 392 .global HAL_PWR_DisableSleepOnExit + 393 .syntax unified + 394 .thumb + 395 .thumb_func + 397 HAL_PWR_DisableSleepOnExit: + 398 .LFB139: + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 399 .loc 1 413 1 is_stmt 1 view -0 + 400 .cfi_startproc + 401 @ args = 0, pretend = 0, frame = 0 + 402 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccVidTYQ.s page 15 + + + 403 @ link register save eliminated. + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 404 .loc 1 415 3 view .LVU68 + 405 0000 024A ldr r2, .L35 + 406 0002 1369 ldr r3, [r2, #16] + 407 0004 23F00203 bic r3, r3, #2 + 408 0008 1361 str r3, [r2, #16] + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 409 .loc 1 416 1 is_stmt 0 view .LVU69 + 410 000a 7047 bx lr + 411 .L36: + 412 .align 2 + 413 .L35: + 414 000c 00ED00E0 .word -536810240 + 415 .cfi_endproc + 416 .LFE139: + 418 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits + 419 .align 1 + 420 .global HAL_PWR_EnableSEVOnPend + 421 .syntax unified + 422 .thumb + 423 .thumb_func + 425 HAL_PWR_EnableSEVOnPend: + 426 .LFB140: + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit. + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 427 .loc 1 427 1 is_stmt 1 view -0 + 428 .cfi_startproc + 429 @ args = 0, pretend = 0, frame = 0 + 430 @ frame_needed = 0, uses_anonymous_args = 0 + 431 @ link register save eliminated. + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 432 .loc 1 429 3 view .LVU71 + 433 0000 024A ldr r2, .L38 + 434 0002 1369 ldr r3, [r2, #16] + 435 0004 43F01003 orr r3, r3, #16 + 436 0008 1361 str r3, [r2, #16] + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 437 .loc 1 430 1 is_stmt 0 view .LVU72 + 438 000a 7047 bx lr + 439 .L39: + 440 .align 2 + 441 .L38: + 442 000c 00ED00E0 .word -536810240 + 443 .cfi_endproc + 444 .LFE140: + ARM GAS /tmp/ccVidTYQ.s page 16 + + + 446 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits + 447 .align 1 + 448 .global HAL_PWR_DisableSEVOnPend + 449 .syntax unified + 450 .thumb + 451 .thumb_func + 453 HAL_PWR_DisableSEVOnPend: + 454 .LFB141: + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit. + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 455 .loc 1 440 1 is_stmt 1 view -0 + 456 .cfi_startproc + 457 @ args = 0, pretend = 0, frame = 0 + 458 @ frame_needed = 0, uses_anonymous_args = 0 + 459 @ link register save eliminated. + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 460 .loc 1 442 3 view .LVU74 + 461 0000 024A ldr r2, .L41 + 462 0002 1369 ldr r3, [r2, #16] + 463 0004 23F01003 bic r3, r3, #16 + 464 0008 1361 str r3, [r2, #16] + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 465 .loc 1 443 1 is_stmt 0 view .LVU75 + 466 000a 7047 bx lr + 467 .L42: + 468 .align 2 + 469 .L41: + 470 000c 00ED00E0 .word -536810240 + 471 .cfi_endproc + 472 .LFE141: + 474 .text + 475 .Letext0: + 476 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 477 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 478 .file 4 "Drivers/CMSIS/Include/core_cm4.h" + 479 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + ARM GAS /tmp/ccVidTYQ.s page 17 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_pwr.c + /tmp/ccVidTYQ.s:21 .text.HAL_PWR_DeInit:0000000000000000 $t + /tmp/ccVidTYQ.s:27 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit + /tmp/ccVidTYQ.s:48 .text.HAL_PWR_DeInit:0000000000000014 $d + /tmp/ccVidTYQ.s:53 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.text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t + /tmp/ccVidTYQ.s:175 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode + /tmp/ccVidTYQ.s:224 .text.HAL_PWR_EnterSLEEPMode:000000000000001c $d + /tmp/ccVidTYQ.s:229 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t + /tmp/ccVidTYQ.s:235 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode + /tmp/ccVidTYQ.s:312 .text.HAL_PWR_EnterSTOPMode:0000000000000030 $d + /tmp/ccVidTYQ.s:318 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t + /tmp/ccVidTYQ.s:324 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode + /tmp/ccVidTYQ.s:357 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d + /tmp/ccVidTYQ.s:363 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t + /tmp/ccVidTYQ.s:369 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit + /tmp/ccVidTYQ.s:386 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d + /tmp/ccVidTYQ.s:391 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t 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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_pwr_ex.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_pwr_ex.lst new file mode 100644 index 0000000..4ed93c4 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_pwr_ex.lst @@ -0,0 +1,499 @@ +ARM GAS /tmp/ccAAJ6DZ.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_pwr_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c" + 20 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits + 21 .align 1 + 22 .global HAL_PWR_ConfigPVD + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_PWR_ConfigPVD: + 28 .LVL0: + 29 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @file stm32f3xx_hal_pwr_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * functionalities of the Power Controller (PWR) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + Extended Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + Extended Peripheral Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ****************************************************************************** + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @attention + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * All rights reserved.

    + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * the "License"; You may not use this file except in compliance with the + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * License. You may obtain a copy of the License at: + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * opensource.org/licenses/BSD-3-Clause + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ****************************************************************************** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/ + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #include "stm32f3xx_hal.h" + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + ARM GAS /tmp/ccAAJ6DZ.s page 2 + + + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief PWREx HAL module driver + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Private_Constants PWR Extended Private Constants + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_MODE_IT (0x00010000U) + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_MODE_EVT (0x00020000U) + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_RISING_EDGE (0x00000001U) + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_FALLING_EDGE (0x00000002U) + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @} + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/ + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/ + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Exported functions ---------------------------------------------------------*/ + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Extended Peripheral Control functions + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** @verbatim + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** =============================================================================== + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ##### Peripheral Extended control functions ##### + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** =============================================================================== + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** PVD configuration (present on all other devices than STM32F3x8 devices) *** + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ========================= + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..] + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** than the PVD threshold. This event is internally connected to the EXTI + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** line16 and can generate an interrupt if enabled. This is done through + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is stopped in Standby mode. + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** -@- PVD is not available on STM32F3x8 Product Line + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** Voltage regulator *** + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ========================= + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..] + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The voltage regulator is always enabled after Reset. It works in three different + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** modes. + ARM GAS /tmp/ccAAJ6DZ.s page 3 + + + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Run mode, the regulator supplies full power to the 1.8V domain (core, memories + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** and digital peripherals). + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Stop mode, the regulator supplies low power to the 1.8V domain, preserving + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** contents of registers and SRAM. + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Stop mode, the regulator is powered off. The contents of the registers and SRAM + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** are lost except for the Standby circuitry and the Backup Domain. + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage. + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** than the PVD threshold. This event is internally connected to the EXTI + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** line16 and can generate an interrupt if enabled. This is done through + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is stopped in Standby mode. + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** SDADC power configuration *** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ================================ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..] + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) On STM32F373xC/STM32F378xx devices, there are up to + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** 3 SDADC instances that can be enabled/disabled. + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** @endverbatim + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || \ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F302xC) || defined(STM32F303xC) || \ + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F303x8) || defined(STM32F334x8) || \ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F301x8) || defined(STM32F302x8) || \ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F373xC) + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * information for the PVD. + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @note Refer to the electrical characteristics of your device datasheet for + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * more details about the voltage threshold corresponding to each + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * detection level. + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 30 .loc 1 130 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 @ link register save eliminated. + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Check the parameters */ + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + 35 .loc 1 132 3 view .LVU1 + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + 36 .loc 1 133 3 view .LVU2 + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Set PLS[7:5] bits according to PVDLevel value */ + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + ARM GAS /tmp/ccAAJ6DZ.s page 4 + + + 37 .loc 1 136 3 view .LVU3 + 38 0000 1E4A ldr r2, .L6 + 39 0002 1368 ldr r3, [r2] + 40 0004 23F0E003 bic r3, r3, #224 + 41 0008 0168 ldr r1, [r0] + 42 000a 0B43 orrs r3, r3, r1 + 43 000c 1360 str r3, [r2] + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + 44 .loc 1 139 3 view .LVU4 + 45 000e 1C4B ldr r3, .L6+4 + 46 0010 5A68 ldr r2, [r3, #4] + 47 0012 22F48032 bic r2, r2, #65536 + 48 0016 5A60 str r2, [r3, #4] + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); + 49 .loc 1 140 3 view .LVU5 + 50 0018 1A68 ldr r2, [r3] + 51 001a 22F48032 bic r2, r2, #65536 + 52 001e 1A60 str r2, [r3] + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + 53 .loc 1 141 3 view .LVU6 + 54 0020 9A68 ldr r2, [r3, #8] + 55 0022 22F48032 bic r2, r2, #65536 + 56 0026 9A60 str r2, [r3, #8] + 57 .loc 1 141 44 view .LVU7 + 58 0028 DA68 ldr r2, [r3, #12] + 59 002a 22F48032 bic r2, r2, #65536 + 60 002e DA60 str r2, [r3, #12] + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure interrupt mode */ + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + 61 .loc 1 144 3 view .LVU8 + 62 .loc 1 144 17 is_stmt 0 view .LVU9 + 63 0030 4368 ldr r3, [r0, #4] + 64 .loc 1 144 5 view .LVU10 + 65 0032 13F4803F tst r3, #65536 + 66 0036 04D0 beq .L2 + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); + 67 .loc 1 146 5 is_stmt 1 view .LVU11 + 68 0038 114A ldr r2, .L6+4 + 69 003a 1368 ldr r3, [r2] + 70 003c 43F48033 orr r3, r3, #65536 + 71 0040 1360 str r3, [r2] + 72 .L2: + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure event mode */ + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + 73 .loc 1 150 3 view .LVU12 + 74 .loc 1 150 17 is_stmt 0 view .LVU13 + 75 0042 4368 ldr r3, [r0, #4] + 76 .loc 1 150 5 view .LVU14 + 77 0044 13F4003F tst r3, #131072 + 78 0048 04D0 beq .L3 + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccAAJ6DZ.s page 5 + + + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + 79 .loc 1 152 5 is_stmt 1 view .LVU15 + 80 004a 0D4A ldr r2, .L6+4 + 81 004c 5368 ldr r3, [r2, #4] + 82 004e 43F48033 orr r3, r3, #65536 + 83 0052 5360 str r3, [r2, #4] + 84 .L3: + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure the edge */ + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + 85 .loc 1 156 3 view .LVU16 + 86 .loc 1 156 17 is_stmt 0 view .LVU17 + 87 0054 4368 ldr r3, [r0, #4] + 88 .loc 1 156 5 view .LVU18 + 89 0056 13F0010F tst r3, #1 + 90 005a 04D0 beq .L4 + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + 91 .loc 1 158 5 is_stmt 1 view .LVU19 + 92 005c 084A ldr r2, .L6+4 + 93 005e 9368 ldr r3, [r2, #8] + 94 0060 43F48033 orr r3, r3, #65536 + 95 0064 9360 str r3, [r2, #8] + 96 .L4: + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + 97 .loc 1 161 3 view .LVU20 + 98 .loc 1 161 17 is_stmt 0 view .LVU21 + 99 0066 4368 ldr r3, [r0, #4] + 100 .loc 1 161 5 view .LVU22 + 101 0068 13F0020F tst r3, #2 + 102 006c 04D0 beq .L1 + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + 103 .loc 1 163 5 is_stmt 1 view .LVU23 + 104 006e 044A ldr r2, .L6+4 + 105 0070 D368 ldr r3, [r2, #12] + 106 0072 43F48033 orr r3, r3, #65536 + 107 0076 D360 str r3, [r2, #12] + 108 .L1: + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 109 .loc 1 165 1 is_stmt 0 view .LVU24 + 110 0078 7047 bx lr + 111 .L7: + 112 007a 00BF .align 2 + 113 .L6: + 114 007c 00700040 .word 1073770496 + 115 0080 00040140 .word 1073808384 + 116 .cfi_endproc + 117 .LFE130: + 119 .section .text.HAL_PWR_EnablePVD,"ax",%progbits + 120 .align 1 + 121 .global HAL_PWR_EnablePVD + 122 .syntax unified + ARM GAS /tmp/ccAAJ6DZ.s page 6 + + + 123 .thumb + 124 .thumb_func + 126 HAL_PWR_EnablePVD: + 127 .LFB131: + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Enables the Power Voltage Detector(PVD). + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_EnablePVD(void) + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 128 .loc 1 172 1 is_stmt 1 view -0 + 129 .cfi_startproc + 130 @ args = 0, pretend = 0, frame = 0 + 131 @ frame_needed = 0, uses_anonymous_args = 0 + 132 @ link register save eliminated. + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** SET_BIT(PWR->CR, PWR_CR_PVDE); + 133 .loc 1 173 3 view .LVU26 + 134 0000 024A ldr r2, .L9 + 135 0002 1368 ldr r3, [r2] + 136 0004 43F01003 orr r3, r3, #16 + 137 0008 1360 str r3, [r2] + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 138 .loc 1 174 1 is_stmt 0 view .LVU27 + 139 000a 7047 bx lr + 140 .L10: + 141 .align 2 + 142 .L9: + 143 000c 00700040 .word 1073770496 + 144 .cfi_endproc + 145 .LFE131: + 147 .section .text.HAL_PWR_DisablePVD,"ax",%progbits + 148 .align 1 + 149 .global HAL_PWR_DisablePVD + 150 .syntax unified + 151 .thumb + 152 .thumb_func + 154 HAL_PWR_DisablePVD: + 155 .LFB132: + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Disables the Power Voltage Detector(PVD). + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_DisablePVD(void) + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 156 .loc 1 181 1 is_stmt 1 view -0 + 157 .cfi_startproc + 158 @ args = 0, pretend = 0, frame = 0 + 159 @ frame_needed = 0, uses_anonymous_args = 0 + 160 @ link register save eliminated. + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR, PWR_CR_PVDE); + 161 .loc 1 182 3 view .LVU29 + 162 0000 024A ldr r2, .L12 + 163 0002 1368 ldr r3, [r2] + 164 0004 23F01003 bic r3, r3, #16 + 165 0008 1360 str r3, [r2] + ARM GAS /tmp/ccAAJ6DZ.s page 7 + + + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 166 .loc 1 183 1 is_stmt 0 view .LVU30 + 167 000a 7047 bx lr + 168 .L13: + 169 .align 2 + 170 .L12: + 171 000c 00700040 .word 1073770496 + 172 .cfi_endproc + 173 .LFE132: + 175 .section .text.HAL_PWR_PVDCallback,"ax",%progbits + 176 .align 1 + 177 .weak HAL_PWR_PVDCallback + 178 .syntax unified + 179 .thumb + 180 .thumb_func + 182 HAL_PWR_PVDCallback: + 183 .LFB134: + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief This function handles the PWR PVD interrupt request. + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @note This API should be called under the PVD_IRQHandler(). + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_PVD_IRQHandler(void) + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Check PWR exti flag */ + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* PWR PVD interrupt user callback */ + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** HAL_PWR_PVDCallback(); + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Clear PWR Exti pending bit */ + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief PWR PVD interrupt callback + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __weak void HAL_PWR_PVDCallback(void) + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 184 .loc 1 208 1 is_stmt 1 view -0 + 185 .cfi_startproc + 186 @ args = 0, pretend = 0, frame = 0 + 187 @ frame_needed = 0, uses_anonymous_args = 0 + 188 @ link register save eliminated. + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** the HAL_PWR_PVDCallback could be implemented in the user file + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 189 .loc 1 212 1 view .LVU32 + 190 0000 7047 bx lr + 191 .cfi_endproc + 192 .LFE134: + 194 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits + 195 .align 1 + ARM GAS /tmp/ccAAJ6DZ.s page 8 + + + 196 .global HAL_PWR_PVD_IRQHandler + 197 .syntax unified + 198 .thumb + 199 .thumb_func + 201 HAL_PWR_PVD_IRQHandler: + 202 .LFB133: + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Check PWR exti flag */ + 203 .loc 1 191 1 view -0 + 204 .cfi_startproc + 205 @ args = 0, pretend = 0, frame = 0 + 206 @ frame_needed = 0, uses_anonymous_args = 0 + 207 0000 08B5 push {r3, lr} + 208 .cfi_def_cfa_offset 8 + 209 .cfi_offset 3, -8 + 210 .cfi_offset 14, -4 + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 211 .loc 1 193 3 view .LVU34 + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 212 .loc 1 193 6 is_stmt 0 view .LVU35 + 213 0002 064B ldr r3, .L19 + 214 0004 5B69 ldr r3, [r3, #20] + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 215 .loc 1 193 5 view .LVU36 + 216 0006 13F4803F tst r3, #65536 + 217 000a 00D1 bne .L18 + 218 .L15: + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 219 .loc 1 201 1 view .LVU37 + 220 000c 08BD pop {r3, pc} + 221 .L18: + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 222 .loc 1 196 5 is_stmt 1 view .LVU38 + 223 000e FFF7FEFF bl HAL_PWR_PVDCallback + 224 .LVL1: + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 225 .loc 1 199 5 view .LVU39 + 226 0012 024B ldr r3, .L19 + 227 0014 4FF48032 mov r2, #65536 + 228 0018 5A61 str r2, [r3, #20] + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 229 .loc 1 201 1 is_stmt 0 view .LVU40 + 230 001a F7E7 b .L15 + 231 .L20: + 232 .align 2 + 233 .L19: + 234 001c 00040140 .word 1073808384 + 235 .cfi_endproc + 236 .LFE133: + 238 .text + 239 .Letext0: + 240 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 241 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 242 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 243 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h" + 244 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + ARM GAS /tmp/ccAAJ6DZ.s page 9 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_pwr_ex.c + /tmp/ccAAJ6DZ.s:21 .text.HAL_PWR_ConfigPVD:0000000000000000 $t + /tmp/ccAAJ6DZ.s:27 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD + /tmp/ccAAJ6DZ.s:114 .text.HAL_PWR_ConfigPVD:000000000000007c $d + /tmp/ccAAJ6DZ.s:120 .text.HAL_PWR_EnablePVD:0000000000000000 $t + /tmp/ccAAJ6DZ.s:126 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD + /tmp/ccAAJ6DZ.s:143 .text.HAL_PWR_EnablePVD:000000000000000c $d + /tmp/ccAAJ6DZ.s:148 .text.HAL_PWR_DisablePVD:0000000000000000 $t + /tmp/ccAAJ6DZ.s:154 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD + /tmp/ccAAJ6DZ.s:171 .text.HAL_PWR_DisablePVD:000000000000000c $d + /tmp/ccAAJ6DZ.s:176 .text.HAL_PWR_PVDCallback:0000000000000000 $t + /tmp/ccAAJ6DZ.s:182 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback + /tmp/ccAAJ6DZ.s:195 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t + /tmp/ccAAJ6DZ.s:201 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler + /tmp/ccAAJ6DZ.s:234 .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d + +NO UNDEFINED SYMBOLS diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_pwr_ex.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_pwr_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..7da9586d82479eae1b2d13be262fa51cb3d61e1d GIT binary patch literal 5500 zcmd5oOW$D&AGO(KbSuv z`#Me0&{EMqlYk-0AEtu%!-Uu$G&(dPu~kT*iXUua5`qfECQ-o;1fA$KAqM4nkMFUs zy%zY%k?(!pkLSGSocEl2&hc}xQ^$l5q>7*+YHCE&z0zZhNf@H-w2gMo267MIc~=)X z|5RXU$H@!1!MkhG3rpK1Zd-a$;)_eSB;Hz@$_4JOJ?eR@7xkv@u8jtyg<$ELjY~_M zEqBBQ&s)CPtI~2+S~OTZv+qdDJ4?&Q=?z+@3G#>ujbq*E(F1ISjrE6JI;`Y-)qC>E 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\ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc.lst new file mode 100644 index 0000000..73aca6b --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc.lst @@ -0,0 +1,6322 @@ +ARM GAS /tmp/cczyIHoC.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_rcc.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c" + 20 .section .text.HAL_RCC_DeInit,"ax",%progbits + 21 .align 1 + 22 .global HAL_RCC_DeInit + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_RCC_DeInit: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @file stm32f3xx_hal_rcc.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * functionalities of the Reset and Clock Control (RCC) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + Peripheral Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### RCC specific features ##### + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** After reset the device is running from Internal High Speed oscillator + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and all peripherals are off except internal SRAM, Flash and JTAG. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** all peripherals mapped on these buses are running at HSI speed. + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) All GPIOs are in input floating state, except the JTAG pins which + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** are assigned to be used for debug purpose. + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] Once the device started from reset, the user application has to: + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the clock source to be used to drive the System clock + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (if the application needs higher frequency/performance) + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the System clock frequency and Flash settings + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the AHB and APB buses prescalers + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Enable the clock for the peripheral(s) to be used + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the clock source(s) for peripherals whose clocks are not + ARM GAS /tmp/cczyIHoC.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS) + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### RCC Limitations ##### + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** A delay between an RCC peripheral clock enable and the effective peripheral + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** enabling should be taken into account in order to manage the peripheral read/write + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** from/to registers. + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) This delay depends on the peripheral mapping. + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) AHB & APB peripherals, 1 dummy read is necessary + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Workarounds: + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @attention + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * All rights reserved.

    + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This software component is licensed by ST under BSD 3-Clause license, + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * the "License"; You may not use this file except in compliance with the + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * License. You may obtain a copy of the License at: + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * opensource.org/licenses/BSD-3-Clause + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #include "stm32f3xx_hal.h" + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @addtogroup STM32F3xx_HAL_Driver + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC RCC + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC HAL module driver + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/ + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/ + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Constants RCC Private Constants + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Bits position in in the CFGR register */ + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE) + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1) + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2) + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + ARM GAS /tmp/cczyIHoC.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/ + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_GPIO_PORT GPIOA + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_PIN GPIO_PIN_8 + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Exported functions ---------------------------------------------------------*/ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initialization and Configuration functions + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### Initialization and de-initialization functions ##### + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** This section provides functions allowing to configure the internal/external oscillators + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and APB2). + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] Internal/external clock and PLL configuration + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the PLL as System clock source. + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** The HSI clock can be used also to clock the USART and I2C peripherals. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock source. + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** through the PLL as System clock source. Can be used also as RTC clock source. + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + ARM GAS /tmp/cczyIHoC.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) PLL (clocked by HSI or HSE), featuring different output clocks: + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The first output is used to generate the high speed system clock (up to 72 MHz) + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The second output is used to generate the clock for the USB FS (48 MHz) + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 M + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz) + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and if a HSE clock failure occurs(HSE used directly or through PLL as System + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock source), the System clocks automatically switched to HSI and an interrupt + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** is generated if enabled. The interrupt is linked to the Cortex-M4 NMI + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (Non-Maskable Interrupt) exception vector. + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock (divided by 2) output on pin (such as PA8 pin). + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] System, AHB and APB buses clocks configuration + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HSE and PLL. + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** The AHB clock (HCLK) is derived from System clock through configurable + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prescaler and used to clock the CPU, memory and peripherals mapped + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** from AHB clock through configurable prescalers and used to clock + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the peripherals mapped on these buses. You can use + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The FLASH program/erase clock which is always HSI 8MHz clock. + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The USB 48 MHz clock which is derived from the PLL VCO clock. + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The I2C clock which can be derived as well from HSI 8MHz clock. + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The ADC clock which is derived from PLL output. + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSE divided by a programmable prescaler). The System clock (SYSCLK) + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** frequency must be higher or equal to the RTC clock frequency. + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) IWDG clock which is always the LSI clock. + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prefetch is disabled. + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Additional consideration on the SYSCLK based on Latency settings: + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +-----------------------------------------------+ + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** | Latency | SYSCLK clock frequency (MHz) | + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +-----------------------------------------------+ + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + ARM GAS /tmp/cczyIHoC.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state. + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The default reset state of the clock configuration is given below: + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - HSI ON and used as system clock source + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - HSE and PLL OFF + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - AHB, APB1 and APB2 prescaler set to 1. + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - CSS and MCO1 OFF + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - All interrupts disabled + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This function does not modify the configuration of the + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - Peripheral clocks + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - LSI, LSE and RTC clocks + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void) + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 29 .loc 1 217 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 0000 38B5 push {r3, r4, r5, lr} + 34 .cfi_def_cfa_offset 16 + 35 .cfi_offset 3, -16 + 36 .cfi_offset 4, -12 + 37 .cfi_offset 5, -8 + 38 .cfi_offset 14, -4 + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0; + 39 .loc 1 218 3 view .LVU1 + 40 .LVL0: + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set HSION bit */ + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSION); + 41 .loc 1 221 3 view .LVU2 + 42 0002 364A ldr r2, .L18 + 43 0004 1368 ldr r3, [r2] + 44 0006 43F00103 orr r3, r3, #1 + 45 000a 1360 str r3, [r2] + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure HSIRDY bit is set before writing default HSITRIM value */ + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 46 .loc 1 225 3 view .LVU3 + 47 .loc 1 225 15 is_stmt 0 view .LVU4 + 48 000c FFF7FEFF bl HAL_GetTick + 49 .LVL1: + 50 0010 0446 mov r4, r0 + 51 .LVL2: + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is ready */ + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + 52 .loc 1 228 3 is_stmt 1 view .LVU5 + 53 .L2: + 54 .loc 1 228 42 view .LVU6 + 55 .loc 1 228 9 is_stmt 0 view .LVU7 + 56 0012 324B ldr r3, .L18 + 57 0014 1B68 ldr r3, [r3] + 58 .loc 1 228 42 view .LVU8 + ARM GAS /tmp/cczyIHoC.s page 6 + + + 59 0016 13F0020F tst r3, #2 + 60 001a 07D1 bne .L14 + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 61 .loc 1 230 5 is_stmt 1 view .LVU9 + 62 .loc 1 230 9 is_stmt 0 view .LVU10 + 63 001c FFF7FEFF bl HAL_GetTick + 64 .LVL3: + 65 .loc 1 230 23 view .LVU11 + 66 0020 001B subs r0, r0, r4 + 67 .loc 1 230 7 view .LVU12 + 68 0022 0228 cmp r0, #2 + 69 0024 F5D9 bls .L2 + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 70 .loc 1 232 14 view .LVU13 + 71 0026 0324 movs r4, #3 + 72 .LVL4: + 73 .L3: + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set HSITRIM default value */ + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, RCC_CR_HSITRIM_4); + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */ + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure HSI selected as system clock source */ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till system clock source is ready */ + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update the SystemCoreClock global variable for HSI as system clock source */ + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SystemCoreClock = HSI_VALUE; + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the source of time base considering new system clock settings */ + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(HAL_InitTick(uwTickPrio) != HAL_OK) + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset HSEON, CSSON, PLLON bits */ + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset HSEBYP bit */ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure PLLRDY is reset */ + ARM GAS /tmp/cczyIHoC.s page 7 + + + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR register */ + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR); + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR2 register */ + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR2); + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR3 register */ + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR3); + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Clear all interrupt flags */ + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable all interrupts */ + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CIR); + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset all CSR flags */ + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_CLEAR_RESET_FLAGS(); + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 74 .loc 1 300 1 view .LVU14 + 75 0028 2046 mov r0, r4 + 76 002a 38BD pop {r3, r4, r5, pc} + 77 .LVL5: + 78 .L14: + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 79 .loc 1 237 3 is_stmt 1 view .LVU15 + 80 002c 2B4A ldr r2, .L18 + 81 002e 1368 ldr r3, [r2] + 82 0030 23F0F803 bic r3, r3, #248 + 83 0034 43F08003 orr r3, r3, #128 + 84 0038 1360 str r3, [r2] + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 85 .loc 1 240 3 view .LVU16 + 86 003a 5168 ldr r1, [r2, #4] + 87 003c 284B ldr r3, .L18+4 + 88 003e 0B40 ands r3, r3, r1 + 89 0040 5360 str r3, [r2, #4] + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 90 .loc 1 244 3 view .LVU17 + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 91 .loc 1 244 15 is_stmt 0 view .LVU18 + 92 0042 FFF7FEFF bl HAL_GetTick + 93 .LVL6: + 94 0046 0446 mov r4, r0 + 95 .LVL7: + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + ARM GAS /tmp/cczyIHoC.s page 8 + + + 96 .loc 1 247 3 is_stmt 1 view .LVU19 + 97 .L5: + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 98 .loc 1 247 43 view .LVU20 + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 99 .loc 1 247 9 is_stmt 0 view .LVU21 + 100 0048 244B ldr r3, .L18 + 101 004a 5B68 ldr r3, [r3, #4] + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 102 .loc 1 247 43 view .LVU22 + 103 004c 13F00C0F tst r3, #12 + 104 0050 08D0 beq .L15 + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 105 .loc 1 249 5 is_stmt 1 view .LVU23 + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 106 .loc 1 249 9 is_stmt 0 view .LVU24 + 107 0052 FFF7FEFF bl HAL_GetTick + 108 .LVL8: + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 109 .loc 1 249 23 view .LVU25 + 110 0056 001B subs r0, r0, r4 + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 111 .loc 1 249 7 view .LVU26 + 112 0058 41F28833 movw r3, #5000 + 113 005c 9842 cmp r0, r3 + 114 005e F3D9 bls .L5 + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 115 .loc 1 251 14 view .LVU27 + 116 0060 0324 movs r4, #3 + 117 .LVL9: + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 118 .loc 1 251 14 view .LVU28 + 119 0062 E1E7 b .L3 + 120 .LVL10: + 121 .L15: + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 122 .loc 1 256 3 is_stmt 1 view .LVU29 + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 123 .loc 1 256 19 is_stmt 0 view .LVU30 + 124 0064 1F4B ldr r3, .L18+8 + 125 0066 204A ldr r2, .L18+12 + 126 0068 1A60 str r2, [r3] + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 127 .loc 1 259 3 is_stmt 1 view .LVU31 + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 128 .loc 1 259 6 is_stmt 0 view .LVU32 + 129 006a 204B ldr r3, .L18+16 + 130 006c 1868 ldr r0, [r3] + 131 006e FFF7FEFF bl HAL_InitTick + 132 .LVL11: + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 133 .loc 1 259 5 view .LVU33 + 134 0072 0446 mov r4, r0 + 135 .LVL12: + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 136 .loc 1 259 5 view .LVU34 + 137 0074 08B1 cbz r0, .L16 + ARM GAS /tmp/cczyIHoC.s page 9 + + + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 138 .loc 1 261 12 view .LVU35 + 139 0076 0124 movs r4, #1 + 140 0078 D6E7 b .L3 + 141 .L16: + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 142 .loc 1 265 3 is_stmt 1 view .LVU36 + 143 007a 184A ldr r2, .L18 + 144 007c 1368 ldr r3, [r2] + 145 007e 23F08473 bic r3, r3, #17301504 + 146 0082 23F48033 bic r3, r3, #65536 + 147 0086 1360 str r3, [r2] + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 148 .loc 1 268 3 view .LVU37 + 149 0088 1368 ldr r3, [r2] + 150 008a 23F48023 bic r3, r3, #262144 + 151 008e 1360 str r3, [r2] + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 152 .loc 1 272 3 view .LVU38 + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 153 .loc 1 272 15 is_stmt 0 view .LVU39 + 154 0090 FFF7FEFF bl HAL_GetTick + 155 .LVL13: + 156 0094 0546 mov r5, r0 + 157 .LVL14: + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 158 .loc 1 273 3 is_stmt 1 view .LVU40 + 159 .L7: + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 160 .loc 1 273 42 view .LVU41 + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 161 .loc 1 273 9 is_stmt 0 view .LVU42 + 162 0096 114B ldr r3, .L18 + 163 0098 1B68 ldr r3, [r3] + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 164 .loc 1 273 42 view .LVU43 + 165 009a 13F0007F tst r3, #33554432 + 166 009e 06D0 beq .L17 + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 167 .loc 1 275 5 is_stmt 1 view .LVU44 + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 168 .loc 1 275 9 is_stmt 0 view .LVU45 + 169 00a0 FFF7FEFF bl HAL_GetTick + 170 .LVL15: + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 171 .loc 1 275 23 view .LVU46 + 172 00a4 401B subs r0, r0, r5 + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 173 .loc 1 275 7 view .LVU47 + 174 00a6 0228 cmp r0, #2 + 175 00a8 F5D9 bls .L7 + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 176 .loc 1 277 14 view .LVU48 + 177 00aa 0324 movs r4, #3 + 178 00ac BCE7 b .L3 + 179 .L17: + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + ARM GAS /tmp/cczyIHoC.s page 10 + + + 180 .loc 1 282 3 is_stmt 1 view .LVU49 + 181 00ae 0B4B ldr r3, .L18 + 182 00b0 0022 movs r2, #0 + 183 00b2 5A60 str r2, [r3, #4] + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 184 .loc 1 285 3 view .LVU50 + 185 00b4 DA62 str r2, [r3, #44] + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 186 .loc 1 288 3 view .LVU51 + 187 00b6 1A63 str r2, [r3, #48] + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 188 .loc 1 291 3 view .LVU52 + 189 00b8 9968 ldr r1, [r3, #8] + 190 00ba 41F41F01 orr r1, r1, #10420224 + 191 00be 9960 str r1, [r3, #8] + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 192 .loc 1 294 3 view .LVU53 + 193 00c0 9A60 str r2, [r3, #8] + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 194 .loc 1 297 3 view .LVU54 + 195 .LVL16: + 196 .LBB168: + 197 .LBI168: + 198 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cczyIHoC.s page 11 + + + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + ARM GAS /tmp/cczyIHoC.s page 12 + + + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + ARM GAS /tmp/cczyIHoC.s page 13 + + + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cczyIHoC.s page 14 + + + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cczyIHoC.s page 15 + + + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/cczyIHoC.s page 16 + + + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cczyIHoC.s page 17 + + + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + ARM GAS /tmp/cczyIHoC.s page 18 + + + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + ARM GAS /tmp/cczyIHoC.s page 19 + + + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + ARM GAS /tmp/cczyIHoC.s page 20 + + + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/cczyIHoC.s page 21 + + + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + ARM GAS /tmp/cczyIHoC.s page 22 + + + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + ARM GAS /tmp/cczyIHoC.s page 23 + + + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + ARM GAS /tmp/cczyIHoC.s page 24 + + + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cczyIHoC.s page 25 + + + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + ARM GAS /tmp/cczyIHoC.s page 26 + + + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cczyIHoC.s page 27 + + + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 199 .loc 2 981 31 view .LVU55 + 200 .LBB169: + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 201 .loc 2 983 3 view .LVU56 + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 202 .loc 2 988 4 view .LVU57 + 203 00c2 4FF08072 mov r2, #16777216 + 204 .syntax unified + 205 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 206 00c6 92FAA2F2 rbit r2, r2 + 207 @ 0 "" 2 + 208 .LVL17: + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + ARM GAS /tmp/cczyIHoC.s page 28 + + + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 209 .loc 2 1001 3 view .LVU58 + 210 .loc 2 1001 3 is_stmt 0 view .LVU59 + 211 .thumb + 212 .syntax unified + 213 .LBE169: + 214 .LBE168: + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 215 .loc 1 297 3 view .LVU60 + 216 00ca B2FA82F2 clz r2, r2 + 217 00ce 084B ldr r3, .L18+20 + 218 00d0 1344 add r3, r3, r2 + 219 00d2 9B00 lsls r3, r3, #2 + 220 00d4 0122 movs r2, #1 + 221 00d6 1A60 str r2, [r3] + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 222 .loc 1 299 3 is_stmt 1 view .LVU61 + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 223 .loc 1 299 10 is_stmt 0 view .LVU62 + 224 00d8 A6E7 b .L3 + 225 .L19: + 226 00da 00BF .align 2 + 227 .L18: + 228 00dc 00100240 .word 1073876992 + 229 00e0 0CC0FFF8 .word -117456884 + 230 00e4 00000000 .word SystemCoreClock + 231 00e8 00127A00 .word 8000000 + 232 00ec 00000000 .word uwTickPrio + 233 00f0 20819010 .word 277905696 + 234 .cfi_endproc + 235 .LFE130: + 237 .section .text.HAL_RCC_OscConfig,"ax",%progbits + 238 .align 1 + 239 .global HAL_RCC_OscConfig + 240 .syntax unified + 241 .thumb + 242 .thumb_func + 244 HAL_RCC_OscConfig: + 245 .LVL18: + 246 .LFB131: + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initializes the RCC Oscillators according to the specified parameters in the + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC_OscInitTypeDef. + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the configuration information for the RCC Oscillators. + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The PLL is not disabled when used as system clock. + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * supported by this macro. User should request a transition to LSE Off + ARM GAS /tmp/cczyIHoC.s page 29 + + + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * first and then LSE On or LSE Bypass. + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * supported by this macro. User should request a transition to HSE Off + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * first and then HSE On or HSE Bypass. + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 247 .loc 1 317 1 is_stmt 1 view -0 + 248 .cfi_startproc + 249 @ args = 0, pretend = 0, frame = 8 + 250 @ frame_needed = 0, uses_anonymous_args = 0 + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart; + 251 .loc 1 318 3 view .LVU64 + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t pll_config; + 252 .loc 1 319 3 view .LVU65 + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t pll_config2; + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check Null pointer */ + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct == NULL) + 253 .loc 1 325 3 view .LVU66 + 254 .loc 1 325 5 is_stmt 0 view .LVU67 + 255 0000 0028 cmp r0, #0 + 256 0002 00F0FF82 beq .L94 + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart; + 257 .loc 1 317 1 view .LVU68 + 258 0006 70B5 push {r4, r5, r6, lr} + 259 .cfi_def_cfa_offset 16 + 260 .cfi_offset 4, -16 + 261 .cfi_offset 5, -12 + 262 .cfi_offset 6, -8 + 263 .cfi_offset 14, -4 + 264 0008 82B0 sub sp, sp, #8 + 265 .cfi_def_cfa_offset 24 + 266 000a 0446 mov r4, r0 + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + 267 .loc 1 331 3 is_stmt 1 view .LVU69 + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------- HSE Configuration ------------------------*/ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 268 .loc 1 334 3 view .LVU70 + 269 .loc 1 334 25 is_stmt 0 view .LVU71 + 270 000c 0368 ldr r3, [r0] + 271 .loc 1 334 5 view .LVU72 + 272 000e 13F0010F tst r3, #1 + 273 0012 3BD0 beq .L22 + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + 274 .loc 1 337 5 is_stmt 1 view .LVU73 + ARM GAS /tmp/cczyIHoC.s page 30 + + + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 275 .loc 1 340 5 view .LVU74 + 276 .loc 1 340 9 is_stmt 0 view .LVU75 + 277 0014 B44B ldr r3, .L132 + 278 0016 5B68 ldr r3, [r3, #4] + 279 0018 03F00C03 and r3, r3, #12 + 280 .loc 1 340 7 view .LVU76 + 281 001c 042B cmp r3, #4 + 282 001e 1ED0 beq .L23 + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 283 .loc 1 341 13 view .LVU77 + 284 0020 B14B ldr r3, .L132 + 285 0022 5B68 ldr r3, [r3, #4] + 286 0024 03F00C03 and r3, r3, #12 + 287 .loc 1 341 8 view .LVU78 + 288 0028 082B cmp r3, #8 + 289 002a 13D0 beq .L118 + 290 .L24: + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_ + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set the new HSE configuration ---------------------------------------*/ + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 291 .loc 1 351 7 is_stmt 1 view .LVU79 + 292 .loc 1 351 7 view .LVU80 + 293 002c 6368 ldr r3, [r4, #4] + 294 002e B3F5803F cmp r3, #65536 + 295 0032 68D0 beq .L119 + 296 .loc 1 351 7 discriminator 2 view .LVU81 + 297 0034 002B cmp r3, #0 + 298 0036 40F09280 bne .L29 + 299 .loc 1 351 7 discriminator 4 view .LVU82 + 300 003a 03F18043 add r3, r3, #1073741824 + 301 003e 03F50433 add r3, r3, #135168 + 302 0042 1A68 ldr r2, [r3] + 303 0044 22F48032 bic r2, r2, #65536 + 304 0048 1A60 str r2, [r3] + 305 .loc 1 351 7 discriminator 4 view .LVU83 + 306 004a 1A68 ldr r2, [r3] + 307 004c 22F48022 bic r2, r2, #262144 + 308 0050 1A60 str r2, [r3] + 309 0052 5DE0 b .L28 + 310 .L118: + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 311 .loc 1 341 82 is_stmt 0 discriminator 1 view .LVU84 + 312 0054 A44B ldr r3, .L132 + 313 0056 5B68 ldr r3, [r3, #4] + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 314 .loc 1 341 78 discriminator 1 view .LVU85 + 315 0058 13F4803F tst r3, #65536 + ARM GAS /tmp/cczyIHoC.s page 31 + + + 316 005c E6D0 beq .L24 + 317 .L23: + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 318 .loc 1 343 7 is_stmt 1 view .LVU86 + 319 .LVL19: + 320 .LBB170: + 321 .LBI170: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 322 .loc 2 981 31 view .LVU87 + 323 .LBB171: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 324 .loc 2 983 3 view .LVU88 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 325 .loc 2 988 4 view .LVU89 + 326 005e 4FF40033 mov r3, #131072 + 327 .syntax unified + 328 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 329 0062 93FAA3F3 rbit r3, r3 + 330 @ 0 "" 2 + 331 .loc 2 1001 3 view .LVU90 + 332 .LVL20: + 333 .loc 2 1001 3 is_stmt 0 view .LVU91 + 334 .thumb + 335 .syntax unified + 336 .LBE171: + 337 .LBE170: + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 338 .loc 1 343 11 view .LVU92 + 339 0066 A04B ldr r3, .L132 + 340 0068 1968 ldr r1, [r3] + 341 .LVL21: + 342 .LBB172: + 343 .LBI172: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 344 .loc 2 981 31 is_stmt 1 view .LVU93 + 345 .LBB173: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 346 .loc 2 983 3 view .LVU94 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 347 .loc 2 988 4 view .LVU95 + 348 006a 4FF40033 mov r3, #131072 + 349 .syntax unified + 350 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 351 006e 93FAA3F3 rbit r3, r3 + 352 @ 0 "" 2 + 353 .LVL22: + 354 .loc 2 1001 3 view .LVU96 + 355 .loc 2 1001 3 is_stmt 0 view .LVU97 + 356 .thumb + 357 .syntax unified + 358 .LBE173: + 359 .LBE172: + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 360 .loc 1 343 11 view .LVU98 + 361 0072 B3FA83F3 clz r3, r3 + 362 0076 03F01F03 and r3, r3, #31 + 363 007a 0122 movs r2, #1 + ARM GAS /tmp/cczyIHoC.s page 32 + + + 364 007c 02FA03F3 lsl r3, r2, r3 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 365 .loc 1 343 9 view .LVU99 + 366 0080 0B42 tst r3, r1 + 367 0082 03D0 beq .L22 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 368 .loc 1 343 78 discriminator 13 view .LVU100 + 369 0084 6368 ldr r3, [r4, #4] + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 370 .loc 1 343 57 discriminator 13 view .LVU101 + 371 0086 002B cmp r3, #0 + 372 0088 00F0BE82 beq .L120 + 373 .LVL23: + 374 .L22: + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the HSE predivision factor --------------------------------*/ + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSE State */ + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSE is ready */ + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSE is disabled */ + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*----------------------------- HSI Configuration --------------------------*/ + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 375 .loc 1 390 3 is_stmt 1 view .LVU102 + 376 .loc 1 390 25 is_stmt 0 view .LVU103 + 377 008c 2368 ldr r3, [r4] + 378 .loc 1 390 5 view .LVU104 + ARM GAS /tmp/cczyIHoC.s page 33 + + + 379 008e 13F0020F tst r3, #2 + 380 0092 00F0C480 beq .L40 + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + 381 .loc 1 393 5 is_stmt 1 view .LVU105 + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + 382 .loc 1 394 5 view .LVU106 + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock * + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 383 .loc 1 397 5 view .LVU107 + 384 .loc 1 397 9 is_stmt 0 view .LVU108 + 385 0096 944B ldr r3, .L132 + 386 0098 5B68 ldr r3, [r3, #4] + 387 .loc 1 397 7 view .LVU109 + 388 009a 13F00C0F tst r3, #12 + 389 009e 00F09C80 beq .L41 + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 390 .loc 1 398 13 view .LVU110 + 391 00a2 914B ldr r3, .L132 + 392 00a4 5B68 ldr r3, [r3, #4] + 393 00a6 03F00C03 and r3, r3, #12 + 394 .loc 1 398 8 view .LVU111 + 395 00aa 082B cmp r3, #8 + 396 00ac 00F08F80 beq .L121 + 397 .L42: + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* When HSI is used as system clock it will not disabled */ + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSI State */ + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 398 .loc 1 415 7 is_stmt 1 view .LVU112 + 399 .loc 1 415 27 is_stmt 0 view .LVU113 + 400 00b0 2369 ldr r3, [r4, #16] + 401 .loc 1 415 9 view .LVU114 + 402 00b2 002B cmp r3, #0 + 403 00b4 00F0F080 beq .L46 + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI). */ + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_ENABLE(); + 404 .loc 1 418 9 is_stmt 1 view .LVU115 + 405 .LVL24: + 406 .LBB174: + 407 .LBI174: + ARM GAS /tmp/cczyIHoC.s page 34 + + + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 408 .loc 2 981 31 view .LVU116 + 409 .LBB175: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 410 .loc 2 983 3 view .LVU117 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 411 .loc 2 988 4 view .LVU118 + 412 00b8 0122 movs r2, #1 + 413 .syntax unified + 414 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 415 00ba 92FAA2F3 rbit r3, r2 + 416 @ 0 "" 2 + 417 .LVL25: + 418 .loc 2 1001 3 view .LVU119 + 419 .loc 2 1001 3 is_stmt 0 view .LVU120 + 420 .thumb + 421 .syntax unified + 422 .LBE175: + 423 .LBE174: + 424 .loc 1 418 9 view .LVU121 + 425 00be B3FA83F3 clz r3, r3 + 426 00c2 03F18453 add r3, r3, #276824064 + 427 00c6 03F58413 add r3, r3, #1081344 + 428 00ca 9B00 lsls r3, r3, #2 + 429 00cc 1A60 str r2, [r3] + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 430 .loc 1 421 9 is_stmt 1 view .LVU122 + 431 .loc 1 421 21 is_stmt 0 view .LVU123 + 432 00ce FFF7FEFF bl HAL_GetTick + 433 .LVL26: + 434 00d2 0546 mov r5, r0 + 435 .LVL27: + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is ready */ + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 436 .loc 1 424 9 is_stmt 1 view .LVU124 + 437 .L47: + 438 .loc 1 424 51 view .LVU125 + 439 .LBB176: + 440 .LBI176: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441 .loc 2 981 31 view .LVU126 + 442 .LBB177: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 443 .loc 2 983 3 view .LVU127 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 444 .loc 2 988 4 view .LVU128 + 445 00d4 0223 movs r3, #2 + 446 .syntax unified + 447 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 448 00d6 93FAA3F3 rbit r3, r3 + 449 @ 0 "" 2 + 450 .loc 2 1001 3 view .LVU129 + 451 .LVL28: + 452 .loc 2 1001 3 is_stmt 0 view .LVU130 + ARM GAS /tmp/cczyIHoC.s page 35 + + + 453 .thumb + 454 .syntax unified + 455 .LBE177: + 456 .LBE176: + 457 .loc 1 424 15 view .LVU131 + 458 00da 834B ldr r3, .L132 + 459 00dc 1968 ldr r1, [r3] + 460 .LVL29: + 461 .LBB178: + 462 .LBI178: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463 .loc 2 981 31 is_stmt 1 view .LVU132 + 464 .LBB179: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465 .loc 2 983 3 view .LVU133 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 466 .loc 2 988 4 view .LVU134 + 467 00de 0223 movs r3, #2 + 468 .syntax unified + 469 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 470 00e0 93FAA3F3 rbit r3, r3 + 471 @ 0 "" 2 + 472 .LVL30: + 473 .loc 2 1001 3 view .LVU135 + 474 .loc 2 1001 3 is_stmt 0 view .LVU136 + 475 .thumb + 476 .syntax unified + 477 .LBE179: + 478 .LBE178: + 479 .loc 1 424 15 view .LVU137 + 480 00e4 B3FA83F3 clz r3, r3 + 481 00e8 03F01F03 and r3, r3, #31 + 482 00ec 0122 movs r2, #1 + 483 00ee 02FA03F3 lsl r3, r2, r3 + 484 .loc 1 424 51 view .LVU138 + 485 00f2 0B42 tst r3, r1 + 486 00f4 40F0C280 bne .L122 + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 487 .loc 1 426 11 is_stmt 1 view .LVU139 + 488 .loc 1 426 15 is_stmt 0 view .LVU140 + 489 00f8 FFF7FEFF bl HAL_GetTick + 490 .LVL31: + 491 .loc 1 426 29 view .LVU141 + 492 00fc 401B subs r0, r0, r5 + 493 .loc 1 426 13 view .LVU142 + 494 00fe 0228 cmp r0, #2 + 495 0100 E8D9 bls .L47 + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 496 .loc 1 428 20 view .LVU143 + 497 0102 0320 movs r0, #3 + 498 0104 89E2 b .L21 + 499 .LVL32: + 500 .L119: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 501 .loc 1 351 7 is_stmt 1 discriminator 1 view .LVU144 + ARM GAS /tmp/cczyIHoC.s page 36 + + + 502 0106 784A ldr r2, .L132 + 503 0108 1368 ldr r3, [r2] + 504 010a 43F48033 orr r3, r3, #65536 + 505 010e 1360 str r3, [r2] + 506 .L28: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 507 .loc 1 351 7 discriminator 10 view .LVU145 + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + 508 .loc 1 355 7 discriminator 10 view .LVU146 + 509 0110 754A ldr r2, .L132 + 510 0112 D36A ldr r3, [r2, #44] + 511 0114 23F00F03 bic r3, r3, #15 + 512 0118 A168 ldr r1, [r4, #8] + 513 011a 0B43 orrs r3, r3, r1 + 514 011c D362 str r3, [r2, #44] + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 515 .loc 1 359 7 discriminator 10 view .LVU147 + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 516 .loc 1 359 27 is_stmt 0 discriminator 10 view .LVU148 + 517 011e 6368 ldr r3, [r4, #4] + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 518 .loc 1 359 9 discriminator 10 view .LVU149 + 519 0120 002B cmp r3, #0 + 520 0122 36D0 beq .L31 + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 521 .loc 1 362 9 is_stmt 1 view .LVU150 + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 522 .loc 1 362 21 is_stmt 0 view .LVU151 + 523 0124 FFF7FEFF bl HAL_GetTick + 524 .LVL33: + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 525 .loc 1 362 21 view .LVU152 + 526 0128 0546 mov r5, r0 + 527 .LVL34: + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 528 .loc 1 365 9 is_stmt 1 view .LVU153 + 529 .L32: + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 530 .loc 1 365 51 view .LVU154 + 531 .LBB180: + 532 .LBI180: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 533 .loc 2 981 31 view .LVU155 + 534 .LBB181: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535 .loc 2 983 3 view .LVU156 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 536 .loc 2 988 4 view .LVU157 + 537 012a 4FF40033 mov r3, #131072 + 538 .syntax unified + 539 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 540 012e 93FAA3F3 rbit r3, r3 + 541 @ 0 "" 2 + 542 .loc 2 1001 3 view .LVU158 + 543 .LVL35: + 544 .loc 2 1001 3 is_stmt 0 view .LVU159 + 545 .thumb + ARM GAS /tmp/cczyIHoC.s page 37 + + + 546 .syntax unified + 547 .LBE181: + 548 .LBE180: + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 549 .loc 1 365 15 view .LVU160 + 550 0132 6D4B ldr r3, .L132 + 551 0134 1968 ldr r1, [r3] + 552 .LVL36: + 553 .LBB182: + 554 .LBI182: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 555 .loc 2 981 31 is_stmt 1 view .LVU161 + 556 .LBB183: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 557 .loc 2 983 3 view .LVU162 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 558 .loc 2 988 4 view .LVU163 + 559 0136 4FF40033 mov r3, #131072 + 560 .syntax unified + 561 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 562 013a 93FAA3F3 rbit r3, r3 + 563 @ 0 "" 2 + 564 .LVL37: + 565 .loc 2 1001 3 view .LVU164 + 566 .loc 2 1001 3 is_stmt 0 view .LVU165 + 567 .thumb + 568 .syntax unified + 569 .LBE183: + 570 .LBE182: + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 571 .loc 1 365 15 view .LVU166 + 572 013e B3FA83F3 clz r3, r3 + 573 0142 03F01F03 and r3, r3, #31 + 574 0146 0122 movs r2, #1 + 575 0148 02FA03F3 lsl r3, r2, r3 + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 576 .loc 1 365 51 view .LVU167 + 577 014c 0B42 tst r3, r1 + 578 014e 9DD1 bne .L22 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 579 .loc 1 367 11 is_stmt 1 view .LVU168 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 580 .loc 1 367 15 is_stmt 0 view .LVU169 + 581 0150 FFF7FEFF bl HAL_GetTick + 582 .LVL38: + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 583 .loc 1 367 29 view .LVU170 + 584 0154 401B subs r0, r0, r5 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 585 .loc 1 367 13 view .LVU171 + 586 0156 6428 cmp r0, #100 + 587 0158 E7D9 bls .L32 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 588 .loc 1 369 20 view .LVU172 + 589 015a 0320 movs r0, #3 + 590 015c 5DE2 b .L21 + 591 .LVL39: + ARM GAS /tmp/cczyIHoC.s page 38 + + + 592 .L29: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 593 .loc 1 351 7 is_stmt 1 discriminator 5 view .LVU173 + 594 015e B3F5A02F cmp r3, #327680 + 595 0162 09D0 beq .L123 + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 596 .loc 1 351 7 discriminator 8 view .LVU174 + 597 0164 604B ldr r3, .L132 + 598 0166 1A68 ldr r2, [r3] + 599 0168 22F48032 bic r2, r2, #65536 + 600 016c 1A60 str r2, [r3] + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 601 .loc 1 351 7 discriminator 8 view .LVU175 + 602 016e 1A68 ldr r2, [r3] + 603 0170 22F48022 bic r2, r2, #262144 + 604 0174 1A60 str r2, [r3] + 605 0176 CBE7 b .L28 + 606 .L123: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 607 .loc 1 351 7 discriminator 7 view .LVU176 + 608 0178 03F18043 add r3, r3, #1073741824 + 609 017c A3F53C33 sub r3, r3, #192512 + 610 0180 1A68 ldr r2, [r3] + 611 0182 42F48022 orr r2, r2, #262144 + 612 0186 1A60 str r2, [r3] + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 613 .loc 1 351 7 discriminator 7 view .LVU177 + 614 0188 1A68 ldr r2, [r3] + 615 018a 42F48032 orr r2, r2, #65536 + 616 018e 1A60 str r2, [r3] + 617 0190 BEE7 b .L28 + 618 .L31: + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 619 .loc 1 376 9 view .LVU178 + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 620 .loc 1 376 21 is_stmt 0 view .LVU179 + 621 0192 FFF7FEFF bl HAL_GetTick + 622 .LVL40: + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 623 .loc 1 376 21 view .LVU180 + 624 0196 0546 mov r5, r0 + 625 .LVL41: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 626 .loc 1 379 9 is_stmt 1 view .LVU181 + 627 .L36: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 628 .loc 1 379 51 view .LVU182 + 629 .LBB184: + 630 .LBI184: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 631 .loc 2 981 31 view .LVU183 + 632 .LBB185: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 633 .loc 2 983 3 view .LVU184 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 634 .loc 2 988 4 view .LVU185 + 635 0198 4FF40033 mov r3, #131072 + ARM GAS /tmp/cczyIHoC.s page 39 + + + 636 .syntax unified + 637 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 638 019c 93FAA3F3 rbit r3, r3 + 639 @ 0 "" 2 + 640 .loc 2 1001 3 view .LVU186 + 641 .LVL42: + 642 .loc 2 1001 3 is_stmt 0 view .LVU187 + 643 .thumb + 644 .syntax unified + 645 .LBE185: + 646 .LBE184: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 647 .loc 1 379 15 view .LVU188 + 648 01a0 514B ldr r3, .L132 + 649 01a2 1968 ldr r1, [r3] + 650 .LVL43: + 651 .LBB186: + 652 .LBI186: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 653 .loc 2 981 31 is_stmt 1 view .LVU189 + 654 .LBB187: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655 .loc 2 983 3 view .LVU190 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 656 .loc 2 988 4 view .LVU191 + 657 01a4 4FF40033 mov r3, #131072 + 658 .syntax unified + 659 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 660 01a8 93FAA3F3 rbit r3, r3 + 661 @ 0 "" 2 + 662 .LVL44: + 663 .loc 2 1001 3 view .LVU192 + 664 .loc 2 1001 3 is_stmt 0 view .LVU193 + 665 .thumb + 666 .syntax unified + 667 .LBE187: + 668 .LBE186: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 669 .loc 1 379 15 view .LVU194 + 670 01ac B3FA83F3 clz r3, r3 + 671 01b0 03F01F03 and r3, r3, #31 + 672 01b4 0122 movs r2, #1 + 673 01b6 02FA03F3 lsl r3, r2, r3 + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 674 .loc 1 379 51 view .LVU195 + 675 01ba 0B42 tst r3, r1 + 676 01bc 3FF466AF beq .L22 + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 677 .loc 1 381 12 is_stmt 1 view .LVU196 + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 678 .loc 1 381 16 is_stmt 0 view .LVU197 + 679 01c0 FFF7FEFF bl HAL_GetTick + 680 .LVL45: + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 681 .loc 1 381 30 view .LVU198 + 682 01c4 401B subs r0, r0, r5 + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + ARM GAS /tmp/cczyIHoC.s page 40 + + + 683 .loc 1 381 14 view .LVU199 + 684 01c6 6428 cmp r0, #100 + 685 01c8 E6D9 bls .L36 + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 686 .loc 1 383 20 view .LVU200 + 687 01ca 0320 movs r0, #3 + 688 01cc 25E2 b .L21 + 689 .LVL46: + 690 .L121: + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 691 .loc 1 398 82 discriminator 1 view .LVU201 + 692 01ce 464B ldr r3, .L132 + 693 01d0 5B68 ldr r3, [r3, #4] + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 694 .loc 1 398 78 discriminator 1 view .LVU202 + 695 01d2 13F4803F tst r3, #65536 + 696 01d6 7FF46BAF bne .L42 + 697 .L41: + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 698 .loc 1 401 7 is_stmt 1 view .LVU203 + 699 .LVL47: + 700 .LBB188: + 701 .LBI188: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 702 .loc 2 981 31 view .LVU204 + 703 .LBB189: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 704 .loc 2 983 3 view .LVU205 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 705 .loc 2 988 4 view .LVU206 + 706 01da 0223 movs r3, #2 + 707 .syntax unified + 708 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 709 01dc 93FAA3F3 rbit r3, r3 + 710 @ 0 "" 2 + 711 .loc 2 1001 3 view .LVU207 + 712 .LVL48: + 713 .loc 2 1001 3 is_stmt 0 view .LVU208 + 714 .thumb + 715 .syntax unified + 716 .LBE189: + 717 .LBE188: + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 718 .loc 1 401 11 view .LVU209 + 719 01e0 414B ldr r3, .L132 + 720 01e2 1968 ldr r1, [r3] + 721 .LVL49: + 722 .LBB190: + 723 .LBI190: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 724 .loc 2 981 31 is_stmt 1 view .LVU210 + 725 .LBB191: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 726 .loc 2 983 3 view .LVU211 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 727 .loc 2 988 4 view .LVU212 + 728 01e4 0223 movs r3, #2 + ARM GAS /tmp/cczyIHoC.s page 41 + + + 729 .syntax unified + 730 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 731 01e6 93FAA3F3 rbit r3, r3 + 732 @ 0 "" 2 + 733 .LVL50: + 734 .loc 2 1001 3 view .LVU213 + 735 .loc 2 1001 3 is_stmt 0 view .LVU214 + 736 .thumb + 737 .syntax unified + 738 .LBE191: + 739 .LBE190: + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 740 .loc 1 401 11 view .LVU215 + 741 01ea B3FA83F3 clz r3, r3 + 742 01ee 03F01F03 and r3, r3, #31 + 743 01f2 0122 movs r2, #1 + 744 01f4 02FA03F3 lsl r3, r2, r3 + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 745 .loc 1 401 9 view .LVU216 + 746 01f8 0B42 tst r3, r1 + 747 01fa 03D0 beq .L45 + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 748 .loc 1 401 78 discriminator 13 view .LVU217 + 749 01fc 2369 ldr r3, [r4, #16] + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 750 .loc 1 401 57 discriminator 13 view .LVU218 + 751 01fe 9342 cmp r3, r2 + 752 0200 40F00482 bne .L98 + 753 .L45: + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 754 .loc 1 409 9 is_stmt 1 view .LVU219 + 755 0204 3848 ldr r0, .L132 + 756 0206 0368 ldr r3, [r0] + 757 0208 23F0F803 bic r3, r3, #248 + 758 020c 6169 ldr r1, [r4, #20] + 759 .LVL51: + 760 .LBB192: + 761 .LBI192: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 762 .loc 2 981 31 view .LVU220 + 763 .LBB193: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 764 .loc 2 983 3 view .LVU221 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 765 .loc 2 988 4 view .LVU222 + 766 020e F822 movs r2, #248 + 767 .syntax unified + 768 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 769 0210 92FAA2F2 rbit r2, r2 + 770 @ 0 "" 2 + 771 .LVL52: + 772 .loc 2 1001 3 view .LVU223 + 773 .loc 2 1001 3 is_stmt 0 view .LVU224 + 774 .thumb + 775 .syntax unified + 776 .LBE193: + 777 .LBE192: + ARM GAS /tmp/cczyIHoC.s page 42 + + + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 778 .loc 1 409 9 view .LVU225 + 779 0214 B2FA82F2 clz r2, r2 + 780 0218 9140 lsls r1, r1, r2 + 781 021a 0B43 orrs r3, r3, r1 + 782 021c 0360 str r3, [r0] + 783 .L40: + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI). */ + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_DISABLE(); + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is disabled */ + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------ LSI Configuration -------------------------*/ + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 784 .loc 1 455 3 is_stmt 1 view .LVU226 + 785 .loc 1 455 25 is_stmt 0 view .LVU227 + 786 021e 2368 ldr r3, [r4] + 787 .loc 1 455 5 view .LVU228 + 788 0220 13F0080F tst r3, #8 + 789 0224 00F08C80 beq .L55 + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + 790 .loc 1 458 5 is_stmt 1 view .LVU229 + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSI State */ + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 791 .loc 1 461 5 view .LVU230 + 792 .loc 1 461 25 is_stmt 0 view .LVU231 + 793 0228 A369 ldr r3, [r4, #24] + 794 .loc 1 461 7 view .LVU232 + 795 022a 002B cmp r3, #0 + 796 022c 60D0 beq .L56 + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (LSI). */ + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSI_ENABLE(); + 797 .loc 1 464 7 is_stmt 1 view .LVU233 + ARM GAS /tmp/cczyIHoC.s page 43 + + + 798 .LVL53: + 799 .LBB194: + 800 .LBI194: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 801 .loc 2 981 31 view .LVU234 + 802 .LBB195: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 803 .loc 2 983 3 view .LVU235 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 804 .loc 2 988 4 view .LVU236 + 805 022e 0121 movs r1, #1 + 806 .syntax unified + 807 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 808 0230 91FAA1F2 rbit r2, r1 + 809 @ 0 "" 2 + 810 .LVL54: + 811 .loc 2 1001 3 view .LVU237 + 812 .loc 2 1001 3 is_stmt 0 view .LVU238 + 813 .thumb + 814 .syntax unified + 815 .LBE195: + 816 .LBE194: + 817 .loc 1 464 7 view .LVU239 + 818 0234 B2FA82F2 clz r2, r2 + 819 0238 2C4B ldr r3, .L132+4 + 820 023a 1344 add r3, r3, r2 + 821 023c 9B00 lsls r3, r3, #2 + 822 023e 1960 str r1, [r3] + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 823 .loc 1 467 7 is_stmt 1 view .LVU240 + 824 .loc 1 467 19 is_stmt 0 view .LVU241 + 825 0240 FFF7FEFF bl HAL_GetTick + 826 .LVL55: + 827 0244 0546 mov r5, r0 + 828 .LVL56: + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSI is ready */ + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 829 .loc 1 470 7 is_stmt 1 view .LVU242 + 830 .L57: + 831 .loc 1 470 49 view .LVU243 + 832 .LBB196: + 833 .LBI196: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 834 .loc 2 981 31 view .LVU244 + 835 .LBB197: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 836 .loc 2 983 3 view .LVU245 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 837 .loc 2 988 4 view .LVU246 + 838 0246 0223 movs r3, #2 + 839 .syntax unified + 840 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 841 0248 93FAA3F2 rbit r2, r3 + 842 @ 0 "" 2 + ARM GAS /tmp/cczyIHoC.s page 44 + + + 843 .LVL57: + 844 .loc 2 1001 3 view .LVU247 + 845 .loc 2 1001 3 is_stmt 0 view .LVU248 + 846 .thumb + 847 .syntax unified + 848 .LBE197: + 849 .LBE196: + 850 .LBB198: + 851 .LBI198: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 852 .loc 2 981 31 is_stmt 1 view .LVU249 + 853 .LBB199: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 854 .loc 2 983 3 view .LVU250 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 855 .loc 2 988 4 view .LVU251 + 856 .syntax unified + 857 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 858 024c 93FAA3F2 rbit r2, r3 + 859 @ 0 "" 2 + 860 .LVL58: + 861 .loc 2 1001 3 view .LVU252 + 862 .loc 2 1001 3 is_stmt 0 view .LVU253 + 863 .thumb + 864 .syntax unified + 865 .LBE199: + 866 .LBE198: + 867 .LBB200: + 868 .LBI200: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 869 .loc 2 981 31 is_stmt 1 view .LVU254 + 870 .LBB201: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871 .loc 2 983 3 view .LVU255 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 872 .loc 2 988 4 view .LVU256 + 873 .syntax unified + 874 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 875 0250 93FAA3F2 rbit r2, r3 + 876 @ 0 "" 2 + 877 .LVL59: + 878 .loc 2 1001 3 view .LVU257 + 879 .loc 2 1001 3 is_stmt 0 view .LVU258 + 880 .thumb + 881 .syntax unified + 882 .LBE201: + 883 .LBE200: + 884 .loc 1 470 13 view .LVU259 + 885 0254 244A ldr r2, .L132 + 886 0256 516A ldr r1, [r2, #36] + 887 .LVL60: + 888 .LBB202: + 889 .LBI202: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890 .loc 2 981 31 is_stmt 1 view .LVU260 + 891 .LBB203: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cczyIHoC.s page 45 + + + 892 .loc 2 983 3 view .LVU261 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 893 .loc 2 988 4 view .LVU262 + 894 .syntax unified + 895 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 896 0258 93FAA3F3 rbit r3, r3 + 897 @ 0 "" 2 + 898 .LVL61: + 899 .loc 2 1001 3 view .LVU263 + 900 .loc 2 1001 3 is_stmt 0 view .LVU264 + 901 .thumb + 902 .syntax unified + 903 .LBE203: + 904 .LBE202: + 905 .loc 1 470 13 view .LVU265 + 906 025c B3FA83F3 clz r3, r3 + 907 0260 03F01F03 and r3, r3, #31 + 908 0264 0122 movs r2, #1 + 909 0266 02FA03F3 lsl r3, r2, r3 + 910 .loc 1 470 49 view .LVU266 + 911 026a 0B42 tst r3, r1 + 912 026c 68D1 bne .L55 + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 913 .loc 1 472 9 is_stmt 1 view .LVU267 + 914 .loc 1 472 13 is_stmt 0 view .LVU268 + 915 026e FFF7FEFF bl HAL_GetTick + 916 .LVL62: + 917 .loc 1 472 27 view .LVU269 + 918 0272 401B subs r0, r0, r5 + 919 .loc 1 472 11 view .LVU270 + 920 0274 0228 cmp r0, #2 + 921 0276 E6D9 bls .L57 + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 922 .loc 1 474 18 view .LVU271 + 923 0278 0320 movs r0, #3 + 924 027a CEE1 b .L21 + 925 .L122: + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 926 .loc 1 433 9 is_stmt 1 view .LVU272 + 927 027c 1A48 ldr r0, .L132 + 928 027e 0368 ldr r3, [r0] + 929 0280 23F0F803 bic r3, r3, #248 + 930 0284 6169 ldr r1, [r4, #20] + 931 .LVL63: + 932 .LBB204: + 933 .LBI204: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 934 .loc 2 981 31 view .LVU273 + 935 .LBB205: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 936 .loc 2 983 3 view .LVU274 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 937 .loc 2 988 4 view .LVU275 + 938 0286 F822 movs r2, #248 + 939 .syntax unified + ARM GAS /tmp/cczyIHoC.s page 46 + + + 940 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 941 0288 92FAA2F2 rbit r2, r2 + 942 @ 0 "" 2 + 943 .LVL64: + 944 .loc 2 1001 3 view .LVU276 + 945 .loc 2 1001 3 is_stmt 0 view .LVU277 + 946 .thumb + 947 .syntax unified + 948 .LBE205: + 949 .LBE204: + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 950 .loc 1 433 9 view .LVU278 + 951 028c B2FA82F2 clz r2, r2 + 952 0290 9140 lsls r1, r1, r2 + 953 0292 0B43 orrs r3, r3, r1 + 954 0294 0360 str r3, [r0] + 955 0296 C2E7 b .L40 + 956 .LVL65: + 957 .L46: + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 958 .loc 1 438 9 is_stmt 1 view .LVU279 + 959 .LBB206: + 960 .LBI206: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 961 .loc 2 981 31 view .LVU280 + 962 .LBB207: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 963 .loc 2 983 3 view .LVU281 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 964 .loc 2 988 4 view .LVU282 + 965 0298 0123 movs r3, #1 + 966 .syntax unified + 967 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 968 029a 93FAA3F3 rbit r3, r3 + 969 @ 0 "" 2 + 970 .LVL66: + 971 .loc 2 1001 3 view .LVU283 + 972 .loc 2 1001 3 is_stmt 0 view .LVU284 + 973 .thumb + 974 .syntax unified + 975 .LBE207: + 976 .LBE206: + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 977 .loc 1 438 9 view .LVU285 + 978 029e B3FA83F3 clz r3, r3 + 979 02a2 03F18453 add r3, r3, #276824064 + 980 02a6 03F58413 add r3, r3, #1081344 + 981 02aa 9B00 lsls r3, r3, #2 + 982 02ac 0022 movs r2, #0 + 983 02ae 1A60 str r2, [r3] + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 984 .loc 1 441 9 is_stmt 1 view .LVU286 + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 985 .loc 1 441 21 is_stmt 0 view .LVU287 + 986 02b0 FFF7FEFF bl HAL_GetTick + 987 .LVL67: + 988 02b4 0546 mov r5, r0 + ARM GAS /tmp/cczyIHoC.s page 47 + + + 989 .LVL68: + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 990 .loc 1 444 9 is_stmt 1 view .LVU288 + 991 .L51: + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 992 .loc 1 444 51 view .LVU289 + 993 .LBB208: + 994 .LBI208: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995 .loc 2 981 31 view .LVU290 + 996 .LBB209: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 997 .loc 2 983 3 view .LVU291 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 998 .loc 2 988 4 view .LVU292 + 999 02b6 0223 movs r3, #2 + 1000 .syntax unified + 1001 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1002 02b8 93FAA3F3 rbit r3, r3 + 1003 @ 0 "" 2 + 1004 .loc 2 1001 3 view .LVU293 + 1005 .LVL69: + 1006 .loc 2 1001 3 is_stmt 0 view .LVU294 + 1007 .thumb + 1008 .syntax unified + 1009 .LBE209: + 1010 .LBE208: + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1011 .loc 1 444 15 view .LVU295 + 1012 02bc 0A4B ldr r3, .L132 + 1013 02be 1968 ldr r1, [r3] + 1014 .LVL70: + 1015 .LBB210: + 1016 .LBI210: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1017 .loc 2 981 31 is_stmt 1 view .LVU296 + 1018 .LBB211: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1019 .loc 2 983 3 view .LVU297 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1020 .loc 2 988 4 view .LVU298 + 1021 02c0 0223 movs r3, #2 + 1022 .syntax unified + 1023 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1024 02c2 93FAA3F3 rbit r3, r3 + 1025 @ 0 "" 2 + 1026 .LVL71: + 1027 .loc 2 1001 3 view .LVU299 + 1028 .loc 2 1001 3 is_stmt 0 view .LVU300 + 1029 .thumb + 1030 .syntax unified + 1031 .LBE211: + 1032 .LBE210: + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1033 .loc 1 444 15 view .LVU301 + 1034 02c6 B3FA83F3 clz r3, r3 + 1035 02ca 03F01F03 and r3, r3, #31 + ARM GAS /tmp/cczyIHoC.s page 48 + + + 1036 02ce 0122 movs r2, #1 + 1037 02d0 02FA03F3 lsl r3, r2, r3 + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1038 .loc 1 444 51 view .LVU302 + 1039 02d4 0B42 tst r3, r1 + 1040 02d6 A2D0 beq .L40 + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1041 .loc 1 446 11 is_stmt 1 view .LVU303 + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1042 .loc 1 446 15 is_stmt 0 view .LVU304 + 1043 02d8 FFF7FEFF bl HAL_GetTick + 1044 .LVL72: + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1045 .loc 1 446 29 view .LVU305 + 1046 02dc 401B subs r0, r0, r5 + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1047 .loc 1 446 13 view .LVU306 + 1048 02de 0228 cmp r0, #2 + 1049 02e0 E9D9 bls .L51 + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1050 .loc 1 448 20 view .LVU307 + 1051 02e2 0320 movs r0, #3 + 1052 02e4 99E1 b .L21 + 1053 .L133: + 1054 02e6 00BF .align 2 + 1055 .L132: + 1056 02e8 00100240 .word 1073876992 + 1057 02ec 20819010 .word 277905696 + 1058 .LVL73: + 1059 .L56: + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (LSI). */ + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSI_DISABLE(); + 1060 .loc 1 481 7 is_stmt 1 view .LVU308 + 1061 .LBB212: + 1062 .LBI212: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1063 .loc 2 981 31 view .LVU309 + 1064 .LBB213: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1065 .loc 2 983 3 view .LVU310 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1066 .loc 2 988 4 view .LVU311 + 1067 02f0 0122 movs r2, #1 + 1068 .syntax unified + 1069 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1070 02f2 92FAA2F2 rbit r2, r2 + 1071 @ 0 "" 2 + 1072 .LVL74: + 1073 .loc 2 1001 3 view .LVU312 + 1074 .loc 2 1001 3 is_stmt 0 view .LVU313 + 1075 .thumb + 1076 .syntax unified + ARM GAS /tmp/cczyIHoC.s page 49 + + + 1077 .LBE213: + 1078 .LBE212: + 1079 .loc 1 481 7 view .LVU314 + 1080 02f6 B2FA82F2 clz r2, r2 + 1081 02fa B74B ldr r3, .L134 + 1082 02fc 1344 add r3, r3, r2 + 1083 02fe 9B00 lsls r3, r3, #2 + 1084 0300 0022 movs r2, #0 + 1085 0302 1A60 str r2, [r3] + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1086 .loc 1 484 7 is_stmt 1 view .LVU315 + 1087 .loc 1 484 19 is_stmt 0 view .LVU316 + 1088 0304 FFF7FEFF bl HAL_GetTick + 1089 .LVL75: + 1090 0308 0546 mov r5, r0 + 1091 .LVL76: + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSI is disabled */ + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 1092 .loc 1 487 7 is_stmt 1 view .LVU317 + 1093 .L59: + 1094 .loc 1 487 49 view .LVU318 + 1095 .LBB214: + 1096 .LBI214: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1097 .loc 2 981 31 view .LVU319 + 1098 .LBB215: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1099 .loc 2 983 3 view .LVU320 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1100 .loc 2 988 4 view .LVU321 + 1101 030a 0223 movs r3, #2 + 1102 .syntax unified + 1103 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1104 030c 93FAA3F2 rbit r2, r3 + 1105 @ 0 "" 2 + 1106 .LVL77: + 1107 .loc 2 1001 3 view .LVU322 + 1108 .loc 2 1001 3 is_stmt 0 view .LVU323 + 1109 .thumb + 1110 .syntax unified + 1111 .LBE215: + 1112 .LBE214: + 1113 .LBB216: + 1114 .LBI216: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1115 .loc 2 981 31 is_stmt 1 view .LVU324 + 1116 .LBB217: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1117 .loc 2 983 3 view .LVU325 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1118 .loc 2 988 4 view .LVU326 + 1119 .syntax unified + 1120 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1121 0310 93FAA3F2 rbit r2, r3 + ARM GAS /tmp/cczyIHoC.s page 50 + + + 1122 @ 0 "" 2 + 1123 .LVL78: + 1124 .loc 2 1001 3 view .LVU327 + 1125 .loc 2 1001 3 is_stmt 0 view .LVU328 + 1126 .thumb + 1127 .syntax unified + 1128 .LBE217: + 1129 .LBE216: + 1130 .LBB218: + 1131 .LBI218: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1132 .loc 2 981 31 is_stmt 1 view .LVU329 + 1133 .LBB219: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1134 .loc 2 983 3 view .LVU330 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1135 .loc 2 988 4 view .LVU331 + 1136 .syntax unified + 1137 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1138 0314 93FAA3F2 rbit r2, r3 + 1139 @ 0 "" 2 + 1140 .LVL79: + 1141 .loc 2 1001 3 view .LVU332 + 1142 .loc 2 1001 3 is_stmt 0 view .LVU333 + 1143 .thumb + 1144 .syntax unified + 1145 .LBE219: + 1146 .LBE218: + 1147 .loc 1 487 13 view .LVU334 + 1148 0318 B04A ldr r2, .L134+4 + 1149 031a 516A ldr r1, [r2, #36] + 1150 .LVL80: + 1151 .LBB220: + 1152 .LBI220: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1153 .loc 2 981 31 is_stmt 1 view .LVU335 + 1154 .LBB221: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1155 .loc 2 983 3 view .LVU336 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1156 .loc 2 988 4 view .LVU337 + 1157 .syntax unified + 1158 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1159 031c 93FAA3F3 rbit r3, r3 + 1160 @ 0 "" 2 + 1161 .LVL81: + 1162 .loc 2 1001 3 view .LVU338 + 1163 .loc 2 1001 3 is_stmt 0 view .LVU339 + 1164 .thumb + 1165 .syntax unified + 1166 .LBE221: + 1167 .LBE220: + 1168 .loc 1 487 13 view .LVU340 + 1169 0320 B3FA83F3 clz r3, r3 + 1170 0324 03F01F03 and r3, r3, #31 + 1171 0328 0122 movs r2, #1 + 1172 032a 02FA03F3 lsl r3, r2, r3 + ARM GAS /tmp/cczyIHoC.s page 51 + + + 1173 .loc 1 487 49 view .LVU341 + 1174 032e 0B42 tst r3, r1 + 1175 0330 06D0 beq .L55 + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 1176 .loc 1 489 9 is_stmt 1 view .LVU342 + 1177 .loc 1 489 13 is_stmt 0 view .LVU343 + 1178 0332 FFF7FEFF bl HAL_GetTick + 1179 .LVL82: + 1180 .loc 1 489 27 view .LVU344 + 1181 0336 401B subs r0, r0, r5 + 1182 .loc 1 489 11 view .LVU345 + 1183 0338 0228 cmp r0, #2 + 1184 033a E6D9 bls .L59 + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 1185 .loc 1 491 18 view .LVU346 + 1186 033c 0320 movs r0, #3 + 1187 033e 6CE1 b .L21 + 1188 .LVL83: + 1189 .L55: + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------ LSE Configuration -------------------------*/ + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 1190 .loc 1 497 3 is_stmt 1 view .LVU347 + 1191 .loc 1 497 25 is_stmt 0 view .LVU348 + 1192 0340 2368 ldr r3, [r4] + 1193 .loc 1 497 5 view .LVU349 + 1194 0342 13F0040F tst r3, #4 + 1195 0346 00F0A980 beq .L61 + 1196 .LBB222: + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** FlagStatus pwrclkchanged = RESET; + 1197 .loc 1 499 5 is_stmt 1 view .LVU350 + 1198 .LVL84: + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + 1199 .loc 1 502 5 view .LVU351 + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update LSE configuration in Backup Domain control register */ + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Requires to enable write access to Backup Domain of necessary */ + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 1200 .loc 1 506 5 view .LVU352 + 1201 .loc 1 506 8 is_stmt 0 view .LVU353 + 1202 034a A44B ldr r3, .L134+4 + 1203 034c DB69 ldr r3, [r3, #28] + 1204 .loc 1 506 7 view .LVU354 + 1205 034e 13F0805F tst r3, #268435456 + 1206 0352 20D1 bne .L103 + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 1207 .loc 1 508 7 is_stmt 1 view .LVU355 + 1208 .LBB223: + ARM GAS /tmp/cczyIHoC.s page 52 + + + 1209 .loc 1 508 7 view .LVU356 + 1210 .loc 1 508 7 view .LVU357 + 1211 0354 A14B ldr r3, .L134+4 + 1212 0356 DA69 ldr r2, [r3, #28] + 1213 0358 42F08052 orr r2, r2, #268435456 + 1214 035c DA61 str r2, [r3, #28] + 1215 .loc 1 508 7 view .LVU358 + 1216 035e DB69 ldr r3, [r3, #28] + 1217 0360 03F08053 and r3, r3, #268435456 + 1218 0364 0193 str r3, [sp, #4] + 1219 .loc 1 508 7 view .LVU359 + 1220 0366 019B ldr r3, [sp, #4] + 1221 .LBE223: + 1222 .loc 1 508 7 view .LVU360 + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pwrclkchanged = SET; + 1223 .loc 1 509 7 view .LVU361 + 1224 .LVL85: + 1225 .loc 1 509 21 is_stmt 0 view .LVU362 + 1226 0368 0125 movs r5, #1 + 1227 .LVL86: + 1228 .L62: + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 1229 .loc 1 512 5 is_stmt 1 view .LVU363 + 1230 .loc 1 512 8 is_stmt 0 view .LVU364 + 1231 036a 9D4B ldr r3, .L134+8 + 1232 036c 1B68 ldr r3, [r3] + 1233 .loc 1 512 7 view .LVU365 + 1234 036e 13F4807F tst r3, #256 + 1235 0372 12D0 beq .L124 + 1236 .L63: + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable write access to Backup domain */ + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait for Backup domain Write protection disable */ + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set the new LSE configuration -----------------------------------------*/ + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 1237 .loc 1 530 5 is_stmt 1 view .LVU366 + 1238 .loc 1 530 5 view .LVU367 + 1239 0374 E368 ldr r3, [r4, #12] + 1240 0376 012B cmp r3, #1 + 1241 0378 23D0 beq .L125 + 1242 .loc 1 530 5 discriminator 2 view .LVU368 + 1243 037a 73BB cbnz r3, .L68 + ARM GAS /tmp/cczyIHoC.s page 53 + + + 1244 .loc 1 530 5 discriminator 4 view .LVU369 + 1245 037c 03F18043 add r3, r3, #1073741824 + 1246 0380 03F50433 add r3, r3, #135168 + 1247 0384 1A6A ldr r2, [r3, #32] + 1248 0386 22F00102 bic r2, r2, #1 + 1249 038a 1A62 str r2, [r3, #32] + 1250 .loc 1 530 5 discriminator 4 view .LVU370 + 1251 038c 1A6A ldr r2, [r3, #32] + 1252 038e 22F00402 bic r2, r2, #4 + 1253 0392 1A62 str r2, [r3, #32] + 1254 0394 1AE0 b .L67 + 1255 .LVL87: + 1256 .L103: + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1257 .loc 1 499 22 is_stmt 0 view .LVU371 + 1258 0396 0025 movs r5, #0 + 1259 0398 E7E7 b .L62 + 1260 .LVL88: + 1261 .L124: + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1262 .loc 1 515 7 is_stmt 1 view .LVU372 + 1263 039a 914A ldr r2, .L134+8 + 1264 039c 1368 ldr r3, [r2] + 1265 039e 43F48073 orr r3, r3, #256 + 1266 03a2 1360 str r3, [r2] + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1267 .loc 1 518 7 view .LVU373 + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1268 .loc 1 518 19 is_stmt 0 view .LVU374 + 1269 03a4 FFF7FEFF bl HAL_GetTick + 1270 .LVL89: + 1271 03a8 0646 mov r6, r0 + 1272 .LVL90: + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1273 .loc 1 520 7 is_stmt 1 view .LVU375 + 1274 .L64: + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1275 .loc 1 520 13 view .LVU376 + 1276 03aa 8D4B ldr r3, .L134+8 + 1277 03ac 1B68 ldr r3, [r3] + 1278 03ae 13F4807F tst r3, #256 + 1279 03b2 DFD1 bne .L63 + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1280 .loc 1 522 9 view .LVU377 + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1281 .loc 1 522 13 is_stmt 0 view .LVU378 + 1282 03b4 FFF7FEFF bl HAL_GetTick + 1283 .LVL91: + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1284 .loc 1 522 27 view .LVU379 + 1285 03b8 801B subs r0, r0, r6 + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1286 .loc 1 522 11 view .LVU380 + 1287 03ba 6428 cmp r0, #100 + 1288 03bc F5D9 bls .L64 + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1289 .loc 1 524 18 view .LVU381 + ARM GAS /tmp/cczyIHoC.s page 54 + + + 1290 03be 0320 movs r0, #3 + 1291 03c0 2BE1 b .L21 + 1292 .LVL92: + 1293 .L125: + 1294 .loc 1 530 5 is_stmt 1 discriminator 1 view .LVU382 + 1295 03c2 864A ldr r2, .L134+4 + 1296 03c4 136A ldr r3, [r2, #32] + 1297 03c6 43F00103 orr r3, r3, #1 + 1298 03ca 1362 str r3, [r2, #32] + 1299 .L67: + 1300 .loc 1 530 5 discriminator 10 view .LVU383 + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */ + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 1301 .loc 1 532 5 discriminator 10 view .LVU384 + 1302 .loc 1 532 25 is_stmt 0 discriminator 10 view .LVU385 + 1303 03cc E368 ldr r3, [r4, #12] + 1304 .loc 1 532 7 discriminator 10 view .LVU386 + 1305 03ce 002B cmp r3, #0 + 1306 03d0 3CD0 beq .L70 + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1307 .loc 1 535 7 is_stmt 1 view .LVU387 + 1308 .loc 1 535 19 is_stmt 0 view .LVU388 + 1309 03d2 FFF7FEFF bl HAL_GetTick + 1310 .LVL93: + 1311 03d6 0646 mov r6, r0 + 1312 .LVL94: + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSE is ready */ + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 1313 .loc 1 538 7 is_stmt 1 view .LVU389 + 1314 .loc 1 538 12 is_stmt 0 view .LVU390 + 1315 03d8 2EE0 b .L71 + 1316 .LVL95: + 1317 .L68: + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */ + 1318 .loc 1 530 5 is_stmt 1 discriminator 5 view .LVU391 + 1319 03da 052B cmp r3, #5 + 1320 03dc 09D0 beq .L126 + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */ + 1321 .loc 1 530 5 discriminator 8 view .LVU392 + 1322 03de 7F4B ldr r3, .L134+4 + 1323 03e0 1A6A ldr r2, [r3, #32] + 1324 03e2 22F00102 bic r2, r2, #1 + 1325 03e6 1A62 str r2, [r3, #32] + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */ + 1326 .loc 1 530 5 discriminator 8 view .LVU393 + 1327 03e8 1A6A ldr r2, [r3, #32] + 1328 03ea 22F00402 bic r2, r2, #4 + 1329 03ee 1A62 str r2, [r3, #32] + 1330 03f0 ECE7 b .L67 + 1331 .L126: + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */ + 1332 .loc 1 530 5 discriminator 7 view .LVU394 + 1333 03f2 7A4B ldr r3, .L134+4 + 1334 03f4 1A6A ldr r2, [r3, #32] + ARM GAS /tmp/cczyIHoC.s page 55 + + + 1335 03f6 42F00402 orr r2, r2, #4 + 1336 03fa 1A62 str r2, [r3, #32] + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */ + 1337 .loc 1 530 5 discriminator 7 view .LVU395 + 1338 03fc 1A6A ldr r2, [r3, #32] + 1339 03fe 42F00102 orr r2, r2, #1 + 1340 0402 1A62 str r2, [r3, #32] + 1341 0404 E2E7 b .L67 + 1342 .LVL96: + 1343 .L72: + 1344 .LBB224: + 1345 .LBI224: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1346 .loc 2 981 31 view .LVU396 + 1347 .LBB225: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1348 .loc 2 983 3 view .LVU397 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1349 .loc 2 988 4 view .LVU398 + 1350 0406 0223 movs r3, #2 + 1351 .syntax unified + 1352 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1353 0408 93FAA3F3 rbit r3, r3 + 1354 @ 0 "" 2 + 1355 .LVL97: + 1356 .loc 2 1001 3 view .LVU399 + 1357 .loc 2 1001 3 is_stmt 0 view .LVU400 + 1358 .thumb + 1359 .syntax unified + 1360 .LBE225: + 1361 .LBE224: + 1362 .loc 1 538 13 view .LVU401 + 1363 040c 734B ldr r3, .L134+4 + 1364 040e 596A ldr r1, [r3, #36] + 1365 .L73: + 1366 .LVL98: + 1367 .LBB226: + 1368 .LBI226: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1369 .loc 2 981 31 is_stmt 1 discriminator 11 view .LVU402 + 1370 .LBB227: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1371 .loc 2 983 3 discriminator 11 view .LVU403 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1372 .loc 2 988 4 discriminator 11 view .LVU404 + 1373 0410 0223 movs r3, #2 + 1374 .syntax unified + 1375 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1376 0412 93FAA3F3 rbit r3, r3 + 1377 @ 0 "" 2 + 1378 .LVL99: + 1379 .loc 2 1001 3 discriminator 11 view .LVU405 + 1380 .loc 2 1001 3 is_stmt 0 discriminator 11 view .LVU406 + 1381 .thumb + 1382 .syntax unified + 1383 .LBE227: + 1384 .LBE226: + ARM GAS /tmp/cczyIHoC.s page 56 + + + 1385 .loc 1 538 13 discriminator 11 view .LVU407 + 1386 0416 B3FA83F3 clz r3, r3 + 1387 041a 03F01F03 and r3, r3, #31 + 1388 041e 0122 movs r2, #1 + 1389 0420 02FA03F3 lsl r3, r2, r3 + 1390 .loc 1 538 49 discriminator 11 view .LVU408 + 1391 0424 1942 tst r1, r3 + 1392 0426 38D1 bne .L75 + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 1393 .loc 1 540 9 is_stmt 1 view .LVU409 + 1394 .loc 1 540 13 is_stmt 0 view .LVU410 + 1395 0428 FFF7FEFF bl HAL_GetTick + 1396 .LVL100: + 1397 .loc 1 540 27 view .LVU411 + 1398 042c 801B subs r0, r0, r6 + 1399 .loc 1 540 11 view .LVU412 + 1400 042e 41F28833 movw r3, #5000 + 1401 0432 9842 cmp r0, r3 + 1402 0434 00F2EC80 bhi .L105 + 1403 .L71: + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1404 .loc 1 538 49 is_stmt 1 view .LVU413 + 1405 .LVL101: + 1406 .LBB228: + 1407 .LBI228: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1408 .loc 2 981 31 view .LVU414 + 1409 .LBB229: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1410 .loc 2 983 3 view .LVU415 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1411 .loc 2 988 4 view .LVU416 + 1412 0438 0223 movs r3, #2 + 1413 .syntax unified + 1414 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1415 043a 93FAA3F2 rbit r2, r3 + 1416 @ 0 "" 2 + 1417 .LVL102: + 1418 .loc 2 1001 3 view .LVU417 + 1419 .loc 2 1001 3 is_stmt 0 view .LVU418 + 1420 .thumb + 1421 .syntax unified + 1422 .LBE229: + 1423 .LBE228: + 1424 .LBB230: + 1425 .LBI230: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1426 .loc 2 981 31 is_stmt 1 view .LVU419 + 1427 .LBB231: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1428 .loc 2 983 3 view .LVU420 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1429 .loc 2 988 4 view .LVU421 + 1430 .syntax unified + 1431 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1432 043e 93FAA3F3 rbit r3, r3 + ARM GAS /tmp/cczyIHoC.s page 57 + + + 1433 @ 0 "" 2 + 1434 .LVL103: + 1435 .loc 2 1001 3 view .LVU422 + 1436 .loc 2 1001 3 is_stmt 0 view .LVU423 + 1437 .thumb + 1438 .syntax unified + 1439 .LBE231: + 1440 .LBE230: + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1441 .loc 1 538 13 view .LVU424 + 1442 0442 002B cmp r3, #0 + 1443 0444 DFD0 beq .L72 + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1444 .loc 1 538 13 discriminator 4 view .LVU425 + 1445 0446 654B ldr r3, .L134+4 + 1446 0448 196A ldr r1, [r3, #32] + 1447 044a E1E7 b .L73 + 1448 .LVL104: + 1449 .L70: + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1450 .loc 1 549 7 is_stmt 1 view .LVU426 + 1451 .loc 1 549 19 is_stmt 0 view .LVU427 + 1452 044c FFF7FEFF bl HAL_GetTick + 1453 .LVL105: + 1454 0450 0646 mov r6, r0 + 1455 .LVL106: + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSE is disabled */ + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 1456 .loc 1 552 7 is_stmt 1 view .LVU428 + 1457 .loc 1 552 12 is_stmt 0 view .LVU429 + 1458 0452 18E0 b .L76 + 1459 .LVL107: + 1460 .L77: + 1461 .LBB232: + 1462 .LBI232: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1463 .loc 2 981 31 is_stmt 1 view .LVU430 + 1464 .LBB233: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1465 .loc 2 983 3 view .LVU431 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1466 .loc 2 988 4 view .LVU432 + 1467 0454 0223 movs r3, #2 + 1468 .syntax unified + 1469 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1470 0456 93FAA3F3 rbit r3, r3 + 1471 @ 0 "" 2 + 1472 .LVL108: + ARM GAS /tmp/cczyIHoC.s page 58 + + + 1473 .loc 2 1001 3 view .LVU433 + 1474 .loc 2 1001 3 is_stmt 0 view .LVU434 + 1475 .thumb + 1476 .syntax unified + 1477 .LBE233: + 1478 .LBE232: + 1479 .loc 1 552 13 view .LVU435 + 1480 045a 604B ldr r3, .L134+4 + 1481 045c 596A ldr r1, [r3, #36] + 1482 .L78: + 1483 .LVL109: + 1484 .LBB234: + 1485 .LBI234: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1486 .loc 2 981 31 is_stmt 1 discriminator 11 view .LVU436 + 1487 .LBB235: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1488 .loc 2 983 3 discriminator 11 view .LVU437 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1489 .loc 2 988 4 discriminator 11 view .LVU438 + 1490 045e 0223 movs r3, #2 + 1491 .syntax unified + 1492 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1493 0460 93FAA3F3 rbit r3, r3 + 1494 @ 0 "" 2 + 1495 .LVL110: + 1496 .loc 2 1001 3 discriminator 11 view .LVU439 + 1497 .loc 2 1001 3 is_stmt 0 discriminator 11 view .LVU440 + 1498 .thumb + 1499 .syntax unified + 1500 .LBE235: + 1501 .LBE234: + 1502 .loc 1 552 13 discriminator 11 view .LVU441 + 1503 0464 B3FA83F3 clz r3, r3 + 1504 0468 03F01F03 and r3, r3, #31 + 1505 046c 0122 movs r2, #1 + 1506 046e 02FA03F3 lsl r3, r2, r3 + 1507 .loc 1 552 49 discriminator 11 view .LVU442 + 1508 0472 1942 tst r1, r3 + 1509 0474 11D0 beq .L75 + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 1510 .loc 1 554 9 is_stmt 1 view .LVU443 + 1511 .loc 1 554 13 is_stmt 0 view .LVU444 + 1512 0476 FFF7FEFF bl HAL_GetTick + 1513 .LVL111: + 1514 .loc 1 554 27 view .LVU445 + 1515 047a 801B subs r0, r0, r6 + 1516 .loc 1 554 11 view .LVU446 + 1517 047c 41F28833 movw r3, #5000 + 1518 0480 9842 cmp r0, r3 + 1519 0482 00F2C780 bhi .L106 + 1520 .L76: + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1521 .loc 1 552 49 is_stmt 1 view .LVU447 + 1522 .LVL112: + 1523 .LBB236: + ARM GAS /tmp/cczyIHoC.s page 59 + + + 1524 .LBI236: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1525 .loc 2 981 31 view .LVU448 + 1526 .LBB237: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1527 .loc 2 983 3 view .LVU449 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1528 .loc 2 988 4 view .LVU450 + 1529 0486 0223 movs r3, #2 + 1530 .syntax unified + 1531 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1532 0488 93FAA3F2 rbit r2, r3 + 1533 @ 0 "" 2 + 1534 .LVL113: + 1535 .loc 2 1001 3 view .LVU451 + 1536 .loc 2 1001 3 is_stmt 0 view .LVU452 + 1537 .thumb + 1538 .syntax unified + 1539 .LBE237: + 1540 .LBE236: + 1541 .LBB238: + 1542 .LBI238: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1543 .loc 2 981 31 is_stmt 1 view .LVU453 + 1544 .LBB239: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1545 .loc 2 983 3 view .LVU454 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1546 .loc 2 988 4 view .LVU455 + 1547 .syntax unified + 1548 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1549 048c 93FAA3F3 rbit r3, r3 + 1550 @ 0 "" 2 + 1551 .LVL114: + 1552 .loc 2 1001 3 view .LVU456 + 1553 .loc 2 1001 3 is_stmt 0 view .LVU457 + 1554 .thumb + 1555 .syntax unified + 1556 .LBE239: + 1557 .LBE238: + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1558 .loc 1 552 13 view .LVU458 + 1559 0490 002B cmp r3, #0 + 1560 0492 DFD0 beq .L77 + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1561 .loc 1 552 13 discriminator 4 view .LVU459 + 1562 0494 514B ldr r3, .L134+4 + 1563 0496 196A ldr r1, [r3, #32] + 1564 0498 E1E7 b .L78 + 1565 .L75: + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Require to disable power clock if necessary */ + ARM GAS /tmp/cczyIHoC.s page 60 + + + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(pwrclkchanged == SET) + 1566 .loc 1 562 5 is_stmt 1 view .LVU460 + 1567 .loc 1 562 7 is_stmt 0 view .LVU461 + 1568 049a B5BB cbnz r5, .L127 + 1569 .LVL115: + 1570 .L61: + 1571 .loc 1 562 7 view .LVU462 + 1572 .LBE222: + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------------- PLL Configuration -----------------------*/ + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + 1573 .loc 1 570 3 is_stmt 1 view .LVU463 + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 1574 .loc 1 571 3 view .LVU464 + 1575 .loc 1 571 30 is_stmt 0 view .LVU465 + 1576 049c E369 ldr r3, [r4, #28] + 1577 .loc 1 571 6 view .LVU466 + 1578 049e 002B cmp r3, #0 + 1579 04a0 00F0BA80 beq .L107 + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if the PLL is used as system clock or not */ + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 1580 .loc 1 574 5 is_stmt 1 view .LVU467 + 1581 .loc 1 574 8 is_stmt 0 view .LVU468 + 1582 04a4 4D4A ldr r2, .L134+4 + 1583 04a6 5268 ldr r2, [r2, #4] + 1584 04a8 02F00C02 and r2, r2, #12 + 1585 .loc 1 574 7 view .LVU469 + 1586 04ac 082A cmp r2, #8 + 1587 04ae 00F09980 beq .L80 + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 1588 .loc 1 576 7 is_stmt 1 view .LVU470 + 1589 .loc 1 576 9 is_stmt 0 view .LVU471 + 1590 04b2 022B cmp r3, #2 + 1591 04b4 2FD0 beq .L128 + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the main PLL. */ + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + ARM GAS /tmp/cczyIHoC.s page 61 + + + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the main PLL clock source, predivider and multiplication factor. */ + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PREDIV, + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL); + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the main PLL clock source and multiplication factor. */ + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL); + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the main PLL. */ + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_ENABLE(); + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is ready */ + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the main PLL. */ + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 1592 .loc 1 628 9 is_stmt 1 view .LVU472 + 1593 .LVL116: + 1594 .LBB240: + 1595 .LBI240: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1596 .loc 2 981 31 view .LVU473 + 1597 .LBB241: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1598 .loc 2 983 3 view .LVU474 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1599 .loc 2 988 4 view .LVU475 + 1600 04b6 4FF08073 mov r3, #16777216 + 1601 .syntax unified + 1602 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1603 04ba 93FAA3F3 rbit r3, r3 + 1604 @ 0 "" 2 + 1605 .LVL117: + 1606 .loc 2 1001 3 view .LVU476 + 1607 .loc 2 1001 3 is_stmt 0 view .LVU477 + 1608 .thumb + 1609 .syntax unified + ARM GAS /tmp/cczyIHoC.s page 62 + + + 1610 .LBE241: + 1611 .LBE240: + 1612 .loc 1 628 9 view .LVU478 + 1613 04be B3FA83F3 clz r3, r3 + 1614 04c2 03F18453 add r3, r3, #276824064 + 1615 04c6 03F58413 add r3, r3, #1081344 + 1616 04ca 9B00 lsls r3, r3, #2 + 1617 04cc 0022 movs r2, #0 + 1618 04ce 1A60 str r2, [r3] + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1619 .loc 1 631 9 is_stmt 1 view .LVU479 + 1620 .loc 1 631 21 is_stmt 0 view .LVU480 + 1621 04d0 FFF7FEFF bl HAL_GetTick + 1622 .LVL118: + 1623 04d4 0446 mov r4, r0 + 1624 .LVL119: + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 1625 .loc 1 634 9 is_stmt 1 view .LVU481 + 1626 .L90: + 1627 .loc 1 634 52 view .LVU482 + 1628 .LBB242: + 1629 .LBI242: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1630 .loc 2 981 31 view .LVU483 + 1631 .LBB243: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1632 .loc 2 983 3 view .LVU484 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1633 .loc 2 988 4 view .LVU485 + 1634 04d6 4FF00073 mov r3, #33554432 + 1635 .syntax unified + 1636 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1637 04da 93FAA3F3 rbit r3, r3 + 1638 @ 0 "" 2 + 1639 .loc 2 1001 3 view .LVU486 + 1640 .LVL120: + 1641 .loc 2 1001 3 is_stmt 0 view .LVU487 + 1642 .thumb + 1643 .syntax unified + 1644 .LBE243: + 1645 .LBE242: + 1646 .loc 1 634 15 view .LVU488 + 1647 04de 3F4B ldr r3, .L134+4 + 1648 04e0 1968 ldr r1, [r3] + 1649 .LVL121: + 1650 .LBB244: + 1651 .LBI244: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1652 .loc 2 981 31 is_stmt 1 view .LVU489 + 1653 .LBB245: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1654 .loc 2 983 3 view .LVU490 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/cczyIHoC.s page 63 + + + 1655 .loc 2 988 4 view .LVU491 + 1656 04e2 4FF00073 mov r3, #33554432 + 1657 .syntax unified + 1658 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1659 04e6 93FAA3F3 rbit r3, r3 + 1660 @ 0 "" 2 + 1661 .LVL122: + 1662 .loc 2 1001 3 view .LVU492 + 1663 .loc 2 1001 3 is_stmt 0 view .LVU493 + 1664 .thumb + 1665 .syntax unified + 1666 .LBE245: + 1667 .LBE244: + 1668 .loc 1 634 15 view .LVU494 + 1669 04ea B3FA83F3 clz r3, r3 + 1670 04ee 03F01F03 and r3, r3, #31 + 1671 04f2 0122 movs r2, #1 + 1672 04f4 02FA03F3 lsl r3, r2, r3 + 1673 .loc 1 634 52 view .LVU495 + 1674 04f8 1942 tst r1, r3 + 1675 04fa 6BD0 beq .L129 + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 1676 .loc 1 636 11 is_stmt 1 view .LVU496 + 1677 .loc 1 636 15 is_stmt 0 view .LVU497 + 1678 04fc FFF7FEFF bl HAL_GetTick + 1679 .LVL123: + 1680 .loc 1 636 29 view .LVU498 + 1681 0500 001B subs r0, r0, r4 + 1682 .loc 1 636 13 view .LVU499 + 1683 0502 0228 cmp r0, #2 + 1684 0504 E7D9 bls .L90 + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 1685 .loc 1 638 20 view .LVU500 + 1686 0506 0320 movs r0, #3 + 1687 0508 87E0 b .L21 + 1688 .LVL124: + 1689 .L127: + 1690 .LBB246: + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1691 .loc 1 564 7 is_stmt 1 view .LVU501 + 1692 050a 344A ldr r2, .L134+4 + 1693 050c D369 ldr r3, [r2, #28] + 1694 050e 23F08053 bic r3, r3, #268435456 + 1695 0512 D361 str r3, [r2, #28] + 1696 0514 C2E7 b .L61 + 1697 .LVL125: + 1698 .L128: + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1699 .loc 1 564 7 is_stmt 0 view .LVU502 + 1700 .LBE246: + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + 1701 .loc 1 579 9 is_stmt 1 view .LVU503 + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 1702 .loc 1 580 9 view .LVU504 + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + ARM GAS /tmp/cczyIHoC.s page 64 + + + 1703 .loc 1 586 9 view .LVU505 + 1704 .LBB247: + 1705 .LBI247: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1706 .loc 2 981 31 view .LVU506 + 1707 .LBB248: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1708 .loc 2 983 3 view .LVU507 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1709 .loc 2 988 4 view .LVU508 + 1710 0516 4FF08073 mov r3, #16777216 + 1711 .syntax unified + 1712 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1713 051a 93FAA3F3 rbit r3, r3 + 1714 @ 0 "" 2 + 1715 .LVL126: + 1716 .loc 2 1001 3 view .LVU509 + 1717 .loc 2 1001 3 is_stmt 0 view .LVU510 + 1718 .thumb + 1719 .syntax unified + 1720 .LBE248: + 1721 .LBE247: + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1722 .loc 1 586 9 view .LVU511 + 1723 051e B3FA83F3 clz r3, r3 + 1724 0522 03F18453 add r3, r3, #276824064 + 1725 0526 03F58413 add r3, r3, #1081344 + 1726 052a 9B00 lsls r3, r3, #2 + 1727 052c 0022 movs r2, #0 + 1728 052e 1A60 str r2, [r3] + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1729 .loc 1 589 9 is_stmt 1 view .LVU512 + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1730 .loc 1 589 21 is_stmt 0 view .LVU513 + 1731 0530 FFF7FEFF bl HAL_GetTick + 1732 .LVL127: + 1733 0534 0546 mov r5, r0 + 1734 .LVL128: + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1735 .loc 1 592 9 is_stmt 1 view .LVU514 + 1736 .L82: + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1737 .loc 1 592 52 view .LVU515 + 1738 .LBB249: + 1739 .LBI249: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1740 .loc 2 981 31 view .LVU516 + 1741 .LBB250: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1742 .loc 2 983 3 view .LVU517 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1743 .loc 2 988 4 view .LVU518 + 1744 0536 4FF00073 mov r3, #33554432 + 1745 .syntax unified + 1746 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1747 053a 93FAA3F3 rbit r3, r3 + 1748 @ 0 "" 2 + ARM GAS /tmp/cczyIHoC.s page 65 + + + 1749 .loc 2 1001 3 view .LVU519 + 1750 .LVL129: + 1751 .loc 2 1001 3 is_stmt 0 view .LVU520 + 1752 .thumb + 1753 .syntax unified + 1754 .LBE250: + 1755 .LBE249: + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1756 .loc 1 592 15 view .LVU521 + 1757 053e 274B ldr r3, .L134+4 + 1758 0540 1968 ldr r1, [r3] + 1759 .LVL130: + 1760 .LBB251: + 1761 .LBI251: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1762 .loc 2 981 31 is_stmt 1 view .LVU522 + 1763 .LBB252: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1764 .loc 2 983 3 view .LVU523 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1765 .loc 2 988 4 view .LVU524 + 1766 0542 4FF00073 mov r3, #33554432 + 1767 .syntax unified + 1768 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1769 0546 93FAA3F3 rbit r3, r3 + 1770 @ 0 "" 2 + 1771 .LVL131: + 1772 .loc 2 1001 3 view .LVU525 + 1773 .loc 2 1001 3 is_stmt 0 view .LVU526 + 1774 .thumb + 1775 .syntax unified + 1776 .LBE252: + 1777 .LBE251: + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1778 .loc 1 592 15 view .LVU527 + 1779 054a B3FA83F3 clz r3, r3 + 1780 054e 03F01F03 and r3, r3, #31 + 1781 0552 0122 movs r2, #1 + 1782 0554 02FA03F3 lsl r3, r2, r3 + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1783 .loc 1 592 52 view .LVU528 + 1784 0558 1942 tst r1, r3 + 1785 055a 06D0 beq .L130 + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1786 .loc 1 594 11 is_stmt 1 view .LVU529 + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1787 .loc 1 594 15 is_stmt 0 view .LVU530 + 1788 055c FFF7FEFF bl HAL_GetTick + 1789 .LVL132: + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1790 .loc 1 594 29 view .LVU531 + 1791 0560 401B subs r0, r0, r5 + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1792 .loc 1 594 13 view .LVU532 + 1793 0562 0228 cmp r0, #2 + 1794 0564 E7D9 bls .L82 + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + ARM GAS /tmp/cczyIHoC.s page 66 + + + 1795 .loc 1 596 20 view .LVU533 + 1796 0566 0320 movs r0, #3 + 1797 0568 57E0 b .L21 + 1798 .L130: + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL); + 1799 .loc 1 607 7 is_stmt 1 view .LVU534 + 1800 056a 1C49 ldr r1, .L134+4 + 1801 056c 4B68 ldr r3, [r1, #4] + 1802 056e 23F47413 bic r3, r3, #3997696 + 1803 0572 626A ldr r2, [r4, #36] + 1804 0574 206A ldr r0, [r4, #32] + 1805 0576 0243 orrs r2, r2, r0 + 1806 0578 1343 orrs r3, r3, r2 + 1807 057a 4B60 str r3, [r1, #4] + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1808 .loc 1 611 9 view .LVU535 + 1809 .LVL133: + 1810 .LBB253: + 1811 .LBI253: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1812 .loc 2 981 31 view .LVU536 + 1813 .LBB254: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1814 .loc 2 983 3 view .LVU537 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1815 .loc 2 988 4 view .LVU538 + 1816 057c 4FF08073 mov r3, #16777216 + 1817 .syntax unified + 1818 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1819 0580 93FAA3F3 rbit r3, r3 + 1820 @ 0 "" 2 + 1821 .LVL134: + 1822 .loc 2 1001 3 view .LVU539 + 1823 .loc 2 1001 3 is_stmt 0 view .LVU540 + 1824 .thumb + 1825 .syntax unified + 1826 .LBE254: + 1827 .LBE253: + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1828 .loc 1 611 9 view .LVU541 + 1829 0584 B3FA83F3 clz r3, r3 + 1830 0588 03F18453 add r3, r3, #276824064 + 1831 058c 03F58413 add r3, r3, #1081344 + 1832 0590 9B00 lsls r3, r3, #2 + 1833 0592 0122 movs r2, #1 + 1834 0594 1A60 str r2, [r3] + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1835 .loc 1 614 9 is_stmt 1 view .LVU542 + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 1836 .loc 1 614 21 is_stmt 0 view .LVU543 + 1837 0596 FFF7FEFF bl HAL_GetTick + 1838 .LVL135: + 1839 059a 0446 mov r4, r0 + 1840 .LVL136: + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1841 .loc 1 617 9 is_stmt 1 view .LVU544 + 1842 .L86: + ARM GAS /tmp/cczyIHoC.s page 67 + + + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1843 .loc 1 617 52 view .LVU545 + 1844 .LBB255: + 1845 .LBI255: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1846 .loc 2 981 31 view .LVU546 + 1847 .LBB256: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1848 .loc 2 983 3 view .LVU547 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1849 .loc 2 988 4 view .LVU548 + 1850 059c 4FF00073 mov r3, #33554432 + 1851 .syntax unified + 1852 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1853 05a0 93FAA3F3 rbit r3, r3 + 1854 @ 0 "" 2 + 1855 .loc 2 1001 3 view .LVU549 + 1856 .LVL137: + 1857 .loc 2 1001 3 is_stmt 0 view .LVU550 + 1858 .thumb + 1859 .syntax unified + 1860 .LBE256: + 1861 .LBE255: + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1862 .loc 1 617 15 view .LVU551 + 1863 05a4 0D4B ldr r3, .L134+4 + 1864 05a6 1968 ldr r1, [r3] + 1865 .LVL138: + 1866 .LBB257: + 1867 .LBI257: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1868 .loc 2 981 31 is_stmt 1 view .LVU552 + 1869 .LBB258: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1870 .loc 2 983 3 view .LVU553 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1871 .loc 2 988 4 view .LVU554 + 1872 05a8 4FF00073 mov r3, #33554432 + 1873 .syntax unified + 1874 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1875 05ac 93FAA3F3 rbit r3, r3 + 1876 @ 0 "" 2 + 1877 .LVL139: + 1878 .loc 2 1001 3 view .LVU555 + 1879 .loc 2 1001 3 is_stmt 0 view .LVU556 + 1880 .thumb + 1881 .syntax unified + 1882 .LBE258: + 1883 .LBE257: + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1884 .loc 1 617 15 view .LVU557 + 1885 05b0 B3FA83F3 clz r3, r3 + 1886 05b4 03F01F03 and r3, r3, #31 + 1887 05b8 0122 movs r2, #1 + 1888 05ba 02FA03F3 lsl r3, r2, r3 + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1889 .loc 1 617 52 view .LVU558 + ARM GAS /tmp/cczyIHoC.s page 68 + + + 1890 05be 1942 tst r1, r3 + 1891 05c0 06D1 bne .L131 + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1892 .loc 1 619 11 is_stmt 1 view .LVU559 + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1893 .loc 1 619 15 is_stmt 0 view .LVU560 + 1894 05c2 FFF7FEFF bl HAL_GetTick + 1895 .LVL140: + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1896 .loc 1 619 29 view .LVU561 + 1897 05c6 001B subs r0, r0, r4 + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1898 .loc 1 619 13 view .LVU562 + 1899 05c8 0228 cmp r0, #2 + 1900 05ca E7D9 bls .L86 + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1901 .loc 1 621 20 view .LVU563 + 1902 05cc 0320 movs r0, #3 + 1903 05ce 24E0 b .L21 + 1904 .L131: + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if there is a request to disable the PLL used as System clock source */ + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Do not return HAL_ERROR if request repeats the current configuration */ + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pll_config = RCC->CFGR; + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pll_config2 = RCC->CFGR2; + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; + 1905 .loc 1 670 10 view .LVU564 + 1906 05d0 0020 movs r0, #0 + 1907 05d2 22E0 b .L21 + 1908 .L129: + 1909 .loc 1 670 10 view .LVU565 + ARM GAS /tmp/cczyIHoC.s page 69 + + + 1910 05d4 0020 movs r0, #0 + 1911 05d6 20E0 b .L21 + 1912 .L135: + 1913 .align 2 + 1914 .L134: + 1915 05d8 20819010 .word 277905696 + 1916 05dc 00100240 .word 1073876992 + 1917 05e0 00700040 .word 1073770496 + 1918 .LVL141: + 1919 .L80: + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1920 .loc 1 646 7 is_stmt 1 view .LVU566 + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1921 .loc 1 646 9 is_stmt 0 view .LVU567 + 1922 05e4 012B cmp r3, #1 + 1923 05e6 1AD0 beq .L111 + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 1924 .loc 1 653 9 is_stmt 1 view .LVU568 + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 1925 .loc 1 653 20 is_stmt 0 view .LVU569 + 1926 05e8 104B ldr r3, .L136 + 1927 05ea 5B68 ldr r3, [r3, #4] + 1928 .LVL142: + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 1929 .loc 1 660 9 is_stmt 1 view .LVU570 + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 1930 .loc 1 660 13 is_stmt 0 view .LVU571 + 1931 05ec 03F48031 and r1, r3, #65536 + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 1932 .loc 1 660 78 view .LVU572 + 1933 05f0 226A ldr r2, [r4, #32] + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 1934 .loc 1 660 11 view .LVU573 + 1935 05f2 9142 cmp r1, r2 + 1936 05f4 15D1 bne .L112 + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif + 1937 .loc 1 661 13 discriminator 1 view .LVU574 + 1938 05f6 03F47013 and r3, r3, #3932160 + 1939 .LVL143: + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif + 1940 .loc 1 661 78 discriminator 1 view .LVU575 + 1941 05fa 626A ldr r2, [r4, #36] + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 1942 .loc 1 660 90 discriminator 1 view .LVU576 + 1943 05fc 9342 cmp r3, r2 + 1944 05fe 12D1 bne .L113 + 1945 .loc 1 670 10 view .LVU577 + 1946 0600 0020 movs r0, #0 + 1947 0602 0AE0 b .L21 + 1948 .LVL144: + 1949 .L94: + 1950 .cfi_def_cfa_offset 0 + 1951 .cfi_restore 4 + 1952 .cfi_restore 5 + 1953 .cfi_restore 6 + 1954 .cfi_restore 14 + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + ARM GAS /tmp/cczyIHoC.s page 70 + + + 1955 .loc 1 327 12 view .LVU578 + 1956 0604 0120 movs r0, #1 + 1957 .LVL145: + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1958 .loc 1 671 1 view .LVU579 + 1959 0606 7047 bx lr + 1960 .LVL146: + 1961 .L120: + 1962 .cfi_def_cfa_offset 24 + 1963 .cfi_offset 4, -16 + 1964 .cfi_offset 5, -12 + 1965 .cfi_offset 6, -8 + 1966 .cfi_offset 14, -4 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1967 .loc 1 345 16 view .LVU580 + 1968 0608 0120 movs r0, #1 + 1969 .LVL147: + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1970 .loc 1 345 16 view .LVU581 + 1971 060a 06E0 b .L21 + 1972 .L98: + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1973 .loc 1 403 16 view .LVU582 + 1974 060c 0120 movs r0, #1 + 1975 060e 04E0 b .L21 + 1976 .LVL148: + 1977 .L105: + 1978 .LBB259: + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1979 .loc 1 542 18 view .LVU583 + 1980 0610 0320 movs r0, #3 + 1981 0612 02E0 b .L21 + 1982 .L106: + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1983 .loc 1 556 18 view .LVU584 + 1984 0614 0320 movs r0, #3 + 1985 0616 00E0 b .L21 + 1986 .LVL149: + 1987 .L107: + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1988 .loc 1 556 18 view .LVU585 + 1989 .LBE259: + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 1990 .loc 1 670 10 view .LVU586 + 1991 0618 0020 movs r0, #0 + 1992 .LVL150: + 1993 .L21: + 1994 .loc 1 671 1 view .LVU587 + 1995 061a 02B0 add sp, sp, #8 + 1996 .cfi_remember_state + 1997 .cfi_def_cfa_offset 16 + 1998 @ sp needed + 1999 061c 70BD pop {r4, r5, r6, pc} + 2000 .LVL151: + 2001 .L111: + 2002 .cfi_restore_state + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + ARM GAS /tmp/cczyIHoC.s page 71 + + + 2003 .loc 1 648 16 view .LVU588 + 2004 061e 0120 movs r0, #1 + 2005 0620 FBE7 b .L21 + 2006 .LVL152: + 2007 .L112: + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2008 .loc 1 664 18 view .LVU589 + 2009 0622 0120 movs r0, #1 + 2010 0624 F9E7 b .L21 + 2011 .LVL153: + 2012 .L113: + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2013 .loc 1 664 18 view .LVU590 + 2014 0626 0120 movs r0, #1 + 2015 0628 F7E7 b .L21 + 2016 .L137: + 2017 062a 00BF .align 2 + 2018 .L136: + 2019 062c 00100240 .word 1073876992 + 2020 .cfi_endproc + 2021 .LFE131: + 2023 .section .text.HAL_RCC_MCOConfig,"ax",%progbits + 2024 .align 1 + 2025 .global HAL_RCC_MCOConfig + 2026 .syntax unified + 2027 .thumb + 2028 .thumb_func + 2030 HAL_RCC_MCOConfig: + 2031 .LVL154: + 2032 .LFB133: + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * parameters in the RCC_ClkInitStruct. + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the configuration information for the RCC peripheral. + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param FLatency FLASH Latency + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * The value of this parameter depend on device used within the same series + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The HSI is used (enabled by hardware) as system clock source after + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * of failure of the HSE used directly or indirectly as system clock + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * (if the Clock Security System CSS is enabled). + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note A switch from one clock source to another occurs only if the target + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * clock source is ready (clock stable after start-up delay or PLL locked). + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * If a clock source which is not yet ready is selected, the switch will + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * occur when the clock source will be ready. + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * currently used as system clock source. + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0U; + ARM GAS /tmp/cczyIHoC.s page 72 + + + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check Null pointer */ + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_ClkInitStruct == NULL) + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** must be correctly programmed according to the frequency of the CPU clock + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HCLK) of the device. */ + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Increasing the number of wait states because of higher CPU frequency */ + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(FLatency > __HAL_FLASH_GET_LATENCY()) + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLatency) + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------- SYSCLK Configuration ---------------------------*/ + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE is selected as System Clock Source */ + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSE ready flag */ + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* PLL is selected as System Clock Source */ + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the PLL ready flag */ + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + ARM GAS /tmp/cczyIHoC.s page 73 + + + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI is selected as System Clock Source */ + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSI ready flag */ + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(FLatency < __HAL_FLASH_GET_LATENCY()) + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLatency) + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/ + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CF + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ + ARM GAS /tmp/cczyIHoC.s page 74 + + + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_InitTick (uwTickPrio); + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC clocks control functions + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### Peripheral Control functions ##### + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** frequencies. + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_MCOPRE) + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO pin. + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note MCO pin should be configured in alternate function mode. + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCO DIV. + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO pin. + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note MCO pin should be configured in alternate function mode. + ARM GAS /tmp/cczyIHoC.s page 75 + + + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCO DIV. + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2033 .loc 1 889 1 is_stmt 1 view -0 + 2034 .cfi_startproc + 2035 @ args = 0, pretend = 0, frame = 24 + 2036 @ frame_needed = 0, uses_anonymous_args = 0 + 2037 .loc 1 889 1 is_stmt 0 view .LVU592 + 2038 0000 30B5 push {r4, r5, lr} + 2039 .cfi_def_cfa_offset 12 + 2040 .cfi_offset 4, -12 + 2041 .cfi_offset 5, -8 + 2042 .cfi_offset 14, -4 + 2043 0002 87B0 sub sp, sp, #28 + 2044 .cfi_def_cfa_offset 40 + 2045 0004 0D46 mov r5, r1 + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** GPIO_InitTypeDef gpio; + 2046 .loc 1 890 3 is_stmt 1 view .LVU593 + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCOx)); + 2047 .loc 1 893 3 view .LVU594 + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + 2048 .loc 1 894 3 view .LVU595 + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + 2049 .loc 1 895 3 view .LVU596 + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Mode = GPIO_MODE_AF_PP; + 2050 .loc 1 898 3 view .LVU597 + 2051 .loc 1 898 18 is_stmt 0 view .LVU598 + 2052 0006 0223 movs r3, #2 + 2053 0008 0293 str r3, [sp, #8] + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Speed = GPIO_SPEED_FREQ_HIGH; + 2054 .loc 1 899 3 is_stmt 1 view .LVU599 + 2055 .loc 1 899 18 is_stmt 0 view .LVU600 + 2056 000a 0323 movs r3, #3 + 2057 000c 0493 str r3, [sp, #16] + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Pull = GPIO_NOPULL; + 2058 .loc 1 900 3 is_stmt 1 view .LVU601 + ARM GAS /tmp/cczyIHoC.s page 76 + + + 2059 .loc 1 900 18 is_stmt 0 view .LVU602 + 2060 000e 0023 movs r3, #0 + 2061 0010 0393 str r3, [sp, #12] + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Pin = MCO1_PIN; + 2062 .loc 1 901 3 is_stmt 1 view .LVU603 + 2063 .loc 1 901 18 is_stmt 0 view .LVU604 + 2064 0012 4FF48072 mov r2, #256 + 2065 .LVL155: + 2066 .loc 1 901 18 view .LVU605 + 2067 0016 0192 str r2, [sp, #4] + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Alternate = GPIO_AF0_MCO; + 2068 .loc 1 902 3 is_stmt 1 view .LVU606 + 2069 .loc 1 902 18 is_stmt 0 view .LVU607 + 2070 0018 0593 str r3, [sp, #20] + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* MCO1 Clock Enable */ + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MCO1_CLK_ENABLE(); + 2071 .loc 1 905 3 is_stmt 1 view .LVU608 + 2072 .LBB260: + 2073 .loc 1 905 3 view .LVU609 + 2074 .loc 1 905 3 view .LVU610 + 2075 001a 0B4C ldr r4, .L140 + 2076 001c 6369 ldr r3, [r4, #20] + 2077 001e 43F40033 orr r3, r3, #131072 + 2078 0022 6361 str r3, [r4, #20] + 2079 .loc 1 905 3 view .LVU611 + 2080 0024 6369 ldr r3, [r4, #20] + 2081 0026 03F40033 and r3, r3, #131072 + 2082 002a 0093 str r3, [sp] + 2083 .loc 1 905 3 view .LVU612 + 2084 002c 009B ldr r3, [sp] + 2085 .LBE260: + 2086 .loc 1 905 3 view .LVU613 + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + 2087 .loc 1 907 3 view .LVU614 + 2088 002e 01A9 add r1, sp, #4 + 2089 .LVL156: + 2090 .loc 1 907 3 is_stmt 0 view .LVU615 + 2091 0030 4FF09040 mov r0, #1207959552 + 2092 .LVL157: + 2093 .loc 1 907 3 view .LVU616 + 2094 0034 FFF7FEFF bl HAL_GPIO_Init + 2095 .LVL158: + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the MCO clock source */ + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); + 2096 .loc 1 910 3 is_stmt 1 view .LVU617 + 2097 0038 6368 ldr r3, [r4, #4] + 2098 003a 23F0E063 bic r3, r3, #117440512 + 2099 003e 2B43 orrs r3, r3, r5 + 2100 0040 6360 str r3, [r4, #4] + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2101 .loc 1 911 1 is_stmt 0 view .LVU618 + 2102 0042 07B0 add sp, sp, #28 + 2103 .cfi_def_cfa_offset 12 + 2104 @ sp needed + ARM GAS /tmp/cczyIHoC.s page 77 + + + 2105 0044 30BD pop {r4, r5, pc} + 2106 .LVL159: + 2107 .L141: + 2108 .loc 1 911 1 view .LVU619 + 2109 0046 00BF .align 2 + 2110 .L140: + 2111 0048 00100240 .word 1073876992 + 2112 .cfi_endproc + 2113 .LFE133: + 2115 .section .text.HAL_RCC_EnableCSS,"ax",%progbits + 2116 .align 1 + 2117 .global HAL_RCC_EnableCSS + 2118 .syntax unified + 2119 .thumb + 2120 .thumb_func + 2122 HAL_RCC_EnableCSS: + 2123 .LFB134: + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Enables the Clock Security System. + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If a failure is detected on the HSE oscillator clock, this oscillator + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void) + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2124 .loc 1 923 1 is_stmt 1 view -0 + 2125 .cfi_startproc + 2126 @ args = 0, pretend = 0, frame = 0 + 2127 @ frame_needed = 0, uses_anonymous_args = 0 + 2128 @ link register save eliminated. + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; + 2129 .loc 1 924 3 view .LVU621 + 2130 .LVL160: + 2131 .LBB261: + 2132 .LBI261: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2133 .loc 2 981 31 view .LVU622 + 2134 .LBB262: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2135 .loc 2 983 3 view .LVU623 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2136 .loc 2 988 4 view .LVU624 + 2137 0000 4FF40023 mov r3, #524288 + 2138 .syntax unified + 2139 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2140 0004 93FAA3F3 rbit r3, r3 + 2141 @ 0 "" 2 + 2142 .LVL161: + 2143 .loc 2 1001 3 view .LVU625 + 2144 .loc 2 1001 3 is_stmt 0 view .LVU626 + 2145 .thumb + 2146 .syntax unified + 2147 .LBE262: + ARM GAS /tmp/cczyIHoC.s page 78 + + + 2148 .LBE261: + 2149 .loc 1 924 22 view .LVU627 + 2150 0008 B3FA83F3 clz r3, r3 + 2151 000c 03F18453 add r3, r3, #276824064 + 2152 0010 03F58413 add r3, r3, #1081344 + 2153 0014 9B00 lsls r3, r3, #2 + 2154 .loc 1 924 38 view .LVU628 + 2155 0016 0122 movs r2, #1 + 2156 0018 1A60 str r2, [r3] + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2157 .loc 1 925 1 view .LVU629 + 2158 001a 7047 bx lr + 2159 .cfi_endproc + 2160 .LFE134: + 2162 .section .text.HAL_RCC_DisableCSS,"ax",%progbits + 2163 .align 1 + 2164 .global HAL_RCC_DisableCSS + 2165 .syntax unified + 2166 .thumb + 2167 .thumb_func + 2169 HAL_RCC_DisableCSS: + 2170 .LFB135: + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Disables the Clock Security System. + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_DisableCSS(void) + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2171 .loc 1 932 1 is_stmt 1 view -0 + 2172 .cfi_startproc + 2173 @ args = 0, pretend = 0, frame = 0 + 2174 @ frame_needed = 0, uses_anonymous_args = 0 + 2175 @ link register save eliminated. + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; + 2176 .loc 1 933 3 view .LVU631 + 2177 .LVL162: + 2178 .LBB263: + 2179 .LBI263: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2180 .loc 2 981 31 view .LVU632 + 2181 .LBB264: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2182 .loc 2 983 3 view .LVU633 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2183 .loc 2 988 4 view .LVU634 + 2184 0000 4FF40023 mov r3, #524288 + 2185 .syntax unified + 2186 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2187 0004 93FAA3F3 rbit r3, r3 + 2188 @ 0 "" 2 + 2189 .LVL163: + 2190 .loc 2 1001 3 view .LVU635 + 2191 .loc 2 1001 3 is_stmt 0 view .LVU636 + 2192 .thumb + 2193 .syntax unified + 2194 .LBE264: + ARM GAS /tmp/cczyIHoC.s page 79 + + + 2195 .LBE263: + 2196 .loc 1 933 22 view .LVU637 + 2197 0008 B3FA83F3 clz r3, r3 + 2198 000c 03F18453 add r3, r3, #276824064 + 2199 0010 03F58413 add r3, r3, #1081344 + 2200 0014 9B00 lsls r3, r3, #2 + 2201 .loc 1 933 38 view .LVU638 + 2202 0016 0022 movs r2, #0 + 2203 0018 1A60 str r2, [r3] + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2204 .loc 1 934 1 view .LVU639 + 2205 001a 7047 bx lr + 2206 .cfi_endproc + 2207 .LFE135: + 2209 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits + 2210 .align 1 + 2211 .global HAL_RCC_GetSysClockFreq + 2212 .syntax unified + 2213 .thumb + 2214 .thumb_func + 2216 HAL_RCC_GetSysClockFreq: + 2217 .LFB136: + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the SYSCLK frequency + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The system frequency computed by this function is not the real + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * frequency in the chip. It is calculated based on the predefined + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * constant and the selected clock source: + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * divided by PREDIV factor(**) + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 8 MHz) but the real value may vary depending on the variations + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * in voltage and temperature. + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * frequency of the crystal used. Otherwise, this function may + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * have wrong result. + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The result of this function could be not correct when using fractional + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * value for HSE crystal. + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This function can be used by the user application to compute the + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * baud-rate for the communication peripherals or configure other parameters. + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time SYSCLK changes, this function must be called to update the + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right SYSCLK value. Otherwise, any configuration based on this function will be incorre + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval SYSCLK frequency + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void) + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2218 .loc 1 966 1 is_stmt 1 view -0 + 2219 .cfi_startproc + 2220 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/cczyIHoC.s page 80 + + + 2221 @ frame_needed = 0, uses_anonymous_args = 0 + 2222 @ link register save eliminated. + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + 2223 .loc 1 967 3 view .LVU641 + 2224 .LVL164: + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t sysclockfreq = 0U; + 2225 .loc 1 968 3 view .LVU642 + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tmpreg = RCC->CFGR; + 2226 .loc 1 970 3 view .LVU643 + 2227 .loc 1 970 10 is_stmt 0 view .LVU644 + 2228 0000 184B ldr r3, .L149 + 2229 0002 5A68 ldr r2, [r3, #4] + 2230 .LVL165: + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** switch (tmpreg & RCC_CFGR_SWS) + 2231 .loc 1 973 3 is_stmt 1 view .LVU645 + 2232 .loc 1 973 18 is_stmt 0 view .LVU646 + 2233 0004 02F00C03 and r3, r2, #12 + 2234 .loc 1 973 3 view .LVU647 + 2235 0008 042B cmp r3, #4 + 2236 000a 26D0 beq .L147 + 2237 000c 082B cmp r3, #8 + 2238 000e 26D1 bne .L148 + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = HSE_VALUE; + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLL + 2239 .loc 1 982 7 is_stmt 1 view .LVU648 + 2240 .loc 1 982 35 is_stmt 0 view .LVU649 + 2241 0010 02F47011 and r1, r2, #3932160 + 2242 .LVL166: + 2243 .LBB265: + 2244 .LBI265: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2245 .loc 2 981 31 is_stmt 1 view .LVU650 + 2246 .LBB266: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2247 .loc 2 983 3 view .LVU651 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2248 .loc 2 988 4 view .LVU652 + 2249 0014 4FF47013 mov r3, #3932160 + 2250 .syntax unified + 2251 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2252 0018 93FAA3F3 rbit r3, r3 + 2253 @ 0 "" 2 + 2254 .LVL167: + 2255 .loc 2 1001 3 view .LVU653 + 2256 .loc 2 1001 3 is_stmt 0 view .LVU654 + 2257 .thumb + 2258 .syntax unified + ARM GAS /tmp/cczyIHoC.s page 81 + + + 2259 .LBE266: + 2260 .LBE265: + 2261 .loc 1 982 72 view .LVU655 + 2262 001c B3FA83F3 clz r3, r3 + 2263 0020 21FA03F3 lsr r3, r1, r3 + 2264 .loc 1 982 34 view .LVU656 + 2265 0024 1049 ldr r1, .L149+4 + 2266 0026 C85C ldrb r0, [r1, r3] @ zero_extendqisi2 + 2267 .LVL168: + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFG + 2268 .loc 1 983 7 is_stmt 1 view .LVU657 + 2269 .loc 1 983 49 is_stmt 0 view .LVU658 + 2270 0028 0E4B ldr r3, .L149 + 2271 002a DB6A ldr r3, [r3, #44] + 2272 .loc 1 983 35 view .LVU659 + 2273 002c 03F00F03 and r3, r3, #15 + 2274 .LVL169: + 2275 .LBB267: + 2276 .LBI267: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2277 .loc 2 981 31 is_stmt 1 view .LVU660 + 2278 .LBB268: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2279 .loc 2 983 3 view .LVU661 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2280 .loc 2 988 4 view .LVU662 + 2281 0030 0F21 movs r1, #15 + 2282 .syntax unified + 2283 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2284 0032 91FAA1F1 rbit r1, r1 + 2285 @ 0 "" 2 + 2286 .LVL170: + 2287 .loc 2 1001 3 view .LVU663 + 2288 .loc 2 1001 3 is_stmt 0 view .LVU664 + 2289 .thumb + 2290 .syntax unified + 2291 .LBE268: + 2292 .LBE267: + 2293 .loc 1 983 77 view .LVU665 + 2294 0036 B1FA81F1 clz r1, r1 + 2295 003a CB40 lsrs r3, r3, r1 + 2296 .loc 1 983 34 view .LVU666 + 2297 003c 0B49 ldr r1, .L149+8 + 2298 003e C95C ldrb r1, [r1, r3] @ zero_extendqisi2 + 2299 .LVL171: + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) + 2300 .loc 1 985 7 is_stmt 1 view .LVU667 + 2301 .loc 1 985 10 is_stmt 0 view .LVU668 + 2302 0040 12F4803F tst r2, #65536 + 2303 0044 05D0 beq .L146 + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + 2304 .loc 1 988 9 is_stmt 1 view .LVU669 + 2305 .loc 1 988 18 is_stmt 0 view .LVU670 + 2306 0046 0A4B ldr r3, .L149+12 + ARM GAS /tmp/cczyIHoC.s page 82 + + + 2307 0048 B3FBF1F3 udiv r3, r3, r1 + 2308 .loc 1 988 16 view .LVU671 + 2309 004c 03FB00F0 mul r0, r3, r0 + 2310 .LVL172: + 2311 .loc 1 988 16 view .LVU672 + 2312 0050 7047 bx lr + 2313 .LVL173: + 2314 .L146: + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); + 2315 .loc 1 993 9 is_stmt 1 view .LVU673 + 2316 .loc 1 993 16 is_stmt 0 view .LVU674 + 2317 0052 084B ldr r3, .L149+16 + 2318 0054 03FB00F0 mul r0, r3, r0 + 2319 .LVL174: + 2320 .loc 1 993 16 view .LVU675 + 2321 0058 7047 bx lr + 2322 .LVL175: + 2323 .L147: + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2324 .loc 1 973 3 view .LVU676 + 2325 005a 0548 ldr r0, .L149+12 + 2326 005c 7047 bx lr + 2327 .L148: + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV) + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = pllclk; +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** default: /* HSI used as system clock */ +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = HSI_VALUE; + 2328 .loc 1 1013 20 view .LVU677 + 2329 005e 0648 ldr r0, .L149+20 + 2330 .LVL176: +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return sysclockfreq; + 2331 .loc 1 1017 3 is_stmt 1 view .LVU678 +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2332 .loc 1 1018 1 is_stmt 0 view .LVU679 + ARM GAS /tmp/cczyIHoC.s page 83 + + + 2333 0060 7047 bx lr + 2334 .L150: + 2335 0062 00BF .align 2 + 2336 .L149: + 2337 0064 00100240 .word 1073876992 + 2338 0068 00000000 .word aPLLMULFactorTable + 2339 006c 00000000 .word aPredivFactorTable + 2340 0070 0024F400 .word 16000000 + 2341 0074 00093D00 .word 4000000 + 2342 0078 00127A00 .word 8000000 + 2343 .cfi_endproc + 2344 .LFE136: + 2346 .section .text.HAL_RCC_ClockConfig,"ax",%progbits + 2347 .align 1 + 2348 .global HAL_RCC_ClockConfig + 2349 .syntax unified + 2350 .thumb + 2351 .thumb_func + 2353 HAL_RCC_ClockConfig: + 2354 .LVL177: + 2355 .LFB132: + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0U; + 2356 .loc 1 697 1 is_stmt 1 view -0 + 2357 .cfi_startproc + 2358 @ args = 0, pretend = 0, frame = 0 + 2359 @ frame_needed = 0, uses_anonymous_args = 0 + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2360 .loc 1 698 3 view .LVU681 + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2361 .loc 1 701 3 view .LVU682 + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2362 .loc 1 701 5 is_stmt 0 view .LVU683 + 2363 0000 0028 cmp r0, #0 + 2364 0002 00F0BE80 beq .L170 + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0U; + 2365 .loc 1 697 1 view .LVU684 + 2366 0006 70B5 push {r4, r5, r6, lr} + 2367 .cfi_def_cfa_offset 16 + 2368 .cfi_offset 4, -16 + 2369 .cfi_offset 5, -12 + 2370 .cfi_offset 6, -8 + 2371 .cfi_offset 14, -4 + 2372 0008 0D46 mov r5, r1 + 2373 000a 0446 mov r4, r0 + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 2374 .loc 1 707 3 is_stmt 1 view .LVU685 + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2375 .loc 1 708 3 view .LVU686 + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2376 .loc 1 715 3 view .LVU687 + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2377 .loc 1 715 17 is_stmt 0 view .LVU688 + 2378 000c 614B ldr r3, .L183 + 2379 000e 1B68 ldr r3, [r3] + 2380 0010 03F00703 and r3, r3, #7 + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2381 .loc 1 715 5 view .LVU689 + ARM GAS /tmp/cczyIHoC.s page 84 + + + 2382 0014 8B42 cmp r3, r1 + 2383 0016 0BD2 bcs .L153 + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2384 .loc 1 718 5 is_stmt 1 view .LVU690 + 2385 0018 5E4A ldr r2, .L183 + 2386 001a 1368 ldr r3, [r2] + 2387 001c 23F00703 bic r3, r3, #7 + 2388 0020 0B43 orrs r3, r3, r1 + 2389 0022 1360 str r3, [r2] + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2390 .loc 1 722 5 view .LVU691 + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2391 .loc 1 722 8 is_stmt 0 view .LVU692 + 2392 0024 1368 ldr r3, [r2] + 2393 0026 03F00703 and r3, r3, #7 + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2394 .loc 1 722 7 view .LVU693 + 2395 002a 8B42 cmp r3, r1 + 2396 002c 40F0AB80 bne .L171 + 2397 .L153: + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2398 .loc 1 729 3 is_stmt 1 view .LVU694 + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2399 .loc 1 729 25 is_stmt 0 view .LVU695 + 2400 0030 2368 ldr r3, [r4] + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2401 .loc 1 729 5 view .LVU696 + 2402 0032 13F0020F tst r3, #2 + 2403 0036 06D0 beq .L154 + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 2404 .loc 1 731 5 is_stmt 1 view .LVU697 + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2405 .loc 1 732 5 view .LVU698 + 2406 0038 574A ldr r2, .L183+4 + 2407 003a 5368 ldr r3, [r2, #4] + 2408 003c 23F0F003 bic r3, r3, #240 + 2409 0040 A168 ldr r1, [r4, #8] + 2410 .LVL178: + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2411 .loc 1 732 5 is_stmt 0 view .LVU699 + 2412 0042 0B43 orrs r3, r3, r1 + 2413 0044 5360 str r3, [r2, #4] + 2414 .L154: + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2415 .loc 1 736 3 is_stmt 1 view .LVU700 + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2416 .loc 1 736 25 is_stmt 0 view .LVU701 + 2417 0046 2368 ldr r3, [r4] + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2418 .loc 1 736 5 view .LVU702 + 2419 0048 13F0010F tst r3, #1 + 2420 004c 5AD0 beq .L155 + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2421 .loc 1 738 5 is_stmt 1 view .LVU703 + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2422 .loc 1 741 5 view .LVU704 + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + ARM GAS /tmp/cczyIHoC.s page 85 + + + 2423 .loc 1 741 25 is_stmt 0 view .LVU705 + 2424 004e 6368 ldr r3, [r4, #4] + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2425 .loc 1 741 7 view .LVU706 + 2426 0050 012B cmp r3, #1 + 2427 0052 2DD0 beq .L181 + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2428 .loc 1 750 10 is_stmt 1 view .LVU707 + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2429 .loc 1 750 12 is_stmt 0 view .LVU708 + 2430 0054 022B cmp r3, #2 + 2431 0056 40D0 beq .L182 + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2432 .loc 1 762 7 is_stmt 1 view .LVU709 + 2433 .LVL179: + 2434 .LBB269: + 2435 .LBI269: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2436 .loc 2 981 31 view .LVU710 + 2437 .LBB270: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2438 .loc 2 983 3 view .LVU711 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2439 .loc 2 988 4 view .LVU712 + 2440 0058 0222 movs r2, #2 + 2441 .syntax unified + 2442 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2443 005a 92FAA2F2 rbit r2, r2 + 2444 @ 0 "" 2 + 2445 .loc 2 1001 3 view .LVU713 + 2446 .LVL180: + 2447 .loc 2 1001 3 is_stmt 0 view .LVU714 + 2448 .thumb + 2449 .syntax unified + 2450 .LBE270: + 2451 .LBE269: + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2452 .loc 1 762 10 view .LVU715 + 2453 005e 4E4A ldr r2, .L183+4 + 2454 0060 1068 ldr r0, [r2] + 2455 .LVL181: + 2456 .LBB271: + 2457 .LBI271: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2458 .loc 2 981 31 is_stmt 1 view .LVU716 + 2459 .LBB272: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2460 .loc 2 983 3 view .LVU717 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2461 .loc 2 988 4 view .LVU718 + 2462 0062 0222 movs r2, #2 + 2463 .syntax unified + 2464 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2465 0064 92FAA2F2 rbit r2, r2 + 2466 @ 0 "" 2 + 2467 .LVL182: + 2468 .loc 2 1001 3 view .LVU719 + ARM GAS /tmp/cczyIHoC.s page 86 + + + 2469 .loc 2 1001 3 is_stmt 0 view .LVU720 + 2470 .thumb + 2471 .syntax unified + 2472 .LBE272: + 2473 .LBE271: + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2474 .loc 1 762 10 view .LVU721 + 2475 0068 B2FA82F2 clz r2, r2 + 2476 006c 02F01F02 and r2, r2, #31 + 2477 0070 0121 movs r1, #1 + 2478 0072 01FA02F2 lsl r2, r1, r2 + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2479 .loc 1 762 9 view .LVU722 + 2480 0076 1042 tst r0, r2 + 2481 0078 00F08780 beq .L174 + 2482 .L159: + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2483 .loc 1 768 5 is_stmt 1 view .LVU723 + 2484 007c 4649 ldr r1, .L183+4 + 2485 007e 4A68 ldr r2, [r1, #4] + 2486 0080 22F00302 bic r2, r2, #3 + 2487 0084 1343 orrs r3, r3, r2 + 2488 0086 4B60 str r3, [r1, #4] + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2489 .loc 1 771 5 view .LVU724 + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2490 .loc 1 771 17 is_stmt 0 view .LVU725 + 2491 0088 FFF7FEFF bl HAL_GetTick + 2492 .LVL183: + 2493 008c 0646 mov r6, r0 + 2494 .LVL184: + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2495 .loc 1 773 5 is_stmt 1 view .LVU726 + 2496 .L165: + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2497 .loc 1 773 42 view .LVU727 + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2498 .loc 1 773 12 is_stmt 0 view .LVU728 + 2499 008e 424B ldr r3, .L183+4 + 2500 0090 5B68 ldr r3, [r3, #4] + 2501 0092 03F00C03 and r3, r3, #12 + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2502 .loc 1 773 63 view .LVU729 + 2503 0096 6268 ldr r2, [r4, #4] + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2504 .loc 1 773 42 view .LVU730 + 2505 0098 B3EB820F cmp r3, r2, lsl #2 + 2506 009c 32D0 beq .L155 + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2507 .loc 1 775 7 is_stmt 1 view .LVU731 + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2508 .loc 1 775 12 is_stmt 0 view .LVU732 + 2509 009e FFF7FEFF bl HAL_GetTick + 2510 .LVL185: + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2511 .loc 1 775 26 view .LVU733 + 2512 00a2 801B subs r0, r0, r6 + ARM GAS /tmp/cczyIHoC.s page 87 + + + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2513 .loc 1 775 10 view .LVU734 + 2514 00a4 41F28833 movw r3, #5000 + 2515 00a8 9842 cmp r0, r3 + 2516 00aa F0D9 bls .L165 + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2517 .loc 1 777 16 view .LVU735 + 2518 00ac 0320 movs r0, #3 + 2519 00ae 67E0 b .L152 + 2520 .LVL186: + 2521 .L181: + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2522 .loc 1 744 7 is_stmt 1 view .LVU736 + 2523 .LBB273: + 2524 .LBI273: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2525 .loc 2 981 31 view .LVU737 + 2526 .LBB274: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2527 .loc 2 983 3 view .LVU738 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2528 .loc 2 988 4 view .LVU739 + 2529 00b0 4FF40032 mov r2, #131072 + 2530 .syntax unified + 2531 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2532 00b4 92FAA2F2 rbit r2, r2 + 2533 @ 0 "" 2 + 2534 .loc 2 1001 3 view .LVU740 + 2535 .LVL187: + 2536 .loc 2 1001 3 is_stmt 0 view .LVU741 + 2537 .thumb + 2538 .syntax unified + 2539 .LBE274: + 2540 .LBE273: + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2541 .loc 1 744 10 view .LVU742 + 2542 00b8 374A ldr r2, .L183+4 + 2543 00ba 1068 ldr r0, [r2] + 2544 .LVL188: + 2545 .LBB275: + 2546 .LBI275: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2547 .loc 2 981 31 is_stmt 1 view .LVU743 + 2548 .LBB276: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2549 .loc 2 983 3 view .LVU744 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2550 .loc 2 988 4 view .LVU745 + 2551 00bc 4FF40032 mov r2, #131072 + 2552 .syntax unified + 2553 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2554 00c0 92FAA2F2 rbit r2, r2 + 2555 @ 0 "" 2 + 2556 .LVL189: + 2557 .loc 2 1001 3 view .LVU746 + 2558 .loc 2 1001 3 is_stmt 0 view .LVU747 + 2559 .thumb + ARM GAS /tmp/cczyIHoC.s page 88 + + + 2560 .syntax unified + 2561 .LBE276: + 2562 .LBE275: + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2563 .loc 1 744 10 view .LVU748 + 2564 00c4 B2FA82F2 clz r2, r2 + 2565 00c8 02F01F02 and r2, r2, #31 + 2566 00cc 0121 movs r1, #1 + 2567 00ce 01FA02F2 lsl r2, r1, r2 + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2568 .loc 1 744 9 view .LVU749 + 2569 00d2 0242 tst r2, r0 + 2570 00d4 D2D1 bne .L159 + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2571 .loc 1 746 16 view .LVU750 + 2572 00d6 0120 movs r0, #1 + 2573 00d8 52E0 b .L152 + 2574 .LVL190: + 2575 .L182: + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2576 .loc 1 753 7 is_stmt 1 view .LVU751 + 2577 .LBB277: + 2578 .LBI277: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2579 .loc 2 981 31 view .LVU752 + 2580 .LBB278: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2581 .loc 2 983 3 view .LVU753 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2582 .loc 2 988 4 view .LVU754 + 2583 00da 4FF00072 mov r2, #33554432 + 2584 .syntax unified + 2585 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2586 00de 92FAA2F2 rbit r2, r2 + 2587 @ 0 "" 2 + 2588 .loc 2 1001 3 view .LVU755 + 2589 .LVL191: + 2590 .loc 2 1001 3 is_stmt 0 view .LVU756 + 2591 .thumb + 2592 .syntax unified + 2593 .LBE278: + 2594 .LBE277: + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2595 .loc 1 753 10 view .LVU757 + 2596 00e2 2D4A ldr r2, .L183+4 + 2597 00e4 1068 ldr r0, [r2] + 2598 .LVL192: + 2599 .LBB279: + 2600 .LBI279: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2601 .loc 2 981 31 is_stmt 1 view .LVU758 + 2602 .LBB280: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2603 .loc 2 983 3 view .LVU759 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2604 .loc 2 988 4 view .LVU760 + 2605 00e6 4FF00072 mov r2, #33554432 + ARM GAS /tmp/cczyIHoC.s page 89 + + + 2606 .syntax unified + 2607 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2608 00ea 92FAA2F2 rbit r2, r2 + 2609 @ 0 "" 2 + 2610 .LVL193: + 2611 .loc 2 1001 3 view .LVU761 + 2612 .loc 2 1001 3 is_stmt 0 view .LVU762 + 2613 .thumb + 2614 .syntax unified + 2615 .LBE280: + 2616 .LBE279: + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2617 .loc 1 753 10 view .LVU763 + 2618 00ee B2FA82F2 clz r2, r2 + 2619 00f2 02F01F02 and r2, r2, #31 + 2620 00f6 0121 movs r1, #1 + 2621 00f8 01FA02F2 lsl r2, r1, r2 + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2622 .loc 1 753 9 view .LVU764 + 2623 00fc 1042 tst r0, r2 + 2624 00fe BDD1 bne .L159 + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2625 .loc 1 755 16 view .LVU765 + 2626 0100 0120 movs r0, #1 + 2627 0102 3DE0 b .L152 + 2628 .LVL194: + 2629 .L155: + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2630 .loc 1 782 3 is_stmt 1 view .LVU766 + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2631 .loc 1 782 17 is_stmt 0 view .LVU767 + 2632 0104 234B ldr r3, .L183 + 2633 0106 1B68 ldr r3, [r3] + 2634 0108 03F00703 and r3, r3, #7 + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2635 .loc 1 782 5 view .LVU768 + 2636 010c AB42 cmp r3, r5 + 2637 010e 0AD9 bls .L167 + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2638 .loc 1 785 5 is_stmt 1 view .LVU769 + 2639 0110 204A ldr r2, .L183 + 2640 0112 1368 ldr r3, [r2] + 2641 0114 23F00703 bic r3, r3, #7 + 2642 0118 2B43 orrs r3, r3, r5 + 2643 011a 1360 str r3, [r2] + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2644 .loc 1 789 5 view .LVU770 + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2645 .loc 1 789 8 is_stmt 0 view .LVU771 + 2646 011c 1368 ldr r3, [r2] + 2647 011e 03F00703 and r3, r3, #7 + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2648 .loc 1 789 7 view .LVU772 + 2649 0122 AB42 cmp r3, r5 + 2650 0124 33D1 bne .L176 + 2651 .L167: + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + ARM GAS /tmp/cczyIHoC.s page 90 + + + 2652 .loc 1 796 3 is_stmt 1 view .LVU773 + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2653 .loc 1 796 25 is_stmt 0 view .LVU774 + 2654 0126 2368 ldr r3, [r4] + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2655 .loc 1 796 5 view .LVU775 + 2656 0128 13F0040F tst r3, #4 + 2657 012c 06D0 beq .L168 + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 2658 .loc 1 798 5 is_stmt 1 view .LVU776 + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2659 .loc 1 799 5 view .LVU777 + 2660 012e 1A4A ldr r2, .L183+4 + 2661 0130 5368 ldr r3, [r2, #4] + 2662 0132 23F4E063 bic r3, r3, #1792 + 2663 0136 E168 ldr r1, [r4, #12] + 2664 0138 0B43 orrs r3, r3, r1 + 2665 013a 5360 str r3, [r2, #4] + 2666 .L168: + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2667 .loc 1 803 3 view .LVU778 + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2668 .loc 1 803 25 is_stmt 0 view .LVU779 + 2669 013c 2368 ldr r3, [r4] + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2670 .loc 1 803 5 view .LVU780 + 2671 013e 13F0080F tst r3, #8 + 2672 0142 07D0 beq .L169 + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 2673 .loc 1 805 5 is_stmt 1 view .LVU781 + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2674 .loc 1 806 5 view .LVU782 + 2675 0144 144A ldr r2, .L183+4 + 2676 0146 5368 ldr r3, [r2, #4] + 2677 0148 23F46053 bic r3, r3, #14336 + 2678 014c 2169 ldr r1, [r4, #16] + 2679 014e 43EAC103 orr r3, r3, r1, lsl #3 + 2680 0152 5360 str r3, [r2, #4] + 2681 .L169: + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2682 .loc 1 810 3 view .LVU783 + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2683 .loc 1 810 21 is_stmt 0 view .LVU784 + 2684 0154 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 2685 .LVL195: + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2686 .loc 1 810 68 view .LVU785 + 2687 0158 0F4B ldr r3, .L183+4 + 2688 015a 5B68 ldr r3, [r3, #4] + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2689 .loc 1 810 75 view .LVU786 + 2690 015c 03F0F003 and r3, r3, #240 + 2691 .LVL196: + 2692 .LBB281: + 2693 .LBI281: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2694 .loc 2 981 31 is_stmt 1 view .LVU787 + ARM GAS /tmp/cczyIHoC.s page 91 + + + 2695 .LBB282: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2696 .loc 2 983 3 view .LVU788 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2697 .loc 2 988 4 view .LVU789 + 2698 0160 F022 movs r2, #240 + 2699 .syntax unified + 2700 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2701 0162 92FAA2F2 rbit r2, r2 + 2702 @ 0 "" 2 + 2703 .LVL197: + 2704 .loc 2 1001 3 view .LVU790 + 2705 .loc 2 1001 3 is_stmt 0 view .LVU791 + 2706 .thumb + 2707 .syntax unified + 2708 .LBE282: + 2709 .LBE281: + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2710 .loc 1 810 91 view .LVU792 + 2711 0166 B2FA82F2 clz r2, r2 + 2712 016a D340 lsrs r3, r3, r2 + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2713 .loc 1 810 63 view .LVU793 + 2714 016c 0B4A ldr r2, .L183+8 + 2715 016e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2716 .loc 1 810 47 view .LVU794 + 2717 0170 D840 lsrs r0, r0, r3 + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2718 .loc 1 810 19 view .LVU795 + 2719 0172 0B4B ldr r3, .L183+12 + 2720 0174 1860 str r0, [r3] + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2721 .loc 1 813 3 is_stmt 1 view .LVU796 + 2722 0176 0B4B ldr r3, .L183+16 + 2723 0178 1868 ldr r0, [r3] + 2724 017a FFF7FEFF bl HAL_InitTick + 2725 .LVL198: + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2726 .loc 1 815 3 view .LVU797 + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2727 .loc 1 815 10 is_stmt 0 view .LVU798 + 2728 017e 0020 movs r0, #0 + 2729 .L152: + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2730 .loc 1 816 1 view .LVU799 + 2731 0180 70BD pop {r4, r5, r6, pc} + 2732 .LVL199: + 2733 .L170: + 2734 .cfi_def_cfa_offset 0 + 2735 .cfi_restore 4 + 2736 .cfi_restore 5 + 2737 .cfi_restore 6 + 2738 .cfi_restore 14 + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2739 .loc 1 703 12 view .LVU800 + 2740 0182 0120 movs r0, #1 + ARM GAS /tmp/cczyIHoC.s page 92 + + + 2741 .LVL200: + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 2742 .loc 1 816 1 view .LVU801 + 2743 0184 7047 bx lr + 2744 .LVL201: + 2745 .L171: + 2746 .cfi_def_cfa_offset 16 + 2747 .cfi_offset 4, -16 + 2748 .cfi_offset 5, -12 + 2749 .cfi_offset 6, -8 + 2750 .cfi_offset 14, -4 + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2751 .loc 1 724 14 view .LVU802 + 2752 0186 0120 movs r0, #1 + 2753 .LVL202: + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2754 .loc 1 724 14 view .LVU803 + 2755 0188 FAE7 b .L152 + 2756 .LVL203: + 2757 .L174: + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2758 .loc 1 764 16 view .LVU804 + 2759 018a 0120 movs r0, #1 + 2760 018c F8E7 b .L152 + 2761 .LVL204: + 2762 .L176: + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2763 .loc 1 791 14 view .LVU805 + 2764 018e 0120 movs r0, #1 + 2765 0190 F6E7 b .L152 + 2766 .L184: + 2767 0192 00BF .align 2 + 2768 .L183: + 2769 0194 00200240 .word 1073881088 + 2770 0198 00100240 .word 1073876992 + 2771 019c 00000000 .word AHBPrescTable + 2772 01a0 00000000 .word SystemCoreClock + 2773 01a4 00000000 .word uwTickPrio + 2774 .cfi_endproc + 2775 .LFE132: + 2777 .section .text.HAL_RCC_GetHCLKFreq,"ax",%progbits + 2778 .align 1 + 2779 .global HAL_RCC_GetHCLKFreq + 2780 .syntax unified + 2781 .thumb + 2782 .thumb_func + 2784 HAL_RCC_GetHCLKFreq: + 2785 .LFB137: +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the HCLK frequency +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time HCLK changes, this function must be called to update the +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right HCLK value. Otherwise, any configuration based on this function will be incorrect +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * and updated within this function +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HCLK frequency + ARM GAS /tmp/cczyIHoC.s page 93 + + +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void) +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2786 .loc 1 1030 1 is_stmt 1 view -0 + 2787 .cfi_startproc + 2788 @ args = 0, pretend = 0, frame = 0 + 2789 @ frame_needed = 0, uses_anonymous_args = 0 + 2790 @ link register save eliminated. +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return SystemCoreClock; + 2791 .loc 1 1031 3 view .LVU807 +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2792 .loc 1 1032 1 is_stmt 0 view .LVU808 + 2793 0000 014B ldr r3, .L186 + 2794 0002 1868 ldr r0, [r3] + 2795 0004 7047 bx lr + 2796 .L187: + 2797 0006 00BF .align 2 + 2798 .L186: + 2799 0008 00000000 .word SystemCoreClock + 2800 .cfi_endproc + 2801 .LFE137: + 2803 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits + 2804 .align 1 + 2805 .global HAL_RCC_GetPCLK1Freq + 2806 .syntax unified + 2807 .thumb + 2808 .thumb_func + 2810 HAL_RCC_GetPCLK1Freq: + 2811 .LFB138: +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the PCLK1 frequency +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time PCLK1 changes, this function must be called to update the +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right PCLK1 value. Otherwise, any configuration based on this function will be incorrec +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval PCLK1 frequency +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void) +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2812 .loc 1 1041 1 is_stmt 1 view -0 + 2813 .cfi_startproc + 2814 @ args = 0, pretend = 0, frame = 0 + 2815 @ frame_needed = 0, uses_anonymous_args = 0 + 2816 0000 08B5 push {r3, lr} + 2817 .cfi_def_cfa_offset 8 + 2818 .cfi_offset 3, -8 + 2819 .cfi_offset 14, -4 +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BIT + 2820 .loc 1 1043 3 view .LVU810 + 2821 .loc 1 1043 11 is_stmt 0 view .LVU811 + 2822 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 2823 .LVL205: + 2824 .loc 1 1043 54 view .LVU812 + 2825 0006 074B ldr r3, .L190 + 2826 0008 5B68 ldr r3, [r3, #4] + 2827 .loc 1 1043 61 view .LVU813 + 2828 000a 03F4E063 and r3, r3, #1792 + ARM GAS /tmp/cczyIHoC.s page 94 + + + 2829 .LVL206: + 2830 .LBB283: + 2831 .LBI283: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2832 .loc 2 981 31 is_stmt 1 view .LVU814 + 2833 .LBB284: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2834 .loc 2 983 3 view .LVU815 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2835 .loc 2 988 4 view .LVU816 + 2836 000e 4FF4E062 mov r2, #1792 + 2837 .syntax unified + 2838 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2839 0012 92FAA2F2 rbit r2, r2 + 2840 @ 0 "" 2 + 2841 .LVL207: + 2842 .loc 2 1001 3 view .LVU817 + 2843 .loc 2 1001 3 is_stmt 0 view .LVU818 + 2844 .thumb + 2845 .syntax unified + 2846 .LBE284: + 2847 .LBE283: + 2848 .loc 1 1043 79 view .LVU819 + 2849 0016 B2FA82F2 clz r2, r2 + 2850 001a D340 lsrs r3, r3, r2 + 2851 .loc 1 1043 49 view .LVU820 + 2852 001c 024A ldr r2, .L190+4 + 2853 001e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2854 .loc 1 1044 1 view .LVU821 + 2855 0020 D840 lsrs r0, r0, r3 + 2856 0022 08BD pop {r3, pc} + 2857 .L191: + 2858 .align 2 + 2859 .L190: + 2860 0024 00100240 .word 1073876992 + 2861 0028 00000000 .word APBPrescTable + 2862 .cfi_endproc + 2863 .LFE138: + 2865 .section .text.HAL_RCC_GetPCLK2Freq,"ax",%progbits + 2866 .align 1 + 2867 .global HAL_RCC_GetPCLK2Freq + 2868 .syntax unified + 2869 .thumb + 2870 .thumb_func + 2872 HAL_RCC_GetPCLK2Freq: + 2873 .LFB139: +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the PCLK2 frequency +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time PCLK2 changes, this function must be called to update the +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right PCLK2 value. Otherwise, any configuration based on this function will be incorrec +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval PCLK2 frequency +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void) +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2874 .loc 1 1053 1 is_stmt 1 view -0 + ARM GAS /tmp/cczyIHoC.s page 95 + + + 2875 .cfi_startproc + 2876 @ args = 0, pretend = 0, frame = 0 + 2877 @ frame_needed = 0, uses_anonymous_args = 0 + 2878 0000 08B5 push {r3, lr} + 2879 .cfi_def_cfa_offset 8 + 2880 .cfi_offset 3, -8 + 2881 .cfi_offset 14, -4 +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITN + 2882 .loc 1 1055 3 view .LVU823 + 2883 .loc 1 1055 11 is_stmt 0 view .LVU824 + 2884 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 2885 .LVL208: + 2886 .loc 1 1055 53 view .LVU825 + 2887 0006 074B ldr r3, .L194 + 2888 0008 5B68 ldr r3, [r3, #4] + 2889 .loc 1 1055 60 view .LVU826 + 2890 000a 03F46053 and r3, r3, #14336 + 2891 .LVL209: + 2892 .LBB285: + 2893 .LBI285: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2894 .loc 2 981 31 is_stmt 1 view .LVU827 + 2895 .LBB286: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2896 .loc 2 983 3 view .LVU828 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2897 .loc 2 988 4 view .LVU829 + 2898 000e 4FF46052 mov r2, #14336 + 2899 .syntax unified + 2900 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2901 0012 92FAA2F2 rbit r2, r2 + 2902 @ 0 "" 2 + 2903 .LVL210: + 2904 .loc 2 1001 3 view .LVU830 + 2905 .loc 2 1001 3 is_stmt 0 view .LVU831 + 2906 .thumb + 2907 .syntax unified + 2908 .LBE286: + 2909 .LBE285: + 2910 .loc 1 1055 78 view .LVU832 + 2911 0016 B2FA82F2 clz r2, r2 + 2912 001a D340 lsrs r3, r3, r2 + 2913 .loc 1 1055 48 view .LVU833 + 2914 001c 024A ldr r2, .L194+4 + 2915 001e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2916 .loc 1 1056 1 view .LVU834 + 2917 0020 D840 lsrs r0, r0, r3 + 2918 0022 08BD pop {r3, pc} + 2919 .L195: + 2920 .align 2 + 2921 .L194: + 2922 0024 00100240 .word 1073876992 + 2923 0028 00000000 .word APBPrescTable + 2924 .cfi_endproc + 2925 .LFE139: + ARM GAS /tmp/cczyIHoC.s page 96 + + + 2927 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits + 2928 .align 1 + 2929 .global HAL_RCC_GetOscConfig + 2930 .syntax unified + 2931 .thumb + 2932 .thumb_func + 2934 HAL_RCC_GetOscConfig: + 2935 .LVL211: + 2936 .LFB140: +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Configures the RCC_OscInitStruct according to the internal +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC configuration registers. +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * will be configured. +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2937 .loc 1 1066 1 is_stmt 1 view -0 + 2938 .cfi_startproc + 2939 @ args = 0, pretend = 0, frame = 0 + 2940 @ frame_needed = 0, uses_anonymous_args = 0 + 2941 @ link register save eliminated. +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(RCC_OscInitStruct != NULL); + 2942 .loc 1 1068 3 view .LVU836 +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set all possible values for the Oscillator type parameter ---------------*/ +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + 2943 .loc 1 1071 3 view .LVU837 + 2944 .loc 1 1071 37 is_stmt 0 view .LVU838 + 2945 0000 0F23 movs r3, #15 + 2946 0002 0360 str r3, [r0] +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HSE configuration -----------------------------------------------*/ +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + 2947 .loc 1 1076 3 is_stmt 1 view .LVU839 + 2948 .loc 1 1076 10 is_stmt 0 view .LVU840 + 2949 0004 2D4B ldr r3, .L209 + 2950 0006 1B68 ldr r3, [r3] + 2951 .loc 1 1076 5 view .LVU841 + 2952 0008 13F4802F tst r3, #262144 + 2953 000c 36D0 beq .L197 +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + 2954 .loc 1 1078 5 is_stmt 1 view .LVU842 + 2955 .loc 1 1078 33 is_stmt 0 view .LVU843 + 2956 000e 4FF4A023 mov r3, #327680 + 2957 0012 4360 str r3, [r0, #4] + 2958 .L198: +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; + ARM GAS /tmp/cczyIHoC.s page 97 + + +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); + 2959 .loc 1 1089 3 is_stmt 1 view .LVU844 + 2960 .loc 1 1089 39 is_stmt 0 view .LVU845 + 2961 0014 294A ldr r2, .L209 + 2962 0016 D36A ldr r3, [r2, #44] + 2963 0018 03F00F03 and r3, r3, #15 + 2964 .loc 1 1089 37 view .LVU846 + 2965 001c 8360 str r3, [r0, #8] +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HSI configuration -----------------------------------------------*/ +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + 2966 .loc 1 1093 3 is_stmt 1 view .LVU847 + 2967 .loc 1 1093 10 is_stmt 0 view .LVU848 + 2968 001e 1368 ldr r3, [r2] + 2969 .loc 1 1093 5 view .LVU849 + 2970 0020 13F0010F tst r3, #1 + 2971 0024 36D0 beq .L200 +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_ON; + 2972 .loc 1 1095 5 is_stmt 1 view .LVU850 + 2973 .loc 1 1095 33 is_stmt 0 view .LVU851 + 2974 0026 0123 movs r3, #1 + 2975 0028 0361 str r3, [r0, #16] + 2976 .L201: +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_OFF; +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RC + 2977 .loc 1 1102 3 is_stmt 1 view .LVU852 + 2978 .loc 1 1102 59 is_stmt 0 view .LVU853 + 2979 002a 2449 ldr r1, .L209 + 2980 002c 0B68 ldr r3, [r1] + 2981 .loc 1 1102 64 view .LVU854 + 2982 002e 03F0F803 and r3, r3, #248 + 2983 .LVL212: + 2984 .LBB287: + 2985 .LBI287: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 2986 .loc 2 981 31 is_stmt 1 view .LVU855 + 2987 .LBB288: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 2988 .loc 2 983 3 view .LVU856 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2989 .loc 2 988 4 view .LVU857 + 2990 0032 F822 movs r2, #248 + 2991 .syntax unified + 2992 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + ARM GAS /tmp/cczyIHoC.s page 98 + + + 2993 0034 92FAA2F2 rbit r2, r2 + 2994 @ 0 "" 2 + 2995 .LVL213: + 2996 .loc 2 1001 3 view .LVU858 + 2997 .loc 2 1001 3 is_stmt 0 view .LVU859 + 2998 .thumb + 2999 .syntax unified + 3000 .LBE288: + 3001 .LBE287: + 3002 .loc 1 1102 44 view .LVU860 + 3003 0038 B2FA82F2 clz r2, r2 + 3004 003c D340 lsrs r3, r3, r2 + 3005 .loc 1 1102 42 view .LVU861 + 3006 003e 4361 str r3, [r0, #20] +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the LSE configuration -----------------------------------------------*/ +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + 3007 .loc 1 1105 3 is_stmt 1 view .LVU862 + 3008 .loc 1 1105 10 is_stmt 0 view .LVU863 + 3009 0040 0B6A ldr r3, [r1, #32] + 3010 .loc 1 1105 5 view .LVU864 + 3011 0042 13F0040F tst r3, #4 + 3012 0046 28D0 beq .L202 +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + 3013 .loc 1 1107 5 is_stmt 1 view .LVU865 + 3014 .loc 1 1107 33 is_stmt 0 view .LVU866 + 3015 0048 0523 movs r3, #5 + 3016 004a C360 str r3, [r0, #12] + 3017 .L203: +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the LSI configuration -----------------------------------------------*/ +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + 3018 .loc 1 1119 3 is_stmt 1 view .LVU867 + 3019 .loc 1 1119 10 is_stmt 0 view .LVU868 + 3020 004c 1B4B ldr r3, .L209 + 3021 004e 5B6A ldr r3, [r3, #36] + 3022 .loc 1 1119 5 view .LVU869 + 3023 0050 13F0010F tst r3, #1 + 3024 0054 2CD0 beq .L205 +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_ON; + 3025 .loc 1 1121 5 is_stmt 1 view .LVU870 + 3026 .loc 1 1121 33 is_stmt 0 view .LVU871 + 3027 0056 0123 movs r3, #1 + 3028 0058 8361 str r3, [r0, #24] + 3029 .L206: +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + ARM GAS /tmp/cczyIHoC.s page 99 + + +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF; +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the PLL configuration -----------------------------------------------*/ +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + 3030 .loc 1 1130 3 is_stmt 1 view .LVU872 + 3031 .loc 1 1130 10 is_stmt 0 view .LVU873 + 3032 005a 184B ldr r3, .L209 + 3033 005c 1B68 ldr r3, [r3] + 3034 .loc 1 1130 5 view .LVU874 + 3035 005e 13F0807F tst r3, #16777216 + 3036 0062 28D0 beq .L207 +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + 3037 .loc 1 1132 5 is_stmt 1 view .LVU875 + 3038 .loc 1 1132 37 is_stmt 0 view .LVU876 + 3039 0064 0223 movs r3, #2 + 3040 0066 C361 str r3, [r0, #28] + 3041 .L208: +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + 3042 .loc 1 1138 3 is_stmt 1 view .LVU877 + 3043 .loc 1 1138 52 is_stmt 0 view .LVU878 + 3044 0068 144A ldr r2, .L209 + 3045 006a 5368 ldr r3, [r2, #4] + 3046 .loc 1 1138 38 view .LVU879 + 3047 006c 03F48033 and r3, r3, #65536 + 3048 .loc 1 1138 36 view .LVU880 + 3049 0070 0362 str r3, [r0, #32] +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + 3050 .loc 1 1139 3 is_stmt 1 view .LVU881 + 3051 .loc 1 1139 49 is_stmt 0 view .LVU882 + 3052 0072 5368 ldr r3, [r2, #4] + 3053 .loc 1 1139 35 view .LVU883 + 3054 0074 03F47013 and r3, r3, #3932160 + 3055 .loc 1 1139 33 view .LVU884 + 3056 0078 4362 str r3, [r0, #36] +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3057 .loc 1 1143 1 view .LVU885 + 3058 007a 7047 bx lr + 3059 .L197: +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3060 .loc 1 1080 8 is_stmt 1 view .LVU886 +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3061 .loc 1 1080 15 is_stmt 0 view .LVU887 + 3062 007c 0F4B ldr r3, .L209 + 3063 007e 1B68 ldr r3, [r3] + ARM GAS /tmp/cczyIHoC.s page 100 + + +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3064 .loc 1 1080 10 view .LVU888 + 3065 0080 13F4803F tst r3, #65536 + 3066 0084 03D0 beq .L199 +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3067 .loc 1 1082 5 is_stmt 1 view .LVU889 +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3068 .loc 1 1082 33 is_stmt 0 view .LVU890 + 3069 0086 4FF48033 mov r3, #65536 + 3070 008a 4360 str r3, [r0, #4] + 3071 008c C2E7 b .L198 + 3072 .L199: +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3073 .loc 1 1086 5 is_stmt 1 view .LVU891 +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3074 .loc 1 1086 33 is_stmt 0 view .LVU892 + 3075 008e 0023 movs r3, #0 + 3076 0090 4360 str r3, [r0, #4] + 3077 0092 BFE7 b .L198 + 3078 .L200: +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3079 .loc 1 1099 5 is_stmt 1 view .LVU893 +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3080 .loc 1 1099 33 is_stmt 0 view .LVU894 + 3081 0094 0023 movs r3, #0 + 3082 0096 0361 str r3, [r0, #16] + 3083 0098 C7E7 b .L201 + 3084 .L202: +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3085 .loc 1 1109 8 is_stmt 1 view .LVU895 +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3086 .loc 1 1109 15 is_stmt 0 view .LVU896 + 3087 009a 084B ldr r3, .L209 + 3088 009c 1B6A ldr r3, [r3, #32] +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3089 .loc 1 1109 10 view .LVU897 + 3090 009e 13F0010F tst r3, #1 + 3091 00a2 02D0 beq .L204 +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3092 .loc 1 1111 5 is_stmt 1 view .LVU898 +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3093 .loc 1 1111 33 is_stmt 0 view .LVU899 + 3094 00a4 0123 movs r3, #1 + 3095 00a6 C360 str r3, [r0, #12] + 3096 00a8 D0E7 b .L203 + 3097 .L204: +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3098 .loc 1 1115 5 is_stmt 1 view .LVU900 +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3099 .loc 1 1115 33 is_stmt 0 view .LVU901 + 3100 00aa 0023 movs r3, #0 + 3101 00ac C360 str r3, [r0, #12] + 3102 00ae CDE7 b .L203 + 3103 .L205: +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3104 .loc 1 1125 5 is_stmt 1 view .LVU902 +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + ARM GAS /tmp/cczyIHoC.s page 101 + + + 3105 .loc 1 1125 33 is_stmt 0 view .LVU903 + 3106 00b0 0023 movs r3, #0 + 3107 00b2 8361 str r3, [r0, #24] + 3108 00b4 D1E7 b .L206 + 3109 .L207: +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3110 .loc 1 1136 5 is_stmt 1 view .LVU904 +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3111 .loc 1 1136 37 is_stmt 0 view .LVU905 + 3112 00b6 0123 movs r3, #1 + 3113 00b8 C361 str r3, [r0, #28] + 3114 00ba D5E7 b .L208 + 3115 .L210: + 3116 .align 2 + 3117 .L209: + 3118 00bc 00100240 .word 1073876992 + 3119 .cfi_endproc + 3120 .LFE140: + 3122 .section .text.HAL_RCC_GetClockConfig,"ax",%progbits + 3123 .align 1 + 3124 .global HAL_RCC_GetClockConfig + 3125 .syntax unified + 3126 .thumb + 3127 .thumb_func + 3129 HAL_RCC_GetClockConfig: + 3130 .LVL214: + 3131 .LFB141: +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Get the RCC_ClkInitStruct according to the internal +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC configuration registers. +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the current clock configuration. +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param pFLatency Pointer on the Flash Latency. +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3132 .loc 1 1154 1 is_stmt 1 view -0 + 3133 .cfi_startproc + 3134 @ args = 0, pretend = 0, frame = 0 + 3135 @ frame_needed = 0, uses_anonymous_args = 0 + 3136 @ link register save eliminated. +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(RCC_ClkInitStruct != NULL); + 3137 .loc 1 1156 3 view .LVU907 +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(pFLatency != NULL); + 3138 .loc 1 1157 3 view .LVU908 +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set all possible values for the Clock type parameter --------------------*/ +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + 3139 .loc 1 1160 3 view .LVU909 + 3140 .loc 1 1160 32 is_stmt 0 view .LVU910 + 3141 0000 0F23 movs r3, #15 + 3142 0002 0360 str r3, [r0] +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/ + ARM GAS /tmp/cczyIHoC.s page 102 + + +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 3143 .loc 1 1163 3 is_stmt 1 view .LVU911 + 3144 .loc 1 1163 51 is_stmt 0 view .LVU912 + 3145 0004 0B4B ldr r3, .L212 + 3146 0006 5A68 ldr r2, [r3, #4] + 3147 .loc 1 1163 37 view .LVU913 + 3148 0008 02F00302 and r2, r2, #3 + 3149 .loc 1 1163 35 view .LVU914 + 3150 000c 4260 str r2, [r0, #4] +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HCLK configuration ----------------------------------------------*/ +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + 3151 .loc 1 1166 3 is_stmt 1 view .LVU915 + 3152 .loc 1 1166 52 is_stmt 0 view .LVU916 + 3153 000e 5A68 ldr r2, [r3, #4] + 3154 .loc 1 1166 38 view .LVU917 + 3155 0010 02F0F002 and r2, r2, #240 + 3156 .loc 1 1166 36 view .LVU918 + 3157 0014 8260 str r2, [r0, #8] +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + 3158 .loc 1 1169 3 is_stmt 1 view .LVU919 + 3159 .loc 1 1169 53 is_stmt 0 view .LVU920 + 3160 0016 5A68 ldr r2, [r3, #4] + 3161 .loc 1 1169 39 view .LVU921 + 3162 0018 02F4E062 and r2, r2, #1792 + 3163 .loc 1 1169 37 view .LVU922 + 3164 001c C260 str r2, [r0, #12] +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the APB2 configuration ----------------------------------------------*/ +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + 3165 .loc 1 1172 3 is_stmt 1 view .LVU923 + 3166 .loc 1 1172 54 is_stmt 0 view .LVU924 + 3167 001e 5B68 ldr r3, [r3, #4] + 3168 .loc 1 1172 39 view .LVU925 + 3169 0020 DB08 lsrs r3, r3, #3 + 3170 0022 03F4E063 and r3, r3, #1792 + 3171 .loc 1 1172 37 view .LVU926 + 3172 0026 0361 str r3, [r0, #16] +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the Flash Wait State (Latency) configuration ------------------------*/ +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 3173 .loc 1 1175 3 is_stmt 1 view .LVU927 + 3174 .loc 1 1175 32 is_stmt 0 view .LVU928 + 3175 0028 034B ldr r3, .L212+4 + 3176 002a 1B68 ldr r3, [r3] + 3177 .loc 1 1175 16 view .LVU929 + 3178 002c 03F00703 and r3, r3, #7 + 3179 .loc 1 1175 14 view .LVU930 + 3180 0030 0B60 str r3, [r1] +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3181 .loc 1 1176 1 view .LVU931 + 3182 0032 7047 bx lr + 3183 .L213: + 3184 .align 2 + 3185 .L212: + ARM GAS /tmp/cczyIHoC.s page 103 + + + 3186 0034 00100240 .word 1073876992 + 3187 0038 00200240 .word 1073881088 + 3188 .cfi_endproc + 3189 .LFE141: + 3191 .section .text.HAL_RCC_CSSCallback,"ax",%progbits + 3192 .align 1 + 3193 .weak HAL_RCC_CSSCallback + 3194 .syntax unified + 3195 .thumb + 3196 .thumb_func + 3198 HAL_RCC_CSSCallback: + 3199 .LFB143: +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief This function handles the RCC CSS interrupt request. +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This API should be called under the NMI_Handler(). +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void) +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check RCC CSSF flag */ +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_IT(RCC_IT_CSS)) +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_RCC_CSSCallback(); +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Clear RCC CSS pending bit */ +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_CLEAR_IT(RCC_IT_CSS); +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC Clock Security System interrupt callback +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval none +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void) +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3200 .loc 1 1201 1 is_stmt 1 view -0 + 3201 .cfi_startproc + 3202 @ args = 0, pretend = 0, frame = 0 + 3203 @ frame_needed = 0, uses_anonymous_args = 0 + 3204 @ link register save eliminated. +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the HAL_RCC_CSSCallback could be implemented in the user file +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3205 .loc 1 1205 1 view .LVU933 + 3206 0000 7047 bx lr + 3207 .cfi_endproc + 3208 .LFE143: + 3210 .section .text.HAL_RCC_NMI_IRQHandler,"ax",%progbits + 3211 .align 1 + 3212 .global HAL_RCC_NMI_IRQHandler + 3213 .syntax unified + 3214 .thumb + 3215 .thumb_func + 3217 HAL_RCC_NMI_IRQHandler: + ARM GAS /tmp/cczyIHoC.s page 104 + + + 3218 .LFB142: +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check RCC CSSF flag */ + 3219 .loc 1 1184 1 view -0 + 3220 .cfi_startproc + 3221 @ args = 0, pretend = 0, frame = 0 + 3222 @ frame_needed = 0, uses_anonymous_args = 0 + 3223 0000 08B5 push {r3, lr} + 3224 .cfi_def_cfa_offset 8 + 3225 .cfi_offset 3, -8 + 3226 .cfi_offset 14, -4 +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3227 .loc 1 1186 3 view .LVU935 +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3228 .loc 1 1186 6 is_stmt 0 view .LVU936 + 3229 0002 064B ldr r3, .L219 + 3230 0004 9B68 ldr r3, [r3, #8] +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3231 .loc 1 1186 5 view .LVU937 + 3232 0006 13F0800F tst r3, #128 + 3233 000a 00D1 bne .L218 + 3234 .L215: +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 3235 .loc 1 1194 1 view .LVU938 + 3236 000c 08BD pop {r3, pc} + 3237 .L218: +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 3238 .loc 1 1189 5 is_stmt 1 view .LVU939 + 3239 000e FFF7FEFF bl HAL_RCC_CSSCallback + 3240 .LVL215: +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3241 .loc 1 1192 5 view .LVU940 + 3242 0012 024B ldr r3, .L219 + 3243 0014 8022 movs r2, #128 + 3244 0016 9A72 strb r2, [r3, #10] +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 3245 .loc 1 1194 1 is_stmt 0 view .LVU941 + 3246 0018 F8E7 b .L215 + 3247 .L220: + 3248 001a 00BF .align 2 + 3249 .L219: + 3250 001c 00100240 .word 1073876992 + 3251 .cfi_endproc + 3252 .LFE142: + 3254 .global aPredivFactorTable + 3255 .section .rodata.aPredivFactorTable,"a" + 3256 .align 2 + 3259 aPredivFactorTable: + 3260 0000 01020304 .ascii "\001\002\003\004\005\006\007\010\011\012\013\014\015" + 3260 05060708 + 3260 090A0B0C + 3260 0D + 3261 000d 0E0F10 .ascii "\016\017\020" + 3262 .global aPLLMULFactorTable + 3263 .section .rodata.aPLLMULFactorTable,"a" + 3264 .align 2 + 3267 aPLLMULFactorTable: + 3268 0000 02030405 .ascii "\002\003\004\005\006\007\010\011\012\013\014\015\016" + ARM GAS /tmp/cczyIHoC.s page 105 + + + 3268 06070809 + 3268 0A0B0C0D + 3268 0E + 3269 000d 0F1010 .ascii "\017\020\020" + 3270 .text + 3271 .Letext0: + 3272 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 3273 .file 4 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 3274 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + 3275 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 3276 .file 7 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 3277 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 3278 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" + 3279 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 3280 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/cczyIHoC.s page 106 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_rcc.c + /tmp/cczyIHoC.s:21 .text.HAL_RCC_DeInit:0000000000000000 $t + /tmp/cczyIHoC.s:27 .text.HAL_RCC_DeInit:0000000000000000 HAL_RCC_DeInit + /tmp/cczyIHoC.s:228 .text.HAL_RCC_DeInit:00000000000000dc $d + /tmp/cczyIHoC.s:238 .text.HAL_RCC_OscConfig:0000000000000000 $t + /tmp/cczyIHoC.s:244 .text.HAL_RCC_OscConfig:0000000000000000 HAL_RCC_OscConfig + /tmp/cczyIHoC.s:1056 .text.HAL_RCC_OscConfig:00000000000002e8 $d + /tmp/cczyIHoC.s:1067 .text.HAL_RCC_OscConfig:00000000000002f0 $t + /tmp/cczyIHoC.s:1915 .text.HAL_RCC_OscConfig:00000000000005d8 $d + /tmp/cczyIHoC.s:1922 .text.HAL_RCC_OscConfig:00000000000005e4 $t + /tmp/cczyIHoC.s:2019 .text.HAL_RCC_OscConfig:000000000000062c $d + /tmp/cczyIHoC.s:2024 .text.HAL_RCC_MCOConfig:0000000000000000 $t + /tmp/cczyIHoC.s:2030 .text.HAL_RCC_MCOConfig:0000000000000000 HAL_RCC_MCOConfig + /tmp/cczyIHoC.s:2111 .text.HAL_RCC_MCOConfig:0000000000000048 $d + /tmp/cczyIHoC.s:2116 .text.HAL_RCC_EnableCSS:0000000000000000 $t + /tmp/cczyIHoC.s:2122 .text.HAL_RCC_EnableCSS:0000000000000000 HAL_RCC_EnableCSS + /tmp/cczyIHoC.s:2163 .text.HAL_RCC_DisableCSS:0000000000000000 $t + /tmp/cczyIHoC.s:2169 .text.HAL_RCC_DisableCSS:0000000000000000 HAL_RCC_DisableCSS + /tmp/cczyIHoC.s:2210 .text.HAL_RCC_GetSysClockFreq:0000000000000000 $t + /tmp/cczyIHoC.s:2216 .text.HAL_RCC_GetSysClockFreq:0000000000000000 HAL_RCC_GetSysClockFreq + /tmp/cczyIHoC.s:2337 .text.HAL_RCC_GetSysClockFreq:0000000000000064 $d + /tmp/cczyIHoC.s:3267 .rodata.aPLLMULFactorTable:0000000000000000 aPLLMULFactorTable + /tmp/cczyIHoC.s:3259 .rodata.aPredivFactorTable:0000000000000000 aPredivFactorTable + /tmp/cczyIHoC.s:2347 .text.HAL_RCC_ClockConfig:0000000000000000 $t + /tmp/cczyIHoC.s:2353 .text.HAL_RCC_ClockConfig:0000000000000000 HAL_RCC_ClockConfig + /tmp/cczyIHoC.s:2769 .text.HAL_RCC_ClockConfig:0000000000000194 $d + /tmp/cczyIHoC.s:2778 .text.HAL_RCC_GetHCLKFreq:0000000000000000 $t + /tmp/cczyIHoC.s:2784 .text.HAL_RCC_GetHCLKFreq:0000000000000000 HAL_RCC_GetHCLKFreq + /tmp/cczyIHoC.s:2799 .text.HAL_RCC_GetHCLKFreq:0000000000000008 $d + /tmp/cczyIHoC.s:2804 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 $t + /tmp/cczyIHoC.s:2810 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 HAL_RCC_GetPCLK1Freq + /tmp/cczyIHoC.s:2860 .text.HAL_RCC_GetPCLK1Freq:0000000000000024 $d + /tmp/cczyIHoC.s:2866 .text.HAL_RCC_GetPCLK2Freq:0000000000000000 $t + /tmp/cczyIHoC.s:2872 .text.HAL_RCC_GetPCLK2Freq:0000000000000000 HAL_RCC_GetPCLK2Freq + /tmp/cczyIHoC.s:2922 .text.HAL_RCC_GetPCLK2Freq:0000000000000024 $d + /tmp/cczyIHoC.s:2928 .text.HAL_RCC_GetOscConfig:0000000000000000 $t + /tmp/cczyIHoC.s:2934 .text.HAL_RCC_GetOscConfig:0000000000000000 HAL_RCC_GetOscConfig + /tmp/cczyIHoC.s:3118 .text.HAL_RCC_GetOscConfig:00000000000000bc $d + /tmp/cczyIHoC.s:3123 .text.HAL_RCC_GetClockConfig:0000000000000000 $t + /tmp/cczyIHoC.s:3129 .text.HAL_RCC_GetClockConfig:0000000000000000 HAL_RCC_GetClockConfig + /tmp/cczyIHoC.s:3186 .text.HAL_RCC_GetClockConfig:0000000000000034 $d + /tmp/cczyIHoC.s:3192 .text.HAL_RCC_CSSCallback:0000000000000000 $t + /tmp/cczyIHoC.s:3198 .text.HAL_RCC_CSSCallback:0000000000000000 HAL_RCC_CSSCallback + /tmp/cczyIHoC.s:3211 .text.HAL_RCC_NMI_IRQHandler:0000000000000000 $t + /tmp/cczyIHoC.s:3217 .text.HAL_RCC_NMI_IRQHandler:0000000000000000 HAL_RCC_NMI_IRQHandler + /tmp/cczyIHoC.s:3250 .text.HAL_RCC_NMI_IRQHandler:000000000000001c $d + /tmp/cczyIHoC.s:3256 .rodata.aPredivFactorTable:0000000000000000 $d + /tmp/cczyIHoC.s:3264 .rodata.aPLLMULFactorTable:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_InitTick +SystemCoreClock +uwTickPrio +HAL_GPIO_Init +AHBPrescTable + ARM GAS /tmp/cczyIHoC.s page 107 + + +APBPrescTable diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc.o new file mode 100644 index 0000000000000000000000000000000000000000..9476579c8fb7158b415452ecc6fbbc541e311728 GIT binary patch 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Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc_ex.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc_ex.lst new file mode 100644 index 0000000..12d9789 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc_ex.lst @@ -0,0 +1,4835 @@ +ARM GAS /tmp/ccLRMPc2.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_rcc_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c" + 20 .section .text.RCC_GetPLLCLKFreq,"ax",%progbits + 21 .align 1 + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 RCC_GetPLLCLKFreq: + 27 .LFB133: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @file stm32f3xx_hal_rcc_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Extended RCC HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * functionalities RCC extension peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + Extended Peripheral Control functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** ****************************************************************************** + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @attention + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * All rights reserved.

    + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * the "License"; You may not use this file except in compliance with the + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * License. You may obtain a copy of the License at: + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * opensource.org/licenses/BSD-3-Clause + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** ****************************************************************************** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/ + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #include "stm32f3xx_hal.h" + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED + ARM GAS /tmp/ccLRMPc2.s page 2 + + + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief RCC Extension HAL module driver. + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private define ------------------------------------------------------------*/ + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private macro -------------------------------------------------------------*/ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Macros RCCEx Private Macros + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @} + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/ + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private functions ---------------------------------------------------------*/ + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || de + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined( + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defin + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_HRTIM1SW) + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Functions RCCEx Private Functions + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** static uint32_t RCC_GetPLLCLKFreq(void); + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @} + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Extended Peripheral Control functions + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @verbatim + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** =============================================================================== + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** ##### Extended Peripheral Control functions ##### + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** =============================================================================== + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** [..] + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequencies. + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** [..] + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** select the RTC clock source; in this case the Backup domain will be reset in + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** order to modify the RTC Clock source, as consequence RTC registers (including + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** the backup registers) are set to their reset values. + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endverbatim + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccLRMPc2.s page 3 + + + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Initializes the RCC extended peripherals clocks according to the specified + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * parameters in the RCC_PeriphCLKInitTypeDef. + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * contains the configuration information for the Extended Peripherals clocks + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB). + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * the RTC clock source; in this case the Backup domain will be reset in + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * order to modify the RTC Clock source, as consequence RTC registers (including + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * the backup registers) and RCC_BDCR register are set to their reset values. + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @note When the TIMx clock source is APB clock, so the TIMx clock is APB clock or + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * APB clock x 2 depending on the APB prescaler. + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @retval HAL status + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t tickstart = 0U; + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t temp_reg = 0U; + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET; + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*---------------------------- RTC configuration -------------------------------*/ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* check for RTC Parameters used to output RTCCLK */ + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* As soon as function is called to change RTC clock source, activation of the + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** power domain is done. */ + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Requires to enable write access to Backup Domain of necessary */ + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Enable write access to Backup domain */ + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Wait for Backup domain Write protection disable */ + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccLRMPc2.s page 4 + + + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSE + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Store the content of BDCR register before the reset of Backup Domain */ + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_FORCE(); + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** RCC->BDCR = temp_reg; + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Wait for LSERDY if LSE was enabled */ + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get Start Tick */ + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Wait till LSE is ready */ + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Require to disable power clock if necessary */ + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(pwrclkchanged == SET) + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------- USART1 Configuration ------------------------*/ + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the USART1 clock source */ + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*----------------------------- USART2 Configuration --------------------------*/ + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccLRMPc2.s page 5 + + + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the USART2 clock source */ + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART3SW) + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ USART3 Configuration ------------------------*/ + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the USART3 clock source */ + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ I2C1 Configuration ------------------------*/ + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the I2C1 clock source */ + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE)\ + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC)\ + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302x8) \ + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ USB Configuration ------------------------*/ + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the USB clock source */ + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || */ + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302x8 || */ + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC */ + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) || defined(STM32F378xx) + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ I2C2 Configuration ------------------------*/ + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccLRMPc2.s page 6 + + + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the I2C2 clock source */ + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC || STM32F378xx */ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ I2C3 Configuration ------------------------*/ + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the I2C3 clock source */ + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ UART4 Configuration ------------------------*/ + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the UART4 clock source */ + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ UART5 Configuration ------------------------*/ + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the UART5 clock source */ + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx */ + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ I2S Configuration ------------------------*/ + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + ARM GAS /tmp/ccLRMPc2.s page 7 + + + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the I2S clock source */ + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ ADC1 clock Configuration ------------------*/ + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1) + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection)); + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the ADC1 clock source */ + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection); + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the ADC12 clock source */ + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx)\ + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303xC) || defined(STM32F358xx) + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34) + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection)); + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the ADC34 clock source */ + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection); + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx || */ + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303xC || STM32F358xx */ + ARM GAS /tmp/ccLRMPc2.s page 8 + + + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F373xC) || defined(STM32F378xx) + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ ADC1 clock Configuration ------------------*/ + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1) + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection)); + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the ADC1 clock source */ + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection); + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F373xC || STM32F378xx */ + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM1 clock Configuration ----------------*/ + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM1 clock source */ + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx)\ + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303xC) || defined(STM32F358xx) + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM8 clock Configuration ----------------*/ + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8) + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection)); + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM8 clock source */ + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection); + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx || */ + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303xC || STM32F358xx */ + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM15 clock Configuration ----------------*/ + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + ARM GAS /tmp/ccLRMPc2.s page 9 + + + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM15 clock source */ + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM16 clock Configuration ----------------*/ + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16) + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection)); + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM16 clock source */ + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection); + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM17 clock Configuration ----------------*/ + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17) + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection)); + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM17 clock source */ + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection); + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F334x8) + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ HRTIM1 clock Configuration ----------------*/ + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the HRTIM1 clock source */ + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F334x8 */ + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F373xC) || defined(STM32F378xx) + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ SDADC clock Configuration -------------------*/ + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC) + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection)); + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the SDADC clock prescaler */ + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection); + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ CEC clock Configuration -------------------*/ + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccLRMPc2.s page 10 + + + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F373xC || STM32F378xx */ + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM2 clock Configuration -------------------*/ + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2) + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection)); + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection); + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM3 clock Configuration -------------------*/ + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34) + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection)); + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection); + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM15 clock Configuration ------------------*/ + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM16 clock Configuration ------------------*/ + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16) + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection)); + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection); + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM17 clock Configuration ------------------*/ + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17) + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection)); + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccLRMPc2.s page 11 + + + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection); + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx) + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM20 clock Configuration ------------------*/ + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20) + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection)); + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx */ + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return HAL_OK; + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Get the RCC_ClkInitStruct according to the internal + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * RCC configuration registers. + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * returns the configuration information for the Extended Peripherals clocks + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks). + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @retval None + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/ + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Common part first */ + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #else + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \ + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the RTC configuration --------------------------------------------*/ + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART1 clock configuration --------------------------------------------*/ + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART2 clock configuration -----------------------------------------*/ + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART3SW) + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART3 clock configuration -----------------------------------------*/ + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2C1 clock configuration -----------------------------------------*/ + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccLRMPc2.s page 12 + + + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE)\ + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC)\ + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302x8) \ + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USB clock configuration -----------------------------------------*/ + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE(); + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || */ + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || */ + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302x8 || */ + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC */ + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) || defined(STM32F378xx) + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2; + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2C2 clock configuration -----------------------------------------*/ + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC || STM32F378xx */ + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3; + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2C3 clock configuration -----------------------------------------*/ + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5); + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART4 clock configuration -----------------------------------------*/ + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART5 clock configuration -----------------------------------------*/ + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx */ + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S; + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2S clock configuration -----------------------------------------*/ + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); + ARM GAS /tmp/ccLRMPc2.s page 13 + + + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) || defined(STM32F378xx) + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1; + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the ADC1 clock configuration -----------------------------------------*/ + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE(); + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC || STM32F378xx */ + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12; + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/ + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE(); + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx)\ + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303xC) || defined(STM32F358xx) + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34; + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/ + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE(); + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx || */ + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303xC || STM32F358xx */ + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1; + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM1 clock configuration -----------------------------------------*/ + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE(); + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx)\ + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303xC) || defined(STM32F358xx) + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8; + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM8 clock configuration -----------------------------------------*/ + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE(); + ARM GAS /tmp/ccLRMPc2.s page 14 + + + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx || */ + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303xC || STM32F358xx */ + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM15 clock configuration -----------------------------------------*/ + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM16 clock configuration -----------------------------------------*/ + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE(); + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM17 clock configuration -----------------------------------------*/ + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE(); + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F334x8) + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the HRTIM1 clock configuration -----------------------------------------*/ + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F334x8 */ + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F373xC) || defined(STM32F378xx) + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC; + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the SDADC clock configuration -----------------------------------------*/ + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE(); + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the CEC clock configuration -----------------------------------------*/ + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F373xC || STM32F378xx */ + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2; + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM2 clock configuration -----------------------------------------*/ + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE(); + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34; + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM3 clock configuration -----------------------------------------*/ + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE(); + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15; + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM15 clock configuration -----------------------------------------*/ + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16; + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM16 clock configuration -----------------------------------------*/ + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE(); + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17; + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM17 clock configuration -----------------------------------------*/ + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE(); + ARM GAS /tmp/ccLRMPc2.s page 15 + + + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined (STM32F303xE) || defined(STM32F398xx) + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20; + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM20 clock configuration -----------------------------------------*/ + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE(); + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx */ + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Returns the peripheral clock frequency + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable. + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @param PeriphClk Peripheral clock identifier + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * This parameter can be one of the following values: + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F301x8 + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F302x8 + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F302xC + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F302xE + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + ARM GAS /tmp/ccLRMPc2.s page 16 + + + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F303x8 + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F303xC + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F303xE + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F318xx + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + ARM GAS /tmp/ccLRMPc2.s page 17 + + + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F328xx + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F334x8 + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F358xx + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F373xC + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F378xx + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F398xx + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + ARM GAS /tmp/ccLRMPc2.s page 18 + + + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* frequency == 0 : means that no available frequency for the peripheral */ + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t frequency = 0U; + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t srcclk = 0U; + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint16_t adc_pll_prediv_table[16] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_SDPRE) + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 3 + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_SDPRE */ + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** switch (PeriphClk) + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_RTC: + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current RTC source */ + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_RTC_SOURCE(); + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if RTC clock selection is LSE */ + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSI is ready and if RTC clock selection is LSI */ + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSI_VALUE; + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSE_VALUE / 32U; + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART1: + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current USART1 source */ + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART1_SOURCE(); + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART1 clock selection is PCLK1 */ + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_USART1CLKSOURCE_PCLK2) + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK2Freq(); + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #else + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USART1CLKSOURCE_PCLK1) + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + ARM GAS /tmp/ccLRMPc2.s page 19 + + +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_USART1CLKSOURCE_PCLK2 */ +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if USART1 clock selection is HSI */ +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART1 clock selection is SYSCLK */ +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if USART1 clock selection is LSE */ +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART2: +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current USART2 source */ +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART2_SOURCE(); +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART2 clock selection is PCLK1 */ +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USART2CLKSOURCE_PCLK1) +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if USART2 clock selection is HSI */ +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART2 clock selection is SYSCLK */ +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if USART2 clock selection is LSE */ +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART3SW) +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART3: +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current USART3 source */ +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART3_SOURCE(); +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART3 clock selection is PCLK1 */ +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USART3CLKSOURCE_PCLK1) +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccLRMPc2.s page 20 + + +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if USART3 clock selection is HSI */ +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART3 clock selection is SYSCLK */ +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if USART3 clock selection is LSE */ +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_UART4SW) +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_UART4: +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current UART4 source */ +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_UART4_SOURCE(); +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if UART4 clock selection is PCLK1 */ +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_UART4CLKSOURCE_PCLK1) +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if UART4 clock selection is HSI */ +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if UART4 clock selection is SYSCLK */ +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if UART4 clock selection is LSE */ +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_UART4SW */ +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_UART5SW) +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_UART5: +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current UART5 source */ +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_UART5_SOURCE(); +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if UART5 clock selection is PCLK1 */ +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_UART5CLKSOURCE_PCLK1) + ARM GAS /tmp/ccLRMPc2.s page 21 + + +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if UART5 clock selection is HSI */ +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if UART5 clock selection is SYSCLK */ +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if UART5 clock selection is LSE */ +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_UART5SW */ +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C1: +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current I2C1 source */ +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C1_SOURCE(); +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if I2C1 clock selection is HSI */ +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2C1 clock selection is SYSCLK */ +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_I2C2SW) +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C2: +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current I2C2 source */ +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C2_SOURCE(); +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if I2C2 clock selection is HSI */ +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2C2 clock selection is SYSCLK */ +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_I2C2SW */ + ARM GAS /tmp/ccLRMPc2.s page 22 + + +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_I2C3SW) +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C3: +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current I2C3 source */ +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C3_SOURCE(); +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if I2C3 clock selection is HSI */ +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2C3 clock selection is SYSCLK */ +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_I2C3SW */ +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_I2SSRC) +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2S: +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current I2S source */ +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2S_SOURCE(); +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */ +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_I2SCLKSOURCE_EXT) +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* External clock used. Frequency cannot be returned.*/ +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = 0xDEADDEADU; +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2S clock selection is SYSCLK */ +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK) +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_I2SSRC */ +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_USBPRE) +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USB: +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready */ +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current USB source */ +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USB_SOURCE(); +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USB clock selection is not divided */ +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USBCLKSOURCE_PLL) +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USB clock selection is divided by 1.5 */ +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */ +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U; + ARM GAS /tmp/ccLRMPc2.s page 23 + + +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_USBPRE */ +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE) +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC1: +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current ADC1 source */ +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC1_SOURCE(); +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC1 clock selection is AHB */ +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_ADC1PLLCLK_OFF) +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* PLL clock has been selected */ +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready */ +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32 +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #else /* RCC_CFGR_ADCPRE */ +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */ +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U) +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES */ +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */ +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADCPRE12) +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC12: +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current ADC12 source */ +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC12_SOURCE(); +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC12 clock selection is AHB */ +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_ADC12PLLCLK_OFF) +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* PLL clock has been selected */ +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready */ +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADCPRE12 */ +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADCPRE34) + ARM GAS /tmp/ccLRMPc2.s page 24 + + +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC34: +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current ADC34 source */ +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC34_SOURCE(); +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC34 clock selection is AHB */ +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_ADC34PLLCLK_OFF) +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* PLL clock has been selected */ +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready */ +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32 +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADCPRE34 */ +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM1SW) +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM1: +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM1 source */ +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM1_SOURCE(); +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM1 clock selection is PLL */ +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM1 clock selection is SYSCLK */ +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM1CLK_HCLK) +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM1SW */ +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM2SW) +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM2: +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM2 source */ +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM2_SOURCE(); +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM2 clock selection is PLL */ +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM2 clock selection is SYSCLK */ +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM2CLK_HCLK) +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccLRMPc2.s page 25 + + +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM2SW */ +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM8SW) +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM8: +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM8 source */ +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM8_SOURCE(); +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM8 clock selection is PLL */ +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM8 clock selection is SYSCLK */ +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM8CLK_HCLK) +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM8SW */ +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM15SW) +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM15: +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM15 source */ +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM15_SOURCE(); +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM15 clock selection is PLL */ +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM15 clock selection is SYSCLK */ +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM15CLK_HCLK) +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM15SW */ +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM16SW) +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM16: +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM16 source */ +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM16_SOURCE(); +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM16 clock selection is PLL */ +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM16 clock selection is SYSCLK */ +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM16CLK_HCLK) +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccLRMPc2.s page 26 + + +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM16SW */ +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM17SW) +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM17: +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM17 source */ +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM17_SOURCE(); +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM17 clock selection is PLL */ +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM17 clock selection is SYSCLK */ +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM17CLK_HCLK) +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM17SW */ +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM20SW) +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM20: +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM20 source */ +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM20_SOURCE(); +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM20 clock selection is PLL */ +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM20 clock selection is SYSCLK */ +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM20CLK_HCLK) +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM20SW */ +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM34SW) +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM34: +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM34 source */ +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM34_SOURCE(); +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM34 clock selection is PLL */ +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM34 clock selection is SYSCLK */ +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM34CLK_HCLK) +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccLRMPc2.s page 27 + + +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM34SW */ +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_HRTIM1SW) +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_HRTIM1: +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current HRTIM1 source */ +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_HRTIM1_SOURCE(); +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if HRTIM1 clock selection is PLL */ +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HRTIM1 clock selection is SYSCLK */ +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_HRTIM1CLK_HCLK) +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_HRTIM1SW */ +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_SDPRE) +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_SDADC: +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current SDADC source */ +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_SDADC_SOURCE(); +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/ +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_SDPRE */ +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_CECSW) +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_CEC: +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current CEC source */ +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_CEC_SOURCE(); +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if CEC clock selection is HSI */ +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if CEC clock selection is LSE */ +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_CECSW */ +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** default: +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return(frequency); + ARM GAS /tmp/ccLRMPc2.s page 28 + + +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @} +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @} +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || de +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined( +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defin +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_HRTIM1SW) +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @addtogroup RCCEx_Private_Functions +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** static uint32_t RCC_GetPLLCLKFreq(void) +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 28 .loc 1 1534 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U; + 33 .loc 1 1535 3 view .LVU1 + 34 .LVL0: +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + 35 .loc 1 1537 3 view .LVU2 + 36 .loc 1 1537 15 is_stmt 0 view .LVU3 + 37 0000 0B4B ldr r3, .L4 + 38 0002 5868 ldr r0, [r3, #4] + 39 .LVL1: +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllmul = ( pllmul >> 18U) + 2U; + 40 .loc 1 1538 3 is_stmt 1 view .LVU4 + 41 .loc 1 1538 21 is_stmt 0 view .LVU5 + 42 0004 C0F38340 ubfx r0, r0, #18, #4 + 43 .LVL2: + 44 .loc 1 1538 10 view .LVU6 + 45 0008 0230 adds r0, r0, #2 + 46 .LVL3: +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 47 .loc 1 1539 3 is_stmt 1 view .LVU7 + 48 .loc 1 1539 18 is_stmt 0 view .LVU8 + 49 000a 5B68 ldr r3, [r3, #4] + 50 .LVL4: +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (pllsource != RCC_PLLSOURCE_HSI) + 51 .loc 1 1541 3 is_stmt 1 view .LVU9 + 52 .loc 1 1541 6 is_stmt 0 view .LVU10 + 53 000c 13F4803F tst r3, #65536 + 54 0010 0AD0 beq .L2 +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; + ARM GAS /tmp/ccLRMPc2.s page 29 + + + 55 .loc 1 1543 5 is_stmt 1 view .LVU11 + 56 .loc 1 1543 18 is_stmt 0 view .LVU12 + 57 0012 074B ldr r3, .L4 + 58 .LVL5: + 59 .loc 1 1543 18 view .LVU13 + 60 0014 DB6A ldr r3, [r3, #44] + 61 .loc 1 1543 26 view .LVU14 + 62 0016 03F00F03 and r3, r3, #15 + 63 .loc 1 1543 12 view .LVU15 + 64 001a 0133 adds r3, r3, #1 + 65 .LVL6: +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllclk = (HSE_VALUE/prediv) * pllmul; + 66 .loc 1 1545 5 is_stmt 1 view .LVU16 + 67 .loc 1 1545 24 is_stmt 0 view .LVU17 + 68 001c 054A ldr r2, .L4+4 + 69 001e B2FBF3F3 udiv r3, r2, r3 + 70 .LVL7: + 71 .loc 1 1545 12 view .LVU18 + 72 0022 03FB00F0 mul r0, r3, r0 + 73 .LVL8: + 74 .loc 1 1545 12 view .LVU19 + 75 0026 7047 bx lr + 76 .LVL9: + 77 .L2: +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */ +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllclk = (HSI_VALUE >> 1U) * pllmul; + 78 .loc 1 1550 5 is_stmt 1 view .LVU20 + 79 .loc 1 1550 12 is_stmt 0 view .LVU21 + 80 0028 034B ldr r3, .L4+8 + 81 .LVL10: + 82 .loc 1 1550 12 view .LVU22 + 83 002a 03FB00F0 mul r0, r3, r0 + 84 .LVL11: +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #else +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllclk = (HSE_VALUE/prediv) * pllmul; +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllclk = (HSI_VALUE/prediv) * pllmul; +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return pllclk; + 85 .loc 1 1566 3 is_stmt 1 view .LVU23 +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 86 .loc 1 1567 1 is_stmt 0 view .LVU24 + 87 002e 7047 bx lr + ARM GAS /tmp/ccLRMPc2.s page 30 + + + 88 .L5: + 89 .align 2 + 90 .L4: + 91 0030 00100240 .word 1073876992 + 92 0034 0024F400 .word 16000000 + 93 0038 00093D00 .word 4000000 + 94 .cfi_endproc + 95 .LFE133: + 97 .section .text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits + 98 .align 1 + 99 .global HAL_RCCEx_PeriphCLKConfig + 100 .syntax unified + 101 .thumb + 102 .thumb_func + 104 HAL_RCCEx_PeriphCLKConfig: + 105 .LVL12: + 106 .LFB130: + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t tickstart = 0U; + 107 .loc 1 108 1 is_stmt 1 view -0 + 108 .cfi_startproc + 109 @ args = 0, pretend = 0, frame = 8 + 110 @ frame_needed = 0, uses_anonymous_args = 0 + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t tickstart = 0U; + 111 .loc 1 108 1 is_stmt 0 view .LVU26 + 112 0000 F0B5 push {r4, r5, r6, r7, lr} + 113 .cfi_def_cfa_offset 20 + 114 .cfi_offset 4, -20 + 115 .cfi_offset 5, -16 + 116 .cfi_offset 6, -12 + 117 .cfi_offset 7, -8 + 118 .cfi_offset 14, -4 + 119 0002 83B0 sub sp, sp, #12 + 120 .cfi_def_cfa_offset 32 + 121 0004 0446 mov r4, r0 + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t temp_reg = 0U; + 122 .loc 1 109 3 is_stmt 1 view .LVU27 + 123 .LVL13: + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET; + 124 .loc 1 110 3 view .LVU28 + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 125 .loc 1 111 3 view .LVU29 + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 126 .loc 1 114 3 view .LVU30 + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 127 .loc 1 117 3 view .LVU31 + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 128 .loc 1 117 21 is_stmt 0 view .LVU32 + 129 0006 0368 ldr r3, [r0] + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 130 .loc 1 117 5 view .LVU33 + 131 0008 13F4803F tst r3, #65536 + 132 000c 48D0 beq .L7 + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 133 .loc 1 120 5 is_stmt 1 view .LVU34 + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 134 .loc 1 126 5 view .LVU35 + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccLRMPc2.s page 31 + + + 135 .loc 1 126 8 is_stmt 0 view .LVU36 + 136 000e 864B ldr r3, .L36 + 137 0010 DB69 ldr r3, [r3, #28] + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 138 .loc 1 126 7 view .LVU37 + 139 0012 13F0805F tst r3, #268435456 + 140 0016 40F0BE80 bne .L28 + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 141 .loc 1 128 7 is_stmt 1 view .LVU38 + 142 .LBB17: + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 143 .loc 1 128 7 view .LVU39 + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 144 .loc 1 128 7 view .LVU40 + 145 001a 834B ldr r3, .L36 + 146 001c DA69 ldr r2, [r3, #28] + 147 001e 42F08052 orr r2, r2, #268435456 + 148 0022 DA61 str r2, [r3, #28] + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 149 .loc 1 128 7 view .LVU41 + 150 0024 DB69 ldr r3, [r3, #28] + 151 0026 03F08053 and r3, r3, #268435456 + 152 002a 0193 str r3, [sp, #4] + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 153 .loc 1 128 7 view .LVU42 + 154 002c 019B ldr r3, [sp, #4] + 155 .LBE17: + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 156 .loc 1 128 7 view .LVU43 + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 157 .loc 1 129 7 view .LVU44 + 158 .LVL14: + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 159 .loc 1 129 21 is_stmt 0 view .LVU45 + 160 002e 0125 movs r5, #1 + 161 .LVL15: + 162 .L8: + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 163 .loc 1 132 5 is_stmt 1 view .LVU46 + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 164 .loc 1 132 8 is_stmt 0 view .LVU47 + 165 0030 7E4B ldr r3, .L36+4 + 166 0032 1B68 ldr r3, [r3] + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 167 .loc 1 132 7 view .LVU48 + 168 0034 13F4807F tst r3, #256 + 169 0038 00F0AF80 beq .L33 + 170 .LVL16: + 171 .L9: + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSE + 172 .loc 1 150 5 is_stmt 1 view .LVU49 + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSE + 173 .loc 1 150 20 is_stmt 0 view .LVU50 + 174 003c 7A4B ldr r3, .L36 + 175 003e 1B6A ldr r3, [r3, #32] + 176 .LVL17: + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccLRMPc2.s page 32 + + + 177 .loc 1 151 5 is_stmt 1 view .LVU51 + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 178 .loc 1 151 7 is_stmt 0 view .LVU52 + 179 0040 13F44073 ands r3, r3, #768 + 180 .LVL18: + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 181 .loc 1 151 7 view .LVU53 + 182 0044 22D0 beq .L13 + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 183 .loc 1 151 64 discriminator 1 view .LVU54 + 184 0046 6268 ldr r2, [r4, #4] + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 185 .loc 1 151 84 discriminator 1 view .LVU55 + 186 0048 02F44072 and r2, r2, #768 + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 187 .loc 1 151 34 discriminator 1 view .LVU56 + 188 004c 9A42 cmp r2, r3 + 189 004e 1DD0 beq .L13 + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 190 .loc 1 154 7 is_stmt 1 view .LVU57 + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 191 .loc 1 154 22 is_stmt 0 view .LVU58 + 192 0050 7548 ldr r0, .L36 + 193 0052 016A ldr r1, [r0, #32] + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 194 .loc 1 154 16 view .LVU59 + 195 0054 21F44076 bic r6, r1, #768 + 196 .LVL19: + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 197 .loc 1 156 7 is_stmt 1 view .LVU60 + 198 .LBB18: + 199 .LBI18: + 200 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccLRMPc2.s page 33 + + + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + ARM GAS /tmp/ccLRMPc2.s page 34 + + + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + ARM GAS /tmp/ccLRMPc2.s page 35 + + + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + ARM GAS /tmp/ccLRMPc2.s page 36 + + + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccLRMPc2.s page 37 + + + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccLRMPc2.s page 38 + + + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + ARM GAS /tmp/ccLRMPc2.s page 39 + + + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccLRMPc2.s page 40 + + + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + ARM GAS /tmp/ccLRMPc2.s page 41 + + + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccLRMPc2.s page 42 + + + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + ARM GAS /tmp/ccLRMPc2.s page 43 + + + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + ARM GAS /tmp/ccLRMPc2.s page 44 + + + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccLRMPc2.s page 45 + + + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccLRMPc2.s page 46 + + + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + ARM GAS /tmp/ccLRMPc2.s page 47 + + + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + ARM GAS /tmp/ccLRMPc2.s page 48 + + + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + ARM GAS /tmp/ccLRMPc2.s page 49 + + + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 201 .loc 2 981 31 view .LVU61 + 202 .LBB19: + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 203 .loc 2 983 3 view .LVU62 + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 204 .loc 2 988 4 view .LVU63 + 205 0058 4FF48033 mov r3, #65536 + ARM GAS /tmp/ccLRMPc2.s page 50 + + + 206 .syntax unified + 207 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 208 005c 93FAA3F2 rbit r2, r3 + 209 @ 0 "" 2 + 210 .LVL20: + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 211 .loc 2 1001 3 view .LVU64 + 212 .loc 2 1001 3 is_stmt 0 view .LVU65 + 213 .thumb + 214 .syntax unified + 215 .LBE19: + 216 .LBE18: + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 217 .loc 1 156 7 view .LVU66 + 218 0060 B2FA82F2 clz r2, r2 + 219 0064 724F ldr r7, .L36+8 + 220 0066 3A44 add r2, r2, r7 + 221 0068 9200 lsls r2, r2, #2 + 222 006a 4FF0010C mov ip, #1 + 223 006e C2F800C0 str ip, [r2] + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + 224 .loc 1 157 7 is_stmt 1 view .LVU67 + 225 .LVL21: + 226 .LBB20: + 227 .LBI20: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 228 .loc 2 981 31 view .LVU68 + 229 .LBB21: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 230 .loc 2 983 3 view .LVU69 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 231 .loc 2 988 4 view .LVU70 + 232 .syntax unified + 233 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 234 0072 93FAA3F3 rbit r3, r3 + 235 @ 0 "" 2 + 236 .LVL22: + 237 .loc 2 1001 3 view .LVU71 + 238 .loc 2 1001 3 is_stmt 0 view .LVU72 + 239 .thumb + 240 .syntax unified + 241 .LBE21: + 242 .LBE20: + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + 243 .loc 1 157 7 view .LVU73 + ARM GAS /tmp/ccLRMPc2.s page 51 + + + 244 0076 B3FA83F3 clz r3, r3 + 245 007a 3B44 add r3, r3, r7 + 246 007c 9B00 lsls r3, r3, #2 + 247 007e 0022 movs r2, #0 + 248 0080 1A60 str r2, [r3] + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 249 .loc 1 159 7 is_stmt 1 view .LVU74 + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 250 .loc 1 159 17 is_stmt 0 view .LVU75 + 251 0082 0662 str r6, [r0, #32] + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 252 .loc 1 162 7 is_stmt 1 view .LVU76 + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 253 .loc 1 162 10 is_stmt 0 view .LVU77 + 254 0084 11F0010F tst r1, #1 + 255 0088 40F09C80 bne .L34 + 256 .LVL23: + 257 .L13: + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 258 .loc 1 177 5 is_stmt 1 view .LVU78 + 259 008c 664A ldr r2, .L36 + 260 008e 136A ldr r3, [r2, #32] + 261 0090 23F44073 bic r3, r3, #768 + 262 0094 6168 ldr r1, [r4, #4] + 263 0096 0B43 orrs r3, r3, r1 + 264 0098 1362 str r3, [r2, #32] + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 265 .loc 1 180 5 view .LVU79 + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 266 .loc 1 180 7 is_stmt 0 view .LVU80 + 267 009a 002D cmp r5, #0 + 268 009c 40F0B980 bne .L35 + 269 .LVL24: + 270 .L7: + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 271 .loc 1 187 3 is_stmt 1 view .LVU81 + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 272 .loc 1 187 21 is_stmt 0 view .LVU82 + 273 00a0 2368 ldr r3, [r4] + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 274 .loc 1 187 5 view .LVU83 + 275 00a2 13F0010F tst r3, #1 + 276 00a6 06D0 beq .L18 + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 277 .loc 1 190 5 is_stmt 1 view .LVU84 + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 278 .loc 1 193 5 view .LVU85 + 279 00a8 5F4A ldr r2, .L36 + 280 00aa 136B ldr r3, [r2, #48] + 281 00ac 23F00303 bic r3, r3, #3 + 282 00b0 A168 ldr r1, [r4, #8] + 283 00b2 0B43 orrs r3, r3, r1 + 284 00b4 1363 str r3, [r2, #48] + 285 .L18: + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 286 .loc 1 198 3 view .LVU86 + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccLRMPc2.s page 52 + + + 287 .loc 1 198 21 is_stmt 0 view .LVU87 + 288 00b6 2368 ldr r3, [r4] + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 289 .loc 1 198 5 view .LVU88 + 290 00b8 13F0020F tst r3, #2 + 291 00bc 06D0 beq .L19 + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 292 .loc 1 201 5 is_stmt 1 view .LVU89 + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 293 .loc 1 204 5 view .LVU90 + 294 00be 5A4A ldr r2, .L36 + 295 00c0 136B ldr r3, [r2, #48] + 296 00c2 23F44033 bic r3, r3, #196608 + 297 00c6 E168 ldr r1, [r4, #12] + 298 00c8 0B43 orrs r3, r3, r1 + 299 00ca 1363 str r3, [r2, #48] + 300 .L19: + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 301 .loc 1 210 3 view .LVU91 + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 302 .loc 1 210 21 is_stmt 0 view .LVU92 + 303 00cc 2368 ldr r3, [r4] + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 304 .loc 1 210 5 view .LVU93 + 305 00ce 13F0040F tst r3, #4 + 306 00d2 06D0 beq .L20 + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 307 .loc 1 213 5 is_stmt 1 view .LVU94 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 308 .loc 1 216 5 view .LVU95 + 309 00d4 544A ldr r2, .L36 + 310 00d6 136B ldr r3, [r2, #48] + 311 00d8 23F44023 bic r3, r3, #786432 + 312 00dc 2169 ldr r1, [r4, #16] + 313 00de 0B43 orrs r3, r3, r1 + 314 00e0 1363 str r3, [r2, #48] + 315 .L20: + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 316 .loc 1 221 3 view .LVU96 + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 317 .loc 1 221 21 is_stmt 0 view .LVU97 + 318 00e2 2368 ldr r3, [r4] + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 319 .loc 1 221 5 view .LVU98 + 320 00e4 13F0200F tst r3, #32 + 321 00e8 06D0 beq .L21 + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 322 .loc 1 224 5 is_stmt 1 view .LVU99 + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 323 .loc 1 227 5 view .LVU100 + 324 00ea 4F4A ldr r2, .L36 + 325 00ec 136B ldr r3, [r2, #48] + 326 00ee 23F01003 bic r3, r3, #16 + 327 00f2 E169 ldr r1, [r4, #28] + 328 00f4 0B43 orrs r3, r3, r1 + 329 00f6 1363 str r3, [r2, #48] + 330 .L21: + ARM GAS /tmp/ccLRMPc2.s page 53 + + + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 331 .loc 1 235 3 view .LVU101 + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 332 .loc 1 235 21 is_stmt 0 view .LVU102 + 333 00f8 2368 ldr r3, [r4] + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 334 .loc 1 235 5 view .LVU103 + 335 00fa 13F4003F tst r3, #131072 + 336 00fe 06D0 beq .L22 + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 337 .loc 1 238 5 is_stmt 1 view .LVU104 + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 338 .loc 1 241 5 view .LVU105 + 339 0100 494A ldr r2, .L36 + 340 0102 5368 ldr r3, [r2, #4] + 341 0104 23F48003 bic r3, r3, #4194304 + 342 0108 216B ldr r1, [r4, #48] + 343 010a 0B43 orrs r3, r3, r1 + 344 010c 5360 str r3, [r2, #4] + 345 .L22: + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 346 .loc 1 255 3 view .LVU106 + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 347 .loc 1 255 21 is_stmt 0 view .LVU107 + 348 010e 2368 ldr r3, [r4] + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 349 .loc 1 255 5 view .LVU108 + 350 0110 13F0400F tst r3, #64 + 351 0114 06D0 beq .L23 + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 352 .loc 1 258 5 is_stmt 1 view .LVU109 + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 353 .loc 1 261 5 view .LVU110 + 354 0116 444A ldr r2, .L36 + 355 0118 136B ldr r3, [r2, #48] + 356 011a 23F02003 bic r3, r3, #32 + 357 011e 216A ldr r1, [r4, #32] + 358 0120 0B43 orrs r3, r3, r1 + 359 0122 1363 str r3, [r2, #48] + 360 .L23: + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 361 .loc 1 288 3 view .LVU111 + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 362 .loc 1 288 21 is_stmt 0 view .LVU112 + 363 0124 2368 ldr r3, [r4] + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 364 .loc 1 288 5 view .LVU113 + 365 0126 13F0080F tst r3, #8 + 366 012a 06D0 beq .L24 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 367 .loc 1 291 5 is_stmt 1 view .LVU114 + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 368 .loc 1 294 5 view .LVU115 + 369 012c 3E4A ldr r2, .L36 + 370 012e 136B ldr r3, [r2, #48] + 371 0130 23F44013 bic r3, r3, #3145728 + 372 0134 6169 ldr r1, [r4, #20] + ARM GAS /tmp/ccLRMPc2.s page 54 + + + 373 0136 0B43 orrs r3, r3, r1 + 374 0138 1363 str r3, [r2, #48] + 375 .L24: + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 376 .loc 1 298 3 view .LVU116 + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 377 .loc 1 298 21 is_stmt 0 view .LVU117 + 378 013a 2368 ldr r3, [r4] + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 379 .loc 1 298 5 view .LVU118 + 380 013c 13F0100F tst r3, #16 + 381 0140 06D0 beq .L25 + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 382 .loc 1 301 5 is_stmt 1 view .LVU119 + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 383 .loc 1 304 5 view .LVU120 + 384 0142 394A ldr r2, .L36 + 385 0144 136B ldr r3, [r2, #48] + 386 0146 23F44003 bic r3, r3, #12582912 + 387 014a A169 ldr r1, [r4, #24] + 388 014c 0B43 orrs r3, r3, r1 + 389 014e 1363 str r3, [r2, #48] + 390 .L25: + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 391 .loc 1 314 3 view .LVU121 + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 392 .loc 1 314 21 is_stmt 0 view .LVU122 + 393 0150 2368 ldr r3, [r4] + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 394 .loc 1 314 5 view .LVU123 + 395 0152 13F4007F tst r3, #512 + 396 0156 06D0 beq .L26 + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 397 .loc 1 317 5 is_stmt 1 view .LVU124 + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 398 .loc 1 320 5 view .LVU125 + 399 0158 334A ldr r2, .L36 + 400 015a 5368 ldr r3, [r2, #4] + 401 015c 23F40003 bic r3, r3, #8388608 + 402 0160 A16A ldr r1, [r4, #40] + 403 0162 0B43 orrs r3, r3, r1 + 404 0164 5360 str r3, [r2, #4] + 405 .L26: + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 406 .loc 1 346 3 view .LVU126 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 407 .loc 1 346 21 is_stmt 0 view .LVU127 + 408 0166 2368 ldr r3, [r4] + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 409 .loc 1 346 5 view .LVU128 + 410 0168 13F0800F tst r3, #128 + 411 016c 06D0 beq .L27 + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 412 .loc 1 349 5 is_stmt 1 view .LVU129 + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 413 .loc 1 352 5 view .LVU130 + 414 016e 2E4A ldr r2, .L36 + ARM GAS /tmp/ccLRMPc2.s page 55 + + + 415 0170 D36A ldr r3, [r2, #44] + 416 0172 23F4F873 bic r3, r3, #496 + 417 0176 616A ldr r1, [r4, #36] + 418 0178 0B43 orrs r3, r3, r1 + 419 017a D362 str r3, [r2, #44] + 420 .L27: + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 421 .loc 1 395 3 view .LVU131 + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 422 .loc 1 395 21 is_stmt 0 view .LVU132 + 423 017c 2368 ldr r3, [r4] + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 424 .loc 1 395 5 view .LVU133 + 425 017e 13F4805F tst r3, #4096 + 426 0182 4DD0 beq .L31 + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 427 .loc 1 398 5 is_stmt 1 view .LVU134 + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 428 .loc 1 401 5 view .LVU135 + 429 0184 284A ldr r2, .L36 + 430 0186 136B ldr r3, [r2, #48] + 431 0188 23F48073 bic r3, r3, #256 + 432 018c E16A ldr r1, [r4, #44] + 433 018e 0B43 orrs r3, r3, r1 + 434 0190 1363 str r3, [r2, #48] + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 435 .loc 1 564 10 is_stmt 0 view .LVU136 + 436 0192 0020 movs r0, #0 + 437 0194 45E0 b .L11 + 438 .LVL25: + 439 .L28: + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 440 .loc 1 111 20 view .LVU137 + 441 0196 0025 movs r5, #0 + 442 0198 4AE7 b .L8 + 443 .LVL26: + 444 .L33: + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 445 .loc 1 135 7 is_stmt 1 view .LVU138 + 446 019a 244A ldr r2, .L36+4 + 447 019c 1368 ldr r3, [r2] + 448 019e 43F48073 orr r3, r3, #256 + 449 01a2 1360 str r3, [r2] + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 450 .loc 1 138 7 view .LVU139 + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 451 .loc 1 138 19 is_stmt 0 view .LVU140 + 452 01a4 FFF7FEFF bl HAL_GetTick + 453 .LVL27: + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 454 .loc 1 138 19 view .LVU141 + 455 01a8 0646 mov r6, r0 + 456 .LVL28: + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 457 .loc 1 140 7 is_stmt 1 view .LVU142 + 458 .L10: + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccLRMPc2.s page 56 + + + 459 .loc 1 140 13 view .LVU143 + 460 01aa 204B ldr r3, .L36+4 + 461 01ac 1B68 ldr r3, [r3] + 462 01ae 13F4807F tst r3, #256 + 463 01b2 7FF443AF bne .L9 + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 464 .loc 1 142 11 view .LVU144 + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 465 .loc 1 142 15 is_stmt 0 view .LVU145 + 466 01b6 FFF7FEFF bl HAL_GetTick + 467 .LVL29: + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 468 .loc 1 142 29 view .LVU146 + 469 01ba 801B subs r0, r0, r6 + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 470 .loc 1 142 13 view .LVU147 + 471 01bc 6428 cmp r0, #100 + 472 01be F4D9 bls .L10 + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 473 .loc 1 144 18 view .LVU148 + 474 01c0 0320 movs r0, #3 + 475 01c2 2EE0 b .L11 + 476 .LVL30: + 477 .L34: + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 478 .loc 1 165 9 is_stmt 1 view .LVU149 + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 479 .loc 1 165 21 is_stmt 0 view .LVU150 + 480 01c4 FFF7FEFF bl HAL_GetTick + 481 .LVL31: + 482 01c8 0646 mov r6, r0 + 483 .LVL32: + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 484 .loc 1 168 9 is_stmt 1 view .LVU151 + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 485 .loc 1 168 14 is_stmt 0 view .LVU152 + 486 01ca 18E0 b .L14 + 487 .LVL33: + 488 .L15: + 489 .LBB22: + 490 .LBI22: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 491 .loc 2 981 31 is_stmt 1 view .LVU153 + 492 .LBB23: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 493 .loc 2 983 3 view .LVU154 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 494 .loc 2 988 4 view .LVU155 + 495 01cc 0223 movs r3, #2 + 496 .syntax unified + 497 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 498 01ce 93FAA3F3 rbit r3, r3 + 499 @ 0 "" 2 + 500 .LVL34: + 501 .loc 2 1001 3 view .LVU156 + 502 .loc 2 1001 3 is_stmt 0 view .LVU157 + 503 .thumb + ARM GAS /tmp/ccLRMPc2.s page 57 + + + 504 .syntax unified + 505 .LBE23: + 506 .LBE22: + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 507 .loc 1 168 15 view .LVU158 + 508 01d2 154B ldr r3, .L36 + 509 01d4 596A ldr r1, [r3, #36] + 510 .L16: + 511 .LVL35: + 512 .LBB24: + 513 .LBI24: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 514 .loc 2 981 31 is_stmt 1 discriminator 11 view .LVU159 + 515 .LBB25: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 516 .loc 2 983 3 discriminator 11 view .LVU160 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 517 .loc 2 988 4 discriminator 11 view .LVU161 + 518 01d6 0223 movs r3, #2 + 519 .syntax unified + 520 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 521 01d8 93FAA3F3 rbit r3, r3 + 522 @ 0 "" 2 + 523 .LVL36: + 524 .loc 2 1001 3 discriminator 11 view .LVU162 + 525 .loc 2 1001 3 is_stmt 0 discriminator 11 view .LVU163 + 526 .thumb + 527 .syntax unified + 528 .LBE25: + 529 .LBE24: + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 530 .loc 1 168 15 discriminator 11 view .LVU164 + 531 01dc B3FA83F3 clz r3, r3 + 532 01e0 03F01F03 and r3, r3, #31 + 533 01e4 0122 movs r2, #1 + 534 01e6 02FA03F3 lsl r3, r2, r3 + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 535 .loc 1 168 51 discriminator 11 view .LVU165 + 536 01ea 0B42 tst r3, r1 + 537 01ec 7FF44EAF bne .L13 + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 538 .loc 1 170 13 is_stmt 1 view .LVU166 + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 539 .loc 1 170 17 is_stmt 0 view .LVU167 + 540 01f0 FFF7FEFF bl HAL_GetTick + 541 .LVL37: + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 542 .loc 1 170 31 view .LVU168 + 543 01f4 801B subs r0, r0, r6 + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 544 .loc 1 170 15 view .LVU169 + 545 01f6 41F28833 movw r3, #5000 + 546 01fa 9842 cmp r0, r3 + 547 01fc 0ED8 bhi .L30 + 548 .L14: + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 549 .loc 1 168 51 is_stmt 1 view .LVU170 + ARM GAS /tmp/ccLRMPc2.s page 58 + + + 550 .LVL38: + 551 .LBB26: + 552 .LBI26: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 553 .loc 2 981 31 view .LVU171 + 554 .LBB27: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 555 .loc 2 983 3 view .LVU172 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 556 .loc 2 988 4 view .LVU173 + 557 01fe 0223 movs r3, #2 + 558 .syntax unified + 559 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 560 0200 93FAA3F2 rbit r2, r3 + 561 @ 0 "" 2 + 562 .LVL39: + 563 .loc 2 1001 3 view .LVU174 + 564 .loc 2 1001 3 is_stmt 0 view .LVU175 + 565 .thumb + 566 .syntax unified + 567 .LBE27: + 568 .LBE26: + 569 .LBB28: + 570 .LBI28: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571 .loc 2 981 31 is_stmt 1 view .LVU176 + 572 .LBB29: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 573 .loc 2 983 3 view .LVU177 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 574 .loc 2 988 4 view .LVU178 + 575 .syntax unified + 576 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 577 0204 93FAA3F3 rbit r3, r3 + 578 @ 0 "" 2 + 579 .LVL40: + 580 .loc 2 1001 3 view .LVU179 + 581 .loc 2 1001 3 is_stmt 0 view .LVU180 + 582 .thumb + 583 .syntax unified + 584 .LBE29: + 585 .LBE28: + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 586 .loc 1 168 15 view .LVU181 + 587 0208 002B cmp r3, #0 + 588 020a DFD0 beq .L15 + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 589 .loc 1 168 15 discriminator 4 view .LVU182 + 590 020c 064B ldr r3, .L36 + 591 020e 196A ldr r1, [r3, #32] + 592 0210 E1E7 b .L16 + 593 .LVL41: + 594 .L35: + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 595 .loc 1 182 7 is_stmt 1 view .LVU183 + 596 0212 D369 ldr r3, [r2, #28] + 597 0214 23F08053 bic r3, r3, #268435456 + ARM GAS /tmp/ccLRMPc2.s page 59 + + + 598 0218 D361 str r3, [r2, #28] + 599 021a 41E7 b .L7 + 600 .LVL42: + 601 .L30: + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 602 .loc 1 172 20 is_stmt 0 view .LVU184 + 603 021c 0320 movs r0, #3 + 604 021e 00E0 b .L11 + 605 .LVL43: + 606 .L31: + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 607 .loc 1 564 10 view .LVU185 + 608 0220 0020 movs r0, #0 + 609 .L11: + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 610 .loc 1 565 1 view .LVU186 + 611 0222 03B0 add sp, sp, #12 + 612 .cfi_def_cfa_offset 20 + 613 @ sp needed + 614 0224 F0BD pop {r4, r5, r6, r7, pc} + 615 .LVL44: + 616 .L37: + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 617 .loc 1 565 1 view .LVU187 + 618 0226 00BF .align 2 + 619 .L36: + 620 0228 00100240 .word 1073876992 + 621 022c 00700040 .word 1073770496 + 622 0230 00819010 .word 277905664 + 623 .cfi_endproc + 624 .LFE130: + 626 .section .text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits + 627 .align 1 + 628 .global HAL_RCCEx_GetPeriphCLKConfig + 629 .syntax unified + 630 .thumb + 631 .thumb_func + 633 HAL_RCCEx_GetPeriphCLKConfig: + 634 .LVL45: + 635 .LFB131: + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/ + 636 .loc 1 576 1 is_stmt 1 view -0 + 637 .cfi_startproc + 638 @ args = 0, pretend = 0, frame = 0 + 639 @ frame_needed = 0, uses_anonymous_args = 0 + 640 @ link register save eliminated. + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + 641 .loc 1 580 3 view .LVU189 + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + 642 .loc 1 580 39 is_stmt 0 view .LVU190 + 643 0000 1F4B ldr r3, .L39 + 644 0002 0360 str r3, [r0] + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART1 clock configuration --------------------------------------------*/ + 645 .loc 1 588 3 is_stmt 1 view .LVU191 + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART1 clock configuration --------------------------------------------*/ + 646 .loc 1 588 38 is_stmt 0 view .LVU192 + 647 0004 1F4B ldr r3, .L39+4 + ARM GAS /tmp/ccLRMPc2.s page 60 + + + 648 0006 1A6A ldr r2, [r3, #32] + 649 0008 02F44072 and r2, r2, #768 + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART1 clock configuration --------------------------------------------*/ + 650 .loc 1 588 36 view .LVU193 + 651 000c 4260 str r2, [r0, #4] + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) + 652 .loc 1 590 3 is_stmt 1 view .LVU194 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) + 653 .loc 1 590 41 is_stmt 0 view .LVU195 + 654 000e 1A6B ldr r2, [r3, #48] + 655 0010 02F00302 and r2, r2, #3 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) + 656 .loc 1 590 39 view .LVU196 + 657 0014 8260 str r2, [r0, #8] + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ + 658 .loc 1 593 3 is_stmt 1 view .LVU197 + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ + 659 .loc 1 593 41 is_stmt 0 view .LVU198 + 660 0016 1A6B ldr r2, [r3, #48] + 661 0018 02F44032 and r2, r2, #196608 + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ + 662 .loc 1 593 39 view .LVU199 + 663 001c C260 str r2, [r0, #12] + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ + 664 .loc 1 597 3 is_stmt 1 view .LVU200 + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ + 665 .loc 1 597 41 is_stmt 0 view .LVU201 + 666 001e 1A6B ldr r2, [r3, #48] + 667 0020 02F44022 and r2, r2, #786432 + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ + 668 .loc 1 597 39 view .LVU202 + 669 0024 0261 str r2, [r0, #16] + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 670 .loc 1 600 3 is_stmt 1 view .LVU203 + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 671 .loc 1 600 39 is_stmt 0 view .LVU204 + 672 0026 1A6B ldr r2, [r3, #48] + 673 0028 02F01002 and r2, r2, #16 + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 674 .loc 1 600 37 view .LVU205 + 675 002c C261 str r2, [r0, #28] + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USB clock configuration -----------------------------------------*/ + 676 .loc 1 607 3 is_stmt 1 view .LVU206 + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USB clock configuration -----------------------------------------*/ + 677 .loc 1 607 39 is_stmt 0 view .LVU207 + 678 002e 164A ldr r2, .L39+8 + 679 0030 0260 str r2, [r0] + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 680 .loc 1 609 3 is_stmt 1 view .LVU208 + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 681 .loc 1 609 38 is_stmt 0 view .LVU209 + 682 0032 5A68 ldr r2, [r3, #4] + 683 0034 02F48002 and r2, r2, #4194304 + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 684 .loc 1 609 36 view .LVU210 + 685 0038 0263 str r2, [r0, #48] + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2C2 clock configuration -----------------------------------------*/ + ARM GAS /tmp/ccLRMPc2.s page 61 + + + 686 .loc 1 621 3 is_stmt 1 view .LVU211 + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2C2 clock configuration -----------------------------------------*/ + 687 .loc 1 621 39 is_stmt 0 view .LVU212 + 688 003a 144A ldr r2, .L39+12 + 689 003c 0260 str r2, [r0] + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 690 .loc 1 623 3 is_stmt 1 view .LVU213 + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 691 .loc 1 623 39 is_stmt 0 view .LVU214 + 692 003e 1A6B ldr r2, [r3, #48] + 693 0040 02F02002 and r2, r2, #32 + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 694 .loc 1 623 37 view .LVU215 + 695 0044 0262 str r2, [r0, #32] + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART4 clock configuration -----------------------------------------*/ + 696 .loc 1 643 3 is_stmt 1 view .LVU216 + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART4 clock configuration -----------------------------------------*/ + 697 .loc 1 643 39 is_stmt 0 view .LVU217 + 698 0046 124A ldr r2, .L39+16 + 699 0048 0260 str r2, [r0] + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART5 clock configuration -----------------------------------------*/ + 700 .loc 1 645 3 is_stmt 1 view .LVU218 + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART5 clock configuration -----------------------------------------*/ + 701 .loc 1 645 40 is_stmt 0 view .LVU219 + 702 004a 1A6B ldr r2, [r3, #48] + 703 004c 02F44012 and r2, r2, #3145728 + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART5 clock configuration -----------------------------------------*/ + 704 .loc 1 645 38 view .LVU220 + 705 0050 4261 str r2, [r0, #20] + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 706 .loc 1 647 3 is_stmt 1 view .LVU221 + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 707 .loc 1 647 40 is_stmt 0 view .LVU222 + 708 0052 1A6B ldr r2, [r3, #48] + 709 0054 02F44002 and r2, r2, #12582912 + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 710 .loc 1 647 38 view .LVU223 + 711 0058 8261 str r2, [r0, #24] + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2S clock configuration -----------------------------------------*/ + 712 .loc 1 656 3 is_stmt 1 view .LVU224 + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2S clock configuration -----------------------------------------*/ + 713 .loc 1 656 39 is_stmt 0 view .LVU225 + 714 005a 0E4A ldr r2, .L39+20 + 715 005c 0260 str r2, [r0] + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 716 .loc 1 658 3 is_stmt 1 view .LVU226 + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 717 .loc 1 658 38 is_stmt 0 view .LVU227 + 718 005e 5A68 ldr r2, [r3, #4] + 719 0060 02F40002 and r2, r2, #8388608 + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 720 .loc 1 658 36 view .LVU228 + 721 0064 8262 str r2, [r0, #40] + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/ + 722 .loc 1 678 3 is_stmt 1 view .LVU229 + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/ + 723 .loc 1 678 39 is_stmt 0 view .LVU230 + ARM GAS /tmp/ccLRMPc2.s page 62 + + + 724 0066 0C4A ldr r2, .L39+24 + 725 0068 0260 str r2, [r0] + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 726 .loc 1 680 3 is_stmt 1 view .LVU231 + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 727 .loc 1 680 40 is_stmt 0 view .LVU232 + 728 006a DA6A ldr r2, [r3, #44] + 729 006c 02F4F872 and r2, r2, #496 + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 730 .loc 1 680 38 view .LVU233 + 731 0070 4262 str r2, [r0, #36] + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM1 clock configuration -----------------------------------------*/ + 732 .loc 1 701 3 is_stmt 1 view .LVU234 + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM1 clock configuration -----------------------------------------*/ + 733 .loc 1 701 39 is_stmt 0 view .LVU235 + 734 0072 0A4A ldr r2, .L39+28 + 735 0074 0260 str r2, [r0] + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 736 .loc 1 703 3 is_stmt 1 view .LVU236 + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 737 .loc 1 703 39 is_stmt 0 view .LVU237 + 738 0076 1B6B ldr r3, [r3, #48] + 739 0078 03F48073 and r3, r3, #256 + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 740 .loc 1 703 37 view .LVU238 + 741 007c C362 str r3, [r0, #44] + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 742 .loc 1 781 1 view .LVU239 + 743 007e 7047 bx lr + 744 .L40: + 745 .align 2 + 746 .L39: + 747 0080 27000100 .word 65575 + 748 0084 00100240 .word 1073876992 + 749 0088 27000300 .word 196647 + 750 008c 67000300 .word 196711 + 751 0090 7F000300 .word 196735 + 752 0094 7F020300 .word 197247 + 753 0098 FF020300 .word 197375 + 754 009c FF120300 .word 201471 + 755 .cfi_endproc + 756 .LFE131: + 758 .section .text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits + 759 .align 1 + 760 .global HAL_RCCEx_GetPeriphCLKFreq + 761 .syntax unified + 762 .thumb + 763 .thumb_func + 765 HAL_RCCEx_GetPeriphCLKFreq: + 766 .LVL46: + 767 .LFB132: + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* frequency == 0 : means that no available frequency for the peripheral */ + 768 .loc 1 947 1 is_stmt 1 view -0 + 769 .cfi_startproc + 770 @ args = 0, pretend = 0, frame = 32 + 771 @ frame_needed = 0, uses_anonymous_args = 0 + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* frequency == 0 : means that no available frequency for the peripheral */ + ARM GAS /tmp/ccLRMPc2.s page 63 + + + 772 .loc 1 947 1 is_stmt 0 view .LVU241 + 773 0000 30B5 push {r4, r5, lr} + 774 .cfi_def_cfa_offset 12 + 775 .cfi_offset 4, -12 + 776 .cfi_offset 5, -8 + 777 .cfi_offset 14, -4 + 778 0002 89B0 sub sp, sp, #36 + 779 .cfi_def_cfa_offset 48 + 780 0004 0446 mov r4, r0 + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 781 .loc 1 949 3 is_stmt 1 view .LVU242 + 782 .LVL47: + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) + 783 .loc 1 951 3 view .LVU243 + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ + 784 .loc 1 953 3 view .LVU244 + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ + 785 .loc 1 953 12 is_stmt 0 view .LVU245 + 786 0006 EC46 mov ip, sp + 787 0008 9B4D ldr r5, .L131 + 788 000a 0FCD ldmia r5!, {r0, r1, r2, r3} + 789 .LVL48: + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ + 790 .loc 1 953 12 view .LVU246 + 791 000c ACE80F00 stmia ip!, {r0, r1, r2, r3} + 792 0010 95E80F00 ldm r5, {r0, r1, r2, r3} + 793 0014 8CE80F00 stm ip, {r0, r1, r2, r3} + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 794 .loc 1 960 3 is_stmt 1 view .LVU247 + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 795 .loc 1 962 3 view .LVU248 + 796 0018 402C cmp r4, #64 + 797 001a 00F05B81 beq .L42 + 798 001e 2BD8 bhi .L43 + 799 0020 202C cmp r4, #32 + 800 0022 00F2A081 bhi .L80 + 801 0026 002C cmp r4, #0 + 802 0028 00F09F81 beq .L81 + 803 002c 013C subs r4, r4, #1 + 804 .LVL49: + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 805 .loc 1 962 3 is_stmt 0 view .LVU249 + 806 002e 1F2C cmp r4, #31 + 807 0030 00F29D81 bhi .L82 + 808 0034 DFE814F0 tbh [pc, r4, lsl #1] + 809 .L46: + 810 0038 7200 .2byte (.L51-.L46)/2 + 811 003a 9500 .2byte (.L50-.L46)/2 + 812 003c 9B01 .2byte (.L82-.L46)/2 + 813 003e BE00 .2byte (.L49-.L46)/2 + 814 0040 9B01 .2byte (.L82-.L46)/2 + 815 0042 9B01 .2byte (.L82-.L46)/2 + 816 0044 9B01 .2byte (.L82-.L46)/2 + 817 0046 E700 .2byte (.L48-.L46)/2 + 818 0048 9B01 .2byte (.L82-.L46)/2 + 819 004a 9B01 .2byte (.L82-.L46)/2 + 820 004c 9B01 .2byte (.L82-.L46)/2 + ARM GAS /tmp/ccLRMPc2.s page 64 + + + 821 004e 9B01 .2byte (.L82-.L46)/2 + 822 0050 9B01 .2byte (.L82-.L46)/2 + 823 0052 9B01 .2byte (.L82-.L46)/2 + 824 0054 9B01 .2byte (.L82-.L46)/2 + 825 0056 0D01 .2byte (.L47-.L46)/2 + 826 0058 9B01 .2byte (.L82-.L46)/2 + 827 005a 9B01 .2byte (.L82-.L46)/2 + 828 005c 9B01 .2byte (.L82-.L46)/2 + 829 005e 9B01 .2byte (.L82-.L46)/2 + 830 0060 9B01 .2byte (.L82-.L46)/2 + 831 0062 9B01 .2byte (.L82-.L46)/2 + 832 0064 9B01 .2byte (.L82-.L46)/2 + 833 0066 9B01 .2byte (.L82-.L46)/2 + 834 0068 9B01 .2byte (.L82-.L46)/2 + 835 006a 9B01 .2byte (.L82-.L46)/2 + 836 006c 9B01 .2byte (.L82-.L46)/2 + 837 006e 9B01 .2byte (.L82-.L46)/2 + 838 0070 9B01 .2byte (.L82-.L46)/2 + 839 0072 9B01 .2byte (.L82-.L46)/2 + 840 0074 9B01 .2byte (.L82-.L46)/2 + 841 0076 3F01 .2byte (.L45-.L46)/2 + 842 .LVL50: + 843 .p2align 1 + 844 .L43: + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 845 .loc 1 962 3 view .LVU250 + 846 0078 B4F5805F cmp r4, #4096 + 847 007c 00F06381 beq .L52 + 848 0080 13D9 bls .L104 + 849 0082 B4F5803F cmp r4, #65536 + 850 0086 22D0 beq .L56 + 851 0088 B4F5003F cmp r4, #131072 + 852 008c 1DD1 bne .L105 +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 853 .loc 1 1215 7 is_stmt 1 view .LVU251 +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 854 .loc 1 1215 11 is_stmt 0 view .LVU252 + 855 008e 7B4B ldr r3, .L131+4 + 856 0090 1868 ldr r0, [r3] +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 857 .loc 1 1215 10 view .LVU253 + 858 0092 10F00070 ands r0, r0, #33554432 + 859 0096 00F06B81 beq .L41 +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 860 .loc 1 1218 9 is_stmt 1 view .LVU254 +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 861 .loc 1 1218 18 is_stmt 0 view .LVU255 + 862 009a 5B68 ldr r3, [r3, #4] + 863 .LVL51: +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 864 .loc 1 1221 9 is_stmt 1 view .LVU256 +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 865 .loc 1 1221 12 is_stmt 0 view .LVU257 + 866 009c 13F4800F tst r3, #4194304 + 867 00a0 00F02A81 beq .L77 +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 868 .loc 1 1223 11 is_stmt 1 view .LVU258 + ARM GAS /tmp/ccLRMPc2.s page 65 + + +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 869 .loc 1 1223 23 is_stmt 0 view .LVU259 + 870 00a4 FFF7FEFF bl RCC_GetPLLCLKFreq + 871 .LVL52: +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 872 .loc 1 1223 23 view .LVU260 + 873 00a8 62E1 b .L41 + 874 .LVL53: + 875 .L104: + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 876 .loc 1 962 3 view .LVU261 + 877 00aa 802C cmp r4, #128 + 878 00ac 00F02A81 beq .L54 + 879 00b0 B4F5007F cmp r4, #512 + 880 00b4 07D1 bne .L106 +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 881 .loc 1 1195 7 is_stmt 1 view .LVU262 +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 882 .loc 1 1195 16 is_stmt 0 view .LVU263 + 883 00b6 714B ldr r3, .L131+4 + 884 00b8 5B68 ldr r3, [r3, #4] + 885 .LVL54: +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 886 .loc 1 1198 7 is_stmt 1 view .LVU264 +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 887 .loc 1 1198 10 is_stmt 0 view .LVU265 + 888 00ba 13F4000F tst r3, #8388608 + 889 00be 00F01881 beq .L107 +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 890 .loc 1 1201 19 view .LVU266 + 891 00c2 6F48 ldr r0, .L131+8 + 892 .LVL55: +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 893 .loc 1 1513 3 is_stmt 1 view .LVU267 +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 894 .loc 1 1513 9 is_stmt 0 view .LVU268 + 895 00c4 54E1 b .L41 + 896 .LVL56: + 897 .L106: + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 898 .loc 1 962 3 view .LVU269 + 899 00c6 0020 movs r0, #0 + 900 00c8 52E1 b .L41 + 901 .L105: + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 902 .loc 1 962 3 view .LVU270 + 903 00ca 0020 movs r0, #0 + 904 00cc 50E1 b .L41 + 905 .L56: + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 906 .loc 1 967 7 is_stmt 1 view .LVU271 + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 907 .loc 1 967 16 is_stmt 0 view .LVU272 + 908 00ce 6B4B ldr r3, .L131+4 + 909 00d0 1B6A ldr r3, [r3, #32] + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 910 .loc 1 967 14 view .LVU273 + ARM GAS /tmp/ccLRMPc2.s page 66 + + + 911 00d2 03F44073 and r3, r3, #768 + 912 .LVL57: + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 913 .loc 1 970 7 is_stmt 1 view .LVU274 + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 914 .loc 1 970 10 is_stmt 0 view .LVU275 + 915 00d6 B3F5807F cmp r3, #256 + 916 00da 07D0 beq .L108 + 917 .L58: + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 918 .loc 1 975 12 is_stmt 1 view .LVU276 + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 919 .loc 1 975 15 is_stmt 0 view .LVU277 + 920 00dc B3F5007F cmp r3, #512 + 921 00e0 0CD0 beq .L109 + 922 .L59: + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 923 .loc 1 980 12 is_stmt 1 view .LVU278 + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 924 .loc 1 980 15 is_stmt 0 view .LVU279 + 925 00e2 B3F5407F cmp r3, #768 + 926 00e6 11D0 beq .L110 + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 927 .loc 1 949 12 view .LVU280 + 928 00e8 0020 movs r0, #0 + 929 00ea 41E1 b .L41 + 930 .L108: + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 931 .loc 1 970 48 discriminator 1 view .LVU281 + 932 00ec 634A ldr r2, .L131+4 + 933 00ee 126A ldr r2, [r2, #32] + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 934 .loc 1 970 44 discriminator 1 view .LVU282 + 935 00f0 12F0020F tst r2, #2 + 936 00f4 F2D0 beq .L58 + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 937 .loc 1 972 19 view .LVU283 + 938 00f6 4FF40040 mov r0, #32768 + 939 00fa 39E1 b .L41 + 940 .L109: + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 941 .loc 1 975 53 discriminator 1 view .LVU284 + 942 00fc 5F4A ldr r2, .L131+4 + 943 00fe 526A ldr r2, [r2, #36] + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 944 .loc 1 975 49 discriminator 1 view .LVU285 + 945 0100 12F0020F tst r2, #2 + 946 0104 EDD0 beq .L59 + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 947 .loc 1 977 19 view .LVU286 + 948 0106 49F64040 movw r0, #40000 + 949 010a 31E1 b .L41 + 950 .L110: + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 951 .loc 1 980 59 discriminator 1 view .LVU287 + 952 010c 5B4B ldr r3, .L131+4 + 953 .LVL58: + ARM GAS /tmp/ccLRMPc2.s page 67 + + + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 954 .loc 1 980 59 discriminator 1 view .LVU288 + 955 010e 1868 ldr r0, [r3] + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 956 .loc 1 980 55 discriminator 1 view .LVU289 + 957 0110 10F40030 ands r0, r0, #131072 + 958 0114 00F02C81 beq .L41 + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 959 .loc 1 982 19 view .LVU290 + 960 0118 5A48 ldr r0, .L131+12 + 961 011a 29E1 b .L41 + 962 .LVL59: + 963 .L51: + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 964 .loc 1 989 7 is_stmt 1 view .LVU291 + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 965 .loc 1 989 16 is_stmt 0 view .LVU292 + 966 011c 574B ldr r3, .L131+4 + 967 011e 1B6B ldr r3, [r3, #48] + 968 .LVL60: + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 969 .loc 1 993 7 is_stmt 1 view .LVU293 + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 970 .loc 1 993 10 is_stmt 0 view .LVU294 + 971 0120 13F00303 ands r3, r3, #3 + 972 .LVL61: + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 973 .loc 1 993 10 view .LVU295 + 974 0124 07D0 beq .L111 +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 975 .loc 1 1004 12 is_stmt 1 view .LVU296 +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 976 .loc 1 1004 15 is_stmt 0 view .LVU297 + 977 0126 032B cmp r3, #3 + 978 0128 08D0 beq .L112 + 979 .L61: +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 980 .loc 1 1009 12 is_stmt 1 view .LVU298 +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 981 .loc 1 1009 15 is_stmt 0 view .LVU299 + 982 012a 012B cmp r3, #1 + 983 012c 0DD0 beq .L113 +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 984 .loc 1 1014 12 is_stmt 1 view .LVU300 +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 985 .loc 1 1014 15 is_stmt 0 view .LVU301 + 986 012e 022B cmp r3, #2 + 987 0130 0ED0 beq .L114 + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 988 .loc 1 949 12 view .LVU302 + 989 0132 0020 movs r0, #0 + 990 0134 1CE1 b .L41 + 991 .L111: + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 992 .loc 1 995 9 is_stmt 1 view .LVU303 + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 993 .loc 1 995 21 is_stmt 0 view .LVU304 + ARM GAS /tmp/ccLRMPc2.s page 68 + + + 994 0136 FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 995 .LVL62: + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 996 .loc 1 995 21 view .LVU305 + 997 013a 19E1 b .L41 + 998 .LVL63: + 999 .L112: +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1000 .loc 1 1004 56 discriminator 1 view .LVU306 + 1001 013c 4F4A ldr r2, .L131+4 + 1002 013e 1268 ldr r2, [r2] +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1003 .loc 1 1004 52 discriminator 1 view .LVU307 + 1004 0140 12F0020F tst r2, #2 + 1005 0144 F1D0 beq .L61 +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1006 .loc 1 1006 19 view .LVU308 + 1007 0146 5048 ldr r0, .L131+16 + 1008 0148 12E1 b .L41 + 1009 .L113: +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1010 .loc 1 1011 9 is_stmt 1 view .LVU309 +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1011 .loc 1 1011 21 is_stmt 0 view .LVU310 + 1012 014a FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1013 .LVL64: +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1014 .loc 1 1011 21 view .LVU311 + 1015 014e 0FE1 b .L41 + 1016 .LVL65: + 1017 .L114: +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1018 .loc 1 1014 56 discriminator 1 view .LVU312 + 1019 0150 4A4B ldr r3, .L131+4 + 1020 .LVL66: +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1021 .loc 1 1014 56 discriminator 1 view .LVU313 + 1022 0152 186A ldr r0, [r3, #32] +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1023 .loc 1 1014 52 discriminator 1 view .LVU314 + 1024 0154 10F00200 ands r0, r0, #2 + 1025 0158 00F00A81 beq .L41 +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1026 .loc 1 1016 19 view .LVU315 + 1027 015c 4FF40040 mov r0, #32768 + 1028 0160 06E1 b .L41 + 1029 .LVL67: + 1030 .L50: +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1031 .loc 1 1024 7 is_stmt 1 view .LVU316 +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1032 .loc 1 1024 16 is_stmt 0 view .LVU317 + 1033 0162 464B ldr r3, .L131+4 + 1034 0164 1B6B ldr r3, [r3, #48] + 1035 .LVL68: +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1036 .loc 1 1027 7 is_stmt 1 view .LVU318 + ARM GAS /tmp/ccLRMPc2.s page 69 + + +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1037 .loc 1 1027 10 is_stmt 0 view .LVU319 + 1038 0166 13F44033 ands r3, r3, #196608 + 1039 .LVL69: +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1040 .loc 1 1027 10 view .LVU320 + 1041 016a 0AD0 beq .L115 +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1042 .loc 1 1032 12 is_stmt 1 view .LVU321 +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1043 .loc 1 1032 15 is_stmt 0 view .LVU322 + 1044 016c B3F5403F cmp r3, #196608 + 1045 0170 0AD0 beq .L116 + 1046 .L64: +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1047 .loc 1 1037 12 is_stmt 1 view .LVU323 +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1048 .loc 1 1037 15 is_stmt 0 view .LVU324 + 1049 0172 B3F5803F cmp r3, #65536 + 1050 0176 0ED0 beq .L117 +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1051 .loc 1 1042 12 is_stmt 1 view .LVU325 +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1052 .loc 1 1042 15 is_stmt 0 view .LVU326 + 1053 0178 B3F5003F cmp r3, #131072 + 1054 017c 0ED0 beq .L118 + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1055 .loc 1 949 12 view .LVU327 + 1056 017e 0020 movs r0, #0 + 1057 0180 F6E0 b .L41 + 1058 .L115: +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1059 .loc 1 1029 9 is_stmt 1 view .LVU328 +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1060 .loc 1 1029 21 is_stmt 0 view .LVU329 + 1061 0182 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1062 .LVL70: +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1063 .loc 1 1029 21 view .LVU330 + 1064 0186 F3E0 b .L41 + 1065 .LVL71: + 1066 .L116: +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1067 .loc 1 1032 56 discriminator 1 view .LVU331 + 1068 0188 3C4A ldr r2, .L131+4 + 1069 018a 1268 ldr r2, [r2] +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1070 .loc 1 1032 52 discriminator 1 view .LVU332 + 1071 018c 12F0020F tst r2, #2 + 1072 0190 EFD0 beq .L64 +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1073 .loc 1 1034 19 view .LVU333 + 1074 0192 3D48 ldr r0, .L131+16 + 1075 0194 ECE0 b .L41 + 1076 .L117: +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1077 .loc 1 1039 9 is_stmt 1 view .LVU334 + ARM GAS /tmp/ccLRMPc2.s page 70 + + +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1078 .loc 1 1039 21 is_stmt 0 view .LVU335 + 1079 0196 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1080 .LVL72: +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1081 .loc 1 1039 21 view .LVU336 + 1082 019a E9E0 b .L41 + 1083 .LVL73: + 1084 .L118: +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1085 .loc 1 1042 56 discriminator 1 view .LVU337 + 1086 019c 03F18043 add r3, r3, #1073741824 + 1087 .LVL74: +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1088 .loc 1 1042 56 discriminator 1 view .LVU338 + 1089 01a0 03F58053 add r3, r3, #4096 + 1090 .LVL75: +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1091 .loc 1 1042 56 discriminator 1 view .LVU339 + 1092 01a4 186A ldr r0, [r3, #32] +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1093 .loc 1 1042 52 discriminator 1 view .LVU340 + 1094 01a6 10F00200 ands r0, r0, #2 + 1095 01aa 00F0E180 beq .L41 +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1096 .loc 1 1044 19 view .LVU341 + 1097 01ae 4FF40040 mov r0, #32768 + 1098 01b2 DDE0 b .L41 + 1099 .LVL76: + 1100 .L49: +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1101 .loc 1 1053 7 is_stmt 1 view .LVU342 +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1102 .loc 1 1053 16 is_stmt 0 view .LVU343 + 1103 01b4 314B ldr r3, .L131+4 + 1104 01b6 1B6B ldr r3, [r3, #48] + 1105 .LVL77: +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1106 .loc 1 1056 7 is_stmt 1 view .LVU344 +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1107 .loc 1 1056 10 is_stmt 0 view .LVU345 + 1108 01b8 13F44023 ands r3, r3, #786432 + 1109 .LVL78: +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1110 .loc 1 1056 10 view .LVU346 + 1111 01bc 0AD0 beq .L119 +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1112 .loc 1 1061 12 is_stmt 1 view .LVU347 +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1113 .loc 1 1061 15 is_stmt 0 view .LVU348 + 1114 01be B3F5402F cmp r3, #786432 + 1115 01c2 0AD0 beq .L120 + 1116 .L67: +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1117 .loc 1 1066 12 is_stmt 1 view .LVU349 +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1118 .loc 1 1066 15 is_stmt 0 view .LVU350 + ARM GAS /tmp/ccLRMPc2.s page 71 + + + 1119 01c4 B3F5802F cmp r3, #262144 + 1120 01c8 0ED0 beq .L121 +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1121 .loc 1 1071 12 is_stmt 1 view .LVU351 +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1122 .loc 1 1071 15 is_stmt 0 view .LVU352 + 1123 01ca B3F5002F cmp r3, #524288 + 1124 01ce 0ED0 beq .L122 + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1125 .loc 1 949 12 view .LVU353 + 1126 01d0 0020 movs r0, #0 + 1127 01d2 CDE0 b .L41 + 1128 .L119: +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1129 .loc 1 1058 9 is_stmt 1 view .LVU354 +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1130 .loc 1 1058 21 is_stmt 0 view .LVU355 + 1131 01d4 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1132 .LVL79: +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1133 .loc 1 1058 21 view .LVU356 + 1134 01d8 CAE0 b .L41 + 1135 .LVL80: + 1136 .L120: +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1137 .loc 1 1061 56 discriminator 1 view .LVU357 + 1138 01da 284A ldr r2, .L131+4 + 1139 01dc 1268 ldr r2, [r2] +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1140 .loc 1 1061 52 discriminator 1 view .LVU358 + 1141 01de 12F0020F tst r2, #2 + 1142 01e2 EFD0 beq .L67 +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1143 .loc 1 1063 19 view .LVU359 + 1144 01e4 2848 ldr r0, .L131+16 + 1145 01e6 C3E0 b .L41 + 1146 .L121: +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1147 .loc 1 1068 9 is_stmt 1 view .LVU360 +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1148 .loc 1 1068 21 is_stmt 0 view .LVU361 + 1149 01e8 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1150 .LVL81: +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1151 .loc 1 1068 21 view .LVU362 + 1152 01ec C0E0 b .L41 + 1153 .LVL82: + 1154 .L122: +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1155 .loc 1 1071 56 discriminator 1 view .LVU363 + 1156 01ee 03F18043 add r3, r3, #1073741824 + 1157 .LVL83: +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1158 .loc 1 1071 56 discriminator 1 view .LVU364 + 1159 01f2 A3F5BE23 sub r3, r3, #389120 + 1160 .LVL84: +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccLRMPc2.s page 72 + + + 1161 .loc 1 1071 56 discriminator 1 view .LVU365 + 1162 01f6 186A ldr r0, [r3, #32] +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1163 .loc 1 1071 52 discriminator 1 view .LVU366 + 1164 01f8 10F00200 ands r0, r0, #2 + 1165 01fc 00F0B880 beq .L41 +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1166 .loc 1 1073 19 view .LVU367 + 1167 0200 4FF40040 mov r0, #32768 + 1168 0204 B4E0 b .L41 + 1169 .LVL85: + 1170 .L48: +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1171 .loc 1 1082 7 is_stmt 1 view .LVU368 +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1172 .loc 1 1082 16 is_stmt 0 view .LVU369 + 1173 0206 1D4B ldr r3, .L131+4 + 1174 0208 1B6B ldr r3, [r3, #48] + 1175 .LVL86: +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1176 .loc 1 1085 7 is_stmt 1 view .LVU370 +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1177 .loc 1 1085 10 is_stmt 0 view .LVU371 + 1178 020a 13F44013 ands r3, r3, #3145728 + 1179 .LVL87: +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1180 .loc 1 1085 10 view .LVU372 + 1181 020e 0AD0 beq .L123 +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1182 .loc 1 1090 12 is_stmt 1 view .LVU373 +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1183 .loc 1 1090 15 is_stmt 0 view .LVU374 + 1184 0210 B3F5401F cmp r3, #3145728 + 1185 0214 0AD0 beq .L124 + 1186 .L70: +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1187 .loc 1 1095 12 is_stmt 1 view .LVU375 +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1188 .loc 1 1095 15 is_stmt 0 view .LVU376 + 1189 0216 B3F5801F cmp r3, #1048576 + 1190 021a 0ED0 beq .L125 +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1191 .loc 1 1100 12 is_stmt 1 view .LVU377 +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1192 .loc 1 1100 15 is_stmt 0 view .LVU378 + 1193 021c B3F5001F cmp r3, #2097152 + 1194 0220 0ED0 beq .L126 + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1195 .loc 1 949 12 view .LVU379 + 1196 0222 0020 movs r0, #0 + 1197 0224 A4E0 b .L41 + 1198 .L123: +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1199 .loc 1 1087 9 is_stmt 1 view .LVU380 +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1200 .loc 1 1087 21 is_stmt 0 view .LVU381 + 1201 0226 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + ARM GAS /tmp/ccLRMPc2.s page 73 + + + 1202 .LVL88: +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1203 .loc 1 1087 21 view .LVU382 + 1204 022a A1E0 b .L41 + 1205 .LVL89: + 1206 .L124: +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1207 .loc 1 1090 55 discriminator 1 view .LVU383 + 1208 022c 134A ldr r2, .L131+4 + 1209 022e 1268 ldr r2, [r2] +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1210 .loc 1 1090 51 discriminator 1 view .LVU384 + 1211 0230 12F0020F tst r2, #2 + 1212 0234 EFD0 beq .L70 +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1213 .loc 1 1092 19 view .LVU385 + 1214 0236 1448 ldr r0, .L131+16 + 1215 0238 9AE0 b .L41 + 1216 .L125: +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1217 .loc 1 1097 9 is_stmt 1 view .LVU386 +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1218 .loc 1 1097 21 is_stmt 0 view .LVU387 + 1219 023a FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1220 .LVL90: +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1221 .loc 1 1097 21 view .LVU388 + 1222 023e 97E0 b .L41 + 1223 .LVL91: + 1224 .L126: +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1225 .loc 1 1100 55 discriminator 1 view .LVU389 + 1226 0240 0E4B ldr r3, .L131+4 + 1227 .LVL92: +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1228 .loc 1 1100 55 discriminator 1 view .LVU390 + 1229 0242 186A ldr r0, [r3, #32] +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1230 .loc 1 1100 51 discriminator 1 view .LVU391 + 1231 0244 10F00200 ands r0, r0, #2 + 1232 0248 00F09280 beq .L41 +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1233 .loc 1 1102 19 view .LVU392 + 1234 024c 4FF40040 mov r0, #32768 + 1235 0250 8EE0 b .L41 + 1236 .LVL93: + 1237 .L47: +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1238 .loc 1 1111 7 is_stmt 1 view .LVU393 +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1239 .loc 1 1111 16 is_stmt 0 view .LVU394 + 1240 0252 0A4B ldr r3, .L131+4 + 1241 0254 1B6B ldr r3, [r3, #48] + 1242 .LVL94: +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1243 .loc 1 1114 7 is_stmt 1 view .LVU395 +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccLRMPc2.s page 74 + + + 1244 .loc 1 1114 10 is_stmt 0 view .LVU396 + 1245 0256 13F44003 ands r3, r3, #12582912 + 1246 .LVL95: +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1247 .loc 1 1114 10 view .LVU397 + 1248 025a 0AD0 beq .L127 +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1249 .loc 1 1119 12 is_stmt 1 view .LVU398 +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1250 .loc 1 1119 15 is_stmt 0 view .LVU399 + 1251 025c B3F5400F cmp r3, #12582912 + 1252 0260 14D0 beq .L128 + 1253 .L73: +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1254 .loc 1 1124 12 is_stmt 1 view .LVU400 +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1255 .loc 1 1124 15 is_stmt 0 view .LVU401 + 1256 0262 B3F5800F cmp r3, #4194304 + 1257 0266 18D0 beq .L129 +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1258 .loc 1 1129 12 is_stmt 1 view .LVU402 +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1259 .loc 1 1129 15 is_stmt 0 view .LVU403 + 1260 0268 B3F5000F cmp r3, #8388608 + 1261 026c 18D0 beq .L130 + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1262 .loc 1 949 12 view .LVU404 + 1263 026e 0020 movs r0, #0 + 1264 0270 7EE0 b .L41 + 1265 .L127: +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1266 .loc 1 1116 9 is_stmt 1 view .LVU405 +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1267 .loc 1 1116 21 is_stmt 0 view .LVU406 + 1268 0272 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1269 .LVL96: +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1270 .loc 1 1116 21 view .LVU407 + 1271 0276 7BE0 b .L41 + 1272 .L132: + 1273 .align 2 + 1274 .L131: + 1275 0278 00000000 .word .LANCHOR0 + 1276 027c 00100240 .word 1073876992 + 1277 0280 ADDEADDE .word -559030611 + 1278 0284 20A10700 .word 500000 + 1279 0288 00127A00 .word 8000000 + 1280 .LVL97: + 1281 .L128: +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1282 .loc 1 1119 55 discriminator 1 view .LVU408 + 1283 028c 394A ldr r2, .L133 + 1284 028e 1268 ldr r2, [r2] +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1285 .loc 1 1119 51 discriminator 1 view .LVU409 + 1286 0290 12F0020F tst r2, #2 + 1287 0294 E5D0 beq .L73 + ARM GAS /tmp/ccLRMPc2.s page 75 + + +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1288 .loc 1 1121 19 view .LVU410 + 1289 0296 3848 ldr r0, .L133+4 + 1290 0298 6AE0 b .L41 + 1291 .L129: +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1292 .loc 1 1126 9 is_stmt 1 view .LVU411 +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1293 .loc 1 1126 21 is_stmt 0 view .LVU412 + 1294 029a FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1295 .LVL98: +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1296 .loc 1 1126 21 view .LVU413 + 1297 029e 67E0 b .L41 + 1298 .LVL99: + 1299 .L130: +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1300 .loc 1 1129 55 discriminator 1 view .LVU414 + 1301 02a0 03F17E53 add r3, r3, #1065353216 + 1302 .LVL100: +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1303 .loc 1 1129 55 discriminator 1 view .LVU415 + 1304 02a4 03F50433 add r3, r3, #135168 + 1305 .LVL101: +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1306 .loc 1 1129 55 discriminator 1 view .LVU416 + 1307 02a8 186A ldr r0, [r3, #32] +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1308 .loc 1 1129 51 discriminator 1 view .LVU417 + 1309 02aa 10F00200 ands r0, r0, #2 + 1310 02ae 5FD0 beq .L41 +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1311 .loc 1 1131 19 view .LVU418 + 1312 02b0 4FF40040 mov r0, #32768 + 1313 02b4 5CE0 b .L41 + 1314 .LVL102: + 1315 .L45: +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1316 .loc 1 1139 7 is_stmt 1 view .LVU419 +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1317 .loc 1 1139 16 is_stmt 0 view .LVU420 + 1318 02b6 2F4B ldr r3, .L133 + 1319 02b8 1B6B ldr r3, [r3, #48] + 1320 .LVL103: +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1321 .loc 1 1142 7 is_stmt 1 view .LVU421 +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1322 .loc 1 1142 10 is_stmt 0 view .LVU422 + 1323 02ba 13F0100F tst r3, #16 + 1324 02be 06D1 bne .L75 +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1325 .loc 1 1142 49 discriminator 1 view .LVU423 + 1326 02c0 2C4B ldr r3, .L133 + 1327 .LVL104: +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1328 .loc 1 1142 49 discriminator 1 view .LVU424 + 1329 02c2 1868 ldr r0, [r3] + ARM GAS /tmp/ccLRMPc2.s page 76 + + +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1330 .loc 1 1142 45 discriminator 1 view .LVU425 + 1331 02c4 10F00200 ands r0, r0, #2 + 1332 02c8 52D0 beq .L41 +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1333 .loc 1 1144 19 view .LVU426 + 1334 02ca 2B48 ldr r0, .L133+4 + 1335 02cc 50E0 b .L41 + 1336 .LVL105: + 1337 .L75: +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1338 .loc 1 1149 9 is_stmt 1 view .LVU427 +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1339 .loc 1 1149 21 is_stmt 0 view .LVU428 + 1340 02ce FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1341 .LVL106: +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1342 .loc 1 1149 21 view .LVU429 + 1343 02d2 4DE0 b .L41 + 1344 .LVL107: + 1345 .L42: +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1346 .loc 1 1157 7 is_stmt 1 view .LVU430 +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1347 .loc 1 1157 16 is_stmt 0 view .LVU431 + 1348 02d4 274B ldr r3, .L133 + 1349 02d6 1B6B ldr r3, [r3, #48] + 1350 .LVL108: +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1351 .loc 1 1160 7 is_stmt 1 view .LVU432 +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1352 .loc 1 1160 10 is_stmt 0 view .LVU433 + 1353 02d8 13F0200F tst r3, #32 + 1354 02dc 06D1 bne .L76 +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1355 .loc 1 1160 49 discriminator 1 view .LVU434 + 1356 02de 254B ldr r3, .L133 + 1357 .LVL109: +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1358 .loc 1 1160 49 discriminator 1 view .LVU435 + 1359 02e0 1868 ldr r0, [r3] +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1360 .loc 1 1160 45 discriminator 1 view .LVU436 + 1361 02e2 10F00200 ands r0, r0, #2 + 1362 02e6 43D0 beq .L41 +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1363 .loc 1 1162 19 view .LVU437 + 1364 02e8 2348 ldr r0, .L133+4 + 1365 02ea 41E0 b .L41 + 1366 .LVL110: + 1367 .L76: +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1368 .loc 1 1167 9 is_stmt 1 view .LVU438 +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1369 .loc 1 1167 21 is_stmt 0 view .LVU439 + 1370 02ec FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1371 .LVL111: + ARM GAS /tmp/ccLRMPc2.s page 77 + + +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1372 .loc 1 1167 21 view .LVU440 + 1373 02f0 3EE0 b .L41 + 1374 .LVL112: + 1375 .L107: +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1376 .loc 1 1204 12 is_stmt 1 view .LVU441 +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1377 .loc 1 1206 9 view .LVU442 +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1378 .loc 1 1206 21 is_stmt 0 view .LVU443 + 1379 02f2 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1380 .LVL113: +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1381 .loc 1 1206 21 view .LVU444 + 1382 02f6 3BE0 b .L41 + 1383 .LVL114: + 1384 .L77: +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1385 .loc 1 1228 11 is_stmt 1 view .LVU445 +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1386 .loc 1 1228 24 is_stmt 0 view .LVU446 + 1387 02f8 FFF7FEFF bl RCC_GetPLLCLKFreq + 1388 .LVL115: +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1389 .loc 1 1228 44 view .LVU447 + 1390 02fc 00EB4000 add r0, r0, r0, lsl #1 +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1391 .loc 1 1228 21 view .LVU448 + 1392 0300 4008 lsrs r0, r0, #1 + 1393 .LVL116: +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1394 .loc 1 1228 21 view .LVU449 + 1395 0302 35E0 b .L41 + 1396 .LVL117: + 1397 .L54: +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC12 clock selection is AHB */ + 1398 .loc 1 1266 7 is_stmt 1 view .LVU450 +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC12 clock selection is AHB */ + 1399 .loc 1 1266 16 is_stmt 0 view .LVU451 + 1400 0304 1B4B ldr r3, .L133 + 1401 0306 DC6A ldr r4, [r3, #44] + 1402 .LVL118: +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1403 .loc 1 1268 7 is_stmt 1 view .LVU452 +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1404 .loc 1 1268 10 is_stmt 0 view .LVU453 + 1405 0308 14F4F874 ands r4, r4, #496 + 1406 .LVL119: +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1407 .loc 1 1268 10 view .LVU454 + 1408 030c 02D1 bne .L78 +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1409 .loc 1 1270 11 is_stmt 1 view .LVU455 +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1410 .loc 1 1270 21 is_stmt 0 view .LVU456 + 1411 030e 1B4B ldr r3, .L133+8 + ARM GAS /tmp/ccLRMPc2.s page 78 + + + 1412 0310 1868 ldr r0, [r3] + 1413 .LVL120: +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1414 .loc 1 1270 21 view .LVU457 + 1415 0312 2DE0 b .L41 + 1416 .LVL121: + 1417 .L78: +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1418 .loc 1 1276 9 is_stmt 1 view .LVU458 +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1419 .loc 1 1276 13 is_stmt 0 view .LVU459 + 1420 0314 174B ldr r3, .L133 + 1421 0316 1868 ldr r0, [r3] +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1422 .loc 1 1276 12 view .LVU460 + 1423 0318 10F00070 ands r0, r0, #33554432 + 1424 031c 28D0 beq .L41 +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1425 .loc 1 1279 11 is_stmt 1 view .LVU461 +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1426 .loc 1 1279 23 is_stmt 0 view .LVU462 + 1427 031e FFF7FEFF bl RCC_GetPLLCLKFreq + 1428 .LVL122: + 1429 .LBB30: + 1430 .LBI30: + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 1431 .loc 2 981 31 is_stmt 1 view .LVU463 + 1432 .LBB31: + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** + 1433 .loc 2 983 3 view .LVU464 + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1434 .loc 2 988 4 view .LVU465 + 1435 0322 4FF4F873 mov r3, #496 + 1436 .syntax unified + 1437 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1438 0326 93FAA3F3 rbit r3, r3 + 1439 @ 0 "" 2 + 1440 .LVL123: + 1441 .loc 2 1001 3 view .LVU466 + 1442 .loc 2 1001 3 is_stmt 0 view .LVU467 + 1443 .thumb + 1444 .syntax unified + 1445 .LBE31: + 1446 .LBE30: +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1447 .loc 1 1279 74 view .LVU468 + 1448 032a B3FA83F3 clz r3, r3 + 1449 032e 24FA03F3 lsr r3, r4, r3 +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1450 .loc 1 1279 111 view .LVU469 + 1451 0332 03F00F03 and r3, r3, #15 +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1452 .loc 1 1279 65 view .LVU470 + 1453 0336 08AA add r2, sp, #32 + 1454 0338 02EB4303 add r3, r2, r3, lsl #1 + 1455 033c 33F8203C ldrh r3, [r3, #-32] +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccLRMPc2.s page 79 + + + 1456 .loc 1 1279 21 view .LVU471 + 1457 0340 B0FBF3F0 udiv r0, r0, r3 + 1458 .LVL124: +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1459 .loc 1 1279 21 view .LVU472 + 1460 0344 14E0 b .L41 + 1461 .LVL125: + 1462 .L52: +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1463 .loc 1 1312 7 is_stmt 1 view .LVU473 +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1464 .loc 1 1312 16 is_stmt 0 view .LVU474 + 1465 0346 0B4B ldr r3, .L133 + 1466 0348 1B6B ldr r3, [r3, #48] + 1467 .LVL126: +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1468 .loc 1 1315 7 is_stmt 1 view .LVU475 +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1469 .loc 1 1315 10 is_stmt 0 view .LVU476 + 1470 034a 13F4807F tst r3, #256 + 1471 034e 07D0 beq .L79 +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1472 .loc 1 1315 46 discriminator 1 view .LVU477 + 1473 0350 084B ldr r3, .L133 + 1474 .LVL127: +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1475 .loc 1 1315 46 discriminator 1 view .LVU478 + 1476 0352 1868 ldr r0, [r3] +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1477 .loc 1 1315 42 discriminator 1 view .LVU479 + 1478 0354 10F00070 ands r0, r0, #33554432 + 1479 0358 0AD0 beq .L41 +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1480 .loc 1 1317 9 is_stmt 1 view .LVU480 +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1481 .loc 1 1317 21 is_stmt 0 view .LVU481 + 1482 035a FFF7FEFF bl RCC_GetPLLCLKFreq + 1483 .LVL128: +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1484 .loc 1 1317 19 view .LVU482 + 1485 035e 07E0 b .L41 + 1486 .LVL129: + 1487 .L79: +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1488 .loc 1 1322 9 is_stmt 1 view .LVU483 +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1489 .loc 1 1322 19 is_stmt 0 view .LVU484 + 1490 0360 064B ldr r3, .L133+8 + 1491 .LVL130: +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1492 .loc 1 1322 19 view .LVU485 + 1493 0362 1868 ldr r0, [r3] + 1494 .LVL131: +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1495 .loc 1 1322 19 view .LVU486 + 1496 0364 04E0 b .L41 + 1497 .LVL132: + ARM GAS /tmp/ccLRMPc2.s page 80 + + + 1498 .L80: + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1499 .loc 1 962 3 view .LVU487 + 1500 0366 0020 movs r0, #0 + 1501 0368 02E0 b .L41 + 1502 .L81: + 1503 036a 0020 movs r0, #0 + 1504 036c 00E0 b .L41 + 1505 .LVL133: + 1506 .L82: + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1507 .loc 1 962 3 view .LVU488 + 1508 036e 0020 movs r0, #0 + 1509 .LVL134: + 1510 .L41: +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1511 .loc 1 1514 1 view .LVU489 + 1512 0370 09B0 add sp, sp, #36 + 1513 .cfi_def_cfa_offset 12 + 1514 @ sp needed + 1515 0372 30BD pop {r4, r5, pc} + 1516 .L134: + 1517 .align 2 + 1518 .L133: + 1519 0374 00100240 .word 1073876992 + 1520 0378 00127A00 .word 8000000 + 1521 037c 00000000 .word SystemCoreClock + 1522 .cfi_endproc + 1523 .LFE132: + 1525 .section .rodata + 1526 .align 2 + 1527 .set .LANCHOR0,. + 0 + 1528 .LC0: + 1529 0000 0100 .short 1 + 1530 0002 0200 .short 2 + 1531 0004 0400 .short 4 + 1532 0006 0600 .short 6 + 1533 0008 0800 .short 8 + 1534 000a 0A00 .short 10 + 1535 000c 0C00 .short 12 + 1536 000e 1000 .short 16 + 1537 0010 2000 .short 32 + 1538 0012 4000 .short 64 + 1539 0014 8000 .short 128 + 1540 0016 0001 .short 256 + 1541 0018 0001 .short 256 + 1542 001a 0001 .short 256 + 1543 001c 0001 .short 256 + 1544 001e 0001 .short 256 + 1545 .text + 1546 .Letext0: + 1547 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1548 .file 4 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 1549 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1550 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1551 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1552 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h" + ARM GAS /tmp/ccLRMPc2.s page 81 + + + 1553 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" + 1554 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 1555 .file 11 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + ARM GAS /tmp/ccLRMPc2.s page 82 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_rcc_ex.c + /tmp/ccLRMPc2.s:21 .text.RCC_GetPLLCLKFreq:0000000000000000 $t + /tmp/ccLRMPc2.s:26 .text.RCC_GetPLLCLKFreq:0000000000000000 RCC_GetPLLCLKFreq + /tmp/ccLRMPc2.s:91 .text.RCC_GetPLLCLKFreq:0000000000000030 $d + /tmp/ccLRMPc2.s:98 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 $t + /tmp/ccLRMPc2.s:104 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 HAL_RCCEx_PeriphCLKConfig + /tmp/ccLRMPc2.s:620 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000228 $d + /tmp/ccLRMPc2.s:627 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 $t + /tmp/ccLRMPc2.s:633 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 HAL_RCCEx_GetPeriphCLKConfig + /tmp/ccLRMPc2.s:747 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000080 $d + /tmp/ccLRMPc2.s:759 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 $t + /tmp/ccLRMPc2.s:765 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 HAL_RCCEx_GetPeriphCLKFreq + /tmp/ccLRMPc2.s:810 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000038 $d + /tmp/ccLRMPc2.s:843 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000078 $t + /tmp/ccLRMPc2.s:1275 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000278 $d + /tmp/ccLRMPc2.s:1283 .text.HAL_RCCEx_GetPeriphCLKFreq:000000000000028c $t + /tmp/ccLRMPc2.s:1519 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000374 $d + /tmp/ccLRMPc2.s:1526 .rodata:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_RCC_GetPCLK2Freq +HAL_RCC_GetSysClockFreq +HAL_RCC_GetPCLK1Freq +SystemCoreClock diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc_ex.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_rcc_ex.o new file mode 100644 index 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Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi.lst new file mode 100644 index 0000000..129b0fe --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi.lst @@ -0,0 +1,15193 @@ +ARM GAS /tmp/ccywxtmH.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_spi.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c" + 20 .section .text.SPI_WaitFlagStateUntilTimeout,"ax",%progbits + 21 .align 1 + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 SPI_WaitFlagStateUntilTimeout: + 27 .LVL0: + 28 .LFB177: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @file stm32f3xx_hal_spi.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * functionalities of the Serial Peripheral Interface (SPI) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + IO operation functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + Peripheral Control functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + Peripheral State functions + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @verbatim + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ============================================================================== + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ##### How to use this driver ##### + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ============================================================================== + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The SPI HAL driver can be used as follows: + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) Declare a SPI_HandleTypeDef handle structure, for example: + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef hspi; + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) Enable the SPIx interface clock + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) SPI pins configuration + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Enable the clock for the SPI GPIOs + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure these SPI pins as alternate function push-pull + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) NVIC configuration if you need to use interrupt process + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure the SPIx interrupt priority + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Enable the NVIC SPI IRQ handle + ARM GAS /tmp/ccywxtmH.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) DMA Configuration if you need to use DMA process + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Enable the DMAx clock + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure the DMA handle parameters + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure the DMA Tx or Rx Stream/Channel + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx hand + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init str + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** by calling the customized HAL_SPI_MspInit() API. + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Circular mode restriction: + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) Master 2Lines RxOnly + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) Master 1Line Rx + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) The CRC feature is not managed when the DMA circular mode is enabled + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Master Receive mode restriction: + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** does not initiate a new transfer the following procedure has to be respected: + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) HAL_SPI_DeInit() + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) HAL_SPI_Init() + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Callback registration: + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** allows the user to configure dynamically the driver callbacks. + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Function HAL_SPI_RegisterCallback() allows to register following callbacks: + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxCpltCallback : SPI Tx Completed callback + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) RxCpltCallback : SPI Rx Completed callback + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxRxCpltCallback : SPI TxRx Completed callback + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxHalfCpltCallback : SPI Tx Half Completed callback + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) RxHalfCpltCallback : SPI Rx Half Completed callback + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) ErrorCallback : SPI Error callback + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) AbortCpltCallback : SPI Abort callback + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) MspInitCallback : SPI Msp Init callback + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) MspDeInitCallback : SPI Msp DeInit callback + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and a pointer to the user callback function. + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** weak function. + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and the Callback ID. + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** This function allows to reset following callbacks: + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxCpltCallback : SPI Tx Completed callback + ARM GAS /tmp/ccywxtmH.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) RxCpltCallback : SPI Rx Completed callback + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxRxCpltCallback : SPI TxRx Completed callback + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxHalfCpltCallback : SPI Tx Half Completed callback + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) RxHalfCpltCallback : SPI Rx Half Completed callback + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) ErrorCallback : SPI Error callback + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) AbortCpltCallback : SPI Abort callback + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) MspInitCallback : SPI Msp Init callback + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) MspDeInitCallback : SPI Msp DeInit callback + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** all callbacks are set to the corresponding weak functions: + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Exception done for MspInit and MspDeInit functions that are + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** these callbacks are null (not registered beforehand). + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Then, the user first registers the MspInit/MspDeInit user callbacks + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** or HAL_SPI_Init() function. + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** not defined, the callback registering feature is not available + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and weak (surcharged) callbacks are used. + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Using the HAL it is not possible to reach all supported SPI frequency with the different SPI + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the following table resume the max SPI frequency reached with data size 8bits/16bits, + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @endverbatim + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Additional table : + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** DataSize = SPI_DATASIZE_8BIT: + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +------------------------------------------------------------------------------------------- + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | Process | Transfer mode |---------------------|----------------------|------------------- + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | | Master | Slave | Master | Slave | Master | Slave + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========================================================================================== + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | R |----------------|----------|----------|-----------|----------|-----------|------- + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|======= + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/ + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|------- + ARM GAS /tmp/ccywxtmH.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/ + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/ + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|======= + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/ + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|------- + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/ + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/ + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +------------------------------------------------------------------------------------------- + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** DataSize = SPI_DATASIZE_16BIT: + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +------------------------------------------------------------------------------------------- + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | Process | Transfer mode |---------------------|----------------------|------------------- + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | | Master | Slave | Master | Slave | Master | Slave + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========================================================================================== + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | R |----------------|----------|----------|-----------|----------|-----------|------- + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|======= + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/ + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|------- + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/ + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/ + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|======= + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/ + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|------- + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/ + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/ + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +------------------------------------------------------------------------------------------- + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bi + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @note + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ****************************************************************************** + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @attention + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * All rights reserved.

    + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * This software component is licensed by ST under BSD 3-Clause license, + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the "License"; You may not use this file except in compliance with the + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * License. You may obtain a copy of the License at: + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * opensource.org/licenses/BSD-3-Clause + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ****************************************************************************** + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Includes ------------------------------------------------------------------*/ + ARM GAS /tmp/ccywxtmH.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #include "stm32f3xx_hal.h" + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @addtogroup STM32F3xx_HAL_Driver + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI SPI + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI HAL module driver + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #ifdef HAL_SPI_MODULE_ENABLED + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private typedef -----------------------------------------------------------*/ + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private defines -----------------------------------------------------------*/ + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Private_Constants SPI Private Constants + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #define SPI_DEFAULT_TIMEOUT 100U + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private macros ------------------------------------------------------------*/ + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private variables ---------------------------------------------------------*/ + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private function prototypes -----------------------------------------------*/ + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Private_Functions SPI Private Functions + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAError(DMA_HandleTypeDef *hdma); + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, Flag + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout, uint32_t Tickstart); + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout, uint32_t Tickstart); + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); + ARM GAS /tmp/ccywxtmH.s page 6 + + + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t T + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Exported functions --------------------------------------------------------*/ + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Exported_Functions SPI Exported Functions + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Initialization and Configuration functions + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @verbatim + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ##### Initialization and de-initialization functions ##### + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] This subsection provides a set of functions allowing to initialize and + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** de-initialize the SPIx peripheral: + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) User must implement HAL_SPI_MspInit() function in which he configures + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) Call the function HAL_SPI_Init() to configure the selected device with + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the selected configuration: + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Mode + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Direction + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Data Size + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Clock Polarity and Phase + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) NSS Management + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) BaudRate Prescaler + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) FirstBit + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TIMode + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) CRC Calculation + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) CRC Polynomial if CRC enabled + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) CRC Length, used only with Data8 and Data16 + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) FIFO reception threshold + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) Call the function HAL_SPI_DeInit() to restore the default configuration + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** of the selected SPIx peripheral. + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @endverbatim + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Initialize the SPI according to the specified parameters + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * in the SPI_InitTypeDef and initialize the associated handle. + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + ARM GAS /tmp/ccywxtmH.s page 7 + + + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t frxth; + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the SPI handle allocation */ + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi == NULL) + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_ERROR; + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the parameters */ + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_MODE(hspi->Init.Mode)); + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_NSS(hspi->Init.NSS)); + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Mode == SPI_MODE_MASTER) + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Force polarity and phase to TI protocaol requirements */ + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State == HAL_SPI_STATE_RESET) + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Allocate lock resource and initialize it */ + ARM GAS /tmp/ccywxtmH.s page 8 + + + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Lock = HAL_UNLOCKED; + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init the SPI Callback settings */ + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->MspInitCallback == NULL) + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback(hspi); + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_MspInit(hspi); + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY; + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the selected SPI peripheral */ + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Align by default the rs fifo threshold on the data size */ + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** frxth = SPI_RXFIFO_THRESHOLD_HF; + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** frxth = SPI_RXFIFO_THRESHOLD_QF; + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC calculation is valid only for 16Bit and 8 Bit */ + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC must be disabled */ + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Communication speed, First bit and CRC calculation state */ + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.NSS & SPI_CR1_SSM) | + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + ARM GAS /tmp/ccywxtmH.s page 9 + + + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*---------------------------- SPIx CRCL Configuration -------------------*/ + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Align the CRC Length on the data size */ + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC Length aligned on the data size : value set by default */ + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure : CRC Length */ + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.TIMode & SPI_CR2_FRF) | + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (frxth & SPI_CR2_FRXTH))); + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure : CRC Polynomial */ + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if defined(SPI_I2SCFGR_I2SMOD) + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* SPI_I2SCFGR_I2SMOD */ + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief De-Initialize the SPI peripheral. + ARM GAS /tmp/ccywxtmH.s page 10 + + + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the SPI handle allocation */ + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi == NULL) + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_ERROR; + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check SPI Instance parameter */ + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY; + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI Peripheral Clock */ + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->MspDeInitCallback == NULL) + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback(hspi); + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_MspDeInit(hspi); + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_RESET; + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Release Lock */ + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Initialize the SPI MSP. + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_MspInit should be implemented in the user file + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 11 + + + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief De-Initialize the SPI MSP. + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_MspDeInit should be implemented in the user file + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Register a User SPI Callback + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * To be used instead of the weak predefined callback + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI. + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param CallbackID ID of the callback to be registered + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pCallback pointer to the Callback function + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef Callb + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** pSPI_CallbackTypeDef pCallback) + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef status = HAL_OK; + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (pCallback == NULL) + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_ERROR; + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process locked */ + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_SPI_STATE_READY == hspi->State) + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** switch (CallbackID) + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_COMPLETE_CB_ID : + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback = pCallback; + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_RX_COMPLETE_CB_ID : + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback = pCallback; + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_RX_COMPLETE_CB_ID : + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback = pCallback; + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + ARM GAS /tmp/ccywxtmH.s page 12 + + + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxHalfCpltCallback = pCallback; + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxHalfCpltCallback = pCallback; + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxHalfCpltCallback = pCallback; + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_ERROR_CB_ID : + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback = pCallback; + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_ABORT_CB_ID : + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback = pCallback; + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPINIT_CB_ID : + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = pCallback; + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPDEINIT_CB_ID : + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = pCallback; + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** default : + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else if (HAL_SPI_STATE_RESET == hspi->State) + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** switch (CallbackID) + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPINIT_CB_ID : + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = pCallback; + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPDEINIT_CB_ID : + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = pCallback; + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** default : + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + ARM GAS /tmp/ccywxtmH.s page 13 + + + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Release Lock */ + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return status; + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Unregister an SPI Callback + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * SPI callback is redirected to the weak predefined callback + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI. + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param CallbackID ID of the callback to be unregistered + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef Cal + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef status = HAL_OK; + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process locked */ + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_SPI_STATE_READY == hspi->State) + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** switch (CallbackID) + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_COMPLETE_CB_ID : + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_RX_COMPLETE_CB_ID : + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_RX_COMPLETE_CB_ID : + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallbac + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallbac + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallb + ARM GAS /tmp/ccywxtmH.s page 14 + + + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_ERROR_CB_ID : + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_ABORT_CB_ID : + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPINIT_CB_ID : + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPDEINIT_CB_ID : + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** default : + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else if (HAL_SPI_STATE_RESET == hspi->State) + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** switch (CallbackID) + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPINIT_CB_ID : + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPDEINIT_CB_ID : + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** default : + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 15 + + + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Release Lock */ + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return status; + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Exported_Functions_Group2 IO operation functions + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Data transfers functions + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @verbatim + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ============================================================================== + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ##### IO operation functions ##### + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** This subsection provides a set of functions allowing to manage the SPI + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** data transfers. + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] The SPI supports master and slave mode : + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) There are two modes of transfer: + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Blocking mode: The communication is performed in polling mode. + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The HAL status of all data processing is returned by the same function + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** after finishing transfer. + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) No-Blocking mode: The communication is performed using Interrupts + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** or DMA, These APIs return the HAL status. + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The end of the data processing will be indicated through the + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** using DMA mode. + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() u + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will be executed respectively at the end of the transmit or Receive process + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either I + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** exist for 1Line (simplex) and 2Lines (full duplex) modes. + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @endverbatim + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit an amount of data in blocking mode. + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_TxXferCount; + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 16 + + + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*Init field not used in handle to zero */ + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)NULL; + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + ARM GAS /tmp/ccywxtmH.s page 17 + + + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while (hspi->TxXferCount > 0U) + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Timeout management */ + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout = + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 8 Bit mode */ + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount > 1U) + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* write on the data register in packing mode */ + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr ++; + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while (hspi->TxXferCount > 0U) + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount > 1U) + ARM GAS /tmp/ccywxtmH.s page 18 + + + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* write on the data register in packing mode */ + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Timeout management */ + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout = + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear overrun flag in 2 Lines communication mode because received is not read */ + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error: + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + ARM GAS /tmp/ccywxtmH.s page 19 + + +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Receive an amount of data in blocking mode. +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be received +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t * ptmpreg8; +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*Init field not used in handle to zero */ +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)NULL; +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 20 + + +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* this is done to handle the CRCNEXT before the latest data */ +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the Rx Fifo threshold */ +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16bit */ +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8bit */ +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction: 1Line */ +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in 8 Bit mode */ +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transfer loop */ +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while (hspi->RxXferCount > 0U) +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the RXNE flag */ +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* read the received data */ +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint8_t); +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Timeout management */ +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout = +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + ARM GAS /tmp/ccywxtmH.s page 21 + + +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transfer loop */ +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while (hspi->RxXferCount > 0U) +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the RXNE flag */ +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Timeout management */ +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout = +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Handle the CRC Transmission */ +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* freeze the CRC before the latest data */ +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read the latest data */ +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* the latest data has not been received */ +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive last data in 16 Bit mode */ +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive last data in 8 Bit mode */ +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait the CRC data */ +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + ARM GAS /tmp/ccywxtmH.s page 22 + + +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC to Flush DR and RXNE flag */ +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC */ +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC */ +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16B +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + ARM GAS /tmp/ccywxtmH.s page 23 + + +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in blocking mode. +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pTxData pointer to transmission data buffer +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pRxData pointer to reception data buffer +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent and received +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxDa +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout) +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_TxXferCount; +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_RxXferCount; +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t spi_cr1; +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t spi_cr2; +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t * ptmpreg8; +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Variable used to alternate Rx and Tx during transfer */ +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t txallowed = 1U; +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init temporary variables */ +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_state = hspi->State; +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_RxXferCount = Size; +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** spi_cr1 = READ_REG(hspi->Instance->CR1); +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** spi_cr2 = READ_REG(hspi->Instance->CR2); + ARM GAS /tmp/ccywxtmH.s page 24 + + +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (!((tmp_state == HAL_SPI_STATE_READY) || \ +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_BUSY_RX) +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*Init field not used in handle to zero */ +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the Rx Fifo threshold */ +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set fiforxthreshold according the reception data length: 16bit */ +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set fiforxthreshold according the reception data length: 8bit */ +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 25 + + +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit and Receive data in 16 Bit mode */ +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check TXE flag */ +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U) +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a reception (Rx). Tx not allowed */ +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** txallowed = 0U; +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check RXNE flag */ +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a Transmission (Tx). Tx is allowed */ +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** txallowed = 1U; +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit and Receive data in 8 Bit mode */ +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 26 + + +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount > 1U) +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check TXE flag */ +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U) +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount > 1U) +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a reception (Rx). Tx not allowed */ +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** txallowed = 0U; +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until RXNE flag is reset */ +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount > 1U) +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + ARM GAS /tmp/ccywxtmH.s page 27 + + +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount <= 1U) +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold before to switch on 8 bit data size */ +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a Transmission (Tx). Tx is allowed */ +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** txallowed = 1U; +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout = +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC from DR to close CRC calculation process */ +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until TXE flag */ +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC */ +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC */ +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC */ +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ + ARM GAS /tmp/ccywxtmH.s page 28 + + +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear CRC Flag */ +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit an amount of data in non-blocking mode with Interrupt. +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + ARM GAS /tmp/ccywxtmH.s page 29 + + +1570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) +1574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; +1585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init field not used in handle to zero */ +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)NULL; +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the function for IT treatment */ +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_TxISR_16BIT; +1596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_TxISR_8BIT; +1600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) +1604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); +1608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable TXE and ERR interrupt */ +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + ARM GAS /tmp/ccywxtmH.s page 30 + + +1627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Receive an amount of data in non-blocking mode with Interrupt. +1636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) +1647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); +1651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) +1657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) +1663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init field not used in handle to zero */ +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)NULL; +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 31 + + +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16 bit */ +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_16BIT; +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8 bit */ +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_8BIT; +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 1U; +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 2U; +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 0U; +1717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable TXE and ERR interrupt */ +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); +1722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Note : The SPI must be enabled after unlocking current process +1724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** to avoid the risk of SPI interrupt handle execution before current +1725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** process unlock */ +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + ARM GAS /tmp/ccywxtmH.s page 32 + + +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. +1742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pTxData pointer to transmission data buffer +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pRxData pointer to reception data buffer +1746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent and received +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pR +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process locked */ +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +1760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init temporary variables */ +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_state = hspi->State; +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (!((tmp_state == HAL_SPI_STATE_READY) || \ +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st +1767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_BUSY_RX) +1780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the function for IT treatment */ +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_2linesRxISR_16BIT; +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_16BIT; + ARM GAS /tmp/ccywxtmH.s page 33 + + +1798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_2linesRxISR_8BIT; +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_8BIT; +1803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 1U; +1810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT +1811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 2U; +1813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 0U; +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if packing mode is enabled and if there is more than 2 data to receive */ +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16 bit */ +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8 bit */ +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +1832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable TXE, RXNE and ERR interrupt */ +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit an amount of data in non-blocking mode with DMA. +1852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer + ARM GAS /tmp/ccywxtmH.s page 34 + + +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +1856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check tx dma handle */ +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); +1864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +1870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) +1878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; +1889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init field not used in handle to zero */ +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)NULL; +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) +1899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); +1903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + ARM GAS /tmp/ccywxtmH.s page 35 + + +1912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI TxDMA Half transfer complete callback */ +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI TxDMA transfer complete callback */ +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA error callback */ +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = SPI_DMAError; +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA AbortCpltCallback */ +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Packing mode is enabled only if the DMA setting is HALWORD */ +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDA +1928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the even/odd of the data size + crc if enabled */ +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->TxXferCount & 0x1U) == 0U) +1931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U); +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the Tx DMA Stream/Channel */ +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instanc +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update SPI error code */ +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +1956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the SPI Error Interrupt Bit */ +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); +1963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable Tx DMA Request */ +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +1966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ + ARM GAS /tmp/ccywxtmH.s page 36 + + +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Receive an amount of data in non-blocking mode with DMA. +1975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note When the CRC feature is enabled the pData Length must be Size + 1. +1980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +1981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +1986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check rx dma handle */ +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); +1989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) +1991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; +1993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check tx dma handle */ +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); +1996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); +1999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +2003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; +2007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) +2011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*Init field not used in handle to zero */ +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + ARM GAS /tmp/ccywxtmH.s page 37 + + +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) +2031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +2038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +2042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +2044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx +2046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Packing mode management is enabled by the DMA settings */ +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDA +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restriction the DMA data received is not allowed in this mode */ +2050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */ +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +2057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16bit */ +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +2060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8bit */ +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) +2067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16bit */ +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +2070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->RxXferCount & 0x1U) == 0x0U) +2072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = hspi->RxXferCount >> 1U; +2075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 38 + + +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI RxDMA Half transfer complete callback */ +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI Rx DMA transfer complete callback */ +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; +2089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA error callback */ +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferErrorCallback = SPI_DMAError; +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA AbortCpltCallback */ +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the Rx DMA Stream/Channel */ +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBu +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update SPI error code */ +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +2110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +2113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the SPI Error Interrupt Bit */ +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); +2117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable Rx DMA Request */ +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +2120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error: +2122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. +2129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pTxData pointer to transmission data buffer +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pRxData pointer to reception data buffer +2133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note When the CRC feature is enabled the pRxData Length must be Size + 1 +2134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *p +2138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t Size) +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 39 + + +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +2143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check rx & tx dma handles */ +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); +2147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); +2150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process locked */ +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init temporary variables */ +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_state = hspi->State; +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (!((tmp_state == HAL_SPI_STATE_READY) || +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; +2162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_BUSY_RX) +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; +2175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init field not used in handle to zero */ +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +2191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +2192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +2193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + ARM GAS /tmp/ccywxtmH.s page 40 + + +2197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Packing mode management is enabled by the DMA settings */ +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDA +2201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restriction the DMA data received is not allowed in this mode */ +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */ +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset the threshold bit */ +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* The packing mode management is enabled by the DMA settings according the spi data size */ +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set fiforxthreshold according the reception data length: 16bit */ +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +2216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8bit */ +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +2221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) +2223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->TxXferSize & 0x1U) == 0x0U) +2225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = hspi->TxXferCount >> 1U; +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; +2233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) +2237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16bit */ +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +2240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->RxXferCount & 0x1U) == 0x0U) +2242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = hspi->RxXferCount >> 1U; +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 41 + + +2254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback * +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State == HAL_SPI_STATE_BUSY_RX) +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI Rx DMA Half transfer complete callback */ +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; +2260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI Tx/Rx DMA Half transfer complete callback */ +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; +2266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA error callback */ +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferErrorCallback = SPI_DMAError; +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA AbortCpltCallback */ +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; +2273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the Rx DMA Stream/Channel */ +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBu +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update SPI error code */ +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable Rx DMA Request */ +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +2288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** is performed in DMA reception complete callback */ +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferHalfCpltCallback = NULL; +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = NULL; +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = NULL; +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; +2295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the Tx DMA Stream/Channel */ +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instanc +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update SPI error code */ +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) +2310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 42 + + +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the SPI Error Interrupt Bit */ +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); +2316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable Tx DMA Request */ +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +2319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +2321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Abort ongoing transfer (blocking mode). +2328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi SPI handle. +2329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), +2330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * started in Interrupt or DMA mode. +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * This procedure performs following operations : +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Disable SPI Interrupts (depending of transfer direction) +2333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +2334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Set handle State to READY +2336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +2337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode; +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t resetcount; +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialized local variable */ +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_OK; +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); +2352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) +2355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_AbortTx_ISR; +2357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) +2361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; +2364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); +2367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + ARM GAS /tmp/ccywxtmH.s page 43 + + +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_AbortRx_ISR; +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) +2378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; +2381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); +2384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Tx request if enabled */ +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) +2393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI DMA Abort callback : +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort DMA Tx Handle linked to SPI Peripheral */ +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +2402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Tx DMA Request */ +2405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); +2406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +2410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +2413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +2414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, +2417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +2419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Rx request if enabled */ +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + ARM GAS /tmp/ccywxtmH.s page 44 + + +2425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI DMA Abort callback : +2430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; +2432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort DMA Rx Handle linked to SPI Peripheral */ +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) +2435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +2437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable peripheral */ +2440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +2441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +2446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, +2450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Rx DMA Request */ +2455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); +2456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Tx and Rx transfer counters */ +2459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +2460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +2461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check error during Abort procedure */ +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) +2464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* return HAL_Error in case of error during Abort procedure */ +2466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset errorCode */ +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +2472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear the Error flags in the SR register */ +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restore hspi->state to ready */ +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + ARM GAS /tmp/ccywxtmH.s page 45 + + +2482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Abort ongoing transfer (Interrupt mode). +2486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi SPI handle. +2487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), +2488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * started in Interrupt or DMA mode. +2489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * This procedure performs following operations : +2490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Disable SPI Interrupts (depending of transfer direction) +2491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +2492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +2493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Set handle State to READY +2494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - At abort completion, call user abort complete callback +2495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +2496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * considered as completed only when user abort complete callback is executed (not when ex +2497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +2500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode; +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t abortcplt ; +2503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; +2504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t resetcount; +2505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialized local variable */ +2507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_OK; +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** abortcplt = 1U; +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; +2511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); +2514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_AbortTx_ISR; +2519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +2521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) +2523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); +2525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; +2526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); +2529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ +2530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; +2531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) +2534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_AbortRx_ISR; +2536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +2538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 46 + + +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); +2542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; +2543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; +2545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); +2546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ +2547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; +2548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks sho +2551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** before any call to DMA Abort functions */ +2552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Tx Handle is valid */ +2553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) +2554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. +2556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Otherwise, set it to NULL */ +2557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) +2558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; +2560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; +2564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Rx Handle is valid */ +2567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. +2570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Otherwise, set it to NULL */ +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) +2572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; +2574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; +2578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Tx request if enabled */ +2582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) +2583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Tx Stream/Channel */ +2585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) +2586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort DMA Tx Handle linked to SPI Peripheral */ +2588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) +2589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; +2591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +2592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** abortcplt = 0U; + ARM GAS /tmp/ccywxtmH.s page 47 + + +2596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Rx request if enabled */ +2600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) +2601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Rx Stream/Channel */ +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) +2604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort DMA Rx Handle linked to SPI Peripheral */ +2606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) +2607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; +2609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +2610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** abortcplt = 0U; +2614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (abortcplt == 1U) +2619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Tx and Rx transfer counters */ +2621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +2622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +2623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check error during Abort procedure */ +2625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) +2626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* return HAL_Error in case of error during Abort procedure */ +2628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset errorCode */ +2633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +2634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear the Error flags in the SR register */ +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); +2639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restore hspi->State to Ready */ +2641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +2645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback(hspi); +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +2647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_AbortCpltCallback(hspi); +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +2649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +2652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 48 + + +2653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Pause the DMA Transfer. +2656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI module. +2658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +2661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +2664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Tx & Rx requests */ +2666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); +2667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +2669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +2670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; +2672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Resume the DMA Transfer. +2676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI module. +2678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +2681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); +2684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the SPI DMA Tx & Rx requests */ +2686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +2689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +2690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; +2692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Stop the DMA Transfer. +2696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI module. +2698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +2701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; +2703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* The Lock is not implemented on this API to allow the user application +2704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() o +2705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated +2706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() +2707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA tx Stream/Channel */ + ARM GAS /tmp/ccywxtmH.s page 49 + + +2710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) +2711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) +2713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); +2715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA rx Stream/Channel */ +2719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) +2720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) +2722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); +2724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +2725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Tx & Rx requests */ +2729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); +2730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; +2732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle SPI interrupt request. +2736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI module. +2738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +2741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itsource = hspi->Instance->CR2; +2743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itflag = hspi->Instance->SR; +2744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI in mode Receiver ----------------------------------------------------*/ +2746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && +2747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXN +2748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR(hspi); +2750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +2751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI in mode Transmitter -------------------------------------------------*/ +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) +2755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR(hspi); +2757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +2758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI in Error Treatment --------------------------------------------------*/ +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != +2762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT +2763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI Overrun error interrupt occurred ----------------------------------*/ +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) +2766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 50 + + +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_BUSY_TX) +2768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +2771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +2775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +2776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI Mode Fault error interrupt occurred -------------------------------*/ +2780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_MODFFLAG(hspi); +2784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI Frame error interrupt occurred ------------------------------------*/ +2787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) +2788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); +2791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) +2794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable all interrupts */ +2796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); +2797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +2799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA requests if enabled */ +2800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN) +2801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); +2803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Rx channel */ +2805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) +2806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI DMA Abort callback : +2808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ +2809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) +2811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); +2813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Tx channel */ +2816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) +2817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI DMA Abort callback : +2819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ +2820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; +2821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) +2822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + ARM GAS /tmp/ccywxtmH.s page 51 + + +2824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +2830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +2831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +2832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +2834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +2838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx Transfer completed callback. +2843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +2848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_TxCpltCallback should be implemented in the user file +2854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx Transfer completed callback. +2859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +2864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_RxCpltCallback should be implemented in the user file +2870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx and Rx Transfer completed callback. +2875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +2880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 52 + + +2881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_TxRxCpltCallback should be implemented in the user file +2886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx Half Transfer completed callback. +2891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_TxHalfCpltCallback should be implemented in the user file +2902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx Half Transfer completed callback. +2907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +2912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file +2918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx and Rx Half Transfer callback. +2923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +2928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file +2934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + ARM GAS /tmp/ccywxtmH.s page 53 + + +2938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI error callback. +2939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +2944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_ErrorCallback should be implemented in the user file +2950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes +2952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and user can use HAL_SPI_GetError() API to check the latest error occurred +2953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI Abort Complete callback. +2958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi SPI handle. +2959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +2962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_AbortCpltCallback can be implemented in the user file. +2968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} +2973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions +2976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI control functions +2977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * +2978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @verbatim +2979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ##### Peripheral State and Errors functions ##### +2981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] +2983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** This subsection provides a set of functions allowing to control the SPI. +2984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral +2985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +2986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @endverbatim +2987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ +2988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Return the SPI handle state. +2992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval SPI state + ARM GAS /tmp/ccywxtmH.s page 54 + + +2995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +2997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return SPI handle state */ +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return hspi->State; +3000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Return the SPI error code. +3004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval SPI error code in bitmap format +3007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return SPI ErrorCode */ +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return hspi->ErrorCode; +3012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} +3016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} +3020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @addtogroup SPI_Private_Functions +3023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Private functions +3024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ +3025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI transmit process complete callback. +3029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +3037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +3039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); +3040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Normal Mode */ +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) +3043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable ERR interrupt */ +3045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); +3046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Tx DMA Request */ +3048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +3049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + ARM GAS /tmp/ccywxtmH.s page 55 + + +3052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +3054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear overrun flag in 2 Lines communication mode because received data is not read */ +3057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_2LINES) +3058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +3060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +3063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +3064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) +3066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +3072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Tx complete callback */ +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback(hspi); +3079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxCpltCallback(hspi); +3081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI receive process complete callback. +3086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +3094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +3096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t * ptmpreg8; +3097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +3098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +3101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); +3102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Normal Mode */ +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) +3105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable ERR interrupt */ +3107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); +3108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 56 + + +3109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC handling */ +3111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until RXNE flag */ +3114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) ! +3115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +3117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC */ +3120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +3121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC */ +3123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +3124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +3126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +3130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC */ +3132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) +3137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstar +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +3141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ +3144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if we are in Master RX 2 line mode */ +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) +3154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) +3156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); +3157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Normal case */ +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +3162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + ARM GAS /tmp/ccywxtmH.s page 57 + + +3166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; +3168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +3171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +3175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) +3176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +3179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) +3183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +3189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ +3194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback(hspi); +3196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); +3198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI transmit receive process complete callback. +3203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +3208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +3211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +3213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t * ptmpreg8; +3214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +3215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +3218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); +3219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Normal Mode */ +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) +3222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 58 + + +3223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable ERR interrupt */ +3224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); +3225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC handling */ +3228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BI +3231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT +3233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart) != HAL_OK) +3234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +3236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +3239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +3240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC */ +3241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TI +3248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +3250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC to Flush DR and RXNE flag */ +3253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +3254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +3256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) +3262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Rx/Tx DMA Request */ +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); +3268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +3272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +3275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) +3276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +3279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 59 + + +3280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) +3283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +3289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx complete callback */ +3294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback(hspi); +3296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); +3298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI half transmit process complete callback. +3303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +3308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Tx half complete callback */ +3312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxHalfCpltCallback(hspi); +3314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxHalfCpltCallback(hspi); +3316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI half receive process complete callback +3321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +3326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx half complete callback */ +3330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxHalfCpltCallback(hspi); +3332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_RxHalfCpltCallback(hspi); +3334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 60 + + +3337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI half transmit receive process complete callback. +3339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx half complete callback */ +3348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxHalfCpltCallback(hspi); +3350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxRxHalfCpltCallback(hspi); +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI communication error callback. +3357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAError(DMA_HandleTypeDef *hdma) +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Stop the disable DMA transfer on SPI side */ +3366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); +3367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); +3369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +3370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +3375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI communication abort callback, when initiated by HAL services on Error +3380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * (To be called at end of DMA Abort procedure following error occurrence). +3381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma DMA handle. +3382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +3385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +3388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +3389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else + ARM GAS /tmp/ccywxtmH.s page 61 + + +3394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +3395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI Tx communication abort callback, when initiated by user +3400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * (To be called at end of DMA Tx Abort procedure following user abort request). +3401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note When this callback is executed, User Abort complete call back is called only if no +3402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * Abort still ongoing for Rx DMA Handle. +3403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma DMA handle. +3404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; +3411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Tx DMA Request */ +3413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +3414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) +3416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +3418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +3421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +3422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL +3425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +3427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if an Abort process is still ongoing */ +3430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) +3431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx->XferAbortCallback != NULL) +3433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete +3439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +3440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; +3441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check no error during Abort procedure */ +3443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) +3444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset errorCode */ +3446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +3447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear the Error flags in the SR register */ +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + ARM GAS /tmp/ccywxtmH.s page 62 + + +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); +3452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restore hspi->State to Ready */ +3454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +3455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Abort complete callback */ +3457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback(hspi); +3459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_AbortCpltCallback(hspi); +3461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI Rx communication abort callback, when initiated by user +3466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * (To be called at end of DMA Rx Abort procedure following user abort request). +3467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note When this callback is executed, User Abort complete call back is called only if no +3468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * Abort still ongoing for Tx DMA Handle. +3469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma DMA handle. +3470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +3473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati +3475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +3477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +3478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; +3480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Rx DMA Request */ +3482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); +3483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) +3486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +3488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +3491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL +3492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; +3494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if an Abort process is still ongoing */ +3497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) +3498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx->XferAbortCallback != NULL) +3500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete +3506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; +3507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + ARM GAS /tmp/ccywxtmH.s page 63 + + +3508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check no error during Abort procedure */ +3510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) +3511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset errorCode */ +3513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; +3514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear the Error flags in the SR register */ +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restore hspi->State to Ready */ +3521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Abort complete callback */ +3524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback(hspi); +3526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_AbortCpltCallback(hspi); +3528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. +3533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in packing mode */ +3540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount > 1U) +3541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); +3544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; +3545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 1U) +3546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8bit */ +3548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +3549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in 8 Bit mode */ +3552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); +3555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; +3556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +3557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check end of the reception */ +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) +3561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 64 + + +3565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +3566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_2linesRxISR_8BITCRC; +3567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ +3572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); +3573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) +3575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); +3577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. +3584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +3589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t * ptmpreg8; +3591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +3592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +3594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +3595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC to flush Data Register */ +3596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize--; +3601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check end of the reception */ +3603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->CRCSize == 0U) +3604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ +3606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) +3609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); +3611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. +3618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + ARM GAS /tmp/ccywxtmH.s page 65 + + +3622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in packing Bit mode */ +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount >= 2U) +3626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); +3629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; +3630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 8 Bit mode */ +3632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); +3635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; +3636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; +3637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transmission */ +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) +3641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set CRC Next Bit to send CRC */ +3646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE interrupt */ +3648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); +3649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE interrupt */ +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); +3655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) +3657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); +3659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. +3665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +3670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in 16 Bit mode */ +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); +3673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); +3674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +3675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) +3677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + ARM GAS /tmp/ccywxtmH.s page 66 + + +3679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_2linesRxISR_16BITCRC; +3682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE interrupt */ +3687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); +3688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) +3690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); +3692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. +3699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +3704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +3706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC to flush Data Register */ +3708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +3709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +3711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE interrupt */ +3713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); +3714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); +3716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. +3721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +3726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); +3730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; +3731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) +3734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + ARM GAS /tmp/ccywxtmH.s page 67 + + +3736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set CRC Next Bit to send CRC */ +3739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE interrupt */ +3741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); +3742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE interrupt */ +3747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); +3748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) +3750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); +3752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the CRC 8-bit receive in Interrupt context. +3759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +3764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t * ptmpreg8; +3766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +3767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +3769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +3770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC to flush Data Register */ +3771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize--; +3776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->CRCSize == 0U) +3778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRx_ISR(hspi); +3780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the receive 8-bit in Interrupt context. +3786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + ARM GAS /tmp/ccywxtmH.s page 68 + + +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; +3794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +3795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +3799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_8BITCRC; +3810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRx_ISR(hspi); +3814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the CRC 16-bit receive in Interrupt context. +3820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +3825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +3827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC to flush Data Register */ +3829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +3830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +3832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ +3834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); +3835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRx_ISR(hspi); +3837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the 16-bit receive in Interrupt context. +3842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +3847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); +3849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + ARM GAS /tmp/ccywxtmH.s page 69 + + +3850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +3851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +3855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) +3861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_16BITCRC; +3866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRx_ISR(hspi); +3870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the data 8-bit transmit in Interrupt mode. +3875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +3880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); +3882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; +3884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) +3886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseTx_ISR(hspi); +3895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the data 16-bit transmit in Interrupt mode. +3900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +3905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + ARM GAS /tmp/ccywxtmH.s page 70 + + +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); +3909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) +3912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseTx_ISR(hspi); +3921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle SPI Communication Timeout. +3926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Flag SPI flag to check +3929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param State flag state to check +3930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +3931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Tickstart tick start value +3932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +3933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, Flag +3935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout, uint32_t Tickstart) +3936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 29 .loc 1 3936 1 view -0 + 30 .cfi_startproc + 31 @ args = 4, pretend = 0, frame = 8 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 .loc 1 3936 1 is_stmt 0 view .LVU1 + 34 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 35 .cfi_def_cfa_offset 32 + 36 .cfi_offset 4, -32 + 37 .cfi_offset 5, -28 + 38 .cfi_offset 6, -24 + 39 .cfi_offset 7, -20 + 40 .cfi_offset 8, -16 + 41 .cfi_offset 9, -12 + 42 .cfi_offset 10, -8 + 43 .cfi_offset 14, -4 + 44 0004 82B0 sub sp, sp, #8 + 45 .cfi_def_cfa_offset 40 + 46 0006 0546 mov r5, r0 + 47 0008 8846 mov r8, r1 + 48 000a 1746 mov r7, r2 + 49 000c 1E46 mov r6, r3 +3937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; + 50 .loc 1 3937 3 is_stmt 1 view .LVU2 +3938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_timeout; + 51 .loc 1 3938 3 view .LVU3 +3939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_tickstart; + 52 .loc 1 3939 3 view .LVU4 + ARM GAS /tmp/ccywxtmH.s page 71 + + +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Adjust Timeout value in case of end of transfer */ +3942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 53 .loc 1 3942 3 view .LVU5 + 54 .loc 1 3942 30 is_stmt 0 view .LVU6 + 55 000e FFF7FEFF bl HAL_GetTick + 56 .LVL1: + 57 .loc 1 3942 44 view .LVU7 + 58 0012 0A9B ldr r3, [sp, #40] + 59 0014 1B1A subs r3, r3, r0 + 60 .loc 1 3942 17 view .LVU8 + 61 0016 03EB0609 add r9, r3, r6 + 62 .LVL2: +3943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_tickstart = HAL_GetTick(); + 63 .loc 1 3943 3 is_stmt 1 view .LVU9 + 64 .loc 1 3943 19 is_stmt 0 view .LVU10 + 65 001a FFF7FEFF bl HAL_GetTick + 66 .LVL3: + 67 001e 8246 mov r10, r0 + 68 .LVL4: +3944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ +3946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 69 .loc 1 3946 3 is_stmt 1 view .LVU11 + 70 .loc 1 3946 43 is_stmt 0 view .LVU12 + 71 0020 284B ldr r3, .L16 + 72 0022 1B68 ldr r3, [r3] + 73 .loc 1 3946 50 view .LVU13 + 74 0024 C3F3CB33 ubfx r3, r3, #15, #12 + 75 .loc 1 3946 23 view .LVU14 + 76 0028 09FB03F3 mul r3, r9, r3 + 77 .loc 1 3946 9 view .LVU15 + 78 002c 0193 str r3, [sp, #4] +3947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 79 .loc 1 3948 3 is_stmt 1 view .LVU16 + 80 .LVL5: + 81 .L3: + 82 .loc 1 3948 57 view .LVU17 + 83 .loc 1 3948 11 is_stmt 0 view .LVU18 + 84 002e 2B68 ldr r3, [r5] + 85 0030 9C68 ldr r4, [r3, #8] + 86 .loc 1 3948 48 view .LVU19 + 87 0032 38EA0404 bics r4, r8, r4 + 88 0036 0CBF ite eq + 89 0038 0123 moveq r3, #1 + 90 003a 0023 movne r3, #0 + 91 .loc 1 3948 57 view .LVU20 + 92 003c BB42 cmp r3, r7 + 93 003e 3DD0 beq .L12 +3949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (Timeout != HAL_MAX_DELAY) + 94 .loc 1 3950 5 is_stmt 1 view .LVU21 + 95 .loc 1 3950 8 is_stmt 0 view .LVU22 + 96 0040 B6F1FF3F cmp r6, #-1 + 97 0044 F3D0 beq .L3 +3951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 72 + + +3952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 98 .loc 1 3952 7 is_stmt 1 view .LVU23 + 99 .loc 1 3952 13 is_stmt 0 view .LVU24 + 100 0046 FFF7FEFF bl HAL_GetTick + 101 .LVL6: + 102 .loc 1 3952 27 view .LVU25 + 103 004a A0EB0A00 sub r0, r0, r10 + 104 .loc 1 3952 10 view .LVU26 + 105 004e 4845 cmp r0, r9 + 106 0050 07D2 bcs .L13 +3953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI and reset the CRC: the CRC value should be cleared +3955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** on both master and slave sides in order to resynchronize the master +3956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and slave for their respective CRC calculation */ +3957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); +3960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN +3963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI peripheral */ +3965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +3966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +3972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +3975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +3978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; +3980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop proced +3982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if(count == 0U) + 107 .loc 1 3982 7 is_stmt 1 view .LVU27 + 108 .loc 1 3982 16 is_stmt 0 view .LVU28 + 109 0052 019A ldr r2, [sp, #4] + 110 .loc 1 3982 9 view .LVU29 + 111 0054 02B1 cbz r2, .L9 + 112 0056 4A46 mov r2, r9 + 113 .L9: + 114 .LVL7: +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_timeout = 0U; +3985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 115 .loc 1 3986 7 is_stmt 1 view .LVU30 + 116 .loc 1 3986 12 is_stmt 0 view .LVU31 + 117 0058 019B ldr r3, [sp, #4] + 118 005a 013B subs r3, r3, #1 + 119 005c 0193 str r3, [sp, #4] + ARM GAS /tmp/ccywxtmH.s page 73 + + + 120 005e 9146 mov r9, r2 + 121 0060 E5E7 b .L3 + 122 .LVL8: + 123 .L13: +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 124 .loc 1 3959 9 is_stmt 1 view .LVU32 + 125 0062 2A68 ldr r2, [r5] + 126 0064 5368 ldr r3, [r2, #4] + 127 0066 23F0E003 bic r3, r3, #224 + 128 006a 5360 str r3, [r2, #4] +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 129 .loc 1 3961 9 view .LVU33 +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 130 .loc 1 3961 24 is_stmt 0 view .LVU34 + 131 006c 6B68 ldr r3, [r5, #4] +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 132 .loc 1 3961 12 view .LVU35 + 133 006e B3F5827F cmp r3, #260 + 134 0072 0BD0 beq .L14 + 135 .L5: +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 136 .loc 1 3969 9 is_stmt 1 view .LVU36 +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 137 .loc 1 3969 23 is_stmt 0 view .LVU37 + 138 0074 AB6A ldr r3, [r5, #40] +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 139 .loc 1 3969 12 view .LVU38 + 140 0076 B3F5005F cmp r3, #8192 + 141 007a 14D0 beq .L15 + 142 .L7: +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 143 .loc 1 3971 11 is_stmt 1 discriminator 1 view .LVU39 +3974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 144 .loc 1 3974 9 discriminator 1 view .LVU40 +3974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 145 .loc 1 3974 21 is_stmt 0 discriminator 1 view .LVU41 + 146 007c 0123 movs r3, #1 + 147 007e 85F85D30 strb r3, [r5, #93] +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 148 .loc 1 3977 9 is_stmt 1 discriminator 1 view .LVU42 +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 149 .loc 1 3977 9 discriminator 1 view .LVU43 + 150 0082 0023 movs r3, #0 + 151 0084 85F85C30 strb r3, [r5, #92] +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 152 .loc 1 3977 9 discriminator 1 view .LVU44 +3979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 153 .loc 1 3979 9 discriminator 1 view .LVU45 +3979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 154 .loc 1 3979 16 is_stmt 0 discriminator 1 view .LVU46 + 155 0088 0320 movs r0, #3 + 156 008a 18E0 b .L8 + 157 .L14: +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 158 .loc 1 3961 65 discriminator 1 view .LVU47 + 159 008c AB68 ldr r3, [r5, #8] +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + ARM GAS /tmp/ccywxtmH.s page 74 + + + 160 .loc 1 3961 50 discriminator 1 view .LVU48 + 161 008e B3F5004F cmp r3, #32768 + 162 0092 02D0 beq .L6 +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 163 .loc 1 3962 54 view .LVU49 + 164 0094 B3F5806F cmp r3, #1024 + 165 0098 ECD1 bne .L5 + 166 .L6: +3965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 167 .loc 1 3965 11 is_stmt 1 view .LVU50 + 168 009a 2A68 ldr r2, [r5] + 169 009c 1368 ldr r3, [r2] + 170 009e 23F04003 bic r3, r3, #64 + 171 00a2 1360 str r3, [r2] + 172 00a4 E6E7 b .L5 + 173 .L15: +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 174 .loc 1 3971 11 view .LVU51 +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 175 .loc 1 3971 11 view .LVU52 + 176 00a6 2A68 ldr r2, [r5] + 177 00a8 1368 ldr r3, [r2] + 178 00aa 23F40053 bic r3, r3, #8192 + 179 00ae 1360 str r3, [r2] +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 180 .loc 1 3971 11 view .LVU53 + 181 00b0 2A68 ldr r2, [r5] + 182 00b2 1368 ldr r3, [r2] + 183 00b4 43F40053 orr r3, r3, #8192 + 184 00b8 1360 str r3, [r2] + 185 00ba DFE7 b .L7 + 186 .L12: +3987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 187 .loc 1 3990 10 is_stmt 0 view .LVU54 + 188 00bc 0020 movs r0, #0 + 189 .L8: +3991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 190 .loc 1 3991 1 view .LVU55 + 191 00be 02B0 add sp, sp, #8 + 192 .cfi_def_cfa_offset 32 + 193 @ sp needed + 194 00c0 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 195 .LVL9: + 196 .L17: + 197 .loc 1 3991 1 view .LVU56 + 198 .align 2 + 199 .L16: + 200 00c4 00000000 .word SystemCoreClock + 201 .cfi_endproc + 202 .LFE177: + 204 .section .text.SPI_WaitFifoStateUntilTimeout,"ax",%progbits + 205 .align 1 + 206 .syntax unified + 207 .thumb + ARM GAS /tmp/ccywxtmH.s page 75 + + + 208 .thumb_func + 210 SPI_WaitFifoStateUntilTimeout: + 211 .LVL10: + 212 .LFB178: +3992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle SPI FIFO Communication Timeout. +3995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Fifo Fifo to check +3998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param State Fifo state to check +3999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +4000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Tickstart tick start value +4001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +4002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint +4004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout, uint32_t Tickstart) +4005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 213 .loc 1 4005 1 is_stmt 1 view -0 + 214 .cfi_startproc + 215 @ args = 4, pretend = 0, frame = 8 + 216 @ frame_needed = 0, uses_anonymous_args = 0 + 217 .loc 1 4005 1 is_stmt 0 view .LVU58 + 218 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr} + 219 .cfi_def_cfa_offset 32 + 220 .cfi_offset 4, -32 + 221 .cfi_offset 5, -28 + 222 .cfi_offset 6, -24 + 223 .cfi_offset 7, -20 + 224 .cfi_offset 8, -16 + 225 .cfi_offset 9, -12 + 226 .cfi_offset 10, -8 + 227 .cfi_offset 14, -4 + 228 0004 82B0 sub sp, sp, #8 + 229 .cfi_def_cfa_offset 40 + 230 0006 0646 mov r6, r0 + 231 0008 0C46 mov r4, r1 + 232 000a 1546 mov r5, r2 + 233 000c 1F46 mov r7, r3 +4006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; + 234 .loc 1 4006 3 is_stmt 1 view .LVU59 +4007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_timeout; + 235 .loc 1 4007 3 view .LVU60 +4008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_tickstart; + 236 .loc 1 4008 3 view .LVU61 +4009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t * ptmpreg8; + 237 .loc 1 4009 3 view .LVU62 +4010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; + 238 .loc 1 4010 3 view .LVU63 + 239 .loc 1 4010 17 is_stmt 0 view .LVU64 + 240 000e 0023 movs r3, #0 + 241 .LVL11: + 242 .loc 1 4010 17 view .LVU65 + 243 0010 8DF80330 strb r3, [sp, #3] +4011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Adjust Timeout value in case of end of transfer */ +4013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + ARM GAS /tmp/ccywxtmH.s page 76 + + + 244 .loc 1 4013 3 is_stmt 1 view .LVU66 + 245 .loc 1 4013 28 is_stmt 0 view .LVU67 + 246 0014 FFF7FEFF bl HAL_GetTick + 247 .LVL12: + 248 .loc 1 4013 42 view .LVU68 + 249 0018 0A9B ldr r3, [sp, #40] + 250 001a 1B1A subs r3, r3, r0 + 251 .loc 1 4013 15 view .LVU69 + 252 001c 03EB0708 add r8, r3, r7 + 253 .LVL13: +4014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_tickstart = HAL_GetTick(); + 254 .loc 1 4014 3 is_stmt 1 view .LVU70 + 255 .loc 1 4014 19 is_stmt 0 view .LVU71 + 256 0020 FFF7FEFF bl HAL_GetTick + 257 .LVL14: + 258 0024 8146 mov r9, r0 + 259 .LVL15: +4015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +4017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + 260 .loc 1 4017 3 is_stmt 1 view .LVU72 + 261 .loc 1 4017 35 is_stmt 0 view .LVU73 + 262 0026 D6F800A0 ldr r10, [r6] + 263 .LVL16: +4018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + 264 .loc 1 4020 3 is_stmt 1 view .LVU74 + 265 .loc 1 4020 43 is_stmt 0 view .LVU75 + 266 002a 304B ldr r3, .L35 + 267 002c 1B68 ldr r3, [r3] + 268 002e 03EB8303 add r3, r3, r3, lsl #2 + 269 0032 C3EBC303 rsb r3, r3, r3, lsl #3 + 270 .loc 1 4020 50 view .LVU76 + 271 0036 1B0D lsrs r3, r3, #20 + 272 .loc 1 4020 23 view .LVU77 + 273 0038 08FB03F3 mul r3, r8, r3 + 274 .loc 1 4020 9 view .LVU78 + 275 003c 0193 str r3, [sp, #4] +4021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while ((hspi->Instance->SR & Fifo) != State) + 276 .loc 1 4022 3 is_stmt 1 view .LVU79 + 277 .loc 1 4022 9 is_stmt 0 view .LVU80 + 278 003e 02E0 b .L21 + 279 .LVL17: + 280 .L20: +4023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) +4025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Flush Data Register by a blank read */ +4027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +4028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +4029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +4030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (Timeout != HAL_MAX_DELAY) + 281 .loc 1 4032 5 is_stmt 1 view .LVU81 + ARM GAS /tmp/ccywxtmH.s page 77 + + + 282 .loc 1 4032 8 is_stmt 0 view .LVU82 + 283 0040 B7F1FF3F cmp r7, #-1 + 284 0044 12D1 bne .L30 + 285 .L21: +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 286 .loc 1 4022 38 is_stmt 1 view .LVU83 +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 287 .loc 1 4022 15 is_stmt 0 view .LVU84 + 288 0046 3368 ldr r3, [r6] +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 289 .loc 1 4022 25 view .LVU85 + 290 0048 9B68 ldr r3, [r3, #8] +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 291 .loc 1 4022 30 view .LVU86 + 292 004a 03EA040C and ip, r3, r4 +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 293 .loc 1 4022 38 view .LVU87 + 294 004e AC45 cmp ip, r5 + 295 0050 47D0 beq .L31 +4024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 296 .loc 1 4024 5 is_stmt 1 view .LVU88 +4024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 297 .loc 1 4024 8 is_stmt 0 view .LVU89 + 298 0052 B4F5C06F cmp r4, #1536 + 299 0056 F3D1 bne .L20 +4024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 300 .loc 1 4024 32 discriminator 1 view .LVU90 + 301 0058 002D cmp r5, #0 + 302 005a F1D1 bne .L20 +4027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ + 303 .loc 1 4027 7 is_stmt 1 view .LVU91 +4027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ + 304 .loc 1 4027 17 is_stmt 0 view .LVU92 + 305 005c 9AF80C30 ldrb r3, [r10, #12] @ zero_extendqisi2 + 306 0060 DBB2 uxtb r3, r3 +4027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ + 307 .loc 1 4027 15 view .LVU93 + 308 0062 8DF80330 strb r3, [sp, #3] +4029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 309 .loc 1 4029 7 is_stmt 1 view .LVU94 + 310 0066 9DF80330 ldrb r3, [sp, #3] @ zero_extendqisi2 + 311 006a E9E7 b .L20 + 312 .L30: +4033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 313 .loc 1 4034 7 view .LVU95 + 314 .loc 1 4034 13 is_stmt 0 view .LVU96 + 315 006c FFF7FEFF bl HAL_GetTick + 316 .LVL18: + 317 .loc 1 4034 27 view .LVU97 + 318 0070 A0EB0900 sub r0, r0, r9 + 319 .loc 1 4034 10 view .LVU98 + 320 0074 4045 cmp r0, r8 + 321 0076 07D2 bcs .L32 +4035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI and reset the CRC: the CRC value should be cleared +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** on both master and slave sides in order to resynchronize the master + ARM GAS /tmp/ccywxtmH.s page 78 + + +4038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and slave for their respective CRC calculation */ +4039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ +4041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); +4042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) +4044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN +4045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI peripheral */ +4047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +4048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +4052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +4054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +4059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); +4060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; +4062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop proced +4064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if(count == 0U) + 322 .loc 1 4064 7 is_stmt 1 view .LVU99 + 323 .loc 1 4064 16 is_stmt 0 view .LVU100 + 324 0078 019A ldr r2, [sp, #4] + 325 .loc 1 4064 9 view .LVU101 + 326 007a 02B1 cbz r2, .L27 + 327 007c 4246 mov r2, r8 + 328 .L27: + 329 .LVL19: +4065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_timeout = 0U; +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 330 .loc 1 4068 7 is_stmt 1 view .LVU102 + 331 .loc 1 4068 12 is_stmt 0 view .LVU103 + 332 007e 019B ldr r3, [sp, #4] + 333 0080 013B subs r3, r3, #1 + 334 0082 0193 str r3, [sp, #4] + 335 0084 9046 mov r8, r2 + 336 0086 DEE7 b .L21 + 337 .LVL20: + 338 .L32: +4041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 339 .loc 1 4041 9 is_stmt 1 view .LVU104 + 340 0088 3268 ldr r2, [r6] + 341 008a 5368 ldr r3, [r2, #4] + 342 008c 23F0E003 bic r3, r3, #224 + 343 0090 5360 str r3, [r2, #4] +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 344 .loc 1 4043 9 view .LVU105 +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + ARM GAS /tmp/ccywxtmH.s page 79 + + + 345 .loc 1 4043 24 is_stmt 0 view .LVU106 + 346 0092 7368 ldr r3, [r6, #4] +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 347 .loc 1 4043 12 view .LVU107 + 348 0094 B3F5827F cmp r3, #260 + 349 0098 0BD0 beq .L33 + 350 .L23: +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 351 .loc 1 4051 9 is_stmt 1 view .LVU108 +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 352 .loc 1 4051 23 is_stmt 0 view .LVU109 + 353 009a B36A ldr r3, [r6, #40] +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 354 .loc 1 4051 12 view .LVU110 + 355 009c B3F5005F cmp r3, #8192 + 356 00a0 14D0 beq .L34 + 357 .L25: +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 358 .loc 1 4053 11 is_stmt 1 discriminator 1 view .LVU111 +4056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 359 .loc 1 4056 9 discriminator 1 view .LVU112 +4056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 360 .loc 1 4056 21 is_stmt 0 discriminator 1 view .LVU113 + 361 00a2 0123 movs r3, #1 + 362 00a4 86F85D30 strb r3, [r6, #93] +4059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 363 .loc 1 4059 9 is_stmt 1 discriminator 1 view .LVU114 +4059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 364 .loc 1 4059 9 discriminator 1 view .LVU115 + 365 00a8 0023 movs r3, #0 + 366 00aa 86F85C30 strb r3, [r6, #92] +4059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 367 .loc 1 4059 9 discriminator 1 view .LVU116 +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 368 .loc 1 4061 9 discriminator 1 view .LVU117 +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 369 .loc 1 4061 16 is_stmt 0 discriminator 1 view .LVU118 + 370 00ae 0320 movs r0, #3 + 371 00b0 18E0 b .L26 + 372 .L33: +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 373 .loc 1 4043 65 discriminator 1 view .LVU119 + 374 00b2 B368 ldr r3, [r6, #8] +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 375 .loc 1 4043 50 discriminator 1 view .LVU120 + 376 00b4 B3F5004F cmp r3, #32768 + 377 00b8 02D0 beq .L24 +4044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 378 .loc 1 4044 54 view .LVU121 + 379 00ba B3F5806F cmp r3, #1024 + 380 00be ECD1 bne .L23 + 381 .L24: +4047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 382 .loc 1 4047 11 is_stmt 1 view .LVU122 + 383 00c0 3268 ldr r2, [r6] + 384 00c2 1368 ldr r3, [r2] + 385 00c4 23F04003 bic r3, r3, #64 + ARM GAS /tmp/ccywxtmH.s page 80 + + + 386 00c8 1360 str r3, [r2] + 387 00ca E6E7 b .L23 + 388 .L34: +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 389 .loc 1 4053 11 view .LVU123 +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 390 .loc 1 4053 11 view .LVU124 + 391 00cc 3268 ldr r2, [r6] + 392 00ce 1368 ldr r3, [r2] + 393 00d0 23F40053 bic r3, r3, #8192 + 394 00d4 1360 str r3, [r2] +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 395 .loc 1 4053 11 view .LVU125 + 396 00d6 3268 ldr r2, [r6] + 397 00d8 1368 ldr r3, [r2] + 398 00da 43F40053 orr r3, r3, #8192 + 399 00de 1360 str r3, [r2] + 400 00e0 DFE7 b .L25 + 401 .L31: +4069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 402 .loc 1 4072 10 is_stmt 0 view .LVU126 + 403 00e2 0020 movs r0, #0 + 404 .L26: +4073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 405 .loc 1 4073 1 view .LVU127 + 406 00e4 02B0 add sp, sp, #8 + 407 .cfi_def_cfa_offset 32 + 408 @ sp needed + 409 00e6 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc} + 410 .LVL21: + 411 .L36: + 412 .loc 1 4073 1 view .LVU128 + 413 00ea 00BF .align 2 + 414 .L35: + 415 00ec 00000000 .word SystemCoreClock + 416 .cfi_endproc + 417 .LFE178: + 419 .section .text.SPI_EndRxTxTransaction,"ax",%progbits + 420 .align 1 + 421 .syntax unified + 422 .thumb + 423 .thumb_func + 425 SPI_EndRxTxTransaction: + 426 .LVL22: + 427 .LFB180: +4074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the check of the RX transaction complete. +4077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +4080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Tickstart tick start value +4081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + ARM GAS /tmp/ccywxtmH.s page 81 + + +4083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t +4084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) +4086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO +4087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI peripheral */ +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); +4090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) +4094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; +4097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) +4100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO +4101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +4103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != +4104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +4106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; +4107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the check of the RXTX or TX transaction complete. +4114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi SPI handle +4115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +4116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Tickstart tick start value +4117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +4118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t +4120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 428 .loc 1 4120 1 is_stmt 1 view -0 + 429 .cfi_startproc + 430 @ args = 0, pretend = 0, frame = 0 + 431 @ frame_needed = 0, uses_anonymous_args = 0 + 432 .loc 1 4120 1 is_stmt 0 view .LVU130 + 433 0000 70B5 push {r4, r5, r6, lr} + 434 .cfi_def_cfa_offset 16 + 435 .cfi_offset 4, -16 + 436 .cfi_offset 5, -12 + 437 .cfi_offset 6, -8 + 438 .cfi_offset 14, -4 + 439 0002 82B0 sub sp, sp, #8 + 440 .cfi_def_cfa_offset 24 + 441 0004 0446 mov r4, r0 + 442 0006 0D46 mov r5, r1 + 443 0008 1646 mov r6, r2 +4121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control if the TX fifo is empty */ +4122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != H + 444 .loc 1 4122 3 is_stmt 1 view .LVU131 + ARM GAS /tmp/ccywxtmH.s page 82 + + + 445 .loc 1 4122 7 is_stmt 0 view .LVU132 + 446 000a 0092 str r2, [sp] + 447 000c 0B46 mov r3, r1 + 448 000e 0022 movs r2, #0 + 449 .LVL23: + 450 .loc 1 4122 7 view .LVU133 + 451 0010 4FF4C051 mov r1, #6144 + 452 .LVL24: + 453 .loc 1 4122 7 view .LVU134 + 454 0014 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 455 .LVL25: + 456 .loc 1 4122 6 view .LVU135 + 457 0018 B0B9 cbnz r0, .L42 +4123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +4125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; +4126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +4129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 458 .loc 1 4129 3 is_stmt 1 view .LVU136 + 459 .loc 1 4129 7 is_stmt 0 view .LVU137 + 460 001a 0096 str r6, [sp] + 461 001c 2B46 mov r3, r5 + 462 001e 0022 movs r2, #0 + 463 0020 8021 movs r1, #128 + 464 0022 2046 mov r0, r4 + 465 0024 FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 466 .LVL26: + 467 .loc 1 4129 6 view .LVU138 + 468 0028 A8B9 cbnz r0, .L43 +4130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +4132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; +4133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control if the RX fifo is empty */ +4136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != H + 469 .loc 1 4136 3 is_stmt 1 view .LVU139 + 470 .loc 1 4136 7 is_stmt 0 view .LVU140 + 471 002a 0096 str r6, [sp] + 472 002c 2B46 mov r3, r5 + 473 002e 0022 movs r2, #0 + 474 0030 4FF4C061 mov r1, #1536 + 475 0034 2046 mov r0, r4 + 476 0036 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 477 .LVL27: + 478 .loc 1 4136 6 view .LVU141 + 479 003a 50B1 cbz r0, .L39 +4137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 480 .loc 1 4138 5 is_stmt 1 view .LVU142 + 481 003c 236E ldr r3, [r4, #96] + 482 003e 43F02003 orr r3, r3, #32 + 483 0042 2366 str r3, [r4, #96] +4139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 484 .loc 1 4139 5 view .LVU143 + ARM GAS /tmp/ccywxtmH.s page 83 + + + 485 .loc 1 4139 12 is_stmt 0 view .LVU144 + 486 0044 0320 movs r0, #3 + 487 0046 04E0 b .L39 + 488 .L42: +4124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 489 .loc 1 4124 5 is_stmt 1 view .LVU145 + 490 0048 236E ldr r3, [r4, #96] + 491 004a 43F02003 orr r3, r3, #32 + 492 004e 2366 str r3, [r4, #96] +4125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 493 .loc 1 4125 5 view .LVU146 +4125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 494 .loc 1 4125 12 is_stmt 0 view .LVU147 + 495 0050 0320 movs r0, #3 + 496 .L39: +4140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; +4143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 497 .loc 1 4143 1 view .LVU148 + 498 0052 02B0 add sp, sp, #8 + 499 .cfi_remember_state + 500 .cfi_def_cfa_offset 16 + 501 @ sp needed + 502 0054 70BD pop {r4, r5, r6, pc} + 503 .LVL28: + 504 .L43: + 505 .cfi_restore_state +4131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 506 .loc 1 4131 5 is_stmt 1 view .LVU149 + 507 0056 236E ldr r3, [r4, #96] + 508 0058 43F02003 orr r3, r3, #32 + 509 005c 2366 str r3, [r4, #96] +4132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 510 .loc 1 4132 5 view .LVU150 +4132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 511 .loc 1 4132 12 is_stmt 0 view .LVU151 + 512 005e 0320 movs r0, #3 + 513 0060 F7E7 b .L39 + 514 .cfi_endproc + 515 .LFE180: + 517 .section .text.SPI_EndRxTransaction,"ax",%progbits + 518 .align 1 + 519 .syntax unified + 520 .thumb + 521 .thumb_func + 523 SPI_EndRxTransaction: + 524 .LVL29: + 525 .LFB179: +4084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 526 .loc 1 4084 1 is_stmt 1 view -0 + 527 .cfi_startproc + 528 @ args = 0, pretend = 0, frame = 0 + 529 @ frame_needed = 0, uses_anonymous_args = 0 +4084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 530 .loc 1 4084 1 is_stmt 0 view .LVU153 + 531 0000 70B5 push {r4, r5, r6, lr} + ARM GAS /tmp/ccywxtmH.s page 84 + + + 532 .cfi_def_cfa_offset 16 + 533 .cfi_offset 4, -16 + 534 .cfi_offset 5, -12 + 535 .cfi_offset 6, -8 + 536 .cfi_offset 14, -4 + 537 0002 82B0 sub sp, sp, #8 + 538 .cfi_def_cfa_offset 24 + 539 0004 0446 mov r4, r0 + 540 0006 0D46 mov r5, r1 + 541 0008 1646 mov r6, r2 +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 542 .loc 1 4085 3 is_stmt 1 view .LVU154 +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 543 .loc 1 4085 18 is_stmt 0 view .LVU155 + 544 000a 4368 ldr r3, [r0, #4] +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 545 .loc 1 4085 6 view .LVU156 + 546 000c B3F5827F cmp r3, #260 + 547 0010 0DD0 beq .L51 + 548 .LVL30: + 549 .L45: +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 550 .loc 1 4093 3 is_stmt 1 view .LVU157 +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 551 .loc 1 4093 7 is_stmt 0 view .LVU158 + 552 0012 0096 str r6, [sp] + 553 0014 2B46 mov r3, r5 + 554 0016 0022 movs r2, #0 + 555 0018 8021 movs r1, #128 + 556 .LVL31: +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 557 .loc 1 4093 7 view .LVU159 + 558 001a 2046 mov r0, r4 + 559 .LVL32: +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 560 .loc 1 4093 7 view .LVU160 + 561 001c FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 562 .LVL33: +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 563 .loc 1 4093 6 view .LVU161 + 564 0020 90B9 cbnz r0, .L52 +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 565 .loc 1 4099 3 is_stmt 1 view .LVU162 +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 566 .loc 1 4099 18 is_stmt 0 view .LVU163 + 567 0022 6368 ldr r3, [r4, #4] +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 568 .loc 1 4099 6 view .LVU164 + 569 0024 B3F5827F cmp r3, #260 + 570 0028 14D0 beq .L53 + 571 .L48: +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 572 .loc 1 4110 1 view .LVU165 + 573 002a 02B0 add sp, sp, #8 + 574 .cfi_remember_state + 575 .cfi_def_cfa_offset 16 + 576 @ sp needed + ARM GAS /tmp/ccywxtmH.s page 85 + + + 577 002c 70BD pop {r4, r5, r6, pc} + 578 .LVL34: + 579 .L51: + 580 .cfi_restore_state +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 581 .loc 1 4085 59 discriminator 1 view .LVU166 + 582 002e 8368 ldr r3, [r0, #8] +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 583 .loc 1 4085 44 discriminator 1 view .LVU167 + 584 0030 B3F5004F cmp r3, #32768 + 585 0034 02D0 beq .L46 +4086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 586 .loc 1 4086 48 view .LVU168 + 587 0036 B3F5806F cmp r3, #1024 + 588 003a EAD1 bne .L45 + 589 .L46: +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 590 .loc 1 4089 5 is_stmt 1 view .LVU169 + 591 003c 2268 ldr r2, [r4] + 592 .LVL35: +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 593 .loc 1 4089 5 is_stmt 0 view .LVU170 + 594 003e 1368 ldr r3, [r2] + 595 0040 23F04003 bic r3, r3, #64 + 596 0044 1360 str r3, [r2] + 597 0046 E4E7 b .L45 + 598 .LVL36: + 599 .L52: +4095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 600 .loc 1 4095 5 is_stmt 1 view .LVU171 + 601 0048 236E ldr r3, [r4, #96] + 602 004a 43F02003 orr r3, r3, #32 + 603 004e 2366 str r3, [r4, #96] +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 604 .loc 1 4096 5 view .LVU172 +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 605 .loc 1 4096 12 is_stmt 0 view .LVU173 + 606 0050 0320 movs r0, #3 + 607 0052 EAE7 b .L48 + 608 .L53: +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 609 .loc 1 4099 59 discriminator 1 view .LVU174 + 610 0054 A368 ldr r3, [r4, #8] +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 611 .loc 1 4099 44 discriminator 1 view .LVU175 + 612 0056 B3F5004F cmp r3, #32768 + 613 005a 02D0 beq .L49 +4100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 614 .loc 1 4100 48 view .LVU176 + 615 005c B3F5806F cmp r3, #1024 + 616 0060 E3D1 bne .L48 + 617 .L49: +4103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 618 .loc 1 4103 5 is_stmt 1 view .LVU177 +4103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 619 .loc 1 4103 9 is_stmt 0 view .LVU178 + 620 0062 0096 str r6, [sp] + ARM GAS /tmp/ccywxtmH.s page 86 + + + 621 0064 2B46 mov r3, r5 + 622 0066 0022 movs r2, #0 + 623 0068 4FF4C061 mov r1, #1536 + 624 006c 2046 mov r0, r4 + 625 006e FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 626 .LVL37: +4103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 627 .loc 1 4103 8 view .LVU179 + 628 0072 0028 cmp r0, #0 + 629 0074 D9D0 beq .L48 +4105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 630 .loc 1 4105 7 is_stmt 1 view .LVU180 + 631 0076 236E ldr r3, [r4, #96] + 632 0078 43F02003 orr r3, r3, #32 + 633 007c 2366 str r3, [r4, #96] +4106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 634 .loc 1 4106 7 view .LVU181 +4106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 635 .loc 1 4106 14 is_stmt 0 view .LVU182 + 636 007e 0320 movs r0, #3 + 637 0080 D3E7 b .L48 + 638 .cfi_endproc + 639 .LFE179: + 641 .section .text.SPI_AbortRx_ISR,"ax",%progbits + 642 .align 1 + 643 .syntax unified + 644 .thumb + 645 .thumb_func + 647 SPI_AbortRx_ISR: + 648 .LVL38: + 649 .LFB184: +4144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the end of the RXTX transaction. +4147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +4150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +4152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +4154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management */ +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); +4157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable ERR interrupt */ +4159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); +4160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) +4163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +4168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +4169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + ARM GAS /tmp/ccywxtmH.s page 87 + + +4170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +4173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +4174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +4184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) +4185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State == HAL_SPI_STATE_BUSY_RX) +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ +4190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback(hspi); +4192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); +4194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx complete callback */ +4200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback(hspi); +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); +4204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +4218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the end of the RX transaction. +4224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None + ARM GAS /tmp/ccywxtmH.s page 88 + + +4227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ +4231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); +4232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) +4235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +4237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +4241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +4242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +4243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +4245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +4246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +4256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) +4257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ +4259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback(hspi); +4261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); +4263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +4275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the end of the TX transaction. +4281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None + ARM GAS /tmp/ccywxtmH.s page 89 + + +4284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +4286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +4288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +4290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); +4291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE and ERR interrupt */ +4293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); +4294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); +4299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear overrun flag in 2 Lines communication mode because received is not read */ +4302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_2LINES) +4303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); +4305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) +4309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ +4320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback(hspi); +4322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxCpltCallback(hspi); +4324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle abort a Rx transaction. +4330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +4333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +4335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 650 .loc 1 4335 1 is_stmt 1 view -0 + 651 .cfi_startproc + 652 @ args = 0, pretend = 0, frame = 8 + 653 @ frame_needed = 0, uses_anonymous_args = 0 + 654 .loc 1 4335 1 is_stmt 0 view .LVU184 + ARM GAS /tmp/ccywxtmH.s page 90 + + + 655 0000 10B5 push {r4, lr} + 656 .cfi_def_cfa_offset 8 + 657 .cfi_offset 4, -8 + 658 .cfi_offset 14, -4 + 659 0002 84B0 sub sp, sp, #16 + 660 .cfi_def_cfa_offset 24 + 661 0004 0446 mov r4, r0 +4336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; + 662 .loc 1 4336 3 is_stmt 1 view .LVU185 +4337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +4339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 663 .loc 1 4339 3 view .LVU186 + 664 0006 0268 ldr r2, [r0] + 665 0008 1368 ldr r3, [r2] + 666 000a 23F04003 bic r3, r3, #64 + 667 000e 1360 str r3, [r2] +4340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 668 .loc 1 4341 3 view .LVU187 + 669 .loc 1 4341 56 is_stmt 0 view .LVU188 + 670 0010 1D4B ldr r3, .L62 + 671 0012 1B68 ldr r3, [r3] + 672 0014 1D4A ldr r2, .L62+4 + 673 0016 A2FB0323 umull r2, r3, r2, r3 + 674 001a 5B0A lsrs r3, r3, #9 + 675 .loc 1 4341 31 view .LVU189 + 676 001c 6422 movs r2, #100 + 677 001e 02FB03F3 mul r3, r2, r3 + 678 .loc 1 4341 9 view .LVU190 + 679 0022 0393 str r3, [sp, #12] +4342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNEIE interrupt */ +4344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + 680 .loc 1 4344 3 is_stmt 1 view .LVU191 + 681 0024 0268 ldr r2, [r0] + 682 0026 5368 ldr r3, [r2, #4] + 683 0028 23F04003 bic r3, r3, #64 + 684 002c 5360 str r3, [r2, #4] + 685 .L57: +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check RXNEIE is disabled */ +4347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do + 686 .loc 1 4347 3 view .LVU192 +4348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 687 .loc 1 4349 5 view .LVU193 + 688 .loc 1 4349 15 is_stmt 0 view .LVU194 + 689 002e 039B ldr r3, [sp, #12] + 690 .loc 1 4349 8 view .LVU195 + 691 0030 43B1 cbz r3, .L61 +4350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); +4352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; +4353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 692 .loc 1 4354 5 is_stmt 1 view .LVU196 + ARM GAS /tmp/ccywxtmH.s page 91 + + + 693 .loc 1 4354 10 is_stmt 0 view .LVU197 + 694 0032 039B ldr r3, [sp, #12] + 695 0034 013B subs r3, r3, #1 + 696 0036 0393 str r3, [sp, #12] +4355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + 697 .loc 1 4355 12 is_stmt 1 view .LVU198 + 698 0038 2368 ldr r3, [r4] + 699 003a 5B68 ldr r3, [r3, #4] + 700 003c 13F0400F tst r3, #64 + 701 0040 F5D1 bne .L57 + 702 0042 03E0 b .L56 + 703 .L61: +4351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 704 .loc 1 4351 7 view .LVU199 + 705 0044 236E ldr r3, [r4, #96] + 706 0046 43F04003 orr r3, r3, #64 + 707 004a 2366 str r3, [r4, #96] +4352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 708 .loc 1 4352 7 view .LVU200 + 709 .L56: +4356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +4358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) + 710 .loc 1 4358 3 view .LVU201 + 711 .loc 1 4358 7 is_stmt 0 view .LVU202 + 712 004c FFF7FEFF bl HAL_GetTick + 713 .LVL39: + 714 .loc 1 4358 7 view .LVU203 + 715 0050 0090 str r0, [sp] + 716 0052 6423 movs r3, #100 + 717 0054 0022 movs r2, #0 + 718 0056 8021 movs r1, #128 + 719 0058 2046 mov r0, r4 + 720 005a FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 721 .LVL40: + 722 .loc 1 4358 6 view .LVU204 + 723 005e 08B1 cbz r0, .L58 +4359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 724 .loc 1 4360 5 is_stmt 1 view .LVU205 + 725 .loc 1 4360 21 is_stmt 0 view .LVU206 + 726 0060 4023 movs r3, #64 + 727 0062 2366 str r3, [r4, #96] + 728 .L58: +4361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +4364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL + 729 .loc 1 4364 3 is_stmt 1 view .LVU207 + 730 .loc 1 4364 7 is_stmt 0 view .LVU208 + 731 0064 FFF7FEFF bl HAL_GetTick + 732 .LVL41: + 733 0068 0090 str r0, [sp] + 734 006a 6423 movs r3, #100 + 735 006c 0022 movs r2, #0 + 736 006e 4FF4C061 mov r1, #1536 + 737 0072 2046 mov r0, r4 + ARM GAS /tmp/ccywxtmH.s page 92 + + + 738 0074 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 739 .LVL42: + 740 .loc 1 4364 6 view .LVU209 + 741 0078 08B1 cbz r0, .L59 +4365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 742 .loc 1 4366 5 is_stmt 1 view .LVU210 + 743 .loc 1 4366 21 is_stmt 0 view .LVU211 + 744 007a 4023 movs r3, #64 + 745 007c 2366 str r3, [r4, #96] + 746 .L59: +4367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_ABORT; + 747 .loc 1 4369 3 is_stmt 1 view .LVU212 + 748 .loc 1 4369 15 is_stmt 0 view .LVU213 + 749 007e 0723 movs r3, #7 + 750 0080 84F85D30 strb r3, [r4, #93] +4370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 751 .loc 1 4370 1 view .LVU214 + 752 0084 04B0 add sp, sp, #16 + 753 .cfi_def_cfa_offset 8 + 754 @ sp needed + 755 0086 10BD pop {r4, pc} + 756 .LVL43: + 757 .L63: + 758 .loc 1 4370 1 view .LVU215 + 759 .align 2 + 760 .L62: + 761 0088 00000000 .word SystemCoreClock + 762 008c F1197605 .word 91625969 + 763 .cfi_endproc + 764 .LFE184: + 766 .section .text.SPI_AbortTx_ISR,"ax",%progbits + 767 .align 1 + 768 .syntax unified + 769 .thumb + 770 .thumb_func + 772 SPI_AbortTx_ISR: + 773 .LVL44: + 774 .LFB185: +4371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle abort a Tx or Rx/Tx transaction. +4374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +4377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +4379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 775 .loc 1 4379 1 is_stmt 1 view -0 + 776 .cfi_startproc + 777 @ args = 0, pretend = 0, frame = 8 + 778 @ frame_needed = 0, uses_anonymous_args = 0 + 779 .loc 1 4379 1 is_stmt 0 view .LVU217 + 780 0000 10B5 push {r4, lr} + 781 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccywxtmH.s page 93 + + + 782 .cfi_offset 4, -8 + 783 .cfi_offset 14, -4 + 784 0002 84B0 sub sp, sp, #16 + 785 .cfi_def_cfa_offset 24 + 786 0004 0446 mov r4, r0 +4380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; + 787 .loc 1 4380 3 is_stmt 1 view .LVU218 +4381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 788 .loc 1 4382 3 view .LVU219 + 789 .loc 1 4382 56 is_stmt 0 view .LVU220 + 790 0006 384B ldr r3, .L78 + 791 0008 1B68 ldr r3, [r3] + 792 000a 384A ldr r2, .L78+4 + 793 000c A2FB0323 umull r2, r3, r2, r3 + 794 0010 5B0A lsrs r3, r3, #9 + 795 .loc 1 4382 31 view .LVU221 + 796 0012 6422 movs r2, #100 + 797 0014 02FB03F3 mul r3, r2, r3 + 798 .loc 1 4382 9 view .LVU222 + 799 0018 0393 str r3, [sp, #12] +4383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXEIE interrupt */ +4385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + 800 .loc 1 4385 3 is_stmt 1 view .LVU223 + 801 001a 0268 ldr r2, [r0] + 802 001c 5368 ldr r3, [r2, #4] + 803 001e 23F08003 bic r3, r3, #128 + 804 0022 5360 str r3, [r2, #4] + 805 .L67: +4386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check TXEIE is disabled */ +4388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do + 806 .loc 1 4388 3 view .LVU224 +4389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 807 .loc 1 4390 5 view .LVU225 + 808 .loc 1 4390 15 is_stmt 0 view .LVU226 + 809 0024 039B ldr r3, [sp, #12] + 810 .loc 1 4390 8 view .LVU227 + 811 0026 43B1 cbz r3, .L76 +4391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); +4393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; +4394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 812 .loc 1 4395 5 is_stmt 1 view .LVU228 + 813 .loc 1 4395 10 is_stmt 0 view .LVU229 + 814 0028 039B ldr r3, [sp, #12] + 815 002a 013B subs r3, r3, #1 + 816 002c 0393 str r3, [sp, #12] +4396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + 817 .loc 1 4396 12 is_stmt 1 view .LVU230 + 818 002e 2368 ldr r3, [r4] + 819 0030 5B68 ldr r3, [r3, #4] + 820 0032 13F0800F tst r3, #128 + 821 0036 F5D1 bne .L67 + ARM GAS /tmp/ccywxtmH.s page 94 + + + 822 0038 03E0 b .L66 + 823 .L76: +4392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 824 .loc 1 4392 7 view .LVU231 + 825 003a 236E ldr r3, [r4, #96] + 826 003c 43F04003 orr r3, r3, #64 + 827 0040 2366 str r3, [r4, #96] +4393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 828 .loc 1 4393 7 view .LVU232 + 829 .L66: +4397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + 830 .loc 1 4398 3 view .LVU233 + 831 .loc 1 4398 7 is_stmt 0 view .LVU234 + 832 0042 FFF7FEFF bl HAL_GetTick + 833 .LVL45: + 834 .loc 1 4398 7 view .LVU235 + 835 0046 0246 mov r2, r0 + 836 0048 6421 movs r1, #100 + 837 004a 2046 mov r0, r4 + 838 004c FFF7FEFF bl SPI_EndRxTxTransaction + 839 .LVL46: + 840 .loc 1 4398 6 view .LVU236 + 841 0050 08B1 cbz r0, .L68 +4399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 842 .loc 1 4400 5 is_stmt 1 view .LVU237 + 843 .loc 1 4400 21 is_stmt 0 view .LVU238 + 844 0052 4023 movs r3, #64 + 845 0054 2366 str r3, [r4, #96] + 846 .L68: +4401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +4404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 847 .loc 1 4404 3 is_stmt 1 view .LVU239 + 848 0056 2268 ldr r2, [r4] + 849 0058 1368 ldr r3, [r2] + 850 005a 23F04003 bic r3, r3, #64 + 851 005e 1360 str r3, [r2] +4405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +4407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL + 852 .loc 1 4407 3 view .LVU240 + 853 .loc 1 4407 7 is_stmt 0 view .LVU241 + 854 0060 FFF7FEFF bl HAL_GetTick + 855 .LVL47: + 856 0064 0090 str r0, [sp] + 857 0066 6423 movs r3, #100 + 858 0068 0022 movs r2, #0 + 859 006a 4FF4C061 mov r1, #1536 + 860 006e 2046 mov r0, r4 + 861 0070 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 862 .LVL48: + 863 .loc 1 4407 6 view .LVU242 + 864 0074 08B1 cbz r0, .L69 +4408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 95 + + +4409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 865 .loc 1 4409 5 is_stmt 1 view .LVU243 + 866 .loc 1 4409 21 is_stmt 0 view .LVU244 + 867 0076 4023 movs r3, #64 + 868 0078 2366 str r3, [r4, #96] + 869 .L69: +4410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ +4413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + 870 .loc 1 4413 3 is_stmt 1 view .LVU245 + 871 .loc 1 4413 7 is_stmt 0 view .LVU246 + 872 007a 2368 ldr r3, [r4] + 873 007c 5A68 ldr r2, [r3, #4] + 874 .loc 1 4413 6 view .LVU247 + 875 007e 12F0400F tst r2, #64 + 876 0082 2BD0 beq .L70 +4414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNEIE interrupt */ +4416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + 877 .loc 1 4416 5 is_stmt 1 view .LVU248 + 878 0084 5A68 ldr r2, [r3, #4] + 879 0086 22F04002 bic r2, r2, #64 + 880 008a 5A60 str r2, [r3, #4] + 881 .L73: +4417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check RXNEIE is disabled */ +4419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do + 882 .loc 1 4419 5 view .LVU249 +4420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 883 .loc 1 4421 7 view .LVU250 + 884 .loc 1 4421 17 is_stmt 0 view .LVU251 + 885 008c 039B ldr r3, [sp, #12] + 886 .loc 1 4421 10 view .LVU252 + 887 008e 43B1 cbz r3, .L77 +4422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); +4424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; +4425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 888 .loc 1 4426 7 is_stmt 1 view .LVU253 + 889 .loc 1 4426 12 is_stmt 0 view .LVU254 + 890 0090 039B ldr r3, [sp, #12] + 891 0092 013B subs r3, r3, #1 + 892 0094 0393 str r3, [sp, #12] +4427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + 893 .loc 1 4427 14 is_stmt 1 view .LVU255 + 894 0096 2368 ldr r3, [r4] + 895 0098 5B68 ldr r3, [r3, #4] + 896 009a 13F0400F tst r3, #64 + 897 009e F5D1 bne .L73 + 898 00a0 03E0 b .L72 + 899 .L77: +4423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 900 .loc 1 4423 9 view .LVU256 + 901 00a2 236E ldr r3, [r4, #96] + ARM GAS /tmp/ccywxtmH.s page 96 + + + 902 00a4 43F04003 orr r3, r3, #64 + 903 00a8 2366 str r3, [r4, #96] +4424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 904 .loc 1 4424 9 view .LVU257 + 905 .L72: +4428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +4430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick() + 906 .loc 1 4430 5 view .LVU258 + 907 .loc 1 4430 9 is_stmt 0 view .LVU259 + 908 00aa FFF7FEFF bl HAL_GetTick + 909 .LVL49: + 910 00ae 0090 str r0, [sp] + 911 00b0 6423 movs r3, #100 + 912 00b2 0022 movs r2, #0 + 913 00b4 8021 movs r1, #128 + 914 00b6 2046 mov r0, r4 + 915 00b8 FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 916 .LVL50: + 917 .loc 1 4430 8 view .LVU260 + 918 00bc 08B1 cbz r0, .L74 +4431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 919 .loc 1 4432 7 is_stmt 1 view .LVU261 + 920 .loc 1 4432 23 is_stmt 0 view .LVU262 + 921 00be 4023 movs r3, #64 + 922 00c0 2366 str r3, [r4, #96] + 923 .L74: +4433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +4436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, H + 924 .loc 1 4436 5 is_stmt 1 view .LVU263 + 925 .loc 1 4436 9 is_stmt 0 view .LVU264 + 926 00c2 FFF7FEFF bl HAL_GetTick + 927 .LVL51: + 928 00c6 0090 str r0, [sp] + 929 00c8 6423 movs r3, #100 + 930 00ca 0022 movs r2, #0 + 931 00cc 4FF4C061 mov r1, #1536 + 932 00d0 2046 mov r0, r4 + 933 00d2 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 934 .LVL52: + 935 .loc 1 4436 8 view .LVU265 + 936 00d6 08B1 cbz r0, .L70 +4437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 937 .loc 1 4438 7 is_stmt 1 view .LVU266 + 938 .loc 1 4438 23 is_stmt 0 view .LVU267 + 939 00d8 4023 movs r3, #64 + 940 00da 2366 str r3, [r4, #96] + 941 .L70: +4439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_ABORT; + 942 .loc 1 4441 3 is_stmt 1 view .LVU268 + 943 .loc 1 4441 15 is_stmt 0 view .LVU269 + ARM GAS /tmp/ccywxtmH.s page 97 + + + 944 00dc 0723 movs r3, #7 + 945 00de 84F85D30 strb r3, [r4, #93] +4442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 946 .loc 1 4442 1 view .LVU270 + 947 00e2 04B0 add sp, sp, #16 + 948 .cfi_def_cfa_offset 8 + 949 @ sp needed + 950 00e4 10BD pop {r4, pc} + 951 .LVL53: + 952 .L79: + 953 .loc 1 4442 1 view .LVU271 + 954 00e6 00BF .align 2 + 955 .L78: + 956 00e8 00000000 .word SystemCoreClock + 957 00ec F1197605 .word 91625969 + 958 .cfi_endproc + 959 .LFE185: + 961 .section .text.HAL_SPI_MspInit,"ax",%progbits + 962 .align 1 + 963 .weak HAL_SPI_MspInit + 964 .syntax unified + 965 .thumb + 966 .thumb_func + 968 HAL_SPI_MspInit: + 969 .LVL54: + 970 .LFB132: + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 971 .loc 1 536 1 is_stmt 1 view -0 + 972 .cfi_startproc + 973 @ args = 0, pretend = 0, frame = 0 + 974 @ frame_needed = 0, uses_anonymous_args = 0 + 975 @ link register save eliminated. + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 976 .loc 1 538 3 view .LVU273 + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 977 .loc 1 543 1 is_stmt 0 view .LVU274 + 978 0000 7047 bx lr + 979 .cfi_endproc + 980 .LFE132: + 982 .section .text.HAL_SPI_Init,"ax",%progbits + 983 .align 1 + 984 .global HAL_SPI_Init + 985 .syntax unified + 986 .thumb + 987 .thumb_func + 989 HAL_SPI_Init: + 990 .LVL55: + 991 .LFB130: + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t frxth; + 992 .loc 1 317 1 is_stmt 1 view -0 + 993 .cfi_startproc + 994 @ args = 0, pretend = 0, frame = 0 + 995 @ frame_needed = 0, uses_anonymous_args = 0 + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 996 .loc 1 318 3 view .LVU276 + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 997 .loc 1 321 3 view .LVU277 + ARM GAS /tmp/ccywxtmH.s page 98 + + + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 998 .loc 1 321 6 is_stmt 0 view .LVU278 + 999 0000 0028 cmp r0, #0 + 1000 0002 6FD0 beq .L88 + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t frxth; + 1001 .loc 1 317 1 view .LVU279 + 1002 0004 10B5 push {r4, lr} + 1003 .cfi_def_cfa_offset 8 + 1004 .cfi_offset 4, -8 + 1005 .cfi_offset 14, -4 + 1006 0006 0446 mov r4, r0 + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_MODE(hspi->Init.Mode)); + 1007 .loc 1 327 3 is_stmt 1 view .LVU280 + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + 1008 .loc 1 328 3 view .LVU281 + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + 1009 .loc 1 329 3 view .LVU282 + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_NSS(hspi->Init.NSS)); + 1010 .loc 1 330 3 view .LVU283 + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + 1011 .loc 1 331 3 view .LVU284 + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + 1012 .loc 1 332 3 view .LVU285 + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + 1013 .loc 1 333 3 view .LVU286 + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + 1014 .loc 1 334 3 view .LVU287 + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 1015 .loc 1 335 3 view .LVU288 + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1016 .loc 1 336 3 view .LVU289 + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1017 .loc 1 336 17 is_stmt 0 view .LVU290 + 1018 0008 436A ldr r3, [r0, #36] + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1019 .loc 1 336 6 view .LVU291 + 1020 000a 33B9 cbnz r3, .L83 + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + 1021 .loc 1 338 5 is_stmt 1 view .LVU292 + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1022 .loc 1 339 5 view .LVU293 + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1023 .loc 1 341 5 view .LVU294 + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1024 .loc 1 341 19 is_stmt 0 view .LVU295 + 1025 000c 4368 ldr r3, [r0, #4] + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1026 .loc 1 341 8 view .LVU296 + 1027 000e B3F5827F cmp r3, #260 + 1028 0012 05D0 beq .L84 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1029 .loc 1 348 7 is_stmt 1 view .LVU297 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1030 .loc 1 348 36 is_stmt 0 view .LVU298 + 1031 0014 0023 movs r3, #0 + 1032 0016 C361 str r3, [r0, #28] + 1033 0018 02E0 b .L84 + ARM GAS /tmp/ccywxtmH.s page 99 + + + 1034 .L83: + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1035 .loc 1 353 5 is_stmt 1 view .LVU299 + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 1036 .loc 1 356 5 view .LVU300 + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 1037 .loc 1 356 28 is_stmt 0 view .LVU301 + 1038 001a 0023 movs r3, #0 + 1039 001c 0361 str r3, [r0, #16] + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1040 .loc 1 357 5 is_stmt 1 view .LVU302 + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1041 .loc 1 357 28 is_stmt 0 view .LVU303 + 1042 001e 4361 str r3, [r0, #20] + 1043 .L84: + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 1044 .loc 1 367 3 is_stmt 1 view .LVU304 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 1045 .loc 1 367 29 is_stmt 0 view .LVU305 + 1046 0020 0023 movs r3, #0 + 1047 0022 A362 str r3, [r4, #40] + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1048 .loc 1 370 3 is_stmt 1 view .LVU306 + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1049 .loc 1 370 11 is_stmt 0 view .LVU307 + 1050 0024 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1051 .loc 1 370 6 view .LVU308 + 1052 0028 002B cmp r3, #0 + 1053 002a 52D0 beq .L94 + 1054 .LVL56: + 1055 .L85: + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1056 .loc 1 399 3 is_stmt 1 view .LVU309 + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1057 .loc 1 399 15 is_stmt 0 view .LVU310 + 1058 002c 0223 movs r3, #2 + 1059 002e 84F85D30 strb r3, [r4, #93] + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1060 .loc 1 402 3 is_stmt 1 view .LVU311 + 1061 0032 2268 ldr r2, [r4] + 1062 0034 1368 ldr r3, [r2] + 1063 0036 23F04003 bic r3, r3, #64 + 1064 003a 1360 str r3, [r2] + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1065 .loc 1 405 3 view .LVU312 + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1066 .loc 1 405 17 is_stmt 0 view .LVU313 + 1067 003c E368 ldr r3, [r4, #12] + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1068 .loc 1 405 6 view .LVU314 + 1069 003e B3F5E06F cmp r3, #1792 + 1070 0042 4CD9 bls .L89 + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1071 .loc 1 407 11 view .LVU315 + 1072 0044 0022 movs r2, #0 + 1073 .L86: + ARM GAS /tmp/ccywxtmH.s page 100 + + + 1074 .LVL57: + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1075 .loc 1 415 3 is_stmt 1 view .LVU316 + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1076 .loc 1 415 6 is_stmt 0 view .LVU317 + 1077 0046 B3F5706F cmp r3, #3840 + 1078 004a 04D0 beq .L87 + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1079 .loc 1 415 51 discriminator 1 view .LVU318 + 1080 004c B3F5E06F cmp r3, #1792 + 1081 0050 01D0 beq .L87 + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1082 .loc 1 418 5 is_stmt 1 view .LVU319 + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1083 .loc 1 418 31 is_stmt 0 view .LVU320 + 1084 0052 0023 movs r3, #0 + 1085 0054 A362 str r3, [r4, #40] + 1086 .L87: + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + 1087 .loc 1 424 3 is_stmt 1 view .LVU321 + 1088 0056 6368 ldr r3, [r4, #4] + 1089 0058 03F48273 and r3, r3, #260 + 1090 005c A168 ldr r1, [r4, #8] + 1091 005e 01F40441 and r1, r1, #33792 + 1092 0062 0B43 orrs r3, r3, r1 + 1093 0064 2169 ldr r1, [r4, #16] + 1094 0066 01F00201 and r1, r1, #2 + 1095 006a 0B43 orrs r3, r3, r1 + 1096 006c 6169 ldr r1, [r4, #20] + 1097 006e 01F00101 and r1, r1, #1 + 1098 0072 0B43 orrs r3, r3, r1 + 1099 0074 A169 ldr r1, [r4, #24] + 1100 0076 01F40071 and r1, r1, #512 + 1101 007a 0B43 orrs r3, r3, r1 + 1102 007c E169 ldr r1, [r4, #28] + 1103 007e 01F03801 and r1, r1, #56 + 1104 0082 0B43 orrs r3, r3, r1 + 1105 0084 216A ldr r1, [r4, #32] + 1106 0086 01F08001 and r1, r1, #128 + 1107 008a 0B43 orrs r3, r3, r1 + 1108 008c A16A ldr r1, [r4, #40] + 1109 008e 01F40051 and r1, r1, #8192 + 1110 0092 2068 ldr r0, [r4] + 1111 0094 0B43 orrs r3, r3, r1 + 1112 0096 0360 str r3, [r0] + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.TIMode & SPI_CR2_FRF) | + 1113 .loc 1 459 3 view .LVU322 + 1114 0098 638B ldrh r3, [r4, #26] + 1115 009a 03F00403 and r3, r3, #4 + 1116 009e 616A ldr r1, [r4, #36] + 1117 00a0 01F01001 and r1, r1, #16 + 1118 00a4 0B43 orrs r3, r3, r1 + 1119 00a6 616B ldr r1, [r4, #52] + 1120 00a8 01F00801 and r1, r1, #8 + 1121 00ac 0B43 orrs r3, r3, r1 + 1122 00ae E168 ldr r1, [r4, #12] + 1123 00b0 01F47061 and r1, r1, #3840 + ARM GAS /tmp/ccywxtmH.s page 101 + + + 1124 00b4 0B43 orrs r3, r3, r1 + 1125 00b6 2168 ldr r1, [r4] + 1126 00b8 1A43 orrs r2, r2, r3 + 1127 .LVL58: + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.TIMode & SPI_CR2_FRF) | + 1128 .loc 1 459 3 is_stmt 0 view .LVU323 + 1129 00ba 4A60 str r2, [r1, #4] + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* SPI_I2SCFGR_I2SMOD */ + 1130 .loc 1 476 3 is_stmt 1 view .LVU324 + 1131 00bc 2268 ldr r2, [r4] + 1132 00be D369 ldr r3, [r2, #28] + 1133 00c0 23F40063 bic r3, r3, #2048 + 1134 00c4 D361 str r3, [r2, #28] + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 1135 .loc 1 479 3 view .LVU325 + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 1136 .loc 1 479 19 is_stmt 0 view .LVU326 + 1137 00c6 0020 movs r0, #0 + 1138 00c8 2066 str r0, [r4, #96] + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1139 .loc 1 480 3 is_stmt 1 view .LVU327 + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1140 .loc 1 480 19 is_stmt 0 view .LVU328 + 1141 00ca 0123 movs r3, #1 + 1142 00cc 84F85D30 strb r3, [r4, #93] + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1143 .loc 1 482 3 is_stmt 1 view .LVU329 + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1144 .loc 1 483 1 is_stmt 0 view .LVU330 + 1145 00d0 10BD pop {r4, pc} + 1146 .LVL59: + 1147 .L94: + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1148 .loc 1 373 5 is_stmt 1 view .LVU331 + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1149 .loc 1 373 16 is_stmt 0 view .LVU332 + 1150 00d2 84F85C30 strb r3, [r4, #92] + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 1151 .loc 1 395 5 is_stmt 1 view .LVU333 + 1152 00d6 2046 mov r0, r4 + 1153 .LVL60: + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 1154 .loc 1 395 5 is_stmt 0 view .LVU334 + 1155 00d8 FFF7FEFF bl HAL_SPI_MspInit + 1156 .LVL61: + 1157 00dc A6E7 b .L85 + 1158 .L89: + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1159 .loc 1 411 11 view .LVU335 + 1160 00de 4FF48052 mov r2, #4096 + 1161 00e2 B0E7 b .L86 + 1162 .LVL62: + 1163 .L88: + 1164 .cfi_def_cfa_offset 0 + 1165 .cfi_restore 4 + 1166 .cfi_restore 14 + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 102 + + + 1167 .loc 1 323 12 view .LVU336 + 1168 00e4 0120 movs r0, #1 + 1169 .LVL63: + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1170 .loc 1 483 1 view .LVU337 + 1171 00e6 7047 bx lr + 1172 .cfi_endproc + 1173 .LFE130: + 1175 .section .text.HAL_SPI_MspDeInit,"ax",%progbits + 1176 .align 1 + 1177 .weak HAL_SPI_MspDeInit + 1178 .syntax unified + 1179 .thumb + 1180 .thumb_func + 1182 HAL_SPI_MspDeInit: + 1183 .LVL64: + 1184 .LFB133: + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 1185 .loc 1 552 1 is_stmt 1 view -0 + 1186 .cfi_startproc + 1187 @ args = 0, pretend = 0, frame = 0 + 1188 @ frame_needed = 0, uses_anonymous_args = 0 + 1189 @ link register save eliminated. + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1190 .loc 1 554 3 view .LVU339 + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1191 .loc 1 559 1 is_stmt 0 view .LVU340 + 1192 0000 7047 bx lr + 1193 .cfi_endproc + 1194 .LFE133: + 1196 .section .text.HAL_SPI_DeInit,"ax",%progbits + 1197 .align 1 + 1198 .global HAL_SPI_DeInit + 1199 .syntax unified + 1200 .thumb + 1201 .thumb_func + 1203 HAL_SPI_DeInit: + 1204 .LVL65: + 1205 .LFB131: + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the SPI handle allocation */ + 1206 .loc 1 492 1 is_stmt 1 view -0 + 1207 .cfi_startproc + 1208 @ args = 0, pretend = 0, frame = 0 + 1209 @ frame_needed = 0, uses_anonymous_args = 0 + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1210 .loc 1 494 3 view .LVU342 + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1211 .loc 1 494 6 is_stmt 0 view .LVU343 + 1212 0000 90B1 cbz r0, .L98 + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the SPI handle allocation */ + 1213 .loc 1 492 1 view .LVU344 + 1214 0002 10B5 push {r4, lr} + 1215 .cfi_def_cfa_offset 8 + 1216 .cfi_offset 4, -8 + 1217 .cfi_offset 14, -4 + 1218 0004 0446 mov r4, r0 + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 103 + + + 1219 .loc 1 500 3 is_stmt 1 view .LVU345 + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1220 .loc 1 502 3 view .LVU346 + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1221 .loc 1 502 15 is_stmt 0 view .LVU347 + 1222 0006 0223 movs r3, #2 + 1223 0008 80F85D30 strb r3, [r0, #93] + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1224 .loc 1 505 3 is_stmt 1 view .LVU348 + 1225 000c 0268 ldr r2, [r0] + 1226 000e 1368 ldr r3, [r2] + 1227 0010 23F04003 bic r3, r3, #64 + 1228 0014 1360 str r3, [r2] + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 1229 .loc 1 517 3 view .LVU349 + 1230 0016 FFF7FEFF bl HAL_SPI_MspDeInit + 1231 .LVL66: + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_RESET; + 1232 .loc 1 520 3 view .LVU350 + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_RESET; + 1233 .loc 1 520 19 is_stmt 0 view .LVU351 + 1234 001a 0020 movs r0, #0 + 1235 001c 2066 str r0, [r4, #96] + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1236 .loc 1 521 3 is_stmt 1 view .LVU352 + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1237 .loc 1 521 15 is_stmt 0 view .LVU353 + 1238 001e 84F85D00 strb r0, [r4, #93] + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1239 .loc 1 524 3 is_stmt 1 view .LVU354 + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1240 .loc 1 524 3 view .LVU355 + 1241 0022 84F85C00 strb r0, [r4, #92] + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1242 .loc 1 524 3 view .LVU356 + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1243 .loc 1 526 3 view .LVU357 + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1244 .loc 1 527 1 is_stmt 0 view .LVU358 + 1245 0026 10BD pop {r4, pc} + 1246 .LVL67: + 1247 .L98: + 1248 .cfi_def_cfa_offset 0 + 1249 .cfi_restore 4 + 1250 .cfi_restore 14 + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1251 .loc 1 496 12 view .LVU359 + 1252 0028 0120 movs r0, #1 + 1253 .LVL68: + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1254 .loc 1 527 1 view .LVU360 + 1255 002a 7047 bx lr + 1256 .cfi_endproc + 1257 .LFE131: + 1259 .section .text.HAL_SPI_Transmit,"ax",%progbits + 1260 .align 1 + 1261 .global HAL_SPI_Transmit + ARM GAS /tmp/ccywxtmH.s page 104 + + + 1262 .syntax unified + 1263 .thumb + 1264 .thumb_func + 1266 HAL_SPI_Transmit: + 1267 .LVL69: + 1268 .LFB134: + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 1269 .loc 1 824 1 is_stmt 1 view -0 + 1270 .cfi_startproc + 1271 @ args = 0, pretend = 0, frame = 8 + 1272 @ frame_needed = 0, uses_anonymous_args = 0 + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 1273 .loc 1 824 1 is_stmt 0 view .LVU362 + 1274 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 1275 .cfi_def_cfa_offset 28 + 1276 .cfi_offset 4, -28 + 1277 .cfi_offset 5, -24 + 1278 .cfi_offset 6, -20 + 1279 .cfi_offset 7, -16 + 1280 .cfi_offset 8, -12 + 1281 .cfi_offset 9, -8 + 1282 .cfi_offset 14, -4 + 1283 0004 83B0 sub sp, sp, #12 + 1284 .cfi_def_cfa_offset 40 + 1285 0006 1D46 mov r5, r3 + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 1286 .loc 1 825 3 is_stmt 1 view .LVU363 + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_TxXferCount; + 1287 .loc 1 826 3 view .LVU364 + 1288 .LVL70: + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1289 .loc 1 827 3 view .LVU365 + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1290 .loc 1 830 3 view .LVU366 + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1291 .loc 1 833 3 view .LVU367 + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1292 .loc 1 833 3 view .LVU368 + 1293 0008 90F85C30 ldrb r3, [r0, #92] @ zero_extendqisi2 + 1294 .LVL71: + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1295 .loc 1 833 3 is_stmt 0 view .LVU369 + 1296 000c 012B cmp r3, #1 + 1297 000e 00F0F680 beq .L128 + 1298 0012 0446 mov r4, r0 + 1299 0014 8846 mov r8, r1 + 1300 0016 9146 mov r9, r2 + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1301 .loc 1 833 3 is_stmt 1 discriminator 2 view .LVU370 + 1302 0018 0123 movs r3, #1 + 1303 001a 80F85C30 strb r3, [r0, #92] + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1304 .loc 1 833 3 discriminator 2 view .LVU371 + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; + 1305 .loc 1 836 3 discriminator 2 view .LVU372 + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; + 1306 .loc 1 836 15 is_stmt 0 discriminator 2 view .LVU373 + ARM GAS /tmp/ccywxtmH.s page 105 + + + 1307 001e FFF7FEFF bl HAL_GetTick + 1308 .LVL72: + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; + 1309 .loc 1 836 15 discriminator 2 view .LVU374 + 1310 0022 0746 mov r7, r0 + 1311 .LVL73: + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1312 .loc 1 837 3 is_stmt 1 discriminator 2 view .LVU375 + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1313 .loc 1 839 3 discriminator 2 view .LVU376 + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1314 .loc 1 839 11 is_stmt 0 discriminator 2 view .LVU377 + 1315 0024 94F85D60 ldrb r6, [r4, #93] @ zero_extendqisi2 + 1316 0028 F6B2 uxtb r6, r6 + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1317 .loc 1 839 6 discriminator 2 view .LVU378 + 1318 002a 012E cmp r6, #1 + 1319 002c 40F0D480 bne .L129 + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1320 .loc 1 845 3 is_stmt 1 view .LVU379 + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1321 .loc 1 845 6 is_stmt 0 view .LVU380 + 1322 0030 B8F1000F cmp r8, #0 + 1323 0034 00F0D180 beq .L105 + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1324 .loc 1 845 23 discriminator 1 view .LVU381 + 1325 0038 B9F1000F cmp r9, #0 + 1326 003c 00F0CD80 beq .L105 + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 1327 .loc 1 852 3 is_stmt 1 view .LVU382 + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 1328 .loc 1 852 21 is_stmt 0 view .LVU383 + 1329 0040 0323 movs r3, #3 + 1330 0042 84F85D30 strb r3, [r4, #93] + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 1331 .loc 1 853 3 is_stmt 1 view .LVU384 + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 1332 .loc 1 853 21 is_stmt 0 view .LVU385 + 1333 0046 0023 movs r3, #0 + 1334 0048 2366 str r3, [r4, #96] + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 1335 .loc 1 854 3 is_stmt 1 view .LVU386 + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 1336 .loc 1 854 21 is_stmt 0 view .LVU387 + 1337 004a C4F83880 str r8, [r4, #56] + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 1338 .loc 1 855 3 is_stmt 1 view .LVU388 + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 1339 .loc 1 855 21 is_stmt 0 view .LVU389 + 1340 004e A4F83C90 strh r9, [r4, #60] @ movhi + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1341 .loc 1 856 3 is_stmt 1 view .LVU390 + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1342 .loc 1 856 21 is_stmt 0 view .LVU391 + 1343 0052 A4F83E90 strh r9, [r4, #62] @ movhi + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 1344 .loc 1 859 3 is_stmt 1 view .LVU392 + ARM GAS /tmp/ccywxtmH.s page 106 + + + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 1345 .loc 1 859 21 is_stmt 0 view .LVU393 + 1346 0056 2364 str r3, [r4, #64] + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 1347 .loc 1 860 3 is_stmt 1 view .LVU394 + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 1348 .loc 1 860 21 is_stmt 0 view .LVU395 + 1349 0058 A4F84430 strh r3, [r4, #68] @ movhi + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 1350 .loc 1 861 3 is_stmt 1 view .LVU396 + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 1351 .loc 1 861 21 is_stmt 0 view .LVU397 + 1352 005c A4F84630 strh r3, [r4, #70] @ movhi + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 1353 .loc 1 862 3 is_stmt 1 view .LVU398 + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 1354 .loc 1 862 21 is_stmt 0 view .LVU399 + 1355 0060 2365 str r3, [r4, #80] + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1356 .loc 1 863 3 is_stmt 1 view .LVU400 + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1357 .loc 1 863 21 is_stmt 0 view .LVU401 + 1358 0062 E364 str r3, [r4, #76] + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1359 .loc 1 866 3 is_stmt 1 view .LVU402 + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1360 .loc 1 866 17 is_stmt 0 view .LVU403 + 1361 0064 A368 ldr r3, [r4, #8] + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1362 .loc 1 866 6 view .LVU404 + 1363 0066 B3F5004F cmp r3, #32768 + 1364 006a 1ED0 beq .L135 + 1365 .L106: + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1366 .loc 1 882 3 is_stmt 1 view .LVU405 + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1367 .loc 1 882 12 is_stmt 0 view .LVU406 + 1368 006c 2368 ldr r3, [r4] + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1369 .loc 1 882 22 view .LVU407 + 1370 006e 1A68 ldr r2, [r3] + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1371 .loc 1 882 6 view .LVU408 + 1372 0070 12F0400F tst r2, #64 + 1373 0074 03D1 bne .L107 + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1374 .loc 1 885 5 is_stmt 1 view .LVU409 + 1375 0076 1A68 ldr r2, [r3] + 1376 0078 42F04002 orr r2, r2, #64 + 1377 007c 1A60 str r2, [r3] + 1378 .L107: + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1379 .loc 1 889 3 view .LVU410 + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1380 .loc 1 889 17 is_stmt 0 view .LVU411 + 1381 007e E368 ldr r3, [r4, #12] + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 107 + + + 1382 .loc 1 889 6 view .LVU412 + 1383 0080 B3F5E06F cmp r3, #1792 + 1384 0084 42D9 bls .L108 + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1385 .loc 1 891 5 is_stmt 1 view .LVU413 + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1386 .loc 1 891 20 is_stmt 0 view .LVU414 + 1387 0086 6368 ldr r3, [r4, #4] + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1388 .loc 1 891 8 view .LVU415 + 1389 0088 13B1 cbz r3, .L109 + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1390 .loc 1 891 45 discriminator 1 view .LVU416 + 1391 008a B9F1010F cmp r9, #1 + 1392 008e 23D1 bne .L111 + 1393 .L109: + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1394 .loc 1 893 7 is_stmt 1 view .LVU417 + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1395 .loc 1 893 46 is_stmt 0 view .LVU418 + 1396 0090 A26B ldr r2, [r4, #56] + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1397 .loc 1 893 11 view .LVU419 + 1398 0092 2368 ldr r3, [r4] + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1399 .loc 1 893 28 view .LVU420 + 1400 0094 1288 ldrh r2, [r2] + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1401 .loc 1 893 26 view .LVU421 + 1402 0096 DA60 str r2, [r3, #12] + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1403 .loc 1 894 7 is_stmt 1 view .LVU422 + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1404 .loc 1 894 11 is_stmt 0 view .LVU423 + 1405 0098 A36B ldr r3, [r4, #56] + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1406 .loc 1 894 24 view .LVU424 + 1407 009a 0233 adds r3, r3, #2 + 1408 009c A363 str r3, [r4, #56] + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1409 .loc 1 895 7 is_stmt 1 view .LVU425 + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1410 .loc 1 895 11 is_stmt 0 view .LVU426 + 1411 009e E38F ldrh r3, [r4, #62] + 1412 00a0 9BB2 uxth r3, r3 + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1413 .loc 1 895 24 view .LVU427 + 1414 00a2 013B subs r3, r3, #1 + 1415 00a4 9BB2 uxth r3, r3 + 1416 00a6 E387 strh r3, [r4, #62] @ movhi + 1417 00a8 16E0 b .L111 + 1418 .L135: + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 1419 .loc 1 869 5 is_stmt 1 view .LVU428 + 1420 00aa 2268 ldr r2, [r4] + 1421 00ac 1368 ldr r3, [r2] + 1422 00ae 23F04003 bic r3, r3, #64 + ARM GAS /tmp/ccywxtmH.s page 108 + + + 1423 00b2 1360 str r3, [r2] + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1424 .loc 1 870 5 view .LVU429 + 1425 00b4 2268 ldr r2, [r4] + 1426 00b6 1368 ldr r3, [r2] + 1427 00b8 43F48043 orr r3, r3, #16384 + 1428 00bc 1360 str r3, [r2] + 1429 00be D5E7 b .L106 + 1430 .LVL74: + 1431 .L112: + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1432 .loc 1 910 9 view .LVU430 + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1433 .loc 1 910 16 is_stmt 0 view .LVU431 + 1434 00c0 FFF7FEFF bl HAL_GetTick + 1435 .LVL75: + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1436 .loc 1 910 30 view .LVU432 + 1437 00c4 C01B subs r0, r0, r7 + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1438 .loc 1 910 12 view .LVU433 + 1439 00c6 A842 cmp r0, r5 + 1440 00c8 03D3 bcc .L114 + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1441 .loc 1 910 56 discriminator 1 view .LVU434 + 1442 00ca B5F1FF3F cmp r5, #-1 + 1443 00ce 40F08E80 bne .L130 + 1444 .L114: + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1445 .loc 1 910 87 discriminator 3 view .LVU435 + 1446 00d2 002D cmp r5, #0 + 1447 00d4 00F08D80 beq .L131 + 1448 .L111: + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1449 .loc 1 898 30 is_stmt 1 view .LVU436 + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1450 .loc 1 898 16 is_stmt 0 view .LVU437 + 1451 00d8 E38F ldrh r3, [r4, #62] + 1452 00da 9BB2 uxth r3, r3 + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1453 .loc 1 898 30 view .LVU438 + 1454 00dc 002B cmp r3, #0 + 1455 00de 66D0 beq .L116 + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1456 .loc 1 901 7 is_stmt 1 view .LVU439 + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1457 .loc 1 901 11 is_stmt 0 view .LVU440 + 1458 00e0 2368 ldr r3, [r4] + 1459 00e2 9A68 ldr r2, [r3, #8] + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1460 .loc 1 901 10 view .LVU441 + 1461 00e4 12F0020F tst r2, #2 + 1462 00e8 EAD0 beq .L112 + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1463 .loc 1 903 9 is_stmt 1 view .LVU442 + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1464 .loc 1 903 48 is_stmt 0 view .LVU443 + ARM GAS /tmp/ccywxtmH.s page 109 + + + 1465 00ea A26B ldr r2, [r4, #56] + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1466 .loc 1 903 30 view .LVU444 + 1467 00ec 1288 ldrh r2, [r2] + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1468 .loc 1 903 28 view .LVU445 + 1469 00ee DA60 str r2, [r3, #12] + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1470 .loc 1 904 9 is_stmt 1 view .LVU446 + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1471 .loc 1 904 13 is_stmt 0 view .LVU447 + 1472 00f0 A36B ldr r3, [r4, #56] + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1473 .loc 1 904 26 view .LVU448 + 1474 00f2 0233 adds r3, r3, #2 + 1475 00f4 A363 str r3, [r4, #56] + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1476 .loc 1 905 9 is_stmt 1 view .LVU449 + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1477 .loc 1 905 13 is_stmt 0 view .LVU450 + 1478 00f6 B4F83EC0 ldrh ip, [r4, #62] + 1479 00fa 1FFA8CFC uxth ip, ip + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1480 .loc 1 905 26 view .LVU451 + 1481 00fe 0CF1FF3C add ip, ip, #-1 + 1482 0102 1FFA8CFC uxth ip, ip + 1483 0106 A4F83EC0 strh ip, [r4, #62] @ movhi + 1484 010a E5E7 b .L111 + 1485 .LVL76: + 1486 .L108: + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1487 .loc 1 921 5 is_stmt 1 view .LVU452 + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1488 .loc 1 921 20 is_stmt 0 view .LVU453 + 1489 010c 6368 ldr r3, [r4, #4] + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1490 .loc 1 921 8 view .LVU454 + 1491 010e 13B1 cbz r3, .L117 + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1492 .loc 1 921 45 discriminator 1 view .LVU455 + 1493 0110 B9F1010F cmp r9, #1 + 1494 0114 33D1 bne .L120 + 1495 .L117: + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1496 .loc 1 923 7 is_stmt 1 view .LVU456 + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1497 .loc 1 923 15 is_stmt 0 view .LVU457 + 1498 0116 E38F ldrh r3, [r4, #62] + 1499 0118 9BB2 uxth r3, r3 + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1500 .loc 1 923 10 view .LVU458 + 1501 011a 012B cmp r3, #1 + 1502 011c 0CD9 bls .L119 + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1503 .loc 1 926 9 is_stmt 1 view .LVU459 + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1504 .loc 1 926 48 is_stmt 0 view .LVU460 + ARM GAS /tmp/ccywxtmH.s page 110 + + + 1505 011e A26B ldr r2, [r4, #56] + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1506 .loc 1 926 13 view .LVU461 + 1507 0120 2368 ldr r3, [r4] + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1508 .loc 1 926 30 view .LVU462 + 1509 0122 1288 ldrh r2, [r2] + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1510 .loc 1 926 28 view .LVU463 + 1511 0124 DA60 str r2, [r3, #12] + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 1512 .loc 1 927 9 is_stmt 1 view .LVU464 + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 1513 .loc 1 927 13 is_stmt 0 view .LVU465 + 1514 0126 A36B ldr r3, [r4, #56] + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 1515 .loc 1 927 26 view .LVU466 + 1516 0128 0233 adds r3, r3, #2 + 1517 012a A363 str r3, [r4, #56] + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1518 .loc 1 928 9 is_stmt 1 view .LVU467 + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1519 .loc 1 928 13 is_stmt 0 view .LVU468 + 1520 012c E38F ldrh r3, [r4, #62] + 1521 012e 9BB2 uxth r3, r3 + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1522 .loc 1 928 27 view .LVU469 + 1523 0130 023B subs r3, r3, #2 + 1524 0132 9BB2 uxth r3, r3 + 1525 0134 E387 strh r3, [r4, #62] @ movhi + 1526 0136 22E0 b .L120 + 1527 .L119: + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr ++; + 1528 .loc 1 932 9 is_stmt 1 view .LVU470 + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr ++; + 1529 .loc 1 932 56 is_stmt 0 view .LVU471 + 1530 0138 A26B ldr r2, [r4, #56] + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr ++; + 1531 .loc 1 932 32 view .LVU472 + 1532 013a 2368 ldr r3, [r4] + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr ++; + 1533 .loc 1 932 51 view .LVU473 + 1534 013c 1278 ldrb r2, [r2] @ zero_extendqisi2 + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr ++; + 1535 .loc 1 932 48 view .LVU474 + 1536 013e 1A73 strb r2, [r3, #12] + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1537 .loc 1 933 9 is_stmt 1 view .LVU475 + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1538 .loc 1 933 13 is_stmt 0 view .LVU476 + 1539 0140 A36B ldr r3, [r4, #56] + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1540 .loc 1 933 26 view .LVU477 + 1541 0142 0133 adds r3, r3, #1 + 1542 0144 A363 str r3, [r4, #56] + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1543 .loc 1 934 9 is_stmt 1 view .LVU478 + ARM GAS /tmp/ccywxtmH.s page 111 + + + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1544 .loc 1 934 13 is_stmt 0 view .LVU479 + 1545 0146 E38F ldrh r3, [r4, #62] + 1546 0148 9BB2 uxth r3, r3 + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1547 .loc 1 934 26 view .LVU480 + 1548 014a 013B subs r3, r3, #1 + 1549 014c 9BB2 uxth r3, r3 + 1550 014e E387 strh r3, [r4, #62] @ movhi + 1551 0150 15E0 b .L120 + 1552 .LVL77: + 1553 .L122: + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 1554 .loc 1 951 11 is_stmt 1 view .LVU481 + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 1555 .loc 1 951 58 is_stmt 0 view .LVU482 + 1556 0152 A36B ldr r3, [r4, #56] + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 1557 .loc 1 951 53 view .LVU483 + 1558 0154 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 1559 .loc 1 951 50 view .LVU484 + 1560 0156 1373 strb r3, [r2, #12] + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1561 .loc 1 952 11 is_stmt 1 view .LVU485 + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1562 .loc 1 952 15 is_stmt 0 view .LVU486 + 1563 0158 A36B ldr r3, [r4, #56] + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1564 .loc 1 952 27 view .LVU487 + 1565 015a 0133 adds r3, r3, #1 + 1566 015c A363 str r3, [r4, #56] + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1567 .loc 1 953 11 is_stmt 1 view .LVU488 + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1568 .loc 1 953 15 is_stmt 0 view .LVU489 + 1569 015e E38F ldrh r3, [r4, #62] + 1570 0160 9BB2 uxth r3, r3 + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1571 .loc 1 953 28 view .LVU490 + 1572 0162 013B subs r3, r3, #1 + 1573 0164 9BB2 uxth r3, r3 + 1574 0166 E387 strh r3, [r4, #62] @ movhi + 1575 0168 09E0 b .L120 + 1576 .L121: + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1577 .loc 1 959 9 is_stmt 1 view .LVU491 + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1578 .loc 1 959 16 is_stmt 0 view .LVU492 + 1579 016a FFF7FEFF bl HAL_GetTick + 1580 .LVL78: + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1581 .loc 1 959 30 view .LVU493 + 1582 016e C01B subs r0, r0, r7 + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1583 .loc 1 959 12 view .LVU494 + 1584 0170 A842 cmp r0, r5 + ARM GAS /tmp/ccywxtmH.s page 112 + + + 1585 0172 02D3 bcc .L124 + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1586 .loc 1 959 56 discriminator 1 view .LVU495 + 1587 0174 B5F1FF3F cmp r5, #-1 + 1588 0178 3DD1 bne .L132 + 1589 .L124: + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1590 .loc 1 959 87 discriminator 3 view .LVU496 + 1591 017a 002D cmp r5, #0 + 1592 017c 3DD0 beq .L133 + 1593 .L120: + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1594 .loc 1 937 30 is_stmt 1 view .LVU497 + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1595 .loc 1 937 16 is_stmt 0 view .LVU498 + 1596 017e E38F ldrh r3, [r4, #62] + 1597 0180 9BB2 uxth r3, r3 + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1598 .loc 1 937 30 view .LVU499 + 1599 0182 A3B1 cbz r3, .L116 + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1600 .loc 1 940 7 is_stmt 1 view .LVU500 + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1601 .loc 1 940 11 is_stmt 0 view .LVU501 + 1602 0184 2268 ldr r2, [r4] + 1603 0186 9368 ldr r3, [r2, #8] + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1604 .loc 1 940 10 view .LVU502 + 1605 0188 13F0020F tst r3, #2 + 1606 018c EDD0 beq .L121 + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1607 .loc 1 942 9 is_stmt 1 view .LVU503 + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1608 .loc 1 942 17 is_stmt 0 view .LVU504 + 1609 018e E38F ldrh r3, [r4, #62] + 1610 0190 9BB2 uxth r3, r3 + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1611 .loc 1 942 12 view .LVU505 + 1612 0192 012B cmp r3, #1 + 1613 0194 DDD9 bls .L122 + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1614 .loc 1 945 11 is_stmt 1 view .LVU506 + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1615 .loc 1 945 50 is_stmt 0 view .LVU507 + 1616 0196 A36B ldr r3, [r4, #56] + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1617 .loc 1 945 32 view .LVU508 + 1618 0198 1B88 ldrh r3, [r3] + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1619 .loc 1 945 30 view .LVU509 + 1620 019a D360 str r3, [r2, #12] + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 1621 .loc 1 946 11 is_stmt 1 view .LVU510 + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 1622 .loc 1 946 15 is_stmt 0 view .LVU511 + 1623 019c A36B ldr r3, [r4, #56] + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + ARM GAS /tmp/ccywxtmH.s page 113 + + + 1624 .loc 1 946 28 view .LVU512 + 1625 019e 0233 adds r3, r3, #2 + 1626 01a0 A363 str r3, [r4, #56] + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1627 .loc 1 947 11 is_stmt 1 view .LVU513 + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1628 .loc 1 947 15 is_stmt 0 view .LVU514 + 1629 01a2 E38F ldrh r3, [r4, #62] + 1630 01a4 9BB2 uxth r3, r3 + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1631 .loc 1 947 29 view .LVU515 + 1632 01a6 023B subs r3, r3, #2 + 1633 01a8 9BB2 uxth r3, r3 + 1634 01aa E387 strh r3, [r4, #62] @ movhi + 1635 01ac E7E7 b .L120 + 1636 .L116: + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1637 .loc 1 976 3 is_stmt 1 view .LVU516 + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1638 .loc 1 976 7 is_stmt 0 view .LVU517 + 1639 01ae 3A46 mov r2, r7 + 1640 01b0 2946 mov r1, r5 + 1641 01b2 2046 mov r0, r4 + 1642 01b4 FFF7FEFF bl SPI_EndRxTxTransaction + 1643 .LVL79: + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1644 .loc 1 976 6 view .LVU518 + 1645 01b8 08B1 cbz r0, .L126 + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1646 .loc 1 978 5 is_stmt 1 view .LVU519 + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1647 .loc 1 978 21 is_stmt 0 view .LVU520 + 1648 01ba 2023 movs r3, #32 + 1649 01bc 2366 str r3, [r4, #96] + 1650 .L126: + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1651 .loc 1 982 3 is_stmt 1 view .LVU521 + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1652 .loc 1 982 17 is_stmt 0 view .LVU522 + 1653 01be A368 ldr r3, [r4, #8] + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1654 .loc 1 982 6 view .LVU523 + 1655 01c0 33B9 cbnz r3, .L127 + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1656 .loc 1 984 5 is_stmt 1 view .LVU524 + 1657 .LBB2: + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1658 .loc 1 984 5 view .LVU525 + 1659 01c2 0193 str r3, [sp, #4] + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1660 .loc 1 984 5 view .LVU526 + 1661 01c4 2368 ldr r3, [r4] + 1662 01c6 DA68 ldr r2, [r3, #12] + 1663 01c8 0192 str r2, [sp, #4] + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1664 .loc 1 984 5 view .LVU527 + 1665 01ca 9B68 ldr r3, [r3, #8] + ARM GAS /tmp/ccywxtmH.s page 114 + + + 1666 01cc 0193 str r3, [sp, #4] + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1667 .loc 1 984 5 view .LVU528 + 1668 01ce 019B ldr r3, [sp, #4] + 1669 .L127: + 1670 .LBE2: + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1671 .loc 1 984 5 discriminator 1 view .LVU529 + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1672 .loc 1 987 3 discriminator 1 view .LVU530 + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1673 .loc 1 987 11 is_stmt 0 discriminator 1 view .LVU531 + 1674 01d0 236E ldr r3, [r4, #96] + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1675 .loc 1 987 6 discriminator 1 view .LVU532 + 1676 01d2 13B9 cbnz r3, .L105 + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_TxXferCount; + 1677 .loc 1 826 21 view .LVU533 + 1678 01d4 0026 movs r6, #0 + 1679 01d6 00E0 b .L105 + 1680 .LVL80: + 1681 .L129: + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 1682 .loc 1 841 15 view .LVU534 + 1683 01d8 0226 movs r6, #2 + 1684 .LVL81: + 1685 .L105: + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ + 1686 .loc 1 993 3 is_stmt 1 view .LVU535 + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ + 1687 .loc 1 993 15 is_stmt 0 view .LVU536 + 1688 01da 0123 movs r3, #1 + 1689 01dc 84F85D30 strb r3, [r4, #93] + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 1690 .loc 1 995 3 is_stmt 1 view .LVU537 + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 1691 .loc 1 995 3 view .LVU538 + 1692 01e0 0023 movs r3, #0 + 1693 01e2 84F85C30 strb r3, [r4, #92] + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 1694 .loc 1 995 3 view .LVU539 + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1695 .loc 1 996 3 view .LVU540 + 1696 .LVL82: + 1697 .L104: + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1698 .loc 1 997 1 is_stmt 0 view .LVU541 + 1699 01e6 3046 mov r0, r6 + 1700 01e8 03B0 add sp, sp, #12 + 1701 .cfi_remember_state + 1702 .cfi_def_cfa_offset 28 + 1703 @ sp needed + 1704 01ea BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 1705 .LVL83: + 1706 .L130: + 1707 .cfi_restore_state + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + ARM GAS /tmp/ccywxtmH.s page 115 + + + 1708 .loc 1 912 21 view .LVU542 + 1709 01ee 0326 movs r6, #3 + 1710 01f0 F3E7 b .L105 + 1711 .L131: + 1712 01f2 0326 movs r6, #3 + 1713 01f4 F1E7 b .L105 + 1714 .L132: + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 1715 .loc 1 961 21 view .LVU543 + 1716 01f6 0326 movs r6, #3 + 1717 01f8 EFE7 b .L105 + 1718 .L133: + 1719 01fa 0326 movs r6, #3 + 1720 01fc EDE7 b .L105 + 1721 .LVL84: + 1722 .L128: + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1723 .loc 1 833 3 view .LVU544 + 1724 01fe 0226 movs r6, #2 + 1725 0200 F1E7 b .L104 + 1726 .cfi_endproc + 1727 .LFE134: + 1729 .section .text.HAL_SPI_TransmitReceive,"ax",%progbits + 1730 .align 1 + 1731 .global HAL_SPI_TransmitReceive + 1732 .syntax unified + 1733 .thumb + 1734 .thumb_func + 1736 HAL_SPI_TransmitReceive: + 1737 .LVL85: + 1738 .LFB136: +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_TxXferCount; + 1739 .loc 1 1250 1 is_stmt 1 view -0 + 1740 .cfi_startproc + 1741 @ args = 4, pretend = 0, frame = 0 + 1742 @ frame_needed = 0, uses_anonymous_args = 0 +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_TxXferCount; + 1743 .loc 1 1250 1 is_stmt 0 view .LVU546 + 1744 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr} + 1745 .cfi_def_cfa_offset 32 + 1746 .cfi_offset 3, -32 + 1747 .cfi_offset 4, -28 + 1748 .cfi_offset 5, -24 + 1749 .cfi_offset 6, -20 + 1750 .cfi_offset 7, -16 + 1751 .cfi_offset 8, -12 + 1752 .cfi_offset 9, -8 + 1753 .cfi_offset 14, -4 + 1754 0004 1F46 mov r7, r3 + 1755 0006 089D ldr r5, [sp, #32] +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_RxXferCount; + 1756 .loc 1 1251 3 is_stmt 1 view .LVU547 +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; + 1757 .loc 1 1252 3 view .LVU548 +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; + 1758 .loc 1 1253 3 view .LVU549 +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + ARM GAS /tmp/ccywxtmH.s page 116 + + + 1759 .loc 1 1254 3 view .LVU550 +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 1760 .loc 1 1255 3 view .LVU551 +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 1761 .loc 1 1265 3 view .LVU552 + 1762 .LVL86: +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1763 .loc 1 1266 3 view .LVU553 +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1764 .loc 1 1269 3 view .LVU554 +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1765 .loc 1 1272 3 view .LVU555 +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1766 .loc 1 1272 3 view .LVU556 + 1767 0008 90F85C30 ldrb r3, [r0, #92] @ zero_extendqisi2 + 1768 .LVL87: +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1769 .loc 1 1272 3 is_stmt 0 view .LVU557 + 1770 000c 012B cmp r3, #1 + 1771 000e 00F06481 beq .L163 + 1772 0012 0446 mov r4, r0 + 1773 0014 8846 mov r8, r1 + 1774 0016 9146 mov r9, r2 +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1775 .loc 1 1272 3 is_stmt 1 discriminator 2 view .LVU558 + 1776 0018 0123 movs r3, #1 + 1777 001a 80F85C30 strb r3, [r0, #92] +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1778 .loc 1 1272 3 discriminator 2 view .LVU559 +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1779 .loc 1 1275 3 discriminator 2 view .LVU560 +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1780 .loc 1 1275 15 is_stmt 0 discriminator 2 view .LVU561 + 1781 001e FFF7FEFF bl HAL_GetTick + 1782 .LVL88: +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1783 .loc 1 1275 15 discriminator 2 view .LVU562 + 1784 0022 0646 mov r6, r0 + 1785 .LVL89: +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 1786 .loc 1 1278 3 is_stmt 1 discriminator 2 view .LVU563 +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 1787 .loc 1 1278 23 is_stmt 0 discriminator 2 view .LVU564 + 1788 0024 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 1789 0028 DBB2 uxtb r3, r3 + 1790 .LVL90: +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; + 1791 .loc 1 1279 3 is_stmt 1 discriminator 2 view .LVU565 +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; + 1792 .loc 1 1279 23 is_stmt 0 discriminator 2 view .LVU566 + 1793 002a 6268 ldr r2, [r4, #4] + 1794 .LVL91: +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_RxXferCount = Size; + 1795 .loc 1 1280 3 is_stmt 1 discriminator 2 view .LVU567 +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 1796 .loc 1 1281 3 discriminator 2 view .LVU568 +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + ARM GAS /tmp/ccywxtmH.s page 117 + + + 1797 .loc 1 1287 3 discriminator 2 view .LVU569 +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 1798 .loc 1 1287 6 is_stmt 0 discriminator 2 view .LVU570 + 1799 002c 012B cmp r3, #1 + 1800 002e 0AD0 beq .L138 +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 1801 .loc 1 1287 7 discriminator 1 view .LVU571 + 1802 0030 B2F5827F cmp r2, #260 + 1803 0034 40F03881 bne .L164 +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1804 .loc 1 1288 54 view .LVU572 + 1805 0038 A268 ldr r2, [r4, #8] + 1806 .LVL92: +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1807 .loc 1 1288 40 view .LVU573 + 1808 003a 002A cmp r2, #0 + 1809 003c 40F03D81 bne .L165 +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1810 .loc 1 1288 90 discriminator 1 view .LVU574 + 1811 0040 042B cmp r3, #4 + 1812 0042 40F03C81 bne .L166 + 1813 .L138: +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1814 .loc 1 1294 3 is_stmt 1 view .LVU575 +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1815 .loc 1 1294 6 is_stmt 0 view .LVU576 + 1816 0046 B8F1000F cmp r8, #0 + 1817 004a 00F03A81 beq .L167 +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1818 .loc 1 1294 25 discriminator 1 view .LVU577 + 1819 004e B9F1000F cmp r9, #0 + 1820 0052 00F03881 beq .L168 +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1821 .loc 1 1294 46 discriminator 2 view .LVU578 + 1822 0056 002F cmp r7, #0 + 1823 0058 00F03781 beq .L169 +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1824 .loc 1 1301 3 is_stmt 1 view .LVU579 +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1825 .loc 1 1301 11 is_stmt 0 view .LVU580 + 1826 005c 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 1827 .LVL93: +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1828 .loc 1 1301 11 view .LVU581 + 1829 0060 DBB2 uxtb r3, r3 +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1830 .loc 1 1301 6 view .LVU582 + 1831 0062 042B cmp r3, #4 + 1832 0064 02D0 beq .L140 +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1833 .loc 1 1303 5 is_stmt 1 view .LVU583 +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1834 .loc 1 1303 17 is_stmt 0 view .LVU584 + 1835 0066 0523 movs r3, #5 + 1836 0068 84F85D30 strb r3, [r4, #93] + 1837 .L140: +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + ARM GAS /tmp/ccywxtmH.s page 118 + + + 1838 .loc 1 1307 3 is_stmt 1 view .LVU585 +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + 1839 .loc 1 1307 21 is_stmt 0 view .LVU586 + 1840 006c 0023 movs r3, #0 + 1841 006e 2366 str r3, [r4, #96] +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 1842 .loc 1 1308 3 is_stmt 1 view .LVU587 +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 1843 .loc 1 1308 21 is_stmt 0 view .LVU588 + 1844 0070 C4F84090 str r9, [r4, #64] +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 1845 .loc 1 1309 3 is_stmt 1 view .LVU589 +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 1846 .loc 1 1309 21 is_stmt 0 view .LVU590 + 1847 0074 A4F84670 strh r7, [r4, #70] @ movhi +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 1848 .loc 1 1310 3 is_stmt 1 view .LVU591 +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 1849 .loc 1 1310 21 is_stmt 0 view .LVU592 + 1850 0078 A4F84470 strh r7, [r4, #68] @ movhi +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 1851 .loc 1 1311 3 is_stmt 1 view .LVU593 +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 1852 .loc 1 1311 21 is_stmt 0 view .LVU594 + 1853 007c C4F83880 str r8, [r4, #56] +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 1854 .loc 1 1312 3 is_stmt 1 view .LVU595 +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 1855 .loc 1 1312 21 is_stmt 0 view .LVU596 + 1856 0080 E787 strh r7, [r4, #62] @ movhi +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1857 .loc 1 1313 3 is_stmt 1 view .LVU597 +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1858 .loc 1 1313 21 is_stmt 0 view .LVU598 + 1859 0082 A787 strh r7, [r4, #60] @ movhi +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 1860 .loc 1 1316 3 is_stmt 1 view .LVU599 +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 1861 .loc 1 1316 21 is_stmt 0 view .LVU600 + 1862 0084 E364 str r3, [r4, #76] +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1863 .loc 1 1317 3 is_stmt 1 view .LVU601 +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1864 .loc 1 1317 21 is_stmt 0 view .LVU602 + 1865 0086 2365 str r3, [r4, #80] +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1866 .loc 1 1328 3 is_stmt 1 view .LVU603 +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1867 .loc 1 1328 18 is_stmt 0 view .LVU604 + 1868 0088 E368 ldr r3, [r4, #12] +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1869 .loc 1 1328 6 view .LVU605 + 1870 008a B3F5E06F cmp r3, #1792 + 1871 008e 01D8 bhi .L141 +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1872 .loc 1 1328 49 discriminator 1 view .LVU606 + 1873 0090 012F cmp r7, #1 + ARM GAS /tmp/ccywxtmH.s page 119 + + + 1874 0092 23D9 bls .L142 + 1875 .L141: +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1876 .loc 1 1331 5 is_stmt 1 view .LVU607 + 1877 0094 2268 ldr r2, [r4] + 1878 0096 5368 ldr r3, [r2, #4] + 1879 0098 23F48053 bic r3, r3, #4096 + 1880 009c 5360 str r3, [r2, #4] + 1881 .LVL94: + 1882 .L143: +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1883 .loc 1 1340 3 view .LVU608 +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1884 .loc 1 1340 12 is_stmt 0 view .LVU609 + 1885 009e 2368 ldr r3, [r4] +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1886 .loc 1 1340 22 view .LVU610 + 1887 00a0 1A68 ldr r2, [r3] +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1888 .loc 1 1340 6 view .LVU611 + 1889 00a2 12F0400F tst r2, #64 + 1890 00a6 03D1 bne .L144 +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1891 .loc 1 1343 5 is_stmt 1 view .LVU612 + 1892 00a8 1A68 ldr r2, [r3] + 1893 00aa 42F04002 orr r2, r2, #64 + 1894 00ae 1A60 str r2, [r3] + 1895 .L144: +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1896 .loc 1 1347 3 view .LVU613 +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1897 .loc 1 1347 17 is_stmt 0 view .LVU614 + 1898 00b0 E368 ldr r3, [r4, #12] +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1899 .loc 1 1347 6 view .LVU615 + 1900 00b2 B3F5E06F cmp r3, #1792 + 1901 00b6 58D9 bls .L145 +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1902 .loc 1 1349 5 is_stmt 1 view .LVU616 +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1903 .loc 1 1349 20 is_stmt 0 view .LVU617 + 1904 00b8 6368 ldr r3, [r4, #4] +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1905 .loc 1 1349 8 view .LVU618 + 1906 00ba 0BB1 cbz r3, .L146 +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1907 .loc 1 1349 45 discriminator 1 view .LVU619 + 1908 00bc 012F cmp r7, #1 + 1909 00be 0BD1 bne .L147 + 1910 .L146: +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1911 .loc 1 1351 7 is_stmt 1 view .LVU620 +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1912 .loc 1 1351 46 is_stmt 0 view .LVU621 + 1913 00c0 A26B ldr r2, [r4, #56] +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1914 .loc 1 1351 11 view .LVU622 + ARM GAS /tmp/ccywxtmH.s page 120 + + + 1915 00c2 2368 ldr r3, [r4] +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1916 .loc 1 1351 28 view .LVU623 + 1917 00c4 1288 ldrh r2, [r2] +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1918 .loc 1 1351 26 view .LVU624 + 1919 00c6 DA60 str r2, [r3, #12] +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1920 .loc 1 1352 7 is_stmt 1 view .LVU625 +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1921 .loc 1 1352 11 is_stmt 0 view .LVU626 + 1922 00c8 A36B ldr r3, [r4, #56] +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1923 .loc 1 1352 24 view .LVU627 + 1924 00ca 0233 adds r3, r3, #2 + 1925 00cc A363 str r3, [r4, #56] +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1926 .loc 1 1353 7 is_stmt 1 view .LVU628 +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1927 .loc 1 1353 11 is_stmt 0 view .LVU629 + 1928 00ce E38F ldrh r3, [r4, #62] + 1929 00d0 9BB2 uxth r3, r3 +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1930 .loc 1 1353 24 view .LVU630 + 1931 00d2 013B subs r3, r3, #1 + 1932 00d4 9BB2 uxth r3, r3 + 1933 00d6 E387 strh r3, [r4, #62] @ movhi + 1934 .L147: +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1935 .loc 1 1387 19 view .LVU631 + 1936 00d8 0127 movs r7, #1 + 1937 .LVL95: +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1938 .loc 1 1387 19 view .LVU632 + 1939 00da 31E0 b .L148 + 1940 .LVL96: + 1941 .L142: +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1942 .loc 1 1336 5 is_stmt 1 view .LVU633 + 1943 00dc 2268 ldr r2, [r4] + 1944 00de 5368 ldr r3, [r2, #4] + 1945 00e0 43F48053 orr r3, r3, #4096 + 1946 00e4 5360 str r3, [r2, #4] + 1947 .LVL97: +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1948 .loc 1 1336 5 is_stmt 0 view .LVU634 + 1949 00e6 DAE7 b .L143 + 1950 .LVL98: + 1951 .L175: +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1952 .loc 1 1360 9 is_stmt 1 view .LVU635 +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1953 .loc 1 1360 48 is_stmt 0 view .LVU636 + 1954 00e8 A26B ldr r2, [r4, #56] +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1955 .loc 1 1360 30 view .LVU637 + 1956 00ea 1288 ldrh r2, [r2] + ARM GAS /tmp/ccywxtmH.s page 121 + + +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1957 .loc 1 1360 28 view .LVU638 + 1958 00ec DA60 str r2, [r3, #12] +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1959 .loc 1 1361 9 is_stmt 1 view .LVU639 +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1960 .loc 1 1361 13 is_stmt 0 view .LVU640 + 1961 00ee A36B ldr r3, [r4, #56] +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1962 .loc 1 1361 26 view .LVU641 + 1963 00f0 0233 adds r3, r3, #2 + 1964 00f2 A363 str r3, [r4, #56] +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a reception (Rx). Tx not allowed */ + 1965 .loc 1 1362 9 is_stmt 1 view .LVU642 +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a reception (Rx). Tx not allowed */ + 1966 .loc 1 1362 13 is_stmt 0 view .LVU643 + 1967 00f4 E38F ldrh r3, [r4, #62] + 1968 00f6 9BB2 uxth r3, r3 +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a reception (Rx). Tx not allowed */ + 1969 .loc 1 1362 26 view .LVU644 + 1970 00f8 013B subs r3, r3, #1 + 1971 00fa 9BB2 uxth r3, r3 + 1972 00fc E387 strh r3, [r4, #62] @ movhi +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1973 .loc 1 1364 9 is_stmt 1 view .LVU645 + 1974 .LVL99: +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 1975 .loc 1 1364 19 is_stmt 0 view .LVU646 + 1976 00fe 0027 movs r7, #0 + 1977 .LVL100: + 1978 .L149: +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1979 .loc 1 1381 7 is_stmt 1 view .LVU647 +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1980 .loc 1 1381 12 is_stmt 0 view .LVU648 + 1981 0100 2368 ldr r3, [r4] + 1982 0102 9A68 ldr r2, [r3, #8] +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1983 .loc 1 1381 10 view .LVU649 + 1984 0104 12F0010F tst r2, #1 + 1985 0108 11D0 beq .L150 +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1986 .loc 1 1381 61 discriminator 1 view .LVU650 + 1987 010a B4F84620 ldrh r2, [r4, #70] + 1988 010e 92B2 uxth r2, r2 +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1989 .loc 1 1381 53 discriminator 1 view .LVU651 + 1990 0110 6AB1 cbz r2, .L150 +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 1991 .loc 1 1383 9 is_stmt 1 view .LVU652 +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 1992 .loc 1 1383 67 is_stmt 0 view .LVU653 + 1993 0112 DA68 ldr r2, [r3, #12] +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 1994 .loc 1 1383 27 view .LVU654 + 1995 0114 236C ldr r3, [r4, #64] +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + ARM GAS /tmp/ccywxtmH.s page 122 + + + 1996 .loc 1 1383 41 view .LVU655 + 1997 0116 1A80 strh r2, [r3] @ movhi +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 1998 .loc 1 1384 9 is_stmt 1 view .LVU656 +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 1999 .loc 1 1384 13 is_stmt 0 view .LVU657 + 2000 0118 236C ldr r3, [r4, #64] +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2001 .loc 1 1384 26 view .LVU658 + 2002 011a 0233 adds r3, r3, #2 + 2003 011c 2364 str r3, [r4, #64] +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a Transmission (Tx). Tx is allowed */ + 2004 .loc 1 1385 9 is_stmt 1 view .LVU659 +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a Transmission (Tx). Tx is allowed */ + 2005 .loc 1 1385 13 is_stmt 0 view .LVU660 + 2006 011e B4F84630 ldrh r3, [r4, #70] + 2007 0122 9BB2 uxth r3, r3 +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a Transmission (Tx). Tx is allowed */ + 2008 .loc 1 1385 26 view .LVU661 + 2009 0124 013B subs r3, r3, #1 + 2010 0126 9BB2 uxth r3, r3 + 2011 0128 A4F84630 strh r3, [r4, #70] @ movhi +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2012 .loc 1 1387 9 is_stmt 1 view .LVU662 + 2013 .LVL101: +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2014 .loc 1 1387 19 is_stmt 0 view .LVU663 + 2015 012c 0127 movs r7, #1 + 2016 .LVL102: + 2017 .L150: +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2018 .loc 1 1389 7 is_stmt 1 view .LVU664 +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2019 .loc 1 1389 13 is_stmt 0 view .LVU665 + 2020 012e FFF7FEFF bl HAL_GetTick + 2021 .LVL103: +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2022 .loc 1 1389 27 view .LVU666 + 2023 0132 831B subs r3, r0, r6 +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2024 .loc 1 1389 10 view .LVU667 + 2025 0134 AB42 cmp r3, r5 + 2026 0136 03D3 bcc .L148 +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2027 .loc 1 1389 53 discriminator 1 view .LVU668 + 2028 0138 B5F1FF3F cmp r5, #-1 + 2029 013c 40F0C780 bne .L170 + 2030 .LVL104: + 2031 .L148: +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2032 .loc 1 1355 37 is_stmt 1 view .LVU669 +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2033 .loc 1 1355 17 is_stmt 0 view .LVU670 + 2034 0140 E38F ldrh r3, [r4, #62] + 2035 0142 9BB2 uxth r3, r3 +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2036 .loc 1 1355 37 view .LVU671 + ARM GAS /tmp/ccywxtmH.s page 123 + + + 2037 0144 2BB9 cbnz r3, .L151 +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2038 .loc 1 1355 45 discriminator 1 view .LVU672 + 2039 0146 B4F84630 ldrh r3, [r4, #70] + 2040 014a 9BB2 uxth r3, r3 +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2041 .loc 1 1355 37 discriminator 1 view .LVU673 + 2042 014c 002B cmp r3, #0 + 2043 014e 00F0A180 beq .L152 + 2044 .L151: +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2045 .loc 1 1358 7 is_stmt 1 view .LVU674 +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2046 .loc 1 1358 12 is_stmt 0 view .LVU675 + 2047 0152 2368 ldr r3, [r4] + 2048 0154 9A68 ldr r2, [r3, #8] +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2049 .loc 1 1358 10 view .LVU676 + 2050 0156 12F0020F tst r2, #2 + 2051 015a D1D0 beq .L149 +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2052 .loc 1 1358 60 discriminator 1 view .LVU677 + 2053 015c E28F ldrh r2, [r4, #62] + 2054 015e 92B2 uxth r2, r2 +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2055 .loc 1 1358 52 discriminator 1 view .LVU678 + 2056 0160 002A cmp r2, #0 + 2057 0162 CDD0 beq .L149 +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2058 .loc 1 1358 80 discriminator 2 view .LVU679 + 2059 0164 002F cmp r7, #0 + 2060 0166 CBD0 beq .L149 + 2061 0168 BEE7 b .L175 + 2062 .LVL105: + 2063 .L145: +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2064 .loc 1 1399 5 is_stmt 1 view .LVU680 +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2065 .loc 1 1399 20 is_stmt 0 view .LVU681 + 2066 016a 6368 ldr r3, [r4, #4] +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2067 .loc 1 1399 8 view .LVU682 + 2068 016c 0BB1 cbz r3, .L153 +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2069 .loc 1 1399 45 discriminator 1 view .LVU683 + 2070 016e 012F cmp r7, #1 + 2071 0170 0FD1 bne .L154 + 2072 .L153: +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2073 .loc 1 1401 7 is_stmt 1 view .LVU684 +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2074 .loc 1 1401 15 is_stmt 0 view .LVU685 + 2075 0172 E38F ldrh r3, [r4, #62] + 2076 0174 9BB2 uxth r3, r3 +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2077 .loc 1 1401 10 view .LVU686 + 2078 0176 012B cmp r3, #1 + ARM GAS /tmp/ccywxtmH.s page 124 + + + 2079 0178 0DD9 bls .L155 +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2080 .loc 1 1403 9 is_stmt 1 view .LVU687 +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2081 .loc 1 1403 48 is_stmt 0 view .LVU688 + 2082 017a A26B ldr r2, [r4, #56] +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2083 .loc 1 1403 13 view .LVU689 + 2084 017c 2368 ldr r3, [r4] +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2085 .loc 1 1403 30 view .LVU690 + 2086 017e 1288 ldrh r2, [r2] +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2087 .loc 1 1403 28 view .LVU691 + 2088 0180 DA60 str r2, [r3, #12] +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 2089 .loc 1 1404 9 is_stmt 1 view .LVU692 +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 2090 .loc 1 1404 13 is_stmt 0 view .LVU693 + 2091 0182 A36B ldr r3, [r4, #56] +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 2092 .loc 1 1404 26 view .LVU694 + 2093 0184 0233 adds r3, r3, #2 + 2094 0186 A363 str r3, [r4, #56] +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2095 .loc 1 1405 9 is_stmt 1 view .LVU695 +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2096 .loc 1 1405 13 is_stmt 0 view .LVU696 + 2097 0188 E38F ldrh r3, [r4, #62] + 2098 018a 9BB2 uxth r3, r3 +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2099 .loc 1 1405 27 view .LVU697 + 2100 018c 023B subs r3, r3, #2 + 2101 018e 9BB2 uxth r3, r3 + 2102 0190 E387 strh r3, [r4, #62] @ movhi + 2103 .L154: +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2104 .loc 1 1469 19 view .LVU698 + 2105 0192 0127 movs r7, #1 + 2106 .LVL106: +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2107 .loc 1 1469 19 view .LVU699 + 2108 0194 49E0 b .L161 + 2109 .LVL107: + 2110 .L155: +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 2111 .loc 1 1409 9 is_stmt 1 view .LVU700 +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 2112 .loc 1 1409 54 is_stmt 0 view .LVU701 + 2113 0196 A26B ldr r2, [r4, #56] +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 2114 .loc 1 1409 31 view .LVU702 + 2115 0198 2368 ldr r3, [r4] +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 2116 .loc 1 1409 49 view .LVU703 + 2117 019a 1278 ldrb r2, [r2] @ zero_extendqisi2 +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + ARM GAS /tmp/ccywxtmH.s page 125 + + + 2118 .loc 1 1409 46 view .LVU704 + 2119 019c 1A73 strb r2, [r3, #12] +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 2120 .loc 1 1410 9 is_stmt 1 view .LVU705 +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 2121 .loc 1 1410 13 is_stmt 0 view .LVU706 + 2122 019e A36B ldr r3, [r4, #56] +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 2123 .loc 1 1410 25 view .LVU707 + 2124 01a0 0133 adds r3, r3, #1 + 2125 01a2 A363 str r3, [r4, #56] +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2126 .loc 1 1411 9 is_stmt 1 view .LVU708 +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2127 .loc 1 1411 13 is_stmt 0 view .LVU709 + 2128 01a4 E38F ldrh r3, [r4, #62] + 2129 01a6 9BB2 uxth r3, r3 +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2130 .loc 1 1411 26 view .LVU710 + 2131 01a8 013B subs r3, r3, #1 + 2132 01aa 9BB2 uxth r3, r3 + 2133 01ac E387 strh r3, [r4, #62] @ movhi + 2134 01ae F0E7 b .L154 + 2135 .LVL108: + 2136 .L177: +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2137 .loc 1 1419 9 is_stmt 1 view .LVU711 +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2138 .loc 1 1419 17 is_stmt 0 view .LVU712 + 2139 01b0 E28F ldrh r2, [r4, #62] + 2140 01b2 92B2 uxth r2, r2 +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2141 .loc 1 1419 12 view .LVU713 + 2142 01b4 012A cmp r2, #1 + 2143 01b6 0CD9 bls .L157 +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2144 .loc 1 1421 11 is_stmt 1 view .LVU714 +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2145 .loc 1 1421 50 is_stmt 0 view .LVU715 + 2146 01b8 A26B ldr r2, [r4, #56] +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2147 .loc 1 1421 32 view .LVU716 + 2148 01ba 1288 ldrh r2, [r2] +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 2149 .loc 1 1421 30 view .LVU717 + 2150 01bc DA60 str r2, [r3, #12] +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 2151 .loc 1 1422 11 is_stmt 1 view .LVU718 +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 2152 .loc 1 1422 15 is_stmt 0 view .LVU719 + 2153 01be A36B ldr r3, [r4, #56] +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 2154 .loc 1 1422 28 view .LVU720 + 2155 01c0 0233 adds r3, r3, #2 + 2156 01c2 A363 str r3, [r4, #56] +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2157 .loc 1 1423 11 is_stmt 1 view .LVU721 + ARM GAS /tmp/ccywxtmH.s page 126 + + +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2158 .loc 1 1423 15 is_stmt 0 view .LVU722 + 2159 01c4 E38F ldrh r3, [r4, #62] + 2160 01c6 9BB2 uxth r3, r3 +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2161 .loc 1 1423 29 view .LVU723 + 2162 01c8 023B subs r3, r3, #2 + 2163 01ca 9BB2 uxth r3, r3 + 2164 01cc E387 strh r3, [r4, #62] @ movhi +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2165 .loc 1 1432 19 view .LVU724 + 2166 01ce 0027 movs r7, #0 + 2167 .LVL109: +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2168 .loc 1 1432 19 view .LVU725 + 2169 01d0 3DE0 b .L156 + 2170 .LVL110: + 2171 .L157: +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 2172 .loc 1 1427 11 is_stmt 1 view .LVU726 +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 2173 .loc 1 1427 56 is_stmt 0 view .LVU727 + 2174 01d2 A26B ldr r2, [r4, #56] +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 2175 .loc 1 1427 51 view .LVU728 + 2176 01d4 1278 ldrb r2, [r2] @ zero_extendqisi2 +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 2177 .loc 1 1427 48 view .LVU729 + 2178 01d6 1A73 strb r2, [r3, #12] +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 2179 .loc 1 1428 11 is_stmt 1 view .LVU730 +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 2180 .loc 1 1428 15 is_stmt 0 view .LVU731 + 2181 01d8 A36B ldr r3, [r4, #56] +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 2182 .loc 1 1428 27 view .LVU732 + 2183 01da 0133 adds r3, r3, #1 + 2184 01dc A363 str r3, [r4, #56] +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2185 .loc 1 1429 11 is_stmt 1 view .LVU733 +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2186 .loc 1 1429 15 is_stmt 0 view .LVU734 + 2187 01de E38F ldrh r3, [r4, #62] + 2188 01e0 9BB2 uxth r3, r3 +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2189 .loc 1 1429 28 view .LVU735 + 2190 01e2 013B subs r3, r3, #1 + 2191 01e4 9BB2 uxth r3, r3 + 2192 01e6 E387 strh r3, [r4, #62] @ movhi +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2193 .loc 1 1432 19 view .LVU736 + 2194 01e8 0027 movs r7, #0 + 2195 .LVL111: +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2196 .loc 1 1432 19 view .LVU737 + 2197 01ea 30E0 b .L156 + 2198 .LVL112: + ARM GAS /tmp/ccywxtmH.s page 127 + + + 2199 .L178: +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2200 .loc 1 1459 13 is_stmt 1 view .LVU738 + 2201 01ec 2268 ldr r2, [r4] + 2202 01ee 5368 ldr r3, [r2, #4] + 2203 01f0 43F48053 orr r3, r3, #4096 + 2204 01f4 5360 str r3, [r2, #4] +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2205 .loc 1 1469 19 is_stmt 0 view .LVU739 + 2206 01f6 0127 movs r7, #1 + 2207 .LVL113: +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2208 .loc 1 1469 19 view .LVU740 + 2209 01f8 0DE0 b .L158 + 2210 .LVL114: + 2211 .L159: +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 2212 .loc 1 1464 11 is_stmt 1 view .LVU741 +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 2213 .loc 1 1464 28 is_stmt 0 view .LVU742 + 2214 01fa 226C ldr r2, [r4, #64] +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 2215 .loc 1 1464 44 view .LVU743 + 2216 01fc 1B7B ldrb r3, [r3, #12] @ zero_extendqisi2 +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 2217 .loc 1 1464 42 view .LVU744 + 2218 01fe 1370 strb r3, [r2] +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2219 .loc 1 1465 11 is_stmt 1 view .LVU745 +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2220 .loc 1 1465 15 is_stmt 0 view .LVU746 + 2221 0200 236C ldr r3, [r4, #64] +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2222 .loc 1 1465 27 view .LVU747 + 2223 0202 0133 adds r3, r3, #1 + 2224 0204 2364 str r3, [r4, #64] +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2225 .loc 1 1466 11 is_stmt 1 view .LVU748 +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2226 .loc 1 1466 15 is_stmt 0 view .LVU749 + 2227 0206 B4F84630 ldrh r3, [r4, #70] + 2228 020a 9BB2 uxth r3, r3 +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2229 .loc 1 1466 28 view .LVU750 + 2230 020c 013B subs r3, r3, #1 + 2231 020e 9BB2 uxth r3, r3 + 2232 0210 A4F84630 strh r3, [r4, #70] @ movhi +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2233 .loc 1 1469 19 view .LVU751 + 2234 0214 0127 movs r7, #1 + 2235 .LVL115: + 2236 .L158: +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2237 .loc 1 1471 7 is_stmt 1 view .LVU752 +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2238 .loc 1 1471 14 is_stmt 0 view .LVU753 + 2239 0216 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccywxtmH.s page 128 + + + 2240 .LVL116: +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2241 .loc 1 1471 28 view .LVU754 + 2242 021a 801B subs r0, r0, r6 +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2243 .loc 1 1471 10 view .LVU755 + 2244 021c A842 cmp r0, r5 + 2245 021e 02D3 bcc .L160 +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2246 .loc 1 1471 54 discriminator 1 view .LVU756 + 2247 0220 B5F1FF3F cmp r5, #-1 + 2248 0224 55D1 bne .L172 + 2249 .L160: +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2250 .loc 1 1471 87 discriminator 3 view .LVU757 + 2251 0226 002D cmp r5, #0 + 2252 0228 55D0 beq .L176 + 2253 .LVL117: + 2254 .L161: +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2255 .loc 1 1414 37 is_stmt 1 view .LVU758 +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2256 .loc 1 1414 17 is_stmt 0 view .LVU759 + 2257 022a E38F ldrh r3, [r4, #62] + 2258 022c 9BB2 uxth r3, r3 +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2259 .loc 1 1414 37 view .LVU760 + 2260 022e 23B9 cbnz r3, .L162 +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2261 .loc 1 1414 45 discriminator 1 view .LVU761 + 2262 0230 B4F84630 ldrh r3, [r4, #70] + 2263 0234 9BB2 uxth r3, r3 +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2264 .loc 1 1414 37 discriminator 1 view .LVU762 + 2265 0236 002B cmp r3, #0 + 2266 0238 2CD0 beq .L152 + 2267 .L162: +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2268 .loc 1 1417 7 is_stmt 1 view .LVU763 +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2269 .loc 1 1417 12 is_stmt 0 view .LVU764 + 2270 023a 2368 ldr r3, [r4] + 2271 023c 9A68 ldr r2, [r3, #8] +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2272 .loc 1 1417 10 view .LVU765 + 2273 023e 12F0020F tst r2, #2 + 2274 0242 04D0 beq .L156 +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2275 .loc 1 1417 60 discriminator 1 view .LVU766 + 2276 0244 E28F ldrh r2, [r4, #62] + 2277 0246 92B2 uxth r2, r2 +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2278 .loc 1 1417 52 discriminator 1 view .LVU767 + 2279 0248 0AB1 cbz r2, .L156 +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2280 .loc 1 1417 80 discriminator 2 view .LVU768 + 2281 024a 002F cmp r7, #0 + ARM GAS /tmp/ccywxtmH.s page 129 + + + 2282 024c B0D1 bne .L177 + 2283 .LVL118: + 2284 .L156: +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2285 .loc 1 1449 7 is_stmt 1 view .LVU769 +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2286 .loc 1 1449 12 is_stmt 0 view .LVU770 + 2287 024e 2368 ldr r3, [r4] + 2288 0250 9A68 ldr r2, [r3, #8] +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2289 .loc 1 1449 10 view .LVU771 + 2290 0252 12F0010F tst r2, #1 + 2291 0256 DED0 beq .L158 +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2292 .loc 1 1449 61 discriminator 1 view .LVU772 + 2293 0258 B4F84620 ldrh r2, [r4, #70] + 2294 025c 92B2 uxth r2, r2 +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2295 .loc 1 1449 53 discriminator 1 view .LVU773 + 2296 025e 002A cmp r2, #0 + 2297 0260 D9D0 beq .L158 +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2298 .loc 1 1451 9 is_stmt 1 view .LVU774 +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2299 .loc 1 1451 17 is_stmt 0 view .LVU775 + 2300 0262 B4F84620 ldrh r2, [r4, #70] + 2301 0266 92B2 uxth r2, r2 +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2302 .loc 1 1451 12 view .LVU776 + 2303 0268 012A cmp r2, #1 + 2304 026a C6D9 bls .L159 +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 2305 .loc 1 1453 11 is_stmt 1 view .LVU777 +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 2306 .loc 1 1453 69 is_stmt 0 view .LVU778 + 2307 026c DA68 ldr r2, [r3, #12] +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 2308 .loc 1 1453 29 view .LVU779 + 2309 026e 236C ldr r3, [r4, #64] +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 2310 .loc 1 1453 43 view .LVU780 + 2311 0270 1A80 strh r2, [r3] @ movhi +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + 2312 .loc 1 1454 11 is_stmt 1 view .LVU781 +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + 2313 .loc 1 1454 15 is_stmt 0 view .LVU782 + 2314 0272 236C ldr r3, [r4, #64] +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + 2315 .loc 1 1454 28 view .LVU783 + 2316 0274 0233 adds r3, r3, #2 + 2317 0276 2364 str r3, [r4, #64] +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount <= 1U) + 2318 .loc 1 1455 11 is_stmt 1 view .LVU784 +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount <= 1U) + 2319 .loc 1 1455 15 is_stmt 0 view .LVU785 + 2320 0278 B4F84630 ldrh r3, [r4, #70] + 2321 027c 9BB2 uxth r3, r3 + ARM GAS /tmp/ccywxtmH.s page 130 + + +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount <= 1U) + 2322 .loc 1 1455 29 view .LVU786 + 2323 027e 023B subs r3, r3, #2 + 2324 0280 9BB2 uxth r3, r3 + 2325 0282 A4F84630 strh r3, [r4, #70] @ movhi +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2326 .loc 1 1456 11 is_stmt 1 view .LVU787 +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2327 .loc 1 1456 19 is_stmt 0 view .LVU788 + 2328 0286 B4F84630 ldrh r3, [r4, #70] + 2329 028a 9BB2 uxth r3, r3 +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2330 .loc 1 1456 14 view .LVU789 + 2331 028c 012B cmp r3, #1 + 2332 028e ADD9 bls .L178 +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2333 .loc 1 1469 19 view .LVU790 + 2334 0290 0127 movs r7, #1 + 2335 .LVL119: +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2336 .loc 1 1469 19 view .LVU791 + 2337 0292 C0E7 b .L158 + 2338 .LVL120: + 2339 .L152: +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2340 .loc 1 1537 3 is_stmt 1 view .LVU792 +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2341 .loc 1 1537 7 is_stmt 0 view .LVU793 + 2342 0294 3246 mov r2, r6 + 2343 0296 2946 mov r1, r5 + 2344 0298 2046 mov r0, r4 + 2345 029a FFF7FEFF bl SPI_EndRxTxTransaction + 2346 .LVL121: +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2347 .loc 1 1537 6 view .LVU794 + 2348 029e 20B1 cbz r0, .L139 +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 2349 .loc 1 1539 5 is_stmt 1 view .LVU795 + 2350 .LVL122: +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2351 .loc 1 1540 5 view .LVU796 +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2352 .loc 1 1540 21 is_stmt 0 view .LVU797 + 2353 02a0 2023 movs r3, #32 + 2354 02a2 2366 str r3, [r4, #96] +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 2355 .loc 1 1539 15 view .LVU798 + 2356 02a4 0120 movs r0, #1 + 2357 02a6 00E0 b .L139 + 2358 .LVL123: + 2359 .L164: +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2360 .loc 1 1290 15 view .LVU799 + 2361 02a8 0220 movs r0, #2 + 2362 .LVL124: + 2363 .L139: +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + ARM GAS /tmp/ccywxtmH.s page 131 + + + 2364 .loc 1 1544 3 is_stmt 1 view .LVU800 +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 2365 .loc 1 1544 15 is_stmt 0 view .LVU801 + 2366 02aa 0123 movs r3, #1 + 2367 02ac 84F85D30 strb r3, [r4, #93] +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2368 .loc 1 1545 3 is_stmt 1 view .LVU802 +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2369 .loc 1 1545 3 view .LVU803 + 2370 02b0 0023 movs r3, #0 + 2371 02b2 84F85C30 strb r3, [r4, #92] +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2372 .loc 1 1545 3 view .LVU804 +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2373 .loc 1 1546 3 view .LVU805 + 2374 .LVL125: + 2375 .L137: +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2376 .loc 1 1547 1 is_stmt 0 view .LVU806 + 2377 02b6 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc} + 2378 .LVL126: + 2379 .L165: +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2380 .loc 1 1290 15 view .LVU807 + 2381 02ba 0220 movs r0, #2 + 2382 .LVL127: +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2383 .loc 1 1290 15 view .LVU808 + 2384 02bc F5E7 b .L139 + 2385 .LVL128: + 2386 .L166: +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2387 .loc 1 1290 15 view .LVU809 + 2388 02be 0220 movs r0, #2 + 2389 .LVL129: +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2390 .loc 1 1290 15 view .LVU810 + 2391 02c0 F3E7 b .L139 + 2392 .LVL130: + 2393 .L167: +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2394 .loc 1 1296 15 view .LVU811 + 2395 02c2 0120 movs r0, #1 + 2396 .LVL131: +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2397 .loc 1 1296 15 view .LVU812 + 2398 02c4 F1E7 b .L139 + 2399 .LVL132: + 2400 .L168: +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2401 .loc 1 1296 15 view .LVU813 + 2402 02c6 0120 movs r0, #1 + 2403 .LVL133: +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2404 .loc 1 1296 15 view .LVU814 + 2405 02c8 EFE7 b .L139 + 2406 .LVL134: + ARM GAS /tmp/ccywxtmH.s page 132 + + + 2407 .L169: +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2408 .loc 1 1296 15 view .LVU815 + 2409 02ca 0120 movs r0, #1 + 2410 .LVL135: +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2411 .loc 1 1296 15 view .LVU816 + 2412 02cc EDE7 b .L139 + 2413 .LVL136: + 2414 .L170: +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2415 .loc 1 1391 19 view .LVU817 + 2416 02ce 0320 movs r0, #3 + 2417 02d0 EBE7 b .L139 + 2418 .L172: +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2419 .loc 1 1473 19 view .LVU818 + 2420 02d2 0320 movs r0, #3 + 2421 02d4 E9E7 b .L139 + 2422 .L176: + 2423 02d6 0320 movs r0, #3 + 2424 02d8 E7E7 b .L139 + 2425 .LVL137: + 2426 .L163: +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2427 .loc 1 1272 3 view .LVU819 + 2428 02da 0220 movs r0, #2 + 2429 .LVL138: +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2430 .loc 1 1272 3 view .LVU820 + 2431 02dc EBE7 b .L137 + 2432 .cfi_endproc + 2433 .LFE136: + 2435 .section .text.HAL_SPI_Receive,"ax",%progbits + 2436 .align 1 + 2437 .global HAL_SPI_Receive + 2438 .syntax unified + 2439 .thumb + 2440 .thumb_func + 2442 HAL_SPI_Receive: + 2443 .LVL139: + 2444 .LFB135: +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 2445 .loc 1 1009 1 is_stmt 1 view -0 + 2446 .cfi_startproc + 2447 @ args = 0, pretend = 0, frame = 0 + 2448 @ frame_needed = 0, uses_anonymous_args = 0 +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 2449 .loc 1 1009 1 is_stmt 0 view .LVU822 + 2450 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 2451 .cfi_def_cfa_offset 28 + 2452 .cfi_offset 4, -28 + 2453 .cfi_offset 5, -24 + 2454 .cfi_offset 6, -20 + 2455 .cfi_offset 7, -16 + 2456 .cfi_offset 8, -12 + 2457 .cfi_offset 9, -8 + ARM GAS /tmp/ccywxtmH.s page 133 + + + 2458 .cfi_offset 14, -4 + 2459 0004 83B0 sub sp, sp, #12 + 2460 .cfi_def_cfa_offset 40 + 2461 0006 0446 mov r4, r0 + 2462 0008 8846 mov r8, r1 + 2463 000a 9146 mov r9, r2 + 2464 000c 1D46 mov r5, r3 +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 2465 .loc 1 1015 3 is_stmt 1 view .LVU823 +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2466 .loc 1 1016 3 view .LVU824 + 2467 .LVL140: +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2468 .loc 1 1018 3 view .LVU825 +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2469 .loc 1 1018 18 is_stmt 0 view .LVU826 + 2470 000e 4068 ldr r0, [r0, #4] + 2471 .LVL141: +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2472 .loc 1 1018 6 view .LVU827 + 2473 0010 B0F5827F cmp r0, #260 + 2474 0014 43D0 beq .L206 + 2475 .LVL142: + 2476 .L180: +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2477 .loc 1 1026 3 is_stmt 1 view .LVU828 +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2478 .loc 1 1026 3 view .LVU829 + 2479 0016 94F85C30 ldrb r3, [r4, #92] @ zero_extendqisi2 + 2480 001a 012B cmp r3, #1 + 2481 001c 00F0C380 beq .L199 +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2482 .loc 1 1026 3 discriminator 2 view .LVU830 + 2483 0020 0123 movs r3, #1 + 2484 0022 84F85C30 strb r3, [r4, #92] +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2485 .loc 1 1026 3 discriminator 2 view .LVU831 +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2486 .loc 1 1029 3 discriminator 2 view .LVU832 +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2487 .loc 1 1029 15 is_stmt 0 discriminator 2 view .LVU833 + 2488 0026 FFF7FEFF bl HAL_GetTick + 2489 .LVL143: +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2490 .loc 1 1029 15 discriminator 2 view .LVU834 + 2491 002a 0746 mov r7, r0 + 2492 .LVL144: +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2493 .loc 1 1031 3 is_stmt 1 discriminator 2 view .LVU835 +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2494 .loc 1 1031 11 is_stmt 0 discriminator 2 view .LVU836 + 2495 002c 94F85D60 ldrb r6, [r4, #93] @ zero_extendqisi2 + 2496 0030 F6B2 uxtb r6, r6 +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2497 .loc 1 1031 6 discriminator 2 view .LVU837 + 2498 0032 012E cmp r6, #1 + 2499 0034 40F0A480 bne .L200 + ARM GAS /tmp/ccywxtmH.s page 134 + + +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2500 .loc 1 1037 3 is_stmt 1 view .LVU838 +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2501 .loc 1 1037 6 is_stmt 0 view .LVU839 + 2502 0038 B8F1000F cmp r8, #0 + 2503 003c 00F0A180 beq .L182 +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2504 .loc 1 1037 23 discriminator 1 view .LVU840 + 2505 0040 B9F1000F cmp r9, #0 + 2506 0044 00F09D80 beq .L182 +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2507 .loc 1 1044 3 is_stmt 1 view .LVU841 +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2508 .loc 1 1044 21 is_stmt 0 view .LVU842 + 2509 0048 0423 movs r3, #4 + 2510 004a 84F85D30 strb r3, [r4, #93] +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 2511 .loc 1 1045 3 is_stmt 1 view .LVU843 +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 2512 .loc 1 1045 21 is_stmt 0 view .LVU844 + 2513 004e 0023 movs r3, #0 + 2514 0050 2366 str r3, [r4, #96] +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 2515 .loc 1 1046 3 is_stmt 1 view .LVU845 +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 2516 .loc 1 1046 21 is_stmt 0 view .LVU846 + 2517 0052 C4F84080 str r8, [r4, #64] +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 2518 .loc 1 1047 3 is_stmt 1 view .LVU847 +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 2519 .loc 1 1047 21 is_stmt 0 view .LVU848 + 2520 0056 A4F84490 strh r9, [r4, #68] @ movhi +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2521 .loc 1 1048 3 is_stmt 1 view .LVU849 +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2522 .loc 1 1048 21 is_stmt 0 view .LVU850 + 2523 005a A4F84690 strh r9, [r4, #70] @ movhi +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 2524 .loc 1 1051 3 is_stmt 1 view .LVU851 +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 2525 .loc 1 1051 21 is_stmt 0 view .LVU852 + 2526 005e A363 str r3, [r4, #56] +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 2527 .loc 1 1052 3 is_stmt 1 view .LVU853 +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 2528 .loc 1 1052 21 is_stmt 0 view .LVU854 + 2529 0060 A387 strh r3, [r4, #60] @ movhi +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 2530 .loc 1 1053 3 is_stmt 1 view .LVU855 +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 2531 .loc 1 1053 21 is_stmt 0 view .LVU856 + 2532 0062 E387 strh r3, [r4, #62] @ movhi +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 2533 .loc 1 1054 3 is_stmt 1 view .LVU857 +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 2534 .loc 1 1054 21 is_stmt 0 view .LVU858 + 2535 0064 E364 str r3, [r4, #76] + ARM GAS /tmp/ccywxtmH.s page 135 + + +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2536 .loc 1 1055 3 is_stmt 1 view .LVU859 +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2537 .loc 1 1055 21 is_stmt 0 view .LVU860 + 2538 0066 2365 str r3, [r4, #80] +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2539 .loc 1 1068 3 is_stmt 1 view .LVU861 +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2540 .loc 1 1068 17 is_stmt 0 view .LVU862 + 2541 0068 E368 ldr r3, [r4, #12] +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2542 .loc 1 1068 6 view .LVU863 + 2543 006a B3F5E06F cmp r3, #1792 + 2544 006e 24D9 bls .L183 +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2545 .loc 1 1071 5 is_stmt 1 view .LVU864 + 2546 0070 2268 ldr r2, [r4] + 2547 0072 5368 ldr r3, [r2, #4] + 2548 0074 23F48053 bic r3, r3, #4096 + 2549 0078 5360 str r3, [r2, #4] + 2550 .L184: +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2551 .loc 1 1080 3 view .LVU865 +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2552 .loc 1 1080 17 is_stmt 0 view .LVU866 + 2553 007a A368 ldr r3, [r4, #8] +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2554 .loc 1 1080 6 view .LVU867 + 2555 007c B3F5004F cmp r3, #32768 + 2556 0080 21D0 beq .L207 + 2557 .L185: +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2558 .loc 1 1088 3 is_stmt 1 view .LVU868 +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2559 .loc 1 1088 12 is_stmt 0 view .LVU869 + 2560 0082 2368 ldr r3, [r4] +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2561 .loc 1 1088 22 view .LVU870 + 2562 0084 1A68 ldr r2, [r3] +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2563 .loc 1 1088 6 view .LVU871 + 2564 0086 12F0400F tst r2, #64 + 2565 008a 03D1 bne .L186 +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2566 .loc 1 1091 5 is_stmt 1 view .LVU872 + 2567 008c 1A68 ldr r2, [r3] + 2568 008e 42F04002 orr r2, r2, #64 + 2569 0092 1A60 str r2, [r3] + 2570 .L186: +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2571 .loc 1 1095 3 view .LVU873 +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2572 .loc 1 1095 17 is_stmt 0 view .LVU874 + 2573 0094 E368 ldr r3, [r4, #12] +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2574 .loc 1 1095 6 view .LVU875 + 2575 0096 B3F5E06F cmp r3, #1792 + ARM GAS /tmp/ccywxtmH.s page 136 + + + 2576 009a 29D9 bls .L187 + 2577 009c 4AE0 b .L188 + 2578 .LVL145: + 2579 .L206: +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2580 .loc 1 1018 58 discriminator 1 view .LVU876 + 2581 009e A368 ldr r3, [r4, #8] + 2582 .LVL146: +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2583 .loc 1 1018 44 discriminator 1 view .LVU877 + 2584 00a0 002B cmp r3, #0 + 2585 00a2 B8D1 bne .L180 +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line + 2586 .loc 1 1020 5 is_stmt 1 view .LVU878 +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line + 2587 .loc 1 1020 17 is_stmt 0 view .LVU879 + 2588 00a4 0423 movs r3, #4 + 2589 00a6 84F85D30 strb r3, [r4, #93] +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2590 .loc 1 1022 5 is_stmt 1 view .LVU880 +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2591 .loc 1 1022 12 is_stmt 0 view .LVU881 + 2592 00aa 0095 str r5, [sp] + 2593 00ac 1346 mov r3, r2 + 2594 00ae 0A46 mov r2, r1 + 2595 .LVL147: +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2596 .loc 1 1022 12 view .LVU882 + 2597 00b0 2046 mov r0, r4 + 2598 00b2 FFF7FEFF bl HAL_SPI_TransmitReceive + 2599 .LVL148: +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2600 .loc 1 1022 12 view .LVU883 + 2601 00b6 0646 mov r6, r0 + 2602 00b8 69E0 b .L181 + 2603 .LVL149: + 2604 .L183: +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2605 .loc 1 1076 5 is_stmt 1 view .LVU884 + 2606 00ba 2268 ldr r2, [r4] + 2607 00bc 5368 ldr r3, [r2, #4] + 2608 00be 43F48053 orr r3, r3, #4096 + 2609 00c2 5360 str r3, [r2, #4] + 2610 00c4 D9E7 b .L184 + 2611 .L207: +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); + 2612 .loc 1 1083 5 view .LVU885 + 2613 00c6 2268 ldr r2, [r4] + 2614 00c8 1368 ldr r3, [r2] + 2615 00ca 23F04003 bic r3, r3, #64 + 2616 00ce 1360 str r3, [r2] +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2617 .loc 1 1084 5 view .LVU886 + 2618 00d0 2268 ldr r2, [r4] + 2619 00d2 1368 ldr r3, [r2] + 2620 00d4 23F48043 bic r3, r3, #16384 + 2621 00d8 1360 str r3, [r2] + ARM GAS /tmp/ccywxtmH.s page 137 + + + 2622 00da D2E7 b .L185 + 2623 .LVL150: + 2624 .L189: +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2625 .loc 1 1111 9 view .LVU887 +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2626 .loc 1 1111 16 is_stmt 0 view .LVU888 + 2627 00dc FFF7FEFF bl HAL_GetTick + 2628 .LVL151: +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2629 .loc 1 1111 30 view .LVU889 + 2630 00e0 C01B subs r0, r0, r7 +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2631 .loc 1 1111 12 view .LVU890 + 2632 00e2 A842 cmp r0, r5 + 2633 00e4 02D3 bcc .L191 +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2634 .loc 1 1111 56 discriminator 1 view .LVU891 + 2635 00e6 B5F1FF3F cmp r5, #-1 + 2636 00ea 54D1 bne .L201 + 2637 .L191: +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2638 .loc 1 1111 87 discriminator 3 view .LVU892 + 2639 00ec 002D cmp r5, #0 + 2640 00ee 54D0 beq .L202 + 2641 .L187: +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2642 .loc 1 1098 30 is_stmt 1 view .LVU893 +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2643 .loc 1 1098 16 is_stmt 0 view .LVU894 + 2644 00f0 B4F84630 ldrh r3, [r4, #70] + 2645 00f4 9BB2 uxth r3, r3 +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2646 .loc 1 1098 30 view .LVU895 + 2647 00f6 002B cmp r3, #0 + 2648 00f8 36D0 beq .L193 +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2649 .loc 1 1101 7 is_stmt 1 view .LVU896 +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2650 .loc 1 1101 11 is_stmt 0 view .LVU897 + 2651 00fa 2368 ldr r3, [r4] + 2652 00fc 9A68 ldr r2, [r3, #8] +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2653 .loc 1 1101 10 view .LVU898 + 2654 00fe 12F0010F tst r2, #1 + 2655 0102 EBD0 beq .L189 +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint8_t); + 2656 .loc 1 1104 9 is_stmt 1 view .LVU899 +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint8_t); + 2657 .loc 1 1104 27 is_stmt 0 view .LVU900 + 2658 0104 226C ldr r2, [r4, #64] +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint8_t); + 2659 .loc 1 1104 43 view .LVU901 + 2660 0106 1B7B ldrb r3, [r3, #12] @ zero_extendqisi2 +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint8_t); + 2661 .loc 1 1104 41 view .LVU902 + 2662 0108 1370 strb r3, [r2] + ARM GAS /tmp/ccywxtmH.s page 138 + + +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2663 .loc 1 1105 9 is_stmt 1 view .LVU903 +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2664 .loc 1 1105 13 is_stmt 0 view .LVU904 + 2665 010a 236C ldr r3, [r4, #64] +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2666 .loc 1 1105 26 view .LVU905 + 2667 010c 0133 adds r3, r3, #1 + 2668 010e 2364 str r3, [r4, #64] +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2669 .loc 1 1106 9 is_stmt 1 view .LVU906 +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2670 .loc 1 1106 13 is_stmt 0 view .LVU907 + 2671 0110 B4F84630 ldrh r3, [r4, #70] + 2672 0114 9BB2 uxth r3, r3 +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2673 .loc 1 1106 26 view .LVU908 + 2674 0116 013B subs r3, r3, #1 + 2675 0118 9BB2 uxth r3, r3 + 2676 011a A4F84630 strh r3, [r4, #70] @ movhi + 2677 011e E7E7 b .L187 + 2678 .L194: +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2679 .loc 1 1134 9 is_stmt 1 view .LVU909 +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2680 .loc 1 1134 16 is_stmt 0 view .LVU910 + 2681 0120 FFF7FEFF bl HAL_GetTick + 2682 .LVL152: +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2683 .loc 1 1134 30 view .LVU911 + 2684 0124 C01B subs r0, r0, r7 +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2685 .loc 1 1134 12 view .LVU912 + 2686 0126 A842 cmp r0, r5 + 2687 0128 02D3 bcc .L196 +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2688 .loc 1 1134 56 discriminator 1 view .LVU913 + 2689 012a B5F1FF3F cmp r5, #-1 + 2690 012e 36D1 bne .L203 + 2691 .L196: +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2692 .loc 1 1134 87 discriminator 3 view .LVU914 + 2693 0130 002D cmp r5, #0 + 2694 0132 36D0 beq .L204 + 2695 .L188: +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2696 .loc 1 1122 30 is_stmt 1 view .LVU915 +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2697 .loc 1 1122 16 is_stmt 0 view .LVU916 + 2698 0134 B4F84630 ldrh r3, [r4, #70] + 2699 0138 9BB2 uxth r3, r3 +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2700 .loc 1 1122 30 view .LVU917 + 2701 013a ABB1 cbz r3, .L193 +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2702 .loc 1 1125 7 is_stmt 1 view .LVU918 +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 139 + + + 2703 .loc 1 1125 11 is_stmt 0 view .LVU919 + 2704 013c 2368 ldr r3, [r4] + 2705 013e 9A68 ldr r2, [r3, #8] +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2706 .loc 1 1125 10 view .LVU920 + 2707 0140 12F0010F tst r2, #1 + 2708 0144 ECD0 beq .L194 +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 2709 .loc 1 1127 9 is_stmt 1 view .LVU921 +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 2710 .loc 1 1127 67 is_stmt 0 view .LVU922 + 2711 0146 DA68 ldr r2, [r3, #12] +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 2712 .loc 1 1127 27 view .LVU923 + 2713 0148 236C ldr r3, [r4, #64] +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 2714 .loc 1 1127 41 view .LVU924 + 2715 014a 1A80 strh r2, [r3] @ movhi +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2716 .loc 1 1128 9 is_stmt 1 view .LVU925 +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2717 .loc 1 1128 13 is_stmt 0 view .LVU926 + 2718 014c 236C ldr r3, [r4, #64] +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 2719 .loc 1 1128 26 view .LVU927 + 2720 014e 0233 adds r3, r3, #2 + 2721 0150 2364 str r3, [r4, #64] +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2722 .loc 1 1129 9 is_stmt 1 view .LVU928 +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2723 .loc 1 1129 13 is_stmt 0 view .LVU929 + 2724 0152 B4F846C0 ldrh ip, [r4, #70] + 2725 0156 1FFA8CFC uxth ip, ip +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2726 .loc 1 1129 26 view .LVU930 + 2727 015a 0CF1FF3C add ip, ip, #-1 + 2728 015e 1FFA8CFC uxth ip, ip + 2729 0162 A4F846C0 strh ip, [r4, #70] @ movhi + 2730 0166 E5E7 b .L188 + 2731 .L193: +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2732 .loc 1 1213 3 is_stmt 1 view .LVU931 +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2733 .loc 1 1213 7 is_stmt 0 view .LVU932 + 2734 0168 3A46 mov r2, r7 + 2735 016a 2946 mov r1, r5 + 2736 016c 2046 mov r0, r4 + 2737 016e FFF7FEFF bl SPI_EndRxTransaction + 2738 .LVL153: +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2739 .loc 1 1213 6 view .LVU933 + 2740 0172 08B1 cbz r0, .L198 +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2741 .loc 1 1215 5 is_stmt 1 view .LVU934 +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2742 .loc 1 1215 21 is_stmt 0 view .LVU935 + 2743 0174 2023 movs r3, #32 + ARM GAS /tmp/ccywxtmH.s page 140 + + + 2744 0176 2366 str r3, [r4, #96] + 2745 .L198: +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2746 .loc 1 1227 3 is_stmt 1 view .LVU936 +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2747 .loc 1 1227 11 is_stmt 0 view .LVU937 + 2748 0178 236E ldr r3, [r4, #96] +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2749 .loc 1 1227 6 view .LVU938 + 2750 017a 13B9 cbnz r3, .L182 +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2751 .loc 1 1016 21 view .LVU939 + 2752 017c 0026 movs r6, #0 + 2753 017e 00E0 b .L182 + 2754 .LVL154: + 2755 .L200: +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2756 .loc 1 1033 15 view .LVU940 + 2757 0180 0226 movs r6, #2 + 2758 .LVL155: + 2759 .L182: +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 2760 .loc 1 1233 3 is_stmt 1 view .LVU941 +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 2761 .loc 1 1233 15 is_stmt 0 view .LVU942 + 2762 0182 0123 movs r3, #1 + 2763 0184 84F85D30 strb r3, [r4, #93] +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2764 .loc 1 1234 3 is_stmt 1 view .LVU943 +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2765 .loc 1 1234 3 view .LVU944 + 2766 0188 0023 movs r3, #0 + 2767 018a 84F85C30 strb r3, [r4, #92] +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2768 .loc 1 1234 3 view .LVU945 +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2769 .loc 1 1235 3 view .LVU946 + 2770 .LVL156: + 2771 .L181: +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2772 .loc 1 1236 1 is_stmt 0 view .LVU947 + 2773 018e 3046 mov r0, r6 + 2774 0190 03B0 add sp, sp, #12 + 2775 .cfi_remember_state + 2776 .cfi_def_cfa_offset 28 + 2777 @ sp needed + 2778 0192 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 2779 .LVL157: + 2780 .L201: + 2781 .cfi_restore_state +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2782 .loc 1 1113 21 view .LVU948 + 2783 0196 0326 movs r6, #3 + 2784 0198 F3E7 b .L182 + 2785 .L202: + 2786 019a 0326 movs r6, #3 + 2787 019c F1E7 b .L182 + ARM GAS /tmp/ccywxtmH.s page 141 + + + 2788 .L203: +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2789 .loc 1 1136 21 view .LVU949 + 2790 019e 0326 movs r6, #3 + 2791 01a0 EFE7 b .L182 + 2792 .L204: + 2793 01a2 0326 movs r6, #3 + 2794 01a4 EDE7 b .L182 + 2795 .LVL158: + 2796 .L199: +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2797 .loc 1 1026 3 view .LVU950 + 2798 01a6 0226 movs r6, #2 + 2799 01a8 F1E7 b .L181 + 2800 .cfi_endproc + 2801 .LFE135: + 2803 .section .text.HAL_SPI_Transmit_IT,"ax",%progbits + 2804 .align 1 + 2805 .global HAL_SPI_Transmit_IT + 2806 .syntax unified + 2807 .thumb + 2808 .thumb_func + 2810 HAL_SPI_Transmit_IT: + 2811 .LVL159: + 2812 .LFB137: +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 2813 .loc 1 1558 1 is_stmt 1 view -0 + 2814 .cfi_startproc + 2815 @ args = 0, pretend = 0, frame = 0 + 2816 @ frame_needed = 0, uses_anonymous_args = 0 + 2817 @ link register save eliminated. +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 2818 .loc 1 1558 1 is_stmt 0 view .LVU952 + 2819 0000 0346 mov r3, r0 +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2820 .loc 1 1559 3 is_stmt 1 view .LVU953 + 2821 .LVL160: +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2822 .loc 1 1562 3 view .LVU954 +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2823 .loc 1 1565 3 view .LVU955 +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2824 .loc 1 1565 3 view .LVU956 + 2825 0002 90F85C00 ldrb r0, [r0, #92] @ zero_extendqisi2 + 2826 .LVL161: +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2827 .loc 1 1565 3 is_stmt 0 view .LVU957 + 2828 0006 0128 cmp r0, #1 + 2829 0008 4CD0 beq .L214 +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2830 .loc 1 1565 3 is_stmt 1 discriminator 2 view .LVU958 + 2831 000a 0120 movs r0, #1 + 2832 000c 83F85C00 strb r0, [r3, #92] +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2833 .loc 1 1565 3 discriminator 2 view .LVU959 +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2834 .loc 1 1567 3 discriminator 2 view .LVU960 + ARM GAS /tmp/ccywxtmH.s page 142 + + +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2835 .loc 1 1567 6 is_stmt 0 discriminator 2 view .LVU961 + 2836 0010 0029 cmp r1, #0 + 2837 0012 3CD0 beq .L215 +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2838 .loc 1 1567 23 discriminator 1 view .LVU962 + 2839 0014 002A cmp r2, #0 + 2840 0016 3CD0 beq .L216 +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2841 .loc 1 1573 3 is_stmt 1 view .LVU963 +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2842 .loc 1 1573 11 is_stmt 0 view .LVU964 + 2843 0018 93F85D00 ldrb r0, [r3, #93] @ zero_extendqisi2 + 2844 001c C0B2 uxtb r0, r0 +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2845 .loc 1 1573 6 view .LVU965 + 2846 001e 0128 cmp r0, #1 + 2847 0020 3CD1 bne .L217 +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2848 .loc 1 1580 3 is_stmt 1 view .LVU966 +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2849 .loc 1 1580 21 is_stmt 0 view .LVU967 + 2850 0022 0320 movs r0, #3 + 2851 0024 83F85D00 strb r0, [r3, #93] +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 2852 .loc 1 1581 3 is_stmt 1 view .LVU968 +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 2853 .loc 1 1581 21 is_stmt 0 view .LVU969 + 2854 0028 0020 movs r0, #0 + 2855 002a 1866 str r0, [r3, #96] +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 2856 .loc 1 1582 3 is_stmt 1 view .LVU970 +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 2857 .loc 1 1582 21 is_stmt 0 view .LVU971 + 2858 002c 9963 str r1, [r3, #56] +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 2859 .loc 1 1583 3 is_stmt 1 view .LVU972 +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 2860 .loc 1 1583 21 is_stmt 0 view .LVU973 + 2861 002e 9A87 strh r2, [r3, #60] @ movhi +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2862 .loc 1 1584 3 is_stmt 1 view .LVU974 +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2863 .loc 1 1584 21 is_stmt 0 view .LVU975 + 2864 0030 DA87 strh r2, [r3, #62] @ movhi +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 2865 .loc 1 1587 3 is_stmt 1 view .LVU976 +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 2866 .loc 1 1587 21 is_stmt 0 view .LVU977 + 2867 0032 1864 str r0, [r3, #64] +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 2868 .loc 1 1588 3 is_stmt 1 view .LVU978 +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 2869 .loc 1 1588 21 is_stmt 0 view .LVU979 + 2870 0034 A3F84400 strh r0, [r3, #68] @ movhi +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 2871 .loc 1 1589 3 is_stmt 1 view .LVU980 + ARM GAS /tmp/ccywxtmH.s page 143 + + +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 2872 .loc 1 1589 21 is_stmt 0 view .LVU981 + 2873 0038 A3F84600 strh r0, [r3, #70] @ movhi +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2874 .loc 1 1590 3 is_stmt 1 view .LVU982 +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2875 .loc 1 1590 21 is_stmt 0 view .LVU983 + 2876 003c D864 str r0, [r3, #76] +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2877 .loc 1 1593 3 is_stmt 1 view .LVU984 +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2878 .loc 1 1593 17 is_stmt 0 view .LVU985 + 2879 003e DA68 ldr r2, [r3, #12] + 2880 .LVL162: +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2881 .loc 1 1593 6 view .LVU986 + 2882 0040 B2F5E06F cmp r2, #1792 + 2883 0044 15D9 bls .L211 +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2884 .loc 1 1595 5 is_stmt 1 view .LVU987 +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2885 .loc 1 1595 17 is_stmt 0 view .LVU988 + 2886 0046 184A ldr r2, .L220 + 2887 0048 1A65 str r2, [r3, #80] + 2888 .L212: +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2889 .loc 1 1603 3 is_stmt 1 view .LVU989 +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2890 .loc 1 1603 17 is_stmt 0 view .LVU990 + 2891 004a 9A68 ldr r2, [r3, #8] +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2892 .loc 1 1603 6 view .LVU991 + 2893 004c B2F5004F cmp r2, #32768 + 2894 0050 12D0 beq .L219 + 2895 .LVL163: + 2896 .L213: +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2897 .loc 1 1619 3 is_stmt 1 view .LVU992 + 2898 0052 1968 ldr r1, [r3] + 2899 0054 4A68 ldr r2, [r1, #4] + 2900 0056 42F0A002 orr r2, r2, #160 + 2901 005a 4A60 str r2, [r1, #4] +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2902 .loc 1 1623 3 view .LVU993 +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2903 .loc 1 1623 12 is_stmt 0 view .LVU994 + 2904 005c 1A68 ldr r2, [r3] +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2905 .loc 1 1623 22 view .LVU995 + 2906 005e 1168 ldr r1, [r2] +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2907 .loc 1 1623 6 view .LVU996 + 2908 0060 11F0400F tst r1, #64 + 2909 0064 1CD1 bne .L218 +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2910 .loc 1 1626 5 is_stmt 1 view .LVU997 + 2911 0066 1168 ldr r1, [r2] + ARM GAS /tmp/ccywxtmH.s page 144 + + + 2912 0068 41F04001 orr r1, r1, #64 + 2913 006c 1160 str r1, [r2] +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2914 .loc 1 1559 21 is_stmt 0 view .LVU998 + 2915 006e 0020 movs r0, #0 + 2916 0070 10E0 b .L210 + 2917 .LVL164: + 2918 .L211: +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2919 .loc 1 1599 5 is_stmt 1 view .LVU999 +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2920 .loc 1 1599 17 is_stmt 0 view .LVU1000 + 2921 0072 0E4A ldr r2, .L220+4 + 2922 0074 1A65 str r2, [r3, #80] + 2923 0076 E8E7 b .L212 + 2924 .L219: +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 2925 .loc 1 1606 5 is_stmt 1 view .LVU1001 + 2926 0078 1968 ldr r1, [r3] + 2927 .LVL165: +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 2928 .loc 1 1606 5 is_stmt 0 view .LVU1002 + 2929 007a 0A68 ldr r2, [r1] + 2930 007c 22F04002 bic r2, r2, #64 + 2931 0080 0A60 str r2, [r1] + 2932 .LVL166: +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2933 .loc 1 1607 5 is_stmt 1 view .LVU1003 + 2934 0082 1968 ldr r1, [r3] + 2935 0084 0A68 ldr r2, [r1] + 2936 0086 42F48042 orr r2, r2, #16384 + 2937 008a 0A60 str r2, [r1] + 2938 008c E1E7 b .L213 + 2939 .LVL167: + 2940 .L215: +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2941 .loc 1 1569 15 is_stmt 0 view .LVU1004 + 2942 008e 0120 movs r0, #1 + 2943 0090 00E0 b .L210 + 2944 .L216: + 2945 0092 0120 movs r0, #1 + 2946 .LVL168: + 2947 .L210: +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2948 .loc 1 1630 3 is_stmt 1 view .LVU1005 +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2949 .loc 1 1630 3 view .LVU1006 + 2950 0094 0022 movs r2, #0 + 2951 0096 83F85C20 strb r2, [r3, #92] +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2952 .loc 1 1630 3 view .LVU1007 +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2953 .loc 1 1631 3 view .LVU1008 +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2954 .loc 1 1631 10 is_stmt 0 view .LVU1009 + 2955 009a 7047 bx lr + 2956 .LVL169: + ARM GAS /tmp/ccywxtmH.s page 145 + + + 2957 .L217: +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2958 .loc 1 1575 15 view .LVU1010 + 2959 009c 0220 movs r0, #2 + 2960 009e F9E7 b .L210 + 2961 .LVL170: + 2962 .L218: +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2963 .loc 1 1559 21 view .LVU1011 + 2964 00a0 0020 movs r0, #0 + 2965 00a2 F7E7 b .L210 + 2966 .LVL171: + 2967 .L214: +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2968 .loc 1 1565 3 view .LVU1012 + 2969 00a4 0220 movs r0, #2 +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2970 .loc 1 1632 1 view .LVU1013 + 2971 00a6 7047 bx lr + 2972 .L221: + 2973 .align 2 + 2974 .L220: + 2975 00a8 00000000 .word SPI_TxISR_16BIT + 2976 00ac 00000000 .word SPI_TxISR_8BIT + 2977 .cfi_endproc + 2978 .LFE137: + 2980 .section .text.HAL_SPI_TransmitReceive_IT,"ax",%progbits + 2981 .align 1 + 2982 .global HAL_SPI_TransmitReceive_IT + 2983 .syntax unified + 2984 .thumb + 2985 .thumb_func + 2987 HAL_SPI_TransmitReceive_IT: + 2988 .LVL172: + 2989 .LFB139: +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; + 2990 .loc 1 1750 1 is_stmt 1 view -0 + 2991 .cfi_startproc + 2992 @ args = 0, pretend = 0, frame = 0 + 2993 @ frame_needed = 0, uses_anonymous_args = 0 + 2994 @ link register save eliminated. +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; + 2995 .loc 1 1750 1 is_stmt 0 view .LVU1015 + 2996 0000 8446 mov ip, r0 +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; + 2997 .loc 1 1751 3 is_stmt 1 view .LVU1016 +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 2998 .loc 1 1752 3 view .LVU1017 +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 2999 .loc 1 1753 3 view .LVU1018 + 3000 .LVL173: +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3001 .loc 1 1756 3 view .LVU1019 +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3002 .loc 1 1759 3 view .LVU1020 +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3003 .loc 1 1759 3 view .LVU1021 + ARM GAS /tmp/ccywxtmH.s page 146 + + + 3004 0002 90F85C00 ldrb r0, [r0, #92] @ zero_extendqisi2 + 3005 .LVL174: +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3006 .loc 1 1759 3 is_stmt 0 view .LVU1022 + 3007 0006 0128 cmp r0, #1 + 3008 0008 79D0 beq .L232 +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; + 3009 .loc 1 1750 1 discriminator 2 view .LVU1023 + 3010 000a 10B4 push {r4} + 3011 .cfi_def_cfa_offset 4 + 3012 .cfi_offset 4, -4 +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3013 .loc 1 1759 3 is_stmt 1 discriminator 2 view .LVU1024 + 3014 000c 0120 movs r0, #1 + 3015 000e 8CF85C00 strb r0, [ip, #92] +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3016 .loc 1 1759 3 discriminator 2 view .LVU1025 +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 3017 .loc 1 1762 3 discriminator 2 view .LVU1026 +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 3018 .loc 1 1762 23 is_stmt 0 discriminator 2 view .LVU1027 + 3019 0012 9CF85D00 ldrb r0, [ip, #93] @ zero_extendqisi2 + 3020 0016 C0B2 uxtb r0, r0 + 3021 .LVL175: +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3022 .loc 1 1763 3 is_stmt 1 discriminator 2 view .LVU1028 +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3023 .loc 1 1763 23 is_stmt 0 discriminator 2 view .LVU1029 + 3024 0018 DCF80440 ldr r4, [ip, #4] + 3025 .LVL176: +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 3026 .loc 1 1765 3 is_stmt 1 discriminator 2 view .LVU1030 +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 3027 .loc 1 1765 6 is_stmt 0 discriminator 2 view .LVU1031 + 3028 001c 0128 cmp r0, #1 + 3029 001e 08D0 beq .L224 +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 3030 .loc 1 1765 7 discriminator 1 view .LVU1032 + 3031 0020 B4F5827F cmp r4, #260 + 3032 0024 58D1 bne .L233 +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3033 .loc 1 1766 54 view .LVU1033 + 3034 0026 DCF80840 ldr r4, [ip, #8] + 3035 .LVL177: +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3036 .loc 1 1766 40 view .LVU1034 + 3037 002a 002C cmp r4, #0 + 3038 002c 5BD1 bne .L234 +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3039 .loc 1 1766 90 discriminator 1 view .LVU1035 + 3040 002e 0428 cmp r0, #4 + 3041 0030 5BD1 bne .L235 + 3042 .L224: +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3043 .loc 1 1772 3 is_stmt 1 view .LVU1036 +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3044 .loc 1 1772 6 is_stmt 0 view .LVU1037 + ARM GAS /tmp/ccywxtmH.s page 147 + + + 3045 0032 0029 cmp r1, #0 + 3046 0034 5BD0 beq .L236 +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3047 .loc 1 1772 25 discriminator 1 view .LVU1038 + 3048 0036 002A cmp r2, #0 + 3049 0038 5BD0 beq .L237 +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3050 .loc 1 1772 46 discriminator 2 view .LVU1039 + 3051 003a 002B cmp r3, #0 + 3052 003c 5BD0 beq .L238 +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3053 .loc 1 1779 3 is_stmt 1 view .LVU1040 +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3054 .loc 1 1779 11 is_stmt 0 view .LVU1041 + 3055 003e 9CF85D00 ldrb r0, [ip, #93] @ zero_extendqisi2 + 3056 .LVL178: +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3057 .loc 1 1779 11 view .LVU1042 + 3058 0042 C0B2 uxtb r0, r0 +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3059 .loc 1 1779 6 view .LVU1043 + 3060 0044 0428 cmp r0, #4 + 3061 0046 02D0 beq .L226 +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3062 .loc 1 1781 5 is_stmt 1 view .LVU1044 +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3063 .loc 1 1781 17 is_stmt 0 view .LVU1045 + 3064 0048 0520 movs r0, #5 + 3065 004a 8CF85D00 strb r0, [ip, #93] + 3066 .L226: +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 3067 .loc 1 1785 3 is_stmt 1 view .LVU1046 +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 3068 .loc 1 1785 21 is_stmt 0 view .LVU1047 + 3069 004e 0020 movs r0, #0 + 3070 0050 CCF86000 str r0, [ip, #96] +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 3071 .loc 1 1786 3 is_stmt 1 view .LVU1048 +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 3072 .loc 1 1786 21 is_stmt 0 view .LVU1049 + 3073 0054 CCF83810 str r1, [ip, #56] +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 3074 .loc 1 1787 3 is_stmt 1 view .LVU1050 +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 3075 .loc 1 1787 21 is_stmt 0 view .LVU1051 + 3076 0058 ACF83C30 strh r3, [ip, #60] @ movhi +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + 3077 .loc 1 1788 3 is_stmt 1 view .LVU1052 +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + 3078 .loc 1 1788 21 is_stmt 0 view .LVU1053 + 3079 005c ACF83E30 strh r3, [ip, #62] @ movhi +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 3080 .loc 1 1789 3 is_stmt 1 view .LVU1054 +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 3081 .loc 1 1789 21 is_stmt 0 view .LVU1055 + 3082 0060 CCF84020 str r2, [ip, #64] +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + ARM GAS /tmp/ccywxtmH.s page 148 + + + 3083 .loc 1 1790 3 is_stmt 1 view .LVU1056 +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 3084 .loc 1 1790 21 is_stmt 0 view .LVU1057 + 3085 0064 ACF84430 strh r3, [ip, #68] @ movhi +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3086 .loc 1 1791 3 is_stmt 1 view .LVU1058 +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3087 .loc 1 1791 21 is_stmt 0 view .LVU1059 + 3088 0068 ACF84630 strh r3, [ip, #70] @ movhi +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3089 .loc 1 1794 3 is_stmt 1 view .LVU1060 +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3090 .loc 1 1794 17 is_stmt 0 view .LVU1061 + 3091 006c DCF80C20 ldr r2, [ip, #12] + 3092 .LVL179: +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3093 .loc 1 1794 6 view .LVU1062 + 3094 0070 B2F5E06F cmp r2, #1792 + 3095 0074 22D9 bls .L227 +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_16BIT; + 3096 .loc 1 1796 5 is_stmt 1 view .LVU1063 +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_16BIT; + 3097 .loc 1 1796 21 is_stmt 0 view .LVU1064 + 3098 0076 2349 ldr r1, .L244 + 3099 .LVL180: +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_16BIT; + 3100 .loc 1 1796 21 view .LVU1065 + 3101 0078 CCF84C10 str r1, [ip, #76] +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3102 .loc 1 1797 5 is_stmt 1 view .LVU1066 +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3103 .loc 1 1797 21 is_stmt 0 view .LVU1067 + 3104 007c 2249 ldr r1, .L244+4 + 3105 007e CCF85010 str r1, [ip, #80] + 3106 .L228: +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3107 .loc 1 1823 3 is_stmt 1 view .LVU1068 +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3108 .loc 1 1823 6 is_stmt 0 view .LVU1069 + 3109 0082 B2F5E06F cmp r2, #1792 + 3110 0086 01D8 bhi .L229 +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3111 .loc 1 1823 49 discriminator 1 view .LVU1070 + 3112 0088 012B cmp r3, #1 + 3113 008a 1ED9 bls .L230 + 3114 .L229: +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3115 .loc 1 1826 5 is_stmt 1 view .LVU1071 + 3116 008c DCF80020 ldr r2, [ip] + 3117 0090 5368 ldr r3, [r2, #4] + 3118 .LVL181: +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3119 .loc 1 1826 5 is_stmt 0 view .LVU1072 + 3120 0092 23F48053 bic r3, r3, #4096 + 3121 0096 5360 str r3, [r2, #4] + 3122 .LVL182: + 3123 .L231: + ARM GAS /tmp/ccywxtmH.s page 149 + + +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3124 .loc 1 1835 3 is_stmt 1 view .LVU1073 + 3125 0098 DCF80020 ldr r2, [ip] + 3126 009c 5368 ldr r3, [r2, #4] + 3127 009e 43F0E003 orr r3, r3, #224 + 3128 00a2 5360 str r3, [r2, #4] +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3129 .loc 1 1838 3 view .LVU1074 +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3130 .loc 1 1838 12 is_stmt 0 view .LVU1075 + 3131 00a4 DCF80030 ldr r3, [ip] +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3132 .loc 1 1838 22 view .LVU1076 + 3133 00a8 1A68 ldr r2, [r3] +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3134 .loc 1 1838 6 view .LVU1077 + 3135 00aa 12F0400F tst r2, #64 + 3136 00ae 24D1 bne .L239 +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3137 .loc 1 1841 5 is_stmt 1 view .LVU1078 + 3138 00b0 1A68 ldr r2, [r3] + 3139 00b2 42F04002 orr r2, r2, #64 + 3140 00b6 1A60 str r2, [r3] +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3141 .loc 1 1753 24 is_stmt 0 view .LVU1079 + 3142 00b8 0020 movs r0, #0 + 3143 00ba 0EE0 b .L225 + 3144 .LVL183: + 3145 .L227: +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_8BIT; + 3146 .loc 1 1801 5 is_stmt 1 view .LVU1080 +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_8BIT; + 3147 .loc 1 1801 21 is_stmt 0 view .LVU1081 + 3148 00bc 1349 ldr r1, .L244+8 + 3149 .LVL184: +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_8BIT; + 3150 .loc 1 1801 21 view .LVU1082 + 3151 00be CCF84C10 str r1, [ip, #76] +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3152 .loc 1 1802 5 is_stmt 1 view .LVU1083 +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3153 .loc 1 1802 21 is_stmt 0 view .LVU1084 + 3154 00c2 1349 ldr r1, .L244+12 + 3155 00c4 CCF85010 str r1, [ip, #80] + 3156 00c8 DBE7 b .L228 + 3157 .L230: +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3158 .loc 1 1831 5 is_stmt 1 view .LVU1085 + 3159 00ca DCF80020 ldr r2, [ip] + 3160 00ce 5368 ldr r3, [r2, #4] + 3161 .LVL185: +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3162 .loc 1 1831 5 is_stmt 0 view .LVU1086 + 3163 00d0 43F48053 orr r3, r3, #4096 + 3164 00d4 5360 str r3, [r2, #4] + 3165 .LVL186: +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 150 + + + 3166 .loc 1 1831 5 view .LVU1087 + 3167 00d6 DFE7 b .L231 + 3168 .LVL187: + 3169 .L233: +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3170 .loc 1 1768 15 view .LVU1088 + 3171 00d8 0220 movs r0, #2 + 3172 .LVL188: + 3173 .L225: +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3174 .loc 1 1846 3 is_stmt 1 view .LVU1089 +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3175 .loc 1 1846 3 view .LVU1090 + 3176 00da 0023 movs r3, #0 + 3177 00dc 8CF85C30 strb r3, [ip, #92] +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3178 .loc 1 1846 3 view .LVU1091 +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3179 .loc 1 1847 3 view .LVU1092 +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3180 .loc 1 1848 1 is_stmt 0 view .LVU1093 + 3181 00e0 5DF8044B ldr r4, [sp], #4 + 3182 .cfi_remember_state + 3183 .cfi_restore 4 + 3184 .cfi_def_cfa_offset 0 + 3185 00e4 7047 bx lr + 3186 .LVL189: + 3187 .L234: + 3188 .cfi_restore_state +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3189 .loc 1 1768 15 view .LVU1094 + 3190 00e6 0220 movs r0, #2 + 3191 .LVL190: +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3192 .loc 1 1768 15 view .LVU1095 + 3193 00e8 F7E7 b .L225 + 3194 .LVL191: + 3195 .L235: +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3196 .loc 1 1768 15 view .LVU1096 + 3197 00ea 0220 movs r0, #2 + 3198 .LVL192: +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3199 .loc 1 1768 15 view .LVU1097 + 3200 00ec F5E7 b .L225 + 3201 .LVL193: + 3202 .L236: +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3203 .loc 1 1774 15 view .LVU1098 + 3204 00ee 0120 movs r0, #1 + 3205 .LVL194: +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3206 .loc 1 1774 15 view .LVU1099 + 3207 00f0 F3E7 b .L225 + 3208 .LVL195: + 3209 .L237: +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + ARM GAS /tmp/ccywxtmH.s page 151 + + + 3210 .loc 1 1774 15 view .LVU1100 + 3211 00f2 0120 movs r0, #1 + 3212 .LVL196: +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3213 .loc 1 1774 15 view .LVU1101 + 3214 00f4 F1E7 b .L225 + 3215 .LVL197: + 3216 .L238: +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3217 .loc 1 1774 15 view .LVU1102 + 3218 00f6 0120 movs r0, #1 + 3219 .LVL198: +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3220 .loc 1 1774 15 view .LVU1103 + 3221 00f8 EFE7 b .L225 + 3222 .LVL199: + 3223 .L239: +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3224 .loc 1 1753 24 view .LVU1104 + 3225 00fa 0020 movs r0, #0 + 3226 00fc EDE7 b .L225 + 3227 .LVL200: + 3228 .L232: + 3229 .cfi_def_cfa_offset 0 + 3230 .cfi_restore 4 +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3231 .loc 1 1759 3 view .LVU1105 + 3232 00fe 0220 movs r0, #2 +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3233 .loc 1 1848 1 view .LVU1106 + 3234 0100 7047 bx lr + 3235 .L245: + 3236 0102 00BF .align 2 + 3237 .L244: + 3238 0104 00000000 .word SPI_2linesRxISR_16BIT + 3239 0108 00000000 .word SPI_2linesTxISR_16BIT + 3240 010c 00000000 .word SPI_2linesRxISR_8BIT + 3241 0110 00000000 .word SPI_2linesTxISR_8BIT + 3242 .cfi_endproc + 3243 .LFE139: + 3245 .section .text.HAL_SPI_Receive_IT,"ax",%progbits + 3246 .align 1 + 3247 .global HAL_SPI_Receive_IT + 3248 .syntax unified + 3249 .thumb + 3250 .thumb_func + 3252 HAL_SPI_Receive_IT: + 3253 .LVL201: + 3254 .LFB138: +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 3255 .loc 1 1643 1 is_stmt 1 view -0 + 3256 .cfi_startproc + 3257 @ args = 0, pretend = 0, frame = 0 + 3258 @ frame_needed = 0, uses_anonymous_args = 0 +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 3259 .loc 1 1643 1 is_stmt 0 view .LVU1108 + 3260 0000 08B5 push {r3, lr} + ARM GAS /tmp/ccywxtmH.s page 152 + + + 3261 .cfi_def_cfa_offset 8 + 3262 .cfi_offset 3, -8 + 3263 .cfi_offset 14, -4 + 3264 0002 8446 mov ip, r0 +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3265 .loc 1 1644 3 is_stmt 1 view .LVU1109 + 3266 .LVL202: +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3267 .loc 1 1646 3 view .LVU1110 +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3268 .loc 1 1646 18 is_stmt 0 view .LVU1111 + 3269 0004 8368 ldr r3, [r0, #8] +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3270 .loc 1 1646 6 view .LVU1112 + 3271 0006 1BB9 cbnz r3, .L247 +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3272 .loc 1 1646 68 discriminator 1 view .LVU1113 + 3273 0008 4368 ldr r3, [r0, #4] +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3274 .loc 1 1646 54 discriminator 1 view .LVU1114 + 3275 000a B3F5827F cmp r3, #260 + 3276 000e 48D0 beq .L257 + 3277 .L247: +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3278 .loc 1 1654 3 is_stmt 1 view .LVU1115 +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3279 .loc 1 1654 3 view .LVU1116 + 3280 0010 9CF85C30 ldrb r3, [ip, #92] @ zero_extendqisi2 + 3281 0014 012B cmp r3, #1 + 3282 0016 6AD0 beq .L253 +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3283 .loc 1 1654 3 discriminator 2 view .LVU1117 + 3284 0018 0123 movs r3, #1 + 3285 001a 8CF85C30 strb r3, [ip, #92] +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3286 .loc 1 1654 3 discriminator 2 view .LVU1118 +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3287 .loc 1 1656 3 discriminator 2 view .LVU1119 +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3288 .loc 1 1656 11 is_stmt 0 discriminator 2 view .LVU1120 + 3289 001e 9CF85D00 ldrb r0, [ip, #93] @ zero_extendqisi2 + 3290 .LVL203: +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3291 .loc 1 1656 11 discriminator 2 view .LVU1121 + 3292 0022 C0B2 uxtb r0, r0 +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3293 .loc 1 1656 6 discriminator 2 view .LVU1122 + 3294 0024 9842 cmp r0, r3 + 3295 0026 5BD1 bne .L254 +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3296 .loc 1 1662 3 is_stmt 1 view .LVU1123 +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3297 .loc 1 1662 6 is_stmt 0 view .LVU1124 + 3298 0028 0029 cmp r1, #0 + 3299 002a 5AD0 beq .L249 +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3300 .loc 1 1662 23 discriminator 1 view .LVU1125 + ARM GAS /tmp/ccywxtmH.s page 153 + + + 3301 002c 002A cmp r2, #0 + 3302 002e 58D0 beq .L249 +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 3303 .loc 1 1669 3 is_stmt 1 view .LVU1126 +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 3304 .loc 1 1669 21 is_stmt 0 view .LVU1127 + 3305 0030 0423 movs r3, #4 + 3306 0032 8CF85D30 strb r3, [ip, #93] +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 3307 .loc 1 1670 3 is_stmt 1 view .LVU1128 +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 3308 .loc 1 1670 21 is_stmt 0 view .LVU1129 + 3309 0036 0023 movs r3, #0 + 3310 0038 CCF86030 str r3, [ip, #96] +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 3311 .loc 1 1671 3 is_stmt 1 view .LVU1130 +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 3312 .loc 1 1671 21 is_stmt 0 view .LVU1131 + 3313 003c CCF84010 str r1, [ip, #64] +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 3314 .loc 1 1672 3 is_stmt 1 view .LVU1132 +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 3315 .loc 1 1672 21 is_stmt 0 view .LVU1133 + 3316 0040 ACF84420 strh r2, [ip, #68] @ movhi +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3317 .loc 1 1673 3 is_stmt 1 view .LVU1134 +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3318 .loc 1 1673 21 is_stmt 0 view .LVU1135 + 3319 0044 ACF84620 strh r2, [ip, #70] @ movhi +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 3320 .loc 1 1676 3 is_stmt 1 view .LVU1136 +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 3321 .loc 1 1676 21 is_stmt 0 view .LVU1137 + 3322 0048 CCF83830 str r3, [ip, #56] +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 3323 .loc 1 1677 3 is_stmt 1 view .LVU1138 +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 3324 .loc 1 1677 21 is_stmt 0 view .LVU1139 + 3325 004c ACF83C30 strh r3, [ip, #60] @ movhi +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 3326 .loc 1 1678 3 is_stmt 1 view .LVU1140 +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 3327 .loc 1 1678 21 is_stmt 0 view .LVU1141 + 3328 0050 ACF83E30 strh r3, [ip, #62] @ movhi +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3329 .loc 1 1679 3 is_stmt 1 view .LVU1142 +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3330 .loc 1 1679 21 is_stmt 0 view .LVU1143 + 3331 0054 CCF85030 str r3, [ip, #80] +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3332 .loc 1 1682 3 is_stmt 1 view .LVU1144 +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3333 .loc 1 1682 17 is_stmt 0 view .LVU1145 + 3334 0058 DCF80C30 ldr r3, [ip, #12] +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3335 .loc 1 1682 6 view .LVU1146 + 3336 005c B3F5E06F cmp r3, #1792 + ARM GAS /tmp/ccywxtmH.s page 154 + + + 3337 0060 27D9 bls .L250 +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_16BIT; + 3338 .loc 1 1685 5 is_stmt 1 view .LVU1147 + 3339 0062 DCF80020 ldr r2, [ip] + 3340 .LVL204: +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_16BIT; + 3341 .loc 1 1685 5 is_stmt 0 view .LVU1148 + 3342 0066 5368 ldr r3, [r2, #4] + 3343 0068 23F48053 bic r3, r3, #4096 + 3344 006c 5360 str r3, [r2, #4] + 3345 .LVL205: +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3346 .loc 1 1686 5 is_stmt 1 view .LVU1149 +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3347 .loc 1 1686 17 is_stmt 0 view .LVU1150 + 3348 006e 214B ldr r3, .L259 + 3349 0070 CCF84C30 str r3, [ip, #76] + 3350 .L251: +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3351 .loc 1 1696 3 is_stmt 1 view .LVU1151 +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3352 .loc 1 1696 17 is_stmt 0 view .LVU1152 + 3353 0074 DCF80830 ldr r3, [ip, #8] +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3354 .loc 1 1696 6 view .LVU1153 + 3355 0078 B3F5004F cmp r3, #32768 + 3356 007c 23D0 beq .L258 + 3357 .L252: +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3358 .loc 1 1721 3 is_stmt 1 view .LVU1154 + 3359 007e DCF80020 ldr r2, [ip] + 3360 0082 5368 ldr r3, [r2, #4] + 3361 0084 43F06003 orr r3, r3, #96 + 3362 0088 5360 str r3, [r2, #4] +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3363 .loc 1 1728 3 view .LVU1155 +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3364 .loc 1 1728 12 is_stmt 0 view .LVU1156 + 3365 008a DCF80030 ldr r3, [ip] +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3366 .loc 1 1728 22 view .LVU1157 + 3367 008e 1A68 ldr r2, [r3] +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3368 .loc 1 1728 6 view .LVU1158 + 3369 0090 12F0400F tst r2, #64 + 3370 0094 29D1 bne .L255 +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3371 .loc 1 1731 5 is_stmt 1 view .LVU1159 + 3372 0096 1A68 ldr r2, [r3] + 3373 0098 42F04002 orr r2, r2, #64 + 3374 009c 1A60 str r2, [r3] +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3375 .loc 1 1644 21 is_stmt 0 view .LVU1160 + 3376 009e 0020 movs r0, #0 + 3377 00a0 1FE0 b .L249 + 3378 .LVL206: + 3379 .L257: + ARM GAS /tmp/ccywxtmH.s page 155 + + +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line + 3380 .loc 1 1648 5 is_stmt 1 view .LVU1161 +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line + 3381 .loc 1 1648 17 is_stmt 0 view .LVU1162 + 3382 00a2 0423 movs r3, #4 + 3383 00a4 80F85D30 strb r3, [r0, #93] +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3384 .loc 1 1650 5 is_stmt 1 view .LVU1163 +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3385 .loc 1 1650 12 is_stmt 0 view .LVU1164 + 3386 00a8 1346 mov r3, r2 + 3387 00aa 0A46 mov r2, r1 + 3388 .LVL207: +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3389 .loc 1 1650 12 view .LVU1165 + 3390 00ac FFF7FEFF bl HAL_SPI_TransmitReceive_IT + 3391 .LVL208: +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3392 .loc 1 1650 12 view .LVU1166 + 3393 00b0 1AE0 b .L248 + 3394 .LVL209: + 3395 .L250: +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_8BIT; + 3396 .loc 1 1691 5 is_stmt 1 view .LVU1167 + 3397 00b2 DCF80020 ldr r2, [ip] + 3398 .LVL210: +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_8BIT; + 3399 .loc 1 1691 5 is_stmt 0 view .LVU1168 + 3400 00b6 5368 ldr r3, [r2, #4] + 3401 00b8 43F48053 orr r3, r3, #4096 + 3402 00bc 5360 str r3, [r2, #4] + 3403 .LVL211: +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3404 .loc 1 1692 5 is_stmt 1 view .LVU1169 +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3405 .loc 1 1692 17 is_stmt 0 view .LVU1170 + 3406 00be 0E4B ldr r3, .L259+4 + 3407 00c0 CCF84C30 str r3, [ip, #76] + 3408 00c4 D6E7 b .L251 + 3409 .L258: +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); + 3410 .loc 1 1699 5 is_stmt 1 view .LVU1171 + 3411 00c6 DCF80020 ldr r2, [ip] + 3412 00ca 1368 ldr r3, [r2] + 3413 00cc 23F04003 bic r3, r3, #64 + 3414 00d0 1360 str r3, [r2] +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3415 .loc 1 1700 5 view .LVU1172 + 3416 00d2 DCF80020 ldr r2, [ip] + 3417 00d6 1368 ldr r3, [r2] + 3418 00d8 23F48043 bic r3, r3, #16384 + 3419 00dc 1360 str r3, [r2] + 3420 00de CEE7 b .L252 + 3421 .LVL212: + 3422 .L254: +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3423 .loc 1 1658 15 is_stmt 0 view .LVU1173 + ARM GAS /tmp/ccywxtmH.s page 156 + + + 3424 00e0 0220 movs r0, #2 + 3425 .LVL213: + 3426 .L249: +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3427 .loc 1 1736 3 is_stmt 1 view .LVU1174 +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3428 .loc 1 1736 3 view .LVU1175 + 3429 00e2 0023 movs r3, #0 + 3430 00e4 8CF85C30 strb r3, [ip, #92] +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3431 .loc 1 1736 3 view .LVU1176 +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3432 .loc 1 1737 3 view .LVU1177 + 3433 .LVL214: + 3434 .L248: +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3435 .loc 1 1738 1 is_stmt 0 view .LVU1178 + 3436 00e8 08BD pop {r3, pc} + 3437 .LVL215: + 3438 .L255: +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3439 .loc 1 1644 21 view .LVU1179 + 3440 00ea 0020 movs r0, #0 + 3441 00ec F9E7 b .L249 + 3442 .LVL216: + 3443 .L253: +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3444 .loc 1 1654 3 view .LVU1180 + 3445 00ee 0220 movs r0, #2 + 3446 .LVL217: +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3447 .loc 1 1654 3 view .LVU1181 + 3448 00f0 FAE7 b .L248 + 3449 .L260: + 3450 00f2 00BF .align 2 + 3451 .L259: + 3452 00f4 00000000 .word SPI_RxISR_16BIT + 3453 00f8 00000000 .word SPI_RxISR_8BIT + 3454 .cfi_endproc + 3455 .LFE138: + 3457 .section .text.HAL_SPI_Transmit_DMA,"ax",%progbits + 3458 .align 1 + 3459 .global HAL_SPI_Transmit_DMA + 3460 .syntax unified + 3461 .thumb + 3462 .thumb_func + 3464 HAL_SPI_Transmit_DMA: + 3465 .LVL218: + 3466 .LFB140: +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 3467 .loc 1 1859 1 is_stmt 1 view -0 + 3468 .cfi_startproc + 3469 @ args = 0, pretend = 0, frame = 0 + 3470 @ frame_needed = 0, uses_anonymous_args = 0 +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 3471 .loc 1 1859 1 is_stmt 0 view .LVU1183 + 3472 0000 38B5 push {r3, r4, r5, lr} + ARM GAS /tmp/ccywxtmH.s page 157 + + + 3473 .cfi_def_cfa_offset 16 + 3474 .cfi_offset 3, -16 + 3475 .cfi_offset 4, -12 + 3476 .cfi_offset 5, -8 + 3477 .cfi_offset 14, -4 +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3478 .loc 1 1860 3 is_stmt 1 view .LVU1184 + 3479 .LVL219: +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3480 .loc 1 1863 3 view .LVU1185 +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3481 .loc 1 1866 3 view .LVU1186 +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3482 .loc 1 1869 3 view .LVU1187 +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3483 .loc 1 1869 3 view .LVU1188 + 3484 0002 90F85C30 ldrb r3, [r0, #92] @ zero_extendqisi2 + 3485 0006 012B cmp r3, #1 + 3486 0008 00F08C80 beq .L269 + 3487 000c 0446 mov r4, r0 +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3488 .loc 1 1869 3 discriminator 2 view .LVU1189 + 3489 000e 0123 movs r3, #1 + 3490 0010 80F85C30 strb r3, [r0, #92] +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3491 .loc 1 1869 3 discriminator 2 view .LVU1190 +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3492 .loc 1 1871 3 discriminator 2 view .LVU1191 +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3493 .loc 1 1871 11 is_stmt 0 discriminator 2 view .LVU1192 + 3494 0014 90F85D50 ldrb r5, [r0, #93] @ zero_extendqisi2 + 3495 0018 EDB2 uxtb r5, r5 +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3496 .loc 1 1871 6 discriminator 2 view .LVU1193 + 3497 001a 9D42 cmp r5, r3 + 3498 001c 7CD1 bne .L270 +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3499 .loc 1 1877 3 is_stmt 1 view .LVU1194 +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3500 .loc 1 1877 6 is_stmt 0 view .LVU1195 + 3501 001e 0029 cmp r1, #0 + 3502 0020 7BD0 beq .L263 +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3503 .loc 1 1877 23 discriminator 1 view .LVU1196 + 3504 0022 002A cmp r2, #0 + 3505 0024 79D0 beq .L263 +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 3506 .loc 1 1884 3 is_stmt 1 view .LVU1197 +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 3507 .loc 1 1884 21 is_stmt 0 view .LVU1198 + 3508 0026 0323 movs r3, #3 + 3509 0028 80F85D30 strb r3, [r0, #93] +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 3510 .loc 1 1885 3 is_stmt 1 view .LVU1199 +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 3511 .loc 1 1885 21 is_stmt 0 view .LVU1200 + 3512 002c 0023 movs r3, #0 + ARM GAS /tmp/ccywxtmH.s page 158 + + + 3513 002e 0366 str r3, [r0, #96] +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 3514 .loc 1 1886 3 is_stmt 1 view .LVU1201 +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 3515 .loc 1 1886 21 is_stmt 0 view .LVU1202 + 3516 0030 8163 str r1, [r0, #56] +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 3517 .loc 1 1887 3 is_stmt 1 view .LVU1203 +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 3518 .loc 1 1887 21 is_stmt 0 view .LVU1204 + 3519 0032 8287 strh r2, [r0, #60] @ movhi +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3520 .loc 1 1888 3 is_stmt 1 view .LVU1205 +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3521 .loc 1 1888 21 is_stmt 0 view .LVU1206 + 3522 0034 C287 strh r2, [r0, #62] @ movhi +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 3523 .loc 1 1891 3 is_stmt 1 view .LVU1207 +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 3524 .loc 1 1891 21 is_stmt 0 view .LVU1208 + 3525 0036 0364 str r3, [r0, #64] +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 3526 .loc 1 1892 3 is_stmt 1 view .LVU1209 +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 3527 .loc 1 1892 21 is_stmt 0 view .LVU1210 + 3528 0038 0365 str r3, [r0, #80] +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 3529 .loc 1 1893 3 is_stmt 1 view .LVU1211 +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 3530 .loc 1 1893 21 is_stmt 0 view .LVU1212 + 3531 003a C364 str r3, [r0, #76] +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 3532 .loc 1 1894 3 is_stmt 1 view .LVU1213 +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 3533 .loc 1 1894 21 is_stmt 0 view .LVU1214 + 3534 003c A0F84430 strh r3, [r0, #68] @ movhi +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3535 .loc 1 1895 3 is_stmt 1 view .LVU1215 +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3536 .loc 1 1895 21 is_stmt 0 view .LVU1216 + 3537 0040 A0F84630 strh r3, [r0, #70] @ movhi +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3538 .loc 1 1898 3 is_stmt 1 view .LVU1217 +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3539 .loc 1 1898 17 is_stmt 0 view .LVU1218 + 3540 0044 8368 ldr r3, [r0, #8] +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3541 .loc 1 1898 6 view .LVU1219 + 3542 0046 B3F5004F cmp r3, #32768 + 3543 004a 39D0 beq .L272 + 3544 .LVL220: + 3545 .L264: +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3546 .loc 1 1914 3 is_stmt 1 view .LVU1220 +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3547 .loc 1 1914 7 is_stmt 0 view .LVU1221 + 3548 004c 636D ldr r3, [r4, #84] + ARM GAS /tmp/ccywxtmH.s page 159 + + +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3549 .loc 1 1914 38 view .LVU1222 + 3550 004e 364A ldr r2, .L275 + 3551 0050 DA62 str r2, [r3, #44] +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3552 .loc 1 1917 3 is_stmt 1 view .LVU1223 +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3553 .loc 1 1917 7 is_stmt 0 view .LVU1224 + 3554 0052 636D ldr r3, [r4, #84] +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3555 .loc 1 1917 34 view .LVU1225 + 3556 0054 354A ldr r2, .L275+4 + 3557 0056 9A62 str r2, [r3, #40] +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3558 .loc 1 1920 3 is_stmt 1 view .LVU1226 +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3559 .loc 1 1920 7 is_stmt 0 view .LVU1227 + 3560 0058 636D ldr r3, [r4, #84] +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3561 .loc 1 1920 35 view .LVU1228 + 3562 005a 354A ldr r2, .L275+8 + 3563 005c 1A63 str r2, [r3, #48] +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3564 .loc 1 1923 3 is_stmt 1 view .LVU1229 +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3565 .loc 1 1923 7 is_stmt 0 view .LVU1230 + 3566 005e 636D ldr r3, [r4, #84] +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3567 .loc 1 1923 35 view .LVU1231 + 3568 0060 0022 movs r2, #0 + 3569 0062 5A63 str r2, [r3, #52] +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Packing mode is enabled only if the DMA setting is HALWORD */ + 3570 .loc 1 1925 3 is_stmt 1 view .LVU1232 + 3571 0064 2268 ldr r2, [r4] + 3572 0066 5368 ldr r3, [r2, #4] + 3573 0068 23F48043 bic r3, r3, #16384 + 3574 006c 5360 str r3, [r2, #4] +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3575 .loc 1 1927 3 view .LVU1233 +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3576 .loc 1 1927 18 is_stmt 0 view .LVU1234 + 3577 006e E368 ldr r3, [r4, #12] +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3578 .loc 1 1927 6 view .LVU1235 + 3579 0070 B3F5E06F cmp r3, #1792 + 3580 0074 04D8 bhi .L265 +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3581 .loc 1 1927 58 discriminator 1 view .LVU1236 + 3582 0076 636D ldr r3, [r4, #84] +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3583 .loc 1 1927 72 discriminator 1 view .LVU1237 + 3584 0078 5B69 ldr r3, [r3, #20] +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3585 .loc 1 1927 50 discriminator 1 view .LVU1238 + 3586 007a B3F5806F cmp r3, #1024 + 3587 007e 2AD0 beq .L273 + 3588 .L265: + ARM GAS /tmp/ccywxtmH.s page 160 + + +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3589 .loc 1 1943 3 is_stmt 1 view .LVU1239 +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3590 .loc 1 1943 91 is_stmt 0 view .LVU1240 + 3591 0080 2268 ldr r2, [r4] +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3592 .loc 1 1944 38 view .LVU1241 + 3593 0082 E38F ldrh r3, [r4, #62] +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3594 .loc 1 1943 17 view .LVU1242 + 3595 0084 9BB2 uxth r3, r3 + 3596 0086 0C32 adds r2, r2, #12 + 3597 0088 A16B ldr r1, [r4, #56] + 3598 .LVL221: +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3599 .loc 1 1943 17 view .LVU1243 + 3600 008a 606D ldr r0, [r4, #84] + 3601 .LVL222: +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3602 .loc 1 1943 17 view .LVU1244 + 3603 008c FFF7FEFF bl HAL_DMA_Start_IT + 3604 .LVL223: +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3605 .loc 1 1943 6 view .LVU1245 + 3606 0090 0146 mov r1, r0 + 3607 0092 0028 cmp r0, #0 + 3608 0094 38D1 bne .L274 +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3609 .loc 1 1955 3 is_stmt 1 view .LVU1246 +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3610 .loc 1 1955 12 is_stmt 0 view .LVU1247 + 3611 0096 2368 ldr r3, [r4] +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3612 .loc 1 1955 22 view .LVU1248 + 3613 0098 1A68 ldr r2, [r3] +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3614 .loc 1 1955 6 view .LVU1249 + 3615 009a 12F0400F tst r2, #64 + 3616 009e 03D1 bne .L268 +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3617 .loc 1 1958 5 is_stmt 1 view .LVU1250 + 3618 00a0 1A68 ldr r2, [r3] + 3619 00a2 42F04002 orr r2, r2, #64 + 3620 00a6 1A60 str r2, [r3] + 3621 .L268: +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3622 .loc 1 1962 3 view .LVU1251 + 3623 00a8 2268 ldr r2, [r4] + 3624 00aa 5368 ldr r3, [r2, #4] + 3625 00ac 43F02003 orr r3, r3, #32 + 3626 00b0 5360 str r3, [r2, #4] +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3627 .loc 1 1965 3 view .LVU1252 + 3628 00b2 2268 ldr r2, [r4] + 3629 00b4 5368 ldr r3, [r2, #4] + 3630 00b6 43F00203 orr r3, r3, #2 + 3631 00ba 5360 str r3, [r2, #4] + ARM GAS /tmp/ccywxtmH.s page 161 + + +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3632 .loc 1 1860 21 is_stmt 0 view .LVU1253 + 3633 00bc 0D46 mov r5, r1 + 3634 00be 2CE0 b .L263 + 3635 .LVL224: + 3636 .L272: +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 3637 .loc 1 1901 5 is_stmt 1 view .LVU1254 + 3638 00c0 0268 ldr r2, [r0] + 3639 .LVL225: +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 3640 .loc 1 1901 5 is_stmt 0 view .LVU1255 + 3641 00c2 1368 ldr r3, [r2] + 3642 00c4 23F04003 bic r3, r3, #64 + 3643 00c8 1360 str r3, [r2] + 3644 .LVL226: +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3645 .loc 1 1902 5 is_stmt 1 view .LVU1256 + 3646 00ca 0268 ldr r2, [r0] + 3647 00cc 1368 ldr r3, [r2] + 3648 00ce 43F48043 orr r3, r3, #16384 + 3649 00d2 1360 str r3, [r2] + 3650 00d4 BAE7 b .L264 + 3651 .L273: +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3652 .loc 1 1930 5 view .LVU1257 +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3653 .loc 1 1930 14 is_stmt 0 view .LVU1258 + 3654 00d6 E38F ldrh r3, [r4, #62] +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3655 .loc 1 1930 8 view .LVU1259 + 3656 00d8 13F0010F tst r3, #1 + 3657 00dc 09D1 bne .L266 +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U); + 3658 .loc 1 1932 7 is_stmt 1 view .LVU1260 + 3659 00de 2268 ldr r2, [r4] + 3660 00e0 5368 ldr r3, [r2, #4] + 3661 00e2 23F48043 bic r3, r3, #16384 + 3662 00e6 5360 str r3, [r2, #4] +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3663 .loc 1 1933 7 view .LVU1261 +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3664 .loc 1 1933 32 is_stmt 0 view .LVU1262 + 3665 00e8 E38F ldrh r3, [r4, #62] +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3666 .loc 1 1933 25 view .LVU1263 + 3667 00ea C3F34E03 ubfx r3, r3, #1, #15 + 3668 00ee E387 strh r3, [r4, #62] @ movhi + 3669 00f0 C6E7 b .L265 + 3670 .L266: +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + 3671 .loc 1 1937 7 is_stmt 1 view .LVU1264 + 3672 00f2 2268 ldr r2, [r4] + 3673 00f4 5368 ldr r3, [r2, #4] + 3674 00f6 43F48043 orr r3, r3, #16384 + 3675 00fa 5360 str r3, [r2, #4] +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 162 + + + 3676 .loc 1 1938 7 view .LVU1265 +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3677 .loc 1 1938 32 is_stmt 0 view .LVU1266 + 3678 00fc E38F ldrh r3, [r4, #62] +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3679 .loc 1 1938 53 view .LVU1267 + 3680 00fe C3F34E03 ubfx r3, r3, #1, #15 + 3681 0102 0133 adds r3, r3, #1 +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3682 .loc 1 1938 25 view .LVU1268 + 3683 0104 E387 strh r3, [r4, #62] @ movhi + 3684 0106 BBE7 b .L265 + 3685 .LVL227: + 3686 .L274: +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3687 .loc 1 1947 5 is_stmt 1 view .LVU1269 + 3688 0108 236E ldr r3, [r4, #96] + 3689 010a 43F01003 orr r3, r3, #16 + 3690 010e 2366 str r3, [r4, #96] +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3691 .loc 1 1948 5 view .LVU1270 + 3692 .LVL228: +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3693 .loc 1 1950 5 view .LVU1271 +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3694 .loc 1 1950 17 is_stmt 0 view .LVU1272 + 3695 0110 0123 movs r3, #1 + 3696 0112 84F85D30 strb r3, [r4, #93] +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3697 .loc 1 1951 5 is_stmt 1 view .LVU1273 + 3698 0116 00E0 b .L263 + 3699 .LVL229: + 3700 .L270: +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3701 .loc 1 1873 15 is_stmt 0 view .LVU1274 + 3702 0118 0225 movs r5, #2 + 3703 .LVL230: + 3704 .L263: +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3705 .loc 1 1969 3 is_stmt 1 view .LVU1275 +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3706 .loc 1 1969 3 view .LVU1276 + 3707 011a 0023 movs r3, #0 + 3708 011c 84F85C30 strb r3, [r4, #92] +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3709 .loc 1 1969 3 view .LVU1277 +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3710 .loc 1 1970 3 view .LVU1278 + 3711 .LVL231: + 3712 .L262: +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3713 .loc 1 1971 1 is_stmt 0 view .LVU1279 + 3714 0120 2846 mov r0, r5 + 3715 0122 38BD pop {r3, r4, r5, pc} + 3716 .LVL232: + 3717 .L269: +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 163 + + + 3718 .loc 1 1869 3 view .LVU1280 + 3719 0124 0225 movs r5, #2 + 3720 0126 FBE7 b .L262 + 3721 .L276: + 3722 .align 2 + 3723 .L275: + 3724 0128 00000000 .word SPI_DMAHalfTransmitCplt + 3725 012c 00000000 .word SPI_DMATransmitCplt + 3726 0130 00000000 .word SPI_DMAError + 3727 .cfi_endproc + 3728 .LFE140: + 3730 .section .text.HAL_SPI_TransmitReceive_DMA,"ax",%progbits + 3731 .align 1 + 3732 .global HAL_SPI_TransmitReceive_DMA + 3733 .syntax unified + 3734 .thumb + 3735 .thumb_func + 3737 HAL_SPI_TransmitReceive_DMA: + 3738 .LVL233: + 3739 .LFB142: +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; + 3740 .loc 1 2139 1 is_stmt 1 view -0 + 3741 .cfi_startproc + 3742 @ args = 0, pretend = 0, frame = 0 + 3743 @ frame_needed = 0, uses_anonymous_args = 0 +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; + 3744 .loc 1 2139 1 is_stmt 0 view .LVU1282 + 3745 0000 38B5 push {r3, r4, r5, lr} + 3746 .cfi_def_cfa_offset 16 + 3747 .cfi_offset 3, -16 + 3748 .cfi_offset 4, -12 + 3749 .cfi_offset 5, -8 + 3750 .cfi_offset 14, -4 + 3751 0002 0446 mov r4, r0 +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; + 3752 .loc 1 2140 3 is_stmt 1 view .LVU1283 +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 3753 .loc 1 2141 3 view .LVU1284 +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3754 .loc 1 2142 3 view .LVU1285 + 3755 .LVL234: +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + 3756 .loc 1 2145 3 view .LVU1286 +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3757 .loc 1 2146 3 view .LVU1287 +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3758 .loc 1 2149 3 view .LVU1288 +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3759 .loc 1 2152 3 view .LVU1289 +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3760 .loc 1 2152 3 view .LVU1290 + 3761 0004 90F85C00 ldrb r0, [r0, #92] @ zero_extendqisi2 + 3762 .LVL235: +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3763 .loc 1 2152 3 is_stmt 0 view .LVU1291 + 3764 0008 0128 cmp r0, #1 + 3765 000a 00F00381 beq .L293 + ARM GAS /tmp/ccywxtmH.s page 164 + + +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3766 .loc 1 2152 3 is_stmt 1 discriminator 2 view .LVU1292 + 3767 000e 0120 movs r0, #1 + 3768 0010 84F85C00 strb r0, [r4, #92] +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3769 .loc 1 2152 3 discriminator 2 view .LVU1293 +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 3770 .loc 1 2155 3 discriminator 2 view .LVU1294 +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 3771 .loc 1 2155 23 is_stmt 0 discriminator 2 view .LVU1295 + 3772 0014 94F85D00 ldrb r0, [r4, #93] @ zero_extendqisi2 + 3773 0018 C0B2 uxtb r0, r0 + 3774 .LVL236: +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3775 .loc 1 2156 3 is_stmt 1 discriminator 2 view .LVU1296 +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3776 .loc 1 2156 23 is_stmt 0 discriminator 2 view .LVU1297 + 3777 001a 6568 ldr r5, [r4, #4] + 3778 .LVL237: +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 3779 .loc 1 2158 3 is_stmt 1 discriminator 2 view .LVU1298 +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 3780 .loc 1 2158 6 is_stmt 0 discriminator 2 view .LVU1299 + 3781 001c 0128 cmp r0, #1 + 3782 001e 0AD0 beq .L279 +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 3783 .loc 1 2158 7 discriminator 1 view .LVU1300 + 3784 0020 B5F5827F cmp r5, #260 + 3785 0024 40F0E580 bne .L294 +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3786 .loc 1 2159 54 view .LVU1301 + 3787 0028 A568 ldr r5, [r4, #8] + 3788 .LVL238: +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3789 .loc 1 2159 40 view .LVU1302 + 3790 002a 002D cmp r5, #0 + 3791 002c 40F0E680 bne .L295 +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3792 .loc 1 2159 90 discriminator 1 view .LVU1303 + 3793 0030 0428 cmp r0, #4 + 3794 0032 40F0E580 bne .L296 + 3795 .L279: +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3796 .loc 1 2165 3 is_stmt 1 view .LVU1304 +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3797 .loc 1 2165 6 is_stmt 0 view .LVU1305 + 3798 0036 0029 cmp r1, #0 + 3799 0038 00F0E480 beq .L297 +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3800 .loc 1 2165 25 discriminator 1 view .LVU1306 + 3801 003c 002A cmp r2, #0 + 3802 003e 00F0E380 beq .L298 +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3803 .loc 1 2165 46 discriminator 2 view .LVU1307 + 3804 0042 002B cmp r3, #0 + 3805 0044 00F0E280 beq .L299 +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 165 + + + 3806 .loc 1 2172 3 is_stmt 1 view .LVU1308 +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3807 .loc 1 2172 11 is_stmt 0 view .LVU1309 + 3808 0048 94F85D00 ldrb r0, [r4, #93] @ zero_extendqisi2 + 3809 .LVL239: +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3810 .loc 1 2172 11 view .LVU1310 + 3811 004c C0B2 uxtb r0, r0 +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3812 .loc 1 2172 6 view .LVU1311 + 3813 004e 0428 cmp r0, #4 + 3814 0050 02D0 beq .L281 +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3815 .loc 1 2174 5 is_stmt 1 view .LVU1312 +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3816 .loc 1 2174 17 is_stmt 0 view .LVU1313 + 3817 0052 0520 movs r0, #5 + 3818 0054 84F85D00 strb r0, [r4, #93] + 3819 .L281: +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 3820 .loc 1 2178 3 is_stmt 1 view .LVU1314 +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 3821 .loc 1 2178 21 is_stmt 0 view .LVU1315 + 3822 0058 0020 movs r0, #0 + 3823 005a 2066 str r0, [r4, #96] +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 3824 .loc 1 2179 3 is_stmt 1 view .LVU1316 +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 3825 .loc 1 2179 21 is_stmt 0 view .LVU1317 + 3826 005c A163 str r1, [r4, #56] +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 3827 .loc 1 2180 3 is_stmt 1 view .LVU1318 +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 3828 .loc 1 2180 21 is_stmt 0 view .LVU1319 + 3829 005e A387 strh r3, [r4, #60] @ movhi +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + 3830 .loc 1 2181 3 is_stmt 1 view .LVU1320 +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + 3831 .loc 1 2181 21 is_stmt 0 view .LVU1321 + 3832 0060 E387 strh r3, [r4, #62] @ movhi +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 3833 .loc 1 2182 3 is_stmt 1 view .LVU1322 +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 3834 .loc 1 2182 21 is_stmt 0 view .LVU1323 + 3835 0062 2264 str r2, [r4, #64] +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 3836 .loc 1 2183 3 is_stmt 1 view .LVU1324 +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 3837 .loc 1 2183 21 is_stmt 0 view .LVU1325 + 3838 0064 A4F84430 strh r3, [r4, #68] @ movhi +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3839 .loc 1 2184 3 is_stmt 1 view .LVU1326 +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3840 .loc 1 2184 21 is_stmt 0 view .LVU1327 + 3841 0068 A4F84630 strh r3, [r4, #70] @ movhi +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 3842 .loc 1 2187 3 is_stmt 1 view .LVU1328 + ARM GAS /tmp/ccywxtmH.s page 166 + + +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 3843 .loc 1 2187 21 is_stmt 0 view .LVU1329 + 3844 006c E064 str r0, [r4, #76] +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3845 .loc 1 2188 3 is_stmt 1 view .LVU1330 +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3846 .loc 1 2188 21 is_stmt 0 view .LVU1331 + 3847 006e 2065 str r0, [r4, #80] +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3848 .loc 1 2200 3 is_stmt 1 view .LVU1332 +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3849 .loc 1 2200 18 is_stmt 0 view .LVU1333 + 3850 0070 E368 ldr r3, [r4, #12] + 3851 .LVL240: +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3852 .loc 1 2200 6 view .LVU1334 + 3853 0072 B3F5E06F cmp r3, #1792 + 3854 0076 05D8 bhi .L282 +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3855 .loc 1 2200 58 discriminator 1 view .LVU1335 + 3856 0078 A36D ldr r3, [r4, #88] +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3857 .loc 1 2200 72 discriminator 1 view .LVU1336 + 3858 007a 5B69 ldr r3, [r3, #20] +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3859 .loc 1 2200 50 discriminator 1 view .LVU1337 + 3860 007c B3F5806F cmp r3, #1024 + 3861 0080 00F0C680 beq .L300 + 3862 .L282: +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3863 .loc 1 2209 3 is_stmt 1 view .LVU1338 + 3864 0084 2268 ldr r2, [r4] + 3865 .LVL241: +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3866 .loc 1 2209 3 is_stmt 0 view .LVU1339 + 3867 0086 5368 ldr r3, [r2, #4] + 3868 0088 23F4C043 bic r3, r3, #24576 + 3869 008c 5360 str r3, [r2, #4] + 3870 .LVL242: +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3871 .loc 1 2212 3 is_stmt 1 view .LVU1340 +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3872 .loc 1 2212 17 is_stmt 0 view .LVU1341 + 3873 008e E368 ldr r3, [r4, #12] +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3874 .loc 1 2212 6 view .LVU1342 + 3875 0090 B3F5E06F cmp r3, #1792 + 3876 0094 28D9 bls .L283 +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3877 .loc 1 2215 5 is_stmt 1 view .LVU1343 + 3878 0096 2268 ldr r2, [r4] + 3879 0098 5368 ldr r3, [r2, #4] + 3880 009a 23F48053 bic r3, r3, #4096 + 3881 009e 5360 str r3, [r2, #4] + 3882 .L284: +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3883 .loc 1 2255 3 view .LVU1344 + ARM GAS /tmp/ccywxtmH.s page 167 + + +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3884 .loc 1 2255 11 is_stmt 0 view .LVU1345 + 3885 00a0 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 3886 00a4 DBB2 uxtb r3, r3 +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3887 .loc 1 2255 6 view .LVU1346 + 3888 00a6 042B cmp r3, #4 + 3889 00a8 69D0 beq .L302 +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + 3890 .loc 1 2264 5 is_stmt 1 view .LVU1347 +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + 3891 .loc 1 2264 9 is_stmt 0 view .LVU1348 + 3892 00aa A36D ldr r3, [r4, #88] +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + 3893 .loc 1 2264 40 view .LVU1349 + 3894 00ac 5A4A ldr r2, .L305 + 3895 00ae DA62 str r2, [r3, #44] +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3896 .loc 1 2265 5 is_stmt 1 view .LVU1350 +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3897 .loc 1 2265 9 is_stmt 0 view .LVU1351 + 3898 00b0 A36D ldr r3, [r4, #88] +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3899 .loc 1 2265 40 view .LVU1352 + 3900 00b2 5A4A ldr r2, .L305+4 + 3901 00b4 9A62 str r2, [r3, #40] + 3902 .L289: +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3903 .loc 1 2269 3 is_stmt 1 view .LVU1353 +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3904 .loc 1 2269 7 is_stmt 0 view .LVU1354 + 3905 00b6 A36D ldr r3, [r4, #88] +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3906 .loc 1 2269 35 view .LVU1355 + 3907 00b8 594A ldr r2, .L305+8 + 3908 00ba 1A63 str r2, [r3, #48] +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3909 .loc 1 2272 3 is_stmt 1 view .LVU1356 +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3910 .loc 1 2272 7 is_stmt 0 view .LVU1357 + 3911 00bc A36D ldr r3, [r4, #88] +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3912 .loc 1 2272 35 view .LVU1358 + 3913 00be 0022 movs r2, #0 + 3914 00c0 5A63 str r2, [r3, #52] +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3915 .loc 1 2275 3 is_stmt 1 view .LVU1359 +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3916 .loc 1 2275 63 is_stmt 0 view .LVU1360 + 3917 00c2 2168 ldr r1, [r4] + 3918 .LVL243: +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3919 .loc 1 2276 38 view .LVU1361 + 3920 00c4 B4F84630 ldrh r3, [r4, #70] +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3921 .loc 1 2275 17 view .LVU1362 + 3922 00c8 9BB2 uxth r3, r3 + ARM GAS /tmp/ccywxtmH.s page 168 + + + 3923 00ca 226C ldr r2, [r4, #64] + 3924 00cc 0C31 adds r1, r1, #12 + 3925 00ce A06D ldr r0, [r4, #88] + 3926 00d0 FFF7FEFF bl HAL_DMA_Start_IT + 3927 .LVL244: +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3928 .loc 1 2275 6 view .LVU1363 + 3929 00d4 0028 cmp r0, #0 + 3930 00d6 59D0 beq .L290 +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3931 .loc 1 2279 5 is_stmt 1 view .LVU1364 + 3932 00d8 236E ldr r3, [r4, #96] + 3933 00da 43F01003 orr r3, r3, #16 + 3934 00de 2366 str r3, [r4, #96] +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3935 .loc 1 2280 5 view .LVU1365 + 3936 .LVL245: +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3937 .loc 1 2282 5 view .LVU1366 +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3938 .loc 1 2282 17 is_stmt 0 view .LVU1367 + 3939 00e0 0120 movs r0, #1 + 3940 00e2 84F85D00 strb r0, [r4, #93] +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3941 .loc 1 2283 5 is_stmt 1 view .LVU1368 + 3942 00e6 85E0 b .L280 + 3943 .LVL246: + 3944 .L283: +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3945 .loc 1 2220 5 view .LVU1369 + 3946 00e8 2268 ldr r2, [r4] + 3947 00ea 5368 ldr r3, [r2, #4] + 3948 00ec 43F48053 orr r3, r3, #4096 + 3949 00f0 5360 str r3, [r2, #4] +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3950 .loc 1 2222 5 view .LVU1370 +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3951 .loc 1 2222 13 is_stmt 0 view .LVU1371 + 3952 00f2 636D ldr r3, [r4, #84] +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3953 .loc 1 2222 27 view .LVU1372 + 3954 00f4 5B69 ldr r3, [r3, #20] +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3955 .loc 1 2222 8 view .LVU1373 + 3956 00f6 B3F5806F cmp r3, #1024 + 3957 00fa 1AD0 beq .L303 + 3958 .L285: +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3959 .loc 1 2236 5 is_stmt 1 view .LVU1374 +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3960 .loc 1 2236 13 is_stmt 0 view .LVU1375 + 3961 00fc A36D ldr r3, [r4, #88] +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3962 .loc 1 2236 27 view .LVU1376 + 3963 00fe 5B69 ldr r3, [r3, #20] +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3964 .loc 1 2236 8 view .LVU1377 + ARM GAS /tmp/ccywxtmH.s page 169 + + + 3965 0100 B3F5806F cmp r3, #1024 + 3966 0104 CCD1 bne .L284 +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 3967 .loc 1 2239 7 is_stmt 1 view .LVU1378 + 3968 0106 2268 ldr r2, [r4] + 3969 0108 5368 ldr r3, [r2, #4] + 3970 010a 23F48053 bic r3, r3, #4096 + 3971 010e 5360 str r3, [r2, #4] +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3972 .loc 1 2241 7 view .LVU1379 +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3973 .loc 1 2241 16 is_stmt 0 view .LVU1380 + 3974 0110 B4F84630 ldrh r3, [r4, #70] +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3975 .loc 1 2241 10 view .LVU1381 + 3976 0114 13F0010F tst r3, #1 + 3977 0118 24D1 bne .L287 +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = hspi->RxXferCount >> 1U; + 3978 .loc 1 2243 9 is_stmt 1 view .LVU1382 + 3979 011a 2268 ldr r2, [r4] + 3980 011c 5368 ldr r3, [r2, #4] + 3981 011e 23F40053 bic r3, r3, #8192 + 3982 0122 5360 str r3, [r2, #4] +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3983 .loc 1 2244 9 view .LVU1383 +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3984 .loc 1 2244 33 is_stmt 0 view .LVU1384 + 3985 0124 B4F84630 ldrh r3, [r4, #70] +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3986 .loc 1 2244 27 view .LVU1385 + 3987 0128 C3F34E03 ubfx r3, r3, #1, #15 + 3988 012c A4F84630 strh r3, [r4, #70] @ movhi + 3989 0130 B6E7 b .L284 + 3990 .L303: +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3991 .loc 1 2224 7 is_stmt 1 view .LVU1386 +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3992 .loc 1 2224 16 is_stmt 0 view .LVU1387 + 3993 0132 A38F ldrh r3, [r4, #60] +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3994 .loc 1 2224 10 view .LVU1388 + 3995 0134 13F0010F tst r3, #1 + 3996 0138 09D1 bne .L286 +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = hspi->TxXferCount >> 1U; + 3997 .loc 1 2226 9 is_stmt 1 view .LVU1389 + 3998 013a 2268 ldr r2, [r4] + 3999 013c 5368 ldr r3, [r2, #4] + 4000 013e 23F48043 bic r3, r3, #16384 + 4001 0142 5360 str r3, [r2, #4] +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4002 .loc 1 2227 9 view .LVU1390 +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4003 .loc 1 2227 33 is_stmt 0 view .LVU1391 + 4004 0144 E38F ldrh r3, [r4, #62] +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4005 .loc 1 2227 27 view .LVU1392 + 4006 0146 C3F34E03 ubfx r3, r3, #1, #15 + ARM GAS /tmp/ccywxtmH.s page 170 + + + 4007 014a E387 strh r3, [r4, #62] @ movhi + 4008 014c D6E7 b .L285 + 4009 .L286: +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + 4010 .loc 1 2231 9 is_stmt 1 view .LVU1393 + 4011 014e 2268 ldr r2, [r4] + 4012 0150 5368 ldr r3, [r2, #4] + 4013 0152 43F48043 orr r3, r3, #16384 + 4014 0156 5360 str r3, [r2, #4] +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4015 .loc 1 2232 9 view .LVU1394 +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4016 .loc 1 2232 34 is_stmt 0 view .LVU1395 + 4017 0158 E38F ldrh r3, [r4, #62] +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4018 .loc 1 2232 55 view .LVU1396 + 4019 015a C3F34E03 ubfx r3, r3, #1, #15 + 4020 015e 0133 adds r3, r3, #1 +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4021 .loc 1 2232 27 view .LVU1397 + 4022 0160 E387 strh r3, [r4, #62] @ movhi + 4023 0162 CBE7 b .L285 + 4024 .L287: +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + 4025 .loc 1 2248 9 is_stmt 1 view .LVU1398 + 4026 0164 2268 ldr r2, [r4] + 4027 0166 5368 ldr r3, [r2, #4] + 4028 0168 43F40053 orr r3, r3, #8192 + 4029 016c 5360 str r3, [r2, #4] +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4030 .loc 1 2249 9 view .LVU1399 +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4031 .loc 1 2249 34 is_stmt 0 view .LVU1400 + 4032 016e B4F84630 ldrh r3, [r4, #70] +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4033 .loc 1 2249 55 view .LVU1401 + 4034 0172 C3F34E03 ubfx r3, r3, #1, #15 + 4035 0176 0133 adds r3, r3, #1 +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4036 .loc 1 2249 27 view .LVU1402 + 4037 0178 A4F84630 strh r3, [r4, #70] @ movhi + 4038 017c 90E7 b .L284 + 4039 .L302: +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + 4040 .loc 1 2258 5 is_stmt 1 view .LVU1403 +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + 4041 .loc 1 2258 9 is_stmt 0 view .LVU1404 + 4042 017e A36D ldr r3, [r4, #88] +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + 4043 .loc 1 2258 40 view .LVU1405 + 4044 0180 284A ldr r2, .L305+12 + 4045 0182 DA62 str r2, [r3, #44] +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4046 .loc 1 2259 5 is_stmt 1 view .LVU1406 +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4047 .loc 1 2259 9 is_stmt 0 view .LVU1407 + 4048 0184 A36D ldr r3, [r4, #88] + ARM GAS /tmp/ccywxtmH.s page 171 + + +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4049 .loc 1 2259 40 view .LVU1408 + 4050 0186 284A ldr r2, .L305+16 + 4051 0188 9A62 str r2, [r3, #40] + 4052 018a 94E7 b .L289 + 4053 .LVL247: + 4054 .L290: +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4055 .loc 1 2287 3 is_stmt 1 view .LVU1409 + 4056 018c 2268 ldr r2, [r4] + 4057 018e 5368 ldr r3, [r2, #4] + 4058 0190 43F00103 orr r3, r3, #1 + 4059 0194 5360 str r3, [r2, #4] +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = NULL; + 4060 .loc 1 2291 3 view .LVU1410 +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = NULL; + 4061 .loc 1 2291 7 is_stmt 0 view .LVU1411 + 4062 0196 626D ldr r2, [r4, #84] +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = NULL; + 4063 .loc 1 2291 38 view .LVU1412 + 4064 0198 0023 movs r3, #0 + 4065 019a D362 str r3, [r2, #44] +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = NULL; + 4066 .loc 1 2292 3 is_stmt 1 view .LVU1413 +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = NULL; + 4067 .loc 1 2292 7 is_stmt 0 view .LVU1414 + 4068 019c 626D ldr r2, [r4, #84] +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = NULL; + 4069 .loc 1 2292 38 view .LVU1415 + 4070 019e 9362 str r3, [r2, #40] +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + 4071 .loc 1 2293 3 is_stmt 1 view .LVU1416 +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + 4072 .loc 1 2293 7 is_stmt 0 view .LVU1417 + 4073 01a0 626D ldr r2, [r4, #84] +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + 4074 .loc 1 2293 38 view .LVU1418 + 4075 01a2 1363 str r3, [r2, #48] +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4076 .loc 1 2294 3 is_stmt 1 view .LVU1419 +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4077 .loc 1 2294 7 is_stmt 0 view .LVU1420 + 4078 01a4 626D ldr r2, [r4, #84] +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4079 .loc 1 2294 38 view .LVU1421 + 4080 01a6 5363 str r3, [r2, #52] +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 4081 .loc 1 2297 3 is_stmt 1 view .LVU1422 +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 4082 .loc 1 2297 91 is_stmt 0 view .LVU1423 + 4083 01a8 2268 ldr r2, [r4] +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4084 .loc 1 2298 38 view .LVU1424 + 4085 01aa E38F ldrh r3, [r4, #62] +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 4086 .loc 1 2297 17 view .LVU1425 + 4087 01ac 9BB2 uxth r3, r3 + ARM GAS /tmp/ccywxtmH.s page 172 + + + 4088 01ae 0C32 adds r2, r2, #12 + 4089 01b0 A16B ldr r1, [r4, #56] + 4090 01b2 606D ldr r0, [r4, #84] + 4091 01b4 FFF7FEFF bl HAL_DMA_Start_IT + 4092 .LVL248: +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 4093 .loc 1 2297 6 view .LVU1426 + 4094 01b8 98B9 cbnz r0, .L304 +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4095 .loc 1 2309 3 is_stmt 1 view .LVU1427 +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4096 .loc 1 2309 12 is_stmt 0 view .LVU1428 + 4097 01ba 2368 ldr r3, [r4] +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4098 .loc 1 2309 22 view .LVU1429 + 4099 01bc 1A68 ldr r2, [r3] +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4100 .loc 1 2309 6 view .LVU1430 + 4101 01be 12F0400F tst r2, #64 + 4102 01c2 03D1 bne .L292 +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4103 .loc 1 2312 5 is_stmt 1 view .LVU1431 + 4104 01c4 1A68 ldr r2, [r3] + 4105 01c6 42F04002 orr r2, r2, #64 + 4106 01ca 1A60 str r2, [r3] + 4107 .L292: +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4108 .loc 1 2315 3 view .LVU1432 + 4109 01cc 2268 ldr r2, [r4] + 4110 01ce 5368 ldr r3, [r2, #4] + 4111 01d0 43F02003 orr r3, r3, #32 + 4112 01d4 5360 str r3, [r2, #4] +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4113 .loc 1 2318 3 view .LVU1433 + 4114 01d6 2268 ldr r2, [r4] + 4115 01d8 5368 ldr r3, [r2, #4] + 4116 01da 43F00203 orr r3, r3, #2 + 4117 01de 5360 str r3, [r2, #4] + 4118 01e0 08E0 b .L280 + 4119 .L304: +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 4120 .loc 1 2301 5 view .LVU1434 + 4121 01e2 236E ldr r3, [r4, #96] + 4122 01e4 43F01003 orr r3, r3, #16 + 4123 01e8 2366 str r3, [r4, #96] +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4124 .loc 1 2302 5 view .LVU1435 + 4125 .LVL249: +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4126 .loc 1 2304 5 view .LVU1436 +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4127 .loc 1 2304 17 is_stmt 0 view .LVU1437 + 4128 01ea 0120 movs r0, #1 + 4129 01ec 84F85D00 strb r0, [r4, #93] +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4130 .loc 1 2305 5 is_stmt 1 view .LVU1438 + 4131 01f0 00E0 b .L280 + ARM GAS /tmp/ccywxtmH.s page 173 + + + 4132 .LVL250: + 4133 .L294: +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4134 .loc 1 2161 15 is_stmt 0 view .LVU1439 + 4135 01f2 0220 movs r0, #2 + 4136 .LVL251: + 4137 .L280: +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4138 .loc 1 2322 3 is_stmt 1 view .LVU1440 +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4139 .loc 1 2322 3 view .LVU1441 + 4140 01f4 0023 movs r3, #0 + 4141 01f6 84F85C30 strb r3, [r4, #92] +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4142 .loc 1 2322 3 view .LVU1442 +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4143 .loc 1 2323 3 view .LVU1443 + 4144 .LVL252: + 4145 .L278: +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4146 .loc 1 2324 1 is_stmt 0 view .LVU1444 + 4147 01fa 38BD pop {r3, r4, r5, pc} + 4148 .LVL253: + 4149 .L295: +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4150 .loc 1 2161 15 view .LVU1445 + 4151 01fc 0220 movs r0, #2 + 4152 .LVL254: +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4153 .loc 1 2161 15 view .LVU1446 + 4154 01fe F9E7 b .L280 + 4155 .LVL255: + 4156 .L296: +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4157 .loc 1 2161 15 view .LVU1447 + 4158 0200 0220 movs r0, #2 + 4159 .LVL256: +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4160 .loc 1 2161 15 view .LVU1448 + 4161 0202 F7E7 b .L280 + 4162 .LVL257: + 4163 .L297: +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4164 .loc 1 2167 15 view .LVU1449 + 4165 0204 0120 movs r0, #1 + 4166 .LVL258: +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4167 .loc 1 2167 15 view .LVU1450 + 4168 0206 F5E7 b .L280 + 4169 .LVL259: + 4170 .L298: +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4171 .loc 1 2167 15 view .LVU1451 + 4172 0208 0120 movs r0, #1 + 4173 .LVL260: +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4174 .loc 1 2167 15 view .LVU1452 + ARM GAS /tmp/ccywxtmH.s page 174 + + + 4175 020a F3E7 b .L280 + 4176 .LVL261: + 4177 .L299: +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4178 .loc 1 2167 15 view .LVU1453 + 4179 020c 0120 movs r0, #1 + 4180 .LVL262: +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4181 .loc 1 2167 15 view .LVU1454 + 4182 020e F1E7 b .L280 + 4183 .LVL263: + 4184 .L300: +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4185 .loc 1 2203 15 view .LVU1455 + 4186 0210 0120 movs r0, #1 + 4187 0212 EFE7 b .L280 + 4188 .LVL264: + 4189 .L293: +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4190 .loc 1 2152 3 view .LVU1456 + 4191 0214 0220 movs r0, #2 + 4192 0216 F0E7 b .L278 + 4193 .L306: + 4194 .align 2 + 4195 .L305: + 4196 0218 00000000 .word SPI_DMAHalfTransmitReceiveCplt + 4197 021c 00000000 .word SPI_DMATransmitReceiveCplt + 4198 0220 00000000 .word SPI_DMAError + 4199 0224 00000000 .word SPI_DMAHalfReceiveCplt + 4200 0228 00000000 .word SPI_DMAReceiveCplt + 4201 .cfi_endproc + 4202 .LFE142: + 4204 .section .text.HAL_SPI_Receive_DMA,"ax",%progbits + 4205 .align 1 + 4206 .global HAL_SPI_Receive_DMA + 4207 .syntax unified + 4208 .thumb + 4209 .thumb_func + 4211 HAL_SPI_Receive_DMA: + 4212 .LVL265: + 4213 .LFB141: +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 4214 .loc 1 1984 1 is_stmt 1 view -0 + 4215 .cfi_startproc + 4216 @ args = 0, pretend = 0, frame = 0 + 4217 @ frame_needed = 0, uses_anonymous_args = 0 +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 4218 .loc 1 1984 1 is_stmt 0 view .LVU1458 + 4219 0000 38B5 push {r3, r4, r5, lr} + 4220 .cfi_def_cfa_offset 16 + 4221 .cfi_offset 3, -16 + 4222 .cfi_offset 4, -12 + 4223 .cfi_offset 5, -8 + 4224 .cfi_offset 14, -4 + 4225 0002 0446 mov r4, r0 +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4226 .loc 1 1985 3 is_stmt 1 view .LVU1459 + ARM GAS /tmp/ccywxtmH.s page 175 + + + 4227 .LVL266: +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4228 .loc 1 1988 3 view .LVU1460 +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4229 .loc 1 1990 3 view .LVU1461 +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4230 .loc 1 1990 18 is_stmt 0 view .LVU1462 + 4231 0004 8368 ldr r3, [r0, #8] +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4232 .loc 1 1990 6 view .LVU1463 + 4233 0006 1BB9 cbnz r3, .L308 +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4234 .loc 1 1990 68 discriminator 1 view .LVU1464 + 4235 0008 4068 ldr r0, [r0, #4] + 4236 .LVL267: +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4237 .loc 1 1990 54 discriminator 1 view .LVU1465 + 4238 000a B0F5827F cmp r0, #260 + 4239 000e 69D0 beq .L321 + 4240 .L308: +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4241 .loc 1 2002 3 is_stmt 1 view .LVU1466 +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4242 .loc 1 2002 3 view .LVU1467 + 4243 0010 94F85C00 ldrb r0, [r4, #92] @ zero_extendqisi2 + 4244 0014 0128 cmp r0, #1 + 4245 0016 00F0B580 beq .L318 +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4246 .loc 1 2002 3 discriminator 2 view .LVU1468 + 4247 001a 0120 movs r0, #1 + 4248 001c 84F85C00 strb r0, [r4, #92] +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4249 .loc 1 2002 3 discriminator 2 view .LVU1469 +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4250 .loc 1 2004 3 discriminator 2 view .LVU1470 +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4251 .loc 1 2004 11 is_stmt 0 discriminator 2 view .LVU1471 + 4252 0020 94F85D50 ldrb r5, [r4, #93] @ zero_extendqisi2 + 4253 0024 EDB2 uxtb r5, r5 +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4254 .loc 1 2004 6 discriminator 2 view .LVU1472 + 4255 0026 8542 cmp r5, r0 + 4256 0028 40F0A680 bne .L319 +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4257 .loc 1 2010 3 is_stmt 1 view .LVU1473 +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4258 .loc 1 2010 6 is_stmt 0 view .LVU1474 + 4259 002c 0029 cmp r1, #0 + 4260 002e 00F0A480 beq .L310 +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4261 .loc 1 2010 23 discriminator 1 view .LVU1475 + 4262 0032 002A cmp r2, #0 + 4263 0034 00F0A180 beq .L310 +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 4264 .loc 1 2017 3 is_stmt 1 view .LVU1476 +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 4265 .loc 1 2017 21 is_stmt 0 view .LVU1477 + ARM GAS /tmp/ccywxtmH.s page 176 + + + 4266 0038 0420 movs r0, #4 + 4267 003a 84F85D00 strb r0, [r4, #93] +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 4268 .loc 1 2018 3 is_stmt 1 view .LVU1478 +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 4269 .loc 1 2018 21 is_stmt 0 view .LVU1479 + 4270 003e 0020 movs r0, #0 + 4271 0040 2066 str r0, [r4, #96] +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 4272 .loc 1 2019 3 is_stmt 1 view .LVU1480 +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 4273 .loc 1 2019 21 is_stmt 0 view .LVU1481 + 4274 0042 2164 str r1, [r4, #64] +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 4275 .loc 1 2020 3 is_stmt 1 view .LVU1482 +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 4276 .loc 1 2020 21 is_stmt 0 view .LVU1483 + 4277 0044 A4F84420 strh r2, [r4, #68] @ movhi +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4278 .loc 1 2021 3 is_stmt 1 view .LVU1484 +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4279 .loc 1 2021 21 is_stmt 0 view .LVU1485 + 4280 0048 A4F84620 strh r2, [r4, #70] @ movhi +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 4281 .loc 1 2024 3 is_stmt 1 view .LVU1486 +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 4282 .loc 1 2024 21 is_stmt 0 view .LVU1487 + 4283 004c E064 str r0, [r4, #76] +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 4284 .loc 1 2025 3 is_stmt 1 view .LVU1488 +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 4285 .loc 1 2025 21 is_stmt 0 view .LVU1489 + 4286 004e 2065 str r0, [r4, #80] +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 4287 .loc 1 2026 3 is_stmt 1 view .LVU1490 +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 4288 .loc 1 2026 21 is_stmt 0 view .LVU1491 + 4289 0050 A087 strh r0, [r4, #60] @ movhi +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4290 .loc 1 2027 3 is_stmt 1 view .LVU1492 +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4291 .loc 1 2027 21 is_stmt 0 view .LVU1493 + 4292 0052 E087 strh r0, [r4, #62] @ movhi +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4293 .loc 1 2030 3 is_stmt 1 view .LVU1494 +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4294 .loc 1 2030 6 is_stmt 0 view .LVU1495 + 4295 0054 B3F5004F cmp r3, #32768 + 4296 0058 4ED0 beq .L322 + 4297 .LVL268: + 4298 .L311: +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4299 .loc 1 2047 3 is_stmt 1 view .LVU1496 +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4300 .loc 1 2047 18 is_stmt 0 view .LVU1497 + 4301 005a E368 ldr r3, [r4, #12] +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 177 + + + 4302 .loc 1 2047 6 view .LVU1498 + 4303 005c B3F5E06F cmp r3, #1792 + 4304 0060 05D8 bhi .L312 +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4305 .loc 1 2047 58 discriminator 1 view .LVU1499 + 4306 0062 A36D ldr r3, [r4, #88] +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4307 .loc 1 2047 72 discriminator 1 view .LVU1500 + 4308 0064 5B69 ldr r3, [r3, #20] +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4309 .loc 1 2047 50 discriminator 1 view .LVU1501 + 4310 0066 B3F5806F cmp r3, #1024 + 4311 006a 00F08680 beq .L310 + 4312 .L312: +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 4313 .loc 1 2055 3 is_stmt 1 view .LVU1502 + 4314 006e 2268 ldr r2, [r4] + 4315 0070 5368 ldr r3, [r2, #4] + 4316 0072 23F40053 bic r3, r3, #8192 + 4317 0076 5360 str r3, [r2, #4] +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4318 .loc 1 2056 3 view .LVU1503 +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4319 .loc 1 2056 17 is_stmt 0 view .LVU1504 + 4320 0078 E368 ldr r3, [r4, #12] +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4321 .loc 1 2056 6 view .LVU1505 + 4322 007a B3F5E06F cmp r3, #1792 + 4323 007e 46D9 bls .L313 +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4324 .loc 1 2059 5 is_stmt 1 view .LVU1506 + 4325 0080 2268 ldr r2, [r4] + 4326 0082 5368 ldr r3, [r2, #4] + 4327 0084 23F48053 bic r3, r3, #4096 + 4328 0088 5360 str r3, [r2, #4] + 4329 .L314: +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4330 .loc 1 2085 3 view .LVU1507 +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4331 .loc 1 2085 7 is_stmt 0 view .LVU1508 + 4332 008a A36D ldr r3, [r4, #88] +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4333 .loc 1 2085 38 view .LVU1509 + 4334 008c 3E4A ldr r2, .L324 + 4335 008e DA62 str r2, [r3, #44] +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4336 .loc 1 2088 3 is_stmt 1 view .LVU1510 +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4337 .loc 1 2088 7 is_stmt 0 view .LVU1511 + 4338 0090 A36D ldr r3, [r4, #88] +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4339 .loc 1 2088 34 view .LVU1512 + 4340 0092 3E4A ldr r2, .L324+4 + 4341 0094 9A62 str r2, [r3, #40] +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4342 .loc 1 2091 3 is_stmt 1 view .LVU1513 +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 178 + + + 4343 .loc 1 2091 7 is_stmt 0 view .LVU1514 + 4344 0096 A36D ldr r3, [r4, #88] +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4345 .loc 1 2091 35 view .LVU1515 + 4346 0098 3D4A ldr r2, .L324+8 + 4347 009a 1A63 str r2, [r3, #48] +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4348 .loc 1 2094 3 is_stmt 1 view .LVU1516 +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4349 .loc 1 2094 7 is_stmt 0 view .LVU1517 + 4350 009c A36D ldr r3, [r4, #88] +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4351 .loc 1 2094 35 view .LVU1518 + 4352 009e 0022 movs r2, #0 + 4353 00a0 5A63 str r2, [r3, #52] +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 4354 .loc 1 2097 3 is_stmt 1 view .LVU1519 +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 4355 .loc 1 2097 63 is_stmt 0 view .LVU1520 + 4356 00a2 2168 ldr r1, [r4] + 4357 .LVL269: +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4358 .loc 1 2098 38 view .LVU1521 + 4359 00a4 B4F84630 ldrh r3, [r4, #70] +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 4360 .loc 1 2097 17 view .LVU1522 + 4361 00a8 9BB2 uxth r3, r3 + 4362 00aa 226C ldr r2, [r4, #64] + 4363 00ac 0C31 adds r1, r1, #12 + 4364 00ae A06D ldr r0, [r4, #88] + 4365 00b0 FFF7FEFF bl HAL_DMA_Start_IT + 4366 .LVL270: +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 4367 .loc 1 2097 6 view .LVU1523 + 4368 00b4 0146 mov r1, r0 + 4369 00b6 0028 cmp r0, #0 + 4370 00b8 56D1 bne .L323 +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4371 .loc 1 2109 3 is_stmt 1 view .LVU1524 +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4372 .loc 1 2109 12 is_stmt 0 view .LVU1525 + 4373 00ba 2368 ldr r3, [r4] +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4374 .loc 1 2109 22 view .LVU1526 + 4375 00bc 1A68 ldr r2, [r3] +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4376 .loc 1 2109 6 view .LVU1527 + 4377 00be 12F0400F tst r2, #64 + 4378 00c2 03D1 bne .L317 +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4379 .loc 1 2112 5 is_stmt 1 view .LVU1528 + 4380 00c4 1A68 ldr r2, [r3] + 4381 00c6 42F04002 orr r2, r2, #64 + 4382 00ca 1A60 str r2, [r3] + 4383 .L317: +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4384 .loc 1 2116 3 view .LVU1529 + ARM GAS /tmp/ccywxtmH.s page 179 + + + 4385 00cc 2268 ldr r2, [r4] + 4386 00ce 5368 ldr r3, [r2, #4] + 4387 00d0 43F02003 orr r3, r3, #32 + 4388 00d4 5360 str r3, [r2, #4] +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4389 .loc 1 2119 3 view .LVU1530 + 4390 00d6 2268 ldr r2, [r4] + 4391 00d8 5368 ldr r3, [r2, #4] + 4392 00da 43F00103 orr r3, r3, #1 + 4393 00de 5360 str r3, [r2, #4] +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4394 .loc 1 1985 21 is_stmt 0 view .LVU1531 + 4395 00e0 0D46 mov r5, r1 + 4396 00e2 4AE0 b .L310 + 4397 .LVL271: + 4398 .L321: +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4399 .loc 1 1992 5 is_stmt 1 view .LVU1532 +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4400 .loc 1 1992 17 is_stmt 0 view .LVU1533 + 4401 00e4 0423 movs r3, #4 + 4402 00e6 84F85D30 strb r3, [r4, #93] +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4403 .loc 1 1995 5 is_stmt 1 view .LVU1534 +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4404 .loc 1 1998 5 view .LVU1535 +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4405 .loc 1 1998 12 is_stmt 0 view .LVU1536 + 4406 00ea 1346 mov r3, r2 + 4407 00ec 0A46 mov r2, r1 + 4408 .LVL272: +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4409 .loc 1 1998 12 view .LVU1537 + 4410 00ee 2046 mov r0, r4 + 4411 00f0 FFF7FEFF bl HAL_SPI_TransmitReceive_DMA + 4412 .LVL273: +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4413 .loc 1 1998 12 view .LVU1538 + 4414 00f4 0546 mov r5, r0 + 4415 00f6 43E0 b .L309 + 4416 .LVL274: + 4417 .L322: +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); + 4418 .loc 1 2033 5 is_stmt 1 view .LVU1539 + 4419 00f8 2268 ldr r2, [r4] + 4420 .LVL275: +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); + 4421 .loc 1 2033 5 is_stmt 0 view .LVU1540 + 4422 00fa 1368 ldr r3, [r2] + 4423 00fc 23F04003 bic r3, r3, #64 + 4424 0100 1360 str r3, [r2] + 4425 .LVL276: +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4426 .loc 1 2034 5 is_stmt 1 view .LVU1541 + 4427 0102 2268 ldr r2, [r4] + 4428 0104 1368 ldr r3, [r2] + 4429 0106 23F48043 bic r3, r3, #16384 + ARM GAS /tmp/ccywxtmH.s page 180 + + + 4430 010a 1360 str r3, [r2] + 4431 010c A5E7 b .L311 + 4432 .L313: +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4433 .loc 1 2064 5 view .LVU1542 + 4434 010e 2268 ldr r2, [r4] + 4435 0110 5368 ldr r3, [r2, #4] + 4436 0112 43F48053 orr r3, r3, #4096 + 4437 0116 5360 str r3, [r2, #4] +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4438 .loc 1 2066 5 view .LVU1543 +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4439 .loc 1 2066 13 is_stmt 0 view .LVU1544 + 4440 0118 A36D ldr r3, [r4, #88] +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4441 .loc 1 2066 27 view .LVU1545 + 4442 011a 5B69 ldr r3, [r3, #20] +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4443 .loc 1 2066 8 view .LVU1546 + 4444 011c B3F5806F cmp r3, #1024 + 4445 0120 B3D1 bne .L314 +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4446 .loc 1 2069 7 is_stmt 1 view .LVU1547 + 4447 0122 2268 ldr r2, [r4] + 4448 0124 5368 ldr r3, [r2, #4] + 4449 0126 23F48053 bic r3, r3, #4096 + 4450 012a 5360 str r3, [r2, #4] +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4451 .loc 1 2071 7 view .LVU1548 +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4452 .loc 1 2071 16 is_stmt 0 view .LVU1549 + 4453 012c B4F84630 ldrh r3, [r4, #70] +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4454 .loc 1 2071 10 view .LVU1550 + 4455 0130 13F0010F tst r3, #1 + 4456 0134 0BD1 bne .L315 +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = hspi->RxXferCount >> 1U; + 4457 .loc 1 2073 9 is_stmt 1 view .LVU1551 + 4458 0136 2268 ldr r2, [r4] + 4459 0138 5368 ldr r3, [r2, #4] + 4460 013a 23F40053 bic r3, r3, #8192 + 4461 013e 5360 str r3, [r2, #4] +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4462 .loc 1 2074 9 view .LVU1552 +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4463 .loc 1 2074 33 is_stmt 0 view .LVU1553 + 4464 0140 B4F84630 ldrh r3, [r4, #70] +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4465 .loc 1 2074 27 view .LVU1554 + 4466 0144 C3F34E03 ubfx r3, r3, #1, #15 + 4467 0148 A4F84630 strh r3, [r4, #70] @ movhi + 4468 014c 9DE7 b .L314 + 4469 .L315: +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + 4470 .loc 1 2078 9 is_stmt 1 view .LVU1555 + 4471 014e 2268 ldr r2, [r4] + 4472 0150 5368 ldr r3, [r2, #4] + ARM GAS /tmp/ccywxtmH.s page 181 + + + 4473 0152 43F40053 orr r3, r3, #8192 + 4474 0156 5360 str r3, [r2, #4] +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4475 .loc 1 2079 9 view .LVU1556 +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4476 .loc 1 2079 34 is_stmt 0 view .LVU1557 + 4477 0158 B4F84630 ldrh r3, [r4, #70] +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4478 .loc 1 2079 55 view .LVU1558 + 4479 015c C3F34E03 ubfx r3, r3, #1, #15 + 4480 0160 0133 adds r3, r3, #1 +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4481 .loc 1 2079 27 view .LVU1559 + 4482 0162 A4F84630 strh r3, [r4, #70] @ movhi + 4483 0166 90E7 b .L314 + 4484 .LVL277: + 4485 .L323: +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 4486 .loc 1 2101 5 is_stmt 1 view .LVU1560 + 4487 0168 236E ldr r3, [r4, #96] + 4488 016a 43F01003 orr r3, r3, #16 + 4489 016e 2366 str r3, [r4, #96] +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4490 .loc 1 2102 5 view .LVU1561 + 4491 .LVL278: +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4492 .loc 1 2104 5 view .LVU1562 +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4493 .loc 1 2104 17 is_stmt 0 view .LVU1563 + 4494 0170 0123 movs r3, #1 + 4495 0172 84F85D30 strb r3, [r4, #93] +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4496 .loc 1 2105 5 is_stmt 1 view .LVU1564 + 4497 0176 00E0 b .L310 + 4498 .LVL279: + 4499 .L319: +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 4500 .loc 1 2006 15 is_stmt 0 view .LVU1565 + 4501 0178 0225 movs r5, #2 + 4502 .LVL280: + 4503 .L310: +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4504 .loc 1 2123 3 is_stmt 1 view .LVU1566 +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4505 .loc 1 2123 3 view .LVU1567 + 4506 017a 0023 movs r3, #0 + 4507 017c 84F85C30 strb r3, [r4, #92] +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4508 .loc 1 2123 3 view .LVU1568 +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4509 .loc 1 2124 3 view .LVU1569 + 4510 .LVL281: + 4511 .L309: +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4512 .loc 1 2125 1 is_stmt 0 view .LVU1570 + 4513 0180 2846 mov r0, r5 + 4514 0182 38BD pop {r3, r4, r5, pc} + ARM GAS /tmp/ccywxtmH.s page 182 + + + 4515 .LVL282: + 4516 .L318: +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4517 .loc 1 2002 3 view .LVU1571 + 4518 0184 0225 movs r5, #2 + 4519 0186 FBE7 b .L309 + 4520 .L325: + 4521 .align 2 + 4522 .L324: + 4523 0188 00000000 .word SPI_DMAHalfReceiveCplt + 4524 018c 00000000 .word SPI_DMAReceiveCplt + 4525 0190 00000000 .word SPI_DMAError + 4526 .cfi_endproc + 4527 .LFE141: + 4529 .section .text.HAL_SPI_Abort,"ax",%progbits + 4530 .align 1 + 4531 .global HAL_SPI_Abort + 4532 .syntax unified + 4533 .thumb + 4534 .thumb_func + 4536 HAL_SPI_Abort: + 4537 .LVL283: + 4538 .LFB143: +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode; + 4539 .loc 1 2340 1 is_stmt 1 view -0 + 4540 .cfi_startproc + 4541 @ args = 0, pretend = 0, frame = 16 + 4542 @ frame_needed = 0, uses_anonymous_args = 0 +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode; + 4543 .loc 1 2340 1 is_stmt 0 view .LVU1573 + 4544 0000 10B5 push {r4, lr} + 4545 .cfi_def_cfa_offset 8 + 4546 .cfi_offset 4, -8 + 4547 .cfi_offset 14, -4 + 4548 0002 86B0 sub sp, sp, #24 + 4549 .cfi_def_cfa_offset 32 + 4550 0004 0446 mov r4, r0 +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; + 4551 .loc 1 2341 3 is_stmt 1 view .LVU1574 +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t resetcount; + 4552 .loc 1 2342 3 view .LVU1575 +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4553 .loc 1 2343 3 view .LVU1576 +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 4554 .loc 1 2346 3 view .LVU1577 + 4555 .LVL284: +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4556 .loc 1 2347 3 view .LVU1578 +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4557 .loc 1 2347 61 is_stmt 0 view .LVU1579 + 4558 0006 5E4B ldr r3, .L347 + 4559 0008 1B68 ldr r3, [r3] + 4560 000a 5E4A ldr r2, .L347+4 + 4561 000c A2FB0323 umull r2, r3, r2, r3 + 4562 0010 5B0A lsrs r3, r3, #9 +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4563 .loc 1 2347 36 view .LVU1580 + ARM GAS /tmp/ccywxtmH.s page 183 + + + 4564 0012 6422 movs r2, #100 + 4565 0014 02FB03F3 mul r3, r2, r3 +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4566 .loc 1 2347 14 view .LVU1581 + 4567 0018 0493 str r3, [sp, #16] +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4568 .loc 1 2348 3 is_stmt 1 view .LVU1582 +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4569 .loc 1 2348 9 is_stmt 0 view .LVU1583 + 4570 001a 049B ldr r3, [sp, #16] + 4571 001c 0593 str r3, [sp, #20] +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4572 .loc 1 2351 3 is_stmt 1 view .LVU1584 + 4573 001e 0268 ldr r2, [r0] + 4574 0020 5368 ldr r3, [r2, #4] + 4575 0022 23F02003 bic r3, r3, #32 + 4576 0026 5360 str r3, [r2, #4] +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4577 .loc 1 2354 3 view .LVU1585 +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4578 .loc 1 2354 7 is_stmt 0 view .LVU1586 + 4579 0028 0268 ldr r2, [r0] + 4580 002a 5368 ldr r3, [r2, #4] +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4581 .loc 1 2354 6 view .LVU1587 + 4582 002c 13F0800F tst r3, #128 + 4583 0030 12D0 beq .L327 +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ + 4584 .loc 1 2356 5 is_stmt 1 view .LVU1588 +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ + 4585 .loc 1 2356 17 is_stmt 0 view .LVU1589 + 4586 0032 554B ldr r3, .L347+8 + 4587 0034 0365 str r3, [r0, #80] + 4588 .L330: +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4589 .loc 1 2358 5 is_stmt 1 view .LVU1590 +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4590 .loc 1 2360 7 view .LVU1591 +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4591 .loc 1 2360 17 is_stmt 0 view .LVU1592 + 4592 0036 059B ldr r3, [sp, #20] +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4593 .loc 1 2360 10 view .LVU1593 + 4594 0038 43B1 cbz r3, .L345 +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 4595 .loc 1 2365 7 is_stmt 1 view .LVU1594 +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 4596 .loc 1 2365 12 is_stmt 0 view .LVU1595 + 4597 003a 059B ldr r3, [sp, #20] + 4598 003c 013B subs r3, r3, #1 + 4599 003e 0593 str r3, [sp, #20] +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 4600 .loc 1 2366 26 is_stmt 1 view .LVU1596 +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 4601 .loc 1 2366 18 is_stmt 0 view .LVU1597 + 4602 0040 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 4603 0044 DBB2 uxtb r3, r3 + ARM GAS /tmp/ccywxtmH.s page 184 + + +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 4604 .loc 1 2366 26 view .LVU1598 + 4605 0046 072B cmp r3, #7 + 4606 0048 F5D1 bne .L330 + 4607 004a 03E0 b .L329 + 4608 .L345: +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 4609 .loc 1 2362 9 is_stmt 1 view .LVU1599 + 4610 004c 236E ldr r3, [r4, #96] + 4611 004e 43F04003 orr r3, r3, #64 + 4612 0052 2366 str r3, [r4, #96] +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4613 .loc 1 2363 9 view .LVU1600 + 4614 .L329: +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4615 .loc 1 2368 5 view .LVU1601 +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4616 .loc 1 2368 11 is_stmt 0 view .LVU1602 + 4617 0054 049B ldr r3, [sp, #16] + 4618 0056 0593 str r3, [sp, #20] + 4619 .L327: +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4620 .loc 1 2371 3 is_stmt 1 view .LVU1603 +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4621 .loc 1 2371 7 is_stmt 0 view .LVU1604 + 4622 0058 5368 ldr r3, [r2, #4] +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4623 .loc 1 2371 6 view .LVU1605 + 4624 005a 13F0400F tst r3, #64 + 4625 005e 12D0 beq .L331 +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ + 4626 .loc 1 2373 5 is_stmt 1 view .LVU1606 +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ + 4627 .loc 1 2373 17 is_stmt 0 view .LVU1607 + 4628 0060 4A4B ldr r3, .L347+12 + 4629 0062 E364 str r3, [r4, #76] + 4630 .L334: +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4631 .loc 1 2375 5 is_stmt 1 view .LVU1608 +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4632 .loc 1 2377 7 view .LVU1609 +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4633 .loc 1 2377 17 is_stmt 0 view .LVU1610 + 4634 0064 059B ldr r3, [sp, #20] +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4635 .loc 1 2377 10 view .LVU1611 + 4636 0066 43B1 cbz r3, .L346 +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 4637 .loc 1 2382 7 is_stmt 1 view .LVU1612 +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 4638 .loc 1 2382 12 is_stmt 0 view .LVU1613 + 4639 0068 059B ldr r3, [sp, #20] + 4640 006a 013B subs r3, r3, #1 + 4641 006c 0593 str r3, [sp, #20] +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 4642 .loc 1 2383 26 is_stmt 1 view .LVU1614 +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + ARM GAS /tmp/ccywxtmH.s page 185 + + + 4643 .loc 1 2383 18 is_stmt 0 view .LVU1615 + 4644 006e 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 4645 0072 DBB2 uxtb r3, r3 +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 4646 .loc 1 2383 26 view .LVU1616 + 4647 0074 072B cmp r3, #7 + 4648 0076 F5D1 bne .L334 + 4649 0078 03E0 b .L333 + 4650 .L346: +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 4651 .loc 1 2379 9 is_stmt 1 view .LVU1617 + 4652 007a 236E ldr r3, [r4, #96] + 4653 007c 43F04003 orr r3, r3, #64 + 4654 0080 2366 str r3, [r4, #96] +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4655 .loc 1 2380 9 view .LVU1618 + 4656 .L333: +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4657 .loc 1 2385 5 view .LVU1619 +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4658 .loc 1 2385 11 is_stmt 0 view .LVU1620 + 4659 0082 049B ldr r3, [sp, #16] + 4660 0084 0593 str r3, [sp, #20] + 4661 .L331: +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4662 .loc 1 2389 3 is_stmt 1 view .LVU1621 +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4663 .loc 1 2389 7 is_stmt 0 view .LVU1622 + 4664 0086 5368 ldr r3, [r2, #4] +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4665 .loc 1 2389 6 view .LVU1623 + 4666 0088 13F0020F tst r3, #2 + 4667 008c 2AD0 beq .L335 +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4668 .loc 1 2392 5 is_stmt 1 view .LVU1624 +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4669 .loc 1 2392 13 is_stmt 0 view .LVU1625 + 4670 008e 636D ldr r3, [r4, #84] +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4671 .loc 1 2392 8 view .LVU1626 + 4672 0090 43B3 cbz r3, .L335 +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4673 .loc 1 2396 7 is_stmt 1 view .LVU1627 +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4674 .loc 1 2396 39 is_stmt 0 view .LVU1628 + 4675 0092 0022 movs r2, #0 + 4676 0094 5A63 str r2, [r3, #52] +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4677 .loc 1 2399 7 is_stmt 1 view .LVU1629 +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4678 .loc 1 2399 11 is_stmt 0 view .LVU1630 + 4679 0096 606D ldr r0, [r4, #84] + 4680 .LVL285: +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4681 .loc 1 2399 11 view .LVU1631 + 4682 0098 FFF7FEFF bl HAL_DMA_Abort + 4683 .LVL286: + ARM GAS /tmp/ccywxtmH.s page 186 + + +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4684 .loc 1 2399 10 view .LVU1632 + 4685 009c 08B1 cbz r0, .L336 +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4686 .loc 1 2401 9 is_stmt 1 view .LVU1633 +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4687 .loc 1 2401 25 is_stmt 0 view .LVU1634 + 4688 009e 4023 movs r3, #64 + 4689 00a0 2366 str r3, [r4, #96] + 4690 .L336: +2405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4691 .loc 1 2405 7 is_stmt 1 view .LVU1635 + 4692 00a2 2268 ldr r2, [r4] + 4693 00a4 5368 ldr r3, [r2, #4] + 4694 00a6 23F00203 bic r3, r3, #2 + 4695 00aa 5360 str r3, [r2, #4] +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4696 .loc 1 2407 7 view .LVU1636 +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4697 .loc 1 2407 11 is_stmt 0 view .LVU1637 + 4698 00ac FFF7FEFF bl HAL_GetTick + 4699 .LVL287: + 4700 00b0 0246 mov r2, r0 + 4701 00b2 6421 movs r1, #100 + 4702 00b4 2046 mov r0, r4 + 4703 00b6 FFF7FEFF bl SPI_EndRxTxTransaction + 4704 .LVL288: +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4705 .loc 1 2407 10 view .LVU1638 + 4706 00ba 08B1 cbz r0, .L337 +2409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4707 .loc 1 2409 9 is_stmt 1 view .LVU1639 +2409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4708 .loc 1 2409 25 is_stmt 0 view .LVU1640 + 4709 00bc 4023 movs r3, #64 + 4710 00be 2366 str r3, [r4, #96] + 4711 .L337: +2413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4712 .loc 1 2413 7 is_stmt 1 view .LVU1641 + 4713 00c0 2268 ldr r2, [r4] + 4714 00c2 1368 ldr r3, [r2] + 4715 00c4 23F04003 bic r3, r3, #64 + 4716 00c8 1360 str r3, [r2] +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4717 .loc 1 2416 7 view .LVU1642 +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4718 .loc 1 2416 11 is_stmt 0 view .LVU1643 + 4719 00ca FFF7FEFF bl HAL_GetTick + 4720 .LVL289: + 4721 00ce 0090 str r0, [sp] + 4722 00d0 6423 movs r3, #100 + 4723 00d2 0022 movs r2, #0 + 4724 00d4 4FF4C061 mov r1, #1536 + 4725 00d8 2046 mov r0, r4 + 4726 00da FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 4727 .LVL290: +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 187 + + + 4728 .loc 1 2416 10 view .LVU1644 + 4729 00de 08B1 cbz r0, .L335 +2418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4730 .loc 1 2418 9 is_stmt 1 view .LVU1645 +2418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4731 .loc 1 2418 25 is_stmt 0 view .LVU1646 + 4732 00e0 4023 movs r3, #64 + 4733 00e2 2366 str r3, [r4, #96] + 4734 .L335: +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4735 .loc 1 2424 3 is_stmt 1 view .LVU1647 +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4736 .loc 1 2424 7 is_stmt 0 view .LVU1648 + 4737 00e4 2368 ldr r3, [r4] + 4738 00e6 5B68 ldr r3, [r3, #4] +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4739 .loc 1 2424 6 view .LVU1649 + 4740 00e8 13F0010F tst r3, #1 + 4741 00ec 2CD0 beq .L338 +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4742 .loc 1 2427 5 is_stmt 1 view .LVU1650 +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4743 .loc 1 2427 13 is_stmt 0 view .LVU1651 + 4744 00ee A36D ldr r3, [r4, #88] +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4745 .loc 1 2427 8 view .LVU1652 + 4746 00f0 53B3 cbz r3, .L338 +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4747 .loc 1 2431 7 is_stmt 1 view .LVU1653 +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4748 .loc 1 2431 39 is_stmt 0 view .LVU1654 + 4749 00f2 0022 movs r2, #0 + 4750 00f4 5A63 str r2, [r3, #52] +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4751 .loc 1 2434 7 is_stmt 1 view .LVU1655 +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4752 .loc 1 2434 11 is_stmt 0 view .LVU1656 + 4753 00f6 A06D ldr r0, [r4, #88] + 4754 00f8 FFF7FEFF bl HAL_DMA_Abort + 4755 .LVL291: +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4756 .loc 1 2434 10 view .LVU1657 + 4757 00fc 08B1 cbz r0, .L339 +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4758 .loc 1 2436 9 is_stmt 1 view .LVU1658 +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4759 .loc 1 2436 25 is_stmt 0 view .LVU1659 + 4760 00fe 4023 movs r3, #64 + 4761 0100 2366 str r3, [r4, #96] + 4762 .L339: +2440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4763 .loc 1 2440 7 is_stmt 1 view .LVU1660 + 4764 0102 2268 ldr r2, [r4] + 4765 0104 1368 ldr r3, [r2] + 4766 0106 23F04003 bic r3, r3, #64 + 4767 010a 1360 str r3, [r2] +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 188 + + + 4768 .loc 1 2443 7 view .LVU1661 +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4769 .loc 1 2443 11 is_stmt 0 view .LVU1662 + 4770 010c FFF7FEFF bl HAL_GetTick + 4771 .LVL292: + 4772 0110 0090 str r0, [sp] + 4773 0112 6423 movs r3, #100 + 4774 0114 0022 movs r2, #0 + 4775 0116 8021 movs r1, #128 + 4776 0118 2046 mov r0, r4 + 4777 011a FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 4778 .LVL293: +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4779 .loc 1 2443 10 view .LVU1663 + 4780 011e 08B1 cbz r0, .L340 +2445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4781 .loc 1 2445 9 is_stmt 1 view .LVU1664 +2445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4782 .loc 1 2445 25 is_stmt 0 view .LVU1665 + 4783 0120 4023 movs r3, #64 + 4784 0122 2366 str r3, [r4, #96] + 4785 .L340: +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4786 .loc 1 2449 7 is_stmt 1 view .LVU1666 +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4787 .loc 1 2449 11 is_stmt 0 view .LVU1667 + 4788 0124 FFF7FEFF bl HAL_GetTick + 4789 .LVL294: + 4790 0128 0090 str r0, [sp] + 4791 012a 6423 movs r3, #100 + 4792 012c 0022 movs r2, #0 + 4793 012e 4FF4C061 mov r1, #1536 + 4794 0132 2046 mov r0, r4 + 4795 0134 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 4796 .LVL295: +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4797 .loc 1 2449 10 view .LVU1668 + 4798 0138 08B1 cbz r0, .L341 +2451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4799 .loc 1 2451 9 is_stmt 1 view .LVU1669 +2451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4800 .loc 1 2451 25 is_stmt 0 view .LVU1670 + 4801 013a 4023 movs r3, #64 + 4802 013c 2366 str r3, [r4, #96] + 4803 .L341: +2455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4804 .loc 1 2455 7 is_stmt 1 view .LVU1671 + 4805 013e 2268 ldr r2, [r4] + 4806 0140 5368 ldr r3, [r2, #4] + 4807 0142 23F00103 bic r3, r3, #1 + 4808 0146 5360 str r3, [r2, #4] + 4809 .L338: +2459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 4810 .loc 1 2459 3 view .LVU1672 +2459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 4811 .loc 1 2459 21 is_stmt 0 view .LVU1673 + 4812 0148 0023 movs r3, #0 + ARM GAS /tmp/ccywxtmH.s page 189 + + + 4813 014a A4F84630 strh r3, [r4, #70] @ movhi +2460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4814 .loc 1 2460 3 is_stmt 1 view .LVU1674 +2460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4815 .loc 1 2460 21 is_stmt 0 view .LVU1675 + 4816 014e E387 strh r3, [r4, #62] @ movhi +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4817 .loc 1 2463 3 is_stmt 1 view .LVU1676 +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4818 .loc 1 2463 11 is_stmt 0 view .LVU1677 + 4819 0150 236E ldr r3, [r4, #96] +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4820 .loc 1 2463 6 view .LVU1678 + 4821 0152 402B cmp r3, #64 + 4822 0154 12D0 beq .L343 +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4823 .loc 1 2471 5 is_stmt 1 view .LVU1679 +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4824 .loc 1 2471 21 is_stmt 0 view .LVU1680 + 4825 0156 0020 movs r0, #0 + 4826 0158 2066 str r0, [r4, #96] + 4827 .L342: + 4828 .LVL296: +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4829 .loc 1 2475 3 is_stmt 1 view .LVU1681 + 4830 .LBB3: +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4831 .loc 1 2475 3 view .LVU1682 + 4832 015a 0022 movs r2, #0 + 4833 015c 0292 str r2, [sp, #8] +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4834 .loc 1 2475 3 view .LVU1683 + 4835 015e 2368 ldr r3, [r4] + 4836 0160 D968 ldr r1, [r3, #12] + 4837 0162 0291 str r1, [sp, #8] +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4838 .loc 1 2475 3 view .LVU1684 + 4839 0164 9968 ldr r1, [r3, #8] + 4840 0166 0291 str r1, [sp, #8] +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4841 .loc 1 2475 3 view .LVU1685 + 4842 0168 0299 ldr r1, [sp, #8] + 4843 .LBE3: +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4844 .loc 1 2475 3 view .LVU1686 +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4845 .loc 1 2476 3 view .LVU1687 + 4846 .LBB4: +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4847 .loc 1 2476 3 view .LVU1688 + 4848 016a 0392 str r2, [sp, #12] +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4849 .loc 1 2476 3 view .LVU1689 + 4850 016c 9B68 ldr r3, [r3, #8] + 4851 016e 0393 str r3, [sp, #12] +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4852 .loc 1 2476 3 view .LVU1690 + ARM GAS /tmp/ccywxtmH.s page 190 + + + 4853 0170 039B ldr r3, [sp, #12] + 4854 .LBE4: +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4855 .loc 1 2476 3 view .LVU1691 +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4856 .loc 1 2479 3 view .LVU1692 +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4857 .loc 1 2479 15 is_stmt 0 view .LVU1693 + 4858 0172 0123 movs r3, #1 + 4859 0174 84F85D30 strb r3, [r4, #93] +2481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4860 .loc 1 2481 3 is_stmt 1 view .LVU1694 +2482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4861 .loc 1 2482 1 is_stmt 0 view .LVU1695 + 4862 0178 06B0 add sp, sp, #24 + 4863 .cfi_remember_state + 4864 .cfi_def_cfa_offset 8 + 4865 @ sp needed + 4866 017a 10BD pop {r4, pc} + 4867 .LVL297: + 4868 .L343: + 4869 .cfi_restore_state +2466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4870 .loc 1 2466 15 view .LVU1696 + 4871 017c 0120 movs r0, #1 + 4872 017e ECE7 b .L342 + 4873 .L348: + 4874 .align 2 + 4875 .L347: + 4876 0180 00000000 .word SystemCoreClock + 4877 0184 F1197605 .word 91625969 + 4878 0188 00000000 .word SPI_AbortTx_ISR + 4879 018c 00000000 .word SPI_AbortRx_ISR + 4880 .cfi_endproc + 4881 .LFE143: + 4883 .section .text.HAL_SPI_DMAPause,"ax",%progbits + 4884 .align 1 + 4885 .global HAL_SPI_DMAPause + 4886 .syntax unified + 4887 .thumb + 4888 .thumb_func + 4890 HAL_SPI_DMAPause: + 4891 .LVL298: + 4892 .LFB145: +2661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ + 4893 .loc 1 2661 1 is_stmt 1 view -0 + 4894 .cfi_startproc + 4895 @ args = 0, pretend = 0, frame = 0 + 4896 @ frame_needed = 0, uses_anonymous_args = 0 + 4897 @ link register save eliminated. +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4898 .loc 1 2663 3 view .LVU1698 +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4899 .loc 1 2663 3 view .LVU1699 + 4900 0000 90F85C30 ldrb r3, [r0, #92] @ zero_extendqisi2 + 4901 0004 012B cmp r3, #1 + 4902 0006 0CD0 beq .L351 + ARM GAS /tmp/ccywxtmH.s page 191 + + +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4903 .loc 1 2663 3 discriminator 2 view .LVU1700 + 4904 0008 0123 movs r3, #1 + 4905 000a 80F85C30 strb r3, [r0, #92] +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4906 .loc 1 2663 3 discriminator 2 view .LVU1701 +2666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4907 .loc 1 2666 3 discriminator 2 view .LVU1702 + 4908 000e 0268 ldr r2, [r0] + 4909 0010 5368 ldr r3, [r2, #4] + 4910 0012 23F00303 bic r3, r3, #3 + 4911 0016 5360 str r3, [r2, #4] +2669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4912 .loc 1 2669 3 discriminator 2 view .LVU1703 +2669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4913 .loc 1 2669 3 discriminator 2 view .LVU1704 + 4914 0018 0023 movs r3, #0 + 4915 001a 80F85C30 strb r3, [r0, #92] +2669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4916 .loc 1 2669 3 discriminator 2 view .LVU1705 +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4917 .loc 1 2671 3 discriminator 2 view .LVU1706 +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4918 .loc 1 2671 10 is_stmt 0 discriminator 2 view .LVU1707 + 4919 001e 1846 mov r0, r3 + 4920 .LVL299: +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4921 .loc 1 2671 10 discriminator 2 view .LVU1708 + 4922 0020 7047 bx lr + 4923 .LVL300: + 4924 .L351: +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4925 .loc 1 2663 3 view .LVU1709 + 4926 0022 0220 movs r0, #2 + 4927 .LVL301: +2672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4928 .loc 1 2672 1 view .LVU1710 + 4929 0024 7047 bx lr + 4930 .cfi_endproc + 4931 .LFE145: + 4933 .section .text.HAL_SPI_DMAResume,"ax",%progbits + 4934 .align 1 + 4935 .global HAL_SPI_DMAResume + 4936 .syntax unified + 4937 .thumb + 4938 .thumb_func + 4940 HAL_SPI_DMAResume: + 4941 .LVL302: + 4942 .LFB146: +2681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ + 4943 .loc 1 2681 1 is_stmt 1 view -0 + 4944 .cfi_startproc + 4945 @ args = 0, pretend = 0, frame = 0 + 4946 @ frame_needed = 0, uses_anonymous_args = 0 + 4947 @ link register save eliminated. +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4948 .loc 1 2683 3 view .LVU1712 + ARM GAS /tmp/ccywxtmH.s page 192 + + +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4949 .loc 1 2683 3 view .LVU1713 + 4950 0000 90F85C30 ldrb r3, [r0, #92] @ zero_extendqisi2 + 4951 0004 012B cmp r3, #1 + 4952 0006 0CD0 beq .L354 +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4953 .loc 1 2683 3 discriminator 2 view .LVU1714 + 4954 0008 0123 movs r3, #1 + 4955 000a 80F85C30 strb r3, [r0, #92] +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4956 .loc 1 2683 3 discriminator 2 view .LVU1715 +2686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4957 .loc 1 2686 3 discriminator 2 view .LVU1716 + 4958 000e 0268 ldr r2, [r0] + 4959 0010 5368 ldr r3, [r2, #4] + 4960 0012 43F00303 orr r3, r3, #3 + 4961 0016 5360 str r3, [r2, #4] +2689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4962 .loc 1 2689 3 discriminator 2 view .LVU1717 +2689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4963 .loc 1 2689 3 discriminator 2 view .LVU1718 + 4964 0018 0023 movs r3, #0 + 4965 001a 80F85C30 strb r3, [r0, #92] +2689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4966 .loc 1 2689 3 discriminator 2 view .LVU1719 +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4967 .loc 1 2691 3 discriminator 2 view .LVU1720 +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4968 .loc 1 2691 10 is_stmt 0 discriminator 2 view .LVU1721 + 4969 001e 1846 mov r0, r3 + 4970 .LVL303: +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4971 .loc 1 2691 10 discriminator 2 view .LVU1722 + 4972 0020 7047 bx lr + 4973 .LVL304: + 4974 .L354: +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4975 .loc 1 2683 3 view .LVU1723 + 4976 0022 0220 movs r0, #2 + 4977 .LVL305: +2692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 4978 .loc 1 2692 1 view .LVU1724 + 4979 0024 7047 bx lr + 4980 .cfi_endproc + 4981 .LFE146: + 4983 .section .text.HAL_SPI_DMAStop,"ax",%progbits + 4984 .align 1 + 4985 .global HAL_SPI_DMAStop + 4986 .syntax unified + 4987 .thumb + 4988 .thumb_func + 4990 HAL_SPI_DMAStop: + 4991 .LVL306: + 4992 .LFB147: +2701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 4993 .loc 1 2701 1 is_stmt 1 view -0 + 4994 .cfi_startproc + ARM GAS /tmp/ccywxtmH.s page 193 + + + 4995 @ args = 0, pretend = 0, frame = 0 + 4996 @ frame_needed = 0, uses_anonymous_args = 0 +2701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 4997 .loc 1 2701 1 is_stmt 0 view .LVU1726 + 4998 0000 38B5 push {r3, r4, r5, lr} + 4999 .cfi_def_cfa_offset 16 + 5000 .cfi_offset 3, -16 + 5001 .cfi_offset 4, -12 + 5002 .cfi_offset 5, -8 + 5003 .cfi_offset 14, -4 + 5004 0002 0446 mov r4, r0 +2702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* The Lock is not implemented on this API to allow the user application + 5005 .loc 1 2702 3 is_stmt 1 view .LVU1727 + 5006 .LVL307: +2710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5007 .loc 1 2710 3 view .LVU1728 +2710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5008 .loc 1 2710 11 is_stmt 0 view .LVU1729 + 5009 0004 406D ldr r0, [r0, #84] + 5010 .LVL308: +2710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5011 .loc 1 2710 6 view .LVU1730 + 5012 0006 48B1 cbz r0, .L358 +2712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5013 .loc 1 2712 5 is_stmt 1 view .LVU1731 +2712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5014 .loc 1 2712 19 is_stmt 0 view .LVU1732 + 5015 0008 FFF7FEFF bl HAL_DMA_Abort + 5016 .LVL309: +2712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5017 .loc 1 2712 8 view .LVU1733 + 5018 000c 0546 mov r5, r0 + 5019 000e 30B1 cbz r0, .L356 +2714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 5020 .loc 1 2714 7 is_stmt 1 view .LVU1734 + 5021 0010 236E ldr r3, [r4, #96] + 5022 0012 43F01003 orr r3, r3, #16 + 5023 0016 2366 str r3, [r4, #96] +2715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5024 .loc 1 2715 7 view .LVU1735 + 5025 .LVL310: +2715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5026 .loc 1 2715 17 is_stmt 0 view .LVU1736 + 5027 0018 0125 movs r5, #1 + 5028 001a 00E0 b .L356 + 5029 .LVL311: + 5030 .L358: +2702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* The Lock is not implemented on this API to allow the user application + 5031 .loc 1 2702 21 view .LVU1737 + 5032 001c 0025 movs r5, #0 + 5033 .LVL312: + 5034 .L356: +2719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5035 .loc 1 2719 3 is_stmt 1 view .LVU1738 +2719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5036 .loc 1 2719 11 is_stmt 0 view .LVU1739 + 5037 001e A06D ldr r0, [r4, #88] + ARM GAS /tmp/ccywxtmH.s page 194 + + +2719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5038 .loc 1 2719 6 view .LVU1740 + 5039 0020 38B1 cbz r0, .L357 +2721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5040 .loc 1 2721 5 is_stmt 1 view .LVU1741 +2721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5041 .loc 1 2721 19 is_stmt 0 view .LVU1742 + 5042 0022 FFF7FEFF bl HAL_DMA_Abort + 5043 .LVL313: +2721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5044 .loc 1 2721 8 view .LVU1743 + 5045 0026 20B1 cbz r0, .L357 +2723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 5046 .loc 1 2723 7 is_stmt 1 view .LVU1744 + 5047 0028 236E ldr r3, [r4, #96] + 5048 002a 43F01003 orr r3, r3, #16 + 5049 002e 2366 str r3, [r4, #96] +2724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5050 .loc 1 2724 7 view .LVU1745 + 5051 .LVL314: +2724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5052 .loc 1 2724 17 is_stmt 0 view .LVU1746 + 5053 0030 0125 movs r5, #1 + 5054 .LVL315: + 5055 .L357: +2729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 5056 .loc 1 2729 3 is_stmt 1 view .LVU1747 + 5057 0032 2268 ldr r2, [r4] + 5058 0034 5368 ldr r3, [r2, #4] + 5059 0036 23F00303 bic r3, r3, #3 + 5060 003a 5360 str r3, [r2, #4] +2730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 5061 .loc 1 2730 3 view .LVU1748 +2730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 5062 .loc 1 2730 15 is_stmt 0 view .LVU1749 + 5063 003c 0123 movs r3, #1 + 5064 003e 84F85D30 strb r3, [r4, #93] +2731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5065 .loc 1 2731 3 is_stmt 1 view .LVU1750 +2732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5066 .loc 1 2732 1 is_stmt 0 view .LVU1751 + 5067 0042 2846 mov r0, r5 + 5068 0044 38BD pop {r3, r4, r5, pc} +2732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5069 .loc 1 2732 1 view .LVU1752 + 5070 .cfi_endproc + 5071 .LFE147: + 5073 .section .text.HAL_SPI_TxCpltCallback,"ax",%progbits + 5074 .align 1 + 5075 .weak HAL_SPI_TxCpltCallback + 5076 .syntax unified + 5077 .thumb + 5078 .thumb_func + 5080 HAL_SPI_TxCpltCallback: + 5081 .LVL316: + 5082 .LFB149: +2848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/ccywxtmH.s page 195 + + + 5083 .loc 1 2848 1 is_stmt 1 view -0 + 5084 .cfi_startproc + 5085 @ args = 0, pretend = 0, frame = 0 + 5086 @ frame_needed = 0, uses_anonymous_args = 0 + 5087 @ link register save eliminated. +2850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5088 .loc 1 2850 3 view .LVU1754 +2855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5089 .loc 1 2855 1 is_stmt 0 view .LVU1755 + 5090 0000 7047 bx lr + 5091 .cfi_endproc + 5092 .LFE149: + 5094 .section .text.HAL_SPI_RxCpltCallback,"ax",%progbits + 5095 .align 1 + 5096 .weak HAL_SPI_RxCpltCallback + 5097 .syntax unified + 5098 .thumb + 5099 .thumb_func + 5101 HAL_SPI_RxCpltCallback: + 5102 .LVL317: + 5103 .LFB150: +2864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 5104 .loc 1 2864 1 is_stmt 1 view -0 + 5105 .cfi_startproc + 5106 @ args = 0, pretend = 0, frame = 0 + 5107 @ frame_needed = 0, uses_anonymous_args = 0 + 5108 @ link register save eliminated. +2866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5109 .loc 1 2866 3 view .LVU1757 +2871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5110 .loc 1 2871 1 is_stmt 0 view .LVU1758 + 5111 0000 7047 bx lr + 5112 .cfi_endproc + 5113 .LFE150: + 5115 .section .text.HAL_SPI_TxRxCpltCallback,"ax",%progbits + 5116 .align 1 + 5117 .weak HAL_SPI_TxRxCpltCallback + 5118 .syntax unified + 5119 .thumb + 5120 .thumb_func + 5122 HAL_SPI_TxRxCpltCallback: + 5123 .LVL318: + 5124 .LFB151: +2880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 5125 .loc 1 2880 1 is_stmt 1 view -0 + 5126 .cfi_startproc + 5127 @ args = 0, pretend = 0, frame = 0 + 5128 @ frame_needed = 0, uses_anonymous_args = 0 + 5129 @ link register save eliminated. +2882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5130 .loc 1 2882 3 view .LVU1760 +2887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5131 .loc 1 2887 1 is_stmt 0 view .LVU1761 + 5132 0000 7047 bx lr + 5133 .cfi_endproc + 5134 .LFE151: + 5136 .section .text.HAL_SPI_TxHalfCpltCallback,"ax",%progbits + ARM GAS /tmp/ccywxtmH.s page 196 + + + 5137 .align 1 + 5138 .weak HAL_SPI_TxHalfCpltCallback + 5139 .syntax unified + 5140 .thumb + 5141 .thumb_func + 5143 HAL_SPI_TxHalfCpltCallback: + 5144 .LVL319: + 5145 .LFB152: +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 5146 .loc 1 2896 1 is_stmt 1 view -0 + 5147 .cfi_startproc + 5148 @ args = 0, pretend = 0, frame = 0 + 5149 @ frame_needed = 0, uses_anonymous_args = 0 + 5150 @ link register save eliminated. +2898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5151 .loc 1 2898 3 view .LVU1763 +2903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5152 .loc 1 2903 1 is_stmt 0 view .LVU1764 + 5153 0000 7047 bx lr + 5154 .cfi_endproc + 5155 .LFE152: + 5157 .section .text.SPI_DMAHalfTransmitCplt,"ax",%progbits + 5158 .align 1 + 5159 .syntax unified + 5160 .thumb + 5161 .thumb_func + 5163 SPI_DMAHalfTransmitCplt: + 5164 .LVL320: + 5165 .LFB162: +3308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5166 .loc 1 3308 1 is_stmt 1 view -0 + 5167 .cfi_startproc + 5168 @ args = 0, pretend = 0, frame = 0 + 5169 @ frame_needed = 0, uses_anonymous_args = 0 +3308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5170 .loc 1 3308 1 is_stmt 0 view .LVU1766 + 5171 0000 08B5 push {r3, lr} + 5172 .cfi_def_cfa_offset 8 + 5173 .cfi_offset 3, -8 + 5174 .cfi_offset 14, -4 +3309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5175 .loc 1 3309 3 is_stmt 1 view .LVU1767 + 5176 .LVL321: +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5177 .loc 1 3315 3 view .LVU1768 + 5178 0002 406A ldr r0, [r0, #36] + 5179 .LVL322: +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5180 .loc 1 3315 3 is_stmt 0 view .LVU1769 + 5181 0004 FFF7FEFF bl HAL_SPI_TxHalfCpltCallback + 5182 .LVL323: +3317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5183 .loc 1 3317 1 view .LVU1770 + 5184 0008 08BD pop {r3, pc} + 5185 .cfi_endproc + 5186 .LFE162: + 5188 .section .text.HAL_SPI_RxHalfCpltCallback,"ax",%progbits + ARM GAS /tmp/ccywxtmH.s page 197 + + + 5189 .align 1 + 5190 .weak HAL_SPI_RxHalfCpltCallback + 5191 .syntax unified + 5192 .thumb + 5193 .thumb_func + 5195 HAL_SPI_RxHalfCpltCallback: + 5196 .LVL324: + 5197 .LFB153: +2912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 5198 .loc 1 2912 1 is_stmt 1 view -0 + 5199 .cfi_startproc + 5200 @ args = 0, pretend = 0, frame = 0 + 5201 @ frame_needed = 0, uses_anonymous_args = 0 + 5202 @ link register save eliminated. +2914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5203 .loc 1 2914 3 view .LVU1772 +2919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5204 .loc 1 2919 1 is_stmt 0 view .LVU1773 + 5205 0000 7047 bx lr + 5206 .cfi_endproc + 5207 .LFE153: + 5209 .section .text.SPI_DMAHalfReceiveCplt,"ax",%progbits + 5210 .align 1 + 5211 .syntax unified + 5212 .thumb + 5213 .thumb_func + 5215 SPI_DMAHalfReceiveCplt: + 5216 .LVL325: + 5217 .LFB163: +3326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5218 .loc 1 3326 1 is_stmt 1 view -0 + 5219 .cfi_startproc + 5220 @ args = 0, pretend = 0, frame = 0 + 5221 @ frame_needed = 0, uses_anonymous_args = 0 +3326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5222 .loc 1 3326 1 is_stmt 0 view .LVU1775 + 5223 0000 08B5 push {r3, lr} + 5224 .cfi_def_cfa_offset 8 + 5225 .cfi_offset 3, -8 + 5226 .cfi_offset 14, -4 +3327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5227 .loc 1 3327 3 is_stmt 1 view .LVU1776 + 5228 .LVL326: +3333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5229 .loc 1 3333 3 view .LVU1777 + 5230 0002 406A ldr r0, [r0, #36] + 5231 .LVL327: +3333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5232 .loc 1 3333 3 is_stmt 0 view .LVU1778 + 5233 0004 FFF7FEFF bl HAL_SPI_RxHalfCpltCallback + 5234 .LVL328: +3335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5235 .loc 1 3335 1 view .LVU1779 + 5236 0008 08BD pop {r3, pc} + 5237 .cfi_endproc + 5238 .LFE163: + 5240 .section .text.HAL_SPI_TxRxHalfCpltCallback,"ax",%progbits + ARM GAS /tmp/ccywxtmH.s page 198 + + + 5241 .align 1 + 5242 .weak HAL_SPI_TxRxHalfCpltCallback + 5243 .syntax unified + 5244 .thumb + 5245 .thumb_func + 5247 HAL_SPI_TxRxHalfCpltCallback: + 5248 .LVL329: + 5249 .LFB154: +2928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 5250 .loc 1 2928 1 is_stmt 1 view -0 + 5251 .cfi_startproc + 5252 @ args = 0, pretend = 0, frame = 0 + 5253 @ frame_needed = 0, uses_anonymous_args = 0 + 5254 @ link register save eliminated. +2930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5255 .loc 1 2930 3 view .LVU1781 +2935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5256 .loc 1 2935 1 is_stmt 0 view .LVU1782 + 5257 0000 7047 bx lr + 5258 .cfi_endproc + 5259 .LFE154: + 5261 .section .text.SPI_DMAHalfTransmitReceiveCplt,"ax",%progbits + 5262 .align 1 + 5263 .syntax unified + 5264 .thumb + 5265 .thumb_func + 5267 SPI_DMAHalfTransmitReceiveCplt: + 5268 .LVL330: + 5269 .LFB164: +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5270 .loc 1 3344 1 is_stmt 1 view -0 + 5271 .cfi_startproc + 5272 @ args = 0, pretend = 0, frame = 0 + 5273 @ frame_needed = 0, uses_anonymous_args = 0 +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5274 .loc 1 3344 1 is_stmt 0 view .LVU1784 + 5275 0000 08B5 push {r3, lr} + 5276 .cfi_def_cfa_offset 8 + 5277 .cfi_offset 3, -8 + 5278 .cfi_offset 14, -4 +3345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5279 .loc 1 3345 3 is_stmt 1 view .LVU1785 + 5280 .LVL331: +3351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5281 .loc 1 3351 3 view .LVU1786 + 5282 0002 406A ldr r0, [r0, #36] + 5283 .LVL332: +3351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5284 .loc 1 3351 3 is_stmt 0 view .LVU1787 + 5285 0004 FFF7FEFF bl HAL_SPI_TxRxHalfCpltCallback + 5286 .LVL333: +3353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5287 .loc 1 3353 1 view .LVU1788 + 5288 0008 08BD pop {r3, pc} + 5289 .cfi_endproc + 5290 .LFE164: + 5292 .section .text.HAL_SPI_ErrorCallback,"ax",%progbits + ARM GAS /tmp/ccywxtmH.s page 199 + + + 5293 .align 1 + 5294 .weak HAL_SPI_ErrorCallback + 5295 .syntax unified + 5296 .thumb + 5297 .thumb_func + 5299 HAL_SPI_ErrorCallback: + 5300 .LVL334: + 5301 .LFB155: +2944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 5302 .loc 1 2944 1 is_stmt 1 view -0 + 5303 .cfi_startproc + 5304 @ args = 0, pretend = 0, frame = 0 + 5305 @ frame_needed = 0, uses_anonymous_args = 0 + 5306 @ link register save eliminated. +2946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5307 .loc 1 2946 3 view .LVU1790 +2954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5308 .loc 1 2954 1 is_stmt 0 view .LVU1791 + 5309 0000 7047 bx lr + 5310 .cfi_endproc + 5311 .LFE155: + 5313 .section .text.SPI_CloseTx_ISR,"ax",%progbits + 5314 .align 1 + 5315 .syntax unified + 5316 .thumb + 5317 .thumb_func + 5319 SPI_CloseTx_ISR: + 5320 .LVL335: + 5321 .LFB183: +4286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 5322 .loc 1 4286 1 is_stmt 1 view -0 + 5323 .cfi_startproc + 5324 @ args = 0, pretend = 0, frame = 8 + 5325 @ frame_needed = 0, uses_anonymous_args = 0 +4286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 5326 .loc 1 4286 1 is_stmt 0 view .LVU1793 + 5327 0000 10B5 push {r4, lr} + 5328 .cfi_def_cfa_offset 8 + 5329 .cfi_offset 4, -8 + 5330 .cfi_offset 14, -4 + 5331 0002 82B0 sub sp, sp, #8 + 5332 .cfi_def_cfa_offset 16 + 5333 0004 0446 mov r4, r0 +4287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5334 .loc 1 4287 3 is_stmt 1 view .LVU1794 +4290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5335 .loc 1 4290 3 view .LVU1795 +4290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5336 .loc 1 4290 15 is_stmt 0 view .LVU1796 + 5337 0006 FFF7FEFF bl HAL_GetTick + 5338 .LVL336: +4290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5339 .loc 1 4290 15 view .LVU1797 + 5340 000a 0246 mov r2, r0 + 5341 .LVL337: +4293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5342 .loc 1 4293 3 is_stmt 1 view .LVU1798 + ARM GAS /tmp/ccywxtmH.s page 200 + + + 5343 000c 2168 ldr r1, [r4] + 5344 000e 4B68 ldr r3, [r1, #4] + 5345 0010 23F0A003 bic r3, r3, #160 + 5346 0014 4B60 str r3, [r1, #4] +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5347 .loc 1 4296 3 view .LVU1799 +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5348 .loc 1 4296 7 is_stmt 0 view .LVU1800 + 5349 0016 6421 movs r1, #100 + 5350 0018 2046 mov r0, r4 + 5351 .LVL338: +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5352 .loc 1 4296 7 view .LVU1801 + 5353 001a FFF7FEFF bl SPI_EndRxTxTransaction + 5354 .LVL339: +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5355 .loc 1 4296 6 view .LVU1802 + 5356 001e 18B1 cbz r0, .L374 +4298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5357 .loc 1 4298 5 is_stmt 1 view .LVU1803 + 5358 0020 236E ldr r3, [r4, #96] + 5359 0022 43F02003 orr r3, r3, #32 + 5360 0026 2366 str r3, [r4, #96] + 5361 .L374: +4302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5362 .loc 1 4302 3 view .LVU1804 +4302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5363 .loc 1 4302 17 is_stmt 0 view .LVU1805 + 5364 0028 A368 ldr r3, [r4, #8] +4302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5365 .loc 1 4302 6 view .LVU1806 + 5366 002a 33B9 cbnz r3, .L375 +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5367 .loc 1 4304 5 is_stmt 1 view .LVU1807 + 5368 .LBB5: +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5369 .loc 1 4304 5 view .LVU1808 + 5370 002c 0193 str r3, [sp, #4] +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5371 .loc 1 4304 5 view .LVU1809 + 5372 002e 2368 ldr r3, [r4] + 5373 0030 DA68 ldr r2, [r3, #12] + 5374 0032 0192 str r2, [sp, #4] +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5375 .loc 1 4304 5 view .LVU1810 + 5376 0034 9B68 ldr r3, [r3, #8] + 5377 0036 0193 str r3, [sp, #4] +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5378 .loc 1 4304 5 view .LVU1811 + 5379 0038 019B ldr r3, [sp, #4] + 5380 .L375: + 5381 .LBE5: +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5382 .loc 1 4304 5 discriminator 1 view .LVU1812 +4307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 5383 .loc 1 4307 3 discriminator 1 view .LVU1813 +4307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + ARM GAS /tmp/ccywxtmH.s page 201 + + + 5384 .loc 1 4307 15 is_stmt 0 discriminator 1 view .LVU1814 + 5385 003a 0123 movs r3, #1 + 5386 003c 84F85D30 strb r3, [r4, #93] +4308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5387 .loc 1 4308 3 is_stmt 1 discriminator 1 view .LVU1815 +4308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5388 .loc 1 4308 11 is_stmt 0 discriminator 1 view .LVU1816 + 5389 0040 236E ldr r3, [r4, #96] +4308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5390 .loc 1 4308 6 discriminator 1 view .LVU1817 + 5391 0042 23B1 cbz r3, .L376 +4314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5392 .loc 1 4314 5 is_stmt 1 view .LVU1818 + 5393 0044 2046 mov r0, r4 + 5394 0046 FFF7FEFF bl HAL_SPI_ErrorCallback + 5395 .LVL340: + 5396 .L373: +4326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5397 .loc 1 4326 1 is_stmt 0 view .LVU1819 + 5398 004a 02B0 add sp, sp, #8 + 5399 .cfi_remember_state + 5400 .cfi_def_cfa_offset 8 + 5401 @ sp needed + 5402 004c 10BD pop {r4, pc} + 5403 .LVL341: + 5404 .L376: + 5405 .cfi_restore_state +4323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5406 .loc 1 4323 5 is_stmt 1 view .LVU1820 + 5407 004e 2046 mov r0, r4 + 5408 0050 FFF7FEFF bl HAL_SPI_TxCpltCallback + 5409 .LVL342: +4326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5410 .loc 1 4326 1 is_stmt 0 view .LVU1821 + 5411 0054 F9E7 b .L373 + 5412 .cfi_endproc + 5413 .LFE183: + 5415 .section .text.SPI_TxISR_8BIT,"ax",%progbits + 5416 .align 1 + 5417 .syntax unified + 5418 .thumb + 5419 .thumb_func + 5421 SPI_TxISR_8BIT: + 5422 .LVL343: + 5423 .LFB175: +3880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 5424 .loc 1 3880 1 is_stmt 1 view -0 + 5425 .cfi_startproc + 5426 @ args = 0, pretend = 0, frame = 0 + 5427 @ frame_needed = 0, uses_anonymous_args = 0 +3880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 5428 .loc 1 3880 1 is_stmt 0 view .LVU1823 + 5429 0000 08B5 push {r3, lr} + 5430 .cfi_def_cfa_offset 8 + 5431 .cfi_offset 3, -8 + 5432 .cfi_offset 14, -4 +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + ARM GAS /tmp/ccywxtmH.s page 202 + + + 5433 .loc 1 3881 3 is_stmt 1 view .LVU1824 +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5434 .loc 1 3881 48 is_stmt 0 view .LVU1825 + 5435 0002 826B ldr r2, [r0, #56] +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5436 .loc 1 3881 25 view .LVU1826 + 5437 0004 0368 ldr r3, [r0] +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5438 .loc 1 3881 43 view .LVU1827 + 5439 0006 1278 ldrb r2, [r2] @ zero_extendqisi2 +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5440 .loc 1 3881 40 view .LVU1828 + 5441 0008 1A73 strb r2, [r3, #12] +3882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5442 .loc 1 3882 3 is_stmt 1 view .LVU1829 +3882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5443 .loc 1 3882 7 is_stmt 0 view .LVU1830 + 5444 000a 836B ldr r3, [r0, #56] +3882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5445 .loc 1 3882 19 view .LVU1831 + 5446 000c 0133 adds r3, r3, #1 + 5447 000e 8363 str r3, [r0, #56] +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5448 .loc 1 3883 3 is_stmt 1 view .LVU1832 +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5449 .loc 1 3883 7 is_stmt 0 view .LVU1833 + 5450 0010 C38F ldrh r3, [r0, #62] + 5451 0012 9BB2 uxth r3, r3 +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5452 .loc 1 3883 20 view .LVU1834 + 5453 0014 013B subs r3, r3, #1 + 5454 0016 9BB2 uxth r3, r3 + 5455 0018 C387 strh r3, [r0, #62] @ movhi +3885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5456 .loc 1 3885 3 is_stmt 1 view .LVU1835 +3885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5457 .loc 1 3885 11 is_stmt 0 view .LVU1836 + 5458 001a C38F ldrh r3, [r0, #62] + 5459 001c 9BB2 uxth r3, r3 +3885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5460 .loc 1 3885 6 view .LVU1837 + 5461 001e 03B1 cbz r3, .L382 + 5462 .LVL344: + 5463 .L379: +3896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5464 .loc 1 3896 1 view .LVU1838 + 5465 0020 08BD pop {r3, pc} + 5466 .LVL345: + 5467 .L382: +3894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5468 .loc 1 3894 5 is_stmt 1 view .LVU1839 + 5469 0022 FFF7FEFF bl SPI_CloseTx_ISR + 5470 .LVL346: +3896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5471 .loc 1 3896 1 is_stmt 0 view .LVU1840 + 5472 0026 FBE7 b .L379 + 5473 .cfi_endproc + ARM GAS /tmp/ccywxtmH.s page 203 + + + 5474 .LFE175: + 5476 .section .text.SPI_TxISR_16BIT,"ax",%progbits + 5477 .align 1 + 5478 .syntax unified + 5479 .thumb + 5480 .thumb_func + 5482 SPI_TxISR_16BIT: + 5483 .LVL347: + 5484 .LFB176: +3905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 5485 .loc 1 3905 1 is_stmt 1 view -0 + 5486 .cfi_startproc + 5487 @ args = 0, pretend = 0, frame = 0 + 5488 @ frame_needed = 0, uses_anonymous_args = 0 +3905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 5489 .loc 1 3905 1 is_stmt 0 view .LVU1842 + 5490 0000 08B5 push {r3, lr} + 5491 .cfi_def_cfa_offset 8 + 5492 .cfi_offset 3, -8 + 5493 .cfi_offset 14, -4 +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5494 .loc 1 3907 3 is_stmt 1 view .LVU1843 +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5495 .loc 1 3907 42 is_stmt 0 view .LVU1844 + 5496 0002 826B ldr r2, [r0, #56] +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5497 .loc 1 3907 7 view .LVU1845 + 5498 0004 0368 ldr r3, [r0] +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5499 .loc 1 3907 24 view .LVU1846 + 5500 0006 1288 ldrh r2, [r2] +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5501 .loc 1 3907 22 view .LVU1847 + 5502 0008 DA60 str r2, [r3, #12] +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5503 .loc 1 3908 3 is_stmt 1 view .LVU1848 +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5504 .loc 1 3908 7 is_stmt 0 view .LVU1849 + 5505 000a 836B ldr r3, [r0, #56] +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5506 .loc 1 3908 20 view .LVU1850 + 5507 000c 0233 adds r3, r3, #2 + 5508 000e 8363 str r3, [r0, #56] +3909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5509 .loc 1 3909 3 is_stmt 1 view .LVU1851 +3909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5510 .loc 1 3909 7 is_stmt 0 view .LVU1852 + 5511 0010 C38F ldrh r3, [r0, #62] + 5512 0012 9BB2 uxth r3, r3 +3909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5513 .loc 1 3909 20 view .LVU1853 + 5514 0014 013B subs r3, r3, #1 + 5515 0016 9BB2 uxth r3, r3 + 5516 0018 C387 strh r3, [r0, #62] @ movhi +3911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5517 .loc 1 3911 3 is_stmt 1 view .LVU1854 +3911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 204 + + + 5518 .loc 1 3911 11 is_stmt 0 view .LVU1855 + 5519 001a C38F ldrh r3, [r0, #62] + 5520 001c 9BB2 uxth r3, r3 +3911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5521 .loc 1 3911 6 view .LVU1856 + 5522 001e 03B1 cbz r3, .L386 + 5523 .LVL348: + 5524 .L383: +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5525 .loc 1 3922 1 view .LVU1857 + 5526 0020 08BD pop {r3, pc} + 5527 .LVL349: + 5528 .L386: +3920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5529 .loc 1 3920 5 is_stmt 1 view .LVU1858 + 5530 0022 FFF7FEFF bl SPI_CloseTx_ISR + 5531 .LVL350: +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5532 .loc 1 3922 1 is_stmt 0 view .LVU1859 + 5533 0026 FBE7 b .L383 + 5534 .cfi_endproc + 5535 .LFE176: + 5537 .section .text.SPI_CloseRx_ISR,"ax",%progbits + 5538 .align 1 + 5539 .syntax unified + 5540 .thumb + 5541 .thumb_func + 5543 SPI_CloseRx_ISR: + 5544 .LVL351: + 5545 .LFB182: +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ + 5546 .loc 1 4229 1 is_stmt 1 view -0 + 5547 .cfi_startproc + 5548 @ args = 0, pretend = 0, frame = 0 + 5549 @ frame_needed = 0, uses_anonymous_args = 0 +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ + 5550 .loc 1 4229 1 is_stmt 0 view .LVU1861 + 5551 0000 10B5 push {r4, lr} + 5552 .cfi_def_cfa_offset 8 + 5553 .cfi_offset 4, -8 + 5554 .cfi_offset 14, -4 + 5555 0002 0446 mov r4, r0 +4231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5556 .loc 1 4231 3 is_stmt 1 view .LVU1862 + 5557 0004 0268 ldr r2, [r0] + 5558 0006 5368 ldr r3, [r2, #4] + 5559 0008 23F06003 bic r3, r3, #96 + 5560 000c 5360 str r3, [r2, #4] +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5561 .loc 1 4234 3 view .LVU1863 +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5562 .loc 1 4234 7 is_stmt 0 view .LVU1864 + 5563 000e FFF7FEFF bl HAL_GetTick + 5564 .LVL352: +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5565 .loc 1 4234 7 view .LVU1865 + 5566 0012 0246 mov r2, r0 + ARM GAS /tmp/ccywxtmH.s page 205 + + + 5567 0014 6421 movs r1, #100 + 5568 0016 2046 mov r0, r4 + 5569 0018 FFF7FEFF bl SPI_EndRxTransaction + 5570 .LVL353: +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5571 .loc 1 4234 6 view .LVU1866 + 5572 001c 18B1 cbz r0, .L388 +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5573 .loc 1 4236 5 is_stmt 1 view .LVU1867 + 5574 001e 236E ldr r3, [r4, #96] + 5575 0020 43F02003 orr r3, r3, #32 + 5576 0024 2366 str r3, [r4, #96] + 5577 .L388: +4238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5578 .loc 1 4238 3 view .LVU1868 +4238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5579 .loc 1 4238 15 is_stmt 0 view .LVU1869 + 5580 0026 0123 movs r3, #1 + 5581 0028 84F85D30 strb r3, [r4, #93] +4256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5582 .loc 1 4256 5 is_stmt 1 view .LVU1870 +4256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5583 .loc 1 4256 13 is_stmt 0 view .LVU1871 + 5584 002c 236E ldr r3, [r4, #96] +4256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5585 .loc 1 4256 8 view .LVU1872 + 5586 002e 1BB9 cbnz r3, .L389 +4262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5587 .loc 1 4262 7 is_stmt 1 view .LVU1873 + 5588 0030 2046 mov r0, r4 + 5589 0032 FFF7FEFF bl HAL_SPI_RxCpltCallback + 5590 .LVL354: + 5591 .L387: +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5592 .loc 1 4277 1 is_stmt 0 view .LVU1874 + 5593 0036 10BD pop {r4, pc} + 5594 .LVL355: + 5595 .L389: +4271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5596 .loc 1 4271 7 is_stmt 1 view .LVU1875 + 5597 0038 2046 mov r0, r4 + 5598 003a FFF7FEFF bl HAL_SPI_ErrorCallback + 5599 .LVL356: +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5600 .loc 1 4277 1 is_stmt 0 view .LVU1876 + 5601 003e FAE7 b .L387 + 5602 .cfi_endproc + 5603 .LFE182: + 5605 .section .text.SPI_RxISR_8BIT,"ax",%progbits + 5606 .align 1 + 5607 .syntax unified + 5608 .thumb + 5609 .thumb_func + 5611 SPI_RxISR_8BIT: + 5612 .LVL357: + 5613 .LFB173: +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + ARM GAS /tmp/ccywxtmH.s page 206 + + + 5614 .loc 1 3791 1 is_stmt 1 view -0 + 5615 .cfi_startproc + 5616 @ args = 0, pretend = 0, frame = 0 + 5617 @ frame_needed = 0, uses_anonymous_args = 0 +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + 5618 .loc 1 3791 1 is_stmt 0 view .LVU1878 + 5619 0000 08B5 push {r3, lr} + 5620 .cfi_def_cfa_offset 8 + 5621 .cfi_offset 3, -8 + 5622 .cfi_offset 14, -4 +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5623 .loc 1 3792 3 is_stmt 1 view .LVU1879 +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5624 .loc 1 3792 46 is_stmt 0 view .LVU1880 + 5625 0002 0268 ldr r2, [r0] +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5626 .loc 1 3792 8 view .LVU1881 + 5627 0004 036C ldr r3, [r0, #64] +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5628 .loc 1 3792 24 view .LVU1882 + 5629 0006 127B ldrb r2, [r2, #12] @ zero_extendqisi2 +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5630 .loc 1 3792 21 view .LVU1883 + 5631 0008 1A70 strb r2, [r3] +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 5632 .loc 1 3793 3 is_stmt 1 view .LVU1884 +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 5633 .loc 1 3793 7 is_stmt 0 view .LVU1885 + 5634 000a 036C ldr r3, [r0, #64] +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 5635 .loc 1 3793 19 view .LVU1886 + 5636 000c 0133 adds r3, r3, #1 + 5637 000e 0364 str r3, [r0, #64] +3794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5638 .loc 1 3794 3 is_stmt 1 view .LVU1887 +3794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5639 .loc 1 3794 7 is_stmt 0 view .LVU1888 + 5640 0010 B0F84630 ldrh r3, [r0, #70] + 5641 0014 9BB2 uxth r3, r3 +3794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5642 .loc 1 3794 20 view .LVU1889 + 5643 0016 013B subs r3, r3, #1 + 5644 0018 9BB2 uxth r3, r3 + 5645 001a A0F84630 strh r3, [r0, #70] @ movhi +3804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5646 .loc 1 3804 3 is_stmt 1 view .LVU1890 +3804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5647 .loc 1 3804 11 is_stmt 0 view .LVU1891 + 5648 001e B0F84630 ldrh r3, [r0, #70] + 5649 0022 9BB2 uxth r3, r3 +3804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5650 .loc 1 3804 6 view .LVU1892 + 5651 0024 03B1 cbz r3, .L395 + 5652 .LVL358: + 5653 .L392: +3815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5654 .loc 1 3815 1 view .LVU1893 + ARM GAS /tmp/ccywxtmH.s page 207 + + + 5655 0026 08BD pop {r3, pc} + 5656 .LVL359: + 5657 .L395: +3813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5658 .loc 1 3813 5 is_stmt 1 view .LVU1894 + 5659 0028 FFF7FEFF bl SPI_CloseRx_ISR + 5660 .LVL360: +3815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5661 .loc 1 3815 1 is_stmt 0 view .LVU1895 + 5662 002c FBE7 b .L392 + 5663 .cfi_endproc + 5664 .LFE173: + 5666 .section .text.SPI_RxISR_16BIT,"ax",%progbits + 5667 .align 1 + 5668 .syntax unified + 5669 .thumb + 5670 .thumb_func + 5672 SPI_RxISR_16BIT: + 5673 .LVL361: + 5674 .LFB174: +3847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + 5675 .loc 1 3847 1 is_stmt 1 view -0 + 5676 .cfi_startproc + 5677 @ args = 0, pretend = 0, frame = 0 + 5678 @ frame_needed = 0, uses_anonymous_args = 0 +3847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + 5679 .loc 1 3847 1 is_stmt 0 view .LVU1897 + 5680 0000 08B5 push {r3, lr} + 5681 .cfi_def_cfa_offset 8 + 5682 .cfi_offset 3, -8 + 5683 .cfi_offset 14, -4 +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5684 .loc 1 3848 3 is_stmt 1 view .LVU1898 +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5685 .loc 1 3848 52 is_stmt 0 view .LVU1899 + 5686 0002 0368 ldr r3, [r0] +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5687 .loc 1 3848 62 view .LVU1900 + 5688 0004 DA68 ldr r2, [r3, #12] +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5689 .loc 1 3848 21 view .LVU1901 + 5690 0006 036C ldr r3, [r0, #64] +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5691 .loc 1 3848 35 view .LVU1902 + 5692 0008 1A80 strh r2, [r3] @ movhi +3849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 5693 .loc 1 3849 3 is_stmt 1 view .LVU1903 +3849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 5694 .loc 1 3849 7 is_stmt 0 view .LVU1904 + 5695 000a 036C ldr r3, [r0, #64] +3849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 5696 .loc 1 3849 20 view .LVU1905 + 5697 000c 0233 adds r3, r3, #2 + 5698 000e 0364 str r3, [r0, #64] +3850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5699 .loc 1 3850 3 is_stmt 1 view .LVU1906 +3850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 208 + + + 5700 .loc 1 3850 7 is_stmt 0 view .LVU1907 + 5701 0010 B0F84630 ldrh r3, [r0, #70] + 5702 0014 9BB2 uxth r3, r3 +3850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5703 .loc 1 3850 20 view .LVU1908 + 5704 0016 013B subs r3, r3, #1 + 5705 0018 9BB2 uxth r3, r3 + 5706 001a A0F84630 strh r3, [r0, #70] @ movhi +3860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5707 .loc 1 3860 3 is_stmt 1 view .LVU1909 +3860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5708 .loc 1 3860 11 is_stmt 0 view .LVU1910 + 5709 001e B0F84630 ldrh r3, [r0, #70] + 5710 0022 9BB2 uxth r3, r3 +3860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5711 .loc 1 3860 6 view .LVU1911 + 5712 0024 03B1 cbz r3, .L399 + 5713 .LVL362: + 5714 .L396: +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5715 .loc 1 3871 1 view .LVU1912 + 5716 0026 08BD pop {r3, pc} + 5717 .LVL363: + 5718 .L399: +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5719 .loc 1 3869 5 is_stmt 1 view .LVU1913 + 5720 0028 FFF7FEFF bl SPI_CloseRx_ISR + 5721 .LVL364: +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5722 .loc 1 3871 1 is_stmt 0 view .LVU1914 + 5723 002c FBE7 b .L396 + 5724 .cfi_endproc + 5725 .LFE174: + 5727 .section .text.SPI_CloseRxTx_ISR,"ax",%progbits + 5728 .align 1 + 5729 .syntax unified + 5730 .thumb + 5731 .thumb_func + 5733 SPI_CloseRxTx_ISR: + 5734 .LVL365: + 5735 .LFB181: +4152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 5736 .loc 1 4152 1 is_stmt 1 view -0 + 5737 .cfi_startproc + 5738 @ args = 0, pretend = 0, frame = 0 + 5739 @ frame_needed = 0, uses_anonymous_args = 0 +4152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 5740 .loc 1 4152 1 is_stmt 0 view .LVU1916 + 5741 0000 10B5 push {r4, lr} + 5742 .cfi_def_cfa_offset 8 + 5743 .cfi_offset 4, -8 + 5744 .cfi_offset 14, -4 + 5745 0002 0446 mov r4, r0 +4153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5746 .loc 1 4153 3 is_stmt 1 view .LVU1917 +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5747 .loc 1 4156 3 view .LVU1918 + ARM GAS /tmp/ccywxtmH.s page 209 + + +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5748 .loc 1 4156 15 is_stmt 0 view .LVU1919 + 5749 0004 FFF7FEFF bl HAL_GetTick + 5750 .LVL366: +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5751 .loc 1 4156 15 view .LVU1920 + 5752 0008 0246 mov r2, r0 + 5753 .LVL367: +4159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5754 .loc 1 4159 3 is_stmt 1 view .LVU1921 + 5755 000a 2168 ldr r1, [r4] + 5756 000c 4B68 ldr r3, [r1, #4] + 5757 000e 23F02003 bic r3, r3, #32 + 5758 0012 4B60 str r3, [r1, #4] +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5759 .loc 1 4162 3 view .LVU1922 +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5760 .loc 1 4162 7 is_stmt 0 view .LVU1923 + 5761 0014 6421 movs r1, #100 + 5762 0016 2046 mov r0, r4 + 5763 .LVL368: +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5764 .loc 1 4162 7 view .LVU1924 + 5765 0018 FFF7FEFF bl SPI_EndRxTxTransaction + 5766 .LVL369: +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5767 .loc 1 4162 6 view .LVU1925 + 5768 001c 18B1 cbz r0, .L401 +4164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5769 .loc 1 4164 5 is_stmt 1 view .LVU1926 + 5770 001e 236E ldr r3, [r4, #96] + 5771 0020 43F02003 orr r3, r3, #32 + 5772 0024 2366 str r3, [r4, #96] + 5773 .L401: +4184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5774 .loc 1 4184 5 view .LVU1927 +4184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5775 .loc 1 4184 13 is_stmt 0 view .LVU1928 + 5776 0026 236E ldr r3, [r4, #96] +4184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5777 .loc 1 4184 8 view .LVU1929 + 5778 0028 93B9 cbnz r3, .L402 +4186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5779 .loc 1 4186 7 is_stmt 1 view .LVU1930 +4186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5780 .loc 1 4186 15 is_stmt 0 view .LVU1931 + 5781 002a 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 5782 002e DBB2 uxtb r3, r3 +4186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5783 .loc 1 4186 10 view .LVU1932 + 5784 0030 042B cmp r3, #4 + 5785 0032 06D0 beq .L406 +4198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx complete callback */ + 5786 .loc 1 4198 9 is_stmt 1 view .LVU1933 +4198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx complete callback */ + 5787 .loc 1 4198 21 is_stmt 0 view .LVU1934 + 5788 0034 0123 movs r3, #1 + ARM GAS /tmp/ccywxtmH.s page 210 + + + 5789 0036 84F85D30 strb r3, [r4, #93] +4203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5790 .loc 1 4203 9 is_stmt 1 view .LVU1935 + 5791 003a 2046 mov r0, r4 + 5792 003c FFF7FEFF bl HAL_SPI_TxRxCpltCallback + 5793 .LVL370: + 5794 .L400: +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5795 .loc 1 4220 1 is_stmt 0 view .LVU1936 + 5796 0040 10BD pop {r4, pc} + 5797 .LVL371: + 5798 .L406: +4188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ + 5799 .loc 1 4188 9 is_stmt 1 view .LVU1937 +4188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ + 5800 .loc 1 4188 21 is_stmt 0 view .LVU1938 + 5801 0042 0123 movs r3, #1 + 5802 0044 84F85D30 strb r3, [r4, #93] +4193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5803 .loc 1 4193 9 is_stmt 1 view .LVU1939 + 5804 0048 2046 mov r0, r4 + 5805 004a FFF7FEFF bl HAL_SPI_RxCpltCallback + 5806 .LVL372: + 5807 004e F7E7 b .L400 + 5808 .L402: +4209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ + 5809 .loc 1 4209 7 view .LVU1940 +4209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ + 5810 .loc 1 4209 19 is_stmt 0 view .LVU1941 + 5811 0050 0123 movs r3, #1 + 5812 0052 84F85D30 strb r3, [r4, #93] +4214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 5813 .loc 1 4214 7 is_stmt 1 view .LVU1942 + 5814 0056 2046 mov r0, r4 + 5815 0058 FFF7FEFF bl HAL_SPI_ErrorCallback + 5816 .LVL373: +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5817 .loc 1 4220 1 is_stmt 0 view .LVU1943 + 5818 005c F0E7 b .L400 + 5819 .cfi_endproc + 5820 .LFE181: + 5822 .section .text.SPI_2linesTxISR_8BIT,"ax",%progbits + 5823 .align 1 + 5824 .syntax unified + 5825 .thumb + 5826 .thumb_func + 5828 SPI_2linesTxISR_8BIT: + 5829 .LVL374: + 5830 .LFB170: +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in packing Bit mode */ + 5831 .loc 1 3623 1 is_stmt 1 view -0 + 5832 .cfi_startproc + 5833 @ args = 0, pretend = 0, frame = 0 + 5834 @ frame_needed = 0, uses_anonymous_args = 0 +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in packing Bit mode */ + 5835 .loc 1 3623 1 is_stmt 0 view .LVU1945 + 5836 0000 08B5 push {r3, lr} + ARM GAS /tmp/ccywxtmH.s page 211 + + + 5837 .cfi_def_cfa_offset 8 + 5838 .cfi_offset 3, -8 + 5839 .cfi_offset 14, -4 +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5840 .loc 1 3625 3 is_stmt 1 view .LVU1946 +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5841 .loc 1 3625 11 is_stmt 0 view .LVU1947 + 5842 0002 C38F ldrh r3, [r0, #62] + 5843 0004 9BB2 uxth r3, r3 +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5844 .loc 1 3625 6 view .LVU1948 + 5845 0006 012B cmp r3, #1 + 5846 0008 18D9 bls .L408 +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5847 .loc 1 3627 5 is_stmt 1 view .LVU1949 +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5848 .loc 1 3627 44 is_stmt 0 view .LVU1950 + 5849 000a 826B ldr r2, [r0, #56] +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5850 .loc 1 3627 9 view .LVU1951 + 5851 000c 0368 ldr r3, [r0] +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5852 .loc 1 3627 26 view .LVU1952 + 5853 000e 1288 ldrh r2, [r2] +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 5854 .loc 1 3627 24 view .LVU1953 + 5855 0010 DA60 str r2, [r3, #12] +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 5856 .loc 1 3628 5 is_stmt 1 view .LVU1954 +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 5857 .loc 1 3628 9 is_stmt 0 view .LVU1955 + 5858 0012 836B ldr r3, [r0, #56] +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 5859 .loc 1 3628 22 view .LVU1956 + 5860 0014 0233 adds r3, r3, #2 + 5861 0016 8363 str r3, [r0, #56] +3629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5862 .loc 1 3629 5 is_stmt 1 view .LVU1957 +3629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5863 .loc 1 3629 9 is_stmt 0 view .LVU1958 + 5864 0018 C38F ldrh r3, [r0, #62] + 5865 001a 9BB2 uxth r3, r3 +3629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5866 .loc 1 3629 23 view .LVU1959 + 5867 001c 023B subs r3, r3, #2 + 5868 001e 9BB2 uxth r3, r3 + 5869 0020 C387 strh r3, [r0, #62] @ movhi + 5870 .L409: +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5871 .loc 1 3640 3 is_stmt 1 view .LVU1960 +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5872 .loc 1 3640 11 is_stmt 0 view .LVU1961 + 5873 0022 C38F ldrh r3, [r0, #62] + 5874 0024 9BB2 uxth r3, r3 +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5875 .loc 1 3640 6 view .LVU1962 + 5876 0026 43B9 cbnz r3, .L407 + ARM GAS /tmp/ccywxtmH.s page 212 + + +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5877 .loc 1 3654 5 is_stmt 1 view .LVU1963 + 5878 0028 0268 ldr r2, [r0] + 5879 002a 5368 ldr r3, [r2, #4] + 5880 002c 23F08003 bic r3, r3, #128 + 5881 0030 5360 str r3, [r2, #4] +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5882 .loc 1 3656 5 view .LVU1964 +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5883 .loc 1 3656 13 is_stmt 0 view .LVU1965 + 5884 0032 B0F84630 ldrh r3, [r0, #70] + 5885 0036 9BB2 uxth r3, r3 +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5886 .loc 1 3656 8 view .LVU1966 + 5887 0038 6BB1 cbz r3, .L412 + 5888 .LVL375: + 5889 .L407: +3661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5890 .loc 1 3661 1 view .LVU1967 + 5891 003a 08BD pop {r3, pc} + 5892 .LVL376: + 5893 .L408: +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5894 .loc 1 3634 5 is_stmt 1 view .LVU1968 +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5895 .loc 1 3634 50 is_stmt 0 view .LVU1969 + 5896 003c 826B ldr r2, [r0, #56] +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5897 .loc 1 3634 27 view .LVU1970 + 5898 003e 0368 ldr r3, [r0] +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5899 .loc 1 3634 45 view .LVU1971 + 5900 0040 1278 ldrb r2, [r2] @ zero_extendqisi2 +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 5901 .loc 1 3634 42 view .LVU1972 + 5902 0042 1A73 strb r2, [r3, #12] +3635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5903 .loc 1 3635 5 is_stmt 1 view .LVU1973 +3635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5904 .loc 1 3635 9 is_stmt 0 view .LVU1974 + 5905 0044 836B ldr r3, [r0, #56] +3635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 5906 .loc 1 3635 21 view .LVU1975 + 5907 0046 0133 adds r3, r3, #1 + 5908 0048 8363 str r3, [r0, #56] +3636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5909 .loc 1 3636 5 is_stmt 1 view .LVU1976 +3636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5910 .loc 1 3636 9 is_stmt 0 view .LVU1977 + 5911 004a C38F ldrh r3, [r0, #62] + 5912 004c 9BB2 uxth r3, r3 +3636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5913 .loc 1 3636 22 view .LVU1978 + 5914 004e 013B subs r3, r3, #1 + 5915 0050 9BB2 uxth r3, r3 + 5916 0052 C387 strh r3, [r0, #62] @ movhi + 5917 0054 E5E7 b .L409 + ARM GAS /tmp/ccywxtmH.s page 213 + + + 5918 .L412: +3658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5919 .loc 1 3658 7 is_stmt 1 view .LVU1979 + 5920 0056 FFF7FEFF bl SPI_CloseRxTx_ISR + 5921 .LVL377: +3661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 5922 .loc 1 3661 1 is_stmt 0 view .LVU1980 + 5923 005a EEE7 b .L407 + 5924 .cfi_endproc + 5925 .LFE170: + 5927 .section .text.SPI_2linesRxISR_8BIT,"ax",%progbits + 5928 .align 1 + 5929 .syntax unified + 5930 .thumb + 5931 .thumb_func + 5933 SPI_2linesRxISR_8BIT: + 5934 .LVL378: + 5935 .LFB169: +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in packing mode */ + 5936 .loc 1 3538 1 is_stmt 1 view -0 + 5937 .cfi_startproc + 5938 @ args = 0, pretend = 0, frame = 0 + 5939 @ frame_needed = 0, uses_anonymous_args = 0 +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in packing mode */ + 5940 .loc 1 3538 1 is_stmt 0 view .LVU1982 + 5941 0000 08B5 push {r3, lr} + 5942 .cfi_def_cfa_offset 8 + 5943 .cfi_offset 3, -8 + 5944 .cfi_offset 14, -4 +3540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5945 .loc 1 3540 3 is_stmt 1 view .LVU1983 +3540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5946 .loc 1 3540 11 is_stmt 0 view .LVU1984 + 5947 0002 B0F84630 ldrh r3, [r0, #70] + 5948 0006 9BB2 uxth r3, r3 +3540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5949 .loc 1 3540 6 view .LVU1985 + 5950 0008 012B cmp r3, #1 + 5951 000a 18D9 bls .L414 +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5952 .loc 1 3542 5 is_stmt 1 view .LVU1986 +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5953 .loc 1 3542 54 is_stmt 0 view .LVU1987 + 5954 000c 0368 ldr r3, [r0] +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5955 .loc 1 3542 64 view .LVU1988 + 5956 000e DA68 ldr r2, [r3, #12] +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5957 .loc 1 3542 23 view .LVU1989 + 5958 0010 036C ldr r3, [r0, #64] +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 5959 .loc 1 3542 37 view .LVU1990 + 5960 0012 1A80 strh r2, [r3] @ movhi +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + 5961 .loc 1 3543 5 is_stmt 1 view .LVU1991 +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + 5962 .loc 1 3543 9 is_stmt 0 view .LVU1992 + ARM GAS /tmp/ccywxtmH.s page 214 + + + 5963 0014 036C ldr r3, [r0, #64] +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + 5964 .loc 1 3543 22 view .LVU1993 + 5965 0016 0233 adds r3, r3, #2 + 5966 0018 0364 str r3, [r0, #64] +3544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 1U) + 5967 .loc 1 3544 5 is_stmt 1 view .LVU1994 +3544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 1U) + 5968 .loc 1 3544 9 is_stmt 0 view .LVU1995 + 5969 001a B0F84630 ldrh r3, [r0, #70] + 5970 001e 9BB2 uxth r3, r3 +3544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 1U) + 5971 .loc 1 3544 23 view .LVU1996 + 5972 0020 023B subs r3, r3, #2 + 5973 0022 9BB2 uxth r3, r3 + 5974 0024 A0F84630 strh r3, [r0, #70] @ movhi +3545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5975 .loc 1 3545 5 is_stmt 1 view .LVU1997 +3545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5976 .loc 1 3545 13 is_stmt 0 view .LVU1998 + 5977 0028 B0F84630 ldrh r3, [r0, #70] + 5978 002c 9BB2 uxth r3, r3 +3545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5979 .loc 1 3545 8 view .LVU1999 + 5980 002e 012B cmp r3, #1 + 5981 0030 13D1 bne .L415 +3548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5982 .loc 1 3548 7 is_stmt 1 view .LVU2000 + 5983 0032 0268 ldr r2, [r0] + 5984 0034 5368 ldr r3, [r2, #4] + 5985 0036 43F48053 orr r3, r3, #4096 + 5986 003a 5360 str r3, [r2, #4] + 5987 003c 0DE0 b .L415 + 5988 .L414: +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5989 .loc 1 3554 5 view .LVU2001 +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5990 .loc 1 3554 48 is_stmt 0 view .LVU2002 + 5991 003e 0268 ldr r2, [r0] +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5992 .loc 1 3554 10 view .LVU2003 + 5993 0040 036C ldr r3, [r0, #64] +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5994 .loc 1 3554 25 view .LVU2004 + 5995 0042 127B ldrb r2, [r2, #12] @ zero_extendqisi2 +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 5996 .loc 1 3554 23 view .LVU2005 + 5997 0044 1A70 strb r2, [r3] +3555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 5998 .loc 1 3555 5 is_stmt 1 view .LVU2006 +3555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 5999 .loc 1 3555 9 is_stmt 0 view .LVU2007 + 6000 0046 036C ldr r3, [r0, #64] +3555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 6001 .loc 1 3555 21 view .LVU2008 + 6002 0048 0133 adds r3, r3, #1 + 6003 004a 0364 str r3, [r0, #64] + ARM GAS /tmp/ccywxtmH.s page 215 + + +3556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6004 .loc 1 3556 5 is_stmt 1 view .LVU2009 +3556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6005 .loc 1 3556 9 is_stmt 0 view .LVU2010 + 6006 004c B0F84630 ldrh r3, [r0, #70] + 6007 0050 9BB2 uxth r3, r3 +3556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6008 .loc 1 3556 22 view .LVU2011 + 6009 0052 013B subs r3, r3, #1 + 6010 0054 9BB2 uxth r3, r3 + 6011 0056 A0F84630 strh r3, [r0, #70] @ movhi + 6012 .L415: +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6013 .loc 1 3560 3 is_stmt 1 view .LVU2012 +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6014 .loc 1 3560 11 is_stmt 0 view .LVU2013 + 6015 005a B0F84630 ldrh r3, [r0, #70] + 6016 005e 9BB2 uxth r3, r3 +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6017 .loc 1 3560 6 view .LVU2014 + 6018 0060 3BB9 cbnz r3, .L413 +3572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6019 .loc 1 3572 5 is_stmt 1 view .LVU2015 + 6020 0062 0268 ldr r2, [r0] + 6021 0064 5368 ldr r3, [r2, #4] + 6022 0066 23F06003 bic r3, r3, #96 + 6023 006a 5360 str r3, [r2, #4] +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6024 .loc 1 3574 5 view .LVU2016 +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6025 .loc 1 3574 13 is_stmt 0 view .LVU2017 + 6026 006c C38F ldrh r3, [r0, #62] + 6027 006e 9BB2 uxth r3, r3 +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6028 .loc 1 3574 8 view .LVU2018 + 6029 0070 03B1 cbz r3, .L418 + 6030 .LVL379: + 6031 .L413: +3579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6032 .loc 1 3579 1 view .LVU2019 + 6033 0072 08BD pop {r3, pc} + 6034 .LVL380: + 6035 .L418: +3576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6036 .loc 1 3576 7 is_stmt 1 view .LVU2020 + 6037 0074 FFF7FEFF bl SPI_CloseRxTx_ISR + 6038 .LVL381: +3579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6039 .loc 1 3579 1 is_stmt 0 view .LVU2021 + 6040 0078 FBE7 b .L413 + 6041 .cfi_endproc + 6042 .LFE169: + 6044 .section .text.SPI_2linesTxISR_16BIT,"ax",%progbits + 6045 .align 1 + 6046 .syntax unified + 6047 .thumb + 6048 .thumb_func + ARM GAS /tmp/ccywxtmH.s page 216 + + + 6050 SPI_2linesTxISR_16BIT: + 6051 .LVL382: + 6052 .LFB172: +3726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 6053 .loc 1 3726 1 is_stmt 1 view -0 + 6054 .cfi_startproc + 6055 @ args = 0, pretend = 0, frame = 0 + 6056 @ frame_needed = 0, uses_anonymous_args = 0 +3726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 6057 .loc 1 3726 1 is_stmt 0 view .LVU2023 + 6058 0000 08B5 push {r3, lr} + 6059 .cfi_def_cfa_offset 8 + 6060 .cfi_offset 3, -8 + 6061 .cfi_offset 14, -4 +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 6062 .loc 1 3728 3 is_stmt 1 view .LVU2024 +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 6063 .loc 1 3728 42 is_stmt 0 view .LVU2025 + 6064 0002 826B ldr r2, [r0, #56] +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 6065 .loc 1 3728 7 view .LVU2026 + 6066 0004 0368 ldr r3, [r0] +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 6067 .loc 1 3728 24 view .LVU2027 + 6068 0006 1288 ldrh r2, [r2] +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 6069 .loc 1 3728 22 view .LVU2028 + 6070 0008 DA60 str r2, [r3, #12] +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 6071 .loc 1 3729 3 is_stmt 1 view .LVU2029 +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 6072 .loc 1 3729 7 is_stmt 0 view .LVU2030 + 6073 000a 836B ldr r3, [r0, #56] +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 6074 .loc 1 3729 20 view .LVU2031 + 6075 000c 0233 adds r3, r3, #2 + 6076 000e 8363 str r3, [r0, #56] +3730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6077 .loc 1 3730 3 is_stmt 1 view .LVU2032 +3730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6078 .loc 1 3730 7 is_stmt 0 view .LVU2033 + 6079 0010 C38F ldrh r3, [r0, #62] + 6080 0012 9BB2 uxth r3, r3 +3730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6081 .loc 1 3730 20 view .LVU2034 + 6082 0014 013B subs r3, r3, #1 + 6083 0016 9BB2 uxth r3, r3 + 6084 0018 C387 strh r3, [r0, #62] @ movhi +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6085 .loc 1 3733 3 is_stmt 1 view .LVU2035 +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6086 .loc 1 3733 11 is_stmt 0 view .LVU2036 + 6087 001a C38F ldrh r3, [r0, #62] + 6088 001c 9BB2 uxth r3, r3 +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6089 .loc 1 3733 6 view .LVU2037 + 6090 001e 43B9 cbnz r3, .L419 + ARM GAS /tmp/ccywxtmH.s page 217 + + +3747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6091 .loc 1 3747 5 is_stmt 1 view .LVU2038 + 6092 0020 0268 ldr r2, [r0] + 6093 0022 5368 ldr r3, [r2, #4] + 6094 0024 23F08003 bic r3, r3, #128 + 6095 0028 5360 str r3, [r2, #4] +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6096 .loc 1 3749 5 view .LVU2039 +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6097 .loc 1 3749 13 is_stmt 0 view .LVU2040 + 6098 002a B0F84630 ldrh r3, [r0, #70] + 6099 002e 9BB2 uxth r3, r3 +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6100 .loc 1 3749 8 view .LVU2041 + 6101 0030 03B1 cbz r3, .L422 + 6102 .LVL383: + 6103 .L419: +3754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6104 .loc 1 3754 1 view .LVU2042 + 6105 0032 08BD pop {r3, pc} + 6106 .LVL384: + 6107 .L422: +3751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6108 .loc 1 3751 7 is_stmt 1 view .LVU2043 + 6109 0034 FFF7FEFF bl SPI_CloseRxTx_ISR + 6110 .LVL385: +3754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6111 .loc 1 3754 1 is_stmt 0 view .LVU2044 + 6112 0038 FBE7 b .L419 + 6113 .cfi_endproc + 6114 .LFE172: + 6116 .section .text.SPI_2linesRxISR_16BIT,"ax",%progbits + 6117 .align 1 + 6118 .syntax unified + 6119 .thumb + 6120 .thumb_func + 6122 SPI_2linesRxISR_16BIT: + 6123 .LVL386: + 6124 .LFB171: +3670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in 16 Bit mode */ + 6125 .loc 1 3670 1 is_stmt 1 view -0 + 6126 .cfi_startproc + 6127 @ args = 0, pretend = 0, frame = 0 + 6128 @ frame_needed = 0, uses_anonymous_args = 0 +3670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in 16 Bit mode */ + 6129 .loc 1 3670 1 is_stmt 0 view .LVU2046 + 6130 0000 08B5 push {r3, lr} + 6131 .cfi_def_cfa_offset 8 + 6132 .cfi_offset 3, -8 + 6133 .cfi_offset 14, -4 +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 6134 .loc 1 3672 3 is_stmt 1 view .LVU2047 +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 6135 .loc 1 3672 52 is_stmt 0 view .LVU2048 + 6136 0002 0368 ldr r3, [r0] +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 6137 .loc 1 3672 62 view .LVU2049 + ARM GAS /tmp/ccywxtmH.s page 218 + + + 6138 0004 DA68 ldr r2, [r3, #12] +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 6139 .loc 1 3672 21 view .LVU2050 + 6140 0006 036C ldr r3, [r0, #64] +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 6141 .loc 1 3672 35 view .LVU2051 + 6142 0008 1A80 strh r2, [r3] @ movhi +3673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 6143 .loc 1 3673 3 is_stmt 1 view .LVU2052 +3673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 6144 .loc 1 3673 7 is_stmt 0 view .LVU2053 + 6145 000a 036C ldr r3, [r0, #64] +3673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 6146 .loc 1 3673 20 view .LVU2054 + 6147 000c 0233 adds r3, r3, #2 + 6148 000e 0364 str r3, [r0, #64] +3674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6149 .loc 1 3674 3 is_stmt 1 view .LVU2055 +3674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6150 .loc 1 3674 7 is_stmt 0 view .LVU2056 + 6151 0010 B0F84630 ldrh r3, [r0, #70] + 6152 0014 9BB2 uxth r3, r3 +3674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6153 .loc 1 3674 20 view .LVU2057 + 6154 0016 013B subs r3, r3, #1 + 6155 0018 9BB2 uxth r3, r3 + 6156 001a A0F84630 strh r3, [r0, #70] @ movhi +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6157 .loc 1 3676 3 is_stmt 1 view .LVU2058 +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6158 .loc 1 3676 11 is_stmt 0 view .LVU2059 + 6159 001e B0F84630 ldrh r3, [r0, #70] + 6160 0022 9BB2 uxth r3, r3 +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6161 .loc 1 3676 6 view .LVU2060 + 6162 0024 3BB9 cbnz r3, .L423 +3687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6163 .loc 1 3687 5 is_stmt 1 view .LVU2061 + 6164 0026 0268 ldr r2, [r0] + 6165 0028 5368 ldr r3, [r2, #4] + 6166 002a 23F04003 bic r3, r3, #64 + 6167 002e 5360 str r3, [r2, #4] +3689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6168 .loc 1 3689 5 view .LVU2062 +3689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6169 .loc 1 3689 13 is_stmt 0 view .LVU2063 + 6170 0030 C38F ldrh r3, [r0, #62] + 6171 0032 9BB2 uxth r3, r3 +3689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6172 .loc 1 3689 8 view .LVU2064 + 6173 0034 03B1 cbz r3, .L426 + 6174 .LVL387: + 6175 .L423: +3694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6176 .loc 1 3694 1 view .LVU2065 + 6177 0036 08BD pop {r3, pc} + 6178 .LVL388: + ARM GAS /tmp/ccywxtmH.s page 219 + + + 6179 .L426: +3691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6180 .loc 1 3691 7 is_stmt 1 view .LVU2066 + 6181 0038 FFF7FEFF bl SPI_CloseRxTx_ISR + 6182 .LVL389: +3694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6183 .loc 1 3694 1 is_stmt 0 view .LVU2067 + 6184 003c FBE7 b .L423 + 6185 .cfi_endproc + 6186 .LFE171: + 6188 .section .text.SPI_DMAError,"ax",%progbits + 6189 .align 1 + 6190 .syntax unified + 6191 .thumb + 6192 .thumb_func + 6194 SPI_DMAError: + 6195 .LVL390: + 6196 .LFB165: +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6197 .loc 1 3362 1 is_stmt 1 view -0 + 6198 .cfi_startproc + 6199 @ args = 0, pretend = 0, frame = 0 + 6200 @ frame_needed = 0, uses_anonymous_args = 0 +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6201 .loc 1 3362 1 is_stmt 0 view .LVU2069 + 6202 0000 08B5 push {r3, lr} + 6203 .cfi_def_cfa_offset 8 + 6204 .cfi_offset 3, -8 + 6205 .cfi_offset 14, -4 +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6206 .loc 1 3363 3 is_stmt 1 view .LVU2070 +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6207 .loc 1 3363 22 is_stmt 0 view .LVU2071 + 6208 0002 406A ldr r0, [r0, #36] + 6209 .LVL391: +3366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6210 .loc 1 3366 3 is_stmt 1 view .LVU2072 + 6211 0004 0268 ldr r2, [r0] + 6212 0006 5368 ldr r3, [r2, #4] + 6213 0008 23F00303 bic r3, r3, #3 + 6214 000c 5360 str r3, [r2, #4] +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6215 .loc 1 3368 3 view .LVU2073 + 6216 000e 036E ldr r3, [r0, #96] + 6217 0010 43F01003 orr r3, r3, #16 + 6218 0014 0366 str r3, [r0, #96] +3369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ + 6219 .loc 1 3369 3 view .LVU2074 +3369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ + 6220 .loc 1 3369 15 is_stmt 0 view .LVU2075 + 6221 0016 0123 movs r3, #1 + 6222 0018 80F85D30 strb r3, [r0, #93] +3374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6223 .loc 1 3374 3 is_stmt 1 view .LVU2076 + 6224 001c FFF7FEFF bl HAL_SPI_ErrorCallback + 6225 .LVL392: +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 220 + + + 6226 .loc 1 3376 1 is_stmt 0 view .LVU2077 + 6227 0020 08BD pop {r3, pc} + 6228 .cfi_endproc + 6229 .LFE165: + 6231 .section .text.SPI_DMATransmitCplt,"ax",%progbits + 6232 .align 1 + 6233 .syntax unified + 6234 .thumb + 6235 .thumb_func + 6237 SPI_DMATransmitCplt: + 6238 .LVL393: + 6239 .LFB159: +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6240 .loc 1 3034 1 is_stmt 1 view -0 + 6241 .cfi_startproc + 6242 @ args = 0, pretend = 0, frame = 8 + 6243 @ frame_needed = 0, uses_anonymous_args = 0 +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6244 .loc 1 3034 1 is_stmt 0 view .LVU2079 + 6245 0000 30B5 push {r4, r5, lr} + 6246 .cfi_def_cfa_offset 12 + 6247 .cfi_offset 4, -12 + 6248 .cfi_offset 5, -8 + 6249 .cfi_offset 14, -4 + 6250 0002 83B0 sub sp, sp, #12 + 6251 .cfi_def_cfa_offset 24 + 6252 0004 0546 mov r5, r0 +3035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 6253 .loc 1 3035 3 is_stmt 1 view .LVU2080 +3035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 6254 .loc 1 3035 22 is_stmt 0 view .LVU2081 + 6255 0006 446A ldr r4, [r0, #36] + 6256 .LVL394: +3036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6257 .loc 1 3036 3 is_stmt 1 view .LVU2082 +3039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6258 .loc 1 3039 3 view .LVU2083 +3039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6259 .loc 1 3039 15 is_stmt 0 view .LVU2084 + 6260 0008 FFF7FEFF bl HAL_GetTick + 6261 .LVL395: +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6262 .loc 1 3042 3 is_stmt 1 view .LVU2085 +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6263 .loc 1 3042 12 is_stmt 0 view .LVU2086 + 6264 000c 2B68 ldr r3, [r5] +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6265 .loc 1 3042 22 view .LVU2087 + 6266 000e 1B68 ldr r3, [r3] +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6267 .loc 1 3042 6 view .LVU2088 + 6268 0010 13F0200F tst r3, #32 + 6269 0014 23D1 bne .L430 + 6270 0016 0246 mov r2, r0 +3045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6271 .loc 1 3045 5 is_stmt 1 view .LVU2089 + 6272 0018 2168 ldr r1, [r4] + ARM GAS /tmp/ccywxtmH.s page 221 + + + 6273 001a 4B68 ldr r3, [r1, #4] + 6274 001c 23F02003 bic r3, r3, #32 + 6275 0020 4B60 str r3, [r1, #4] +3048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6276 .loc 1 3048 5 view .LVU2090 + 6277 0022 2168 ldr r1, [r4] + 6278 0024 4B68 ldr r3, [r1, #4] + 6279 0026 23F00203 bic r3, r3, #2 + 6280 002a 4B60 str r3, [r1, #4] +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6281 .loc 1 3051 5 view .LVU2091 +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6282 .loc 1 3051 9 is_stmt 0 view .LVU2092 + 6283 002c 6421 movs r1, #100 + 6284 002e 2046 mov r0, r4 + 6285 .LVL396: +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6286 .loc 1 3051 9 view .LVU2093 + 6287 0030 FFF7FEFF bl SPI_EndRxTxTransaction + 6288 .LVL397: +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6289 .loc 1 3051 8 view .LVU2094 + 6290 0034 18B1 cbz r0, .L431 +3053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6291 .loc 1 3053 7 is_stmt 1 view .LVU2095 + 6292 0036 236E ldr r3, [r4, #96] + 6293 0038 43F02003 orr r3, r3, #32 + 6294 003c 2366 str r3, [r4, #96] + 6295 .L431: +3057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6296 .loc 1 3057 5 view .LVU2096 +3057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6297 .loc 1 3057 19 is_stmt 0 view .LVU2097 + 6298 003e A368 ldr r3, [r4, #8] +3057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6299 .loc 1 3057 8 view .LVU2098 + 6300 0040 33B9 cbnz r3, .L432 +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6301 .loc 1 3059 7 is_stmt 1 view .LVU2099 + 6302 .LBB6: +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6303 .loc 1 3059 7 view .LVU2100 + 6304 0042 0193 str r3, [sp, #4] +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6305 .loc 1 3059 7 view .LVU2101 + 6306 0044 2368 ldr r3, [r4] + 6307 0046 DA68 ldr r2, [r3, #12] + 6308 0048 0192 str r2, [sp, #4] +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6309 .loc 1 3059 7 view .LVU2102 + 6310 004a 9B68 ldr r3, [r3, #8] + 6311 004c 0193 str r3, [sp, #4] +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6312 .loc 1 3059 7 view .LVU2103 + 6313 004e 019B ldr r3, [sp, #4] + 6314 .L432: + 6315 .LBE6: + ARM GAS /tmp/ccywxtmH.s page 222 + + +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6316 .loc 1 3059 7 discriminator 1 view .LVU2104 +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6317 .loc 1 3062 5 discriminator 1 view .LVU2105 +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6318 .loc 1 3062 23 is_stmt 0 discriminator 1 view .LVU2106 + 6319 0050 0023 movs r3, #0 + 6320 0052 E387 strh r3, [r4, #62] @ movhi +3063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6321 .loc 1 3063 5 is_stmt 1 discriminator 1 view .LVU2107 +3063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6322 .loc 1 3063 17 is_stmt 0 discriminator 1 view .LVU2108 + 6323 0054 0123 movs r3, #1 + 6324 0056 84F85D30 strb r3, [r4, #93] +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6325 .loc 1 3065 5 is_stmt 1 discriminator 1 view .LVU2109 +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6326 .loc 1 3065 13 is_stmt 0 discriminator 1 view .LVU2110 + 6327 005a 236E ldr r3, [r4, #96] +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6328 .loc 1 3065 8 discriminator 1 view .LVU2111 + 6329 005c 23B9 cbnz r3, .L435 + 6330 .L430: +3080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6331 .loc 1 3080 3 is_stmt 1 view .LVU2112 + 6332 005e 2046 mov r0, r4 + 6333 0060 FFF7FEFF bl HAL_SPI_TxCpltCallback + 6334 .LVL398: + 6335 .L429: +3082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6336 .loc 1 3082 1 is_stmt 0 view .LVU2113 + 6337 0064 03B0 add sp, sp, #12 + 6338 .cfi_remember_state + 6339 .cfi_def_cfa_offset 12 + 6340 @ sp needed + 6341 0066 30BD pop {r4, r5, pc} + 6342 .LVL399: + 6343 .L435: + 6344 .cfi_restore_state +3071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6345 .loc 1 3071 7 is_stmt 1 view .LVU2114 + 6346 0068 2046 mov r0, r4 + 6347 006a FFF7FEFF bl HAL_SPI_ErrorCallback + 6348 .LVL400: +3073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6349 .loc 1 3073 7 view .LVU2115 + 6350 006e F9E7 b .L429 + 6351 .cfi_endproc + 6352 .LFE159: + 6354 .section .text.SPI_DMAReceiveCplt,"ax",%progbits + 6355 .align 1 + 6356 .syntax unified + 6357 .thumb + 6358 .thumb_func + 6360 SPI_DMAReceiveCplt: + 6361 .LVL401: + 6362 .LFB160: + ARM GAS /tmp/ccywxtmH.s page 223 + + +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6363 .loc 1 3091 1 view -0 + 6364 .cfi_startproc + 6365 @ args = 0, pretend = 0, frame = 0 + 6366 @ frame_needed = 0, uses_anonymous_args = 0 +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6367 .loc 1 3091 1 is_stmt 0 view .LVU2117 + 6368 0000 38B5 push {r3, r4, r5, lr} + 6369 .cfi_def_cfa_offset 16 + 6370 .cfi_offset 3, -16 + 6371 .cfi_offset 4, -12 + 6372 .cfi_offset 5, -8 + 6373 .cfi_offset 14, -4 + 6374 0002 0546 mov r5, r0 +3092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 6375 .loc 1 3092 3 is_stmt 1 view .LVU2118 +3092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 6376 .loc 1 3092 22 is_stmt 0 view .LVU2119 + 6377 0004 446A ldr r4, [r0, #36] + 6378 .LVL402: +3093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 6379 .loc 1 3093 3 is_stmt 1 view .LVU2120 +3101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6380 .loc 1 3101 3 view .LVU2121 +3101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6381 .loc 1 3101 15 is_stmt 0 view .LVU2122 + 6382 0006 FFF7FEFF bl HAL_GetTick + 6383 .LVL403: +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6384 .loc 1 3104 3 is_stmt 1 view .LVU2123 +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6385 .loc 1 3104 12 is_stmt 0 view .LVU2124 + 6386 000a 2B68 ldr r3, [r5] +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6387 .loc 1 3104 22 view .LVU2125 + 6388 000c 1B68 ldr r3, [r3] +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6389 .loc 1 3104 6 view .LVU2126 + 6390 000e 13F0200F tst r3, #32 + 6391 0012 1FD1 bne .L437 + 6392 0014 0246 mov r2, r0 +3107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6393 .loc 1 3107 5 is_stmt 1 view .LVU2127 + 6394 0016 2168 ldr r1, [r4] + 6395 0018 4B68 ldr r3, [r1, #4] + 6396 001a 23F02003 bic r3, r3, #32 + 6397 001e 4B60 str r3, [r1, #4] +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6398 .loc 1 3153 5 view .LVU2128 +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6399 .loc 1 3153 20 is_stmt 0 view .LVU2129 + 6400 0020 A368 ldr r3, [r4, #8] +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6401 .loc 1 3153 8 view .LVU2130 + 6402 0022 1BB9 cbnz r3, .L438 +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6403 .loc 1 3153 70 discriminator 1 view .LVU2131 + ARM GAS /tmp/ccywxtmH.s page 224 + + + 6404 0024 6368 ldr r3, [r4, #4] +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6405 .loc 1 3153 56 discriminator 1 view .LVU2132 + 6406 0026 B3F5827F cmp r3, #260 + 6407 002a 17D0 beq .L443 + 6408 .L438: +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6409 .loc 1 3161 7 is_stmt 1 view .LVU2133 + 6410 002c 2168 ldr r1, [r4] + 6411 002e 4B68 ldr r3, [r1, #4] + 6412 0030 23F00103 bic r3, r3, #1 + 6413 0034 4B60 str r3, [r1, #4] + 6414 .L439: +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6415 .loc 1 3165 5 view .LVU2134 +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6416 .loc 1 3165 9 is_stmt 0 view .LVU2135 + 6417 0036 6421 movs r1, #100 + 6418 0038 2046 mov r0, r4 + 6419 .LVL404: +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6420 .loc 1 3165 9 view .LVU2136 + 6421 003a FFF7FEFF bl SPI_EndRxTransaction + 6422 .LVL405: +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6423 .loc 1 3165 8 view .LVU2137 + 6424 003e 08B1 cbz r0, .L440 +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6425 .loc 1 3167 7 is_stmt 1 view .LVU2138 +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6426 .loc 1 3167 23 is_stmt 0 view .LVU2139 + 6427 0040 2023 movs r3, #32 + 6428 0042 2366 str r3, [r4, #96] + 6429 .L440: +3170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6430 .loc 1 3170 5 is_stmt 1 view .LVU2140 +3170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6431 .loc 1 3170 23 is_stmt 0 view .LVU2141 + 6432 0044 0023 movs r3, #0 + 6433 0046 A4F84630 strh r3, [r4, #70] @ movhi +3171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6434 .loc 1 3171 5 is_stmt 1 view .LVU2142 +3171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6435 .loc 1 3171 17 is_stmt 0 view .LVU2143 + 6436 004a 0123 movs r3, #1 + 6437 004c 84F85D30 strb r3, [r4, #93] +3182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6438 .loc 1 3182 5 is_stmt 1 view .LVU2144 +3182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6439 .loc 1 3182 13 is_stmt 0 view .LVU2145 + 6440 0050 236E ldr r3, [r4, #96] +3182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6441 .loc 1 3182 8 view .LVU2146 + 6442 0052 4BB9 cbnz r3, .L444 + 6443 .L437: +3197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6444 .loc 1 3197 3 is_stmt 1 view .LVU2147 + ARM GAS /tmp/ccywxtmH.s page 225 + + + 6445 0054 2046 mov r0, r4 + 6446 0056 FFF7FEFF bl HAL_SPI_RxCpltCallback + 6447 .LVL406: + 6448 .L436: +3199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6449 .loc 1 3199 1 is_stmt 0 view .LVU2148 + 6450 005a 38BD pop {r3, r4, r5, pc} + 6451 .LVL407: + 6452 .L443: +3156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6453 .loc 1 3156 7 is_stmt 1 view .LVU2149 + 6454 005c 2168 ldr r1, [r4] + 6455 005e 4B68 ldr r3, [r1, #4] + 6456 0060 23F00303 bic r3, r3, #3 + 6457 0064 4B60 str r3, [r1, #4] + 6458 0066 E6E7 b .L439 + 6459 .LVL408: + 6460 .L444: +3188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6461 .loc 1 3188 7 view .LVU2150 + 6462 0068 2046 mov r0, r4 + 6463 006a FFF7FEFF bl HAL_SPI_ErrorCallback + 6464 .LVL409: +3190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6465 .loc 1 3190 7 view .LVU2151 + 6466 006e F4E7 b .L436 + 6467 .cfi_endproc + 6468 .LFE160: + 6470 .section .text.SPI_DMATransmitReceiveCplt,"ax",%progbits + 6471 .align 1 + 6472 .syntax unified + 6473 .thumb + 6474 .thumb_func + 6476 SPI_DMATransmitReceiveCplt: + 6477 .LVL410: + 6478 .LFB161: +3208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6479 .loc 1 3208 1 view -0 + 6480 .cfi_startproc + 6481 @ args = 0, pretend = 0, frame = 0 + 6482 @ frame_needed = 0, uses_anonymous_args = 0 +3208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6483 .loc 1 3208 1 is_stmt 0 view .LVU2153 + 6484 0000 38B5 push {r3, r4, r5, lr} + 6485 .cfi_def_cfa_offset 16 + 6486 .cfi_offset 3, -16 + 6487 .cfi_offset 4, -12 + 6488 .cfi_offset 5, -8 + 6489 .cfi_offset 14, -4 + 6490 0002 0546 mov r5, r0 +3209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 6491 .loc 1 3209 3 is_stmt 1 view .LVU2154 +3209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 6492 .loc 1 3209 22 is_stmt 0 view .LVU2155 + 6493 0004 446A ldr r4, [r0, #36] + 6494 .LVL411: +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + ARM GAS /tmp/ccywxtmH.s page 226 + + + 6495 .loc 1 3210 3 is_stmt 1 view .LVU2156 +3218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6496 .loc 1 3218 3 view .LVU2157 +3218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6497 .loc 1 3218 15 is_stmt 0 view .LVU2158 + 6498 0006 FFF7FEFF bl HAL_GetTick + 6499 .LVL412: +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6500 .loc 1 3221 3 is_stmt 1 view .LVU2159 +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6501 .loc 1 3221 12 is_stmt 0 view .LVU2160 + 6502 000a 2B68 ldr r3, [r5] +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6503 .loc 1 3221 22 view .LVU2161 + 6504 000c 1B68 ldr r3, [r3] +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6505 .loc 1 3221 6 view .LVU2162 + 6506 000e 13F0200F tst r3, #32 + 6507 0012 1CD1 bne .L446 + 6508 0014 0246 mov r2, r0 +3224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6509 .loc 1 3224 5 is_stmt 1 view .LVU2163 + 6510 0016 2168 ldr r1, [r4] + 6511 0018 4B68 ldr r3, [r1, #4] + 6512 001a 23F02003 bic r3, r3, #32 + 6513 001e 4B60 str r3, [r1, #4] +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6514 .loc 1 3261 5 view .LVU2164 +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6515 .loc 1 3261 9 is_stmt 0 view .LVU2165 + 6516 0020 6421 movs r1, #100 + 6517 0022 2046 mov r0, r4 + 6518 .LVL413: +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6519 .loc 1 3261 9 view .LVU2166 + 6520 0024 FFF7FEFF bl SPI_EndRxTxTransaction + 6521 .LVL414: +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6522 .loc 1 3261 8 view .LVU2167 + 6523 0028 18B1 cbz r0, .L447 +3263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6524 .loc 1 3263 7 is_stmt 1 view .LVU2168 + 6525 002a 236E ldr r3, [r4, #96] + 6526 002c 43F02003 orr r3, r3, #32 + 6527 0030 2366 str r3, [r4, #96] + 6528 .L447: +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6529 .loc 1 3267 5 view .LVU2169 + 6530 0032 2268 ldr r2, [r4] + 6531 0034 5368 ldr r3, [r2, #4] + 6532 0036 23F00303 bic r3, r3, #3 + 6533 003a 5360 str r3, [r2, #4] +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 6534 .loc 1 3269 5 view .LVU2170 +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 6535 .loc 1 3269 23 is_stmt 0 view .LVU2171 + 6536 003c 0023 movs r3, #0 + ARM GAS /tmp/ccywxtmH.s page 227 + + + 6537 003e E387 strh r3, [r4, #62] @ movhi +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6538 .loc 1 3270 5 is_stmt 1 view .LVU2172 +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6539 .loc 1 3270 23 is_stmt 0 view .LVU2173 + 6540 0040 A4F84630 strh r3, [r4, #70] @ movhi +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6541 .loc 1 3271 5 is_stmt 1 view .LVU2174 +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6542 .loc 1 3271 17 is_stmt 0 view .LVU2175 + 6543 0044 0123 movs r3, #1 + 6544 0046 84F85D30 strb r3, [r4, #93] +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6545 .loc 1 3282 5 is_stmt 1 view .LVU2176 +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6546 .loc 1 3282 13 is_stmt 0 view .LVU2177 + 6547 004a 236E ldr r3, [r4, #96] +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6548 .loc 1 3282 8 view .LVU2178 + 6549 004c 1BB9 cbnz r3, .L450 + 6550 .L446: +3297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6551 .loc 1 3297 3 is_stmt 1 view .LVU2179 + 6552 004e 2046 mov r0, r4 + 6553 0050 FFF7FEFF bl HAL_SPI_TxRxCpltCallback + 6554 .LVL415: + 6555 .L445: +3299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6556 .loc 1 3299 1 is_stmt 0 view .LVU2180 + 6557 0054 38BD pop {r3, r4, r5, pc} + 6558 .LVL416: + 6559 .L450: +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6560 .loc 1 3288 7 is_stmt 1 view .LVU2181 + 6561 0056 2046 mov r0, r4 + 6562 0058 FFF7FEFF bl HAL_SPI_ErrorCallback + 6563 .LVL417: +3290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6564 .loc 1 3290 7 view .LVU2182 + 6565 005c FAE7 b .L445 + 6566 .cfi_endproc + 6567 .LFE161: + 6569 .section .text.HAL_SPI_IRQHandler,"ax",%progbits + 6570 .align 1 + 6571 .global HAL_SPI_IRQHandler + 6572 .syntax unified + 6573 .thumb + 6574 .thumb_func + 6576 HAL_SPI_IRQHandler: + 6577 .LVL418: + 6578 .LFB148: +2741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itsource = hspi->Instance->CR2; + 6579 .loc 1 2741 1 view -0 + 6580 .cfi_startproc + 6581 @ args = 0, pretend = 0, frame = 16 + 6582 @ frame_needed = 0, uses_anonymous_args = 0 +2741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itsource = hspi->Instance->CR2; + ARM GAS /tmp/ccywxtmH.s page 228 + + + 6583 .loc 1 2741 1 is_stmt 0 view .LVU2184 + 6584 0000 10B5 push {r4, lr} + 6585 .cfi_def_cfa_offset 8 + 6586 .cfi_offset 4, -8 + 6587 .cfi_offset 14, -4 + 6588 0002 84B0 sub sp, sp, #16 + 6589 .cfi_def_cfa_offset 24 + 6590 0004 0446 mov r4, r0 +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itflag = hspi->Instance->SR; + 6591 .loc 1 2742 3 is_stmt 1 view .LVU2185 +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itflag = hspi->Instance->SR; + 6592 .loc 1 2742 27 is_stmt 0 view .LVU2186 + 6593 0006 0268 ldr r2, [r0] +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itflag = hspi->Instance->SR; + 6594 .loc 1 2742 12 view .LVU2187 + 6595 0008 5168 ldr r1, [r2, #4] + 6596 .LVL419: +2743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6597 .loc 1 2743 3 is_stmt 1 view .LVU2188 +2743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6598 .loc 1 2743 12 is_stmt 0 view .LVU2189 + 6599 000a 9368 ldr r3, [r2, #8] + 6600 .LVL420: +2746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXN + 6601 .loc 1 2746 3 is_stmt 1 view .LVU2190 +2746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXN + 6602 .loc 1 2746 55 is_stmt 0 view .LVU2191 + 6603 000c 03F04100 and r0, r3, #65 + 6604 .LVL421: +2746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXN + 6605 .loc 1 2746 6 view .LVU2192 + 6606 0010 0128 cmp r0, #1 + 6607 0012 67D0 beq .L463 + 6608 .L452: +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6609 .loc 1 2754 3 is_stmt 1 view .LVU2193 +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6610 .loc 1 2754 6 is_stmt 0 view .LVU2194 + 6611 0014 13F0020F tst r3, #2 + 6612 0018 02D0 beq .L454 +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6613 .loc 1 2754 55 discriminator 1 view .LVU2195 + 6614 001a 11F0800F tst r1, #128 + 6615 001e 68D1 bne .L464 + 6616 .L454: +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT + 6617 .loc 1 2761 3 is_stmt 1 view .LVU2196 +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT + 6618 .loc 1 2761 6 is_stmt 0 view .LVU2197 + 6619 0020 13F4B07F tst r3, #352 + 6620 0024 68D0 beq .L451 +2762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6621 .loc 1 2762 60 view .LVU2198 + 6622 0026 11F0200F tst r1, #32 + 6623 002a 65D0 beq .L451 +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6624 .loc 1 2765 5 is_stmt 1 view .LVU2199 + ARM GAS /tmp/ccywxtmH.s page 229 + + +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6625 .loc 1 2765 8 is_stmt 0 view .LVU2200 + 6626 002c 13F0400F tst r3, #64 + 6627 0030 0FD0 beq .L455 +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6628 .loc 1 2767 7 is_stmt 1 view .LVU2201 +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6629 .loc 1 2767 15 is_stmt 0 view .LVU2202 + 6630 0032 94F85D00 ldrb r0, [r4, #93] @ zero_extendqisi2 + 6631 0036 C0B2 uxtb r0, r0 +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6632 .loc 1 2767 10 view .LVU2203 + 6633 0038 0328 cmp r0, #3 + 6634 003a 5FD0 beq .L456 +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 6635 .loc 1 2769 9 is_stmt 1 view .LVU2204 + 6636 003c 206E ldr r0, [r4, #96] + 6637 003e 40F00400 orr r0, r0, #4 + 6638 0042 2066 str r0, [r4, #96] +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6639 .loc 1 2770 9 view .LVU2205 + 6640 .LBB7: +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6641 .loc 1 2770 9 view .LVU2206 + 6642 0044 0020 movs r0, #0 + 6643 0046 0090 str r0, [sp] +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6644 .loc 1 2770 9 view .LVU2207 + 6645 0048 D068 ldr r0, [r2, #12] + 6646 004a 0090 str r0, [sp] +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6647 .loc 1 2770 9 view .LVU2208 + 6648 004c 9068 ldr r0, [r2, #8] + 6649 004e 0090 str r0, [sp] +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6650 .loc 1 2770 9 view .LVU2209 + 6651 0050 0098 ldr r0, [sp] + 6652 .LBE7: +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6653 .loc 1 2770 9 view .LVU2210 + 6654 .L455: +2780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6655 .loc 1 2780 5 view .LVU2211 +2780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6656 .loc 1 2780 8 is_stmt 0 view .LVU2212 + 6657 0052 13F0200F tst r3, #32 + 6658 0056 0CD0 beq .L457 +2782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_MODFFLAG(hspi); + 6659 .loc 1 2782 7 is_stmt 1 view .LVU2213 + 6660 0058 206E ldr r0, [r4, #96] + 6661 005a 40F00100 orr r0, r0, #1 + 6662 005e 2066 str r0, [r4, #96] +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6663 .loc 1 2783 7 view .LVU2214 + 6664 .LBB8: +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6665 .loc 1 2783 7 view .LVU2215 + ARM GAS /tmp/ccywxtmH.s page 230 + + + 6666 0060 0020 movs r0, #0 + 6667 0062 0290 str r0, [sp, #8] +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6668 .loc 1 2783 7 view .LVU2216 + 6669 0064 9068 ldr r0, [r2, #8] + 6670 0066 0290 str r0, [sp, #8] +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6671 .loc 1 2783 7 view .LVU2217 + 6672 0068 1068 ldr r0, [r2] + 6673 006a 20F04000 bic r0, r0, #64 + 6674 006e 1060 str r0, [r2] +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6675 .loc 1 2783 7 view .LVU2218 + 6676 0070 029A ldr r2, [sp, #8] + 6677 .L457: +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6678 .loc 1 2783 7 is_stmt 0 view .LVU2219 + 6679 .LBE8: +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6680 .loc 1 2783 7 is_stmt 1 discriminator 1 view .LVU2220 +2787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6681 .loc 1 2787 5 discriminator 1 view .LVU2221 +2787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6682 .loc 1 2787 8 is_stmt 0 discriminator 1 view .LVU2222 + 6683 0072 13F4807F tst r3, #256 + 6684 0076 09D0 beq .L458 +2789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 6685 .loc 1 2789 7 is_stmt 1 view .LVU2223 + 6686 0078 236E ldr r3, [r4, #96] + 6687 .LVL422: +2789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 6688 .loc 1 2789 7 is_stmt 0 view .LVU2224 + 6689 007a 43F00803 orr r3, r3, #8 + 6690 007e 2366 str r3, [r4, #96] +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6691 .loc 1 2790 7 is_stmt 1 view .LVU2225 + 6692 .LBB9: +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6693 .loc 1 2790 7 view .LVU2226 + 6694 0080 0023 movs r3, #0 + 6695 0082 0393 str r3, [sp, #12] +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6696 .loc 1 2790 7 view .LVU2227 + 6697 0084 2368 ldr r3, [r4] + 6698 0086 9B68 ldr r3, [r3, #8] + 6699 0088 0393 str r3, [sp, #12] +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6700 .loc 1 2790 7 view .LVU2228 + 6701 008a 039B ldr r3, [sp, #12] + 6702 .L458: +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6703 .loc 1 2790 7 is_stmt 0 view .LVU2229 + 6704 .LBE9: +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6705 .loc 1 2790 7 is_stmt 1 discriminator 1 view .LVU2230 +2793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6706 .loc 1 2793 5 discriminator 1 view .LVU2231 + ARM GAS /tmp/ccywxtmH.s page 231 + + +2793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6707 .loc 1 2793 13 is_stmt 0 discriminator 1 view .LVU2232 + 6708 008c 236E ldr r3, [r4, #96] +2793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6709 .loc 1 2793 8 discriminator 1 view .LVU2233 + 6710 008e 002B cmp r3, #0 + 6711 0090 32D0 beq .L451 +2796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6712 .loc 1 2796 7 is_stmt 1 view .LVU2234 + 6713 0092 2268 ldr r2, [r4] + 6714 0094 5368 ldr r3, [r2, #4] + 6715 0096 23F0E003 bic r3, r3, #224 + 6716 009a 5360 str r3, [r2, #4] +2798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA requests if enabled */ + 6717 .loc 1 2798 7 view .LVU2235 +2798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA requests if enabled */ + 6718 .loc 1 2798 19 is_stmt 0 view .LVU2236 + 6719 009c 0123 movs r3, #1 + 6720 009e 84F85D30 strb r3, [r4, #93] +2800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6721 .loc 1 2800 7 is_stmt 1 view .LVU2237 +2800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6722 .loc 1 2800 10 is_stmt 0 view .LVU2238 + 6723 00a2 11F0030F tst r1, #3 + 6724 00a6 31D0 beq .L460 +2802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6725 .loc 1 2802 9 is_stmt 1 view .LVU2239 + 6726 00a8 2268 ldr r2, [r4] + 6727 00aa 5368 ldr r3, [r2, #4] + 6728 00ac 23F00303 bic r3, r3, #3 + 6729 00b0 5360 str r3, [r2, #4] +2805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6730 .loc 1 2805 9 view .LVU2240 +2805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6731 .loc 1 2805 17 is_stmt 0 view .LVU2241 + 6732 00b2 A36D ldr r3, [r4, #88] +2805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6733 .loc 1 2805 12 view .LVU2242 + 6734 00b4 4BB1 cbz r3, .L461 +2809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + 6735 .loc 1 2809 11 is_stmt 1 view .LVU2243 +2809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + 6736 .loc 1 2809 43 is_stmt 0 view .LVU2244 + 6737 00b6 174A ldr r2, .L465 + 6738 00b8 5A63 str r2, [r3, #52] +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6739 .loc 1 2810 11 is_stmt 1 view .LVU2245 +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6740 .loc 1 2810 25 is_stmt 0 view .LVU2246 + 6741 00ba A06D ldr r0, [r4, #88] + 6742 00bc FFF7FEFF bl HAL_DMA_Abort_IT + 6743 .LVL423: +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6744 .loc 1 2810 14 view .LVU2247 + 6745 00c0 18B1 cbz r0, .L461 +2812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6746 .loc 1 2812 13 is_stmt 1 view .LVU2248 + ARM GAS /tmp/ccywxtmH.s page 232 + + + 6747 00c2 236E ldr r3, [r4, #96] + 6748 00c4 43F04003 orr r3, r3, #64 + 6749 00c8 2366 str r3, [r4, #96] + 6750 .L461: +2816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6751 .loc 1 2816 9 view .LVU2249 +2816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6752 .loc 1 2816 17 is_stmt 0 view .LVU2250 + 6753 00ca 636D ldr r3, [r4, #84] +2816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6754 .loc 1 2816 12 view .LVU2251 + 6755 00cc A3B1 cbz r3, .L451 +2820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + 6756 .loc 1 2820 11 is_stmt 1 view .LVU2252 +2820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + 6757 .loc 1 2820 43 is_stmt 0 view .LVU2253 + 6758 00ce 114A ldr r2, .L465 + 6759 00d0 5A63 str r2, [r3, #52] +2821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6760 .loc 1 2821 11 is_stmt 1 view .LVU2254 +2821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6761 .loc 1 2821 25 is_stmt 0 view .LVU2255 + 6762 00d2 606D ldr r0, [r4, #84] + 6763 00d4 FFF7FEFF bl HAL_DMA_Abort_IT + 6764 .LVL424: +2821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6765 .loc 1 2821 14 view .LVU2256 + 6766 00d8 70B1 cbz r0, .L451 +2823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6767 .loc 1 2823 13 is_stmt 1 view .LVU2257 + 6768 00da 236E ldr r3, [r4, #96] + 6769 00dc 43F04003 orr r3, r3, #64 + 6770 00e0 2366 str r3, [r4, #96] + 6771 00e2 09E0 b .L451 + 6772 .LVL425: + 6773 .L463: +2747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6774 .loc 1 2747 56 is_stmt 0 view .LVU2258 + 6775 00e4 11F0400F tst r1, #64 + 6776 00e8 94D0 beq .L452 +2749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6777 .loc 1 2749 5 is_stmt 1 view .LVU2259 +2749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6778 .loc 1 2749 9 is_stmt 0 view .LVU2260 + 6779 00ea E36C ldr r3, [r4, #76] + 6780 .LVL426: +2749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6781 .loc 1 2749 5 view .LVU2261 + 6782 00ec 2046 mov r0, r4 + 6783 00ee 9847 blx r3 + 6784 .LVL427: +2750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6785 .loc 1 2750 5 is_stmt 1 view .LVU2262 + 6786 00f0 02E0 b .L451 + 6787 .LVL428: + 6788 .L464: +2756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + ARM GAS /tmp/ccywxtmH.s page 233 + + + 6789 .loc 1 2756 5 view .LVU2263 +2756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6790 .loc 1 2756 9 is_stmt 0 view .LVU2264 + 6791 00f2 236D ldr r3, [r4, #80] + 6792 .LVL429: +2756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6793 .loc 1 2756 5 view .LVU2265 + 6794 00f4 2046 mov r0, r4 + 6795 00f6 9847 blx r3 + 6796 .LVL430: +2757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6797 .loc 1 2757 5 is_stmt 1 view .LVU2266 + 6798 .L451: +2839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6799 .loc 1 2839 1 is_stmt 0 view .LVU2267 + 6800 00f8 04B0 add sp, sp, #16 + 6801 .cfi_remember_state + 6802 .cfi_def_cfa_offset 8 + 6803 @ sp needed + 6804 00fa 10BD pop {r4, pc} + 6805 .LVL431: + 6806 .L456: + 6807 .cfi_restore_state +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6808 .loc 1 2774 9 is_stmt 1 view .LVU2268 + 6809 .LBB10: +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6810 .loc 1 2774 9 view .LVU2269 + 6811 00fc 0023 movs r3, #0 + 6812 .LVL432: +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6813 .loc 1 2774 9 is_stmt 0 view .LVU2270 + 6814 00fe 0193 str r3, [sp, #4] +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6815 .loc 1 2774 9 is_stmt 1 view .LVU2271 + 6816 0100 D368 ldr r3, [r2, #12] + 6817 0102 0193 str r3, [sp, #4] +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6818 .loc 1 2774 9 view .LVU2272 + 6819 0104 9368 ldr r3, [r2, #8] + 6820 0106 0193 str r3, [sp, #4] +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6821 .loc 1 2774 9 view .LVU2273 + 6822 0108 019B ldr r3, [sp, #4] + 6823 .LBE10: +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6824 .loc 1 2774 9 view .LVU2274 +2775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6825 .loc 1 2775 9 view .LVU2275 + 6826 010a F5E7 b .L451 + 6827 .L460: +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6828 .loc 1 2833 9 view .LVU2276 + 6829 010c 2046 mov r0, r4 + 6830 010e FFF7FEFF bl HAL_SPI_ErrorCallback + 6831 .LVL433: +2837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 234 + + + 6832 .loc 1 2837 5 view .LVU2277 + 6833 0112 F1E7 b .L451 + 6834 .L466: + 6835 .align 2 + 6836 .L465: + 6837 0114 00000000 .word SPI_DMAAbortOnError + 6838 .cfi_endproc + 6839 .LFE148: + 6841 .section .text.SPI_DMAAbortOnError,"ax",%progbits + 6842 .align 1 + 6843 .syntax unified + 6844 .thumb + 6845 .thumb_func + 6847 SPI_DMAAbortOnError: + 6848 .LVL434: + 6849 .LFB166: +3385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6850 .loc 1 3385 1 view -0 + 6851 .cfi_startproc + 6852 @ args = 0, pretend = 0, frame = 0 + 6853 @ frame_needed = 0, uses_anonymous_args = 0 +3385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6854 .loc 1 3385 1 is_stmt 0 view .LVU2279 + 6855 0000 08B5 push {r3, lr} + 6856 .cfi_def_cfa_offset 8 + 6857 .cfi_offset 3, -8 + 6858 .cfi_offset 14, -4 +3386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 6859 .loc 1 3386 3 is_stmt 1 view .LVU2280 +3386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 6860 .loc 1 3386 22 is_stmt 0 view .LVU2281 + 6861 0002 406A ldr r0, [r0, #36] + 6862 .LVL435: +3387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 6863 .loc 1 3387 3 is_stmt 1 view .LVU2282 +3387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 6864 .loc 1 3387 21 is_stmt 0 view .LVU2283 + 6865 0004 0023 movs r3, #0 + 6866 0006 A0F84630 strh r3, [r0, #70] @ movhi +3388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6867 .loc 1 3388 3 is_stmt 1 view .LVU2284 +3388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6868 .loc 1 3388 21 is_stmt 0 view .LVU2285 + 6869 000a C387 strh r3, [r0, #62] @ movhi +3394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 6870 .loc 1 3394 3 is_stmt 1 view .LVU2286 + 6871 000c FFF7FEFF bl HAL_SPI_ErrorCallback + 6872 .LVL436: +3396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6873 .loc 1 3396 1 is_stmt 0 view .LVU2287 + 6874 0010 08BD pop {r3, pc} + 6875 .cfi_endproc + 6876 .LFE166: + 6878 .section .text.HAL_SPI_AbortCpltCallback,"ax",%progbits + 6879 .align 1 + 6880 .weak HAL_SPI_AbortCpltCallback + 6881 .syntax unified + ARM GAS /tmp/ccywxtmH.s page 235 + + + 6882 .thumb + 6883 .thumb_func + 6885 HAL_SPI_AbortCpltCallback: + 6886 .LVL437: + 6887 .LFB156: +2962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 6888 .loc 1 2962 1 is_stmt 1 view -0 + 6889 .cfi_startproc + 6890 @ args = 0, pretend = 0, frame = 0 + 6891 @ frame_needed = 0, uses_anonymous_args = 0 + 6892 @ link register save eliminated. +2964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6893 .loc 1 2964 3 view .LVU2289 +2969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6894 .loc 1 2969 1 is_stmt 0 view .LVU2290 + 6895 0000 7047 bx lr + 6896 .cfi_endproc + 6897 .LFE156: + 6899 .section .text.HAL_SPI_Abort_IT,"ax",%progbits + 6900 .align 1 + 6901 .global HAL_SPI_Abort_IT + 6902 .syntax unified + 6903 .thumb + 6904 .thumb_func + 6906 HAL_SPI_Abort_IT: + 6907 .LVL438: + 6908 .LFB144: +2500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode; + 6909 .loc 1 2500 1 is_stmt 1 view -0 + 6910 .cfi_startproc + 6911 @ args = 0, pretend = 0, frame = 16 + 6912 @ frame_needed = 0, uses_anonymous_args = 0 +2500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode; + 6913 .loc 1 2500 1 is_stmt 0 view .LVU2292 + 6914 0000 70B5 push {r4, r5, r6, lr} + 6915 .cfi_def_cfa_offset 16 + 6916 .cfi_offset 4, -16 + 6917 .cfi_offset 5, -12 + 6918 .cfi_offset 6, -8 + 6919 .cfi_offset 14, -4 + 6920 0002 84B0 sub sp, sp, #16 + 6921 .cfi_def_cfa_offset 32 + 6922 0004 0446 mov r4, r0 +2501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t abortcplt ; + 6923 .loc 1 2501 3 is_stmt 1 view .LVU2293 +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; + 6924 .loc 1 2502 3 view .LVU2294 +2503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t resetcount; + 6925 .loc 1 2503 3 view .LVU2295 +2504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6926 .loc 1 2504 3 view .LVU2296 +2507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** abortcplt = 1U; + 6927 .loc 1 2507 3 view .LVU2297 + 6928 .LVL439: +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 6929 .loc 1 2508 3 view .LVU2298 +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + ARM GAS /tmp/ccywxtmH.s page 236 + + + 6930 .loc 1 2509 3 view .LVU2299 +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 6931 .loc 1 2509 61 is_stmt 0 view .LVU2300 + 6932 0006 504B ldr r3, .L496 + 6933 0008 1B68 ldr r3, [r3] + 6934 000a 504A ldr r2, .L496+4 + 6935 000c A2FB0323 umull r2, r3, r2, r3 + 6936 0010 5B0A lsrs r3, r3, #9 +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 6937 .loc 1 2509 36 view .LVU2301 + 6938 0012 6422 movs r2, #100 + 6939 0014 02FB03F3 mul r3, r2, r3 +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 6940 .loc 1 2509 14 view .LVU2302 + 6941 0018 0293 str r3, [sp, #8] +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6942 .loc 1 2510 3 is_stmt 1 view .LVU2303 +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6943 .loc 1 2510 9 is_stmt 0 view .LVU2304 + 6944 001a 029B ldr r3, [sp, #8] + 6945 001c 0393 str r3, [sp, #12] +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 6946 .loc 1 2513 3 is_stmt 1 view .LVU2305 + 6947 001e 0268 ldr r2, [r0] + 6948 0020 5368 ldr r3, [r2, #4] + 6949 0022 23F02003 bic r3, r3, #32 + 6950 0026 5360 str r3, [r2, #4] +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6951 .loc 1 2516 3 view .LVU2306 +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6952 .loc 1 2516 7 is_stmt 0 view .LVU2307 + 6953 0028 0268 ldr r2, [r0] + 6954 002a 5368 ldr r3, [r2, #4] +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6955 .loc 1 2516 6 view .LVU2308 + 6956 002c 13F0800F tst r3, #128 + 6957 0030 12D0 beq .L471 +2518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ + 6958 .loc 1 2518 5 is_stmt 1 view .LVU2309 +2518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ + 6959 .loc 1 2518 17 is_stmt 0 view .LVU2310 + 6960 0032 474B ldr r3, .L496+8 + 6961 0034 0365 str r3, [r0, #80] + 6962 .L474: +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6963 .loc 1 2520 5 is_stmt 1 view .LVU2311 +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6964 .loc 1 2522 7 view .LVU2312 +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6965 .loc 1 2522 17 is_stmt 0 view .LVU2313 + 6966 0036 039B ldr r3, [sp, #12] +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6967 .loc 1 2522 10 view .LVU2314 + 6968 0038 43B1 cbz r3, .L493 +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 6969 .loc 1 2527 7 is_stmt 1 view .LVU2315 +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + ARM GAS /tmp/ccywxtmH.s page 237 + + + 6970 .loc 1 2527 12 is_stmt 0 view .LVU2316 + 6971 003a 039B ldr r3, [sp, #12] + 6972 003c 013B subs r3, r3, #1 + 6973 003e 0393 str r3, [sp, #12] +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 6974 .loc 1 2528 26 is_stmt 1 view .LVU2317 +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 6975 .loc 1 2528 18 is_stmt 0 view .LVU2318 + 6976 0040 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 6977 0044 DBB2 uxtb r3, r3 +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 6978 .loc 1 2528 26 view .LVU2319 + 6979 0046 072B cmp r3, #7 + 6980 0048 F5D1 bne .L474 + 6981 004a 03E0 b .L473 + 6982 .L493: +2524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 6983 .loc 1 2524 9 is_stmt 1 view .LVU2320 + 6984 004c 236E ldr r3, [r4, #96] + 6985 004e 43F04003 orr r3, r3, #64 + 6986 0052 2366 str r3, [r4, #96] +2525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6987 .loc 1 2525 9 view .LVU2321 + 6988 .L473: +2530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6989 .loc 1 2530 5 view .LVU2322 +2530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6990 .loc 1 2530 11 is_stmt 0 view .LVU2323 + 6991 0054 029B ldr r3, [sp, #8] + 6992 0056 0393 str r3, [sp, #12] + 6993 .L471: +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6994 .loc 1 2533 3 is_stmt 1 view .LVU2324 +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6995 .loc 1 2533 7 is_stmt 0 view .LVU2325 + 6996 0058 5368 ldr r3, [r2, #4] +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6997 .loc 1 2533 6 view .LVU2326 + 6998 005a 13F0400F tst r3, #64 + 6999 005e 12D0 beq .L475 +2535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ + 7000 .loc 1 2535 5 is_stmt 1 view .LVU2327 +2535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ + 7001 .loc 1 2535 17 is_stmt 0 view .LVU2328 + 7002 0060 3C4B ldr r3, .L496+12 + 7003 0062 E364 str r3, [r4, #76] + 7004 .L478: +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7005 .loc 1 2537 5 is_stmt 1 view .LVU2329 +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7006 .loc 1 2539 7 view .LVU2330 +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7007 .loc 1 2539 17 is_stmt 0 view .LVU2331 + 7008 0064 039B ldr r3, [sp, #12] +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7009 .loc 1 2539 10 view .LVU2332 + 7010 0066 43B1 cbz r3, .L494 + ARM GAS /tmp/ccywxtmH.s page 238 + + +2544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 7011 .loc 1 2544 7 is_stmt 1 view .LVU2333 +2544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 7012 .loc 1 2544 12 is_stmt 0 view .LVU2334 + 7013 0068 039B ldr r3, [sp, #12] + 7014 006a 013B subs r3, r3, #1 + 7015 006c 0393 str r3, [sp, #12] +2545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 7016 .loc 1 2545 26 is_stmt 1 view .LVU2335 +2545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 7017 .loc 1 2545 18 is_stmt 0 view .LVU2336 + 7018 006e 94F85D30 ldrb r3, [r4, #93] @ zero_extendqisi2 + 7019 0072 DBB2 uxtb r3, r3 +2545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ + 7020 .loc 1 2545 26 view .LVU2337 + 7021 0074 072B cmp r3, #7 + 7022 0076 F5D1 bne .L478 + 7023 0078 03E0 b .L477 + 7024 .L494: +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 7025 .loc 1 2541 9 is_stmt 1 view .LVU2338 + 7026 007a 236E ldr r3, [r4, #96] + 7027 007c 43F04003 orr r3, r3, #64 + 7028 0080 2366 str r3, [r4, #96] +2542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7029 .loc 1 2542 9 view .LVU2339 + 7030 .L477: +2547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7031 .loc 1 2547 5 view .LVU2340 +2547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7032 .loc 1 2547 11 is_stmt 0 view .LVU2341 + 7033 0082 029B ldr r3, [sp, #8] + 7034 0084 0393 str r3, [sp, #12] + 7035 .L475: +2553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7036 .loc 1 2553 3 is_stmt 1 view .LVU2342 +2553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7037 .loc 1 2553 11 is_stmt 0 view .LVU2343 + 7038 0086 636D ldr r3, [r4, #84] +2553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7039 .loc 1 2553 6 view .LVU2344 + 7040 0088 2BB1 cbz r3, .L479 +2557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7041 .loc 1 2557 5 is_stmt 1 view .LVU2345 +2557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7042 .loc 1 2557 9 is_stmt 0 view .LVU2346 + 7043 008a 5268 ldr r2, [r2, #4] +2557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7044 .loc 1 2557 8 view .LVU2347 + 7045 008c 12F0020F tst r2, #2 + 7046 0090 1BD0 beq .L480 +2559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7047 .loc 1 2559 7 is_stmt 1 view .LVU2348 +2559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7048 .loc 1 2559 39 is_stmt 0 view .LVU2349 + 7049 0092 314A ldr r2, .L496+16 + 7050 0094 5A63 str r2, [r3, #52] + ARM GAS /tmp/ccywxtmH.s page 239 + + + 7051 .L479: +2567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7052 .loc 1 2567 3 is_stmt 1 view .LVU2350 +2567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7053 .loc 1 2567 11 is_stmt 0 view .LVU2351 + 7054 0096 A36D ldr r3, [r4, #88] +2567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7055 .loc 1 2567 6 view .LVU2352 + 7056 0098 33B1 cbz r3, .L481 +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7057 .loc 1 2571 5 is_stmt 1 view .LVU2353 +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7058 .loc 1 2571 9 is_stmt 0 view .LVU2354 + 7059 009a 2268 ldr r2, [r4] + 7060 009c 5268 ldr r2, [r2, #4] +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7061 .loc 1 2571 8 view .LVU2355 + 7062 009e 12F0010F tst r2, #1 + 7063 00a2 15D0 beq .L482 +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7064 .loc 1 2573 7 is_stmt 1 view .LVU2356 +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7065 .loc 1 2573 39 is_stmt 0 view .LVU2357 + 7066 00a4 2D4A ldr r2, .L496+20 + 7067 00a6 5A63 str r2, [r3, #52] + 7068 .L481: +2582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7069 .loc 1 2582 3 is_stmt 1 view .LVU2358 +2582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7070 .loc 1 2582 7 is_stmt 0 view .LVU2359 + 7071 00a8 2368 ldr r3, [r4] + 7072 00aa 5B68 ldr r3, [r3, #4] +2582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7073 .loc 1 2582 6 view .LVU2360 + 7074 00ac 13F0020F tst r3, #2 + 7075 00b0 11D0 beq .L487 +2585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7076 .loc 1 2585 5 is_stmt 1 view .LVU2361 +2585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7077 .loc 1 2585 13 is_stmt 0 view .LVU2362 + 7078 00b2 606D ldr r0, [r4, #84] + 7079 .LVL440: +2585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7080 .loc 1 2585 8 view .LVU2363 + 7081 00b4 28B3 cbz r0, .L488 +2588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7082 .loc 1 2588 7 is_stmt 1 view .LVU2364 +2588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7083 .loc 1 2588 11 is_stmt 0 view .LVU2365 + 7084 00b6 FFF7FEFF bl HAL_DMA_Abort_IT + 7085 .LVL441: +2588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7086 .loc 1 2588 10 view .LVU2366 + 7087 00ba 20B3 cbz r0, .L489 +2590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 7088 .loc 1 2590 9 is_stmt 1 view .LVU2367 +2590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + ARM GAS /tmp/ccywxtmH.s page 240 + + + 7089 .loc 1 2590 13 is_stmt 0 view .LVU2368 + 7090 00bc 636D ldr r3, [r4, #84] +2590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 7091 .loc 1 2590 41 view .LVU2369 + 7092 00be 0022 movs r2, #0 + 7093 00c0 5A63 str r2, [r3, #52] +2591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7094 .loc 1 2591 9 is_stmt 1 view .LVU2370 +2591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7095 .loc 1 2591 25 is_stmt 0 view .LVU2371 + 7096 00c2 4023 movs r3, #64 + 7097 00c4 2366 str r3, [r4, #96] +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 7098 .loc 1 2508 13 view .LVU2372 + 7099 00c6 0126 movs r6, #1 + 7100 00c8 06E0 b .L483 + 7101 .LVL442: + 7102 .L480: +2563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7103 .loc 1 2563 7 is_stmt 1 view .LVU2373 +2563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7104 .loc 1 2563 39 is_stmt 0 view .LVU2374 + 7105 00ca 0022 movs r2, #0 + 7106 00cc 5A63 str r2, [r3, #52] + 7107 00ce E2E7 b .L479 + 7108 .L482: +2577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7109 .loc 1 2577 7 is_stmt 1 view .LVU2375 +2577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7110 .loc 1 2577 39 is_stmt 0 view .LVU2376 + 7111 00d0 0022 movs r2, #0 + 7112 00d2 5A63 str r2, [r3, #52] + 7113 00d4 E8E7 b .L481 + 7114 .L487: +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 7115 .loc 1 2508 13 view .LVU2377 + 7116 00d6 0126 movs r6, #1 + 7117 .LVL443: + 7118 .L483: +2600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7119 .loc 1 2600 3 is_stmt 1 view .LVU2378 +2600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7120 .loc 1 2600 7 is_stmt 0 view .LVU2379 + 7121 00d8 2368 ldr r3, [r4] + 7122 00da 5B68 ldr r3, [r3, #4] +2600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7123 .loc 1 2600 6 view .LVU2380 + 7124 00dc 13F0010F tst r3, #1 + 7125 00e0 0AD0 beq .L484 +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7126 .loc 1 2603 5 is_stmt 1 view .LVU2381 +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7127 .loc 1 2603 13 is_stmt 0 view .LVU2382 + 7128 00e2 A06D ldr r0, [r4, #88] +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7129 .loc 1 2603 8 view .LVU2383 + 7130 00e4 40B1 cbz r0, .L484 + ARM GAS /tmp/ccywxtmH.s page 241 + + +2606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7131 .loc 1 2606 7 is_stmt 1 view .LVU2384 +2606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7132 .loc 1 2606 11 is_stmt 0 view .LVU2385 + 7133 00e6 FFF7FEFF bl HAL_DMA_Abort_IT + 7134 .LVL444: +2606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7135 .loc 1 2606 10 view .LVU2386 + 7136 00ea 0546 mov r5, r0 + 7137 00ec 30B1 cbz r0, .L485 +2608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 7138 .loc 1 2608 9 is_stmt 1 view .LVU2387 +2608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 7139 .loc 1 2608 13 is_stmt 0 view .LVU2388 + 7140 00ee A36D ldr r3, [r4, #88] +2608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 7141 .loc 1 2608 41 view .LVU2389 + 7142 00f0 0022 movs r2, #0 + 7143 00f2 5A63 str r2, [r3, #52] +2609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7144 .loc 1 2609 9 is_stmt 1 view .LVU2390 +2609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7145 .loc 1 2609 25 is_stmt 0 view .LVU2391 + 7146 00f4 4023 movs r3, #64 + 7147 00f6 2366 str r3, [r4, #96] + 7148 .L484: +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7149 .loc 1 2618 3 is_stmt 1 view .LVU2392 +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7150 .loc 1 2618 6 is_stmt 0 view .LVU2393 + 7151 00f8 3EB9 cbnz r6, .L495 +2507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** abortcplt = 1U; + 7152 .loc 1 2507 13 view .LVU2394 + 7153 00fa 0025 movs r5, #0 + 7154 .LVL445: + 7155 .L485: +2651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7156 .loc 1 2651 3 is_stmt 1 view .LVU2395 +2652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7157 .loc 1 2652 1 is_stmt 0 view .LVU2396 + 7158 00fc 2846 mov r0, r5 + 7159 00fe 04B0 add sp, sp, #16 + 7160 .cfi_remember_state + 7161 .cfi_def_cfa_offset 16 + 7162 @ sp needed + 7163 0100 70BD pop {r4, r5, r6, pc} + 7164 .LVL446: + 7165 .L488: + 7166 .cfi_restore_state +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 7167 .loc 1 2508 13 view .LVU2397 + 7168 0102 0126 movs r6, #1 + 7169 0104 E8E7 b .L483 + 7170 .L489: +2595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7171 .loc 1 2595 19 view .LVU2398 + 7172 0106 0026 movs r6, #0 + ARM GAS /tmp/ccywxtmH.s page 242 + + + 7173 0108 E6E7 b .L483 + 7174 .LVL447: + 7175 .L495: +2621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 7176 .loc 1 2621 5 is_stmt 1 view .LVU2399 +2621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 7177 .loc 1 2621 23 is_stmt 0 view .LVU2400 + 7178 010a 0023 movs r3, #0 + 7179 010c A4F84630 strh r3, [r4, #70] @ movhi +2622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7180 .loc 1 2622 5 is_stmt 1 view .LVU2401 +2622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7181 .loc 1 2622 23 is_stmt 0 view .LVU2402 + 7182 0110 E387 strh r3, [r4, #62] @ movhi +2625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7183 .loc 1 2625 5 is_stmt 1 view .LVU2403 +2625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7184 .loc 1 2625 13 is_stmt 0 view .LVU2404 + 7185 0112 236E ldr r3, [r4, #96] +2625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7186 .loc 1 2625 8 view .LVU2405 + 7187 0114 402B cmp r3, #64 + 7188 0116 14D0 beq .L491 +2633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7189 .loc 1 2633 7 is_stmt 1 view .LVU2406 +2633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7190 .loc 1 2633 23 is_stmt 0 view .LVU2407 + 7191 0118 0025 movs r5, #0 + 7192 011a 2566 str r5, [r4, #96] + 7193 .L486: + 7194 .LVL448: +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7195 .loc 1 2637 5 is_stmt 1 view .LVU2408 + 7196 .LBB11: +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7197 .loc 1 2637 5 view .LVU2409 + 7198 011c 0022 movs r2, #0 + 7199 011e 0092 str r2, [sp] +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7200 .loc 1 2637 5 view .LVU2410 + 7201 0120 2368 ldr r3, [r4] + 7202 0122 D968 ldr r1, [r3, #12] + 7203 0124 0091 str r1, [sp] +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7204 .loc 1 2637 5 view .LVU2411 + 7205 0126 9968 ldr r1, [r3, #8] + 7206 0128 0091 str r1, [sp] +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7207 .loc 1 2637 5 view .LVU2412 + 7208 012a 0099 ldr r1, [sp] + 7209 .LBE11: +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7210 .loc 1 2637 5 view .LVU2413 +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7211 .loc 1 2638 5 view .LVU2414 + 7212 .LBB12: +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccywxtmH.s page 243 + + + 7213 .loc 1 2638 5 view .LVU2415 + 7214 012c 0192 str r2, [sp, #4] +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7215 .loc 1 2638 5 view .LVU2416 + 7216 012e 9B68 ldr r3, [r3, #8] + 7217 0130 0193 str r3, [sp, #4] +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7218 .loc 1 2638 5 view .LVU2417 + 7219 0132 019B ldr r3, [sp, #4] + 7220 .LBE12: +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7221 .loc 1 2638 5 view .LVU2418 +2641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7222 .loc 1 2641 5 view .LVU2419 +2641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7223 .loc 1 2641 17 is_stmt 0 view .LVU2420 + 7224 0134 0123 movs r3, #1 + 7225 0136 84F85D30 strb r3, [r4, #93] +2647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 7226 .loc 1 2647 5 is_stmt 1 view .LVU2421 + 7227 013a 2046 mov r0, r4 + 7228 013c FFF7FEFF bl HAL_SPI_AbortCpltCallback + 7229 .LVL449: + 7230 0140 DCE7 b .L485 + 7231 .LVL450: + 7232 .L491: +2628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7233 .loc 1 2628 17 is_stmt 0 view .LVU2422 + 7234 0142 0125 movs r5, #1 + 7235 0144 EAE7 b .L486 + 7236 .L497: + 7237 0146 00BF .align 2 + 7238 .L496: + 7239 0148 00000000 .word SystemCoreClock + 7240 014c F1197605 .word 91625969 + 7241 0150 00000000 .word SPI_AbortTx_ISR + 7242 0154 00000000 .word SPI_AbortRx_ISR + 7243 0158 00000000 .word SPI_DMATxAbortCallback + 7244 015c 00000000 .word SPI_DMARxAbortCallback + 7245 .cfi_endproc + 7246 .LFE144: + 7248 .section .text.SPI_DMARxAbortCallback,"ax",%progbits + 7249 .align 1 + 7250 .syntax unified + 7251 .thumb + 7252 .thumb_func + 7254 SPI_DMARxAbortCallback: + 7255 .LVL451: + 7256 .LFB168: +3473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 7257 .loc 1 3473 1 is_stmt 1 view -0 + 7258 .cfi_startproc + 7259 @ args = 0, pretend = 0, frame = 8 + 7260 @ frame_needed = 0, uses_anonymous_args = 0 +3473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 7261 .loc 1 3473 1 is_stmt 0 view .LVU2424 + 7262 0000 30B5 push {r4, r5, lr} + ARM GAS /tmp/ccywxtmH.s page 244 + + + 7263 .cfi_def_cfa_offset 12 + 7264 .cfi_offset 4, -12 + 7265 .cfi_offset 5, -8 + 7266 .cfi_offset 14, -4 + 7267 0002 85B0 sub sp, sp, #20 + 7268 .cfi_def_cfa_offset 32 +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7269 .loc 1 3474 3 is_stmt 1 view .LVU2425 +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7270 .loc 1 3474 22 is_stmt 0 view .LVU2426 + 7271 0004 446A ldr r4, [r0, #36] + 7272 .LVL452: +3477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7273 .loc 1 3477 3 is_stmt 1 view .LVU2427 + 7274 0006 2268 ldr r2, [r4] + 7275 0008 1368 ldr r3, [r2] + 7276 000a 23F04003 bic r3, r3, #64 + 7277 000e 1360 str r3, [r2] +3479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7278 .loc 1 3479 3 view .LVU2428 +3479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7279 .loc 1 3479 7 is_stmt 0 view .LVU2429 + 7280 0010 A36D ldr r3, [r4, #88] +3479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7281 .loc 1 3479 35 view .LVU2430 + 7282 0012 0025 movs r5, #0 + 7283 0014 5D63 str r5, [r3, #52] +3482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7284 .loc 1 3482 3 is_stmt 1 view .LVU2431 + 7285 0016 2268 ldr r2, [r4] + 7286 0018 5368 ldr r3, [r2, #4] + 7287 001a 23F00103 bic r3, r3, #1 + 7288 001e 5360 str r3, [r2, #4] +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7289 .loc 1 3485 3 view .LVU2432 +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7290 .loc 1 3485 7 is_stmt 0 view .LVU2433 + 7291 0020 FFF7FEFF bl HAL_GetTick + 7292 .LVL453: +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7293 .loc 1 3485 7 view .LVU2434 + 7294 0024 0090 str r0, [sp] + 7295 0026 6423 movs r3, #100 + 7296 0028 2A46 mov r2, r5 + 7297 002a 8021 movs r1, #128 + 7298 002c 2046 mov r0, r4 + 7299 002e FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 7300 .LVL454: +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7301 .loc 1 3485 6 view .LVU2435 + 7302 0032 08B1 cbz r0, .L499 +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7303 .loc 1 3487 5 is_stmt 1 view .LVU2436 +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7304 .loc 1 3487 21 is_stmt 0 view .LVU2437 + 7305 0034 4023 movs r3, #64 + 7306 0036 2366 str r3, [r4, #96] + ARM GAS /tmp/ccywxtmH.s page 245 + + + 7307 .L499: +3491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7308 .loc 1 3491 3 is_stmt 1 view .LVU2438 +3491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7309 .loc 1 3491 7 is_stmt 0 view .LVU2439 + 7310 0038 FFF7FEFF bl HAL_GetTick + 7311 .LVL455: + 7312 003c 0090 str r0, [sp] + 7313 003e 6423 movs r3, #100 + 7314 0040 0022 movs r2, #0 + 7315 0042 4FF4C061 mov r1, #1536 + 7316 0046 2046 mov r0, r4 + 7317 0048 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 7318 .LVL456: +3491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7319 .loc 1 3491 6 view .LVU2440 + 7320 004c 08B1 cbz r0, .L500 +3493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7321 .loc 1 3493 5 is_stmt 1 view .LVU2441 +3493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7322 .loc 1 3493 21 is_stmt 0 view .LVU2442 + 7323 004e 4023 movs r3, #64 + 7324 0050 2366 str r3, [r4, #96] + 7325 .L500: +3497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7326 .loc 1 3497 3 is_stmt 1 view .LVU2443 +3497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7327 .loc 1 3497 11 is_stmt 0 view .LVU2444 + 7328 0052 636D ldr r3, [r4, #84] +3497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7329 .loc 1 3497 6 view .LVU2445 + 7330 0054 0BB1 cbz r3, .L501 +3499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7331 .loc 1 3499 5 is_stmt 1 view .LVU2446 +3499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7332 .loc 1 3499 21 is_stmt 0 view .LVU2447 + 7333 0056 5B6B ldr r3, [r3, #52] +3499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7334 .loc 1 3499 8 view .LVU2448 + 7335 0058 D3B9 cbnz r3, .L498 + 7336 .L501: +3506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 7337 .loc 1 3506 3 is_stmt 1 view .LVU2449 +3506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 7338 .loc 1 3506 21 is_stmt 0 view .LVU2450 + 7339 005a 0023 movs r3, #0 + 7340 005c A4F84630 strh r3, [r4, #70] @ movhi +3507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7341 .loc 1 3507 3 is_stmt 1 view .LVU2451 +3507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7342 .loc 1 3507 21 is_stmt 0 view .LVU2452 + 7343 0060 E387 strh r3, [r4, #62] @ movhi +3510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7344 .loc 1 3510 3 is_stmt 1 view .LVU2453 +3510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7345 .loc 1 3510 11 is_stmt 0 view .LVU2454 + 7346 0062 236E ldr r3, [r4, #96] + ARM GAS /tmp/ccywxtmH.s page 246 + + +3510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7347 .loc 1 3510 6 view .LVU2455 + 7348 0064 402B cmp r3, #64 + 7349 0066 01D0 beq .L503 +3513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7350 .loc 1 3513 5 is_stmt 1 view .LVU2456 +3513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7351 .loc 1 3513 21 is_stmt 0 view .LVU2457 + 7352 0068 0023 movs r3, #0 + 7353 006a 2366 str r3, [r4, #96] + 7354 .L503: +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7355 .loc 1 3517 3 is_stmt 1 view .LVU2458 + 7356 .LBB13: +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7357 .loc 1 3517 3 view .LVU2459 + 7358 006c 0022 movs r2, #0 + 7359 006e 0292 str r2, [sp, #8] +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7360 .loc 1 3517 3 view .LVU2460 + 7361 0070 2368 ldr r3, [r4] + 7362 0072 D968 ldr r1, [r3, #12] + 7363 0074 0291 str r1, [sp, #8] +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7364 .loc 1 3517 3 view .LVU2461 + 7365 0076 9968 ldr r1, [r3, #8] + 7366 0078 0291 str r1, [sp, #8] +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7367 .loc 1 3517 3 view .LVU2462 + 7368 007a 0299 ldr r1, [sp, #8] + 7369 .LBE13: +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7370 .loc 1 3517 3 view .LVU2463 +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7371 .loc 1 3518 3 view .LVU2464 + 7372 .LBB14: +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7373 .loc 1 3518 3 view .LVU2465 + 7374 007c 0392 str r2, [sp, #12] +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7375 .loc 1 3518 3 view .LVU2466 + 7376 007e 9B68 ldr r3, [r3, #8] + 7377 0080 0393 str r3, [sp, #12] +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7378 .loc 1 3518 3 view .LVU2467 + 7379 0082 039B ldr r3, [sp, #12] + 7380 .LBE14: +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7381 .loc 1 3518 3 view .LVU2468 +3521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7382 .loc 1 3521 3 view .LVU2469 +3521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7383 .loc 1 3521 16 is_stmt 0 view .LVU2470 + 7384 0084 0123 movs r3, #1 + 7385 0086 84F85D30 strb r3, [r4, #93] +3527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 7386 .loc 1 3527 3 is_stmt 1 view .LVU2471 + ARM GAS /tmp/ccywxtmH.s page 247 + + + 7387 008a 2046 mov r0, r4 + 7388 008c FFF7FEFF bl HAL_SPI_AbortCpltCallback + 7389 .LVL457: + 7390 .L498: +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7391 .loc 1 3529 1 is_stmt 0 view .LVU2472 + 7392 0090 05B0 add sp, sp, #20 + 7393 .cfi_def_cfa_offset 12 + 7394 @ sp needed + 7395 0092 30BD pop {r4, r5, pc} +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7396 .loc 1 3529 1 view .LVU2473 + 7397 .cfi_endproc + 7398 .LFE168: + 7400 .section .text.SPI_DMATxAbortCallback,"ax",%progbits + 7401 .align 1 + 7402 .syntax unified + 7403 .thumb + 7404 .thumb_func + 7406 SPI_DMATxAbortCallback: + 7407 .LVL458: + 7408 .LFB167: +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 7409 .loc 1 3407 1 is_stmt 1 view -0 + 7410 .cfi_startproc + 7411 @ args = 0, pretend = 0, frame = 8 + 7412 @ frame_needed = 0, uses_anonymous_args = 0 +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 7413 .loc 1 3407 1 is_stmt 0 view .LVU2475 + 7414 0000 10B5 push {r4, lr} + 7415 .cfi_def_cfa_offset 8 + 7416 .cfi_offset 4, -8 + 7417 .cfi_offset 14, -4 + 7418 0002 84B0 sub sp, sp, #16 + 7419 .cfi_def_cfa_offset 24 +3408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7420 .loc 1 3408 3 is_stmt 1 view .LVU2476 +3408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7421 .loc 1 3408 22 is_stmt 0 view .LVU2477 + 7422 0004 446A ldr r4, [r0, #36] + 7423 .LVL459: +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7424 .loc 1 3410 3 is_stmt 1 view .LVU2478 +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7425 .loc 1 3410 7 is_stmt 0 view .LVU2479 + 7426 0006 636D ldr r3, [r4, #84] +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7427 .loc 1 3410 35 view .LVU2480 + 7428 0008 0022 movs r2, #0 + 7429 000a 5A63 str r2, [r3, #52] +3413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7430 .loc 1 3413 3 is_stmt 1 view .LVU2481 + 7431 000c 2268 ldr r2, [r4] + 7432 000e 5368 ldr r3, [r2, #4] + 7433 0010 23F00203 bic r3, r3, #2 + 7434 0014 5360 str r3, [r2, #4] +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 248 + + + 7435 .loc 1 3415 3 view .LVU2482 +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7436 .loc 1 3415 7 is_stmt 0 view .LVU2483 + 7437 0016 FFF7FEFF bl HAL_GetTick + 7438 .LVL460: +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7439 .loc 1 3415 7 view .LVU2484 + 7440 001a 0246 mov r2, r0 + 7441 001c 6421 movs r1, #100 + 7442 001e 2046 mov r0, r4 + 7443 0020 FFF7FEFF bl SPI_EndRxTxTransaction + 7444 .LVL461: +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7445 .loc 1 3415 6 view .LVU2485 + 7446 0024 08B1 cbz r0, .L506 +3417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7447 .loc 1 3417 5 is_stmt 1 view .LVU2486 +3417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7448 .loc 1 3417 21 is_stmt 0 view .LVU2487 + 7449 0026 4023 movs r3, #64 + 7450 0028 2366 str r3, [r4, #96] + 7451 .L506: +3421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7452 .loc 1 3421 3 is_stmt 1 view .LVU2488 + 7453 002a 2268 ldr r2, [r4] + 7454 002c 1368 ldr r3, [r2] + 7455 002e 23F04003 bic r3, r3, #64 + 7456 0032 1360 str r3, [r2] +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7457 .loc 1 3424 3 view .LVU2489 +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7458 .loc 1 3424 7 is_stmt 0 view .LVU2490 + 7459 0034 FFF7FEFF bl HAL_GetTick + 7460 .LVL462: + 7461 0038 0090 str r0, [sp] + 7462 003a 6423 movs r3, #100 + 7463 003c 0022 movs r2, #0 + 7464 003e 4FF4C061 mov r1, #1536 + 7465 0042 2046 mov r0, r4 + 7466 0044 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 7467 .LVL463: +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7468 .loc 1 3424 6 view .LVU2491 + 7469 0048 08B1 cbz r0, .L507 +3426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7470 .loc 1 3426 5 is_stmt 1 view .LVU2492 +3426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7471 .loc 1 3426 21 is_stmt 0 view .LVU2493 + 7472 004a 4023 movs r3, #64 + 7473 004c 2366 str r3, [r4, #96] + 7474 .L507: +3430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7475 .loc 1 3430 3 is_stmt 1 view .LVU2494 +3430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7476 .loc 1 3430 11 is_stmt 0 view .LVU2495 + 7477 004e A36D ldr r3, [r4, #88] +3430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccywxtmH.s page 249 + + + 7478 .loc 1 3430 6 view .LVU2496 + 7479 0050 0BB1 cbz r3, .L508 +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7480 .loc 1 3432 5 is_stmt 1 view .LVU2497 +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7481 .loc 1 3432 21 is_stmt 0 view .LVU2498 + 7482 0052 5B6B ldr r3, [r3, #52] +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7483 .loc 1 3432 8 view .LVU2499 + 7484 0054 D3B9 cbnz r3, .L505 + 7485 .L508: +3439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 7486 .loc 1 3439 3 is_stmt 1 view .LVU2500 +3439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 7487 .loc 1 3439 21 is_stmt 0 view .LVU2501 + 7488 0056 0023 movs r3, #0 + 7489 0058 A4F84630 strh r3, [r4, #70] @ movhi +3440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7490 .loc 1 3440 3 is_stmt 1 view .LVU2502 +3440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7491 .loc 1 3440 21 is_stmt 0 view .LVU2503 + 7492 005c E387 strh r3, [r4, #62] @ movhi +3443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7493 .loc 1 3443 3 is_stmt 1 view .LVU2504 +3443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7494 .loc 1 3443 11 is_stmt 0 view .LVU2505 + 7495 005e 236E ldr r3, [r4, #96] +3443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7496 .loc 1 3443 6 view .LVU2506 + 7497 0060 402B cmp r3, #64 + 7498 0062 01D0 beq .L510 +3446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7499 .loc 1 3446 5 is_stmt 1 view .LVU2507 +3446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7500 .loc 1 3446 21 is_stmt 0 view .LVU2508 + 7501 0064 0023 movs r3, #0 + 7502 0066 2366 str r3, [r4, #96] + 7503 .L510: +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7504 .loc 1 3450 3 is_stmt 1 view .LVU2509 + 7505 .LBB15: +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7506 .loc 1 3450 3 view .LVU2510 + 7507 0068 0022 movs r2, #0 + 7508 006a 0292 str r2, [sp, #8] +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7509 .loc 1 3450 3 view .LVU2511 + 7510 006c 2368 ldr r3, [r4] + 7511 006e D968 ldr r1, [r3, #12] + 7512 0070 0291 str r1, [sp, #8] +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7513 .loc 1 3450 3 view .LVU2512 + 7514 0072 9968 ldr r1, [r3, #8] + 7515 0074 0291 str r1, [sp, #8] +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7516 .loc 1 3450 3 view .LVU2513 + 7517 0076 0299 ldr r1, [sp, #8] + ARM GAS /tmp/ccywxtmH.s page 250 + + + 7518 .LBE15: +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 7519 .loc 1 3450 3 view .LVU2514 +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7520 .loc 1 3451 3 view .LVU2515 + 7521 .LBB16: +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7522 .loc 1 3451 3 view .LVU2516 + 7523 0078 0392 str r2, [sp, #12] +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7524 .loc 1 3451 3 view .LVU2517 + 7525 007a 9B68 ldr r3, [r3, #8] + 7526 007c 0393 str r3, [sp, #12] +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7527 .loc 1 3451 3 view .LVU2518 + 7528 007e 039B ldr r3, [sp, #12] + 7529 .LBE16: +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7530 .loc 1 3451 3 view .LVU2519 +3454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7531 .loc 1 3454 3 view .LVU2520 +3454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7532 .loc 1 3454 16 is_stmt 0 view .LVU2521 + 7533 0080 0123 movs r3, #1 + 7534 0082 84F85D30 strb r3, [r4, #93] +3460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 7535 .loc 1 3460 3 is_stmt 1 view .LVU2522 + 7536 0086 2046 mov r0, r4 + 7537 0088 FFF7FEFF bl HAL_SPI_AbortCpltCallback + 7538 .LVL464: + 7539 .L505: +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7540 .loc 1 3462 1 is_stmt 0 view .LVU2523 + 7541 008c 04B0 add sp, sp, #16 + 7542 .cfi_def_cfa_offset 8 + 7543 @ sp needed + 7544 008e 10BD pop {r4, pc} +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7545 .loc 1 3462 1 view .LVU2524 + 7546 .cfi_endproc + 7547 .LFE167: + 7549 .section .text.HAL_SPI_GetState,"ax",%progbits + 7550 .align 1 + 7551 .global HAL_SPI_GetState + 7552 .syntax unified + 7553 .thumb + 7554 .thumb_func + 7556 HAL_SPI_GetState: + 7557 .LVL465: + 7558 .LFB157: +2997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return SPI handle state */ + 7559 .loc 1 2997 1 is_stmt 1 view -0 + 7560 .cfi_startproc + 7561 @ args = 0, pretend = 0, frame = 0 + 7562 @ frame_needed = 0, uses_anonymous_args = 0 + 7563 @ link register save eliminated. +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccywxtmH.s page 251 + + + 7564 .loc 1 2999 3 view .LVU2526 +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7565 .loc 1 2999 14 is_stmt 0 view .LVU2527 + 7566 0000 90F85D00 ldrb r0, [r0, #93] @ zero_extendqisi2 + 7567 .LVL466: +3000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7568 .loc 1 3000 1 view .LVU2528 + 7569 0004 7047 bx lr + 7570 .cfi_endproc + 7571 .LFE157: + 7573 .section .text.HAL_SPI_GetError,"ax",%progbits + 7574 .align 1 + 7575 .global HAL_SPI_GetError + 7576 .syntax unified + 7577 .thumb + 7578 .thumb_func + 7580 HAL_SPI_GetError: + 7581 .LVL467: + 7582 .LFB158: +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return SPI ErrorCode */ + 7583 .loc 1 3009 1 is_stmt 1 view -0 + 7584 .cfi_startproc + 7585 @ args = 0, pretend = 0, frame = 0 + 7586 @ frame_needed = 0, uses_anonymous_args = 0 + 7587 @ link register save eliminated. +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7588 .loc 1 3011 3 view .LVU2530 +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7589 .loc 1 3011 14 is_stmt 0 view .LVU2531 + 7590 0000 006E ldr r0, [r0, #96] + 7591 .LVL468: +3012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 7592 .loc 1 3012 1 view .LVU2532 + 7593 0002 7047 bx lr + 7594 .cfi_endproc + 7595 .LFE158: + 7597 .text + 7598 .Letext0: + 7599 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 7600 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 7601 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 7602 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 7603 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 7604 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 7605 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 7606 .file 9 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + 7607 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccywxtmH.s page 252 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_spi.c + /tmp/ccywxtmH.s:21 .text.SPI_WaitFlagStateUntilTimeout:0000000000000000 $t + /tmp/ccywxtmH.s:26 .text.SPI_WaitFlagStateUntilTimeout:0000000000000000 SPI_WaitFlagStateUntilTimeout + /tmp/ccywxtmH.s:200 .text.SPI_WaitFlagStateUntilTimeout:00000000000000c4 $d + /tmp/ccywxtmH.s:205 .text.SPI_WaitFifoStateUntilTimeout:0000000000000000 $t + /tmp/ccywxtmH.s:210 .text.SPI_WaitFifoStateUntilTimeout:0000000000000000 SPI_WaitFifoStateUntilTimeout + /tmp/ccywxtmH.s:415 .text.SPI_WaitFifoStateUntilTimeout:00000000000000ec $d + /tmp/ccywxtmH.s:420 .text.SPI_EndRxTxTransaction:0000000000000000 $t + /tmp/ccywxtmH.s:425 .text.SPI_EndRxTxTransaction:0000000000000000 SPI_EndRxTxTransaction + /tmp/ccywxtmH.s:518 .text.SPI_EndRxTransaction:0000000000000000 $t + /tmp/ccywxtmH.s:523 .text.SPI_EndRxTransaction:0000000000000000 SPI_EndRxTransaction + /tmp/ccywxtmH.s:642 .text.SPI_AbortRx_ISR:0000000000000000 $t + /tmp/ccywxtmH.s:647 .text.SPI_AbortRx_ISR:0000000000000000 SPI_AbortRx_ISR + /tmp/ccywxtmH.s:761 .text.SPI_AbortRx_ISR:0000000000000088 $d + /tmp/ccywxtmH.s:767 .text.SPI_AbortTx_ISR:0000000000000000 $t + /tmp/ccywxtmH.s:772 .text.SPI_AbortTx_ISR:0000000000000000 SPI_AbortTx_ISR + /tmp/ccywxtmH.s:956 .text.SPI_AbortTx_ISR:00000000000000e8 $d + /tmp/ccywxtmH.s:962 .text.HAL_SPI_MspInit:0000000000000000 $t + /tmp/ccywxtmH.s:968 .text.HAL_SPI_MspInit:0000000000000000 HAL_SPI_MspInit + /tmp/ccywxtmH.s:983 .text.HAL_SPI_Init:0000000000000000 $t + /tmp/ccywxtmH.s:989 .text.HAL_SPI_Init:0000000000000000 HAL_SPI_Init + /tmp/ccywxtmH.s:1176 .text.HAL_SPI_MspDeInit:0000000000000000 $t + /tmp/ccywxtmH.s:1182 .text.HAL_SPI_MspDeInit:0000000000000000 HAL_SPI_MspDeInit + /tmp/ccywxtmH.s:1197 .text.HAL_SPI_DeInit:0000000000000000 $t + /tmp/ccywxtmH.s:1203 .text.HAL_SPI_DeInit:0000000000000000 HAL_SPI_DeInit + /tmp/ccywxtmH.s:1260 .text.HAL_SPI_Transmit:0000000000000000 $t + /tmp/ccywxtmH.s:1266 .text.HAL_SPI_Transmit:0000000000000000 HAL_SPI_Transmit + /tmp/ccywxtmH.s:1730 .text.HAL_SPI_TransmitReceive:0000000000000000 $t + /tmp/ccywxtmH.s:1736 .text.HAL_SPI_TransmitReceive:0000000000000000 HAL_SPI_TransmitReceive + /tmp/ccywxtmH.s:2436 .text.HAL_SPI_Receive:0000000000000000 $t + /tmp/ccywxtmH.s:2442 .text.HAL_SPI_Receive:0000000000000000 HAL_SPI_Receive + /tmp/ccywxtmH.s:2804 .text.HAL_SPI_Transmit_IT:0000000000000000 $t + /tmp/ccywxtmH.s:2810 .text.HAL_SPI_Transmit_IT:0000000000000000 HAL_SPI_Transmit_IT + /tmp/ccywxtmH.s:2975 .text.HAL_SPI_Transmit_IT:00000000000000a8 $d + /tmp/ccywxtmH.s:5482 .text.SPI_TxISR_16BIT:0000000000000000 SPI_TxISR_16BIT + /tmp/ccywxtmH.s:5421 .text.SPI_TxISR_8BIT:0000000000000000 SPI_TxISR_8BIT + /tmp/ccywxtmH.s:2981 .text.HAL_SPI_TransmitReceive_IT:0000000000000000 $t + /tmp/ccywxtmH.s:2987 .text.HAL_SPI_TransmitReceive_IT:0000000000000000 HAL_SPI_TransmitReceive_IT + /tmp/ccywxtmH.s:3238 .text.HAL_SPI_TransmitReceive_IT:0000000000000104 $d + /tmp/ccywxtmH.s:6122 .text.SPI_2linesRxISR_16BIT:0000000000000000 SPI_2linesRxISR_16BIT + /tmp/ccywxtmH.s:6050 .text.SPI_2linesTxISR_16BIT:0000000000000000 SPI_2linesTxISR_16BIT + /tmp/ccywxtmH.s:5933 .text.SPI_2linesRxISR_8BIT:0000000000000000 SPI_2linesRxISR_8BIT + /tmp/ccywxtmH.s:5828 .text.SPI_2linesTxISR_8BIT:0000000000000000 SPI_2linesTxISR_8BIT + /tmp/ccywxtmH.s:3246 .text.HAL_SPI_Receive_IT:0000000000000000 $t + /tmp/ccywxtmH.s:3252 .text.HAL_SPI_Receive_IT:0000000000000000 HAL_SPI_Receive_IT + /tmp/ccywxtmH.s:3452 .text.HAL_SPI_Receive_IT:00000000000000f4 $d + /tmp/ccywxtmH.s:5672 .text.SPI_RxISR_16BIT:0000000000000000 SPI_RxISR_16BIT + /tmp/ccywxtmH.s:5611 .text.SPI_RxISR_8BIT:0000000000000000 SPI_RxISR_8BIT + /tmp/ccywxtmH.s:3458 .text.HAL_SPI_Transmit_DMA:0000000000000000 $t + /tmp/ccywxtmH.s:3464 .text.HAL_SPI_Transmit_DMA:0000000000000000 HAL_SPI_Transmit_DMA + /tmp/ccywxtmH.s:3724 .text.HAL_SPI_Transmit_DMA:0000000000000128 $d + /tmp/ccywxtmH.s:5163 .text.SPI_DMAHalfTransmitCplt:0000000000000000 SPI_DMAHalfTransmitCplt + /tmp/ccywxtmH.s:6237 .text.SPI_DMATransmitCplt:0000000000000000 SPI_DMATransmitCplt + /tmp/ccywxtmH.s:6194 .text.SPI_DMAError:0000000000000000 SPI_DMAError + /tmp/ccywxtmH.s:3731 .text.HAL_SPI_TransmitReceive_DMA:0000000000000000 $t + /tmp/ccywxtmH.s:3737 .text.HAL_SPI_TransmitReceive_DMA:0000000000000000 HAL_SPI_TransmitReceive_DMA + ARM GAS /tmp/ccywxtmH.s page 253 + + + /tmp/ccywxtmH.s:4196 .text.HAL_SPI_TransmitReceive_DMA:0000000000000218 $d + /tmp/ccywxtmH.s:5267 .text.SPI_DMAHalfTransmitReceiveCplt:0000000000000000 SPI_DMAHalfTransmitReceiveCplt + /tmp/ccywxtmH.s:6476 .text.SPI_DMATransmitReceiveCplt:0000000000000000 SPI_DMATransmitReceiveCplt + /tmp/ccywxtmH.s:5215 .text.SPI_DMAHalfReceiveCplt:0000000000000000 SPI_DMAHalfReceiveCplt + /tmp/ccywxtmH.s:6360 .text.SPI_DMAReceiveCplt:0000000000000000 SPI_DMAReceiveCplt + /tmp/ccywxtmH.s:4205 .text.HAL_SPI_Receive_DMA:0000000000000000 $t + /tmp/ccywxtmH.s:4211 .text.HAL_SPI_Receive_DMA:0000000000000000 HAL_SPI_Receive_DMA + /tmp/ccywxtmH.s:4523 .text.HAL_SPI_Receive_DMA:0000000000000188 $d + /tmp/ccywxtmH.s:4530 .text.HAL_SPI_Abort:0000000000000000 $t + /tmp/ccywxtmH.s:4536 .text.HAL_SPI_Abort:0000000000000000 HAL_SPI_Abort + /tmp/ccywxtmH.s:4876 .text.HAL_SPI_Abort:0000000000000180 $d + /tmp/ccywxtmH.s:4884 .text.HAL_SPI_DMAPause:0000000000000000 $t + /tmp/ccywxtmH.s:4890 .text.HAL_SPI_DMAPause:0000000000000000 HAL_SPI_DMAPause + /tmp/ccywxtmH.s:4934 .text.HAL_SPI_DMAResume:0000000000000000 $t + /tmp/ccywxtmH.s:4940 .text.HAL_SPI_DMAResume:0000000000000000 HAL_SPI_DMAResume + /tmp/ccywxtmH.s:4984 .text.HAL_SPI_DMAStop:0000000000000000 $t + /tmp/ccywxtmH.s:4990 .text.HAL_SPI_DMAStop:0000000000000000 HAL_SPI_DMAStop + /tmp/ccywxtmH.s:5074 .text.HAL_SPI_TxCpltCallback:0000000000000000 $t + /tmp/ccywxtmH.s:5080 .text.HAL_SPI_TxCpltCallback:0000000000000000 HAL_SPI_TxCpltCallback + /tmp/ccywxtmH.s:5095 .text.HAL_SPI_RxCpltCallback:0000000000000000 $t + /tmp/ccywxtmH.s:5101 .text.HAL_SPI_RxCpltCallback:0000000000000000 HAL_SPI_RxCpltCallback + /tmp/ccywxtmH.s:5116 .text.HAL_SPI_TxRxCpltCallback:0000000000000000 $t + /tmp/ccywxtmH.s:5122 .text.HAL_SPI_TxRxCpltCallback:0000000000000000 HAL_SPI_TxRxCpltCallback + /tmp/ccywxtmH.s:5137 .text.HAL_SPI_TxHalfCpltCallback:0000000000000000 $t + /tmp/ccywxtmH.s:5143 .text.HAL_SPI_TxHalfCpltCallback:0000000000000000 HAL_SPI_TxHalfCpltCallback + /tmp/ccywxtmH.s:5158 .text.SPI_DMAHalfTransmitCplt:0000000000000000 $t + /tmp/ccywxtmH.s:5189 .text.HAL_SPI_RxHalfCpltCallback:0000000000000000 $t + /tmp/ccywxtmH.s:5195 .text.HAL_SPI_RxHalfCpltCallback:0000000000000000 HAL_SPI_RxHalfCpltCallback + /tmp/ccywxtmH.s:5210 .text.SPI_DMAHalfReceiveCplt:0000000000000000 $t + /tmp/ccywxtmH.s:5241 .text.HAL_SPI_TxRxHalfCpltCallback:0000000000000000 $t + /tmp/ccywxtmH.s:5247 .text.HAL_SPI_TxRxHalfCpltCallback:0000000000000000 HAL_SPI_TxRxHalfCpltCallback + /tmp/ccywxtmH.s:5262 .text.SPI_DMAHalfTransmitReceiveCplt:0000000000000000 $t + /tmp/ccywxtmH.s:5293 .text.HAL_SPI_ErrorCallback:0000000000000000 $t + /tmp/ccywxtmH.s:5299 .text.HAL_SPI_ErrorCallback:0000000000000000 HAL_SPI_ErrorCallback + /tmp/ccywxtmH.s:5314 .text.SPI_CloseTx_ISR:0000000000000000 $t + /tmp/ccywxtmH.s:5319 .text.SPI_CloseTx_ISR:0000000000000000 SPI_CloseTx_ISR + /tmp/ccywxtmH.s:5416 .text.SPI_TxISR_8BIT:0000000000000000 $t + /tmp/ccywxtmH.s:5477 .text.SPI_TxISR_16BIT:0000000000000000 $t + /tmp/ccywxtmH.s:5538 .text.SPI_CloseRx_ISR:0000000000000000 $t + /tmp/ccywxtmH.s:5543 .text.SPI_CloseRx_ISR:0000000000000000 SPI_CloseRx_ISR + /tmp/ccywxtmH.s:5606 .text.SPI_RxISR_8BIT:0000000000000000 $t + /tmp/ccywxtmH.s:5667 .text.SPI_RxISR_16BIT:0000000000000000 $t + /tmp/ccywxtmH.s:5728 .text.SPI_CloseRxTx_ISR:0000000000000000 $t + /tmp/ccywxtmH.s:5733 .text.SPI_CloseRxTx_ISR:0000000000000000 SPI_CloseRxTx_ISR + /tmp/ccywxtmH.s:5823 .text.SPI_2linesTxISR_8BIT:0000000000000000 $t + /tmp/ccywxtmH.s:5928 .text.SPI_2linesRxISR_8BIT:0000000000000000 $t + /tmp/ccywxtmH.s:6045 .text.SPI_2linesTxISR_16BIT:0000000000000000 $t + /tmp/ccywxtmH.s:6117 .text.SPI_2linesRxISR_16BIT:0000000000000000 $t + /tmp/ccywxtmH.s:6189 .text.SPI_DMAError:0000000000000000 $t + /tmp/ccywxtmH.s:6232 .text.SPI_DMATransmitCplt:0000000000000000 $t + /tmp/ccywxtmH.s:6355 .text.SPI_DMAReceiveCplt:0000000000000000 $t + /tmp/ccywxtmH.s:6471 .text.SPI_DMATransmitReceiveCplt:0000000000000000 $t + /tmp/ccywxtmH.s:6570 .text.HAL_SPI_IRQHandler:0000000000000000 $t + /tmp/ccywxtmH.s:6576 .text.HAL_SPI_IRQHandler:0000000000000000 HAL_SPI_IRQHandler + /tmp/ccywxtmH.s:6837 .text.HAL_SPI_IRQHandler:0000000000000114 $d + /tmp/ccywxtmH.s:6847 .text.SPI_DMAAbortOnError:0000000000000000 SPI_DMAAbortOnError + /tmp/ccywxtmH.s:6842 .text.SPI_DMAAbortOnError:0000000000000000 $t + ARM GAS /tmp/ccywxtmH.s page 254 + + + /tmp/ccywxtmH.s:6879 .text.HAL_SPI_AbortCpltCallback:0000000000000000 $t + /tmp/ccywxtmH.s:6885 .text.HAL_SPI_AbortCpltCallback:0000000000000000 HAL_SPI_AbortCpltCallback + /tmp/ccywxtmH.s:6900 .text.HAL_SPI_Abort_IT:0000000000000000 $t + /tmp/ccywxtmH.s:6906 .text.HAL_SPI_Abort_IT:0000000000000000 HAL_SPI_Abort_IT + /tmp/ccywxtmH.s:7239 .text.HAL_SPI_Abort_IT:0000000000000148 $d + /tmp/ccywxtmH.s:7406 .text.SPI_DMATxAbortCallback:0000000000000000 SPI_DMATxAbortCallback + /tmp/ccywxtmH.s:7254 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b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi_ex.d new file mode 100644 index 0000000..6c6c151 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi_ex.d @@ -0,0 +1,58 @@ +build/stm32f3xx_hal_spi_ex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi_ex.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi_ex.lst new file mode 100644 index 0000000..30c6381 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi_ex.lst @@ -0,0 +1,236 @@ +ARM GAS /tmp/ccqmlNi8.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_spi_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c" + 20 .section .text.HAL_SPIEx_FlushRxFifo,"ax",%progbits + 21 .align 1 + 22 .global HAL_SPIEx_FlushRxFifo + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_SPIEx_FlushRxFifo: + 28 .LVL0: + 29 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @file stm32f3xx_hal_spi_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @brief Extended SPI HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * SPI peripheral extended functionalities : + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + IO operation functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ****************************************************************************** + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @attention + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * All rights reserved.

    + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * the "License"; You may not use this file except in compliance with the + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * License. You may obtain a copy of the License at: + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * opensource.org/licenses/BSD-3-Clause + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ****************************************************************************** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Includes ------------------------------------------------------------------*/ + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** #include "stm32f3xx_hal.h" + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + ARM GAS /tmp/ccqmlNi8.s page 2 + + + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @defgroup SPIEx SPIEx + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @brief SPI Extended HAL module driver + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** #ifdef HAL_SPI_MODULE_ENABLED + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private defines -----------------------------------------------------------*/ + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @defgroup SPIEx_Private_Constants SPIEx Private Constants + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** #define SPI_FIFO_SIZE 4UL + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @} + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private macros ------------------------------------------------------------*/ + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private variables ---------------------------------------------------------*/ + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Exported functions --------------------------------------------------------*/ + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @brief Data transfers functions + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** @verbatim + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ============================================================================== + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ##### IO operation functions ##### + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** =============================================================================== + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** [..] + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** This subsection provides a set of extended functions to manage the SPI + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** data transfers. + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** (#) Rx data flush function: + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** (++) HAL_SPIEx_FlushRxFifo() + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** @endverbatim + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @brief Flush the RX fifo. + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * the configuration information for the specified SPI module. + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @retval HAL status + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 30 .loc 1 81 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 8 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 @ link register save eliminated. + ARM GAS /tmp/ccqmlNi8.s page 3 + + + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** __IO uint32_t tmpreg; + 35 .loc 1 82 3 view .LVU1 + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** uint8_t count = 0U; + 36 .loc 1 83 3 view .LVU2 + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) + 37 .loc 1 84 3 view .LVU3 + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** uint8_t count = 0U; + 38 .loc 1 83 12 is_stmt 0 view .LVU4 + 39 0000 0023 movs r3, #0 + 40 .LVL1: + 41 .loc 1 84 48 is_stmt 1 view .LVU5 + 42 .loc 1 84 15 is_stmt 0 view .LVU6 + 43 0002 0268 ldr r2, [r0] + 44 .loc 1 84 25 view .LVU7 + 45 0004 9168 ldr r1, [r2, #8] + 46 .loc 1 84 48 view .LVU8 + 47 0006 11F4C06F tst r1, #1536 + 48 000a 12D0 beq .L10 + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** __IO uint32_t tmpreg; + 49 .loc 1 81 1 view .LVU9 + 50 000c 82B0 sub sp, sp, #8 + 51 .cfi_def_cfa_offset 8 + 52 000e 04E0 b .L4 + 53 .L12: + 54 .loc 1 84 48 is_stmt 1 view .LVU10 + 55 .loc 1 84 15 is_stmt 0 view .LVU11 + 56 0010 0268 ldr r2, [r0] + 57 .loc 1 84 25 view .LVU12 + 58 0012 9168 ldr r1, [r2, #8] + 59 .loc 1 84 48 view .LVU13 + 60 0014 11F4C06F tst r1, #1536 + 61 0018 09D0 beq .L11 + 62 .L4: + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** count++; + 63 .loc 1 86 5 is_stmt 1 view .LVU14 + 64 .loc 1 86 10 is_stmt 0 view .LVU15 + 65 001a 0133 adds r3, r3, #1 + 66 .LVL2: + 67 .loc 1 86 10 view .LVU16 + 68 001c DBB2 uxtb r3, r3 + 69 .LVL3: + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** tmpreg = hspi->Instance->DR; + 70 .loc 1 87 5 is_stmt 1 view .LVU17 + 71 .loc 1 87 28 is_stmt 0 view .LVU18 + 72 001e D268 ldr r2, [r2, #12] + 73 .loc 1 87 12 view .LVU19 + 74 0020 0192 str r2, [sp, #4] + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** UNUSED(tmpreg); /* To avoid GCC warning */ + 75 .loc 1 88 5 is_stmt 1 view .LVU20 + 76 0022 019A ldr r2, [sp, #4] + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** if (count == SPI_FIFO_SIZE) + 77 .loc 1 89 5 view .LVU21 + 78 .loc 1 89 8 is_stmt 0 view .LVU22 + 79 0024 042B cmp r3, #4 + 80 0026 F3D1 bne .L12 + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + ARM GAS /tmp/ccqmlNi8.s page 4 + + + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** return HAL_TIMEOUT; + 81 .loc 1 91 14 view .LVU23 + 82 0028 0320 movs r0, #3 + 83 .LVL4: + 84 .L3: + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** return HAL_OK; + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 85 .loc 1 95 1 view .LVU24 + 86 002a 02B0 add sp, sp, #8 + 87 .cfi_remember_state + 88 .cfi_def_cfa_offset 0 + 89 @ sp needed + 90 002c 7047 bx lr + 91 .LVL5: + 92 .L11: + 93 .cfi_restore_state + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 94 .loc 1 94 10 view .LVU25 + 95 002e 0020 movs r0, #0 + 96 .LVL6: + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 97 .loc 1 94 10 view .LVU26 + 98 0030 FBE7 b .L3 + 99 .LVL7: + 100 .L10: + 101 .cfi_def_cfa_offset 0 + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 102 .loc 1 94 10 view .LVU27 + 103 0032 0020 movs r0, #0 + 104 .LVL8: + 105 .loc 1 95 1 view .LVU28 + 106 0034 7047 bx lr + 107 .cfi_endproc + 108 .LFE130: + 110 .text + 111 .Letext0: + 112 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 113 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 114 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 115 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 116 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 117 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + ARM GAS /tmp/ccqmlNi8.s page 5 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_spi_ex.c + /tmp/ccqmlNi8.s:21 .text.HAL_SPIEx_FlushRxFifo:0000000000000000 $t + /tmp/ccqmlNi8.s:27 .text.HAL_SPIEx_FlushRxFifo:0000000000000000 HAL_SPIEx_FlushRxFifo + +NO UNDEFINED SYMBOLS diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi_ex.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_spi_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..907928e9bbb0a9ad3c02cdd1699a38b178056cff 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Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + 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+Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_tim.lst 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Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: 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b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_tim_ex.lst @@ -0,0 +1,30 @@ +ARM GAS /tmp/ccs2Pp9d.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_tim_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c" + 20 .Letext0: + ARM GAS /tmp/ccs2Pp9d.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_hal_tim_ex.c + +NO UNDEFINED SYMBOLS diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_tim_ex.o b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_hal_tim_ex.o new file mode 100644 index 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100644 index 0000000..0b67161 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_it.d @@ -0,0 +1,60 @@ +build/stm32f3xx_it.o: Core/Src/stm32f3xx_it.c Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Core/Inc/stm32f3xx_it.h +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Core/Inc/stm32f3xx_it.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_it.lst b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_it.lst new file mode 100644 index 0000000..fb1a7f0 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/stm32f3xx_it.lst @@ -0,0 +1,507 @@ +ARM GAS /tmp/ccmKlJMS.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_it.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/stm32f3xx_it.c" + 20 .section .text.NMI_Handler,"ax",%progbits + 21 .align 1 + 22 .global NMI_Handler + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 NMI_Handler: + 28 .LFB130: + 1:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/stm32f3xx_it.c **** /** + 3:Core/Src/stm32f3xx_it.c **** ****************************************************************************** + 4:Core/Src/stm32f3xx_it.c **** * @file stm32f3xx_it.c + 5:Core/Src/stm32f3xx_it.c **** * @brief Interrupt Service Routines. + 6:Core/Src/stm32f3xx_it.c **** ****************************************************************************** + 7:Core/Src/stm32f3xx_it.c **** * @attention + 8:Core/Src/stm32f3xx_it.c **** * + 9:Core/Src/stm32f3xx_it.c **** * Copyright (c) 2023 STMicroelectronics. + 10:Core/Src/stm32f3xx_it.c **** * All rights reserved. + 11:Core/Src/stm32f3xx_it.c **** * + 12:Core/Src/stm32f3xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Core/Src/stm32f3xx_it.c **** * in the root directory of this software component. + 14:Core/Src/stm32f3xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Core/Src/stm32f3xx_it.c **** * + 16:Core/Src/stm32f3xx_it.c **** ****************************************************************************** + 17:Core/Src/stm32f3xx_it.c **** */ + 18:Core/Src/stm32f3xx_it.c **** /* USER CODE END Header */ + 19:Core/Src/stm32f3xx_it.c **** + 20:Core/Src/stm32f3xx_it.c **** /* Includes ------------------------------------------------------------------*/ + 21:Core/Src/stm32f3xx_it.c **** #include "main.h" + 22:Core/Src/stm32f3xx_it.c **** #include "stm32f3xx_it.h" + 23:Core/Src/stm32f3xx_it.c **** /* Private includes ----------------------------------------------------------*/ + 24:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN Includes */ + 25:Core/Src/stm32f3xx_it.c **** /* USER CODE END Includes */ + 26:Core/Src/stm32f3xx_it.c **** + 27:Core/Src/stm32f3xx_it.c **** /* Private typedef -----------------------------------------------------------*/ + 28:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN TD */ + 29:Core/Src/stm32f3xx_it.c **** + 30:Core/Src/stm32f3xx_it.c **** /* USER CODE END TD */ + ARM GAS /tmp/ccmKlJMS.s page 2 + + + 31:Core/Src/stm32f3xx_it.c **** + 32:Core/Src/stm32f3xx_it.c **** /* Private define ------------------------------------------------------------*/ + 33:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PD */ + 34:Core/Src/stm32f3xx_it.c **** + 35:Core/Src/stm32f3xx_it.c **** /* USER CODE END PD */ + 36:Core/Src/stm32f3xx_it.c **** + 37:Core/Src/stm32f3xx_it.c **** /* Private macro -------------------------------------------------------------*/ + 38:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PM */ + 39:Core/Src/stm32f3xx_it.c **** + 40:Core/Src/stm32f3xx_it.c **** /* USER CODE END PM */ + 41:Core/Src/stm32f3xx_it.c **** + 42:Core/Src/stm32f3xx_it.c **** /* Private variables ---------------------------------------------------------*/ + 43:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PV */ + 44:Core/Src/stm32f3xx_it.c **** + 45:Core/Src/stm32f3xx_it.c **** /* USER CODE END PV */ + 46:Core/Src/stm32f3xx_it.c **** + 47:Core/Src/stm32f3xx_it.c **** /* Private function prototypes -----------------------------------------------*/ + 48:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PFP */ + 49:Core/Src/stm32f3xx_it.c **** + 50:Core/Src/stm32f3xx_it.c **** /* USER CODE END PFP */ + 51:Core/Src/stm32f3xx_it.c **** + 52:Core/Src/stm32f3xx_it.c **** /* Private user code ---------------------------------------------------------*/ + 53:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN 0 */ + 54:Core/Src/stm32f3xx_it.c **** + 55:Core/Src/stm32f3xx_it.c **** /* USER CODE END 0 */ + 56:Core/Src/stm32f3xx_it.c **** + 57:Core/Src/stm32f3xx_it.c **** /* External variables --------------------------------------------------------*/ + 58:Core/Src/stm32f3xx_it.c **** extern CAN_HandleTypeDef hcan; + 59:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN EV */ + 60:Core/Src/stm32f3xx_it.c **** + 61:Core/Src/stm32f3xx_it.c **** /* USER CODE END EV */ + 62:Core/Src/stm32f3xx_it.c **** + 63:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ + 64:Core/Src/stm32f3xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */ + 65:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ + 66:Core/Src/stm32f3xx_it.c **** /** + 67:Core/Src/stm32f3xx_it.c **** * @brief This function handles Non maskable interrupt. + 68:Core/Src/stm32f3xx_it.c **** */ + 69:Core/Src/stm32f3xx_it.c **** void NMI_Handler(void) + 70:Core/Src/stm32f3xx_it.c **** { + 29 .loc 1 70 1 view -0 + 30 .cfi_startproc + 31 @ Volatile: function does not return. + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 @ link register save eliminated. + 35 .L2: + 71:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + 72:Core/Src/stm32f3xx_it.c **** + 73:Core/Src/stm32f3xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ + 74:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + 75:Core/Src/stm32f3xx_it.c **** while (1) + 36 .loc 1 75 3 discriminator 1 view .LVU1 + 76:Core/Src/stm32f3xx_it.c **** { + 77:Core/Src/stm32f3xx_it.c **** } + 37 .loc 1 77 3 discriminator 1 view .LVU2 + 75:Core/Src/stm32f3xx_it.c **** { + ARM GAS /tmp/ccmKlJMS.s page 3 + + + 38 .loc 1 75 9 discriminator 1 view .LVU3 + 39 0000 FEE7 b .L2 + 40 .cfi_endproc + 41 .LFE130: + 43 .section .text.HardFault_Handler,"ax",%progbits + 44 .align 1 + 45 .global HardFault_Handler + 46 .syntax unified + 47 .thumb + 48 .thumb_func + 50 HardFault_Handler: + 51 .LFB131: + 78:Core/Src/stm32f3xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ + 79:Core/Src/stm32f3xx_it.c **** } + 80:Core/Src/stm32f3xx_it.c **** + 81:Core/Src/stm32f3xx_it.c **** /** + 82:Core/Src/stm32f3xx_it.c **** * @brief This function handles Hard fault interrupt. + 83:Core/Src/stm32f3xx_it.c **** */ + 84:Core/Src/stm32f3xx_it.c **** void HardFault_Handler(void) + 85:Core/Src/stm32f3xx_it.c **** { + 52 .loc 1 85 1 view -0 + 53 .cfi_startproc + 54 @ Volatile: function does not return. + 55 @ args = 0, pretend = 0, frame = 0 + 56 @ frame_needed = 0, uses_anonymous_args = 0 + 57 @ link register save eliminated. + 58 .L4: + 86:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ + 87:Core/Src/stm32f3xx_it.c **** + 88:Core/Src/stm32f3xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ + 89:Core/Src/stm32f3xx_it.c **** while (1) + 59 .loc 1 89 3 discriminator 1 view .LVU5 + 90:Core/Src/stm32f3xx_it.c **** { + 91:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + 92:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ + 93:Core/Src/stm32f3xx_it.c **** } + 60 .loc 1 93 3 discriminator 1 view .LVU6 + 89:Core/Src/stm32f3xx_it.c **** { + 61 .loc 1 89 9 discriminator 1 view .LVU7 + 62 0000 FEE7 b .L4 + 63 .cfi_endproc + 64 .LFE131: + 66 .section .text.MemManage_Handler,"ax",%progbits + 67 .align 1 + 68 .global MemManage_Handler + 69 .syntax unified + 70 .thumb + 71 .thumb_func + 73 MemManage_Handler: + 74 .LFB132: + 94:Core/Src/stm32f3xx_it.c **** } + 95:Core/Src/stm32f3xx_it.c **** + 96:Core/Src/stm32f3xx_it.c **** /** + 97:Core/Src/stm32f3xx_it.c **** * @brief This function handles Memory management fault. + 98:Core/Src/stm32f3xx_it.c **** */ + 99:Core/Src/stm32f3xx_it.c **** void MemManage_Handler(void) + 100:Core/Src/stm32f3xx_it.c **** { + ARM GAS /tmp/ccmKlJMS.s page 4 + + + 75 .loc 1 100 1 view -0 + 76 .cfi_startproc + 77 @ Volatile: function does not return. + 78 @ args = 0, pretend = 0, frame = 0 + 79 @ frame_needed = 0, uses_anonymous_args = 0 + 80 @ link register save eliminated. + 81 .L6: + 101:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + 102:Core/Src/stm32f3xx_it.c **** + 103:Core/Src/stm32f3xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */ + 104:Core/Src/stm32f3xx_it.c **** while (1) + 82 .loc 1 104 3 discriminator 1 view .LVU9 + 105:Core/Src/stm32f3xx_it.c **** { + 106:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + 107:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */ + 108:Core/Src/stm32f3xx_it.c **** } + 83 .loc 1 108 3 discriminator 1 view .LVU10 + 104:Core/Src/stm32f3xx_it.c **** { + 84 .loc 1 104 9 discriminator 1 view .LVU11 + 85 0000 FEE7 b .L6 + 86 .cfi_endproc + 87 .LFE132: + 89 .section .text.BusFault_Handler,"ax",%progbits + 90 .align 1 + 91 .global BusFault_Handler + 92 .syntax unified + 93 .thumb + 94 .thumb_func + 96 BusFault_Handler: + 97 .LFB133: + 109:Core/Src/stm32f3xx_it.c **** } + 110:Core/Src/stm32f3xx_it.c **** + 111:Core/Src/stm32f3xx_it.c **** /** + 112:Core/Src/stm32f3xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault. + 113:Core/Src/stm32f3xx_it.c **** */ + 114:Core/Src/stm32f3xx_it.c **** void BusFault_Handler(void) + 115:Core/Src/stm32f3xx_it.c **** { + 98 .loc 1 115 1 view -0 + 99 .cfi_startproc + 100 @ Volatile: function does not return. + 101 @ args = 0, pretend = 0, frame = 0 + 102 @ frame_needed = 0, uses_anonymous_args = 0 + 103 @ link register save eliminated. + 104 .L8: + 116:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */ + 117:Core/Src/stm32f3xx_it.c **** + 118:Core/Src/stm32f3xx_it.c **** /* USER CODE END BusFault_IRQn 0 */ + 119:Core/Src/stm32f3xx_it.c **** while (1) + 105 .loc 1 119 3 discriminator 1 view .LVU13 + 120:Core/Src/stm32f3xx_it.c **** { + 121:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + 122:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */ + 123:Core/Src/stm32f3xx_it.c **** } + 106 .loc 1 123 3 discriminator 1 view .LVU14 + 119:Core/Src/stm32f3xx_it.c **** { + 107 .loc 1 119 9 discriminator 1 view .LVU15 + 108 0000 FEE7 b .L8 + ARM GAS /tmp/ccmKlJMS.s page 5 + + + 109 .cfi_endproc + 110 .LFE133: + 112 .section .text.UsageFault_Handler,"ax",%progbits + 113 .align 1 + 114 .global UsageFault_Handler + 115 .syntax unified + 116 .thumb + 117 .thumb_func + 119 UsageFault_Handler: + 120 .LFB134: + 124:Core/Src/stm32f3xx_it.c **** } + 125:Core/Src/stm32f3xx_it.c **** + 126:Core/Src/stm32f3xx_it.c **** /** + 127:Core/Src/stm32f3xx_it.c **** * @brief This function handles Undefined instruction or illegal state. + 128:Core/Src/stm32f3xx_it.c **** */ + 129:Core/Src/stm32f3xx_it.c **** void UsageFault_Handler(void) + 130:Core/Src/stm32f3xx_it.c **** { + 121 .loc 1 130 1 view -0 + 122 .cfi_startproc + 123 @ Volatile: function does not return. + 124 @ args = 0, pretend = 0, frame = 0 + 125 @ frame_needed = 0, uses_anonymous_args = 0 + 126 @ link register save eliminated. + 127 .L10: + 131:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */ + 132:Core/Src/stm32f3xx_it.c **** + 133:Core/Src/stm32f3xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */ + 134:Core/Src/stm32f3xx_it.c **** while (1) + 128 .loc 1 134 3 discriminator 1 view .LVU17 + 135:Core/Src/stm32f3xx_it.c **** { + 136:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + 137:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */ + 138:Core/Src/stm32f3xx_it.c **** } + 129 .loc 1 138 3 discriminator 1 view .LVU18 + 134:Core/Src/stm32f3xx_it.c **** { + 130 .loc 1 134 9 discriminator 1 view .LVU19 + 131 0000 FEE7 b .L10 + 132 .cfi_endproc + 133 .LFE134: + 135 .section .text.SVC_Handler,"ax",%progbits + 136 .align 1 + 137 .global SVC_Handler + 138 .syntax unified + 139 .thumb + 140 .thumb_func + 142 SVC_Handler: + 143 .LFB135: + 139:Core/Src/stm32f3xx_it.c **** } + 140:Core/Src/stm32f3xx_it.c **** + 141:Core/Src/stm32f3xx_it.c **** /** + 142:Core/Src/stm32f3xx_it.c **** * @brief This function handles System service call via SWI instruction. + 143:Core/Src/stm32f3xx_it.c **** */ + 144:Core/Src/stm32f3xx_it.c **** void SVC_Handler(void) + 145:Core/Src/stm32f3xx_it.c **** { + 144 .loc 1 145 1 view -0 + 145 .cfi_startproc + 146 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccmKlJMS.s page 6 + + + 147 @ frame_needed = 0, uses_anonymous_args = 0 + 148 @ link register save eliminated. + 146:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */ + 147:Core/Src/stm32f3xx_it.c **** + 148:Core/Src/stm32f3xx_it.c **** /* USER CODE END SVCall_IRQn 0 */ + 149:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */ + 150:Core/Src/stm32f3xx_it.c **** + 151:Core/Src/stm32f3xx_it.c **** /* USER CODE END SVCall_IRQn 1 */ + 152:Core/Src/stm32f3xx_it.c **** } + 149 .loc 1 152 1 view .LVU21 + 150 0000 7047 bx lr + 151 .cfi_endproc + 152 .LFE135: + 154 .section .text.DebugMon_Handler,"ax",%progbits + 155 .align 1 + 156 .global DebugMon_Handler + 157 .syntax unified + 158 .thumb + 159 .thumb_func + 161 DebugMon_Handler: + 162 .LFB136: + 153:Core/Src/stm32f3xx_it.c **** + 154:Core/Src/stm32f3xx_it.c **** /** + 155:Core/Src/stm32f3xx_it.c **** * @brief This function handles Debug monitor. + 156:Core/Src/stm32f3xx_it.c **** */ + 157:Core/Src/stm32f3xx_it.c **** void DebugMon_Handler(void) + 158:Core/Src/stm32f3xx_it.c **** { + 163 .loc 1 158 1 view -0 + 164 .cfi_startproc + 165 @ args = 0, pretend = 0, frame = 0 + 166 @ frame_needed = 0, uses_anonymous_args = 0 + 167 @ link register save eliminated. + 159:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + 160:Core/Src/stm32f3xx_it.c **** + 161:Core/Src/stm32f3xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */ + 162:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + 163:Core/Src/stm32f3xx_it.c **** + 164:Core/Src/stm32f3xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */ + 165:Core/Src/stm32f3xx_it.c **** } + 168 .loc 1 165 1 view .LVU23 + 169 0000 7047 bx lr + 170 .cfi_endproc + 171 .LFE136: + 173 .section .text.PendSV_Handler,"ax",%progbits + 174 .align 1 + 175 .global PendSV_Handler + 176 .syntax unified + 177 .thumb + 178 .thumb_func + 180 PendSV_Handler: + 181 .LFB137: + 166:Core/Src/stm32f3xx_it.c **** + 167:Core/Src/stm32f3xx_it.c **** /** + 168:Core/Src/stm32f3xx_it.c **** * @brief This function handles Pendable request for system service. + 169:Core/Src/stm32f3xx_it.c **** */ + 170:Core/Src/stm32f3xx_it.c **** void PendSV_Handler(void) + 171:Core/Src/stm32f3xx_it.c **** { + ARM GAS /tmp/ccmKlJMS.s page 7 + + + 182 .loc 1 171 1 view -0 + 183 .cfi_startproc + 184 @ args = 0, pretend = 0, frame = 0 + 185 @ frame_needed = 0, uses_anonymous_args = 0 + 186 @ link register save eliminated. + 172:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ + 173:Core/Src/stm32f3xx_it.c **** + 174:Core/Src/stm32f3xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ + 175:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ + 176:Core/Src/stm32f3xx_it.c **** + 177:Core/Src/stm32f3xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ + 178:Core/Src/stm32f3xx_it.c **** } + 187 .loc 1 178 1 view .LVU25 + 188 0000 7047 bx lr + 189 .cfi_endproc + 190 .LFE137: + 192 .section .text.SysTick_Handler,"ax",%progbits + 193 .align 1 + 194 .global SysTick_Handler + 195 .syntax unified + 196 .thumb + 197 .thumb_func + 199 SysTick_Handler: + 200 .LFB138: + 179:Core/Src/stm32f3xx_it.c **** + 180:Core/Src/stm32f3xx_it.c **** /** + 181:Core/Src/stm32f3xx_it.c **** * @brief This function handles System tick timer. + 182:Core/Src/stm32f3xx_it.c **** */ + 183:Core/Src/stm32f3xx_it.c **** void SysTick_Handler(void) + 184:Core/Src/stm32f3xx_it.c **** { + 201 .loc 1 184 1 view -0 + 202 .cfi_startproc + 203 @ args = 0, pretend = 0, frame = 0 + 204 @ frame_needed = 0, uses_anonymous_args = 0 + 205 0000 08B5 push {r3, lr} + 206 .cfi_def_cfa_offset 8 + 207 .cfi_offset 3, -8 + 208 .cfi_offset 14, -4 + 185:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ + 186:Core/Src/stm32f3xx_it.c **** + 187:Core/Src/stm32f3xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ + 188:Core/Src/stm32f3xx_it.c **** HAL_IncTick(); + 209 .loc 1 188 3 view .LVU27 + 210 0002 FFF7FEFF bl HAL_IncTick + 211 .LVL0: + 189:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ + 190:Core/Src/stm32f3xx_it.c **** + 191:Core/Src/stm32f3xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ + 192:Core/Src/stm32f3xx_it.c **** } + 212 .loc 1 192 1 is_stmt 0 view .LVU28 + 213 0006 08BD pop {r3, pc} + 214 .cfi_endproc + 215 .LFE138: + 217 .section .text.USB_LP_CAN_RX0_IRQHandler,"ax",%progbits + 218 .align 1 + 219 .global USB_LP_CAN_RX0_IRQHandler + 220 .syntax unified + ARM GAS /tmp/ccmKlJMS.s page 8 + + + 221 .thumb + 222 .thumb_func + 224 USB_LP_CAN_RX0_IRQHandler: + 225 .LFB139: + 193:Core/Src/stm32f3xx_it.c **** + 194:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ + 195:Core/Src/stm32f3xx_it.c **** /* STM32F3xx Peripheral Interrupt Handlers */ + 196:Core/Src/stm32f3xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */ + 197:Core/Src/stm32f3xx_it.c **** /* For the available peripheral interrupt handler names, */ + 198:Core/Src/stm32f3xx_it.c **** /* please refer to the startup file (startup_stm32f3xx.s). */ + 199:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ + 200:Core/Src/stm32f3xx_it.c **** + 201:Core/Src/stm32f3xx_it.c **** /** + 202:Core/Src/stm32f3xx_it.c **** * @brief This function handles USB low priority or CAN_RX0 interrupts. + 203:Core/Src/stm32f3xx_it.c **** */ + 204:Core/Src/stm32f3xx_it.c **** void USB_LP_CAN_RX0_IRQHandler(void) + 205:Core/Src/stm32f3xx_it.c **** { + 226 .loc 1 205 1 is_stmt 1 view -0 + 227 .cfi_startproc + 228 @ args = 0, pretend = 0, frame = 0 + 229 @ frame_needed = 0, uses_anonymous_args = 0 + 230 0000 08B5 push {r3, lr} + 231 .cfi_def_cfa_offset 8 + 232 .cfi_offset 3, -8 + 233 .cfi_offset 14, -4 + 206:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ + 207:Core/Src/stm32f3xx_it.c **** + 208:Core/Src/stm32f3xx_it.c **** /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ + 209:Core/Src/stm32f3xx_it.c **** HAL_CAN_IRQHandler(&hcan); + 234 .loc 1 209 3 view .LVU30 + 235 0002 0248 ldr r0, .L18 + 236 0004 FFF7FEFF bl HAL_CAN_IRQHandler + 237 .LVL1: + 210:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ + 211:Core/Src/stm32f3xx_it.c **** + 212:Core/Src/stm32f3xx_it.c **** /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ + 213:Core/Src/stm32f3xx_it.c **** } + 238 .loc 1 213 1 is_stmt 0 view .LVU31 + 239 0008 08BD pop {r3, pc} + 240 .L19: + 241 000a 00BF .align 2 + 242 .L18: + 243 000c 00000000 .word hcan + 244 .cfi_endproc + 245 .LFE139: + 247 .text + 248 .Letext0: + 249 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 250 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 251 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 252 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 253 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 254 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccmKlJMS.s page 9 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32f3xx_it.c + /tmp/ccmKlJMS.s:21 .text.NMI_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:27 .text.NMI_Handler:0000000000000000 NMI_Handler + /tmp/ccmKlJMS.s:44 .text.HardFault_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:50 .text.HardFault_Handler:0000000000000000 HardFault_Handler + /tmp/ccmKlJMS.s:67 .text.MemManage_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:73 .text.MemManage_Handler:0000000000000000 MemManage_Handler + /tmp/ccmKlJMS.s:90 .text.BusFault_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:96 .text.BusFault_Handler:0000000000000000 BusFault_Handler + /tmp/ccmKlJMS.s:113 .text.UsageFault_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:119 .text.UsageFault_Handler:0000000000000000 UsageFault_Handler + /tmp/ccmKlJMS.s:136 .text.SVC_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:142 .text.SVC_Handler:0000000000000000 SVC_Handler + /tmp/ccmKlJMS.s:155 .text.DebugMon_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:161 .text.DebugMon_Handler:0000000000000000 DebugMon_Handler + /tmp/ccmKlJMS.s:174 .text.PendSV_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:180 .text.PendSV_Handler:0000000000000000 PendSV_Handler + /tmp/ccmKlJMS.s:193 .text.SysTick_Handler:0000000000000000 $t + /tmp/ccmKlJMS.s:199 .text.SysTick_Handler:0000000000000000 SysTick_Handler + /tmp/ccmKlJMS.s:218 .text.USB_LP_CAN_RX0_IRQHandler:0000000000000000 $t + /tmp/ccmKlJMS.s:224 .text.USB_LP_CAN_RX0_IRQHandler:0000000000000000 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a/BMS_Testbench/BMS_Software_V1/build/syscalls.lst b/BMS_Testbench/BMS_Software_V1/build/syscalls.lst new file mode 100644 index 0000000..2165cc6 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/syscalls.lst @@ -0,0 +1,861 @@ +ARM GAS /tmp/cccbubnS.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "syscalls.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/syscalls.c" + 20 .section .text.initialise_monitor_handles,"ax",%progbits + 21 .align 1 + 22 .global initialise_monitor_handles + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 initialise_monitor_handles: + 28 .LFB25: + 1:Core/Src/syscalls.c **** /** + 2:Core/Src/syscalls.c **** ****************************************************************************** + 3:Core/Src/syscalls.c **** * @file syscalls.c + 4:Core/Src/syscalls.c **** * @author Auto-generated by STM32CubeIDE + 5:Core/Src/syscalls.c **** * @brief STM32CubeIDE Minimal System calls file + 6:Core/Src/syscalls.c **** * + 7:Core/Src/syscalls.c **** * For more information about which c-functions + 8:Core/Src/syscalls.c **** * need which of these lowlevel functions + 9:Core/Src/syscalls.c **** * please consult the Newlib libc-manual + 10:Core/Src/syscalls.c **** ****************************************************************************** + 11:Core/Src/syscalls.c **** * @attention + 12:Core/Src/syscalls.c **** * + 13:Core/Src/syscalls.c **** * Copyright (c) 2020-2022 STMicroelectronics. + 14:Core/Src/syscalls.c **** * All rights reserved. + 15:Core/Src/syscalls.c **** * + 16:Core/Src/syscalls.c **** * This software is licensed under terms that can be found in the LICENSE file + 17:Core/Src/syscalls.c **** * in the root directory of this software component. + 18:Core/Src/syscalls.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Core/Src/syscalls.c **** * + 20:Core/Src/syscalls.c **** ****************************************************************************** + 21:Core/Src/syscalls.c **** */ + 22:Core/Src/syscalls.c **** + 23:Core/Src/syscalls.c **** /* Includes */ + 24:Core/Src/syscalls.c **** #include + 25:Core/Src/syscalls.c **** #include + 26:Core/Src/syscalls.c **** #include + 27:Core/Src/syscalls.c **** #include + 28:Core/Src/syscalls.c **** #include + 29:Core/Src/syscalls.c **** #include + 30:Core/Src/syscalls.c **** #include + ARM GAS /tmp/cccbubnS.s page 2 + + + 31:Core/Src/syscalls.c **** #include + 32:Core/Src/syscalls.c **** + 33:Core/Src/syscalls.c **** + 34:Core/Src/syscalls.c **** /* Variables */ + 35:Core/Src/syscalls.c **** extern int __io_putchar(int ch) __attribute__((weak)); + 36:Core/Src/syscalls.c **** extern int __io_getchar(void) __attribute__((weak)); + 37:Core/Src/syscalls.c **** + 38:Core/Src/syscalls.c **** + 39:Core/Src/syscalls.c **** char *__env[1] = { 0 }; + 40:Core/Src/syscalls.c **** char **environ = __env; + 41:Core/Src/syscalls.c **** + 42:Core/Src/syscalls.c **** + 43:Core/Src/syscalls.c **** /* Functions */ + 44:Core/Src/syscalls.c **** void initialise_monitor_handles() + 45:Core/Src/syscalls.c **** { + 29 .loc 1 45 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 46:Core/Src/syscalls.c **** } + 34 .loc 1 46 1 view .LVU1 + 35 0000 7047 bx lr + 36 .cfi_endproc + 37 .LFE25: + 39 .section .text._getpid,"ax",%progbits + 40 .align 1 + 41 .global _getpid + 42 .syntax unified + 43 .thumb + 44 .thumb_func + 46 _getpid: + 47 .LFB26: + 47:Core/Src/syscalls.c **** + 48:Core/Src/syscalls.c **** int _getpid(void) + 49:Core/Src/syscalls.c **** { + 48 .loc 1 49 1 view -0 + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 50:Core/Src/syscalls.c **** return 1; + 53 .loc 1 50 3 view .LVU3 + 51:Core/Src/syscalls.c **** } + 54 .loc 1 51 1 is_stmt 0 view .LVU4 + 55 0000 0120 movs r0, #1 + 56 0002 7047 bx lr + 57 .cfi_endproc + 58 .LFE26: + 60 .section .text._kill,"ax",%progbits + 61 .align 1 + 62 .global _kill + 63 .syntax unified + 64 .thumb + 65 .thumb_func + 67 _kill: + 68 .LVL0: + ARM GAS /tmp/cccbubnS.s page 3 + + + 69 .LFB27: + 52:Core/Src/syscalls.c **** + 53:Core/Src/syscalls.c **** int _kill(int pid, int sig) + 54:Core/Src/syscalls.c **** { + 70 .loc 1 54 1 is_stmt 1 view -0 + 71 .cfi_startproc + 72 @ args = 0, pretend = 0, frame = 0 + 73 @ frame_needed = 0, uses_anonymous_args = 0 + 74 .loc 1 54 1 is_stmt 0 view .LVU6 + 75 0000 08B5 push {r3, lr} + 76 .cfi_def_cfa_offset 8 + 77 .cfi_offset 3, -8 + 78 .cfi_offset 14, -4 + 55:Core/Src/syscalls.c **** (void)pid; + 79 .loc 1 55 3 is_stmt 1 view .LVU7 + 56:Core/Src/syscalls.c **** (void)sig; + 80 .loc 1 56 3 view .LVU8 + 57:Core/Src/syscalls.c **** errno = EINVAL; + 81 .loc 1 57 3 view .LVU9 + 82 0002 FFF7FEFF bl __errno + 83 .LVL1: + 84 .loc 1 57 9 is_stmt 0 view .LVU10 + 85 0006 1623 movs r3, #22 + 86 0008 0360 str r3, [r0] + 58:Core/Src/syscalls.c **** return -1; + 87 .loc 1 58 3 is_stmt 1 view .LVU11 + 59:Core/Src/syscalls.c **** } + 88 .loc 1 59 1 is_stmt 0 view .LVU12 + 89 000a 4FF0FF30 mov r0, #-1 + 90 000e 08BD pop {r3, pc} + 91 .cfi_endproc + 92 .LFE27: + 94 .section .text._exit,"ax",%progbits + 95 .align 1 + 96 .global _exit + 97 .syntax unified + 98 .thumb + 99 .thumb_func + 101 _exit: + 102 .LVL2: + 103 .LFB28: + 60:Core/Src/syscalls.c **** + 61:Core/Src/syscalls.c **** void _exit (int status) + 62:Core/Src/syscalls.c **** { + 104 .loc 1 62 1 is_stmt 1 view -0 + 105 .cfi_startproc + 106 @ Volatile: function does not return. + 107 @ args = 0, pretend = 0, frame = 0 + 108 @ frame_needed = 0, uses_anonymous_args = 0 + 109 .loc 1 62 1 is_stmt 0 view .LVU14 + 110 0000 08B5 push {r3, lr} + 111 .cfi_def_cfa_offset 8 + 112 .cfi_offset 3, -8 + 113 .cfi_offset 14, -4 + 63:Core/Src/syscalls.c **** _kill(status, -1); + 114 .loc 1 63 3 is_stmt 1 view .LVU15 + 115 0002 4FF0FF31 mov r1, #-1 + ARM GAS /tmp/cccbubnS.s page 4 + + + 116 0006 FFF7FEFF bl _kill + 117 .LVL3: + 118 .L6: + 64:Core/Src/syscalls.c **** while (1) {} /* Make sure we hang here */ + 119 .loc 1 64 3 discriminator 1 view .LVU16 + 120 .loc 1 64 14 discriminator 1 view .LVU17 + 121 .loc 1 64 9 discriminator 1 view .LVU18 + 122 000a FEE7 b .L6 + 123 .cfi_endproc + 124 .LFE28: + 126 .section .text._read,"ax",%progbits + 127 .align 1 + 128 .weak _read + 129 .syntax unified + 130 .thumb + 131 .thumb_func + 133 _read: + 134 .LVL4: + 135 .LFB29: + 65:Core/Src/syscalls.c **** } + 66:Core/Src/syscalls.c **** + 67:Core/Src/syscalls.c **** __attribute__((weak)) int _read(int file, char *ptr, int len) + 68:Core/Src/syscalls.c **** { + 136 .loc 1 68 1 view -0 + 137 .cfi_startproc + 138 @ args = 0, pretend = 0, frame = 0 + 139 @ frame_needed = 0, uses_anonymous_args = 0 + 140 .loc 1 68 1 is_stmt 0 view .LVU20 + 141 0000 70B5 push {r4, r5, r6, lr} + 142 .cfi_def_cfa_offset 16 + 143 .cfi_offset 4, -16 + 144 .cfi_offset 5, -12 + 145 .cfi_offset 6, -8 + 146 .cfi_offset 14, -4 + 147 0002 0C46 mov r4, r1 + 148 0004 1646 mov r6, r2 + 69:Core/Src/syscalls.c **** (void)file; + 149 .loc 1 69 3 is_stmt 1 view .LVU21 + 70:Core/Src/syscalls.c **** int DataIdx; + 150 .loc 1 70 3 view .LVU22 + 71:Core/Src/syscalls.c **** + 72:Core/Src/syscalls.c **** for (DataIdx = 0; DataIdx < len; DataIdx++) + 151 .loc 1 72 3 view .LVU23 + 152 .LVL5: + 153 .loc 1 72 16 is_stmt 0 view .LVU24 + 154 0006 0025 movs r5, #0 + 155 .loc 1 72 3 view .LVU25 + 156 0008 06E0 b .L9 + 157 .LVL6: + 158 .L10: + 73:Core/Src/syscalls.c **** { + 74:Core/Src/syscalls.c **** *ptr++ = __io_getchar(); + 159 .loc 1 74 5 is_stmt 1 discriminator 3 view .LVU26 + 160 .loc 1 74 14 is_stmt 0 discriminator 3 view .LVU27 + 161 000a FFF7FEFF bl __io_getchar + 162 .LVL7: + 163 .loc 1 74 9 discriminator 3 view .LVU28 + ARM GAS /tmp/cccbubnS.s page 5 + + + 164 000e 2146 mov r1, r4 + 165 .LVL8: + 166 .loc 1 74 12 discriminator 3 view .LVU29 + 167 0010 01F8010B strb r0, [r1], #1 + 168 .LVL9: + 72:Core/Src/syscalls.c **** { + 169 .loc 1 72 43 is_stmt 1 discriminator 3 view .LVU30 + 170 0014 0135 adds r5, r5, #1 + 171 .LVL10: + 172 .loc 1 74 9 is_stmt 0 discriminator 3 view .LVU31 + 173 0016 0C46 mov r4, r1 + 174 .LVL11: + 175 .L9: + 72:Core/Src/syscalls.c **** { + 176 .loc 1 72 29 is_stmt 1 discriminator 1 view .LVU32 + 177 0018 B542 cmp r5, r6 + 178 001a F6DB blt .L10 + 75:Core/Src/syscalls.c **** } + 76:Core/Src/syscalls.c **** + 77:Core/Src/syscalls.c **** return len; + 179 .loc 1 77 3 view .LVU33 + 78:Core/Src/syscalls.c **** } + 180 .loc 1 78 1 is_stmt 0 view .LVU34 + 181 001c 3046 mov r0, r6 + 182 001e 70BD pop {r4, r5, r6, pc} + 183 .loc 1 78 1 view .LVU35 + 184 .cfi_endproc + 185 .LFE29: + 187 .section .text._write,"ax",%progbits + 188 .align 1 + 189 .weak _write + 190 .syntax unified + 191 .thumb + 192 .thumb_func + 194 _write: + 195 .LVL12: + 196 .LFB30: + 79:Core/Src/syscalls.c **** + 80:Core/Src/syscalls.c **** __attribute__((weak)) int _write(int file, char *ptr, int len) + 81:Core/Src/syscalls.c **** { + 197 .loc 1 81 1 is_stmt 1 view -0 + 198 .cfi_startproc + 199 @ args = 0, pretend = 0, frame = 0 + 200 @ frame_needed = 0, uses_anonymous_args = 0 + 201 .loc 1 81 1 is_stmt 0 view .LVU37 + 202 0000 70B5 push {r4, r5, r6, lr} + 203 .cfi_def_cfa_offset 16 + 204 .cfi_offset 4, -16 + 205 .cfi_offset 5, -12 + 206 .cfi_offset 6, -8 + 207 .cfi_offset 14, -4 + 208 0002 0C46 mov r4, r1 + 209 0004 1646 mov r6, r2 + 82:Core/Src/syscalls.c **** (void)file; + 210 .loc 1 82 3 is_stmt 1 view .LVU38 + 83:Core/Src/syscalls.c **** int DataIdx; + 211 .loc 1 83 3 view .LVU39 + ARM GAS /tmp/cccbubnS.s page 6 + + + 84:Core/Src/syscalls.c **** + 85:Core/Src/syscalls.c **** for (DataIdx = 0; DataIdx < len; DataIdx++) + 212 .loc 1 85 3 view .LVU40 + 213 .LVL13: + 214 .loc 1 85 16 is_stmt 0 view .LVU41 + 215 0006 0025 movs r5, #0 + 216 .loc 1 85 3 view .LVU42 + 217 0008 04E0 b .L13 + 218 .LVL14: + 219 .L14: + 86:Core/Src/syscalls.c **** { + 87:Core/Src/syscalls.c **** __io_putchar(*ptr++); + 220 .loc 1 87 5 is_stmt 1 discriminator 3 view .LVU43 + 221 .loc 1 87 5 is_stmt 0 discriminator 3 view .LVU44 + 222 000a 14F8010B ldrb r0, [r4], #1 @ zero_extendqisi2 + 223 .LVL15: + 224 .loc 1 87 5 discriminator 3 view .LVU45 + 225 000e FFF7FEFF bl __io_putchar + 226 .LVL16: + 85:Core/Src/syscalls.c **** { + 227 .loc 1 85 43 is_stmt 1 discriminator 3 view .LVU46 + 228 0012 0135 adds r5, r5, #1 + 229 .LVL17: + 230 .L13: + 85:Core/Src/syscalls.c **** { + 231 .loc 1 85 29 discriminator 1 view .LVU47 + 232 0014 B542 cmp r5, r6 + 233 0016 F8DB blt .L14 + 88:Core/Src/syscalls.c **** } + 89:Core/Src/syscalls.c **** return len; + 234 .loc 1 89 3 view .LVU48 + 90:Core/Src/syscalls.c **** } + 235 .loc 1 90 1 is_stmt 0 view .LVU49 + 236 0018 3046 mov r0, r6 + 237 001a 70BD pop {r4, r5, r6, pc} + 238 .loc 1 90 1 view .LVU50 + 239 .cfi_endproc + 240 .LFE30: + 242 .section .text._close,"ax",%progbits + 243 .align 1 + 244 .global _close + 245 .syntax unified + 246 .thumb + 247 .thumb_func + 249 _close: + 250 .LVL18: + 251 .LFB31: + 91:Core/Src/syscalls.c **** + 92:Core/Src/syscalls.c **** int _close(int file) + 93:Core/Src/syscalls.c **** { + 252 .loc 1 93 1 is_stmt 1 view -0 + 253 .cfi_startproc + 254 @ args = 0, pretend = 0, frame = 0 + 255 @ frame_needed = 0, uses_anonymous_args = 0 + 256 @ link register save eliminated. + 94:Core/Src/syscalls.c **** (void)file; + 257 .loc 1 94 3 view .LVU52 + ARM GAS /tmp/cccbubnS.s page 7 + + + 95:Core/Src/syscalls.c **** return -1; + 258 .loc 1 95 3 view .LVU53 + 96:Core/Src/syscalls.c **** } + 259 .loc 1 96 1 is_stmt 0 view .LVU54 + 260 0000 4FF0FF30 mov r0, #-1 + 261 .LVL19: + 262 .loc 1 96 1 view .LVU55 + 263 0004 7047 bx lr + 264 .cfi_endproc + 265 .LFE31: + 267 .section .text._fstat,"ax",%progbits + 268 .align 1 + 269 .global _fstat + 270 .syntax unified + 271 .thumb + 272 .thumb_func + 274 _fstat: + 275 .LVL20: + 276 .LFB32: + 97:Core/Src/syscalls.c **** + 98:Core/Src/syscalls.c **** + 99:Core/Src/syscalls.c **** int _fstat(int file, struct stat *st) + 100:Core/Src/syscalls.c **** { + 277 .loc 1 100 1 is_stmt 1 view -0 + 278 .cfi_startproc + 279 @ args = 0, pretend = 0, frame = 0 + 280 @ frame_needed = 0, uses_anonymous_args = 0 + 281 @ link register save eliminated. + 101:Core/Src/syscalls.c **** (void)file; + 282 .loc 1 101 3 view .LVU57 + 102:Core/Src/syscalls.c **** st->st_mode = S_IFCHR; + 283 .loc 1 102 3 view .LVU58 + 284 .loc 1 102 15 is_stmt 0 view .LVU59 + 285 0000 4FF40053 mov r3, #8192 + 286 0004 4B60 str r3, [r1, #4] + 103:Core/Src/syscalls.c **** return 0; + 287 .loc 1 103 3 is_stmt 1 view .LVU60 + 104:Core/Src/syscalls.c **** } + 288 .loc 1 104 1 is_stmt 0 view .LVU61 + 289 0006 0020 movs r0, #0 + 290 .LVL21: + 291 .loc 1 104 1 view .LVU62 + 292 0008 7047 bx lr + 293 .cfi_endproc + 294 .LFE32: + 296 .section .text._isatty,"ax",%progbits + 297 .align 1 + 298 .global _isatty + 299 .syntax unified + 300 .thumb + 301 .thumb_func + 303 _isatty: + 304 .LVL22: + 305 .LFB33: + 105:Core/Src/syscalls.c **** + 106:Core/Src/syscalls.c **** int _isatty(int file) + 107:Core/Src/syscalls.c **** { + ARM GAS /tmp/cccbubnS.s page 8 + + + 306 .loc 1 107 1 is_stmt 1 view -0 + 307 .cfi_startproc + 308 @ args = 0, pretend = 0, frame = 0 + 309 @ frame_needed = 0, uses_anonymous_args = 0 + 310 @ link register save eliminated. + 108:Core/Src/syscalls.c **** (void)file; + 311 .loc 1 108 3 view .LVU64 + 109:Core/Src/syscalls.c **** return 1; + 312 .loc 1 109 3 view .LVU65 + 110:Core/Src/syscalls.c **** } + 313 .loc 1 110 1 is_stmt 0 view .LVU66 + 314 0000 0120 movs r0, #1 + 315 .LVL23: + 316 .loc 1 110 1 view .LVU67 + 317 0002 7047 bx lr + 318 .cfi_endproc + 319 .LFE33: + 321 .section .text._lseek,"ax",%progbits + 322 .align 1 + 323 .global _lseek + 324 .syntax unified + 325 .thumb + 326 .thumb_func + 328 _lseek: + 329 .LVL24: + 330 .LFB34: + 111:Core/Src/syscalls.c **** + 112:Core/Src/syscalls.c **** int _lseek(int file, int ptr, int dir) + 113:Core/Src/syscalls.c **** { + 331 .loc 1 113 1 is_stmt 1 view -0 + 332 .cfi_startproc + 333 @ args = 0, pretend = 0, frame = 0 + 334 @ frame_needed = 0, uses_anonymous_args = 0 + 335 @ link register save eliminated. + 114:Core/Src/syscalls.c **** (void)file; + 336 .loc 1 114 3 view .LVU69 + 115:Core/Src/syscalls.c **** (void)ptr; + 337 .loc 1 115 3 view .LVU70 + 116:Core/Src/syscalls.c **** (void)dir; + 338 .loc 1 116 3 view .LVU71 + 117:Core/Src/syscalls.c **** return 0; + 339 .loc 1 117 3 view .LVU72 + 118:Core/Src/syscalls.c **** } + 340 .loc 1 118 1 is_stmt 0 view .LVU73 + 341 0000 0020 movs r0, #0 + 342 .LVL25: + 343 .loc 1 118 1 view .LVU74 + 344 0002 7047 bx lr + 345 .cfi_endproc + 346 .LFE34: + 348 .section .text._open,"ax",%progbits + 349 .align 1 + 350 .global _open + 351 .syntax unified + 352 .thumb + 353 .thumb_func + 355 _open: + ARM GAS /tmp/cccbubnS.s page 9 + + + 356 .LVL26: + 357 .LFB35: + 119:Core/Src/syscalls.c **** + 120:Core/Src/syscalls.c **** int _open(char *path, int flags, ...) + 121:Core/Src/syscalls.c **** { + 358 .loc 1 121 1 is_stmt 1 view -0 + 359 .cfi_startproc + 360 @ args = 4, pretend = 12, frame = 0 + 361 @ frame_needed = 0, uses_anonymous_args = 1 + 362 @ link register save eliminated. + 363 .loc 1 121 1 is_stmt 0 view .LVU76 + 364 0000 0EB4 push {r1, r2, r3} + 365 .cfi_def_cfa_offset 12 + 366 .cfi_offset 1, -12 + 367 .cfi_offset 2, -8 + 368 .cfi_offset 3, -4 + 122:Core/Src/syscalls.c **** (void)path; + 369 .loc 1 122 3 is_stmt 1 view .LVU77 + 123:Core/Src/syscalls.c **** (void)flags; + 370 .loc 1 123 3 view .LVU78 + 124:Core/Src/syscalls.c **** /* Pretend like we always fail */ + 125:Core/Src/syscalls.c **** return -1; + 371 .loc 1 125 3 view .LVU79 + 126:Core/Src/syscalls.c **** } + 372 .loc 1 126 1 is_stmt 0 view .LVU80 + 373 0002 4FF0FF30 mov r0, #-1 + 374 .LVL27: + 375 .loc 1 126 1 view .LVU81 + 376 0006 03B0 add sp, sp, #12 + 377 .cfi_restore 3 + 378 .cfi_restore 2 + 379 .cfi_restore 1 + 380 .cfi_def_cfa_offset 0 + 381 0008 7047 bx lr + 382 .cfi_endproc + 383 .LFE35: + 385 .section .text._wait,"ax",%progbits + 386 .align 1 + 387 .global _wait + 388 .syntax unified + 389 .thumb + 390 .thumb_func + 392 _wait: + 393 .LVL28: + 394 .LFB36: + 127:Core/Src/syscalls.c **** + 128:Core/Src/syscalls.c **** int _wait(int *status) + 129:Core/Src/syscalls.c **** { + 395 .loc 1 129 1 is_stmt 1 view -0 + 396 .cfi_startproc + 397 @ args = 0, pretend = 0, frame = 0 + 398 @ frame_needed = 0, uses_anonymous_args = 0 + 399 .loc 1 129 1 is_stmt 0 view .LVU83 + 400 0000 08B5 push {r3, lr} + 401 .cfi_def_cfa_offset 8 + 402 .cfi_offset 3, -8 + 403 .cfi_offset 14, -4 + ARM GAS /tmp/cccbubnS.s page 10 + + + 130:Core/Src/syscalls.c **** (void)status; + 404 .loc 1 130 3 is_stmt 1 view .LVU84 + 131:Core/Src/syscalls.c **** errno = ECHILD; + 405 .loc 1 131 3 view .LVU85 + 406 0002 FFF7FEFF bl __errno + 407 .LVL29: + 408 .loc 1 131 9 is_stmt 0 view .LVU86 + 409 0006 0A23 movs r3, #10 + 410 0008 0360 str r3, [r0] + 132:Core/Src/syscalls.c **** return -1; + 411 .loc 1 132 3 is_stmt 1 view .LVU87 + 133:Core/Src/syscalls.c **** } + 412 .loc 1 133 1 is_stmt 0 view .LVU88 + 413 000a 4FF0FF30 mov r0, #-1 + 414 000e 08BD pop {r3, pc} + 415 .cfi_endproc + 416 .LFE36: + 418 .section .text._unlink,"ax",%progbits + 419 .align 1 + 420 .global _unlink + 421 .syntax unified + 422 .thumb + 423 .thumb_func + 425 _unlink: + 426 .LVL30: + 427 .LFB37: + 134:Core/Src/syscalls.c **** + 135:Core/Src/syscalls.c **** int _unlink(char *name) + 136:Core/Src/syscalls.c **** { + 428 .loc 1 136 1 is_stmt 1 view -0 + 429 .cfi_startproc + 430 @ args = 0, pretend = 0, frame = 0 + 431 @ frame_needed = 0, uses_anonymous_args = 0 + 432 .loc 1 136 1 is_stmt 0 view .LVU90 + 433 0000 08B5 push {r3, lr} + 434 .cfi_def_cfa_offset 8 + 435 .cfi_offset 3, -8 + 436 .cfi_offset 14, -4 + 137:Core/Src/syscalls.c **** (void)name; + 437 .loc 1 137 3 is_stmt 1 view .LVU91 + 138:Core/Src/syscalls.c **** errno = ENOENT; + 438 .loc 1 138 3 view .LVU92 + 439 0002 FFF7FEFF bl __errno + 440 .LVL31: + 441 .loc 1 138 9 is_stmt 0 view .LVU93 + 442 0006 0223 movs r3, #2 + 443 0008 0360 str r3, [r0] + 139:Core/Src/syscalls.c **** return -1; + 444 .loc 1 139 3 is_stmt 1 view .LVU94 + 140:Core/Src/syscalls.c **** } + 445 .loc 1 140 1 is_stmt 0 view .LVU95 + 446 000a 4FF0FF30 mov r0, #-1 + 447 000e 08BD pop {r3, pc} + 448 .cfi_endproc + 449 .LFE37: + 451 .section .text._times,"ax",%progbits + 452 .align 1 + ARM GAS /tmp/cccbubnS.s page 11 + + + 453 .global _times + 454 .syntax unified + 455 .thumb + 456 .thumb_func + 458 _times: + 459 .LVL32: + 460 .LFB38: + 141:Core/Src/syscalls.c **** + 142:Core/Src/syscalls.c **** int _times(struct tms *buf) + 143:Core/Src/syscalls.c **** { + 461 .loc 1 143 1 is_stmt 1 view -0 + 462 .cfi_startproc + 463 @ args = 0, pretend = 0, frame = 0 + 464 @ frame_needed = 0, uses_anonymous_args = 0 + 465 @ link register save eliminated. + 144:Core/Src/syscalls.c **** (void)buf; + 466 .loc 1 144 3 view .LVU97 + 145:Core/Src/syscalls.c **** return -1; + 467 .loc 1 145 3 view .LVU98 + 146:Core/Src/syscalls.c **** } + 468 .loc 1 146 1 is_stmt 0 view .LVU99 + 469 0000 4FF0FF30 mov r0, #-1 + 470 .LVL33: + 471 .loc 1 146 1 view .LVU100 + 472 0004 7047 bx lr + 473 .cfi_endproc + 474 .LFE38: + 476 .section .text._stat,"ax",%progbits + 477 .align 1 + 478 .global _stat + 479 .syntax unified + 480 .thumb + 481 .thumb_func + 483 _stat: + 484 .LVL34: + 485 .LFB39: + 147:Core/Src/syscalls.c **** + 148:Core/Src/syscalls.c **** int _stat(char *file, struct stat *st) + 149:Core/Src/syscalls.c **** { + 486 .loc 1 149 1 is_stmt 1 view -0 + 487 .cfi_startproc + 488 @ args = 0, pretend = 0, frame = 0 + 489 @ frame_needed = 0, uses_anonymous_args = 0 + 490 @ link register save eliminated. + 150:Core/Src/syscalls.c **** (void)file; + 491 .loc 1 150 3 view .LVU102 + 151:Core/Src/syscalls.c **** st->st_mode = S_IFCHR; + 492 .loc 1 151 3 view .LVU103 + 493 .loc 1 151 15 is_stmt 0 view .LVU104 + 494 0000 4FF40053 mov r3, #8192 + 495 0004 4B60 str r3, [r1, #4] + 152:Core/Src/syscalls.c **** return 0; + 496 .loc 1 152 3 is_stmt 1 view .LVU105 + 153:Core/Src/syscalls.c **** } + 497 .loc 1 153 1 is_stmt 0 view .LVU106 + 498 0006 0020 movs r0, #0 + 499 .LVL35: + ARM GAS /tmp/cccbubnS.s page 12 + + + 500 .loc 1 153 1 view .LVU107 + 501 0008 7047 bx lr + 502 .cfi_endproc + 503 .LFE39: + 505 .section .text._link,"ax",%progbits + 506 .align 1 + 507 .global _link + 508 .syntax unified + 509 .thumb + 510 .thumb_func + 512 _link: + 513 .LVL36: + 514 .LFB40: + 154:Core/Src/syscalls.c **** + 155:Core/Src/syscalls.c **** int _link(char *old, char *new) + 156:Core/Src/syscalls.c **** { + 515 .loc 1 156 1 is_stmt 1 view -0 + 516 .cfi_startproc + 517 @ args = 0, pretend = 0, frame = 0 + 518 @ frame_needed = 0, uses_anonymous_args = 0 + 519 .loc 1 156 1 is_stmt 0 view .LVU109 + 520 0000 08B5 push {r3, lr} + 521 .cfi_def_cfa_offset 8 + 522 .cfi_offset 3, -8 + 523 .cfi_offset 14, -4 + 157:Core/Src/syscalls.c **** (void)old; + 524 .loc 1 157 3 is_stmt 1 view .LVU110 + 158:Core/Src/syscalls.c **** (void)new; + 525 .loc 1 158 3 view .LVU111 + 159:Core/Src/syscalls.c **** errno = EMLINK; + 526 .loc 1 159 3 view .LVU112 + 527 0002 FFF7FEFF bl __errno + 528 .LVL37: + 529 .loc 1 159 9 is_stmt 0 view .LVU113 + 530 0006 1F23 movs r3, #31 + 531 0008 0360 str r3, [r0] + 160:Core/Src/syscalls.c **** return -1; + 532 .loc 1 160 3 is_stmt 1 view .LVU114 + 161:Core/Src/syscalls.c **** } + 533 .loc 1 161 1 is_stmt 0 view .LVU115 + 534 000a 4FF0FF30 mov r0, #-1 + 535 000e 08BD pop {r3, pc} + 536 .cfi_endproc + 537 .LFE40: + 539 .section .text._fork,"ax",%progbits + 540 .align 1 + 541 .global _fork + 542 .syntax unified + 543 .thumb + 544 .thumb_func + 546 _fork: + 547 .LFB41: + 162:Core/Src/syscalls.c **** + 163:Core/Src/syscalls.c **** int _fork(void) + 164:Core/Src/syscalls.c **** { + 548 .loc 1 164 1 is_stmt 1 view -0 + 549 .cfi_startproc + ARM GAS /tmp/cccbubnS.s page 13 + + + 550 @ args = 0, pretend = 0, frame = 0 + 551 @ frame_needed = 0, uses_anonymous_args = 0 + 552 0000 08B5 push {r3, lr} + 553 .cfi_def_cfa_offset 8 + 554 .cfi_offset 3, -8 + 555 .cfi_offset 14, -4 + 165:Core/Src/syscalls.c **** errno = EAGAIN; + 556 .loc 1 165 3 view .LVU117 + 557 0002 FFF7FEFF bl __errno + 558 .LVL38: + 559 .loc 1 165 9 is_stmt 0 view .LVU118 + 560 0006 0B23 movs r3, #11 + 561 0008 0360 str r3, [r0] + 166:Core/Src/syscalls.c **** return -1; + 562 .loc 1 166 3 is_stmt 1 view .LVU119 + 167:Core/Src/syscalls.c **** } + 563 .loc 1 167 1 is_stmt 0 view .LVU120 + 564 000a 4FF0FF30 mov r0, #-1 + 565 000e 08BD pop {r3, pc} + 566 .cfi_endproc + 567 .LFE41: + 569 .section .text._execve,"ax",%progbits + 570 .align 1 + 571 .global _execve + 572 .syntax unified + 573 .thumb + 574 .thumb_func + 576 _execve: + 577 .LVL39: + 578 .LFB42: + 168:Core/Src/syscalls.c **** + 169:Core/Src/syscalls.c **** int _execve(char *name, char **argv, char **env) + 170:Core/Src/syscalls.c **** { + 579 .loc 1 170 1 is_stmt 1 view -0 + 580 .cfi_startproc + 581 @ args = 0, pretend = 0, frame = 0 + 582 @ frame_needed = 0, uses_anonymous_args = 0 + 583 .loc 1 170 1 is_stmt 0 view .LVU122 + 584 0000 08B5 push {r3, lr} + 585 .cfi_def_cfa_offset 8 + 586 .cfi_offset 3, -8 + 587 .cfi_offset 14, -4 + 171:Core/Src/syscalls.c **** (void)name; + 588 .loc 1 171 3 is_stmt 1 view .LVU123 + 172:Core/Src/syscalls.c **** (void)argv; + 589 .loc 1 172 3 view .LVU124 + 173:Core/Src/syscalls.c **** (void)env; + 590 .loc 1 173 3 view .LVU125 + 174:Core/Src/syscalls.c **** errno = ENOMEM; + 591 .loc 1 174 3 view .LVU126 + 592 0002 FFF7FEFF bl __errno + 593 .LVL40: + 594 .loc 1 174 9 is_stmt 0 view .LVU127 + 595 0006 0C23 movs r3, #12 + 596 0008 0360 str r3, [r0] + 175:Core/Src/syscalls.c **** return -1; + 597 .loc 1 175 3 is_stmt 1 view .LVU128 + ARM GAS /tmp/cccbubnS.s page 14 + + + 176:Core/Src/syscalls.c **** } + 598 .loc 1 176 1 is_stmt 0 view .LVU129 + 599 000a 4FF0FF30 mov r0, #-1 + 600 000e 08BD pop {r3, pc} + 601 .cfi_endproc + 602 .LFE42: + 604 .global environ + 605 .section .data.environ,"aw" + 606 .align 2 + 609 environ: + 610 0000 00000000 .word __env + 611 .global __env + 612 .section .bss.__env,"aw",%nobits + 613 .align 2 + 616 __env: + 617 0000 00000000 .space 4 + 618 .weak __io_putchar + 619 .weak __io_getchar + 620 .text + 621 .Letext0: + 622 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 623 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 624 .file 4 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 625 .file 5 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 626 .file 6 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 627 .file 7 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 628 .file 8 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 629 .file 9 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + ARM GAS /tmp/cccbubnS.s page 15 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 syscalls.c + /tmp/cccbubnS.s:21 .text.initialise_monitor_handles:0000000000000000 $t + /tmp/cccbubnS.s:27 .text.initialise_monitor_handles:0000000000000000 initialise_monitor_handles + /tmp/cccbubnS.s:40 .text._getpid:0000000000000000 $t + /tmp/cccbubnS.s:46 .text._getpid:0000000000000000 _getpid + /tmp/cccbubnS.s:61 .text._kill:0000000000000000 $t + /tmp/cccbubnS.s:67 .text._kill:0000000000000000 _kill + /tmp/cccbubnS.s:95 .text._exit:0000000000000000 $t + /tmp/cccbubnS.s:101 .text._exit:0000000000000000 _exit + /tmp/cccbubnS.s:127 .text._read:0000000000000000 $t + /tmp/cccbubnS.s:133 .text._read:0000000000000000 _read + /tmp/cccbubnS.s:188 .text._write:0000000000000000 $t + /tmp/cccbubnS.s:194 .text._write:0000000000000000 _write + /tmp/cccbubnS.s:243 .text._close:0000000000000000 $t + /tmp/cccbubnS.s:249 .text._close:0000000000000000 _close + /tmp/cccbubnS.s:268 .text._fstat:0000000000000000 $t + /tmp/cccbubnS.s:274 .text._fstat:0000000000000000 _fstat + /tmp/cccbubnS.s:297 .text._isatty:0000000000000000 $t + /tmp/cccbubnS.s:303 .text._isatty:0000000000000000 _isatty + /tmp/cccbubnS.s:322 .text._lseek:0000000000000000 $t + /tmp/cccbubnS.s:328 .text._lseek:0000000000000000 _lseek + /tmp/cccbubnS.s:349 .text._open:0000000000000000 $t + /tmp/cccbubnS.s:355 .text._open:0000000000000000 _open + /tmp/cccbubnS.s:386 .text._wait:0000000000000000 $t + /tmp/cccbubnS.s:392 .text._wait:0000000000000000 _wait + /tmp/cccbubnS.s:419 .text._unlink:0000000000000000 $t + /tmp/cccbubnS.s:425 .text._unlink:0000000000000000 _unlink + /tmp/cccbubnS.s:452 .text._times:0000000000000000 $t + /tmp/cccbubnS.s:458 .text._times:0000000000000000 _times + /tmp/cccbubnS.s:477 .text._stat:0000000000000000 $t + /tmp/cccbubnS.s:483 .text._stat:0000000000000000 _stat + /tmp/cccbubnS.s:506 .text._link:0000000000000000 $t + /tmp/cccbubnS.s:512 .text._link:0000000000000000 _link + /tmp/cccbubnS.s:540 .text._fork:0000000000000000 $t + /tmp/cccbubnS.s:546 .text._fork:0000000000000000 _fork + /tmp/cccbubnS.s:570 .text._execve:0000000000000000 $t + /tmp/cccbubnS.s:576 .text._execve:0000000000000000 _execve + /tmp/cccbubnS.s:609 .data.environ:0000000000000000 environ + /tmp/cccbubnS.s:606 .data.environ:0000000000000000 $d + /tmp/cccbubnS.s:616 .bss.__env:0000000000000000 __env + /tmp/cccbubnS.s:613 .bss.__env:0000000000000000 $d + +UNDEFINED SYMBOLS +__errno +__io_getchar +__io_putchar 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.file "sysmem.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/sysmem.c" + 20 .section .text._sbrk,"ax",%progbits + 21 .align 1 + 22 .global _sbrk + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 _sbrk: + 28 .LVL0: + 29 .LFB0: + 1:Core/Src/sysmem.c **** /** + 2:Core/Src/sysmem.c **** ****************************************************************************** + 3:Core/Src/sysmem.c **** * @file sysmem.c + 4:Core/Src/sysmem.c **** * @author Generated by STM32CubeIDE + 5:Core/Src/sysmem.c **** * @brief STM32CubeIDE System Memory calls file + 6:Core/Src/sysmem.c **** * + 7:Core/Src/sysmem.c **** * For more information about which C functions + 8:Core/Src/sysmem.c **** * need which of these lowlevel functions + 9:Core/Src/sysmem.c **** * please consult the newlib libc manual + 10:Core/Src/sysmem.c **** ****************************************************************************** + 11:Core/Src/sysmem.c **** * @attention + 12:Core/Src/sysmem.c **** * + 13:Core/Src/sysmem.c **** * Copyright (c) 2022 STMicroelectronics. + 14:Core/Src/sysmem.c **** * All rights reserved. + 15:Core/Src/sysmem.c **** * + 16:Core/Src/sysmem.c **** * This software is licensed under terms that can be found in the LICENSE file + 17:Core/Src/sysmem.c **** * in the root directory of this software component. + 18:Core/Src/sysmem.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Core/Src/sysmem.c **** * + 20:Core/Src/sysmem.c **** ****************************************************************************** + 21:Core/Src/sysmem.c **** */ + 22:Core/Src/sysmem.c **** + 23:Core/Src/sysmem.c **** /* Includes */ + 24:Core/Src/sysmem.c **** #include + 25:Core/Src/sysmem.c **** #include + 26:Core/Src/sysmem.c **** + 27:Core/Src/sysmem.c **** /** + 28:Core/Src/sysmem.c **** * Pointer to the current high watermark of the heap usage + 29:Core/Src/sysmem.c **** */ + ARM GAS /tmp/ccisrOc0.s page 2 + + + 30:Core/Src/sysmem.c **** static uint8_t *__sbrk_heap_end = NULL; + 31:Core/Src/sysmem.c **** + 32:Core/Src/sysmem.c **** /** + 33:Core/Src/sysmem.c **** * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + 34:Core/Src/sysmem.c **** * and others from the C library + 35:Core/Src/sysmem.c **** * + 36:Core/Src/sysmem.c **** * @verbatim + 37:Core/Src/sysmem.c **** * ############################################################################ + 38:Core/Src/sysmem.c **** * # .data # .bss # newlib heap # MSP stack # + 39:Core/Src/sysmem.c **** * # # # # Reserved by _Min_Stack_Size # + 40:Core/Src/sysmem.c **** * ############################################################################ + 41:Core/Src/sysmem.c **** * ^-- RAM start ^-- _end _estack, RAM end --^ + 42:Core/Src/sysmem.c **** * @endverbatim + 43:Core/Src/sysmem.c **** * + 44:Core/Src/sysmem.c **** * This implementation starts allocating at the '_end' linker symbol + 45:Core/Src/sysmem.c **** * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + 46:Core/Src/sysmem.c **** * The implementation considers '_estack' linker symbol to be RAM end + 47:Core/Src/sysmem.c **** * NOTE: If the MSP stack, at any point during execution, grows larger than the + 48:Core/Src/sysmem.c **** * reserved size, please increase the '_Min_Stack_Size'. + 49:Core/Src/sysmem.c **** * + 50:Core/Src/sysmem.c **** * @param incr Memory size + 51:Core/Src/sysmem.c **** * @return Pointer to allocated memory + 52:Core/Src/sysmem.c **** */ + 53:Core/Src/sysmem.c **** void *_sbrk(ptrdiff_t incr) + 54:Core/Src/sysmem.c **** { + 30 .loc 1 54 1 view -0 + 31 .cfi_startproc + 32 @ args = 0, pretend = 0, frame = 0 + 33 @ frame_needed = 0, uses_anonymous_args = 0 + 34 .loc 1 54 1 is_stmt 0 view .LVU1 + 35 0000 10B5 push {r4, lr} + 36 .cfi_def_cfa_offset 8 + 37 .cfi_offset 4, -8 + 38 .cfi_offset 14, -4 + 39 0002 0346 mov r3, r0 + 55:Core/Src/sysmem.c **** extern uint8_t _end; /* Symbol defined in the linker script */ + 40 .loc 1 55 3 is_stmt 1 view .LVU2 + 56:Core/Src/sysmem.c **** extern uint8_t _estack; /* Symbol defined in the linker script */ + 41 .loc 1 56 3 view .LVU3 + 57:Core/Src/sysmem.c **** extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + 42 .loc 1 57 3 view .LVU4 + 58:Core/Src/sysmem.c **** const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 43 .loc 1 58 3 view .LVU5 + 44 .loc 1 58 18 is_stmt 0 view .LVU6 + 45 0004 0C4A ldr r2, .L8 + 46 0006 0D49 ldr r1, .L8+4 + 47 .LVL1: + 59:Core/Src/sysmem.c **** const uint8_t *max_heap = (uint8_t *)stack_limit; + 48 .loc 1 59 3 is_stmt 1 view .LVU7 + 60:Core/Src/sysmem.c **** uint8_t *prev_heap_end; + 49 .loc 1 60 3 view .LVU8 + 61:Core/Src/sysmem.c **** + 62:Core/Src/sysmem.c **** /* Initialize heap end at first call */ + 63:Core/Src/sysmem.c **** if (NULL == __sbrk_heap_end) + 50 .loc 1 63 3 view .LVU9 + 51 .loc 1 63 12 is_stmt 0 view .LVU10 + 52 0008 0D48 ldr r0, .L8+8 + ARM GAS /tmp/ccisrOc0.s page 3 + + + 53 .LVL2: + 54 .loc 1 63 12 view .LVU11 + 55 000a 0068 ldr r0, [r0] + 56 .loc 1 63 6 view .LVU12 + 57 000c 40B1 cbz r0, .L6 + 58 .L2: + 64:Core/Src/sysmem.c **** { + 65:Core/Src/sysmem.c **** __sbrk_heap_end = &_end; + 66:Core/Src/sysmem.c **** } + 67:Core/Src/sysmem.c **** + 68:Core/Src/sysmem.c **** /* Protect heap from growing into the reserved MSP stack */ + 69:Core/Src/sysmem.c **** if (__sbrk_heap_end + incr > max_heap) + 59 .loc 1 69 3 is_stmt 1 view .LVU13 + 60 .loc 1 69 23 is_stmt 0 view .LVU14 + 61 000e 0C48 ldr r0, .L8+8 + 62 0010 0068 ldr r0, [r0] + 63 0012 0344 add r3, r3, r0 + 64 .LVL3: + 65 .loc 1 69 6 view .LVU15 + 66 0014 521A subs r2, r2, r1 + 67 0016 9342 cmp r3, r2 + 68 0018 06D8 bhi .L7 + 70:Core/Src/sysmem.c **** { + 71:Core/Src/sysmem.c **** errno = ENOMEM; + 72:Core/Src/sysmem.c **** return (void *)-1; + 73:Core/Src/sysmem.c **** } + 74:Core/Src/sysmem.c **** + 75:Core/Src/sysmem.c **** prev_heap_end = __sbrk_heap_end; + 69 .loc 1 75 3 is_stmt 1 view .LVU16 + 70 .LVL4: + 76:Core/Src/sysmem.c **** __sbrk_heap_end += incr; + 71 .loc 1 76 3 view .LVU17 + 72 .loc 1 76 19 is_stmt 0 view .LVU18 + 73 001a 094A ldr r2, .L8+8 + 74 001c 1360 str r3, [r2] + 77:Core/Src/sysmem.c **** + 78:Core/Src/sysmem.c **** return (void *)prev_heap_end; + 75 .loc 1 78 3 is_stmt 1 view .LVU19 + 76 .LVL5: + 77 .L1: + 79:Core/Src/sysmem.c **** } + 78 .loc 1 79 1 is_stmt 0 view .LVU20 + 79 001e 10BD pop {r4, pc} + 80 .LVL6: + 81 .L6: + 65:Core/Src/sysmem.c **** } + 82 .loc 1 65 5 is_stmt 1 view .LVU21 + 65:Core/Src/sysmem.c **** } + 83 .loc 1 65 21 is_stmt 0 view .LVU22 + 84 0020 0748 ldr r0, .L8+8 + 85 0022 084C ldr r4, .L8+12 + 86 0024 0460 str r4, [r0] + 87 0026 F2E7 b .L2 + 88 .LVL7: + 89 .L7: + 71:Core/Src/sysmem.c **** return (void *)-1; + 90 .loc 1 71 5 is_stmt 1 view .LVU23 + ARM GAS /tmp/ccisrOc0.s page 4 + + + 91 0028 FFF7FEFF bl __errno + 92 .LVL8: + 71:Core/Src/sysmem.c **** return (void *)-1; + 93 .loc 1 71 11 is_stmt 0 view .LVU24 + 94 002c 0C23 movs r3, #12 + 95 002e 0360 str r3, [r0] + 72:Core/Src/sysmem.c **** } + 96 .loc 1 72 5 is_stmt 1 view .LVU25 + 72:Core/Src/sysmem.c **** } + 97 .loc 1 72 12 is_stmt 0 view .LVU26 + 98 0030 4FF0FF30 mov r0, #-1 + 99 0034 F3E7 b .L1 + 100 .L9: + 101 0036 00BF .align 2 + 102 .L8: + 103 0038 00000000 .word _estack + 104 003c 00000000 .word _Min_Stack_Size + 105 0040 00000000 .word __sbrk_heap_end + 106 0044 00000000 .word _end + 107 .cfi_endproc + 108 .LFE0: + 110 .section .bss.__sbrk_heap_end,"aw",%nobits + 111 .align 2 + 114 __sbrk_heap_end: + 115 0000 00000000 .space 4 + 116 .text + 117 .Letext0: + 118 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 119 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 120 .file 4 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 121 .file 5 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Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: diff --git a/BMS_Testbench/BMS_Software_V1/build/system_stm32f3xx.lst b/BMS_Testbench/BMS_Software_V1/build/system_stm32f3xx.lst new file mode 100644 index 0000000..1aed0ed --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/build/system_stm32f3xx.lst @@ -0,0 +1,575 @@ +ARM GAS /tmp/ccIBrQzE.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 1 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "system_stm32f3xx.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/system_stm32f3xx.c" + 20 .section .text.SystemInit,"ax",%progbits + 21 .align 1 + 22 .global SystemInit + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 SystemInit: + 28 .LFB130: + 1:Core/Src/system_stm32f3xx.c **** /** + 2:Core/Src/system_stm32f3xx.c **** ****************************************************************************** + 3:Core/Src/system_stm32f3xx.c **** * @file system_stm32f3xx.c + 4:Core/Src/system_stm32f3xx.c **** * @author MCD Application Team + 5:Core/Src/system_stm32f3xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + 6:Core/Src/system_stm32f3xx.c **** * + 7:Core/Src/system_stm32f3xx.c **** * 1. This file provides two functions and one global variable to be called from + 8:Core/Src/system_stm32f3xx.c **** * user application: + 9:Core/Src/system_stm32f3xx.c **** * - SystemInit(): This function is called at startup just after reset and + 10:Core/Src/system_stm32f3xx.c **** * before branch to main program. This call is made inside + 11:Core/Src/system_stm32f3xx.c **** * the "startup_stm32f3xx.s" file. + 12:Core/Src/system_stm32f3xx.c **** * + 13:Core/Src/system_stm32f3xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + 14:Core/Src/system_stm32f3xx.c **** * by the user application to setup the SysTick + 15:Core/Src/system_stm32f3xx.c **** * timer or configure other parameters. + 16:Core/Src/system_stm32f3xx.c **** * + 17:Core/Src/system_stm32f3xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + 18:Core/Src/system_stm32f3xx.c **** * be called whenever the core clock is changed + 19:Core/Src/system_stm32f3xx.c **** * during program execution. + 20:Core/Src/system_stm32f3xx.c **** * + 21:Core/Src/system_stm32f3xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source. + 22:Core/Src/system_stm32f3xx.c **** * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to + 23:Core/Src/system_stm32f3xx.c **** * configure the system clock before to branch to main program. + 24:Core/Src/system_stm32f3xx.c **** * + 25:Core/Src/system_stm32f3xx.c **** * 3. This file configures the system clock as follows: + 26:Core/Src/system_stm32f3xx.c **** *============================================================================= + 27:Core/Src/system_stm32f3xx.c **** * Supported STM32F3xx device + 28:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 29:Core/Src/system_stm32f3xx.c **** * System Clock source | HSI + 30:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + ARM GAS /tmp/ccIBrQzE.s page 2 + + + 31:Core/Src/system_stm32f3xx.c **** * SYSCLK(Hz) | 8000000 + 32:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 33:Core/Src/system_stm32f3xx.c **** * HCLK(Hz) | 8000000 + 34:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 35:Core/Src/system_stm32f3xx.c **** * AHB Prescaler | 1 + 36:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 37:Core/Src/system_stm32f3xx.c **** * APB2 Prescaler | 1 + 38:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 39:Core/Src/system_stm32f3xx.c **** * APB1 Prescaler | 1 + 40:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 41:Core/Src/system_stm32f3xx.c **** * USB Clock | DISABLE + 42:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 43:Core/Src/system_stm32f3xx.c **** *============================================================================= + 44:Core/Src/system_stm32f3xx.c **** ****************************************************************************** + 45:Core/Src/system_stm32f3xx.c **** * @attention + 46:Core/Src/system_stm32f3xx.c **** * + 47:Core/Src/system_stm32f3xx.c **** *

    © Copyright (c) 2016 STMicroelectronics. + 48:Core/Src/system_stm32f3xx.c **** * All rights reserved.

    + 49:Core/Src/system_stm32f3xx.c **** * + 50:Core/Src/system_stm32f3xx.c **** * This software component is licensed by ST under BSD 3-Clause license, + 51:Core/Src/system_stm32f3xx.c **** * the "License"; You may not use this file except in compliance with the + 52:Core/Src/system_stm32f3xx.c **** * License. You may obtain a copy of the License at: + 53:Core/Src/system_stm32f3xx.c **** * opensource.org/licenses/BSD-3-Clause + 54:Core/Src/system_stm32f3xx.c **** * + 55:Core/Src/system_stm32f3xx.c **** ****************************************************************************** + 56:Core/Src/system_stm32f3xx.c **** */ + 57:Core/Src/system_stm32f3xx.c **** + 58:Core/Src/system_stm32f3xx.c **** /** @addtogroup CMSIS + 59:Core/Src/system_stm32f3xx.c **** * @{ + 60:Core/Src/system_stm32f3xx.c **** */ + 61:Core/Src/system_stm32f3xx.c **** + 62:Core/Src/system_stm32f3xx.c **** /** @addtogroup stm32f3xx_system + 63:Core/Src/system_stm32f3xx.c **** * @{ + 64:Core/Src/system_stm32f3xx.c **** */ + 65:Core/Src/system_stm32f3xx.c **** + 66:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Includes + 67:Core/Src/system_stm32f3xx.c **** * @{ + 68:Core/Src/system_stm32f3xx.c **** */ + 69:Core/Src/system_stm32f3xx.c **** + 70:Core/Src/system_stm32f3xx.c **** #include "stm32f3xx.h" + 71:Core/Src/system_stm32f3xx.c **** + 72:Core/Src/system_stm32f3xx.c **** /** + 73:Core/Src/system_stm32f3xx.c **** * @} + 74:Core/Src/system_stm32f3xx.c **** */ + 75:Core/Src/system_stm32f3xx.c **** + 76:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_TypesDefinitions + 77:Core/Src/system_stm32f3xx.c **** * @{ + 78:Core/Src/system_stm32f3xx.c **** */ + 79:Core/Src/system_stm32f3xx.c **** + 80:Core/Src/system_stm32f3xx.c **** /** + 81:Core/Src/system_stm32f3xx.c **** * @} + 82:Core/Src/system_stm32f3xx.c **** */ + 83:Core/Src/system_stm32f3xx.c **** + 84:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Defines + 85:Core/Src/system_stm32f3xx.c **** * @{ + 86:Core/Src/system_stm32f3xx.c **** */ + 87:Core/Src/system_stm32f3xx.c **** #if !defined (HSE_VALUE) + ARM GAS /tmp/ccIBrQzE.s page 3 + + + 88:Core/Src/system_stm32f3xx.c **** #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + 89:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user + 90:Core/Src/system_stm32f3xx.c **** #endif /* HSE_VALUE */ + 91:Core/Src/system_stm32f3xx.c **** + 92:Core/Src/system_stm32f3xx.c **** #if !defined (HSI_VALUE) + 93:Core/Src/system_stm32f3xx.c **** #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + 94:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user + 95:Core/Src/system_stm32f3xx.c **** #endif /* HSI_VALUE */ + 96:Core/Src/system_stm32f3xx.c **** + 97:Core/Src/system_stm32f3xx.c **** /* Note: Following vector table addresses must be defined in line with linker + 98:Core/Src/system_stm32f3xx.c **** configuration. */ + 99:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate the vector table + 100:Core/Src/system_stm32f3xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic + 101:Core/Src/system_stm32f3xx.c **** remap of boot address selected */ + 102:Core/Src/system_stm32f3xx.c **** /* #define USER_VECT_TAB_ADDRESS */ + 103:Core/Src/system_stm32f3xx.c **** + 104:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS) + 105:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table + 106:Core/Src/system_stm32f3xx.c **** in Sram else user remap will be done in Flash. */ + 107:Core/Src/system_stm32f3xx.c **** /* #define VECT_TAB_SRAM */ + 108:Core/Src/system_stm32f3xx.c **** #if defined(VECT_TAB_SRAM) + 109:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + 110:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */ + 111:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + 112:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */ + 113:Core/Src/system_stm32f3xx.c **** #else + 114:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + 115:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */ + 116:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + 117:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */ + 118:Core/Src/system_stm32f3xx.c **** #endif /* VECT_TAB_SRAM */ + 119:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ + 120:Core/Src/system_stm32f3xx.c **** + 121:Core/Src/system_stm32f3xx.c **** /******************************************************************************/ + 122:Core/Src/system_stm32f3xx.c **** /** + 123:Core/Src/system_stm32f3xx.c **** * @} + 124:Core/Src/system_stm32f3xx.c **** */ + 125:Core/Src/system_stm32f3xx.c **** + 126:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Macros + 127:Core/Src/system_stm32f3xx.c **** * @{ + 128:Core/Src/system_stm32f3xx.c **** */ + 129:Core/Src/system_stm32f3xx.c **** + 130:Core/Src/system_stm32f3xx.c **** /** + 131:Core/Src/system_stm32f3xx.c **** * @} + 132:Core/Src/system_stm32f3xx.c **** */ + 133:Core/Src/system_stm32f3xx.c **** + 134:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Variables + 135:Core/Src/system_stm32f3xx.c **** * @{ + 136:Core/Src/system_stm32f3xx.c **** */ + 137:Core/Src/system_stm32f3xx.c **** /* This variable is updated in three ways: + 138:Core/Src/system_stm32f3xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() + 139:Core/Src/system_stm32f3xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 140:Core/Src/system_stm32f3xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 141:Core/Src/system_stm32f3xx.c **** Note: If you use this function to configure the system clock there is no need to + 142:Core/Src/system_stm32f3xx.c **** call the 2 first functions listed above, since SystemCoreClock variable is + 143:Core/Src/system_stm32f3xx.c **** updated automatically. + 144:Core/Src/system_stm32f3xx.c **** */ + ARM GAS /tmp/ccIBrQzE.s page 4 + + + 145:Core/Src/system_stm32f3xx.c **** uint32_t SystemCoreClock = 8000000; + 146:Core/Src/system_stm32f3xx.c **** + 147:Core/Src/system_stm32f3xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + 148:Core/Src/system_stm32f3xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + 149:Core/Src/system_stm32f3xx.c **** + 150:Core/Src/system_stm32f3xx.c **** /** + 151:Core/Src/system_stm32f3xx.c **** * @} + 152:Core/Src/system_stm32f3xx.c **** */ + 153:Core/Src/system_stm32f3xx.c **** + 154:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes + 155:Core/Src/system_stm32f3xx.c **** * @{ + 156:Core/Src/system_stm32f3xx.c **** */ + 157:Core/Src/system_stm32f3xx.c **** + 158:Core/Src/system_stm32f3xx.c **** /** + 159:Core/Src/system_stm32f3xx.c **** * @} + 160:Core/Src/system_stm32f3xx.c **** */ + 161:Core/Src/system_stm32f3xx.c **** + 162:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Functions + 163:Core/Src/system_stm32f3xx.c **** * @{ + 164:Core/Src/system_stm32f3xx.c **** */ + 165:Core/Src/system_stm32f3xx.c **** + 166:Core/Src/system_stm32f3xx.c **** /** + 167:Core/Src/system_stm32f3xx.c **** * @brief Setup the microcontroller system + 168:Core/Src/system_stm32f3xx.c **** * @param None + 169:Core/Src/system_stm32f3xx.c **** * @retval None + 170:Core/Src/system_stm32f3xx.c **** */ + 171:Core/Src/system_stm32f3xx.c **** void SystemInit(void) + 172:Core/Src/system_stm32f3xx.c **** { + 29 .loc 1 172 1 view -0 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 0, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 173:Core/Src/system_stm32f3xx.c **** /* FPU settings --------------------------------------------------------------*/ + 174:Core/Src/system_stm32f3xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + 175:Core/Src/system_stm32f3xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 34 .loc 1 175 3 view .LVU1 + 35 .loc 1 175 6 is_stmt 0 view .LVU2 + 36 0000 034A ldr r2, .L2 + 37 0002 D2F88830 ldr r3, [r2, #136] + 38 .loc 1 175 14 view .LVU3 + 39 0006 43F47003 orr r3, r3, #15728640 + 40 000a C2F88830 str r3, [r2, #136] + 176:Core/Src/system_stm32f3xx.c **** #endif + 177:Core/Src/system_stm32f3xx.c **** + 178:Core/Src/system_stm32f3xx.c **** /* Configure the Vector Table location -------------------------------------*/ + 179:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS) + 180:Core/Src/system_stm32f3xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM + 181:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ + 182:Core/Src/system_stm32f3xx.c **** } + 41 .loc 1 182 1 view .LVU4 + 42 000e 7047 bx lr + 43 .L3: + 44 .align 2 + 45 .L2: + 46 0010 00ED00E0 .word -536810240 + 47 .cfi_endproc + ARM GAS /tmp/ccIBrQzE.s page 5 + + + 48 .LFE130: + 50 .section .text.SystemCoreClockUpdate,"ax",%progbits + 51 .align 1 + 52 .global SystemCoreClockUpdate + 53 .syntax unified + 54 .thumb + 55 .thumb_func + 57 SystemCoreClockUpdate: + 58 .LFB131: + 183:Core/Src/system_stm32f3xx.c **** + 184:Core/Src/system_stm32f3xx.c **** /** + 185:Core/Src/system_stm32f3xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. + 186:Core/Src/system_stm32f3xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can + 187:Core/Src/system_stm32f3xx.c **** * be used by the user application to setup the SysTick timer or configure + 188:Core/Src/system_stm32f3xx.c **** * other parameters. + 189:Core/Src/system_stm32f3xx.c **** * + 190:Core/Src/system_stm32f3xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called + 191:Core/Src/system_stm32f3xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration + 192:Core/Src/system_stm32f3xx.c **** * based on this variable will be incorrect. + 193:Core/Src/system_stm32f3xx.c **** * + 194:Core/Src/system_stm32f3xx.c **** * @note - The system frequency computed by this function is not the real + 195:Core/Src/system_stm32f3xx.c **** * frequency in the chip. It is calculated based on the predefined + 196:Core/Src/system_stm32f3xx.c **** * constant and the selected clock source: + 197:Core/Src/system_stm32f3xx.c **** * + 198:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + 199:Core/Src/system_stm32f3xx.c **** * + 200:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + 201:Core/Src/system_stm32f3xx.c **** * + 202:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + 203:Core/Src/system_stm32f3xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. + 204:Core/Src/system_stm32f3xx.c **** * + 205:Core/Src/system_stm32f3xx.c **** * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value + 206:Core/Src/system_stm32f3xx.c **** * 8 MHz) but the real value may vary depending on the variations + 207:Core/Src/system_stm32f3xx.c **** * in voltage and temperature. + 208:Core/Src/system_stm32f3xx.c **** * + 209:Core/Src/system_stm32f3xx.c **** * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value + 210:Core/Src/system_stm32f3xx.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real + 211:Core/Src/system_stm32f3xx.c **** * frequency of the crystal used. Otherwise, this function may + 212:Core/Src/system_stm32f3xx.c **** * have wrong result. + 213:Core/Src/system_stm32f3xx.c **** * + 214:Core/Src/system_stm32f3xx.c **** * - The result of this function could be not correct when using fractional + 215:Core/Src/system_stm32f3xx.c **** * value for HSE crystal. + 216:Core/Src/system_stm32f3xx.c **** * + 217:Core/Src/system_stm32f3xx.c **** * @param None + 218:Core/Src/system_stm32f3xx.c **** * @retval None + 219:Core/Src/system_stm32f3xx.c **** */ + 220:Core/Src/system_stm32f3xx.c **** void SystemCoreClockUpdate (void) + 221:Core/Src/system_stm32f3xx.c **** { + 59 .loc 1 221 1 is_stmt 1 view -0 + 60 .cfi_startproc + 61 @ args = 0, pretend = 0, frame = 0 + 62 @ frame_needed = 0, uses_anonymous_args = 0 + 63 @ link register save eliminated. + 222:Core/Src/system_stm32f3xx.c **** uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + 64 .loc 1 222 3 view .LVU6 + 65 .LVL0: + 223:Core/Src/system_stm32f3xx.c **** + ARM GAS /tmp/ccIBrQzE.s page 6 + + + 224:Core/Src/system_stm32f3xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 225:Core/Src/system_stm32f3xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS; + 66 .loc 1 225 3 view .LVU7 + 67 .loc 1 225 12 is_stmt 0 view .LVU8 + 68 0000 1D4B ldr r3, .L11 + 69 0002 5B68 ldr r3, [r3, #4] + 70 .loc 1 225 7 view .LVU9 + 71 0004 03F00C03 and r3, r3, #12 + 72 .LVL1: + 226:Core/Src/system_stm32f3xx.c **** + 227:Core/Src/system_stm32f3xx.c **** switch (tmp) + 73 .loc 1 227 3 is_stmt 1 view .LVU10 + 74 0008 042B cmp r3, #4 + 75 000a 14D0 beq .L5 + 76 000c 082B cmp r3, #8 + 77 000e 16D0 beq .L6 + 78 0010 1BB1 cbz r3, .L10 + 228:Core/Src/system_stm32f3xx.c **** { + 229:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + 230:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE; + 231:Core/Src/system_stm32f3xx.c **** break; + 232:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + 233:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSE_VALUE; + 234:Core/Src/system_stm32f3xx.c **** break; + 235:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + 236:Core/Src/system_stm32f3xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/ + 237:Core/Src/system_stm32f3xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + 238:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 239:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2; + 240:Core/Src/system_stm32f3xx.c **** + 241:Core/Src/system_stm32f3xx.c **** #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) + 242:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + 243:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + 244:Core/Src/system_stm32f3xx.c **** { + 245:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 246:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + 247:Core/Src/system_stm32f3xx.c **** } + 248:Core/Src/system_stm32f3xx.c **** else + 249:Core/Src/system_stm32f3xx.c **** { + 250:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock selected as PREDIV1 clock entry */ + 251:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; + 252:Core/Src/system_stm32f3xx.c **** } + 253:Core/Src/system_stm32f3xx.c **** #else + 254:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) + 255:Core/Src/system_stm32f3xx.c **** { + 256:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + 257:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + 258:Core/Src/system_stm32f3xx.c **** } + 259:Core/Src/system_stm32f3xx.c **** else + 260:Core/Src/system_stm32f3xx.c **** { + 261:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + 262:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 263:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + 264:Core/Src/system_stm32f3xx.c **** } + 265:Core/Src/system_stm32f3xx.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + 266:Core/Src/system_stm32f3xx.c **** break; + 267:Core/Src/system_stm32f3xx.c **** default: /* HSI used as system clock */ + ARM GAS /tmp/ccIBrQzE.s page 7 + + + 268:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE; + 79 .loc 1 268 7 view .LVU11 + 80 .loc 1 268 23 is_stmt 0 view .LVU12 + 81 0012 1A4B ldr r3, .L11+4 + 82 .LVL2: + 83 .loc 1 268 23 view .LVU13 + 84 0014 1A4A ldr r2, .L11+8 + 85 0016 1A60 str r2, [r3] + 269:Core/Src/system_stm32f3xx.c **** break; + 86 .loc 1 269 7 is_stmt 1 view .LVU14 + 87 0018 02E0 b .L8 + 88 .LVL3: + 89 .L10: + 230:Core/Src/system_stm32f3xx.c **** break; + 90 .loc 1 230 7 view .LVU15 + 230:Core/Src/system_stm32f3xx.c **** break; + 91 .loc 1 230 23 is_stmt 0 view .LVU16 + 92 001a 184B ldr r3, .L11+4 + 93 .LVL4: + 230:Core/Src/system_stm32f3xx.c **** break; + 94 .loc 1 230 23 view .LVU17 + 95 001c 184A ldr r2, .L11+8 + 96 001e 1A60 str r2, [r3] + 231:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + 97 .loc 1 231 7 is_stmt 1 view .LVU18 + 98 .LVL5: + 99 .L8: + 270:Core/Src/system_stm32f3xx.c **** } + 271:Core/Src/system_stm32f3xx.c **** /* Compute HCLK clock frequency ----------------*/ + 272:Core/Src/system_stm32f3xx.c **** /* Get HCLK prescaler */ + 273:Core/Src/system_stm32f3xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + 100 .loc 1 273 3 view .LVU19 + 101 .loc 1 273 28 is_stmt 0 view .LVU20 + 102 0020 154B ldr r3, .L11 + 103 0022 5B68 ldr r3, [r3, #4] + 104 .loc 1 273 52 view .LVU21 + 105 0024 C3F30313 ubfx r3, r3, #4, #4 + 106 .loc 1 273 22 view .LVU22 + 107 0028 164A ldr r2, .L11+12 + 108 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2 + 109 .LVL6: + 274:Core/Src/system_stm32f3xx.c **** /* HCLK clock frequency */ + 275:Core/Src/system_stm32f3xx.c **** SystemCoreClock >>= tmp; + 110 .loc 1 275 3 is_stmt 1 view .LVU23 + 111 .loc 1 275 19 is_stmt 0 view .LVU24 + 112 002c 134A ldr r2, .L11+4 + 113 002e 1368 ldr r3, [r2] + 114 0030 CB40 lsrs r3, r3, r1 + 115 0032 1360 str r3, [r2] + 276:Core/Src/system_stm32f3xx.c **** } + 116 .loc 1 276 1 view .LVU25 + 117 0034 7047 bx lr + 118 .LVL7: + 119 .L5: + 233:Core/Src/system_stm32f3xx.c **** break; + 120 .loc 1 233 7 is_stmt 1 view .LVU26 + 233:Core/Src/system_stm32f3xx.c **** break; + ARM GAS /tmp/ccIBrQzE.s page 8 + + + 121 .loc 1 233 23 is_stmt 0 view .LVU27 + 122 0036 114B ldr r3, .L11+4 + 123 .LVL8: + 233:Core/Src/system_stm32f3xx.c **** break; + 124 .loc 1 233 23 view .LVU28 + 125 0038 134A ldr r2, .L11+16 + 126 003a 1A60 str r2, [r3] + 234:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + 127 .loc 1 234 7 is_stmt 1 view .LVU29 + 128 003c F0E7 b .L8 + 129 .LVL9: + 130 .L6: + 237:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 131 .loc 1 237 7 view .LVU30 + 237:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 132 .loc 1 237 20 is_stmt 0 view .LVU31 + 133 003e 0E4A ldr r2, .L11 + 134 0040 5368 ldr r3, [r2, #4] + 135 .LVL10: + 238:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2; + 136 .loc 1 238 7 is_stmt 1 view .LVU32 + 238:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2; + 137 .loc 1 238 22 is_stmt 0 view .LVU33 + 138 0042 5268 ldr r2, [r2, #4] + 139 .LVL11: + 239:Core/Src/system_stm32f3xx.c **** + 140 .loc 1 239 7 is_stmt 1 view .LVU34 + 239:Core/Src/system_stm32f3xx.c **** + 141 .loc 1 239 27 is_stmt 0 view .LVU35 + 142 0044 C3F38343 ubfx r3, r3, #18, #4 + 143 .LVL12: + 239:Core/Src/system_stm32f3xx.c **** + 144 .loc 1 239 15 view .LVU36 + 145 0048 0233 adds r3, r3, #2 + 146 .LVL13: + 254:Core/Src/system_stm32f3xx.c **** { + 147 .loc 1 254 7 is_stmt 1 view .LVU37 + 254:Core/Src/system_stm32f3xx.c **** { + 148 .loc 1 254 10 is_stmt 0 view .LVU38 + 149 004a 12F4803F tst r2, #65536 + 150 004e 05D1 bne .L9 + 257:Core/Src/system_stm32f3xx.c **** } + 151 .loc 1 257 9 is_stmt 1 view .LVU39 + 257:Core/Src/system_stm32f3xx.c **** } + 152 .loc 1 257 44 is_stmt 0 view .LVU40 + 153 0050 0E4A ldr r2, .L11+20 + 154 .LVL14: + 257:Core/Src/system_stm32f3xx.c **** } + 155 .loc 1 257 44 view .LVU41 + 156 0052 02FB03F3 mul r3, r2, r3 + 157 .LVL15: + 257:Core/Src/system_stm32f3xx.c **** } + 158 .loc 1 257 25 view .LVU42 + 159 0056 094A ldr r2, .L11+4 + 160 0058 1360 str r3, [r2] + 161 005a E1E7 b .L8 + 162 .LVL16: + ARM GAS /tmp/ccIBrQzE.s page 9 + + + 163 .L9: + 261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 164 .loc 1 261 9 is_stmt 1 view .LVU43 + 261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 165 .loc 1 261 28 is_stmt 0 view .LVU44 + 166 005c 064A ldr r2, .L11 + 167 .LVL17: + 261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 168 .loc 1 261 28 view .LVU45 + 169 005e D16A ldr r1, [r2, #44] + 261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 170 .loc 1 261 36 view .LVU46 + 171 0060 01F00F01 and r1, r1, #15 + 261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 172 .loc 1 261 22 view .LVU47 + 173 0064 0131 adds r1, r1, #1 + 174 .LVL18: + 263:Core/Src/system_stm32f3xx.c **** } + 175 .loc 1 263 9 is_stmt 1 view .LVU48 + 263:Core/Src/system_stm32f3xx.c **** } + 176 .loc 1 263 38 is_stmt 0 view .LVU49 + 177 0066 084A ldr r2, .L11+16 + 178 0068 B2FBF1F2 udiv r2, r2, r1 + 263:Core/Src/system_stm32f3xx.c **** } + 179 .loc 1 263 54 view .LVU50 + 180 006c 02FB03F3 mul r3, r2, r3 + 181 .LVL19: + 263:Core/Src/system_stm32f3xx.c **** } + 182 .loc 1 263 25 view .LVU51 + 183 0070 024A ldr r2, .L11+4 + 184 0072 1360 str r3, [r2] + 185 0074 D4E7 b .L8 + 186 .L12: + 187 0076 00BF .align 2 + 188 .L11: + 189 0078 00100240 .word 1073876992 + 190 007c 00000000 .word SystemCoreClock + 191 0080 00127A00 .word 8000000 + 192 0084 00000000 .word AHBPrescTable + 193 0088 0024F400 .word 16000000 + 194 008c 00093D00 .word 4000000 + 195 .cfi_endproc + 196 .LFE131: + 198 .global APBPrescTable + 199 .section .rodata.APBPrescTable,"a" + 200 .align 2 + 203 APBPrescTable: + 204 0000 00000000 .ascii "\000\000\000\000\001\002\003\004" + 204 01020304 + 205 .global AHBPrescTable + 206 .section .rodata.AHBPrescTable,"a" + 207 .align 2 + 210 AHBPrescTable: + 211 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006" + 211 00000000 + 211 01020304 + 211 06 + ARM GAS /tmp/ccIBrQzE.s page 10 + + + 212 000d 070809 .ascii "\007\010\011" + 213 .global SystemCoreClock + 214 .section .data.SystemCoreClock,"aw" + 215 .align 2 + 218 SystemCoreClock: + 219 0000 00127A00 .word 8000000 + 220 .text + 221 .Letext0: + 222 .file 2 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 223 .file 3 "/home/david/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-non + 224 .file 4 "Drivers/CMSIS/Include/core_cm4.h" + 225 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + 226 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + ARM GAS /tmp/ccIBrQzE.s page 11 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 system_stm32f3xx.c + /tmp/ccIBrQzE.s:21 .text.SystemInit:0000000000000000 $t + /tmp/ccIBrQzE.s:27 .text.SystemInit:0000000000000000 SystemInit + /tmp/ccIBrQzE.s:46 .text.SystemInit:0000000000000010 $d + /tmp/ccIBrQzE.s:51 .text.SystemCoreClockUpdate:0000000000000000 $t + /tmp/ccIBrQzE.s:57 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate + /tmp/ccIBrQzE.s:189 .text.SystemCoreClockUpdate:0000000000000078 $d + /tmp/ccIBrQzE.s:218 .data.SystemCoreClock:0000000000000000 SystemCoreClock + /tmp/ccIBrQzE.s:210 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable + /tmp/ccIBrQzE.s:203 .rodata.APBPrescTable:0000000000000000 APBPrescTable + /tmp/ccIBrQzE.s:200 .rodata.APBPrescTable:0000000000000000 $d + /tmp/ccIBrQzE.s:207 .rodata.AHBPrescTable:0000000000000000 $d + /tmp/ccIBrQzE.s:215 .data.SystemCoreClock:0000000000000000 $d + +NO UNDEFINED SYMBOLS diff --git a/BMS_Testbench/BMS_Software_V1/build/system_stm32f3xx.o b/BMS_Testbench/BMS_Software_V1/build/system_stm32f3xx.o new file mode 100644 index 0000000000000000000000000000000000000000..46bb5359bfacbeab756e26a9d53e8a863589eed9 GIT binary patch literal 6200 zcmd5=YiwM_6`t99@9sM5=dSJ8P6F#-z#-XPdu^PTLu{`dzc4tvc2oqdy^p*0!oIqD zZ49CUsYHURKcJ64fSO9B4>hU^{n1hirM%kkCX}{Rr6@?0M=2$cAc2BJzcY94`g%cX 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This should match your board +source [find target/stm32f3x.cfg] + +hla_serial 00160013544B500520343637 diff --git a/BMS_Testbench/BMS_Software_V1/startup_stm32f302xc.s b/BMS_Testbench/BMS_Software_V1/startup_stm32f302xc.s new file mode 100644 index 0000000..d946fff --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/startup_stm32f302xc.s @@ -0,0 +1,441 @@ +/** + ****************************************************************************** + * @file startup_stm32f302xc.s + * @author MCD Application Team + * @brief STM32F302xB/STM32F302xC devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_TSC_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_CAN_TX_IRQHandler + .word USB_LP_CAN_RX0_IRQHandler + .word CAN_RX1_IRQHandler + .word CAN_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word 0 + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word COMP1_2_IRQHandler + .word COMP4_6_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word USBWakeUp_RMP_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word FPU_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_TSC_IRQHandler + .thumb_set EXTI2_TSC_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_CAN_TX_IRQHandler + .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler + + .weak USB_LP_CAN_RX0_IRQHandler + .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler + + .weak CAN_RX1_IRQHandler + .thumb_set CAN_RX1_IRQHandler,Default_Handler + + .weak CAN_SCE_IRQHandler + .thumb_set CAN_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP1_2_IRQHandler + .thumb_set COMP1_2_IRQHandler,Default_Handler + + .weak COMP4_6_IRQHandler + .thumb_set COMP4_6_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak USBWakeUp_RMP_IRQHandler + .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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+../Core/Src/ADBMS_Abstraction.c:124:7:amsSetGPIO 16 static +../Core/Src/ADBMS_Abstraction.c:129:7:readGPIO 16 static +../Core/Src/ADBMS_Abstraction.c:134:7:amsConfigBalancing 24 static +../Core/Src/ADBMS_Abstraction.c:155:7:amsStartBalancing 16 static +../Core/Src/ADBMS_Abstraction.c:161:7:amsStopBalancing 8 static +../Core/Src/ADBMS_Abstraction.c:167:7:amsSelfTest 4 static +../Core/Src/ADBMS_Abstraction.c:174:7:amsConfigUnderVoltage 24 static +../Core/Src/ADBMS_Abstraction.c:189:7:amsCheckUnderOverVoltage 40 static +../Core/Src/ADBMS_Abstraction.c:223:7:amsConfigOverVoltage 24 static +../Core/Src/ADBMS_Abstraction.c:300:7:amsClearStatus 16 static +../Core/Src/ADBMS_Abstraction.c:306:7:amsClearAux 16 static +../Core/Src/ADBMS_Abstraction.c:312:7:amsClearCells 16 static +../Core/Src/ADBMS_Abstraction.c:319:7:amsSendWarning 4 static +../Core/Src/ADBMS_Abstraction.c:325:7:amsSendError 4 static +../Core/Src/ADBMS_Abstraction.c:331:7:amsClearWarning 4 static +../Core/Src/ADBMS_Abstraction.c:337:7:amsClearError 4 static +../Core/Src/ADBMS_Abstraction.c:343:7:amscheckOpenCellWire 64 static +../Core/Src/ADBMS_Abstraction.c:388:7:amsReadCellVoltages 24 static diff --git a/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/ADBMS_LL_Driver.d b/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/ADBMS_LL_Driver.d new file mode 100644 index 0000000..fd59ba4 --- /dev/null +++ b/BMS_Testbench/BMS_Software_V1/Debug/Core/Src/ADBMS_LL_Driver.d @@ -0,0 +1,62 @@ +Core/Src/ADBMS_LL_Driver.o: ../Core/Src/ADBMS_LL_Driver.c \ + ../Core/Inc/ADBMS_LL_Driver.h ../Core/Inc/main.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + ../Core/Inc/stm32f3xx_hal_conf.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h +../Core/Inc/ADBMS_LL_Driver.h: +../Core/Inc/main.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +../Core/Inc/stm32f3xx_hal_conf.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: 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