1271 lines
68 KiB
Plaintext
1271 lines
68 KiB
Plaintext
ARM GAS /tmp/cchfFOsO.s page 1
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1 .cpu cortex-m7
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2 .arch armv7e-m
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3 .fpu fpv5-d16
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4 .eabi_attribute 28, 1
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5 .eabi_attribute 20, 1
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6 .eabi_attribute 21, 1
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7 .eabi_attribute 23, 3
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8 .eabi_attribute 24, 1
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9 .eabi_attribute 25, 1
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10 .eabi_attribute 26, 1
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11 .eabi_attribute 30, 1
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12 .eabi_attribute 34, 1
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13 .eabi_attribute 18, 4
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14 .file "system_stm32h7xx.c"
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15 .text
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16 .Ltext0:
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17 .cfi_sections .debug_frame
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18 .file 1 "Core/Src/system_stm32h7xx.c"
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19 .section .text.SystemInit,"ax",%progbits
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20 .align 1
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21 .global SystemInit
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22 .syntax unified
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23 .thumb
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24 .thumb_func
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26 SystemInit:
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27 .LFB335:
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1:Core/Src/system_stm32h7xx.c **** /**
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2:Core/Src/system_stm32h7xx.c **** ******************************************************************************
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3:Core/Src/system_stm32h7xx.c **** * @file system_stm32h7xx.c
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4:Core/Src/system_stm32h7xx.c **** * @author MCD Application Team
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5:Core/Src/system_stm32h7xx.c **** * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
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6:Core/Src/system_stm32h7xx.c **** *
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7:Core/Src/system_stm32h7xx.c **** * This file provides two functions and one global variable to be called from
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8:Core/Src/system_stm32h7xx.c **** * user application:
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9:Core/Src/system_stm32h7xx.c **** * - ExitRun0Mode(): Specifies the Power Supply source. This function is
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10:Core/Src/system_stm32h7xx.c **** * called at startup just after reset and before the call
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11:Core/Src/system_stm32h7xx.c **** * of SystemInit(). This call is made inside
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12:Core/Src/system_stm32h7xx.c **** * the "startup_stm32h7xx.s" file.
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13:Core/Src/system_stm32h7xx.c **** *
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14:Core/Src/system_stm32h7xx.c **** * - SystemInit(): This function is called at startup just after reset and
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15:Core/Src/system_stm32h7xx.c **** * before branch to main program. This call is made inside
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16:Core/Src/system_stm32h7xx.c **** * the "startup_stm32h7xx.s" file.
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17:Core/Src/system_stm32h7xx.c **** *
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18:Core/Src/system_stm32h7xx.c **** * - SystemCoreClock variable: Contains the core clock, it can be used
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19:Core/Src/system_stm32h7xx.c **** * by the user application to setup the SysTick
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20:Core/Src/system_stm32h7xx.c **** * timer or configure other parameters.
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21:Core/Src/system_stm32h7xx.c **** *
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22:Core/Src/system_stm32h7xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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23:Core/Src/system_stm32h7xx.c **** * be called whenever the core clock is changed
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24:Core/Src/system_stm32h7xx.c **** * during program execution.
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25:Core/Src/system_stm32h7xx.c **** *
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26:Core/Src/system_stm32h7xx.c **** *
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27:Core/Src/system_stm32h7xx.c **** ******************************************************************************
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28:Core/Src/system_stm32h7xx.c **** * @attention
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29:Core/Src/system_stm32h7xx.c **** *
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30:Core/Src/system_stm32h7xx.c **** * Copyright (c) 2017 STMicroelectronics.
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31:Core/Src/system_stm32h7xx.c **** * All rights reserved.
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ARM GAS /tmp/cchfFOsO.s page 2
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32:Core/Src/system_stm32h7xx.c **** *
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33:Core/Src/system_stm32h7xx.c **** * This software is licensed under terms that can be found in the LICENSE file
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34:Core/Src/system_stm32h7xx.c **** * in the root directory of this software component.
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35:Core/Src/system_stm32h7xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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36:Core/Src/system_stm32h7xx.c **** *
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37:Core/Src/system_stm32h7xx.c **** ******************************************************************************
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38:Core/Src/system_stm32h7xx.c **** */
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39:Core/Src/system_stm32h7xx.c ****
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40:Core/Src/system_stm32h7xx.c **** /** @addtogroup CMSIS
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41:Core/Src/system_stm32h7xx.c **** * @{
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42:Core/Src/system_stm32h7xx.c **** */
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43:Core/Src/system_stm32h7xx.c ****
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44:Core/Src/system_stm32h7xx.c **** /** @addtogroup stm32h7xx_system
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45:Core/Src/system_stm32h7xx.c **** * @{
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46:Core/Src/system_stm32h7xx.c **** */
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47:Core/Src/system_stm32h7xx.c ****
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48:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Includes
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49:Core/Src/system_stm32h7xx.c **** * @{
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50:Core/Src/system_stm32h7xx.c **** */
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51:Core/Src/system_stm32h7xx.c ****
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52:Core/Src/system_stm32h7xx.c **** #include "stm32h7xx.h"
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53:Core/Src/system_stm32h7xx.c **** #include <math.h>
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54:Core/Src/system_stm32h7xx.c ****
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55:Core/Src/system_stm32h7xx.c **** #if !defined (HSE_VALUE)
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56:Core/Src/system_stm32h7xx.c **** #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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57:Core/Src/system_stm32h7xx.c **** #endif /* HSE_VALUE */
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58:Core/Src/system_stm32h7xx.c ****
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59:Core/Src/system_stm32h7xx.c **** #if !defined (CSI_VALUE)
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60:Core/Src/system_stm32h7xx.c **** #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
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61:Core/Src/system_stm32h7xx.c **** #endif /* CSI_VALUE */
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62:Core/Src/system_stm32h7xx.c ****
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63:Core/Src/system_stm32h7xx.c **** #if !defined (HSI_VALUE)
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64:Core/Src/system_stm32h7xx.c **** #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
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65:Core/Src/system_stm32h7xx.c **** #endif /* HSI_VALUE */
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66:Core/Src/system_stm32h7xx.c ****
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67:Core/Src/system_stm32h7xx.c ****
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68:Core/Src/system_stm32h7xx.c **** /**
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69:Core/Src/system_stm32h7xx.c **** * @}
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70:Core/Src/system_stm32h7xx.c **** */
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71:Core/Src/system_stm32h7xx.c ****
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72:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_TypesDefinitions
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73:Core/Src/system_stm32h7xx.c **** * @{
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74:Core/Src/system_stm32h7xx.c **** */
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75:Core/Src/system_stm32h7xx.c ****
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76:Core/Src/system_stm32h7xx.c **** /**
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77:Core/Src/system_stm32h7xx.c **** * @}
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78:Core/Src/system_stm32h7xx.c **** */
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79:Core/Src/system_stm32h7xx.c ****
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80:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Defines
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81:Core/Src/system_stm32h7xx.c **** * @{
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82:Core/Src/system_stm32h7xx.c **** */
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83:Core/Src/system_stm32h7xx.c ****
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84:Core/Src/system_stm32h7xx.c **** /************************* Miscellaneous Configuration ************************/
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85:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM)
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86:Core/Src/system_stm32h7xx.c **** /* #define DATA_IN_D2_SRAM */
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87:Core/Src/system_stm32h7xx.c ****
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88:Core/Src/system_stm32h7xx.c **** /* Note: Following vector table addresses must be defined in line with linker
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ARM GAS /tmp/cchfFOsO.s page 3
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89:Core/Src/system_stm32h7xx.c **** configuration. */
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90:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
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91:Core/Src/system_stm32h7xx.c **** anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
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92:Core/Src/system_stm32h7xx.c **** remap of boot address selected */
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93:Core/Src/system_stm32h7xx.c **** /* #define USER_VECT_TAB_ADDRESS */
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94:Core/Src/system_stm32h7xx.c ****
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95:Core/Src/system_stm32h7xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
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96:Core/Src/system_stm32h7xx.c **** #if defined(DUAL_CORE) && defined(CORE_CM4)
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97:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
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98:Core/Src/system_stm32h7xx.c **** in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
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99:Core/Src/system_stm32h7xx.c **** /* #define VECT_TAB_SRAM */
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100:Core/Src/system_stm32h7xx.c **** #if defined(VECT_TAB_SRAM)
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101:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
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102:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x400. */
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103:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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104:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x400. */
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105:Core/Src/system_stm32h7xx.c **** #else
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106:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
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107:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x400. */
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108:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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109:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x400. */
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110:Core/Src/system_stm32h7xx.c **** #endif /* VECT_TAB_SRAM */
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111:Core/Src/system_stm32h7xx.c **** #else
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112:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
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113:Core/Src/system_stm32h7xx.c **** in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
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114:Core/Src/system_stm32h7xx.c **** /* #define VECT_TAB_SRAM */
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115:Core/Src/system_stm32h7xx.c **** #if defined(VECT_TAB_SRAM)
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116:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
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117:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x400. */
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118:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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119:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x400. */
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120:Core/Src/system_stm32h7xx.c **** #else
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121:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
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122:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x400. */
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123:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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124:Core/Src/system_stm32h7xx.c **** This value must be a multiple of 0x400. */
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125:Core/Src/system_stm32h7xx.c **** #endif /* VECT_TAB_SRAM */
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126:Core/Src/system_stm32h7xx.c **** #endif /* DUAL_CORE && CORE_CM4 */
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127:Core/Src/system_stm32h7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
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128:Core/Src/system_stm32h7xx.c **** /******************************************************************************/
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129:Core/Src/system_stm32h7xx.c ****
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130:Core/Src/system_stm32h7xx.c **** /**
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131:Core/Src/system_stm32h7xx.c **** * @}
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132:Core/Src/system_stm32h7xx.c **** */
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133:Core/Src/system_stm32h7xx.c ****
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134:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Macros
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135:Core/Src/system_stm32h7xx.c **** * @{
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136:Core/Src/system_stm32h7xx.c **** */
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137:Core/Src/system_stm32h7xx.c ****
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138:Core/Src/system_stm32h7xx.c **** /**
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139:Core/Src/system_stm32h7xx.c **** * @}
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140:Core/Src/system_stm32h7xx.c **** */
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141:Core/Src/system_stm32h7xx.c ****
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142:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Variables
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143:Core/Src/system_stm32h7xx.c **** * @{
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144:Core/Src/system_stm32h7xx.c **** */
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145:Core/Src/system_stm32h7xx.c **** /* This variable is updated in three ways:
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ARM GAS /tmp/cchfFOsO.s page 4
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146:Core/Src/system_stm32h7xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
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147:Core/Src/system_stm32h7xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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148:Core/Src/system_stm32h7xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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149:Core/Src/system_stm32h7xx.c **** Note: If you use this function to configure the system clock; then there
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150:Core/Src/system_stm32h7xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
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151:Core/Src/system_stm32h7xx.c **** variable is updated automatically.
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152:Core/Src/system_stm32h7xx.c **** */
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153:Core/Src/system_stm32h7xx.c **** uint32_t SystemCoreClock = 64000000;
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154:Core/Src/system_stm32h7xx.c **** uint32_t SystemD2Clock = 64000000;
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155:Core/Src/system_stm32h7xx.c **** const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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156:Core/Src/system_stm32h7xx.c ****
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157:Core/Src/system_stm32h7xx.c **** /**
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158:Core/Src/system_stm32h7xx.c **** * @}
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159:Core/Src/system_stm32h7xx.c **** */
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160:Core/Src/system_stm32h7xx.c ****
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161:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
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162:Core/Src/system_stm32h7xx.c **** * @{
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163:Core/Src/system_stm32h7xx.c **** */
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164:Core/Src/system_stm32h7xx.c ****
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165:Core/Src/system_stm32h7xx.c **** /**
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166:Core/Src/system_stm32h7xx.c **** * @}
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167:Core/Src/system_stm32h7xx.c **** */
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168:Core/Src/system_stm32h7xx.c ****
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169:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Functions
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170:Core/Src/system_stm32h7xx.c **** * @{
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171:Core/Src/system_stm32h7xx.c **** */
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172:Core/Src/system_stm32h7xx.c ****
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173:Core/Src/system_stm32h7xx.c **** /**
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174:Core/Src/system_stm32h7xx.c **** * @brief Setup the microcontroller system
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175:Core/Src/system_stm32h7xx.c **** * Initialize the FPU setting and vector table location
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176:Core/Src/system_stm32h7xx.c **** * configuration.
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177:Core/Src/system_stm32h7xx.c **** * @param None
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178:Core/Src/system_stm32h7xx.c **** * @retval None
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179:Core/Src/system_stm32h7xx.c **** */
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180:Core/Src/system_stm32h7xx.c **** void SystemInit (void)
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181:Core/Src/system_stm32h7xx.c **** {
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28 .loc 1 181 1 view -0
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29 .cfi_startproc
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30 @ args = 0, pretend = 0, frame = 0
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31 @ frame_needed = 0, uses_anonymous_args = 0
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32 @ link register save eliminated.
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182:Core/Src/system_stm32h7xx.c **** #if defined (DATA_IN_D2_SRAM)
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183:Core/Src/system_stm32h7xx.c **** __IO uint32_t tmpreg;
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184:Core/Src/system_stm32h7xx.c **** #endif /* DATA_IN_D2_SRAM */
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185:Core/Src/system_stm32h7xx.c ****
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186:Core/Src/system_stm32h7xx.c **** /* FPU settings ------------------------------------------------------------*/
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187:Core/Src/system_stm32h7xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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188:Core/Src/system_stm32h7xx.c **** SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
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33 .loc 1 188 5 view .LVU1
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34 .loc 1 188 8 is_stmt 0 view .LVU2
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35 0000 2B4A ldr r2, .L5
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36 0002 D2F88830 ldr r3, [r2, #136]
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37 .loc 1 188 16 view .LVU3
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38 0006 43F47003 orr r3, r3, #15728640
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39 000a C2F88830 str r3, [r2, #136]
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189:Core/Src/system_stm32h7xx.c **** #endif
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190:Core/Src/system_stm32h7xx.c **** /* Reset the RCC clock configuration to the default reset state ------------*/
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ARM GAS /tmp/cchfFOsO.s page 5
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191:Core/Src/system_stm32h7xx.c ****
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192:Core/Src/system_stm32h7xx.c **** /* Increasing the CPU frequency */
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193:Core/Src/system_stm32h7xx.c **** if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
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40 .loc 1 193 3 is_stmt 1 view .LVU4
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41 .loc 1 193 32 is_stmt 0 view .LVU5
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42 000e 294B ldr r3, .L5+4
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43 0010 1B68 ldr r3, [r3]
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44 0012 03F00F03 and r3, r3, #15
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45 .loc 1 193 5 view .LVU6
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46 0016 022B cmp r3, #2
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47 0018 06D8 bhi .L2
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194:Core/Src/system_stm32h7xx.c **** {
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195:Core/Src/system_stm32h7xx.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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196:Core/Src/system_stm32h7xx.c **** MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
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48 .loc 1 196 5 is_stmt 1 view .LVU7
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49 001a 264A ldr r2, .L5+4
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50 001c 1368 ldr r3, [r2]
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51 001e 23F00F03 bic r3, r3, #15
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52 0022 43F00303 orr r3, r3, #3
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53 0026 1360 str r3, [r2]
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54 .L2:
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197:Core/Src/system_stm32h7xx.c **** }
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198:Core/Src/system_stm32h7xx.c ****
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199:Core/Src/system_stm32h7xx.c **** /* Set HSION bit */
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200:Core/Src/system_stm32h7xx.c **** RCC->CR |= RCC_CR_HSION;
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55 .loc 1 200 3 view .LVU8
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56 .loc 1 200 6 is_stmt 0 view .LVU9
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57 0028 234B ldr r3, .L5+8
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58 002a 1A68 ldr r2, [r3]
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59 .loc 1 200 11 view .LVU10
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60 002c 42F00102 orr r2, r2, #1
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61 0030 1A60 str r2, [r3]
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201:Core/Src/system_stm32h7xx.c ****
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202:Core/Src/system_stm32h7xx.c **** /* Reset CFGR register */
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203:Core/Src/system_stm32h7xx.c **** RCC->CFGR = 0x00000000;
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62 .loc 1 203 3 is_stmt 1 view .LVU11
|
||
63 .loc 1 203 13 is_stmt 0 view .LVU12
|
||
64 0032 0022 movs r2, #0
|
||
65 0034 1A61 str r2, [r3, #16]
|
||
204:Core/Src/system_stm32h7xx.c ****
|
||
205:Core/Src/system_stm32h7xx.c **** /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
|
||
206:Core/Src/system_stm32h7xx.c **** RCC->CR &= 0xEAF6ED7FU;
|
||
66 .loc 1 206 3 is_stmt 1 view .LVU13
|
||
67 .loc 1 206 6 is_stmt 0 view .LVU14
|
||
68 0036 1968 ldr r1, [r3]
|
||
69 .loc 1 206 11 view .LVU15
|
||
70 0038 204A ldr r2, .L5+12
|
||
71 003a 0A40 ands r2, r2, r1
|
||
72 003c 1A60 str r2, [r3]
|
||
207:Core/Src/system_stm32h7xx.c ****
|
||
208:Core/Src/system_stm32h7xx.c **** /* Decreasing the number of wait states because of lower CPU frequency */
|
||
209:Core/Src/system_stm32h7xx.c **** if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
|
||
73 .loc 1 209 3 is_stmt 1 view .LVU16
|
||
74 .loc 1 209 32 is_stmt 0 view .LVU17
|
||
75 003e 1D4B ldr r3, .L5+4
|
||
76 0040 1B68 ldr r3, [r3]
|
||
77 .loc 1 209 5 view .LVU18
|
||
ARM GAS /tmp/cchfFOsO.s page 6
|
||
|
||
|
||
78 0042 13F00C0F tst r3, #12
|
||
79 0046 06D0 beq .L3
|
||
210:Core/Src/system_stm32h7xx.c **** {
|
||
211:Core/Src/system_stm32h7xx.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
||
212:Core/Src/system_stm32h7xx.c **** MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
|
||
80 .loc 1 212 5 is_stmt 1 view .LVU19
|
||
81 0048 1A4A ldr r2, .L5+4
|
||
82 004a 1368 ldr r3, [r2]
|
||
83 004c 23F00F03 bic r3, r3, #15
|
||
84 0050 43F00303 orr r3, r3, #3
|
||
85 0054 1360 str r3, [r2]
|
||
86 .L3:
|
||
213:Core/Src/system_stm32h7xx.c **** }
|
||
214:Core/Src/system_stm32h7xx.c ****
|
||
215:Core/Src/system_stm32h7xx.c **** #if defined(D3_SRAM_BASE)
|
||
216:Core/Src/system_stm32h7xx.c **** /* Reset D1CFGR register */
|
||
217:Core/Src/system_stm32h7xx.c **** RCC->D1CFGR = 0x00000000;
|
||
218:Core/Src/system_stm32h7xx.c ****
|
||
219:Core/Src/system_stm32h7xx.c **** /* Reset D2CFGR register */
|
||
220:Core/Src/system_stm32h7xx.c **** RCC->D2CFGR = 0x00000000;
|
||
221:Core/Src/system_stm32h7xx.c ****
|
||
222:Core/Src/system_stm32h7xx.c **** /* Reset D3CFGR register */
|
||
223:Core/Src/system_stm32h7xx.c **** RCC->D3CFGR = 0x00000000;
|
||
224:Core/Src/system_stm32h7xx.c **** #else
|
||
225:Core/Src/system_stm32h7xx.c **** /* Reset CDCFGR1 register */
|
||
226:Core/Src/system_stm32h7xx.c **** RCC->CDCFGR1 = 0x00000000;
|
||
87 .loc 1 226 3 view .LVU20
|
||
88 .loc 1 226 16 is_stmt 0 view .LVU21
|
||
89 0056 184B ldr r3, .L5+8
|
||
90 0058 0022 movs r2, #0
|
||
91 005a 9A61 str r2, [r3, #24]
|
||
227:Core/Src/system_stm32h7xx.c ****
|
||
228:Core/Src/system_stm32h7xx.c **** /* Reset CDCFGR2 register */
|
||
229:Core/Src/system_stm32h7xx.c **** RCC->CDCFGR2 = 0x00000000;
|
||
92 .loc 1 229 3 is_stmt 1 view .LVU22
|
||
93 .loc 1 229 16 is_stmt 0 view .LVU23
|
||
94 005c DA61 str r2, [r3, #28]
|
||
230:Core/Src/system_stm32h7xx.c ****
|
||
231:Core/Src/system_stm32h7xx.c **** /* Reset SRDCFGR register */
|
||
232:Core/Src/system_stm32h7xx.c **** RCC->SRDCFGR = 0x00000000;
|
||
95 .loc 1 232 3 is_stmt 1 view .LVU24
|
||
96 .loc 1 232 16 is_stmt 0 view .LVU25
|
||
97 005e 1A62 str r2, [r3, #32]
|
||
233:Core/Src/system_stm32h7xx.c **** #endif
|
||
234:Core/Src/system_stm32h7xx.c **** /* Reset PLLCKSELR register */
|
||
235:Core/Src/system_stm32h7xx.c **** RCC->PLLCKSELR = 0x02020200;
|
||
98 .loc 1 235 3 is_stmt 1 view .LVU26
|
||
99 .loc 1 235 18 is_stmt 0 view .LVU27
|
||
100 0060 1749 ldr r1, .L5+16
|
||
101 0062 9962 str r1, [r3, #40]
|
||
236:Core/Src/system_stm32h7xx.c ****
|
||
237:Core/Src/system_stm32h7xx.c **** /* Reset PLLCFGR register */
|
||
238:Core/Src/system_stm32h7xx.c **** RCC->PLLCFGR = 0x01FF0000;
|
||
102 .loc 1 238 3 is_stmt 1 view .LVU28
|
||
103 .loc 1 238 16 is_stmt 0 view .LVU29
|
||
104 0064 1749 ldr r1, .L5+20
|
||
105 0066 D962 str r1, [r3, #44]
|
||
ARM GAS /tmp/cchfFOsO.s page 7
|
||
|
||
|
||
239:Core/Src/system_stm32h7xx.c **** /* Reset PLL1DIVR register */
|
||
240:Core/Src/system_stm32h7xx.c **** RCC->PLL1DIVR = 0x01010280;
|
||
106 .loc 1 240 3 is_stmt 1 view .LVU30
|
||
107 .loc 1 240 17 is_stmt 0 view .LVU31
|
||
108 0068 1749 ldr r1, .L5+24
|
||
109 006a 1963 str r1, [r3, #48]
|
||
241:Core/Src/system_stm32h7xx.c **** /* Reset PLL1FRACR register */
|
||
242:Core/Src/system_stm32h7xx.c **** RCC->PLL1FRACR = 0x00000000;
|
||
110 .loc 1 242 3 is_stmt 1 view .LVU32
|
||
111 .loc 1 242 18 is_stmt 0 view .LVU33
|
||
112 006c 5A63 str r2, [r3, #52]
|
||
243:Core/Src/system_stm32h7xx.c ****
|
||
244:Core/Src/system_stm32h7xx.c **** /* Reset PLL2DIVR register */
|
||
245:Core/Src/system_stm32h7xx.c **** RCC->PLL2DIVR = 0x01010280;
|
||
113 .loc 1 245 3 is_stmt 1 view .LVU34
|
||
114 .loc 1 245 17 is_stmt 0 view .LVU35
|
||
115 006e 9963 str r1, [r3, #56]
|
||
246:Core/Src/system_stm32h7xx.c ****
|
||
247:Core/Src/system_stm32h7xx.c **** /* Reset PLL2FRACR register */
|
||
248:Core/Src/system_stm32h7xx.c ****
|
||
249:Core/Src/system_stm32h7xx.c **** RCC->PLL2FRACR = 0x00000000;
|
||
116 .loc 1 249 3 is_stmt 1 view .LVU36
|
||
117 .loc 1 249 18 is_stmt 0 view .LVU37
|
||
118 0070 DA63 str r2, [r3, #60]
|
||
250:Core/Src/system_stm32h7xx.c **** /* Reset PLL3DIVR register */
|
||
251:Core/Src/system_stm32h7xx.c **** RCC->PLL3DIVR = 0x01010280;
|
||
119 .loc 1 251 3 is_stmt 1 view .LVU38
|
||
120 .loc 1 251 17 is_stmt 0 view .LVU39
|
||
121 0072 1964 str r1, [r3, #64]
|
||
252:Core/Src/system_stm32h7xx.c ****
|
||
253:Core/Src/system_stm32h7xx.c **** /* Reset PLL3FRACR register */
|
||
254:Core/Src/system_stm32h7xx.c **** RCC->PLL3FRACR = 0x00000000;
|
||
122 .loc 1 254 3 is_stmt 1 view .LVU40
|
||
123 .loc 1 254 18 is_stmt 0 view .LVU41
|
||
124 0074 5A64 str r2, [r3, #68]
|
||
255:Core/Src/system_stm32h7xx.c ****
|
||
256:Core/Src/system_stm32h7xx.c **** /* Reset HSEBYP bit */
|
||
257:Core/Src/system_stm32h7xx.c **** RCC->CR &= 0xFFFBFFFFU;
|
||
125 .loc 1 257 3 is_stmt 1 view .LVU42
|
||
126 .loc 1 257 6 is_stmt 0 view .LVU43
|
||
127 0076 1968 ldr r1, [r3]
|
||
128 .loc 1 257 11 view .LVU44
|
||
129 0078 21F48021 bic r1, r1, #262144
|
||
130 007c 1960 str r1, [r3]
|
||
258:Core/Src/system_stm32h7xx.c ****
|
||
259:Core/Src/system_stm32h7xx.c **** /* Disable all interrupts */
|
||
260:Core/Src/system_stm32h7xx.c **** RCC->CIER = 0x00000000;
|
||
131 .loc 1 260 3 is_stmt 1 view .LVU45
|
||
132 .loc 1 260 13 is_stmt 0 view .LVU46
|
||
133 007e 1A66 str r2, [r3, #96]
|
||
261:Core/Src/system_stm32h7xx.c ****
|
||
262:Core/Src/system_stm32h7xx.c **** #if (STM32H7_DEV_ID == 0x450UL)
|
||
263:Core/Src/system_stm32h7xx.c **** /* dual core CM7 or single core line */
|
||
264:Core/Src/system_stm32h7xx.c **** if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
|
||
265:Core/Src/system_stm32h7xx.c **** {
|
||
266:Core/Src/system_stm32h7xx.c **** /* if stm32h7 revY*/
|
||
267:Core/Src/system_stm32h7xx.c **** /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
|
||
ARM GAS /tmp/cchfFOsO.s page 8
|
||
|
||
|
||
268:Core/Src/system_stm32h7xx.c **** *((__IO uint32_t*)0x51008108) = 0x000000001U;
|
||
269:Core/Src/system_stm32h7xx.c **** }
|
||
270:Core/Src/system_stm32h7xx.c **** #endif /* STM32H7_DEV_ID */
|
||
271:Core/Src/system_stm32h7xx.c ****
|
||
272:Core/Src/system_stm32h7xx.c **** #if defined(DATA_IN_D2_SRAM)
|
||
273:Core/Src/system_stm32h7xx.c **** /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) *
|
||
274:Core/Src/system_stm32h7xx.c **** #if defined(RCC_AHB2ENR_D2SRAM3EN)
|
||
275:Core/Src/system_stm32h7xx.c **** RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
|
||
276:Core/Src/system_stm32h7xx.c **** #elif defined(RCC_AHB2ENR_D2SRAM2EN)
|
||
277:Core/Src/system_stm32h7xx.c **** RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
|
||
278:Core/Src/system_stm32h7xx.c **** #else
|
||
279:Core/Src/system_stm32h7xx.c **** RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
|
||
280:Core/Src/system_stm32h7xx.c **** #endif /* RCC_AHB2ENR_D2SRAM3EN */
|
||
281:Core/Src/system_stm32h7xx.c ****
|
||
282:Core/Src/system_stm32h7xx.c **** tmpreg = RCC->AHB2ENR;
|
||
283:Core/Src/system_stm32h7xx.c **** (void) tmpreg;
|
||
284:Core/Src/system_stm32h7xx.c **** #endif /* DATA_IN_D2_SRAM */
|
||
285:Core/Src/system_stm32h7xx.c ****
|
||
286:Core/Src/system_stm32h7xx.c **** #if defined(DUAL_CORE) && defined(CORE_CM4)
|
||
287:Core/Src/system_stm32h7xx.c **** /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
|
||
288:Core/Src/system_stm32h7xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
|
||
289:Core/Src/system_stm32h7xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AX
|
||
290:Core/Src/system_stm32h7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
|
||
291:Core/Src/system_stm32h7xx.c ****
|
||
292:Core/Src/system_stm32h7xx.c **** #else
|
||
293:Core/Src/system_stm32h7xx.c **** if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
|
||
134 .loc 1 293 3 is_stmt 1 view .LVU47
|
||
135 .loc 1 293 6 is_stmt 0 view .LVU48
|
||
136 0080 D3F83431 ldr r3, [r3, #308]
|
||
137 .loc 1 293 5 view .LVU49
|
||
138 0084 13F4805F tst r3, #4096
|
||
139 0088 10D1 bne .L1
|
||
294:Core/Src/system_stm32h7xx.c **** {
|
||
295:Core/Src/system_stm32h7xx.c **** /* Enable the FMC interface clock */
|
||
296:Core/Src/system_stm32h7xx.c **** SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
|
||
140 .loc 1 296 5 is_stmt 1 view .LVU50
|
||
141 008a 0B4B ldr r3, .L5+8
|
||
142 008c D3F83421 ldr r2, [r3, #308]
|
||
143 0090 42F48052 orr r2, r2, #4096
|
||
144 0094 C3F83421 str r2, [r3, #308]
|
||
297:Core/Src/system_stm32h7xx.c ****
|
||
298:Core/Src/system_stm32h7xx.c **** /*
|
||
299:Core/Src/system_stm32h7xx.c **** * Disable the FMC bank1 (enabled after reset).
|
||
300:Core/Src/system_stm32h7xx.c **** * This, prevents CPU speculation access on this bank which blocks the use of FMC during
|
||
301:Core/Src/system_stm32h7xx.c **** * 24us. During this time the others FMC master (such as LTDC) cannot use it!
|
||
302:Core/Src/system_stm32h7xx.c **** */
|
||
303:Core/Src/system_stm32h7xx.c **** FMC_Bank1_R->BTCR[0] = 0x000030D2;
|
||
145 .loc 1 303 5 view .LVU51
|
||
146 .loc 1 303 26 is_stmt 0 view .LVU52
|
||
147 0098 0C4A ldr r2, .L5+28
|
||
148 009a 43F2D201 movw r1, #12498
|
||
149 009e 1160 str r1, [r2]
|
||
304:Core/Src/system_stm32h7xx.c ****
|
||
305:Core/Src/system_stm32h7xx.c **** /* Disable the FMC interface clock */
|
||
306:Core/Src/system_stm32h7xx.c **** CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
|
||
150 .loc 1 306 5 is_stmt 1 view .LVU53
|
||
151 00a0 D3F83421 ldr r2, [r3, #308]
|
||
ARM GAS /tmp/cchfFOsO.s page 9
|
||
|
||
|
||
152 00a4 22F48052 bic r2, r2, #4096
|
||
153 00a8 C3F83421 str r2, [r3, #308]
|
||
154 .L1:
|
||
307:Core/Src/system_stm32h7xx.c **** }
|
||
308:Core/Src/system_stm32h7xx.c ****
|
||
309:Core/Src/system_stm32h7xx.c **** /* Configure the Vector Table location -------------------------------------*/
|
||
310:Core/Src/system_stm32h7xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
|
||
311:Core/Src/system_stm32h7xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AX
|
||
312:Core/Src/system_stm32h7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
|
||
313:Core/Src/system_stm32h7xx.c ****
|
||
314:Core/Src/system_stm32h7xx.c **** #endif /*DUAL_CORE && CORE_CM4*/
|
||
315:Core/Src/system_stm32h7xx.c **** }
|
||
155 .loc 1 315 1 is_stmt 0 view .LVU54
|
||
156 00ac 7047 bx lr
|
||
157 .L6:
|
||
158 00ae 00BF .align 2
|
||
159 .L5:
|
||
160 00b0 00ED00E0 .word -536810240
|
||
161 00b4 00200052 .word 1375739904
|
||
162 00b8 00440258 .word 1476543488
|
||
163 00bc 7FEDF6EA .word -352916097
|
||
164 00c0 00020202 .word 33686016
|
||
165 00c4 0000FF01 .word 33488896
|
||
166 00c8 80020101 .word 16843392
|
||
167 00cc 00400052 .word 1375748096
|
||
168 .cfi_endproc
|
||
169 .LFE335:
|
||
171 .section .text.SystemCoreClockUpdate,"ax",%progbits
|
||
172 .align 1
|
||
173 .global SystemCoreClockUpdate
|
||
174 .syntax unified
|
||
175 .thumb
|
||
176 .thumb_func
|
||
178 SystemCoreClockUpdate:
|
||
179 .LFB336:
|
||
316:Core/Src/system_stm32h7xx.c ****
|
||
317:Core/Src/system_stm32h7xx.c **** /**
|
||
318:Core/Src/system_stm32h7xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
|
||
319:Core/Src/system_stm32h7xx.c **** * The SystemCoreClock variable contains the core clock , it can
|
||
320:Core/Src/system_stm32h7xx.c **** * be used by the user application to setup the SysTick timer or configure
|
||
321:Core/Src/system_stm32h7xx.c **** * other parameters.
|
||
322:Core/Src/system_stm32h7xx.c **** *
|
||
323:Core/Src/system_stm32h7xx.c **** * @note Each time the core clock changes, this function must be called
|
||
324:Core/Src/system_stm32h7xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
|
||
325:Core/Src/system_stm32h7xx.c **** * based on this variable will be incorrect.
|
||
326:Core/Src/system_stm32h7xx.c **** *
|
||
327:Core/Src/system_stm32h7xx.c **** * @note - The system frequency computed by this function is not the real
|
||
328:Core/Src/system_stm32h7xx.c **** * frequency in the chip. It is calculated based on the predefined
|
||
329:Core/Src/system_stm32h7xx.c **** * constant and the selected clock source:
|
||
330:Core/Src/system_stm32h7xx.c **** *
|
||
331:Core/Src/system_stm32h7xx.c **** * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
|
||
332:Core/Src/system_stm32h7xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||
333:Core/Src/system_stm32h7xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||
334:Core/Src/system_stm32h7xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
|
||
335:Core/Src/system_stm32h7xx.c **** * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
|
||
336:Core/Src/system_stm32h7xx.c **** *
|
||
337:Core/Src/system_stm32h7xx.c **** * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||
ARM GAS /tmp/cchfFOsO.s page 10
|
||
|
||
|
||
338:Core/Src/system_stm32h7xx.c **** * 4 MHz) but the real value may vary depending on the variations
|
||
339:Core/Src/system_stm32h7xx.c **** * in voltage and temperature.
|
||
340:Core/Src/system_stm32h7xx.c **** * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||
341:Core/Src/system_stm32h7xx.c **** * 64 MHz) but the real value may vary depending on the variations
|
||
342:Core/Src/system_stm32h7xx.c **** * in voltage and temperature.
|
||
343:Core/Src/system_stm32h7xx.c **** *
|
||
344:Core/Src/system_stm32h7xx.c **** * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
|
||
345:Core/Src/system_stm32h7xx.c **** * 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||
346:Core/Src/system_stm32h7xx.c **** * frequency of the crystal used. Otherwise, this function may
|
||
347:Core/Src/system_stm32h7xx.c **** * have wrong result.
|
||
348:Core/Src/system_stm32h7xx.c **** *
|
||
349:Core/Src/system_stm32h7xx.c **** * - The result of this function could be not correct when using fractional
|
||
350:Core/Src/system_stm32h7xx.c **** * value for HSE crystal.
|
||
351:Core/Src/system_stm32h7xx.c **** * @param None
|
||
352:Core/Src/system_stm32h7xx.c **** * @retval None
|
||
353:Core/Src/system_stm32h7xx.c **** */
|
||
354:Core/Src/system_stm32h7xx.c **** void SystemCoreClockUpdate (void)
|
||
355:Core/Src/system_stm32h7xx.c **** {
|
||
180 .loc 1 355 1 is_stmt 1 view -0
|
||
181 .cfi_startproc
|
||
182 @ args = 0, pretend = 0, frame = 0
|
||
183 @ frame_needed = 0, uses_anonymous_args = 0
|
||
184 @ link register save eliminated.
|
||
185 0000 10B4 push {r4}
|
||
186 .cfi_def_cfa_offset 4
|
||
187 .cfi_offset 4, -4
|
||
356:Core/Src/system_stm32h7xx.c **** uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
|
||
188 .loc 1 356 3 view .LVU56
|
||
357:Core/Src/system_stm32h7xx.c **** uint32_t common_system_clock;
|
||
189 .loc 1 357 3 view .LVU57
|
||
358:Core/Src/system_stm32h7xx.c **** float_t fracn1, pllvco;
|
||
190 .loc 1 358 3 view .LVU58
|
||
359:Core/Src/system_stm32h7xx.c ****
|
||
360:Core/Src/system_stm32h7xx.c ****
|
||
361:Core/Src/system_stm32h7xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
|
||
362:Core/Src/system_stm32h7xx.c ****
|
||
363:Core/Src/system_stm32h7xx.c **** switch (RCC->CFGR & RCC_CFGR_SWS)
|
||
191 .loc 1 363 3 view .LVU59
|
||
192 .loc 1 363 14 is_stmt 0 view .LVU60
|
||
193 0002 7B4B ldr r3, .L20
|
||
194 0004 1B69 ldr r3, [r3, #16]
|
||
195 .loc 1 363 21 view .LVU61
|
||
196 0006 03F03803 and r3, r3, #56
|
||
197 .loc 1 363 3 view .LVU62
|
||
198 000a 182B cmp r3, #24
|
||
199 000c 00F2D280 bhi .L8
|
||
200 0010 DFE813F0 tbh [pc, r3, lsl #1]
|
||
201 .L10:
|
||
202 0014 1B00 .2byte (.L13-.L10)/2
|
||
203 0016 D000 .2byte (.L8-.L10)/2
|
||
204 0018 D000 .2byte (.L8-.L10)/2
|
||
205 001a D000 .2byte (.L8-.L10)/2
|
||
206 001c D000 .2byte (.L8-.L10)/2
|
||
207 001e D000 .2byte (.L8-.L10)/2
|
||
208 0020 D000 .2byte (.L8-.L10)/2
|
||
209 0022 D000 .2byte (.L8-.L10)/2
|
||
210 0024 1900 .2byte (.L12-.L10)/2
|
||
ARM GAS /tmp/cchfFOsO.s page 11
|
||
|
||
|
||
211 0026 D000 .2byte (.L8-.L10)/2
|
||
212 0028 D000 .2byte (.L8-.L10)/2
|
||
213 002a D000 .2byte (.L8-.L10)/2
|
||
214 002c D000 .2byte (.L8-.L10)/2
|
||
215 002e D000 .2byte (.L8-.L10)/2
|
||
216 0030 D000 .2byte (.L8-.L10)/2
|
||
217 0032 D000 .2byte (.L8-.L10)/2
|
||
218 0034 EC00 .2byte (.L18-.L10)/2
|
||
219 0036 D000 .2byte (.L8-.L10)/2
|
||
220 0038 D000 .2byte (.L8-.L10)/2
|
||
221 003a D000 .2byte (.L8-.L10)/2
|
||
222 003c D000 .2byte (.L8-.L10)/2
|
||
223 003e D000 .2byte (.L8-.L10)/2
|
||
224 0040 D000 .2byte (.L8-.L10)/2
|
||
225 0042 D000 .2byte (.L8-.L10)/2
|
||
226 0044 2200 .2byte (.L9-.L10)/2
|
||
227 .p2align 1
|
||
228 .L12:
|
||
229 0046 6B4A ldr r2, .L20+4
|
||
230 0048 BAE0 b .L11
|
||
231 .L13:
|
||
364:Core/Src/system_stm32h7xx.c **** {
|
||
365:Core/Src/system_stm32h7xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
||
366:Core/Src/system_stm32h7xx.c **** common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||
232 .loc 1 366 5 is_stmt 1 view .LVU63
|
||
233 .loc 1 366 57 is_stmt 0 view .LVU64
|
||
234 004a 694B ldr r3, .L20
|
||
235 004c 1B68 ldr r3, [r3]
|
||
236 .loc 1 366 78 view .LVU65
|
||
237 004e C3F3C103 ubfx r3, r3, #3, #2
|
||
238 .loc 1 366 25 view .LVU66
|
||
239 0052 694A ldr r2, .L20+8
|
||
240 0054 DA40 lsrs r2, r2, r3
|
||
241 .LVL0:
|
||
367:Core/Src/system_stm32h7xx.c **** break;
|
||
242 .loc 1 367 5 is_stmt 1 view .LVU67
|
||
243 0056 B3E0 b .L11
|
||
244 .LVL1:
|
||
245 .L9:
|
||
368:Core/Src/system_stm32h7xx.c ****
|
||
369:Core/Src/system_stm32h7xx.c **** case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
|
||
370:Core/Src/system_stm32h7xx.c **** common_system_clock = CSI_VALUE;
|
||
371:Core/Src/system_stm32h7xx.c **** break;
|
||
372:Core/Src/system_stm32h7xx.c ****
|
||
373:Core/Src/system_stm32h7xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
||
374:Core/Src/system_stm32h7xx.c **** common_system_clock = HSE_VALUE;
|
||
375:Core/Src/system_stm32h7xx.c **** break;
|
||
376:Core/Src/system_stm32h7xx.c ****
|
||
377:Core/Src/system_stm32h7xx.c **** case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
|
||
378:Core/Src/system_stm32h7xx.c ****
|
||
379:Core/Src/system_stm32h7xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
||
380:Core/Src/system_stm32h7xx.c **** SYSCLK = PLL_VCO / PLLR
|
||
381:Core/Src/system_stm32h7xx.c **** */
|
||
382:Core/Src/system_stm32h7xx.c **** pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
||
246 .loc 1 382 5 view .LVU68
|
||
247 .loc 1 382 21 is_stmt 0 view .LVU69
|
||
248 0058 654B ldr r3, .L20
|
||
ARM GAS /tmp/cchfFOsO.s page 12
|
||
|
||
|
||
249 005a 996A ldr r1, [r3, #40]
|
||
250 .loc 1 382 15 view .LVU70
|
||
251 005c 01F00301 and r1, r1, #3
|
||
252 .LVL2:
|
||
383:Core/Src/system_stm32h7xx.c **** pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
|
||
253 .loc 1 383 5 is_stmt 1 view .LVU71
|
||
254 .loc 1 383 17 is_stmt 0 view .LVU72
|
||
255 0060 9C6A ldr r4, [r3, #40]
|
||
256 .loc 1 383 10 view .LVU73
|
||
257 0062 C4F30512 ubfx r2, r4, #4, #6
|
||
258 .LVL3:
|
||
384:Core/Src/system_stm32h7xx.c **** pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
|
||
259 .loc 1 384 5 is_stmt 1 view .LVU74
|
||
260 .loc 1 384 22 is_stmt 0 view .LVU75
|
||
261 0066 D86A ldr r0, [r3, #44]
|
||
262 .loc 1 384 15 view .LVU76
|
||
263 0068 00F00100 and r0, r0, #1
|
||
264 .LVL4:
|
||
385:Core/Src/system_stm32h7xx.c **** fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
|
||
265 .loc 1 385 5 is_stmt 1 view .LVU77
|
||
266 .loc 1 385 50 is_stmt 0 view .LVU78
|
||
267 006c 5B6B ldr r3, [r3, #52]
|
||
268 .loc 1 385 85 view .LVU79
|
||
269 006e C3F3CC03 ubfx r3, r3, #3, #13
|
||
270 .loc 1 385 23 view .LVU80
|
||
271 0072 00FB03F3 mul r3, r0, r3
|
||
272 .loc 1 385 12 view .LVU81
|
||
273 0076 07EE903A vmov s15, r3 @ int
|
||
274 007a F8EE677A vcvt.f32.u32 s15, s15
|
||
275 .LVL5:
|
||
386:Core/Src/system_stm32h7xx.c ****
|
||
387:Core/Src/system_stm32h7xx.c **** if (pllm != 0U)
|
||
276 .loc 1 387 5 is_stmt 1 view .LVU82
|
||
277 .loc 1 387 8 is_stmt 0 view .LVU83
|
||
278 007e 14F47C7F tst r4, #1008
|
||
279 0082 00F09D80 beq .L11
|
||
388:Core/Src/system_stm32h7xx.c **** {
|
||
389:Core/Src/system_stm32h7xx.c **** switch (pllsource)
|
||
280 .loc 1 389 7 is_stmt 1 view .LVU84
|
||
281 0086 0129 cmp r1, #1
|
||
282 0088 36D0 beq .L14
|
||
283 008a 0229 cmp r1, #2
|
||
284 008c 51D0 beq .L15
|
||
285 008e 0029 cmp r1, #0
|
||
286 0090 6CD1 bne .L16
|
||
390:Core/Src/system_stm32h7xx.c **** {
|
||
391:Core/Src/system_stm32h7xx.c **** case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
|
||
392:Core/Src/system_stm32h7xx.c ****
|
||
393:Core/Src/system_stm32h7xx.c **** hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
||
287 .loc 1 393 9 view .LVU85
|
||
288 .loc 1 393 39 is_stmt 0 view .LVU86
|
||
289 0092 5748 ldr r0, .L20
|
||
290 .LVL6:
|
||
291 .loc 1 393 39 view .LVU87
|
||
292 0094 0168 ldr r1, [r0]
|
||
293 .LVL7:
|
||
294 .loc 1 393 60 view .LVU88
|
||
ARM GAS /tmp/cchfFOsO.s page 13
|
||
|
||
|
||
295 0096 C1F3C101 ubfx r1, r1, #3, #2
|
||
296 .loc 1 393 18 view .LVU89
|
||
297 009a 574B ldr r3, .L20+8
|
||
298 009c CB40 lsrs r3, r3, r1
|
||
299 .LVL8:
|
||
394:Core/Src/system_stm32h7xx.c **** pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL
|
||
300 .loc 1 394 9 is_stmt 1 view .LVU90
|
||
301 .loc 1 394 20 is_stmt 0 view .LVU91
|
||
302 009e 07EE103A vmov s14, r3 @ int
|
||
303 00a2 F8EE476A vcvt.f32.u32 s13, s14
|
||
304 .loc 1 394 40 view .LVU92
|
||
305 00a6 07EE102A vmov s14, r2 @ int
|
||
306 00aa B8EE476A vcvt.f32.u32 s12, s14
|
||
307 .loc 1 394 38 view .LVU93
|
||
308 00ae 86EE867A vdiv.f32 s14, s13, s12
|
||
309 .loc 1 394 81 view .LVU94
|
||
310 00b2 036B ldr r3, [r0, #48]
|
||
311 .LVL9:
|
||
312 .loc 1 394 67 view .LVU95
|
||
313 00b4 C3F30803 ubfx r3, r3, #0, #9
|
||
314 .loc 1 394 58 view .LVU96
|
||
315 00b8 06EE903A vmov s13, r3 @ int
|
||
316 00bc F8EE666A vcvt.f32.u32 s13, s13
|
||
317 .loc 1 394 120 view .LVU97
|
||
318 00c0 9FED4E6A vldr.32 s12, .L20+12
|
||
319 00c4 67EE867A vmul.f32 s15, s15, s12
|
||
320 .LVL10:
|
||
321 .loc 1 394 111 view .LVU98
|
||
322 00c8 76EEA77A vadd.f32 s15, s13, s15
|
||
323 .loc 1 394 138 view .LVU99
|
||
324 00cc F7EE006A vmov.f32 s13, #1.0e+0
|
||
325 00d0 77EEA67A vadd.f32 s15, s15, s13
|
||
326 .loc 1 394 16 view .LVU100
|
||
327 00d4 27EE277A vmul.f32 s14, s14, s15
|
||
328 .LVL11:
|
||
395:Core/Src/system_stm32h7xx.c ****
|
||
396:Core/Src/system_stm32h7xx.c **** break;
|
||
329 .loc 1 396 9 is_stmt 1 view .LVU101
|
||
330 .L17:
|
||
397:Core/Src/system_stm32h7xx.c ****
|
||
398:Core/Src/system_stm32h7xx.c **** case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
|
||
399:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_
|
||
400:Core/Src/system_stm32h7xx.c **** break;
|
||
401:Core/Src/system_stm32h7xx.c ****
|
||
402:Core/Src/system_stm32h7xx.c **** case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
|
||
403:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_
|
||
404:Core/Src/system_stm32h7xx.c **** break;
|
||
405:Core/Src/system_stm32h7xx.c ****
|
||
406:Core/Src/system_stm32h7xx.c **** default:
|
||
407:Core/Src/system_stm32h7xx.c **** hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
||
408:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
|
||
409:Core/Src/system_stm32h7xx.c **** break;
|
||
410:Core/Src/system_stm32h7xx.c **** }
|
||
411:Core/Src/system_stm32h7xx.c **** pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
|
||
331 .loc 1 411 7 view .LVU102
|
||
332 .loc 1 411 20 is_stmt 0 view .LVU103
|
||
333 00d8 454B ldr r3, .L20
|
||
ARM GAS /tmp/cchfFOsO.s page 14
|
||
|
||
|
||
334 00da 1B6B ldr r3, [r3, #48]
|
||
335 .loc 1 411 50 view .LVU104
|
||
336 00dc C3F34623 ubfx r3, r3, #9, #7
|
||
337 .loc 1 411 12 view .LVU105
|
||
338 00e0 0133 adds r3, r3, #1
|
||
339 .LVL12:
|
||
412:Core/Src/system_stm32h7xx.c **** common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
|
||
340 .loc 1 412 7 is_stmt 1 view .LVU106
|
||
341 .loc 1 412 57 is_stmt 0 view .LVU107
|
||
342 00e2 07EE903A vmov s15, r3 @ int
|
||
343 00e6 F8EE677A vcvt.f32.u32 s15, s15
|
||
344 .loc 1 412 40 view .LVU108
|
||
345 00ea C7EE276A vdiv.f32 s13, s14, s15
|
||
346 .loc 1 412 27 view .LVU109
|
||
347 00ee FCEEE67A vcvt.u32.f32 s15, s13
|
||
348 00f2 17EE902A vmov r2, s15 @ int
|
||
349 .LVL13:
|
||
350 .loc 1 412 27 view .LVU110
|
||
351 00f6 63E0 b .L11
|
||
352 .LVL14:
|
||
353 .L14:
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
354 .loc 1 399 11 is_stmt 1 view .LVU111
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
355 .loc 1 399 42 is_stmt 0 view .LVU112
|
||
356 00f8 07EE102A vmov s14, r2 @ int
|
||
357 00fc F8EE476A vcvt.f32.u32 s13, s14
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
358 .loc 1 399 40 view .LVU113
|
||
359 0100 9FED3F6A vldr.32 s12, .L20+16
|
||
360 0104 86EE267A vdiv.f32 s14, s12, s13
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
361 .loc 1 399 83 view .LVU114
|
||
362 0108 394B ldr r3, .L20
|
||
363 010a 1B6B ldr r3, [r3, #48]
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
364 .loc 1 399 69 view .LVU115
|
||
365 010c C3F30803 ubfx r3, r3, #0, #9
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
366 .loc 1 399 60 view .LVU116
|
||
367 0110 06EE903A vmov s13, r3 @ int
|
||
368 0114 F8EE666A vcvt.f32.u32 s13, s13
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
369 .loc 1 399 122 view .LVU117
|
||
370 0118 9FED386A vldr.32 s12, .L20+12
|
||
371 011c 67EE867A vmul.f32 s15, s15, s12
|
||
372 .LVL15:
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
373 .loc 1 399 113 view .LVU118
|
||
374 0120 76EEA77A vadd.f32 s15, s13, s15
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
375 .loc 1 399 140 view .LVU119
|
||
376 0124 F7EE006A vmov.f32 s13, #1.0e+0
|
||
377 0128 77EEA67A vadd.f32 s15, s15, s13
|
||
399:Core/Src/system_stm32h7xx.c **** break;
|
||
378 .loc 1 399 18 view .LVU120
|
||
379 012c 27EE277A vmul.f32 s14, s14, s15
|
||
ARM GAS /tmp/cchfFOsO.s page 15
|
||
|
||
|
||
380 .LVL16:
|
||
400:Core/Src/system_stm32h7xx.c ****
|
||
381 .loc 1 400 9 is_stmt 1 view .LVU121
|
||
382 0130 D2E7 b .L17
|
||
383 .LVL17:
|
||
384 .L15:
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
385 .loc 1 403 11 view .LVU122
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
386 .loc 1 403 42 is_stmt 0 view .LVU123
|
||
387 0132 07EE102A vmov s14, r2 @ int
|
||
388 0136 F8EE476A vcvt.f32.u32 s13, s14
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
389 .loc 1 403 40 view .LVU124
|
||
390 013a 9FED326A vldr.32 s12, .L20+20
|
||
391 013e 86EE267A vdiv.f32 s14, s12, s13
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
392 .loc 1 403 83 view .LVU125
|
||
393 0142 2B4B ldr r3, .L20
|
||
394 0144 1B6B ldr r3, [r3, #48]
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
395 .loc 1 403 69 view .LVU126
|
||
396 0146 C3F30803 ubfx r3, r3, #0, #9
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
397 .loc 1 403 60 view .LVU127
|
||
398 014a 06EE903A vmov s13, r3 @ int
|
||
399 014e F8EE666A vcvt.f32.u32 s13, s13
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
400 .loc 1 403 122 view .LVU128
|
||
401 0152 9FED2A6A vldr.32 s12, .L20+12
|
||
402 0156 67EE867A vmul.f32 s15, s15, s12
|
||
403 .LVL18:
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
404 .loc 1 403 113 view .LVU129
|
||
405 015a 76EEA77A vadd.f32 s15, s13, s15
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
406 .loc 1 403 140 view .LVU130
|
||
407 015e F7EE006A vmov.f32 s13, #1.0e+0
|
||
408 0162 77EEA67A vadd.f32 s15, s15, s13
|
||
403:Core/Src/system_stm32h7xx.c **** break;
|
||
409 .loc 1 403 18 view .LVU131
|
||
410 0166 27EE277A vmul.f32 s14, s14, s15
|
||
411 .LVL19:
|
||
404:Core/Src/system_stm32h7xx.c ****
|
||
412 .loc 1 404 9 is_stmt 1 view .LVU132
|
||
413 016a B5E7 b .L17
|
||
414 .LVL20:
|
||
415 .L16:
|
||
407:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
|
||
416 .loc 1 407 11 view .LVU133
|
||
407:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
|
||
417 .loc 1 407 41 is_stmt 0 view .LVU134
|
||
418 016c 2048 ldr r0, .L20
|
||
419 .LVL21:
|
||
407:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
|
||
420 .loc 1 407 41 view .LVU135
|
||
421 016e 0168 ldr r1, [r0]
|
||
ARM GAS /tmp/cchfFOsO.s page 16
|
||
|
||
|
||
422 .LVL22:
|
||
407:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
|
||
423 .loc 1 407 62 view .LVU136
|
||
424 0170 C1F3C101 ubfx r1, r1, #3, #2
|
||
407:Core/Src/system_stm32h7xx.c **** pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
|
||
425 .loc 1 407 20 view .LVU137
|
||
426 0174 204B ldr r3, .L20+8
|
||
427 0176 CB40 lsrs r3, r3, r1
|
||
428 .LVL23:
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
429 .loc 1 408 11 is_stmt 1 view .LVU138
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
430 .loc 1 408 21 is_stmt 0 view .LVU139
|
||
431 0178 07EE103A vmov s14, r3 @ int
|
||
432 017c F8EE476A vcvt.f32.u32 s13, s14
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
433 .loc 1 408 41 view .LVU140
|
||
434 0180 07EE102A vmov s14, r2 @ int
|
||
435 0184 B8EE476A vcvt.f32.u32 s12, s14
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
436 .loc 1 408 39 view .LVU141
|
||
437 0188 86EE867A vdiv.f32 s14, s13, s12
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
438 .loc 1 408 82 view .LVU142
|
||
439 018c 036B ldr r3, [r0, #48]
|
||
440 .LVL24:
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
441 .loc 1 408 68 view .LVU143
|
||
442 018e C3F30803 ubfx r3, r3, #0, #9
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
443 .loc 1 408 59 view .LVU144
|
||
444 0192 06EE903A vmov s13, r3 @ int
|
||
445 0196 F8EE666A vcvt.f32.u32 s13, s13
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
446 .loc 1 408 121 view .LVU145
|
||
447 019a 9FED186A vldr.32 s12, .L20+12
|
||
448 019e 67EE867A vmul.f32 s15, s15, s12
|
||
449 .LVL25:
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
450 .loc 1 408 112 view .LVU146
|
||
451 01a2 76EEA77A vadd.f32 s15, s13, s15
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
452 .loc 1 408 139 view .LVU147
|
||
453 01a6 F7EE006A vmov.f32 s13, #1.0e+0
|
||
454 01aa 77EEA67A vadd.f32 s15, s15, s13
|
||
408:Core/Src/system_stm32h7xx.c **** break;
|
||
455 .loc 1 408 18 view .LVU148
|
||
456 01ae 27EE277A vmul.f32 s14, s14, s15
|
||
457 .LVL26:
|
||
409:Core/Src/system_stm32h7xx.c **** }
|
||
458 .loc 1 409 9 is_stmt 1 view .LVU149
|
||
459 01b2 91E7 b .L17
|
||
460 .LVL27:
|
||
461 .L8:
|
||
413:Core/Src/system_stm32h7xx.c **** }
|
||
414:Core/Src/system_stm32h7xx.c **** else
|
||
415:Core/Src/system_stm32h7xx.c **** {
|
||
ARM GAS /tmp/cchfFOsO.s page 17
|
||
|
||
|
||
416:Core/Src/system_stm32h7xx.c **** common_system_clock = 0U;
|
||
417:Core/Src/system_stm32h7xx.c **** }
|
||
418:Core/Src/system_stm32h7xx.c **** break;
|
||
419:Core/Src/system_stm32h7xx.c ****
|
||
420:Core/Src/system_stm32h7xx.c **** default:
|
||
421:Core/Src/system_stm32h7xx.c **** common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||
462 .loc 1 421 5 view .LVU150
|
||
463 .loc 1 421 57 is_stmt 0 view .LVU151
|
||
464 01b4 0E4B ldr r3, .L20
|
||
465 01b6 1B68 ldr r3, [r3]
|
||
466 .loc 1 421 78 view .LVU152
|
||
467 01b8 C3F3C103 ubfx r3, r3, #3, #2
|
||
468 .loc 1 421 25 view .LVU153
|
||
469 01bc 0E4A ldr r2, .L20+8
|
||
470 01be DA40 lsrs r2, r2, r3
|
||
471 .LVL28:
|
||
422:Core/Src/system_stm32h7xx.c **** break;
|
||
472 .loc 1 422 5 is_stmt 1 view .LVU154
|
||
473 .L11:
|
||
423:Core/Src/system_stm32h7xx.c **** }
|
||
424:Core/Src/system_stm32h7xx.c ****
|
||
425:Core/Src/system_stm32h7xx.c **** /* Compute SystemClock frequency --------------------------------------------------*/
|
||
426:Core/Src/system_stm32h7xx.c **** #if defined (RCC_D1CFGR_D1CPRE)
|
||
427:Core/Src/system_stm32h7xx.c **** tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
|
||
428:Core/Src/system_stm32h7xx.c ****
|
||
429:Core/Src/system_stm32h7xx.c **** /* common_system_clock frequency : CM7 CPU frequency */
|
||
430:Core/Src/system_stm32h7xx.c **** common_system_clock >>= tmp;
|
||
431:Core/Src/system_stm32h7xx.c ****
|
||
432:Core/Src/system_stm32h7xx.c **** /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
|
||
433:Core/Src/system_stm32h7xx.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_
|
||
434:Core/Src/system_stm32h7xx.c ****
|
||
435:Core/Src/system_stm32h7xx.c **** #else
|
||
436:Core/Src/system_stm32h7xx.c **** tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
|
||
474 .loc 1 436 3 view .LVU155
|
||
475 .loc 1 436 30 is_stmt 0 view .LVU156
|
||
476 01c0 0B48 ldr r0, .L20
|
||
477 01c2 8369 ldr r3, [r0, #24]
|
||
478 .loc 1 436 61 view .LVU157
|
||
479 01c4 C3F30323 ubfx r3, r3, #8, #4
|
||
480 .loc 1 436 25 view .LVU158
|
||
481 01c8 0F49 ldr r1, .L20+24
|
||
482 01ca CB5C ldrb r3, [r1, r3] @ zero_extendqisi2
|
||
483 .LVL29:
|
||
437:Core/Src/system_stm32h7xx.c ****
|
||
438:Core/Src/system_stm32h7xx.c **** /* common_system_clock frequency : CM7 CPU frequency */
|
||
439:Core/Src/system_stm32h7xx.c **** common_system_clock >>= tmp;
|
||
484 .loc 1 439 3 is_stmt 1 view .LVU159
|
||
485 .loc 1 439 23 is_stmt 0 view .LVU160
|
||
486 01cc DA40 lsrs r2, r2, r3
|
||
487 .LVL30:
|
||
440:Core/Src/system_stm32h7xx.c ****
|
||
441:Core/Src/system_stm32h7xx.c **** /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
|
||
442:Core/Src/system_stm32h7xx.c **** SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RC
|
||
488 .loc 1 442 3 is_stmt 1 view .LVU161
|
||
489 .loc 1 442 66 is_stmt 0 view .LVU162
|
||
490 01ce 8369 ldr r3, [r0, #24]
|
||
491 .LVL31:
|
||
ARM GAS /tmp/cchfFOsO.s page 18
|
||
|
||
|
||
492 .loc 1 442 95 view .LVU163
|
||
493 01d0 03F00F03 and r3, r3, #15
|
||
494 .loc 1 442 61 view .LVU164
|
||
495 01d4 CB5C ldrb r3, [r1, r3] @ zero_extendqisi2
|
||
496 .loc 1 442 121 view .LVU165
|
||
497 01d6 03F01F03 and r3, r3, #31
|
||
498 .loc 1 442 40 view .LVU166
|
||
499 01da 22FA03F3 lsr r3, r2, r3
|
||
500 .loc 1 442 17 view .LVU167
|
||
501 01de 0B49 ldr r1, .L20+28
|
||
502 .loc 1 442 17 view .LVU168
|
||
503 01e0 0B60 str r3, [r1]
|
||
443:Core/Src/system_stm32h7xx.c ****
|
||
444:Core/Src/system_stm32h7xx.c **** #endif
|
||
445:Core/Src/system_stm32h7xx.c ****
|
||
446:Core/Src/system_stm32h7xx.c **** #if defined(DUAL_CORE) && defined(CORE_CM4)
|
||
447:Core/Src/system_stm32h7xx.c **** SystemCoreClock = SystemD2Clock;
|
||
448:Core/Src/system_stm32h7xx.c **** #else
|
||
449:Core/Src/system_stm32h7xx.c **** SystemCoreClock = common_system_clock;
|
||
504 .loc 1 449 3 is_stmt 1 view .LVU169
|
||
505 .loc 1 449 19 is_stmt 0 view .LVU170
|
||
506 01e2 0B4B ldr r3, .L20+32
|
||
507 01e4 1A60 str r2, [r3]
|
||
450:Core/Src/system_stm32h7xx.c **** #endif /* DUAL_CORE && CORE_CM4 */
|
||
451:Core/Src/system_stm32h7xx.c **** }
|
||
508 .loc 1 451 1 view .LVU171
|
||
509 01e6 5DF8044B ldr r4, [sp], #4
|
||
510 .cfi_remember_state
|
||
511 .cfi_restore 4
|
||
512 .cfi_def_cfa_offset 0
|
||
513 01ea 7047 bx lr
|
||
514 .LVL32:
|
||
515 .L18:
|
||
516 .cfi_restore_state
|
||
374:Core/Src/system_stm32h7xx.c **** break;
|
||
517 .loc 1 374 25 view .LVU172
|
||
518 01ec 094A ldr r2, .L20+36
|
||
519 01ee E7E7 b .L11
|
||
520 .L21:
|
||
521 .align 2
|
||
522 .L20:
|
||
523 01f0 00440258 .word 1476543488
|
||
524 01f4 00093D00 .word 4000000
|
||
525 01f8 0090D003 .word 64000000
|
||
526 01fc 00000039 .word 956301312
|
||
527 0200 0024744A .word 1249125376
|
||
528 0204 001BB74B .word 1270291200
|
||
529 0208 00000000 .word D1CorePrescTable
|
||
530 020c 00000000 .word SystemD2Clock
|
||
531 0210 00000000 .word SystemCoreClock
|
||
532 0214 00366E01 .word 24000000
|
||
533 .cfi_endproc
|
||
534 .LFE336:
|
||
536 .section .text.ExitRun0Mode,"ax",%progbits
|
||
537 .align 1
|
||
538 .global ExitRun0Mode
|
||
539 .syntax unified
|
||
ARM GAS /tmp/cchfFOsO.s page 19
|
||
|
||
|
||
540 .thumb
|
||
541 .thumb_func
|
||
543 ExitRun0Mode:
|
||
544 .LFB337:
|
||
452:Core/Src/system_stm32h7xx.c ****
|
||
453:Core/Src/system_stm32h7xx.c **** /**
|
||
454:Core/Src/system_stm32h7xx.c **** * @brief Exit Run* mode and Configure the system Power Supply
|
||
455:Core/Src/system_stm32h7xx.c **** *
|
||
456:Core/Src/system_stm32h7xx.c **** * @note This function exits the Run* mode and configures the system power supply
|
||
457:Core/Src/system_stm32h7xx.c **** * according to the definition to be used at compilation preprocessing level.
|
||
458:Core/Src/system_stm32h7xx.c **** * The application shall set one of the following configuration option:
|
||
459:Core/Src/system_stm32h7xx.c **** * - PWR_LDO_SUPPLY
|
||
460:Core/Src/system_stm32h7xx.c **** * - PWR_DIRECT_SMPS_SUPPLY
|
||
461:Core/Src/system_stm32h7xx.c **** * - PWR_EXTERNAL_SOURCE_SUPPLY
|
||
462:Core/Src/system_stm32h7xx.c **** * - PWR_SMPS_1V8_SUPPLIES_LDO
|
||
463:Core/Src/system_stm32h7xx.c **** * - PWR_SMPS_2V5_SUPPLIES_LDO
|
||
464:Core/Src/system_stm32h7xx.c **** * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
|
||
465:Core/Src/system_stm32h7xx.c **** * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
|
||
466:Core/Src/system_stm32h7xx.c **** * - PWR_SMPS_1V8_SUPPLIES_EXT
|
||
467:Core/Src/system_stm32h7xx.c **** * - PWR_SMPS_2V5_SUPPLIES_EXT
|
||
468:Core/Src/system_stm32h7xx.c **** *
|
||
469:Core/Src/system_stm32h7xx.c **** * @note The function modifies the PWR->CR3 register to enable or disable specific
|
||
470:Core/Src/system_stm32h7xx.c **** * power supply modes and waits until the voltage level flag is set, indicating
|
||
471:Core/Src/system_stm32h7xx.c **** * that the power supply configuration is stable.
|
||
472:Core/Src/system_stm32h7xx.c **** *
|
||
473:Core/Src/system_stm32h7xx.c **** * @param None
|
||
474:Core/Src/system_stm32h7xx.c **** * @retval None
|
||
475:Core/Src/system_stm32h7xx.c **** */
|
||
476:Core/Src/system_stm32h7xx.c **** void ExitRun0Mode(void)
|
||
477:Core/Src/system_stm32h7xx.c **** {
|
||
545 .loc 1 477 1 is_stmt 1 view -0
|
||
546 .cfi_startproc
|
||
547 @ args = 0, pretend = 0, frame = 0
|
||
548 @ frame_needed = 0, uses_anonymous_args = 0
|
||
549 @ link register save eliminated.
|
||
478:Core/Src/system_stm32h7xx.c **** #if defined(USE_PWR_LDO_SUPPLY)
|
||
479:Core/Src/system_stm32h7xx.c **** #if defined(SMPS)
|
||
480:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode by disabling SMPS and enabling LDO */
|
||
481:Core/Src/system_stm32h7xx.c **** PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN;
|
||
482:Core/Src/system_stm32h7xx.c **** #else
|
||
483:Core/Src/system_stm32h7xx.c **** /* Enable LDO mode */
|
||
484:Core/Src/system_stm32h7xx.c **** PWR->CR3 |= PWR_CR3_LDOEN;
|
||
550 .loc 1 484 5 view .LVU174
|
||
551 .loc 1 484 8 is_stmt 0 view .LVU175
|
||
552 0000 054A ldr r2, .L24
|
||
553 0002 D368 ldr r3, [r2, #12]
|
||
554 .loc 1 484 14 view .LVU176
|
||
555 0004 43F00203 orr r3, r3, #2
|
||
556 0008 D360 str r3, [r2, #12]
|
||
485:Core/Src/system_stm32h7xx.c **** #endif /* SMPS */
|
||
486:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
487:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
557 .loc 1 487 3 is_stmt 1 view .LVU177
|
||
558 .L23:
|
||
488:Core/Src/system_stm32h7xx.c **** {}
|
||
559 .loc 1 488 4 view .LVU178
|
||
487:Core/Src/system_stm32h7xx.c **** {}
|
||
ARM GAS /tmp/cchfFOsO.s page 20
|
||
|
||
|
||
560 .loc 1 487 43 discriminator 1 view .LVU179
|
||
487:Core/Src/system_stm32h7xx.c **** {}
|
||
561 .loc 1 487 14 is_stmt 0 discriminator 1 view .LVU180
|
||
562 000a 034B ldr r3, .L24
|
||
563 000c 5B68 ldr r3, [r3, #4]
|
||
487:Core/Src/system_stm32h7xx.c **** {}
|
||
564 .loc 1 487 43 discriminator 1 view .LVU181
|
||
565 000e 13F4005F tst r3, #8192
|
||
566 0012 FAD0 beq .L23
|
||
489:Core/Src/system_stm32h7xx.c **** #elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY)
|
||
490:Core/Src/system_stm32h7xx.c **** #if defined(SMPS)
|
||
491:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode */
|
||
492:Core/Src/system_stm32h7xx.c **** PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
|
||
493:Core/Src/system_stm32h7xx.c **** #else
|
||
494:Core/Src/system_stm32h7xx.c **** PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
|
||
495:Core/Src/system_stm32h7xx.c **** #endif /* SMPS */
|
||
496:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
497:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
498:Core/Src/system_stm32h7xx.c **** {}
|
||
499:Core/Src/system_stm32h7xx.c **** #elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS)
|
||
500:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode */
|
||
501:Core/Src/system_stm32h7xx.c **** PWR->CR3 &= ~(PWR_CR3_LDOEN);
|
||
502:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
503:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
504:Core/Src/system_stm32h7xx.c **** {}
|
||
505:Core/Src/system_stm32h7xx.c **** #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS)
|
||
506:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode */
|
||
507:Core/Src/system_stm32h7xx.c **** PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||
508:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
509:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
510:Core/Src/system_stm32h7xx.c **** {}
|
||
511:Core/Src/system_stm32h7xx.c **** #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS)
|
||
512:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode */
|
||
513:Core/Src/system_stm32h7xx.c **** PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||
514:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
515:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
516:Core/Src/system_stm32h7xx.c **** {}
|
||
517:Core/Src/system_stm32h7xx.c **** #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
|
||
518:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode */
|
||
519:Core/Src/system_stm32h7xx.c **** PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||
520:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
521:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
522:Core/Src/system_stm32h7xx.c **** {}
|
||
523:Core/Src/system_stm32h7xx.c **** #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
|
||
524:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode */
|
||
525:Core/Src/system_stm32h7xx.c **** PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||
526:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
527:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
528:Core/Src/system_stm32h7xx.c **** {}
|
||
529:Core/Src/system_stm32h7xx.c **** #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS)
|
||
530:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode */
|
||
531:Core/Src/system_stm32h7xx.c **** PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPS
|
||
532:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
533:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
534:Core/Src/system_stm32h7xx.c **** {}
|
||
535:Core/Src/system_stm32h7xx.c **** #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS)
|
||
536:Core/Src/system_stm32h7xx.c **** /* Exit Run* mode */
|
||
ARM GAS /tmp/cchfFOsO.s page 21
|
||
|
||
|
||
537:Core/Src/system_stm32h7xx.c **** PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPS
|
||
538:Core/Src/system_stm32h7xx.c **** /* Wait till voltage level flag is set */
|
||
539:Core/Src/system_stm32h7xx.c **** while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||
540:Core/Src/system_stm32h7xx.c **** {}
|
||
541:Core/Src/system_stm32h7xx.c **** #else
|
||
542:Core/Src/system_stm32h7xx.c **** /* No system power supply configuration is selected at exit Run* mode */
|
||
543:Core/Src/system_stm32h7xx.c **** #endif /* USE_PWR_LDO_SUPPLY */
|
||
544:Core/Src/system_stm32h7xx.c **** }
|
||
567 .loc 1 544 1 view .LVU182
|
||
568 0014 7047 bx lr
|
||
569 .L25:
|
||
570 0016 00BF .align 2
|
||
571 .L24:
|
||
572 0018 00480258 .word 1476544512
|
||
573 .cfi_endproc
|
||
574 .LFE337:
|
||
576 .global D1CorePrescTable
|
||
577 .section .rodata.D1CorePrescTable,"a"
|
||
578 .align 2
|
||
581 D1CorePrescTable:
|
||
582 0000 00000000 .ascii "\000\000\000\000\001\002\003\004\001\002\003\004\006"
|
||
582 01020304
|
||
582 01020304
|
||
582 06
|
||
583 000d 070809 .ascii "\007\010\011"
|
||
584 .global SystemD2Clock
|
||
585 .section .data.SystemD2Clock,"aw"
|
||
586 .align 2
|
||
589 SystemD2Clock:
|
||
590 0000 0090D003 .word 64000000
|
||
591 .global SystemCoreClock
|
||
592 .section .data.SystemCoreClock,"aw"
|
||
593 .align 2
|
||
596 SystemCoreClock:
|
||
597 0000 0090D003 .word 64000000
|
||
598 .text
|
||
599 .Letext0:
|
||
600 .file 2 "/home/k/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-ea
|
||
601 .file 3 "/home/k/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-ea
|
||
602 .file 4 "Drivers/CMSIS/Include/core_cm7.h"
|
||
603 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h"
|
||
604 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h"
|
||
605 .file 7 "/home/k/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-ea
|
||
ARM GAS /tmp/cchfFOsO.s page 22
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 system_stm32h7xx.c
|
||
/tmp/cchfFOsO.s:20 .text.SystemInit:00000000 $t
|
||
/tmp/cchfFOsO.s:26 .text.SystemInit:00000000 SystemInit
|
||
/tmp/cchfFOsO.s:160 .text.SystemInit:000000b0 $d
|
||
/tmp/cchfFOsO.s:172 .text.SystemCoreClockUpdate:00000000 $t
|
||
/tmp/cchfFOsO.s:178 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
|
||
/tmp/cchfFOsO.s:202 .text.SystemCoreClockUpdate:00000014 $d
|
||
/tmp/cchfFOsO.s:227 .text.SystemCoreClockUpdate:00000046 $t
|
||
/tmp/cchfFOsO.s:523 .text.SystemCoreClockUpdate:000001f0 $d
|
||
/tmp/cchfFOsO.s:581 .rodata.D1CorePrescTable:00000000 D1CorePrescTable
|
||
/tmp/cchfFOsO.s:589 .data.SystemD2Clock:00000000 SystemD2Clock
|
||
/tmp/cchfFOsO.s:596 .data.SystemCoreClock:00000000 SystemCoreClock
|
||
/tmp/cchfFOsO.s:537 .text.ExitRun0Mode:00000000 $t
|
||
/tmp/cchfFOsO.s:543 .text.ExitRun0Mode:00000000 ExitRun0Mode
|
||
/tmp/cchfFOsO.s:572 .text.ExitRun0Mode:00000018 $d
|
||
/tmp/cchfFOsO.s:578 .rodata.D1CorePrescTable:00000000 $d
|
||
/tmp/cchfFOsO.s:586 .data.SystemD2Clock:00000000 $d
|
||
/tmp/cchfFOsO.s:593 .data.SystemCoreClock:00000000 $d
|
||
|
||
NO UNDEFINED SYMBOLS
|