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sensor-node/Software/build/debug/main.lst

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ARM GAS /tmp/cckN5aRQ.s page 1
1 .cpu cortex-m7
2 .arch armv7e-m
3 .fpu fpv5-d16
4 .eabi_attribute 28, 1
5 .eabi_attribute 20, 1
6 .eabi_attribute 21, 1
7 .eabi_attribute 23, 3
8 .eabi_attribute 24, 1
9 .eabi_attribute 25, 1
10 .eabi_attribute 26, 1
11 .eabi_attribute 30, 1
12 .eabi_attribute 34, 1
13 .eabi_attribute 18, 4
14 .file "main.c"
15 .text
16 .Ltext0:
17 .cfi_sections .debug_frame
18 .file 1 "Core/Src/main.c"
19 .section .text.MPU_Config,"ax",%progbits
20 .align 1
21 .syntax unified
22 .thumb
23 .thumb_func
25 MPU_Config:
26 .LFB347:
1:Core/Src/main.c **** /* USER CODE BEGIN Header */
2:Core/Src/main.c **** /**
3:Core/Src/main.c **** ******************************************************************************
4:Core/Src/main.c **** * @file : main.c
5:Core/Src/main.c **** * @brief : Main program body
6:Core/Src/main.c **** ******************************************************************************
7:Core/Src/main.c **** * @attention
8:Core/Src/main.c **** *
9:Core/Src/main.c **** * Copyright (c) 2025 STMicroelectronics.
10:Core/Src/main.c **** * All rights reserved.
11:Core/Src/main.c **** *
12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file
13:Core/Src/main.c **** * in the root directory of this software component.
14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
15:Core/Src/main.c **** *
16:Core/Src/main.c **** ******************************************************************************
17:Core/Src/main.c **** */
18:Core/Src/main.c **** /* USER CODE END Header */
19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
20:Core/Src/main.c **** #include "main.h"
21:Core/Src/main.c ****
22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
23:Core/Src/main.c **** /* USER CODE BEGIN Includes */
24:Core/Src/main.c ****
25:Core/Src/main.c **** /* USER CODE END Includes */
26:Core/Src/main.c ****
27:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
28:Core/Src/main.c **** /* USER CODE BEGIN PTD */
29:Core/Src/main.c ****
30:Core/Src/main.c **** /* USER CODE END PTD */
31:Core/Src/main.c ****
32:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
ARM GAS /tmp/cckN5aRQ.s page 2
33:Core/Src/main.c **** /* USER CODE BEGIN PD */
34:Core/Src/main.c ****
35:Core/Src/main.c **** /* USER CODE END PD */
36:Core/Src/main.c ****
37:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
38:Core/Src/main.c **** /* USER CODE BEGIN PM */
39:Core/Src/main.c ****
40:Core/Src/main.c **** /* USER CODE END PM */
41:Core/Src/main.c ****
42:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
43:Core/Src/main.c **** ADC_HandleTypeDef hadc1;
44:Core/Src/main.c **** DMA_HandleTypeDef hdma_adc1;
45:Core/Src/main.c ****
46:Core/Src/main.c **** FDCAN_HandleTypeDef hfdcan1;
47:Core/Src/main.c **** FDCAN_HandleTypeDef hfdcan2;
48:Core/Src/main.c ****
49:Core/Src/main.c **** TIM_HandleTypeDef htim1;
50:Core/Src/main.c **** TIM_HandleTypeDef htim3;
51:Core/Src/main.c **** TIM_HandleTypeDef htim4;
52:Core/Src/main.c **** TIM_HandleTypeDef htim6;
53:Core/Src/main.c **** TIM_HandleTypeDef htim8;
54:Core/Src/main.c ****
55:Core/Src/main.c **** /* USER CODE BEGIN PV */
56:Core/Src/main.c ****
57:Core/Src/main.c **** /* USER CODE END PV */
58:Core/Src/main.c ****
59:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
60:Core/Src/main.c **** void SystemClock_Config(void);
61:Core/Src/main.c **** static void MPU_Config(void);
62:Core/Src/main.c **** static void MX_GPIO_Init(void);
63:Core/Src/main.c **** static void MX_DMA_Init(void);
64:Core/Src/main.c **** static void MX_ADC1_Init(void);
65:Core/Src/main.c **** static void MX_FDCAN1_Init(void);
66:Core/Src/main.c **** static void MX_FDCAN2_Init(void);
67:Core/Src/main.c **** static void MX_TIM1_Init(void);
68:Core/Src/main.c **** static void MX_TIM3_Init(void);
69:Core/Src/main.c **** static void MX_TIM4_Init(void);
70:Core/Src/main.c **** static void MX_TIM8_Init(void);
71:Core/Src/main.c **** static void MX_TIM6_Init(void);
72:Core/Src/main.c **** /* USER CODE BEGIN PFP */
73:Core/Src/main.c ****
74:Core/Src/main.c **** /* USER CODE END PFP */
75:Core/Src/main.c ****
76:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
77:Core/Src/main.c **** /* USER CODE BEGIN 0 */
78:Core/Src/main.c ****
79:Core/Src/main.c **** /* USER CODE END 0 */
80:Core/Src/main.c ****
81:Core/Src/main.c **** /**
82:Core/Src/main.c **** * @brief The application entry point.
83:Core/Src/main.c **** * @retval int
84:Core/Src/main.c **** */
85:Core/Src/main.c **** int main(void)
86:Core/Src/main.c **** {
87:Core/Src/main.c ****
88:Core/Src/main.c **** /* USER CODE BEGIN 1 */
89:Core/Src/main.c ****
ARM GAS /tmp/cckN5aRQ.s page 3
90:Core/Src/main.c **** /* USER CODE END 1 */
91:Core/Src/main.c ****
92:Core/Src/main.c **** /* MPU Configuration--------------------------------------------------------*/
93:Core/Src/main.c **** MPU_Config();
94:Core/Src/main.c ****
95:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/
96:Core/Src/main.c ****
97:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
98:Core/Src/main.c **** HAL_Init();
99:Core/Src/main.c ****
100:Core/Src/main.c **** /* USER CODE BEGIN Init */
101:Core/Src/main.c ****
102:Core/Src/main.c **** /* USER CODE END Init */
103:Core/Src/main.c ****
104:Core/Src/main.c **** /* Configure the system clock */
105:Core/Src/main.c **** SystemClock_Config();
106:Core/Src/main.c ****
107:Core/Src/main.c **** /* USER CODE BEGIN SysInit */
108:Core/Src/main.c ****
109:Core/Src/main.c **** /* USER CODE END SysInit */
110:Core/Src/main.c ****
111:Core/Src/main.c **** /* Initialize all configured peripherals */
112:Core/Src/main.c **** MX_GPIO_Init();
113:Core/Src/main.c **** MX_DMA_Init();
114:Core/Src/main.c **** MX_ADC1_Init();
115:Core/Src/main.c **** MX_FDCAN1_Init();
116:Core/Src/main.c **** MX_FDCAN2_Init();
117:Core/Src/main.c **** MX_TIM1_Init();
118:Core/Src/main.c **** MX_TIM3_Init();
119:Core/Src/main.c **** MX_TIM4_Init();
120:Core/Src/main.c **** MX_TIM8_Init();
121:Core/Src/main.c **** MX_TIM6_Init();
122:Core/Src/main.c **** /* USER CODE BEGIN 2 */
123:Core/Src/main.c ****
124:Core/Src/main.c **** /* USER CODE END 2 */
125:Core/Src/main.c ****
126:Core/Src/main.c **** /* Infinite loop */
127:Core/Src/main.c **** /* USER CODE BEGIN WHILE */
128:Core/Src/main.c **** while (1)
129:Core/Src/main.c **** {
130:Core/Src/main.c **** /* USER CODE END WHILE */
131:Core/Src/main.c ****
132:Core/Src/main.c **** /* USER CODE BEGIN 3 */
133:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_R_GPIO_Port, STATUS_R_Pin, GPIO_PIN_SET);
134:Core/Src/main.c **** HAL_Delay(500);
135:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_R_GPIO_Port, STATUS_R_Pin, GPIO_PIN_RESET);
136:Core/Src/main.c **** HAL_Delay(500);
137:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_G_GPIO_Port, STATUS_G_Pin, GPIO_PIN_SET);
138:Core/Src/main.c **** HAL_Delay(500);
139:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_G_GPIO_Port, STATUS_G_Pin, GPIO_PIN_RESET);
140:Core/Src/main.c **** HAL_Delay(500);
141:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_B_GPIO_Port, STATUS_B_Pin, GPIO_PIN_SET);
142:Core/Src/main.c **** HAL_Delay(500);
143:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_B_GPIO_Port, STATUS_B_Pin, GPIO_PIN_RESET);
144:Core/Src/main.c **** HAL_Delay(500);
145:Core/Src/main.c **** /* USER CODE END 3 */
146:Core/Src/main.c **** }
ARM GAS /tmp/cckN5aRQ.s page 4
147:Core/Src/main.c **** }
148:Core/Src/main.c ****
149:Core/Src/main.c **** /**
150:Core/Src/main.c **** * @brief System Clock Configuration
151:Core/Src/main.c **** * @retval None
152:Core/Src/main.c **** */
153:Core/Src/main.c **** void SystemClock_Config(void)
154:Core/Src/main.c **** {
155:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
156:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
157:Core/Src/main.c ****
158:Core/Src/main.c **** /*AXI clock gating */
159:Core/Src/main.c **** RCC->CKGAENR = 0xFFFFFFFF;
160:Core/Src/main.c ****
161:Core/Src/main.c **** /** Supply configuration update enable
162:Core/Src/main.c **** */
163:Core/Src/main.c **** HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
164:Core/Src/main.c ****
165:Core/Src/main.c **** /** Configure the main internal regulator output voltage
166:Core/Src/main.c **** */
167:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
168:Core/Src/main.c ****
169:Core/Src/main.c **** while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
170:Core/Src/main.c ****
171:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters
172:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure.
173:Core/Src/main.c **** */
174:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
175:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
178:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2;
179:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 32;
180:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2;
181:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 3;
182:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2;
183:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
184:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
185:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0;
186:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
187:Core/Src/main.c **** {
188:Core/Src/main.c **** Error_Handler();
189:Core/Src/main.c **** }
190:Core/Src/main.c ****
191:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks
192:Core/Src/main.c **** */
193:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
194:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
195:Core/Src/main.c **** |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
196:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
197:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
198:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
199:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
200:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
201:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
202:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
203:Core/Src/main.c ****
ARM GAS /tmp/cckN5aRQ.s page 5
204:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
205:Core/Src/main.c **** {
206:Core/Src/main.c **** Error_Handler();
207:Core/Src/main.c **** }
208:Core/Src/main.c **** }
209:Core/Src/main.c ****
210:Core/Src/main.c **** /**
211:Core/Src/main.c **** * @brief ADC1 Initialization Function
212:Core/Src/main.c **** * @param None
213:Core/Src/main.c **** * @retval None
214:Core/Src/main.c **** */
215:Core/Src/main.c **** static void MX_ADC1_Init(void)
216:Core/Src/main.c **** {
217:Core/Src/main.c ****
218:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */
219:Core/Src/main.c ****
220:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */
221:Core/Src/main.c ****
222:Core/Src/main.c **** ADC_MultiModeTypeDef multimode = {0};
223:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
224:Core/Src/main.c ****
225:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */
226:Core/Src/main.c ****
227:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */
228:Core/Src/main.c ****
229:Core/Src/main.c **** /** Common config
230:Core/Src/main.c **** */
231:Core/Src/main.c **** hadc1.Instance = ADC1;
232:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
233:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_16B;
234:Core/Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
235:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
236:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
237:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
238:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1;
239:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
240:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T6_TRGO;
241:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
242:Core/Src/main.c **** hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
243:Core/Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
244:Core/Src/main.c **** hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
245:Core/Src/main.c **** hadc1.Init.OversamplingMode = DISABLE;
246:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
247:Core/Src/main.c **** {
248:Core/Src/main.c **** Error_Handler();
249:Core/Src/main.c **** }
250:Core/Src/main.c ****
251:Core/Src/main.c **** /** Configure the ADC multi-mode
252:Core/Src/main.c **** */
253:Core/Src/main.c **** multimode.Mode = ADC_MODE_INDEPENDENT;
254:Core/Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
255:Core/Src/main.c **** {
256:Core/Src/main.c **** Error_Handler();
257:Core/Src/main.c **** }
258:Core/Src/main.c ****
259:Core/Src/main.c **** /** Configure Regular Channel
260:Core/Src/main.c **** */
ARM GAS /tmp/cckN5aRQ.s page 6
261:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_3;
262:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
263:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES_5;
264:Core/Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
265:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
266:Core/Src/main.c **** sConfig.Offset = 0;
267:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE;
268:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
269:Core/Src/main.c **** {
270:Core/Src/main.c **** Error_Handler();
271:Core/Src/main.c **** }
272:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */
273:Core/Src/main.c ****
274:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */
275:Core/Src/main.c ****
276:Core/Src/main.c **** }
277:Core/Src/main.c ****
278:Core/Src/main.c **** /**
279:Core/Src/main.c **** * @brief FDCAN1 Initialization Function
280:Core/Src/main.c **** * @param None
281:Core/Src/main.c **** * @retval None
282:Core/Src/main.c **** */
283:Core/Src/main.c **** static void MX_FDCAN1_Init(void)
284:Core/Src/main.c **** {
285:Core/Src/main.c ****
286:Core/Src/main.c **** /* USER CODE BEGIN FDCAN1_Init 0 */
287:Core/Src/main.c ****
288:Core/Src/main.c **** /* USER CODE END FDCAN1_Init 0 */
289:Core/Src/main.c ****
290:Core/Src/main.c **** /* USER CODE BEGIN FDCAN1_Init 1 */
291:Core/Src/main.c ****
292:Core/Src/main.c **** /* USER CODE END FDCAN1_Init 1 */
293:Core/Src/main.c **** hfdcan1.Instance = FDCAN1;
294:Core/Src/main.c **** hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
295:Core/Src/main.c **** hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
296:Core/Src/main.c **** hfdcan1.Init.AutoRetransmission = DISABLE;
297:Core/Src/main.c **** hfdcan1.Init.TransmitPause = DISABLE;
298:Core/Src/main.c **** hfdcan1.Init.ProtocolException = DISABLE;
299:Core/Src/main.c **** hfdcan1.Init.NominalPrescaler = 3;
300:Core/Src/main.c **** hfdcan1.Init.NominalSyncJumpWidth = 1;
301:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg1 = 13;
302:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg2 = 2;
303:Core/Src/main.c **** hfdcan1.Init.DataPrescaler = 1;
304:Core/Src/main.c **** hfdcan1.Init.DataSyncJumpWidth = 1;
305:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg1 = 1;
306:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg2 = 1;
307:Core/Src/main.c **** hfdcan1.Init.MessageRAMOffset = 0;
308:Core/Src/main.c **** hfdcan1.Init.StdFiltersNbr = 0;
309:Core/Src/main.c **** hfdcan1.Init.ExtFiltersNbr = 0;
310:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtsNbr = 0;
311:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
312:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtsNbr = 0;
313:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
314:Core/Src/main.c **** hfdcan1.Init.RxBuffersNbr = 0;
315:Core/Src/main.c **** hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
316:Core/Src/main.c **** hfdcan1.Init.TxEventsNbr = 0;
317:Core/Src/main.c **** hfdcan1.Init.TxBuffersNbr = 0;
ARM GAS /tmp/cckN5aRQ.s page 7
318:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueElmtsNbr = 0;
319:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
320:Core/Src/main.c **** hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
321:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
322:Core/Src/main.c **** {
323:Core/Src/main.c **** Error_Handler();
324:Core/Src/main.c **** }
325:Core/Src/main.c **** /* USER CODE BEGIN FDCAN1_Init 2 */
326:Core/Src/main.c ****
327:Core/Src/main.c **** /* USER CODE END FDCAN1_Init 2 */
328:Core/Src/main.c ****
329:Core/Src/main.c **** }
330:Core/Src/main.c ****
331:Core/Src/main.c **** /**
332:Core/Src/main.c **** * @brief FDCAN2 Initialization Function
333:Core/Src/main.c **** * @param None
334:Core/Src/main.c **** * @retval None
335:Core/Src/main.c **** */
336:Core/Src/main.c **** static void MX_FDCAN2_Init(void)
337:Core/Src/main.c **** {
338:Core/Src/main.c ****
339:Core/Src/main.c **** /* USER CODE BEGIN FDCAN2_Init 0 */
340:Core/Src/main.c ****
341:Core/Src/main.c **** /* USER CODE END FDCAN2_Init 0 */
342:Core/Src/main.c ****
343:Core/Src/main.c **** /* USER CODE BEGIN FDCAN2_Init 1 */
344:Core/Src/main.c ****
345:Core/Src/main.c **** /* USER CODE END FDCAN2_Init 1 */
346:Core/Src/main.c **** hfdcan2.Instance = FDCAN2;
347:Core/Src/main.c **** hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
348:Core/Src/main.c **** hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
349:Core/Src/main.c **** hfdcan2.Init.AutoRetransmission = DISABLE;
350:Core/Src/main.c **** hfdcan2.Init.TransmitPause = DISABLE;
351:Core/Src/main.c **** hfdcan2.Init.ProtocolException = DISABLE;
352:Core/Src/main.c **** hfdcan2.Init.NominalPrescaler = 3;
353:Core/Src/main.c **** hfdcan2.Init.NominalSyncJumpWidth = 1;
354:Core/Src/main.c **** hfdcan2.Init.NominalTimeSeg1 = 13;
355:Core/Src/main.c **** hfdcan2.Init.NominalTimeSeg2 = 2;
356:Core/Src/main.c **** hfdcan2.Init.DataPrescaler = 1;
357:Core/Src/main.c **** hfdcan2.Init.DataSyncJumpWidth = 1;
358:Core/Src/main.c **** hfdcan2.Init.DataTimeSeg1 = 1;
359:Core/Src/main.c **** hfdcan2.Init.DataTimeSeg2 = 1;
360:Core/Src/main.c **** hfdcan2.Init.MessageRAMOffset = 0;
361:Core/Src/main.c **** hfdcan2.Init.StdFiltersNbr = 0;
362:Core/Src/main.c **** hfdcan2.Init.ExtFiltersNbr = 0;
363:Core/Src/main.c **** hfdcan2.Init.RxFifo0ElmtsNbr = 0;
364:Core/Src/main.c **** hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
365:Core/Src/main.c **** hfdcan2.Init.RxFifo1ElmtsNbr = 0;
366:Core/Src/main.c **** hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
367:Core/Src/main.c **** hfdcan2.Init.RxBuffersNbr = 0;
368:Core/Src/main.c **** hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
369:Core/Src/main.c **** hfdcan2.Init.TxEventsNbr = 0;
370:Core/Src/main.c **** hfdcan2.Init.TxBuffersNbr = 0;
371:Core/Src/main.c **** hfdcan2.Init.TxFifoQueueElmtsNbr = 0;
372:Core/Src/main.c **** hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
373:Core/Src/main.c **** hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
374:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
ARM GAS /tmp/cckN5aRQ.s page 8
375:Core/Src/main.c **** {
376:Core/Src/main.c **** Error_Handler();
377:Core/Src/main.c **** }
378:Core/Src/main.c **** /* USER CODE BEGIN FDCAN2_Init 2 */
379:Core/Src/main.c ****
380:Core/Src/main.c **** /* USER CODE END FDCAN2_Init 2 */
381:Core/Src/main.c ****
382:Core/Src/main.c **** }
383:Core/Src/main.c ****
384:Core/Src/main.c **** /**
385:Core/Src/main.c **** * @brief TIM1 Initialization Function
386:Core/Src/main.c **** * @param None
387:Core/Src/main.c **** * @retval None
388:Core/Src/main.c **** */
389:Core/Src/main.c **** static void MX_TIM1_Init(void)
390:Core/Src/main.c **** {
391:Core/Src/main.c ****
392:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 0 */
393:Core/Src/main.c ****
394:Core/Src/main.c **** /* USER CODE END TIM1_Init 0 */
395:Core/Src/main.c ****
396:Core/Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0};
397:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
398:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
399:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
400:Core/Src/main.c ****
401:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 1 */
402:Core/Src/main.c ****
403:Core/Src/main.c **** /* USER CODE END TIM1_Init 1 */
404:Core/Src/main.c **** htim1.Instance = TIM1;
405:Core/Src/main.c **** htim1.Init.Prescaler = 0;
406:Core/Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
407:Core/Src/main.c **** htim1.Init.Period = 65535;
408:Core/Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
409:Core/Src/main.c **** htim1.Init.RepetitionCounter = 0;
410:Core/Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
411:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
412:Core/Src/main.c **** {
413:Core/Src/main.c **** Error_Handler();
414:Core/Src/main.c **** }
415:Core/Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
416:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
417:Core/Src/main.c **** {
418:Core/Src/main.c **** Error_Handler();
419:Core/Src/main.c **** }
420:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
421:Core/Src/main.c **** {
422:Core/Src/main.c **** Error_Handler();
423:Core/Src/main.c **** }
424:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
425:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
426:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
427:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
428:Core/Src/main.c **** {
429:Core/Src/main.c **** Error_Handler();
430:Core/Src/main.c **** }
431:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1;
ARM GAS /tmp/cckN5aRQ.s page 9
432:Core/Src/main.c **** sConfigOC.Pulse = 0;
433:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
434:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
435:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
436:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
437:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
438:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
439:Core/Src/main.c **** {
440:Core/Src/main.c **** Error_Handler();
441:Core/Src/main.c **** }
442:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
443:Core/Src/main.c **** {
444:Core/Src/main.c **** Error_Handler();
445:Core/Src/main.c **** }
446:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
447:Core/Src/main.c **** {
448:Core/Src/main.c **** Error_Handler();
449:Core/Src/main.c **** }
450:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
451:Core/Src/main.c **** {
452:Core/Src/main.c **** Error_Handler();
453:Core/Src/main.c **** }
454:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
455:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
456:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
457:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0;
458:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
459:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
460:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0;
461:Core/Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
462:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
463:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0;
464:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
465:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
466:Core/Src/main.c **** {
467:Core/Src/main.c **** Error_Handler();
468:Core/Src/main.c **** }
469:Core/Src/main.c **** /* USER CODE BEGIN TIM1_Init 2 */
470:Core/Src/main.c ****
471:Core/Src/main.c **** /* USER CODE END TIM1_Init 2 */
472:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim1);
473:Core/Src/main.c ****
474:Core/Src/main.c **** }
475:Core/Src/main.c ****
476:Core/Src/main.c **** /**
477:Core/Src/main.c **** * @brief TIM3 Initialization Function
478:Core/Src/main.c **** * @param None
479:Core/Src/main.c **** * @retval None
480:Core/Src/main.c **** */
481:Core/Src/main.c **** static void MX_TIM3_Init(void)
482:Core/Src/main.c **** {
483:Core/Src/main.c ****
484:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 0 */
485:Core/Src/main.c ****
486:Core/Src/main.c **** /* USER CODE END TIM3_Init 0 */
487:Core/Src/main.c ****
488:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
ARM GAS /tmp/cckN5aRQ.s page 10
489:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
490:Core/Src/main.c ****
491:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 1 */
492:Core/Src/main.c ****
493:Core/Src/main.c **** /* USER CODE END TIM3_Init 1 */
494:Core/Src/main.c **** htim3.Instance = TIM3;
495:Core/Src/main.c **** htim3.Init.Prescaler = 0;
496:Core/Src/main.c **** htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
497:Core/Src/main.c **** htim3.Init.Period = 65535;
498:Core/Src/main.c **** htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
499:Core/Src/main.c **** htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
500:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
501:Core/Src/main.c **** {
502:Core/Src/main.c **** Error_Handler();
503:Core/Src/main.c **** }
504:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
505:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
506:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
507:Core/Src/main.c **** {
508:Core/Src/main.c **** Error_Handler();
509:Core/Src/main.c **** }
510:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1;
511:Core/Src/main.c **** sConfigOC.Pulse = 0;
512:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
513:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
514:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
515:Core/Src/main.c **** {
516:Core/Src/main.c **** Error_Handler();
517:Core/Src/main.c **** }
518:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
519:Core/Src/main.c **** {
520:Core/Src/main.c **** Error_Handler();
521:Core/Src/main.c **** }
522:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 2 */
523:Core/Src/main.c ****
524:Core/Src/main.c **** /* USER CODE END TIM3_Init 2 */
525:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim3);
526:Core/Src/main.c ****
527:Core/Src/main.c **** }
528:Core/Src/main.c ****
529:Core/Src/main.c **** /**
530:Core/Src/main.c **** * @brief TIM4 Initialization Function
531:Core/Src/main.c **** * @param None
532:Core/Src/main.c **** * @retval None
533:Core/Src/main.c **** */
534:Core/Src/main.c **** static void MX_TIM4_Init(void)
535:Core/Src/main.c **** {
536:Core/Src/main.c ****
537:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 0 */
538:Core/Src/main.c ****
539:Core/Src/main.c **** /* USER CODE END TIM4_Init 0 */
540:Core/Src/main.c ****
541:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
542:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
543:Core/Src/main.c ****
544:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 1 */
545:Core/Src/main.c ****
ARM GAS /tmp/cckN5aRQ.s page 11
546:Core/Src/main.c **** /* USER CODE END TIM4_Init 1 */
547:Core/Src/main.c **** htim4.Instance = TIM4;
548:Core/Src/main.c **** htim4.Init.Prescaler = 0;
549:Core/Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
550:Core/Src/main.c **** htim4.Init.Period = 65535;
551:Core/Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
552:Core/Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
553:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
554:Core/Src/main.c **** {
555:Core/Src/main.c **** Error_Handler();
556:Core/Src/main.c **** }
557:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
558:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
559:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
560:Core/Src/main.c **** {
561:Core/Src/main.c **** Error_Handler();
562:Core/Src/main.c **** }
563:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1;
564:Core/Src/main.c **** sConfigOC.Pulse = 0;
565:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
566:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
567:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
568:Core/Src/main.c **** {
569:Core/Src/main.c **** Error_Handler();
570:Core/Src/main.c **** }
571:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
572:Core/Src/main.c **** {
573:Core/Src/main.c **** Error_Handler();
574:Core/Src/main.c **** }
575:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 2 */
576:Core/Src/main.c ****
577:Core/Src/main.c **** /* USER CODE END TIM4_Init 2 */
578:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim4);
579:Core/Src/main.c ****
580:Core/Src/main.c **** }
581:Core/Src/main.c ****
582:Core/Src/main.c **** /**
583:Core/Src/main.c **** * @brief TIM6 Initialization Function
584:Core/Src/main.c **** * @param None
585:Core/Src/main.c **** * @retval None
586:Core/Src/main.c **** */
587:Core/Src/main.c **** static void MX_TIM6_Init(void)
588:Core/Src/main.c **** {
589:Core/Src/main.c ****
590:Core/Src/main.c **** /* USER CODE BEGIN TIM6_Init 0 */
591:Core/Src/main.c ****
592:Core/Src/main.c **** /* USER CODE END TIM6_Init 0 */
593:Core/Src/main.c ****
594:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
595:Core/Src/main.c ****
596:Core/Src/main.c **** /* USER CODE BEGIN TIM6_Init 1 */
597:Core/Src/main.c ****
598:Core/Src/main.c **** /* USER CODE END TIM6_Init 1 */
599:Core/Src/main.c **** htim6.Instance = TIM6;
600:Core/Src/main.c **** htim6.Init.Prescaler = 2;
601:Core/Src/main.c **** htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
602:Core/Src/main.c **** htim6.Init.Period = 48000;
ARM GAS /tmp/cckN5aRQ.s page 12
603:Core/Src/main.c **** htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
604:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
605:Core/Src/main.c **** {
606:Core/Src/main.c **** Error_Handler();
607:Core/Src/main.c **** }
608:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
609:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
610:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
611:Core/Src/main.c **** {
612:Core/Src/main.c **** Error_Handler();
613:Core/Src/main.c **** }
614:Core/Src/main.c **** /* USER CODE BEGIN TIM6_Init 2 */
615:Core/Src/main.c ****
616:Core/Src/main.c **** /* USER CODE END TIM6_Init 2 */
617:Core/Src/main.c ****
618:Core/Src/main.c **** }
619:Core/Src/main.c ****
620:Core/Src/main.c **** /**
621:Core/Src/main.c **** * @brief TIM8 Initialization Function
622:Core/Src/main.c **** * @param None
623:Core/Src/main.c **** * @retval None
624:Core/Src/main.c **** */
625:Core/Src/main.c **** static void MX_TIM8_Init(void)
626:Core/Src/main.c **** {
627:Core/Src/main.c ****
628:Core/Src/main.c **** /* USER CODE BEGIN TIM8_Init 0 */
629:Core/Src/main.c ****
630:Core/Src/main.c **** /* USER CODE END TIM8_Init 0 */
631:Core/Src/main.c ****
632:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
633:Core/Src/main.c **** TIM_IC_InitTypeDef sConfigIC = {0};
634:Core/Src/main.c ****
635:Core/Src/main.c **** /* USER CODE BEGIN TIM8_Init 1 */
636:Core/Src/main.c ****
637:Core/Src/main.c **** /* USER CODE END TIM8_Init 1 */
638:Core/Src/main.c **** htim8.Instance = TIM8;
639:Core/Src/main.c **** htim8.Init.Prescaler = 0;
640:Core/Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
641:Core/Src/main.c **** htim8.Init.Period = 65535;
642:Core/Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
643:Core/Src/main.c **** htim8.Init.RepetitionCounter = 0;
644:Core/Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
645:Core/Src/main.c **** if (HAL_TIM_IC_Init(&htim8) != HAL_OK)
646:Core/Src/main.c **** {
647:Core/Src/main.c **** Error_Handler();
648:Core/Src/main.c **** }
649:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
650:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
651:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
652:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
653:Core/Src/main.c **** {
654:Core/Src/main.c **** Error_Handler();
655:Core/Src/main.c **** }
656:Core/Src/main.c **** sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
657:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
658:Core/Src/main.c **** sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
659:Core/Src/main.c **** sConfigIC.ICFilter = 0;
ARM GAS /tmp/cckN5aRQ.s page 13
660:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim8, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
661:Core/Src/main.c **** {
662:Core/Src/main.c **** Error_Handler();
663:Core/Src/main.c **** }
664:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim8, &sConfigIC, TIM_CHANNEL_2) != HAL_OK)
665:Core/Src/main.c **** {
666:Core/Src/main.c **** Error_Handler();
667:Core/Src/main.c **** }
668:Core/Src/main.c **** /* USER CODE BEGIN TIM8_Init 2 */
669:Core/Src/main.c ****
670:Core/Src/main.c **** /* USER CODE END TIM8_Init 2 */
671:Core/Src/main.c ****
672:Core/Src/main.c **** }
673:Core/Src/main.c ****
674:Core/Src/main.c **** /**
675:Core/Src/main.c **** * Enable DMA controller clock
676:Core/Src/main.c **** */
677:Core/Src/main.c **** static void MX_DMA_Init(void)
678:Core/Src/main.c **** {
679:Core/Src/main.c ****
680:Core/Src/main.c **** /* DMA controller clock enable */
681:Core/Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
682:Core/Src/main.c ****
683:Core/Src/main.c **** /* DMA interrupt init */
684:Core/Src/main.c **** /* DMA1_Stream0_IRQn interrupt configuration */
685:Core/Src/main.c **** HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
686:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
687:Core/Src/main.c ****
688:Core/Src/main.c **** }
689:Core/Src/main.c ****
690:Core/Src/main.c **** /**
691:Core/Src/main.c **** * @brief GPIO Initialization Function
692:Core/Src/main.c **** * @param None
693:Core/Src/main.c **** * @retval None
694:Core/Src/main.c **** */
695:Core/Src/main.c **** static void MX_GPIO_Init(void)
696:Core/Src/main.c **** {
697:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
698:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */
699:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */
700:Core/Src/main.c ****
701:Core/Src/main.c **** /* GPIO Ports Clock Enable */
702:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE();
703:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
704:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
705:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
706:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
707:Core/Src/main.c ****
708:Core/Src/main.c **** /*Configure GPIO pin Output Level */
709:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOB, STATUS1_Pin|STATUS2_Pin|STATUS_R_Pin|STATUS_G_Pin, GPIO_PIN_RESET);
710:Core/Src/main.c ****
711:Core/Src/main.c **** /*Configure GPIO pin Output Level */
712:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_B_GPIO_Port, STATUS_B_Pin, GPIO_PIN_RESET);
713:Core/Src/main.c ****
714:Core/Src/main.c **** /*Configure GPIO pins : STATUS1_Pin STATUS2_Pin STATUS_R_Pin STATUS_G_Pin */
715:Core/Src/main.c **** GPIO_InitStruct.Pin = STATUS1_Pin|STATUS2_Pin|STATUS_R_Pin|STATUS_G_Pin;
716:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
ARM GAS /tmp/cckN5aRQ.s page 14
717:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
718:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
719:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
720:Core/Src/main.c ****
721:Core/Src/main.c **** /*Configure GPIO pin : STATUS_B_Pin */
722:Core/Src/main.c **** GPIO_InitStruct.Pin = STATUS_B_Pin;
723:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
724:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
725:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
726:Core/Src/main.c **** HAL_GPIO_Init(STATUS_B_GPIO_Port, &GPIO_InitStruct);
727:Core/Src/main.c ****
728:Core/Src/main.c **** /*Configure GPIO pin : D1_IC_Pin */
729:Core/Src/main.c **** GPIO_InitStruct.Pin = D1_IC_Pin;
730:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
731:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
732:Core/Src/main.c **** HAL_GPIO_Init(D1_IC_GPIO_Port, &GPIO_InitStruct);
733:Core/Src/main.c ****
734:Core/Src/main.c **** /*Configure GPIO pins : D2_Pin D3_Pin D4_IC_Pin */
735:Core/Src/main.c **** GPIO_InitStruct.Pin = D2_Pin|D3_Pin|D4_IC_Pin;
736:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
737:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
738:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
739:Core/Src/main.c ****
740:Core/Src/main.c **** /*Configure GPIO pin : D5_Pin */
741:Core/Src/main.c **** GPIO_InitStruct.Pin = D5_Pin;
742:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
743:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
744:Core/Src/main.c **** HAL_GPIO_Init(D5_GPIO_Port, &GPIO_InitStruct);
745:Core/Src/main.c ****
746:Core/Src/main.c **** /*Configure GPIO pin : D6_Pin */
747:Core/Src/main.c **** GPIO_InitStruct.Pin = D6_Pin;
748:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
749:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
750:Core/Src/main.c **** HAL_GPIO_Init(D6_GPIO_Port, &GPIO_InitStruct);
751:Core/Src/main.c ****
752:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */
753:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */
754:Core/Src/main.c **** }
755:Core/Src/main.c ****
756:Core/Src/main.c **** /* USER CODE BEGIN 4 */
757:Core/Src/main.c ****
758:Core/Src/main.c **** /* USER CODE END 4 */
759:Core/Src/main.c ****
760:Core/Src/main.c **** /* MPU Configuration */
761:Core/Src/main.c ****
762:Core/Src/main.c **** void MPU_Config(void)
763:Core/Src/main.c **** {
27 .loc 1 763 1 view -0
28 .cfi_startproc
29 @ args = 0, pretend = 0, frame = 16
30 @ frame_needed = 0, uses_anonymous_args = 0
31 0000 30B5 push {r4, r5, lr}
32 .cfi_def_cfa_offset 12
33 .cfi_offset 4, -12
34 .cfi_offset 5, -8
35 .cfi_offset 14, -4
36 0002 85B0 sub sp, sp, #20
ARM GAS /tmp/cckN5aRQ.s page 15
37 .cfi_def_cfa_offset 32
764:Core/Src/main.c **** MPU_Region_InitTypeDef MPU_InitStruct = {0};
38 .loc 1 764 3 view .LVU1
39 .loc 1 764 26 is_stmt 0 view .LVU2
40 0004 0024 movs r4, #0
41 0006 0094 str r4, [sp]
42 0008 0194 str r4, [sp, #4]
43 000a 0294 str r4, [sp, #8]
44 000c 0394 str r4, [sp, #12]
765:Core/Src/main.c ****
766:Core/Src/main.c **** /* Disables the MPU */
767:Core/Src/main.c **** HAL_MPU_Disable();
45 .loc 1 767 3 is_stmt 1 view .LVU3
46 000e FFF7FEFF bl HAL_MPU_Disable
47 .LVL0:
768:Core/Src/main.c ****
769:Core/Src/main.c **** /** Initializes and configures the Region and the memory to be protected
770:Core/Src/main.c **** */
771:Core/Src/main.c **** MPU_InitStruct.Enable = MPU_REGION_ENABLE;
48 .loc 1 771 3 view .LVU4
49 .loc 1 771 25 is_stmt 0 view .LVU5
50 0012 0123 movs r3, #1
51 0014 8DF80030 strb r3, [sp]
772:Core/Src/main.c **** MPU_InitStruct.Number = MPU_REGION_NUMBER0;
52 .loc 1 772 3 is_stmt 1 view .LVU6
53 .loc 1 772 25 is_stmt 0 view .LVU7
54 0018 8DF80140 strb r4, [sp, #1]
773:Core/Src/main.c **** MPU_InitStruct.BaseAddress = 0x0;
55 .loc 1 773 3 is_stmt 1 view .LVU8
56 .loc 1 773 30 is_stmt 0 view .LVU9
57 001c 0194 str r4, [sp, #4]
774:Core/Src/main.c **** MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
58 .loc 1 774 3 is_stmt 1 view .LVU10
59 .loc 1 774 23 is_stmt 0 view .LVU11
60 001e 1F22 movs r2, #31
61 0020 8DF80820 strb r2, [sp, #8]
775:Core/Src/main.c **** MPU_InitStruct.SubRegionDisable = 0x87;
62 .loc 1 775 3 is_stmt 1 view .LVU12
63 .loc 1 775 35 is_stmt 0 view .LVU13
64 0024 8722 movs r2, #135
65 0026 8DF80920 strb r2, [sp, #9]
776:Core/Src/main.c **** MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
66 .loc 1 776 3 is_stmt 1 view .LVU14
67 .loc 1 776 31 is_stmt 0 view .LVU15
68 002a 8DF80A40 strb r4, [sp, #10]
777:Core/Src/main.c **** MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
69 .loc 1 777 3 is_stmt 1 view .LVU16
70 .loc 1 777 35 is_stmt 0 view .LVU17
71 002e 8DF80B40 strb r4, [sp, #11]
778:Core/Src/main.c **** MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
72 .loc 1 778 3 is_stmt 1 view .LVU18
73 .loc 1 778 30 is_stmt 0 view .LVU19
74 0032 8DF80C30 strb r3, [sp, #12]
779:Core/Src/main.c **** MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
75 .loc 1 779 3 is_stmt 1 view .LVU20
76 .loc 1 779 30 is_stmt 0 view .LVU21
77 0036 8DF80D30 strb r3, [sp, #13]
ARM GAS /tmp/cckN5aRQ.s page 16
780:Core/Src/main.c **** MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
78 .loc 1 780 3 is_stmt 1 view .LVU22
79 .loc 1 780 30 is_stmt 0 view .LVU23
80 003a 8DF80E40 strb r4, [sp, #14]
781:Core/Src/main.c **** MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
81 .loc 1 781 3 is_stmt 1 view .LVU24
82 .loc 1 781 31 is_stmt 0 view .LVU25
83 003e 8DF80F40 strb r4, [sp, #15]
782:Core/Src/main.c ****
783:Core/Src/main.c **** HAL_MPU_ConfigRegion(&MPU_InitStruct);
84 .loc 1 783 3 is_stmt 1 view .LVU26
85 0042 6846 mov r0, sp
86 0044 FFF7FEFF bl HAL_MPU_ConfigRegion
87 .LVL1:
784:Core/Src/main.c **** /* Enables the MPU */
785:Core/Src/main.c **** HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
88 .loc 1 785 3 view .LVU27
89 0048 0420 movs r0, #4
90 004a FFF7FEFF bl HAL_MPU_Enable
91 .LVL2:
786:Core/Src/main.c ****
787:Core/Src/main.c **** }
92 .loc 1 787 1 is_stmt 0 view .LVU28
93 004e 05B0 add sp, sp, #20
94 .cfi_def_cfa_offset 12
95 @ sp needed
96 0050 30BD pop {r4, r5, pc}
97 .cfi_endproc
98 .LFE347:
100 .section .text.MX_GPIO_Init,"ax",%progbits
101 .align 1
102 .syntax unified
103 .thumb
104 .thumb_func
106 MX_GPIO_Init:
107 .LFB346:
696:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
108 .loc 1 696 1 is_stmt 1 view -0
109 .cfi_startproc
110 @ args = 0, pretend = 0, frame = 40
111 @ frame_needed = 0, uses_anonymous_args = 0
112 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr}
113 .cfi_def_cfa_offset 24
114 .cfi_offset 4, -24
115 .cfi_offset 5, -20
116 .cfi_offset 6, -16
117 .cfi_offset 7, -12
118 .cfi_offset 8, -8
119 .cfi_offset 14, -4
120 0004 8AB0 sub sp, sp, #40
121 .cfi_def_cfa_offset 64
697:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */
122 .loc 1 697 3 view .LVU30
697:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */
123 .loc 1 697 20 is_stmt 0 view .LVU31
124 0006 05AD add r5, sp, #20
125 0008 0024 movs r4, #0
ARM GAS /tmp/cckN5aRQ.s page 17
126 000a 0594 str r4, [sp, #20]
127 000c 0694 str r4, [sp, #24]
128 000e 0794 str r4, [sp, #28]
129 0010 0894 str r4, [sp, #32]
130 0012 0994 str r4, [sp, #36]
702:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
131 .loc 1 702 3 is_stmt 1 view .LVU32
132 .LBB4:
702:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
133 .loc 1 702 3 view .LVU33
702:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
134 .loc 1 702 3 view .LVU34
135 0014 434B ldr r3, .L5
136 0016 D3F84021 ldr r2, [r3, #320]
137 001a 42F08002 orr r2, r2, #128
138 001e C3F84021 str r2, [r3, #320]
702:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
139 .loc 1 702 3 view .LVU35
140 0022 D3F84021 ldr r2, [r3, #320]
141 0026 02F08002 and r2, r2, #128
142 002a 0092 str r2, [sp]
702:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
143 .loc 1 702 3 view .LVU36
144 002c 009A ldr r2, [sp]
145 .LBE4:
702:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
146 .loc 1 702 3 view .LVU37
703:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
147 .loc 1 703 3 view .LVU38
148 .LBB5:
703:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
149 .loc 1 703 3 view .LVU39
703:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
150 .loc 1 703 3 view .LVU40
151 002e D3F84021 ldr r2, [r3, #320]
152 0032 42F00402 orr r2, r2, #4
153 0036 C3F84021 str r2, [r3, #320]
703:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
154 .loc 1 703 3 view .LVU41
155 003a D3F84021 ldr r2, [r3, #320]
156 003e 02F00402 and r2, r2, #4
157 0042 0192 str r2, [sp, #4]
703:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
158 .loc 1 703 3 view .LVU42
159 0044 019A ldr r2, [sp, #4]
160 .LBE5:
703:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
161 .loc 1 703 3 view .LVU43
704:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
162 .loc 1 704 3 view .LVU44
163 .LBB6:
704:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
164 .loc 1 704 3 view .LVU45
704:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
165 .loc 1 704 3 view .LVU46
166 0046 D3F84021 ldr r2, [r3, #320]
167 004a 42F00102 orr r2, r2, #1
ARM GAS /tmp/cckN5aRQ.s page 18
168 004e C3F84021 str r2, [r3, #320]
704:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
169 .loc 1 704 3 view .LVU47
170 0052 D3F84021 ldr r2, [r3, #320]
171 0056 02F00102 and r2, r2, #1
172 005a 0292 str r2, [sp, #8]
704:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
173 .loc 1 704 3 view .LVU48
174 005c 029A ldr r2, [sp, #8]
175 .LBE6:
704:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
176 .loc 1 704 3 view .LVU49
705:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
177 .loc 1 705 3 view .LVU50
178 .LBB7:
705:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
179 .loc 1 705 3 view .LVU51
705:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
180 .loc 1 705 3 view .LVU52
181 005e D3F84021 ldr r2, [r3, #320]
182 0062 42F00202 orr r2, r2, #2
183 0066 C3F84021 str r2, [r3, #320]
705:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
184 .loc 1 705 3 view .LVU53
185 006a D3F84021 ldr r2, [r3, #320]
186 006e 02F00202 and r2, r2, #2
187 0072 0392 str r2, [sp, #12]
705:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
188 .loc 1 705 3 view .LVU54
189 0074 039A ldr r2, [sp, #12]
190 .LBE7:
705:Core/Src/main.c **** __HAL_RCC_GPIOD_CLK_ENABLE();
191 .loc 1 705 3 view .LVU55
706:Core/Src/main.c ****
192 .loc 1 706 3 view .LVU56
193 .LBB8:
706:Core/Src/main.c ****
194 .loc 1 706 3 view .LVU57
706:Core/Src/main.c ****
195 .loc 1 706 3 view .LVU58
196 0076 D3F84021 ldr r2, [r3, #320]
197 007a 42F00802 orr r2, r2, #8
198 007e C3F84021 str r2, [r3, #320]
706:Core/Src/main.c ****
199 .loc 1 706 3 view .LVU59
200 0082 D3F84031 ldr r3, [r3, #320]
201 0086 03F00803 and r3, r3, #8
202 008a 0493 str r3, [sp, #16]
706:Core/Src/main.c ****
203 .loc 1 706 3 view .LVU60
204 008c 049B ldr r3, [sp, #16]
205 .LBE8:
706:Core/Src/main.c ****
206 .loc 1 706 3 view .LVU61
709:Core/Src/main.c ****
207 .loc 1 709 3 view .LVU62
208 008e 264E ldr r6, .L5+4
ARM GAS /tmp/cckN5aRQ.s page 19
209 0090 2246 mov r2, r4
210 0092 4CF20441 movw r1, #50180
211 0096 3046 mov r0, r6
212 0098 FFF7FEFF bl HAL_GPIO_WritePin
213 .LVL3:
712:Core/Src/main.c ****
214 .loc 1 712 3 view .LVU63
215 009c 234F ldr r7, .L5+8
216 009e 2246 mov r2, r4
217 00a0 4FF48051 mov r1, #4096
218 00a4 3846 mov r0, r7
219 00a6 FFF7FEFF bl HAL_GPIO_WritePin
220 .LVL4:
715:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
221 .loc 1 715 3 view .LVU64
715:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
222 .loc 1 715 23 is_stmt 0 view .LVU65
223 00aa 4CF20443 movw r3, #50180
224 00ae 0593 str r3, [sp, #20]
716:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
225 .loc 1 716 3 is_stmt 1 view .LVU66
716:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
226 .loc 1 716 24 is_stmt 0 view .LVU67
227 00b0 4FF00108 mov r8, #1
228 00b4 CDF81880 str r8, [sp, #24]
717:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
229 .loc 1 717 3 is_stmt 1 view .LVU68
717:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
230 .loc 1 717 24 is_stmt 0 view .LVU69
231 00b8 0794 str r4, [sp, #28]
718:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
232 .loc 1 718 3 is_stmt 1 view .LVU70
718:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
233 .loc 1 718 25 is_stmt 0 view .LVU71
234 00ba 0894 str r4, [sp, #32]
719:Core/Src/main.c ****
235 .loc 1 719 3 is_stmt 1 view .LVU72
236 00bc 2946 mov r1, r5
237 00be 3046 mov r0, r6
238 00c0 FFF7FEFF bl HAL_GPIO_Init
239 .LVL5:
722:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
240 .loc 1 722 3 view .LVU73
722:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
241 .loc 1 722 23 is_stmt 0 view .LVU74
242 00c4 4FF48053 mov r3, #4096
243 00c8 0593 str r3, [sp, #20]
723:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
244 .loc 1 723 3 is_stmt 1 view .LVU75
723:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
245 .loc 1 723 24 is_stmt 0 view .LVU76
246 00ca CDF81880 str r8, [sp, #24]
724:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
247 .loc 1 724 3 is_stmt 1 view .LVU77
724:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
248 .loc 1 724 24 is_stmt 0 view .LVU78
249 00ce 0794 str r4, [sp, #28]
ARM GAS /tmp/cckN5aRQ.s page 20
725:Core/Src/main.c **** HAL_GPIO_Init(STATUS_B_GPIO_Port, &GPIO_InitStruct);
250 .loc 1 725 3 is_stmt 1 view .LVU79
725:Core/Src/main.c **** HAL_GPIO_Init(STATUS_B_GPIO_Port, &GPIO_InitStruct);
251 .loc 1 725 25 is_stmt 0 view .LVU80
252 00d0 0894 str r4, [sp, #32]
726:Core/Src/main.c ****
253 .loc 1 726 3 is_stmt 1 view .LVU81
254 00d2 2946 mov r1, r5
255 00d4 3846 mov r0, r7
256 00d6 FFF7FEFF bl HAL_GPIO_Init
257 .LVL6:
729:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
258 .loc 1 729 3 view .LVU82
729:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
259 .loc 1 729 23 is_stmt 0 view .LVU83
260 00da 4FF40043 mov r3, #32768
261 00de 0593 str r3, [sp, #20]
730:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
262 .loc 1 730 3 is_stmt 1 view .LVU84
730:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
263 .loc 1 730 24 is_stmt 0 view .LVU85
264 00e0 0694 str r4, [sp, #24]
731:Core/Src/main.c **** HAL_GPIO_Init(D1_IC_GPIO_Port, &GPIO_InitStruct);
265 .loc 1 731 3 is_stmt 1 view .LVU86
731:Core/Src/main.c **** HAL_GPIO_Init(D1_IC_GPIO_Port, &GPIO_InitStruct);
266 .loc 1 731 24 is_stmt 0 view .LVU87
267 00e2 0794 str r4, [sp, #28]
732:Core/Src/main.c ****
268 .loc 1 732 3 is_stmt 1 view .LVU88
269 00e4 2946 mov r1, r5
270 00e6 3846 mov r0, r7
271 00e8 FFF7FEFF bl HAL_GPIO_Init
272 .LVL7:
735:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
273 .loc 1 735 3 view .LVU89
735:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
274 .loc 1 735 23 is_stmt 0 view .LVU90
275 00ec 4FF4E053 mov r3, #7168
276 00f0 0593 str r3, [sp, #20]
736:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
277 .loc 1 736 3 is_stmt 1 view .LVU91
736:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
278 .loc 1 736 24 is_stmt 0 view .LVU92
279 00f2 0694 str r4, [sp, #24]
737:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
280 .loc 1 737 3 is_stmt 1 view .LVU93
737:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
281 .loc 1 737 24 is_stmt 0 view .LVU94
282 00f4 0794 str r4, [sp, #28]
738:Core/Src/main.c ****
283 .loc 1 738 3 is_stmt 1 view .LVU95
284 00f6 2946 mov r1, r5
285 00f8 0D48 ldr r0, .L5+12
286 00fa FFF7FEFF bl HAL_GPIO_Init
287 .LVL8:
741:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
288 .loc 1 741 3 view .LVU96
ARM GAS /tmp/cckN5aRQ.s page 21
741:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
289 .loc 1 741 23 is_stmt 0 view .LVU97
290 00fe 0423 movs r3, #4
291 0100 0593 str r3, [sp, #20]
742:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
292 .loc 1 742 3 is_stmt 1 view .LVU98
742:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
293 .loc 1 742 24 is_stmt 0 view .LVU99
294 0102 0694 str r4, [sp, #24]
743:Core/Src/main.c **** HAL_GPIO_Init(D5_GPIO_Port, &GPIO_InitStruct);
295 .loc 1 743 3 is_stmt 1 view .LVU100
743:Core/Src/main.c **** HAL_GPIO_Init(D5_GPIO_Port, &GPIO_InitStruct);
296 .loc 1 743 24 is_stmt 0 view .LVU101
297 0104 0794 str r4, [sp, #28]
744:Core/Src/main.c ****
298 .loc 1 744 3 is_stmt 1 view .LVU102
299 0106 2946 mov r1, r5
300 0108 0A48 ldr r0, .L5+16
301 010a FFF7FEFF bl HAL_GPIO_Init
302 .LVL9:
747:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
303 .loc 1 747 3 view .LVU103
747:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
304 .loc 1 747 23 is_stmt 0 view .LVU104
305 010e 1023 movs r3, #16
306 0110 0593 str r3, [sp, #20]
748:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
307 .loc 1 748 3 is_stmt 1 view .LVU105
748:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
308 .loc 1 748 24 is_stmt 0 view .LVU106
309 0112 0694 str r4, [sp, #24]
749:Core/Src/main.c **** HAL_GPIO_Init(D6_GPIO_Port, &GPIO_InitStruct);
310 .loc 1 749 3 is_stmt 1 view .LVU107
749:Core/Src/main.c **** HAL_GPIO_Init(D6_GPIO_Port, &GPIO_InitStruct);
311 .loc 1 749 24 is_stmt 0 view .LVU108
312 0114 0794 str r4, [sp, #28]
750:Core/Src/main.c ****
313 .loc 1 750 3 is_stmt 1 view .LVU109
314 0116 2946 mov r1, r5
315 0118 3046 mov r0, r6
316 011a FFF7FEFF bl HAL_GPIO_Init
317 .LVL10:
754:Core/Src/main.c ****
318 .loc 1 754 1 is_stmt 0 view .LVU110
319 011e 0AB0 add sp, sp, #40
320 .cfi_def_cfa_offset 24
321 @ sp needed
322 0120 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
323 .L6:
324 .align 2
325 .L5:
326 0124 00440258 .word 1476543488
327 0128 00040258 .word 1476527104
328 012c 00000258 .word 1476526080
329 0130 00080258 .word 1476528128
330 0134 000C0258 .word 1476529152
331 .cfi_endproc
ARM GAS /tmp/cckN5aRQ.s page 22
332 .LFE346:
334 .section .text.MX_DMA_Init,"ax",%progbits
335 .align 1
336 .syntax unified
337 .thumb
338 .thumb_func
340 MX_DMA_Init:
341 .LFB345:
678:Core/Src/main.c ****
342 .loc 1 678 1 is_stmt 1 view -0
343 .cfi_startproc
344 @ args = 0, pretend = 0, frame = 8
345 @ frame_needed = 0, uses_anonymous_args = 0
346 0000 00B5 push {lr}
347 .cfi_def_cfa_offset 4
348 .cfi_offset 14, -4
349 0002 83B0 sub sp, sp, #12
350 .cfi_def_cfa_offset 16
681:Core/Src/main.c ****
351 .loc 1 681 3 view .LVU112
352 .LBB9:
681:Core/Src/main.c ****
353 .loc 1 681 3 view .LVU113
681:Core/Src/main.c ****
354 .loc 1 681 3 view .LVU114
355 0004 0B4B ldr r3, .L9
356 0006 D3F83821 ldr r2, [r3, #312]
357 000a 42F00102 orr r2, r2, #1
358 000e C3F83821 str r2, [r3, #312]
681:Core/Src/main.c ****
359 .loc 1 681 3 view .LVU115
360 0012 D3F83831 ldr r3, [r3, #312]
361 0016 03F00103 and r3, r3, #1
362 001a 0193 str r3, [sp, #4]
681:Core/Src/main.c ****
363 .loc 1 681 3 view .LVU116
364 001c 019B ldr r3, [sp, #4]
365 .LBE9:
681:Core/Src/main.c ****
366 .loc 1 681 3 view .LVU117
685:Core/Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
367 .loc 1 685 3 view .LVU118
368 001e 0022 movs r2, #0
369 0020 1146 mov r1, r2
370 0022 0B20 movs r0, #11
371 0024 FFF7FEFF bl HAL_NVIC_SetPriority
372 .LVL11:
686:Core/Src/main.c ****
373 .loc 1 686 3 view .LVU119
374 0028 0B20 movs r0, #11
375 002a FFF7FEFF bl HAL_NVIC_EnableIRQ
376 .LVL12:
688:Core/Src/main.c ****
377 .loc 1 688 1 is_stmt 0 view .LVU120
378 002e 03B0 add sp, sp, #12
379 .cfi_def_cfa_offset 4
380 @ sp needed
ARM GAS /tmp/cckN5aRQ.s page 23
381 0030 5DF804FB ldr pc, [sp], #4
382 .L10:
383 .align 2
384 .L9:
385 0034 00440258 .word 1476543488
386 .cfi_endproc
387 .LFE345:
389 .section .text.Error_Handler,"ax",%progbits
390 .align 1
391 .global Error_Handler
392 .syntax unified
393 .thumb
394 .thumb_func
396 Error_Handler:
397 .LFB348:
788:Core/Src/main.c ****
789:Core/Src/main.c **** /**
790:Core/Src/main.c **** * @brief This function is executed in case of error occurrence.
791:Core/Src/main.c **** * @retval None
792:Core/Src/main.c **** */
793:Core/Src/main.c **** void Error_Handler(void)
794:Core/Src/main.c **** {
398 .loc 1 794 1 is_stmt 1 view -0
399 .cfi_startproc
400 @ Volatile: function does not return.
401 @ args = 0, pretend = 0, frame = 0
402 @ frame_needed = 0, uses_anonymous_args = 0
403 @ link register save eliminated.
795:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */
796:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */
797:Core/Src/main.c **** __disable_irq();
404 .loc 1 797 3 view .LVU122
405 .LBB10:
406 .LBI10:
407 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
ARM GAS /tmp/cckN5aRQ.s page 24
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
ARM GAS /tmp/cckN5aRQ.s page 25
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER
117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
119:Drivers/CMSIS/Include/cmsis_gcc.h ****
120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */
121:Drivers/CMSIS/Include/cmsis_gcc.h ****
122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss
127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly
128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script.
129:Drivers/CMSIS/Include/cmsis_gcc.h ****
130:Drivers/CMSIS/Include/cmsis_gcc.h **** */
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN;
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src;
ARM GAS /tmp/cckN5aRQ.s page 26
137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t;
140:Drivers/CMSIS/Include/cmsis_gcc.h ****
141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t;
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__;
147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__;
148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__;
149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__;
150:Drivers/CMSIS/Include/cmsis_gcc.h ****
151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i];
154:Drivers/CMSIS/Include/cmsis_gcc.h **** }
155:Drivers/CMSIS/Include/cmsis_gcc.h **** }
156:Drivers/CMSIS/Include/cmsis_gcc.h ****
157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u;
160:Drivers/CMSIS/Include/cmsis_gcc.h **** }
161:Drivers/CMSIS/Include/cmsis_gcc.h **** }
162:Drivers/CMSIS/Include/cmsis_gcc.h ****
163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start();
164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
165:Drivers/CMSIS/Include/cmsis_gcc.h ****
166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start
167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
168:Drivers/CMSIS/Include/cmsis_gcc.h ****
169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop
171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
172:Drivers/CMSIS/Include/cmsis_gcc.h ****
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit
175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
176:Drivers/CMSIS/Include/cmsis_gcc.h ****
177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors
179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
180:Drivers/CMSIS/Include/cmsis_gcc.h ****
181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
184:Drivers/CMSIS/Include/cmsis_gcc.h ****
185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
189:Drivers/CMSIS/Include/cmsis_gcc.h **** */
190:Drivers/CMSIS/Include/cmsis_gcc.h ****
191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
ARM GAS /tmp/cckN5aRQ.s page 27
194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
195:Drivers/CMSIS/Include/cmsis_gcc.h **** */
196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
200:Drivers/CMSIS/Include/cmsis_gcc.h ****
201:Drivers/CMSIS/Include/cmsis_gcc.h ****
202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
206:Drivers/CMSIS/Include/cmsis_gcc.h **** */
207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
408 .loc 2 207 27 view .LVU123
409 .LBB11:
208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
410 .loc 2 209 3 view .LVU124
411 .syntax unified
412 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
413 0000 72B6 cpsid i
414 @ 0 "" 2
415 .thumb
416 .syntax unified
417 .L12:
418 .LBE11:
419 .LBE10:
798:Core/Src/main.c **** while (1)
420 .loc 1 798 3 view .LVU125
799:Core/Src/main.c **** {
800:Core/Src/main.c **** }
421 .loc 1 800 3 view .LVU126
798:Core/Src/main.c **** while (1)
422 .loc 1 798 9 view .LVU127
423 0002 FEE7 b .L12
424 .cfi_endproc
425 .LFE348:
427 .section .text.MX_ADC1_Init,"ax",%progbits
428 .align 1
429 .syntax unified
430 .thumb
431 .thumb_func
433 MX_ADC1_Init:
434 .LFB337:
216:Core/Src/main.c ****
435 .loc 1 216 1 view -0
436 .cfi_startproc
437 @ args = 0, pretend = 0, frame = 40
438 @ frame_needed = 0, uses_anonymous_args = 0
439 0000 00B5 push {lr}
440 .cfi_def_cfa_offset 4
441 .cfi_offset 14, -4
442 0002 8BB0 sub sp, sp, #44
443 .cfi_def_cfa_offset 48
222:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
444 .loc 1 222 3 view .LVU129
ARM GAS /tmp/cckN5aRQ.s page 28
222:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
445 .loc 1 222 24 is_stmt 0 view .LVU130
446 0004 0023 movs r3, #0
447 0006 0793 str r3, [sp, #28]
448 0008 0893 str r3, [sp, #32]
449 000a 0993 str r3, [sp, #36]
223:Core/Src/main.c ****
450 .loc 1 223 3 is_stmt 1 view .LVU131
223:Core/Src/main.c ****
451 .loc 1 223 26 is_stmt 0 view .LVU132
452 000c 0093 str r3, [sp]
453 000e 0193 str r3, [sp, #4]
454 0010 0293 str r3, [sp, #8]
455 0012 0393 str r3, [sp, #12]
456 0014 0493 str r3, [sp, #16]
457 0016 0593 str r3, [sp, #20]
458 0018 0693 str r3, [sp, #24]
231:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
459 .loc 1 231 3 is_stmt 1 view .LVU133
231:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
460 .loc 1 231 18 is_stmt 0 view .LVU134
461 001a 2048 ldr r0, .L21
462 001c 204A ldr r2, .L21+4
463 001e 0260 str r2, [r0]
232:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_16B;
464 .loc 1 232 3 is_stmt 1 view .LVU135
232:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_16B;
465 .loc 1 232 29 is_stmt 0 view .LVU136
466 0020 4360 str r3, [r0, #4]
233:Core/Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
467 .loc 1 233 3 is_stmt 1 view .LVU137
233:Core/Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
468 .loc 1 233 25 is_stmt 0 view .LVU138
469 0022 8360 str r3, [r0, #8]
234:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
470 .loc 1 234 3 is_stmt 1 view .LVU139
234:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
471 .loc 1 234 27 is_stmt 0 view .LVU140
472 0024 C360 str r3, [r0, #12]
235:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
473 .loc 1 235 3 is_stmt 1 view .LVU141
235:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
474 .loc 1 235 27 is_stmt 0 view .LVU142
475 0026 0822 movs r2, #8
476 0028 0261 str r2, [r0, #16]
236:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
477 .loc 1 236 3 is_stmt 1 view .LVU143
236:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
478 .loc 1 236 31 is_stmt 0 view .LVU144
479 002a 0375 strb r3, [r0, #20]
237:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1;
480 .loc 1 237 3 is_stmt 1 view .LVU145
237:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1;
481 .loc 1 237 33 is_stmt 0 view .LVU146
482 002c 4375 strb r3, [r0, #21]
238:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
483 .loc 1 238 3 is_stmt 1 view .LVU147
ARM GAS /tmp/cckN5aRQ.s page 29
238:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
484 .loc 1 238 30 is_stmt 0 view .LVU148
485 002e 0122 movs r2, #1
486 0030 8261 str r2, [r0, #24]
239:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T6_TRGO;
487 .loc 1 239 3 is_stmt 1 view .LVU149
239:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T6_TRGO;
488 .loc 1 239 36 is_stmt 0 view .LVU150
489 0032 0377 strb r3, [r0, #28]
240:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
490 .loc 1 240 3 is_stmt 1 view .LVU151
240:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
491 .loc 1 240 31 is_stmt 0 view .LVU152
492 0034 4FF4B462 mov r2, #1440
493 0038 4262 str r2, [r0, #36]
241:Core/Src/main.c **** hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
494 .loc 1 241 3 is_stmt 1 view .LVU153
241:Core/Src/main.c **** hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
495 .loc 1 241 35 is_stmt 0 view .LVU154
496 003a 4FF48062 mov r2, #1024
497 003e 8262 str r2, [r0, #40]
242:Core/Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
498 .loc 1 242 3 is_stmt 1 view .LVU155
242:Core/Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
499 .loc 1 242 39 is_stmt 0 view .LVU156
500 0040 C362 str r3, [r0, #44]
243:Core/Src/main.c **** hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
501 .loc 1 243 3 is_stmt 1 view .LVU157
243:Core/Src/main.c **** hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
502 .loc 1 243 22 is_stmt 0 view .LVU158
503 0042 4FF48052 mov r2, #4096
504 0046 0263 str r2, [r0, #48]
244:Core/Src/main.c **** hadc1.Init.OversamplingMode = DISABLE;
505 .loc 1 244 3 is_stmt 1 view .LVU159
244:Core/Src/main.c **** hadc1.Init.OversamplingMode = DISABLE;
506 .loc 1 244 27 is_stmt 0 view .LVU160
507 0048 4363 str r3, [r0, #52]
245:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
508 .loc 1 245 3 is_stmt 1 view .LVU161
245:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
509 .loc 1 245 31 is_stmt 0 view .LVU162
510 004a 80F83830 strb r3, [r0, #56]
246:Core/Src/main.c **** {
511 .loc 1 246 3 is_stmt 1 view .LVU163
246:Core/Src/main.c **** {
512 .loc 1 246 7 is_stmt 0 view .LVU164
513 004e FFF7FEFF bl HAL_ADC_Init
514 .LVL13:
246:Core/Src/main.c **** {
515 .loc 1 246 6 discriminator 1 view .LVU165
516 0052 E8B9 cbnz r0, .L18
253:Core/Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
517 .loc 1 253 3 is_stmt 1 view .LVU166
253:Core/Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
518 .loc 1 253 18 is_stmt 0 view .LVU167
519 0054 0023 movs r3, #0
520 0056 0793 str r3, [sp, #28]
ARM GAS /tmp/cckN5aRQ.s page 30
254:Core/Src/main.c **** {
521 .loc 1 254 3 is_stmt 1 view .LVU168
254:Core/Src/main.c **** {
522 .loc 1 254 7 is_stmt 0 view .LVU169
523 0058 07A9 add r1, sp, #28
524 005a 1048 ldr r0, .L21
525 005c FFF7FEFF bl HAL_ADCEx_MultiModeConfigChannel
526 .LVL14:
254:Core/Src/main.c **** {
527 .loc 1 254 6 discriminator 1 view .LVU170
528 0060 C0B9 cbnz r0, .L19
261:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
529 .loc 1 261 3 is_stmt 1 view .LVU171
261:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
530 .loc 1 261 19 is_stmt 0 view .LVU172
531 0062 104B ldr r3, .L21+8
532 0064 0093 str r3, [sp]
262:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES_5;
533 .loc 1 262 3 is_stmt 1 view .LVU173
262:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES_5;
534 .loc 1 262 16 is_stmt 0 view .LVU174
535 0066 0623 movs r3, #6
536 0068 0193 str r3, [sp, #4]
263:Core/Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
537 .loc 1 263 3 is_stmt 1 view .LVU175
263:Core/Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
538 .loc 1 263 24 is_stmt 0 view .LVU176
539 006a 0323 movs r3, #3
540 006c 0293 str r3, [sp, #8]
264:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
541 .loc 1 264 3 is_stmt 1 view .LVU177
264:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
542 .loc 1 264 22 is_stmt 0 view .LVU178
543 006e 40F2FF73 movw r3, #2047
544 0072 0393 str r3, [sp, #12]
265:Core/Src/main.c **** sConfig.Offset = 0;
545 .loc 1 265 3 is_stmt 1 view .LVU179
265:Core/Src/main.c **** sConfig.Offset = 0;
546 .loc 1 265 24 is_stmt 0 view .LVU180
547 0074 0423 movs r3, #4
548 0076 0493 str r3, [sp, #16]
266:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE;
549 .loc 1 266 3 is_stmt 1 view .LVU181
266:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE;
550 .loc 1 266 18 is_stmt 0 view .LVU182
551 0078 0023 movs r3, #0
552 007a 0593 str r3, [sp, #20]
267:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
553 .loc 1 267 3 is_stmt 1 view .LVU183
267:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
554 .loc 1 267 34 is_stmt 0 view .LVU184
555 007c 8DF81930 strb r3, [sp, #25]
268:Core/Src/main.c **** {
556 .loc 1 268 3 is_stmt 1 view .LVU185
268:Core/Src/main.c **** {
557 .loc 1 268 7 is_stmt 0 view .LVU186
558 0080 6946 mov r1, sp
ARM GAS /tmp/cckN5aRQ.s page 31
559 0082 0648 ldr r0, .L21
560 0084 FFF7FEFF bl HAL_ADC_ConfigChannel
561 .LVL15:
268:Core/Src/main.c **** {
562 .loc 1 268 6 discriminator 1 view .LVU187
563 0088 30B9 cbnz r0, .L20
276:Core/Src/main.c ****
564 .loc 1 276 1 view .LVU188
565 008a 0BB0 add sp, sp, #44
566 .cfi_remember_state
567 .cfi_def_cfa_offset 4
568 @ sp needed
569 008c 5DF804FB ldr pc, [sp], #4
570 .L18:
571 .cfi_restore_state
248:Core/Src/main.c **** }
572 .loc 1 248 5 is_stmt 1 view .LVU189
573 0090 FFF7FEFF bl Error_Handler
574 .LVL16:
575 .L19:
256:Core/Src/main.c **** }
576 .loc 1 256 5 view .LVU190
577 0094 FFF7FEFF bl Error_Handler
578 .LVL17:
579 .L20:
270:Core/Src/main.c **** }
580 .loc 1 270 5 view .LVU191
581 0098 FFF7FEFF bl Error_Handler
582 .LVL18:
583 .L22:
584 .align 2
585 .L21:
586 009c 00000000 .word hadc1
587 00a0 00200240 .word 1073881088
588 00a4 0800900C .word 210763784
589 .cfi_endproc
590 .LFE337:
592 .section .text.MX_FDCAN1_Init,"ax",%progbits
593 .align 1
594 .syntax unified
595 .thumb
596 .thumb_func
598 MX_FDCAN1_Init:
599 .LFB338:
284:Core/Src/main.c ****
600 .loc 1 284 1 view -0
601 .cfi_startproc
602 @ args = 0, pretend = 0, frame = 0
603 @ frame_needed = 0, uses_anonymous_args = 0
604 0000 08B5 push {r3, lr}
605 .cfi_def_cfa_offset 8
606 .cfi_offset 3, -8
607 .cfi_offset 14, -4
293:Core/Src/main.c **** hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
608 .loc 1 293 3 view .LVU193
293:Core/Src/main.c **** hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
609 .loc 1 293 20 is_stmt 0 view .LVU194
ARM GAS /tmp/cckN5aRQ.s page 32
610 0002 1548 ldr r0, .L27
611 0004 154B ldr r3, .L27+4
612 0006 0360 str r3, [r0]
294:Core/Src/main.c **** hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
613 .loc 1 294 3 is_stmt 1 view .LVU195
294:Core/Src/main.c **** hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
614 .loc 1 294 28 is_stmt 0 view .LVU196
615 0008 0023 movs r3, #0
616 000a 8360 str r3, [r0, #8]
295:Core/Src/main.c **** hfdcan1.Init.AutoRetransmission = DISABLE;
617 .loc 1 295 3 is_stmt 1 view .LVU197
295:Core/Src/main.c **** hfdcan1.Init.AutoRetransmission = DISABLE;
618 .loc 1 295 21 is_stmt 0 view .LVU198
619 000c C360 str r3, [r0, #12]
296:Core/Src/main.c **** hfdcan1.Init.TransmitPause = DISABLE;
620 .loc 1 296 3 is_stmt 1 view .LVU199
296:Core/Src/main.c **** hfdcan1.Init.TransmitPause = DISABLE;
621 .loc 1 296 35 is_stmt 0 view .LVU200
622 000e 0374 strb r3, [r0, #16]
297:Core/Src/main.c **** hfdcan1.Init.ProtocolException = DISABLE;
623 .loc 1 297 3 is_stmt 1 view .LVU201
297:Core/Src/main.c **** hfdcan1.Init.ProtocolException = DISABLE;
624 .loc 1 297 30 is_stmt 0 view .LVU202
625 0010 4374 strb r3, [r0, #17]
298:Core/Src/main.c **** hfdcan1.Init.NominalPrescaler = 3;
626 .loc 1 298 3 is_stmt 1 view .LVU203
298:Core/Src/main.c **** hfdcan1.Init.NominalPrescaler = 3;
627 .loc 1 298 34 is_stmt 0 view .LVU204
628 0012 8374 strb r3, [r0, #18]
299:Core/Src/main.c **** hfdcan1.Init.NominalSyncJumpWidth = 1;
629 .loc 1 299 3 is_stmt 1 view .LVU205
299:Core/Src/main.c **** hfdcan1.Init.NominalSyncJumpWidth = 1;
630 .loc 1 299 33 is_stmt 0 view .LVU206
631 0014 0322 movs r2, #3
632 0016 4261 str r2, [r0, #20]
300:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg1 = 13;
633 .loc 1 300 3 is_stmt 1 view .LVU207
300:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg1 = 13;
634 .loc 1 300 37 is_stmt 0 view .LVU208
635 0018 0122 movs r2, #1
636 001a 8261 str r2, [r0, #24]
301:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg2 = 2;
637 .loc 1 301 3 is_stmt 1 view .LVU209
301:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg2 = 2;
638 .loc 1 301 32 is_stmt 0 view .LVU210
639 001c 0D21 movs r1, #13
640 001e C161 str r1, [r0, #28]
302:Core/Src/main.c **** hfdcan1.Init.DataPrescaler = 1;
641 .loc 1 302 3 is_stmt 1 view .LVU211
302:Core/Src/main.c **** hfdcan1.Init.DataPrescaler = 1;
642 .loc 1 302 32 is_stmt 0 view .LVU212
643 0020 0221 movs r1, #2
644 0022 0162 str r1, [r0, #32]
303:Core/Src/main.c **** hfdcan1.Init.DataSyncJumpWidth = 1;
645 .loc 1 303 3 is_stmt 1 view .LVU213
303:Core/Src/main.c **** hfdcan1.Init.DataSyncJumpWidth = 1;
646 .loc 1 303 30 is_stmt 0 view .LVU214
ARM GAS /tmp/cckN5aRQ.s page 33
647 0024 4262 str r2, [r0, #36]
304:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg1 = 1;
648 .loc 1 304 3 is_stmt 1 view .LVU215
304:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg1 = 1;
649 .loc 1 304 34 is_stmt 0 view .LVU216
650 0026 8262 str r2, [r0, #40]
305:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg2 = 1;
651 .loc 1 305 3 is_stmt 1 view .LVU217
305:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg2 = 1;
652 .loc 1 305 29 is_stmt 0 view .LVU218
653 0028 C262 str r2, [r0, #44]
306:Core/Src/main.c **** hfdcan1.Init.MessageRAMOffset = 0;
654 .loc 1 306 3 is_stmt 1 view .LVU219
306:Core/Src/main.c **** hfdcan1.Init.MessageRAMOffset = 0;
655 .loc 1 306 29 is_stmt 0 view .LVU220
656 002a 0263 str r2, [r0, #48]
307:Core/Src/main.c **** hfdcan1.Init.StdFiltersNbr = 0;
657 .loc 1 307 3 is_stmt 1 view .LVU221
307:Core/Src/main.c **** hfdcan1.Init.StdFiltersNbr = 0;
658 .loc 1 307 33 is_stmt 0 view .LVU222
659 002c 4363 str r3, [r0, #52]
308:Core/Src/main.c **** hfdcan1.Init.ExtFiltersNbr = 0;
660 .loc 1 308 3 is_stmt 1 view .LVU223
308:Core/Src/main.c **** hfdcan1.Init.ExtFiltersNbr = 0;
661 .loc 1 308 30 is_stmt 0 view .LVU224
662 002e 8363 str r3, [r0, #56]
309:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtsNbr = 0;
663 .loc 1 309 3 is_stmt 1 view .LVU225
309:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtsNbr = 0;
664 .loc 1 309 30 is_stmt 0 view .LVU226
665 0030 C363 str r3, [r0, #60]
310:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
666 .loc 1 310 3 is_stmt 1 view .LVU227
310:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
667 .loc 1 310 32 is_stmt 0 view .LVU228
668 0032 0364 str r3, [r0, #64]
311:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtsNbr = 0;
669 .loc 1 311 3 is_stmt 1 view .LVU229
311:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtsNbr = 0;
670 .loc 1 311 32 is_stmt 0 view .LVU230
671 0034 0422 movs r2, #4
672 0036 4264 str r2, [r0, #68]
312:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
673 .loc 1 312 3 is_stmt 1 view .LVU231
312:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
674 .loc 1 312 32 is_stmt 0 view .LVU232
675 0038 8364 str r3, [r0, #72]
313:Core/Src/main.c **** hfdcan1.Init.RxBuffersNbr = 0;
676 .loc 1 313 3 is_stmt 1 view .LVU233
313:Core/Src/main.c **** hfdcan1.Init.RxBuffersNbr = 0;
677 .loc 1 313 32 is_stmt 0 view .LVU234
678 003a C264 str r2, [r0, #76]
314:Core/Src/main.c **** hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
679 .loc 1 314 3 is_stmt 1 view .LVU235
314:Core/Src/main.c **** hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
680 .loc 1 314 29 is_stmt 0 view .LVU236
681 003c 0365 str r3, [r0, #80]
ARM GAS /tmp/cckN5aRQ.s page 34
315:Core/Src/main.c **** hfdcan1.Init.TxEventsNbr = 0;
682 .loc 1 315 3 is_stmt 1 view .LVU237
315:Core/Src/main.c **** hfdcan1.Init.TxEventsNbr = 0;
683 .loc 1 315 29 is_stmt 0 view .LVU238
684 003e 4265 str r2, [r0, #84]
316:Core/Src/main.c **** hfdcan1.Init.TxBuffersNbr = 0;
685 .loc 1 316 3 is_stmt 1 view .LVU239
316:Core/Src/main.c **** hfdcan1.Init.TxBuffersNbr = 0;
686 .loc 1 316 28 is_stmt 0 view .LVU240
687 0040 8365 str r3, [r0, #88]
317:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueElmtsNbr = 0;
688 .loc 1 317 3 is_stmt 1 view .LVU241
317:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueElmtsNbr = 0;
689 .loc 1 317 29 is_stmt 0 view .LVU242
690 0042 C365 str r3, [r0, #92]
318:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
691 .loc 1 318 3 is_stmt 1 view .LVU243
318:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
692 .loc 1 318 36 is_stmt 0 view .LVU244
693 0044 0366 str r3, [r0, #96]
319:Core/Src/main.c **** hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
694 .loc 1 319 3 is_stmt 1 view .LVU245
319:Core/Src/main.c **** hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
695 .loc 1 319 32 is_stmt 0 view .LVU246
696 0046 4366 str r3, [r0, #100]
320:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
697 .loc 1 320 3 is_stmt 1 view .LVU247
320:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
698 .loc 1 320 27 is_stmt 0 view .LVU248
699 0048 8266 str r2, [r0, #104]
321:Core/Src/main.c **** {
700 .loc 1 321 3 is_stmt 1 view .LVU249
321:Core/Src/main.c **** {
701 .loc 1 321 7 is_stmt 0 view .LVU250
702 004a FFF7FEFF bl HAL_FDCAN_Init
703 .LVL19:
321:Core/Src/main.c **** {
704 .loc 1 321 6 discriminator 1 view .LVU251
705 004e 00B9 cbnz r0, .L26
329:Core/Src/main.c ****
706 .loc 1 329 1 view .LVU252
707 0050 08BD pop {r3, pc}
708 .L26:
323:Core/Src/main.c **** }
709 .loc 1 323 5 is_stmt 1 view .LVU253
710 0052 FFF7FEFF bl Error_Handler
711 .LVL20:
712 .L28:
713 0056 00BF .align 2
714 .L27:
715 0058 00000000 .word hfdcan1
716 005c 00A00040 .word 1073782784
717 .cfi_endproc
718 .LFE338:
720 .section .text.MX_FDCAN2_Init,"ax",%progbits
721 .align 1
722 .syntax unified
ARM GAS /tmp/cckN5aRQ.s page 35
723 .thumb
724 .thumb_func
726 MX_FDCAN2_Init:
727 .LFB339:
337:Core/Src/main.c ****
728 .loc 1 337 1 view -0
729 .cfi_startproc
730 @ args = 0, pretend = 0, frame = 0
731 @ frame_needed = 0, uses_anonymous_args = 0
732 0000 08B5 push {r3, lr}
733 .cfi_def_cfa_offset 8
734 .cfi_offset 3, -8
735 .cfi_offset 14, -4
346:Core/Src/main.c **** hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
736 .loc 1 346 3 view .LVU255
346:Core/Src/main.c **** hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
737 .loc 1 346 20 is_stmt 0 view .LVU256
738 0002 1548 ldr r0, .L33
739 0004 154B ldr r3, .L33+4
740 0006 0360 str r3, [r0]
347:Core/Src/main.c **** hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
741 .loc 1 347 3 is_stmt 1 view .LVU257
347:Core/Src/main.c **** hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
742 .loc 1 347 28 is_stmt 0 view .LVU258
743 0008 0023 movs r3, #0
744 000a 8360 str r3, [r0, #8]
348:Core/Src/main.c **** hfdcan2.Init.AutoRetransmission = DISABLE;
745 .loc 1 348 3 is_stmt 1 view .LVU259
348:Core/Src/main.c **** hfdcan2.Init.AutoRetransmission = DISABLE;
746 .loc 1 348 21 is_stmt 0 view .LVU260
747 000c C360 str r3, [r0, #12]
349:Core/Src/main.c **** hfdcan2.Init.TransmitPause = DISABLE;
748 .loc 1 349 3 is_stmt 1 view .LVU261
349:Core/Src/main.c **** hfdcan2.Init.TransmitPause = DISABLE;
749 .loc 1 349 35 is_stmt 0 view .LVU262
750 000e 0374 strb r3, [r0, #16]
350:Core/Src/main.c **** hfdcan2.Init.ProtocolException = DISABLE;
751 .loc 1 350 3 is_stmt 1 view .LVU263
350:Core/Src/main.c **** hfdcan2.Init.ProtocolException = DISABLE;
752 .loc 1 350 30 is_stmt 0 view .LVU264
753 0010 4374 strb r3, [r0, #17]
351:Core/Src/main.c **** hfdcan2.Init.NominalPrescaler = 3;
754 .loc 1 351 3 is_stmt 1 view .LVU265
351:Core/Src/main.c **** hfdcan2.Init.NominalPrescaler = 3;
755 .loc 1 351 34 is_stmt 0 view .LVU266
756 0012 8374 strb r3, [r0, #18]
352:Core/Src/main.c **** hfdcan2.Init.NominalSyncJumpWidth = 1;
757 .loc 1 352 3 is_stmt 1 view .LVU267
352:Core/Src/main.c **** hfdcan2.Init.NominalSyncJumpWidth = 1;
758 .loc 1 352 33 is_stmt 0 view .LVU268
759 0014 0322 movs r2, #3
760 0016 4261 str r2, [r0, #20]
353:Core/Src/main.c **** hfdcan2.Init.NominalTimeSeg1 = 13;
761 .loc 1 353 3 is_stmt 1 view .LVU269
353:Core/Src/main.c **** hfdcan2.Init.NominalTimeSeg1 = 13;
762 .loc 1 353 37 is_stmt 0 view .LVU270
763 0018 0122 movs r2, #1
ARM GAS /tmp/cckN5aRQ.s page 36
764 001a 8261 str r2, [r0, #24]
354:Core/Src/main.c **** hfdcan2.Init.NominalTimeSeg2 = 2;
765 .loc 1 354 3 is_stmt 1 view .LVU271
354:Core/Src/main.c **** hfdcan2.Init.NominalTimeSeg2 = 2;
766 .loc 1 354 32 is_stmt 0 view .LVU272
767 001c 0D21 movs r1, #13
768 001e C161 str r1, [r0, #28]
355:Core/Src/main.c **** hfdcan2.Init.DataPrescaler = 1;
769 .loc 1 355 3 is_stmt 1 view .LVU273
355:Core/Src/main.c **** hfdcan2.Init.DataPrescaler = 1;
770 .loc 1 355 32 is_stmt 0 view .LVU274
771 0020 0221 movs r1, #2
772 0022 0162 str r1, [r0, #32]
356:Core/Src/main.c **** hfdcan2.Init.DataSyncJumpWidth = 1;
773 .loc 1 356 3 is_stmt 1 view .LVU275
356:Core/Src/main.c **** hfdcan2.Init.DataSyncJumpWidth = 1;
774 .loc 1 356 30 is_stmt 0 view .LVU276
775 0024 4262 str r2, [r0, #36]
357:Core/Src/main.c **** hfdcan2.Init.DataTimeSeg1 = 1;
776 .loc 1 357 3 is_stmt 1 view .LVU277
357:Core/Src/main.c **** hfdcan2.Init.DataTimeSeg1 = 1;
777 .loc 1 357 34 is_stmt 0 view .LVU278
778 0026 8262 str r2, [r0, #40]
358:Core/Src/main.c **** hfdcan2.Init.DataTimeSeg2 = 1;
779 .loc 1 358 3 is_stmt 1 view .LVU279
358:Core/Src/main.c **** hfdcan2.Init.DataTimeSeg2 = 1;
780 .loc 1 358 29 is_stmt 0 view .LVU280
781 0028 C262 str r2, [r0, #44]
359:Core/Src/main.c **** hfdcan2.Init.MessageRAMOffset = 0;
782 .loc 1 359 3 is_stmt 1 view .LVU281
359:Core/Src/main.c **** hfdcan2.Init.MessageRAMOffset = 0;
783 .loc 1 359 29 is_stmt 0 view .LVU282
784 002a 0263 str r2, [r0, #48]
360:Core/Src/main.c **** hfdcan2.Init.StdFiltersNbr = 0;
785 .loc 1 360 3 is_stmt 1 view .LVU283
360:Core/Src/main.c **** hfdcan2.Init.StdFiltersNbr = 0;
786 .loc 1 360 33 is_stmt 0 view .LVU284
787 002c 4363 str r3, [r0, #52]
361:Core/Src/main.c **** hfdcan2.Init.ExtFiltersNbr = 0;
788 .loc 1 361 3 is_stmt 1 view .LVU285
361:Core/Src/main.c **** hfdcan2.Init.ExtFiltersNbr = 0;
789 .loc 1 361 30 is_stmt 0 view .LVU286
790 002e 8363 str r3, [r0, #56]
362:Core/Src/main.c **** hfdcan2.Init.RxFifo0ElmtsNbr = 0;
791 .loc 1 362 3 is_stmt 1 view .LVU287
362:Core/Src/main.c **** hfdcan2.Init.RxFifo0ElmtsNbr = 0;
792 .loc 1 362 30 is_stmt 0 view .LVU288
793 0030 C363 str r3, [r0, #60]
363:Core/Src/main.c **** hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
794 .loc 1 363 3 is_stmt 1 view .LVU289
363:Core/Src/main.c **** hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
795 .loc 1 363 32 is_stmt 0 view .LVU290
796 0032 0364 str r3, [r0, #64]
364:Core/Src/main.c **** hfdcan2.Init.RxFifo1ElmtsNbr = 0;
797 .loc 1 364 3 is_stmt 1 view .LVU291
364:Core/Src/main.c **** hfdcan2.Init.RxFifo1ElmtsNbr = 0;
798 .loc 1 364 32 is_stmt 0 view .LVU292
ARM GAS /tmp/cckN5aRQ.s page 37
799 0034 0422 movs r2, #4
800 0036 4264 str r2, [r0, #68]
365:Core/Src/main.c **** hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
801 .loc 1 365 3 is_stmt 1 view .LVU293
365:Core/Src/main.c **** hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
802 .loc 1 365 32 is_stmt 0 view .LVU294
803 0038 8364 str r3, [r0, #72]
366:Core/Src/main.c **** hfdcan2.Init.RxBuffersNbr = 0;
804 .loc 1 366 3 is_stmt 1 view .LVU295
366:Core/Src/main.c **** hfdcan2.Init.RxBuffersNbr = 0;
805 .loc 1 366 32 is_stmt 0 view .LVU296
806 003a C264 str r2, [r0, #76]
367:Core/Src/main.c **** hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
807 .loc 1 367 3 is_stmt 1 view .LVU297
367:Core/Src/main.c **** hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
808 .loc 1 367 29 is_stmt 0 view .LVU298
809 003c 0365 str r3, [r0, #80]
368:Core/Src/main.c **** hfdcan2.Init.TxEventsNbr = 0;
810 .loc 1 368 3 is_stmt 1 view .LVU299
368:Core/Src/main.c **** hfdcan2.Init.TxEventsNbr = 0;
811 .loc 1 368 29 is_stmt 0 view .LVU300
812 003e 4265 str r2, [r0, #84]
369:Core/Src/main.c **** hfdcan2.Init.TxBuffersNbr = 0;
813 .loc 1 369 3 is_stmt 1 view .LVU301
369:Core/Src/main.c **** hfdcan2.Init.TxBuffersNbr = 0;
814 .loc 1 369 28 is_stmt 0 view .LVU302
815 0040 8365 str r3, [r0, #88]
370:Core/Src/main.c **** hfdcan2.Init.TxFifoQueueElmtsNbr = 0;
816 .loc 1 370 3 is_stmt 1 view .LVU303
370:Core/Src/main.c **** hfdcan2.Init.TxFifoQueueElmtsNbr = 0;
817 .loc 1 370 29 is_stmt 0 view .LVU304
818 0042 C365 str r3, [r0, #92]
371:Core/Src/main.c **** hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
819 .loc 1 371 3 is_stmt 1 view .LVU305
371:Core/Src/main.c **** hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
820 .loc 1 371 36 is_stmt 0 view .LVU306
821 0044 0366 str r3, [r0, #96]
372:Core/Src/main.c **** hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
822 .loc 1 372 3 is_stmt 1 view .LVU307
372:Core/Src/main.c **** hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
823 .loc 1 372 32 is_stmt 0 view .LVU308
824 0046 4366 str r3, [r0, #100]
373:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
825 .loc 1 373 3 is_stmt 1 view .LVU309
373:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
826 .loc 1 373 27 is_stmt 0 view .LVU310
827 0048 8266 str r2, [r0, #104]
374:Core/Src/main.c **** {
828 .loc 1 374 3 is_stmt 1 view .LVU311
374:Core/Src/main.c **** {
829 .loc 1 374 7 is_stmt 0 view .LVU312
830 004a FFF7FEFF bl HAL_FDCAN_Init
831 .LVL21:
374:Core/Src/main.c **** {
832 .loc 1 374 6 discriminator 1 view .LVU313
833 004e 00B9 cbnz r0, .L32
382:Core/Src/main.c ****
ARM GAS /tmp/cckN5aRQ.s page 38
834 .loc 1 382 1 view .LVU314
835 0050 08BD pop {r3, pc}
836 .L32:
376:Core/Src/main.c **** }
837 .loc 1 376 5 is_stmt 1 view .LVU315
838 0052 FFF7FEFF bl Error_Handler
839 .LVL22:
840 .L34:
841 0056 00BF .align 2
842 .L33:
843 0058 00000000 .word hfdcan2
844 005c 00A40040 .word 1073783808
845 .cfi_endproc
846 .LFE339:
848 .section .text.MX_TIM1_Init,"ax",%progbits
849 .align 1
850 .syntax unified
851 .thumb
852 .thumb_func
854 MX_TIM1_Init:
855 .LFB340:
390:Core/Src/main.c ****
856 .loc 1 390 1 view -0
857 .cfi_startproc
858 @ args = 0, pretend = 0, frame = 112
859 @ frame_needed = 0, uses_anonymous_args = 0
860 0000 10B5 push {r4, lr}
861 .cfi_def_cfa_offset 8
862 .cfi_offset 4, -8
863 .cfi_offset 14, -4
864 0002 9CB0 sub sp, sp, #112
865 .cfi_def_cfa_offset 120
396:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
866 .loc 1 396 3 view .LVU317
396:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
867 .loc 1 396 26 is_stmt 0 view .LVU318
868 0004 0024 movs r4, #0
869 0006 1894 str r4, [sp, #96]
870 0008 1994 str r4, [sp, #100]
871 000a 1A94 str r4, [sp, #104]
872 000c 1B94 str r4, [sp, #108]
397:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
873 .loc 1 397 3 is_stmt 1 view .LVU319
397:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
874 .loc 1 397 27 is_stmt 0 view .LVU320
875 000e 1594 str r4, [sp, #84]
876 0010 1694 str r4, [sp, #88]
877 0012 1794 str r4, [sp, #92]
398:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
878 .loc 1 398 3 is_stmt 1 view .LVU321
398:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
879 .loc 1 398 22 is_stmt 0 view .LVU322
880 0014 0E94 str r4, [sp, #56]
881 0016 0F94 str r4, [sp, #60]
882 0018 1094 str r4, [sp, #64]
883 001a 1194 str r4, [sp, #68]
884 001c 1294 str r4, [sp, #72]
ARM GAS /tmp/cckN5aRQ.s page 39
885 001e 1394 str r4, [sp, #76]
886 0020 1494 str r4, [sp, #80]
399:Core/Src/main.c ****
887 .loc 1 399 3 is_stmt 1 view .LVU323
399:Core/Src/main.c ****
888 .loc 1 399 34 is_stmt 0 view .LVU324
889 0022 3422 movs r2, #52
890 0024 2146 mov r1, r4
891 0026 01A8 add r0, sp, #4
892 0028 FFF7FEFF bl memset
893 .LVL23:
404:Core/Src/main.c **** htim1.Init.Prescaler = 0;
894 .loc 1 404 3 is_stmt 1 view .LVU325
404:Core/Src/main.c **** htim1.Init.Prescaler = 0;
895 .loc 1 404 18 is_stmt 0 view .LVU326
896 002c 3A48 ldr r0, .L55
897 002e 3B4B ldr r3, .L55+4
898 0030 0360 str r3, [r0]
405:Core/Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
899 .loc 1 405 3 is_stmt 1 view .LVU327
405:Core/Src/main.c **** htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
900 .loc 1 405 24 is_stmt 0 view .LVU328
901 0032 4460 str r4, [r0, #4]
406:Core/Src/main.c **** htim1.Init.Period = 65535;
902 .loc 1 406 3 is_stmt 1 view .LVU329
406:Core/Src/main.c **** htim1.Init.Period = 65535;
903 .loc 1 406 26 is_stmt 0 view .LVU330
904 0034 8460 str r4, [r0, #8]
407:Core/Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
905 .loc 1 407 3 is_stmt 1 view .LVU331
407:Core/Src/main.c **** htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
906 .loc 1 407 21 is_stmt 0 view .LVU332
907 0036 4FF6FF73 movw r3, #65535
908 003a C360 str r3, [r0, #12]
408:Core/Src/main.c **** htim1.Init.RepetitionCounter = 0;
909 .loc 1 408 3 is_stmt 1 view .LVU333
408:Core/Src/main.c **** htim1.Init.RepetitionCounter = 0;
910 .loc 1 408 28 is_stmt 0 view .LVU334
911 003c 0461 str r4, [r0, #16]
409:Core/Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
912 .loc 1 409 3 is_stmt 1 view .LVU335
409:Core/Src/main.c **** htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
913 .loc 1 409 32 is_stmt 0 view .LVU336
914 003e 4461 str r4, [r0, #20]
410:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
915 .loc 1 410 3 is_stmt 1 view .LVU337
410:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
916 .loc 1 410 32 is_stmt 0 view .LVU338
917 0040 8461 str r4, [r0, #24]
411:Core/Src/main.c **** {
918 .loc 1 411 3 is_stmt 1 view .LVU339
411:Core/Src/main.c **** {
919 .loc 1 411 7 is_stmt 0 view .LVU340
920 0042 FFF7FEFF bl HAL_TIM_Base_Init
921 .LVL24:
411:Core/Src/main.c **** {
922 .loc 1 411 6 discriminator 1 view .LVU341
ARM GAS /tmp/cckN5aRQ.s page 40
923 0046 0028 cmp r0, #0
924 0048 53D1 bne .L46
415:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
925 .loc 1 415 3 is_stmt 1 view .LVU342
415:Core/Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
926 .loc 1 415 34 is_stmt 0 view .LVU343
927 004a 4FF48053 mov r3, #4096
928 004e 1893 str r3, [sp, #96]
416:Core/Src/main.c **** {
929 .loc 1 416 3 is_stmt 1 view .LVU344
416:Core/Src/main.c **** {
930 .loc 1 416 7 is_stmt 0 view .LVU345
931 0050 18A9 add r1, sp, #96
932 0052 3148 ldr r0, .L55
933 0054 FFF7FEFF bl HAL_TIM_ConfigClockSource
934 .LVL25:
416:Core/Src/main.c **** {
935 .loc 1 416 6 discriminator 1 view .LVU346
936 0058 0028 cmp r0, #0
937 005a 4CD1 bne .L47
420:Core/Src/main.c **** {
938 .loc 1 420 3 is_stmt 1 view .LVU347
420:Core/Src/main.c **** {
939 .loc 1 420 7 is_stmt 0 view .LVU348
940 005c 2E48 ldr r0, .L55
941 005e FFF7FEFF bl HAL_TIM_PWM_Init
942 .LVL26:
420:Core/Src/main.c **** {
943 .loc 1 420 6 discriminator 1 view .LVU349
944 0062 0028 cmp r0, #0
945 0064 49D1 bne .L48
424:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
946 .loc 1 424 3 is_stmt 1 view .LVU350
424:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
947 .loc 1 424 37 is_stmt 0 view .LVU351
948 0066 0023 movs r3, #0
949 0068 1593 str r3, [sp, #84]
425:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
950 .loc 1 425 3 is_stmt 1 view .LVU352
425:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
951 .loc 1 425 38 is_stmt 0 view .LVU353
952 006a 1693 str r3, [sp, #88]
426:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
953 .loc 1 426 3 is_stmt 1 view .LVU354
426:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
954 .loc 1 426 33 is_stmt 0 view .LVU355
955 006c 1793 str r3, [sp, #92]
427:Core/Src/main.c **** {
956 .loc 1 427 3 is_stmt 1 view .LVU356
427:Core/Src/main.c **** {
957 .loc 1 427 7 is_stmt 0 view .LVU357
958 006e 15A9 add r1, sp, #84
959 0070 2948 ldr r0, .L55
960 0072 FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
961 .LVL27:
427:Core/Src/main.c **** {
962 .loc 1 427 6 discriminator 1 view .LVU358
ARM GAS /tmp/cckN5aRQ.s page 41
963 0076 0028 cmp r0, #0
964 0078 41D1 bne .L49
431:Core/Src/main.c **** sConfigOC.Pulse = 0;
965 .loc 1 431 3 is_stmt 1 view .LVU359
431:Core/Src/main.c **** sConfigOC.Pulse = 0;
966 .loc 1 431 20 is_stmt 0 view .LVU360
967 007a 6023 movs r3, #96
968 007c 0E93 str r3, [sp, #56]
432:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
969 .loc 1 432 3 is_stmt 1 view .LVU361
432:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
970 .loc 1 432 19 is_stmt 0 view .LVU362
971 007e 0022 movs r2, #0
972 0080 0F92 str r2, [sp, #60]
433:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
973 .loc 1 433 3 is_stmt 1 view .LVU363
433:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
974 .loc 1 433 24 is_stmt 0 view .LVU364
975 0082 1092 str r2, [sp, #64]
434:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
976 .loc 1 434 3 is_stmt 1 view .LVU365
434:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
977 .loc 1 434 25 is_stmt 0 view .LVU366
978 0084 1192 str r2, [sp, #68]
435:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
979 .loc 1 435 3 is_stmt 1 view .LVU367
435:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
980 .loc 1 435 24 is_stmt 0 view .LVU368
981 0086 1292 str r2, [sp, #72]
436:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
982 .loc 1 436 3 is_stmt 1 view .LVU369
436:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
983 .loc 1 436 25 is_stmt 0 view .LVU370
984 0088 1392 str r2, [sp, #76]
437:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
985 .loc 1 437 3 is_stmt 1 view .LVU371
437:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
986 .loc 1 437 26 is_stmt 0 view .LVU372
987 008a 1492 str r2, [sp, #80]
438:Core/Src/main.c **** {
988 .loc 1 438 3 is_stmt 1 view .LVU373
438:Core/Src/main.c **** {
989 .loc 1 438 7 is_stmt 0 view .LVU374
990 008c 0EA9 add r1, sp, #56
991 008e 2248 ldr r0, .L55
992 0090 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
993 .LVL28:
438:Core/Src/main.c **** {
994 .loc 1 438 6 discriminator 1 view .LVU375
995 0094 0028 cmp r0, #0
996 0096 34D1 bne .L50
442:Core/Src/main.c **** {
997 .loc 1 442 3 is_stmt 1 view .LVU376
442:Core/Src/main.c **** {
998 .loc 1 442 7 is_stmt 0 view .LVU377
999 0098 0422 movs r2, #4
1000 009a 0EA9 add r1, sp, #56
ARM GAS /tmp/cckN5aRQ.s page 42
1001 009c 1E48 ldr r0, .L55
1002 009e FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
1003 .LVL29:
442:Core/Src/main.c **** {
1004 .loc 1 442 6 discriminator 1 view .LVU378
1005 00a2 0028 cmp r0, #0
1006 00a4 2FD1 bne .L51
446:Core/Src/main.c **** {
1007 .loc 1 446 3 is_stmt 1 view .LVU379
446:Core/Src/main.c **** {
1008 .loc 1 446 7 is_stmt 0 view .LVU380
1009 00a6 0822 movs r2, #8
1010 00a8 0EA9 add r1, sp, #56
1011 00aa 1B48 ldr r0, .L55
1012 00ac FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
1013 .LVL30:
446:Core/Src/main.c **** {
1014 .loc 1 446 6 discriminator 1 view .LVU381
1015 00b0 58BB cbnz r0, .L52
450:Core/Src/main.c **** {
1016 .loc 1 450 3 is_stmt 1 view .LVU382
450:Core/Src/main.c **** {
1017 .loc 1 450 7 is_stmt 0 view .LVU383
1018 00b2 0C22 movs r2, #12
1019 00b4 0EA9 add r1, sp, #56
1020 00b6 1848 ldr r0, .L55
1021 00b8 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
1022 .LVL31:
450:Core/Src/main.c **** {
1023 .loc 1 450 6 discriminator 1 view .LVU384
1024 00bc 38BB cbnz r0, .L53
454:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
1025 .loc 1 454 3 is_stmt 1 view .LVU385
454:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
1026 .loc 1 454 40 is_stmt 0 view .LVU386
1027 00be 0023 movs r3, #0
1028 00c0 0193 str r3, [sp, #4]
455:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
1029 .loc 1 455 3 is_stmt 1 view .LVU387
455:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
1030 .loc 1 455 41 is_stmt 0 view .LVU388
1031 00c2 0293 str r3, [sp, #8]
456:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0;
1032 .loc 1 456 3 is_stmt 1 view .LVU389
456:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0;
1033 .loc 1 456 34 is_stmt 0 view .LVU390
1034 00c4 0393 str r3, [sp, #12]
457:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
1035 .loc 1 457 3 is_stmt 1 view .LVU391
457:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
1036 .loc 1 457 33 is_stmt 0 view .LVU392
1037 00c6 0493 str r3, [sp, #16]
458:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
1038 .loc 1 458 3 is_stmt 1 view .LVU393
458:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
1039 .loc 1 458 35 is_stmt 0 view .LVU394
1040 00c8 0593 str r3, [sp, #20]
ARM GAS /tmp/cckN5aRQ.s page 43
459:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0;
1041 .loc 1 459 3 is_stmt 1 view .LVU395
459:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0;
1042 .loc 1 459 38 is_stmt 0 view .LVU396
1043 00ca 4FF40052 mov r2, #8192
1044 00ce 0692 str r2, [sp, #24]
460:Core/Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
1045 .loc 1 460 3 is_stmt 1 view .LVU397
460:Core/Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
1046 .loc 1 460 36 is_stmt 0 view .LVU398
1047 00d0 0793 str r3, [sp, #28]
461:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
1048 .loc 1 461 3 is_stmt 1 view .LVU399
461:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
1049 .loc 1 461 36 is_stmt 0 view .LVU400
1050 00d2 0993 str r3, [sp, #36]
462:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0;
1051 .loc 1 462 3 is_stmt 1 view .LVU401
462:Core/Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0;
1052 .loc 1 462 39 is_stmt 0 view .LVU402
1053 00d4 4FF00072 mov r2, #33554432
1054 00d8 0A92 str r2, [sp, #40]
463:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
1055 .loc 1 463 3 is_stmt 1 view .LVU403
463:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
1056 .loc 1 463 37 is_stmt 0 view .LVU404
1057 00da 0B93 str r3, [sp, #44]
464:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
1058 .loc 1 464 3 is_stmt 1 view .LVU405
464:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
1059 .loc 1 464 40 is_stmt 0 view .LVU406
1060 00dc 0D93 str r3, [sp, #52]
465:Core/Src/main.c **** {
1061 .loc 1 465 3 is_stmt 1 view .LVU407
465:Core/Src/main.c **** {
1062 .loc 1 465 7 is_stmt 0 view .LVU408
1063 00de 01A9 add r1, sp, #4
1064 00e0 0D48 ldr r0, .L55
1065 00e2 FFF7FEFF bl HAL_TIMEx_ConfigBreakDeadTime
1066 .LVL32:
465:Core/Src/main.c **** {
1067 .loc 1 465 6 discriminator 1 view .LVU409
1068 00e6 A0B9 cbnz r0, .L54
472:Core/Src/main.c ****
1069 .loc 1 472 3 is_stmt 1 view .LVU410
1070 00e8 0B48 ldr r0, .L55
1071 00ea FFF7FEFF bl HAL_TIM_MspPostInit
1072 .LVL33:
474:Core/Src/main.c ****
1073 .loc 1 474 1 is_stmt 0 view .LVU411
1074 00ee 1CB0 add sp, sp, #112
1075 .cfi_remember_state
1076 .cfi_def_cfa_offset 8
1077 @ sp needed
1078 00f0 10BD pop {r4, pc}
1079 .L46:
1080 .cfi_restore_state
ARM GAS /tmp/cckN5aRQ.s page 44
413:Core/Src/main.c **** }
1081 .loc 1 413 5 is_stmt 1 view .LVU412
1082 00f2 FFF7FEFF bl Error_Handler
1083 .LVL34:
1084 .L47:
418:Core/Src/main.c **** }
1085 .loc 1 418 5 view .LVU413
1086 00f6 FFF7FEFF bl Error_Handler
1087 .LVL35:
1088 .L48:
422:Core/Src/main.c **** }
1089 .loc 1 422 5 view .LVU414
1090 00fa FFF7FEFF bl Error_Handler
1091 .LVL36:
1092 .L49:
429:Core/Src/main.c **** }
1093 .loc 1 429 5 view .LVU415
1094 00fe FFF7FEFF bl Error_Handler
1095 .LVL37:
1096 .L50:
440:Core/Src/main.c **** }
1097 .loc 1 440 5 view .LVU416
1098 0102 FFF7FEFF bl Error_Handler
1099 .LVL38:
1100 .L51:
444:Core/Src/main.c **** }
1101 .loc 1 444 5 view .LVU417
1102 0106 FFF7FEFF bl Error_Handler
1103 .LVL39:
1104 .L52:
448:Core/Src/main.c **** }
1105 .loc 1 448 5 view .LVU418
1106 010a FFF7FEFF bl Error_Handler
1107 .LVL40:
1108 .L53:
452:Core/Src/main.c **** }
1109 .loc 1 452 5 view .LVU419
1110 010e FFF7FEFF bl Error_Handler
1111 .LVL41:
1112 .L54:
467:Core/Src/main.c **** }
1113 .loc 1 467 5 view .LVU420
1114 0112 FFF7FEFF bl Error_Handler
1115 .LVL42:
1116 .L56:
1117 0116 00BF .align 2
1118 .L55:
1119 0118 00000000 .word htim1
1120 011c 00000140 .word 1073807360
1121 .cfi_endproc
1122 .LFE340:
1124 .section .text.MX_TIM3_Init,"ax",%progbits
1125 .align 1
1126 .syntax unified
1127 .thumb
1128 .thumb_func
1130 MX_TIM3_Init:
ARM GAS /tmp/cckN5aRQ.s page 45
1131 .LFB341:
482:Core/Src/main.c ****
1132 .loc 1 482 1 view -0
1133 .cfi_startproc
1134 @ args = 0, pretend = 0, frame = 40
1135 @ frame_needed = 0, uses_anonymous_args = 0
1136 0000 00B5 push {lr}
1137 .cfi_def_cfa_offset 4
1138 .cfi_offset 14, -4
1139 0002 8BB0 sub sp, sp, #44
1140 .cfi_def_cfa_offset 48
488:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
1141 .loc 1 488 3 view .LVU422
488:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
1142 .loc 1 488 27 is_stmt 0 view .LVU423
1143 0004 0023 movs r3, #0
1144 0006 0793 str r3, [sp, #28]
1145 0008 0893 str r3, [sp, #32]
1146 000a 0993 str r3, [sp, #36]
489:Core/Src/main.c ****
1147 .loc 1 489 3 is_stmt 1 view .LVU424
489:Core/Src/main.c ****
1148 .loc 1 489 22 is_stmt 0 view .LVU425
1149 000c 0093 str r3, [sp]
1150 000e 0193 str r3, [sp, #4]
1151 0010 0293 str r3, [sp, #8]
1152 0012 0393 str r3, [sp, #12]
1153 0014 0493 str r3, [sp, #16]
1154 0016 0593 str r3, [sp, #20]
1155 0018 0693 str r3, [sp, #24]
494:Core/Src/main.c **** htim3.Init.Prescaler = 0;
1156 .loc 1 494 3 is_stmt 1 view .LVU426
494:Core/Src/main.c **** htim3.Init.Prescaler = 0;
1157 .loc 1 494 18 is_stmt 0 view .LVU427
1158 001a 1A48 ldr r0, .L67
1159 001c 1A4A ldr r2, .L67+4
1160 001e 0260 str r2, [r0]
495:Core/Src/main.c **** htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
1161 .loc 1 495 3 is_stmt 1 view .LVU428
495:Core/Src/main.c **** htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
1162 .loc 1 495 24 is_stmt 0 view .LVU429
1163 0020 4360 str r3, [r0, #4]
496:Core/Src/main.c **** htim3.Init.Period = 65535;
1164 .loc 1 496 3 is_stmt 1 view .LVU430
496:Core/Src/main.c **** htim3.Init.Period = 65535;
1165 .loc 1 496 26 is_stmt 0 view .LVU431
1166 0022 8360 str r3, [r0, #8]
497:Core/Src/main.c **** htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1167 .loc 1 497 3 is_stmt 1 view .LVU432
497:Core/Src/main.c **** htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1168 .loc 1 497 21 is_stmt 0 view .LVU433
1169 0024 4FF6FF72 movw r2, #65535
1170 0028 C260 str r2, [r0, #12]
498:Core/Src/main.c **** htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1171 .loc 1 498 3 is_stmt 1 view .LVU434
498:Core/Src/main.c **** htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1172 .loc 1 498 28 is_stmt 0 view .LVU435
ARM GAS /tmp/cckN5aRQ.s page 46
1173 002a 0361 str r3, [r0, #16]
499:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
1174 .loc 1 499 3 is_stmt 1 view .LVU436
499:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
1175 .loc 1 499 32 is_stmt 0 view .LVU437
1176 002c 8361 str r3, [r0, #24]
500:Core/Src/main.c **** {
1177 .loc 1 500 3 is_stmt 1 view .LVU438
500:Core/Src/main.c **** {
1178 .loc 1 500 7 is_stmt 0 view .LVU439
1179 002e FFF7FEFF bl HAL_TIM_PWM_Init
1180 .LVL43:
500:Core/Src/main.c **** {
1181 .loc 1 500 6 discriminator 1 view .LVU440
1182 0032 F8B9 cbnz r0, .L63
504:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1183 .loc 1 504 3 is_stmt 1 view .LVU441
504:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1184 .loc 1 504 37 is_stmt 0 view .LVU442
1185 0034 0023 movs r3, #0
1186 0036 0793 str r3, [sp, #28]
505:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
1187 .loc 1 505 3 is_stmt 1 view .LVU443
505:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
1188 .loc 1 505 33 is_stmt 0 view .LVU444
1189 0038 0993 str r3, [sp, #36]
506:Core/Src/main.c **** {
1190 .loc 1 506 3 is_stmt 1 view .LVU445
506:Core/Src/main.c **** {
1191 .loc 1 506 7 is_stmt 0 view .LVU446
1192 003a 07A9 add r1, sp, #28
1193 003c 1148 ldr r0, .L67
1194 003e FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
1195 .LVL44:
506:Core/Src/main.c **** {
1196 .loc 1 506 6 discriminator 1 view .LVU447
1197 0042 C8B9 cbnz r0, .L64
510:Core/Src/main.c **** sConfigOC.Pulse = 0;
1198 .loc 1 510 3 is_stmt 1 view .LVU448
510:Core/Src/main.c **** sConfigOC.Pulse = 0;
1199 .loc 1 510 20 is_stmt 0 view .LVU449
1200 0044 6023 movs r3, #96
1201 0046 0093 str r3, [sp]
511:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
1202 .loc 1 511 3 is_stmt 1 view .LVU450
511:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
1203 .loc 1 511 19 is_stmt 0 view .LVU451
1204 0048 0023 movs r3, #0
1205 004a 0193 str r3, [sp, #4]
512:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
1206 .loc 1 512 3 is_stmt 1 view .LVU452
512:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
1207 .loc 1 512 24 is_stmt 0 view .LVU453
1208 004c 0293 str r3, [sp, #8]
513:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
1209 .loc 1 513 3 is_stmt 1 view .LVU454
513:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
ARM GAS /tmp/cckN5aRQ.s page 47
1210 .loc 1 513 24 is_stmt 0 view .LVU455
1211 004e 0493 str r3, [sp, #16]
514:Core/Src/main.c **** {
1212 .loc 1 514 3 is_stmt 1 view .LVU456
514:Core/Src/main.c **** {
1213 .loc 1 514 7 is_stmt 0 view .LVU457
1214 0050 0422 movs r2, #4
1215 0052 6946 mov r1, sp
1216 0054 0B48 ldr r0, .L67
1217 0056 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
1218 .LVL45:
514:Core/Src/main.c **** {
1219 .loc 1 514 6 discriminator 1 view .LVU458
1220 005a 78B9 cbnz r0, .L65
518:Core/Src/main.c **** {
1221 .loc 1 518 3 is_stmt 1 view .LVU459
518:Core/Src/main.c **** {
1222 .loc 1 518 7 is_stmt 0 view .LVU460
1223 005c 0C22 movs r2, #12
1224 005e 6946 mov r1, sp
1225 0060 0848 ldr r0, .L67
1226 0062 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
1227 .LVL46:
518:Core/Src/main.c **** {
1228 .loc 1 518 6 discriminator 1 view .LVU461
1229 0066 58B9 cbnz r0, .L66
525:Core/Src/main.c ****
1230 .loc 1 525 3 is_stmt 1 view .LVU462
1231 0068 0648 ldr r0, .L67
1232 006a FFF7FEFF bl HAL_TIM_MspPostInit
1233 .LVL47:
527:Core/Src/main.c ****
1234 .loc 1 527 1 is_stmt 0 view .LVU463
1235 006e 0BB0 add sp, sp, #44
1236 .cfi_remember_state
1237 .cfi_def_cfa_offset 4
1238 @ sp needed
1239 0070 5DF804FB ldr pc, [sp], #4
1240 .L63:
1241 .cfi_restore_state
502:Core/Src/main.c **** }
1242 .loc 1 502 5 is_stmt 1 view .LVU464
1243 0074 FFF7FEFF bl Error_Handler
1244 .LVL48:
1245 .L64:
508:Core/Src/main.c **** }
1246 .loc 1 508 5 view .LVU465
1247 0078 FFF7FEFF bl Error_Handler
1248 .LVL49:
1249 .L65:
516:Core/Src/main.c **** }
1250 .loc 1 516 5 view .LVU466
1251 007c FFF7FEFF bl Error_Handler
1252 .LVL50:
1253 .L66:
520:Core/Src/main.c **** }
1254 .loc 1 520 5 view .LVU467
ARM GAS /tmp/cckN5aRQ.s page 48
1255 0080 FFF7FEFF bl Error_Handler
1256 .LVL51:
1257 .L68:
1258 .align 2
1259 .L67:
1260 0084 00000000 .word htim3
1261 0088 00040040 .word 1073742848
1262 .cfi_endproc
1263 .LFE341:
1265 .section .text.MX_TIM4_Init,"ax",%progbits
1266 .align 1
1267 .syntax unified
1268 .thumb
1269 .thumb_func
1271 MX_TIM4_Init:
1272 .LFB342:
535:Core/Src/main.c ****
1273 .loc 1 535 1 view -0
1274 .cfi_startproc
1275 @ args = 0, pretend = 0, frame = 40
1276 @ frame_needed = 0, uses_anonymous_args = 0
1277 0000 00B5 push {lr}
1278 .cfi_def_cfa_offset 4
1279 .cfi_offset 14, -4
1280 0002 8BB0 sub sp, sp, #44
1281 .cfi_def_cfa_offset 48
541:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
1282 .loc 1 541 3 view .LVU469
541:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
1283 .loc 1 541 27 is_stmt 0 view .LVU470
1284 0004 0023 movs r3, #0
1285 0006 0793 str r3, [sp, #28]
1286 0008 0893 str r3, [sp, #32]
1287 000a 0993 str r3, [sp, #36]
542:Core/Src/main.c ****
1288 .loc 1 542 3 is_stmt 1 view .LVU471
542:Core/Src/main.c ****
1289 .loc 1 542 22 is_stmt 0 view .LVU472
1290 000c 0093 str r3, [sp]
1291 000e 0193 str r3, [sp, #4]
1292 0010 0293 str r3, [sp, #8]
1293 0012 0393 str r3, [sp, #12]
1294 0014 0493 str r3, [sp, #16]
1295 0016 0593 str r3, [sp, #20]
1296 0018 0693 str r3, [sp, #24]
547:Core/Src/main.c **** htim4.Init.Prescaler = 0;
1297 .loc 1 547 3 is_stmt 1 view .LVU473
547:Core/Src/main.c **** htim4.Init.Prescaler = 0;
1298 .loc 1 547 18 is_stmt 0 view .LVU474
1299 001a 1A48 ldr r0, .L79
1300 001c 1A4A ldr r2, .L79+4
1301 001e 0260 str r2, [r0]
548:Core/Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
1302 .loc 1 548 3 is_stmt 1 view .LVU475
548:Core/Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
1303 .loc 1 548 24 is_stmt 0 view .LVU476
1304 0020 4360 str r3, [r0, #4]
ARM GAS /tmp/cckN5aRQ.s page 49
549:Core/Src/main.c **** htim4.Init.Period = 65535;
1305 .loc 1 549 3 is_stmt 1 view .LVU477
549:Core/Src/main.c **** htim4.Init.Period = 65535;
1306 .loc 1 549 26 is_stmt 0 view .LVU478
1307 0022 8360 str r3, [r0, #8]
550:Core/Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1308 .loc 1 550 3 is_stmt 1 view .LVU479
550:Core/Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1309 .loc 1 550 21 is_stmt 0 view .LVU480
1310 0024 4FF6FF72 movw r2, #65535
1311 0028 C260 str r2, [r0, #12]
551:Core/Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1312 .loc 1 551 3 is_stmt 1 view .LVU481
551:Core/Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1313 .loc 1 551 28 is_stmt 0 view .LVU482
1314 002a 0361 str r3, [r0, #16]
552:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
1315 .loc 1 552 3 is_stmt 1 view .LVU483
552:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
1316 .loc 1 552 32 is_stmt 0 view .LVU484
1317 002c 8361 str r3, [r0, #24]
553:Core/Src/main.c **** {
1318 .loc 1 553 3 is_stmt 1 view .LVU485
553:Core/Src/main.c **** {
1319 .loc 1 553 7 is_stmt 0 view .LVU486
1320 002e FFF7FEFF bl HAL_TIM_PWM_Init
1321 .LVL52:
553:Core/Src/main.c **** {
1322 .loc 1 553 6 discriminator 1 view .LVU487
1323 0032 F0B9 cbnz r0, .L75
557:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1324 .loc 1 557 3 is_stmt 1 view .LVU488
557:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1325 .loc 1 557 37 is_stmt 0 view .LVU489
1326 0034 0023 movs r3, #0
1327 0036 0793 str r3, [sp, #28]
558:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
1328 .loc 1 558 3 is_stmt 1 view .LVU490
558:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
1329 .loc 1 558 33 is_stmt 0 view .LVU491
1330 0038 0993 str r3, [sp, #36]
559:Core/Src/main.c **** {
1331 .loc 1 559 3 is_stmt 1 view .LVU492
559:Core/Src/main.c **** {
1332 .loc 1 559 7 is_stmt 0 view .LVU493
1333 003a 07A9 add r1, sp, #28
1334 003c 1148 ldr r0, .L79
1335 003e FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
1336 .LVL53:
559:Core/Src/main.c **** {
1337 .loc 1 559 6 discriminator 1 view .LVU494
1338 0042 C0B9 cbnz r0, .L76
563:Core/Src/main.c **** sConfigOC.Pulse = 0;
1339 .loc 1 563 3 is_stmt 1 view .LVU495
563:Core/Src/main.c **** sConfigOC.Pulse = 0;
1340 .loc 1 563 20 is_stmt 0 view .LVU496
1341 0044 6023 movs r3, #96
ARM GAS /tmp/cckN5aRQ.s page 50
1342 0046 0093 str r3, [sp]
564:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
1343 .loc 1 564 3 is_stmt 1 view .LVU497
564:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
1344 .loc 1 564 19 is_stmt 0 view .LVU498
1345 0048 0022 movs r2, #0
1346 004a 0192 str r2, [sp, #4]
565:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
1347 .loc 1 565 3 is_stmt 1 view .LVU499
565:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
1348 .loc 1 565 24 is_stmt 0 view .LVU500
1349 004c 0292 str r2, [sp, #8]
566:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
1350 .loc 1 566 3 is_stmt 1 view .LVU501
566:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
1351 .loc 1 566 24 is_stmt 0 view .LVU502
1352 004e 0492 str r2, [sp, #16]
567:Core/Src/main.c **** {
1353 .loc 1 567 3 is_stmt 1 view .LVU503
567:Core/Src/main.c **** {
1354 .loc 1 567 7 is_stmt 0 view .LVU504
1355 0050 6946 mov r1, sp
1356 0052 0C48 ldr r0, .L79
1357 0054 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
1358 .LVL54:
567:Core/Src/main.c **** {
1359 .loc 1 567 6 discriminator 1 view .LVU505
1360 0058 78B9 cbnz r0, .L77
571:Core/Src/main.c **** {
1361 .loc 1 571 3 is_stmt 1 view .LVU506
571:Core/Src/main.c **** {
1362 .loc 1 571 7 is_stmt 0 view .LVU507
1363 005a 0422 movs r2, #4
1364 005c 6946 mov r1, sp
1365 005e 0948 ldr r0, .L79
1366 0060 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
1367 .LVL55:
571:Core/Src/main.c **** {
1368 .loc 1 571 6 discriminator 1 view .LVU508
1369 0064 58B9 cbnz r0, .L78
578:Core/Src/main.c ****
1370 .loc 1 578 3 is_stmt 1 view .LVU509
1371 0066 0748 ldr r0, .L79
1372 0068 FFF7FEFF bl HAL_TIM_MspPostInit
1373 .LVL56:
580:Core/Src/main.c ****
1374 .loc 1 580 1 is_stmt 0 view .LVU510
1375 006c 0BB0 add sp, sp, #44
1376 .cfi_remember_state
1377 .cfi_def_cfa_offset 4
1378 @ sp needed
1379 006e 5DF804FB ldr pc, [sp], #4
1380 .L75:
1381 .cfi_restore_state
555:Core/Src/main.c **** }
1382 .loc 1 555 5 is_stmt 1 view .LVU511
1383 0072 FFF7FEFF bl Error_Handler
ARM GAS /tmp/cckN5aRQ.s page 51
1384 .LVL57:
1385 .L76:
561:Core/Src/main.c **** }
1386 .loc 1 561 5 view .LVU512
1387 0076 FFF7FEFF bl Error_Handler
1388 .LVL58:
1389 .L77:
569:Core/Src/main.c **** }
1390 .loc 1 569 5 view .LVU513
1391 007a FFF7FEFF bl Error_Handler
1392 .LVL59:
1393 .L78:
573:Core/Src/main.c **** }
1394 .loc 1 573 5 view .LVU514
1395 007e FFF7FEFF bl Error_Handler
1396 .LVL60:
1397 .L80:
1398 0082 00BF .align 2
1399 .L79:
1400 0084 00000000 .word htim4
1401 0088 00080040 .word 1073743872
1402 .cfi_endproc
1403 .LFE342:
1405 .section .text.MX_TIM8_Init,"ax",%progbits
1406 .align 1
1407 .syntax unified
1408 .thumb
1409 .thumb_func
1411 MX_TIM8_Init:
1412 .LFB344:
626:Core/Src/main.c ****
1413 .loc 1 626 1 view -0
1414 .cfi_startproc
1415 @ args = 0, pretend = 0, frame = 32
1416 @ frame_needed = 0, uses_anonymous_args = 0
1417 0000 00B5 push {lr}
1418 .cfi_def_cfa_offset 4
1419 .cfi_offset 14, -4
1420 0002 89B0 sub sp, sp, #36
1421 .cfi_def_cfa_offset 40
632:Core/Src/main.c **** TIM_IC_InitTypeDef sConfigIC = {0};
1422 .loc 1 632 3 view .LVU516
632:Core/Src/main.c **** TIM_IC_InitTypeDef sConfigIC = {0};
1423 .loc 1 632 27 is_stmt 0 view .LVU517
1424 0004 0023 movs r3, #0
1425 0006 0593 str r3, [sp, #20]
1426 0008 0693 str r3, [sp, #24]
1427 000a 0793 str r3, [sp, #28]
633:Core/Src/main.c ****
1428 .loc 1 633 3 is_stmt 1 view .LVU518
633:Core/Src/main.c ****
1429 .loc 1 633 22 is_stmt 0 view .LVU519
1430 000c 0193 str r3, [sp, #4]
1431 000e 0293 str r3, [sp, #8]
1432 0010 0393 str r3, [sp, #12]
1433 0012 0493 str r3, [sp, #16]
638:Core/Src/main.c **** htim8.Init.Prescaler = 0;
ARM GAS /tmp/cckN5aRQ.s page 52
1434 .loc 1 638 3 is_stmt 1 view .LVU520
638:Core/Src/main.c **** htim8.Init.Prescaler = 0;
1435 .loc 1 638 18 is_stmt 0 view .LVU521
1436 0014 1948 ldr r0, .L91
1437 0016 1A4A ldr r2, .L91+4
1438 0018 0260 str r2, [r0]
639:Core/Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
1439 .loc 1 639 3 is_stmt 1 view .LVU522
639:Core/Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
1440 .loc 1 639 24 is_stmt 0 view .LVU523
1441 001a 4360 str r3, [r0, #4]
640:Core/Src/main.c **** htim8.Init.Period = 65535;
1442 .loc 1 640 3 is_stmt 1 view .LVU524
640:Core/Src/main.c **** htim8.Init.Period = 65535;
1443 .loc 1 640 26 is_stmt 0 view .LVU525
1444 001c 8360 str r3, [r0, #8]
641:Core/Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1445 .loc 1 641 3 is_stmt 1 view .LVU526
641:Core/Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1446 .loc 1 641 21 is_stmt 0 view .LVU527
1447 001e 4FF6FF72 movw r2, #65535
1448 0022 C260 str r2, [r0, #12]
642:Core/Src/main.c **** htim8.Init.RepetitionCounter = 0;
1449 .loc 1 642 3 is_stmt 1 view .LVU528
642:Core/Src/main.c **** htim8.Init.RepetitionCounter = 0;
1450 .loc 1 642 28 is_stmt 0 view .LVU529
1451 0024 0361 str r3, [r0, #16]
643:Core/Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1452 .loc 1 643 3 is_stmt 1 view .LVU530
643:Core/Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1453 .loc 1 643 32 is_stmt 0 view .LVU531
1454 0026 4361 str r3, [r0, #20]
644:Core/Src/main.c **** if (HAL_TIM_IC_Init(&htim8) != HAL_OK)
1455 .loc 1 644 3 is_stmt 1 view .LVU532
644:Core/Src/main.c **** if (HAL_TIM_IC_Init(&htim8) != HAL_OK)
1456 .loc 1 644 32 is_stmt 0 view .LVU533
1457 0028 8361 str r3, [r0, #24]
645:Core/Src/main.c **** {
1458 .loc 1 645 3 is_stmt 1 view .LVU534
645:Core/Src/main.c **** {
1459 .loc 1 645 7 is_stmt 0 view .LVU535
1460 002a FFF7FEFF bl HAL_TIM_IC_Init
1461 .LVL61:
645:Core/Src/main.c **** {
1462 .loc 1 645 6 discriminator 1 view .LVU536
1463 002e E8B9 cbnz r0, .L87
649:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
1464 .loc 1 649 3 is_stmt 1 view .LVU537
649:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
1465 .loc 1 649 37 is_stmt 0 view .LVU538
1466 0030 0023 movs r3, #0
1467 0032 0593 str r3, [sp, #20]
650:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1468 .loc 1 650 3 is_stmt 1 view .LVU539
650:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1469 .loc 1 650 38 is_stmt 0 view .LVU540
1470 0034 0693 str r3, [sp, #24]
ARM GAS /tmp/cckN5aRQ.s page 53
651:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
1471 .loc 1 651 3 is_stmt 1 view .LVU541
651:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
1472 .loc 1 651 33 is_stmt 0 view .LVU542
1473 0036 0793 str r3, [sp, #28]
652:Core/Src/main.c **** {
1474 .loc 1 652 3 is_stmt 1 view .LVU543
652:Core/Src/main.c **** {
1475 .loc 1 652 7 is_stmt 0 view .LVU544
1476 0038 05A9 add r1, sp, #20
1477 003a 1048 ldr r0, .L91
1478 003c FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
1479 .LVL62:
652:Core/Src/main.c **** {
1480 .loc 1 652 6 discriminator 1 view .LVU545
1481 0040 B0B9 cbnz r0, .L88
656:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
1482 .loc 1 656 3 is_stmt 1 view .LVU546
656:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
1483 .loc 1 656 24 is_stmt 0 view .LVU547
1484 0042 0022 movs r2, #0
1485 0044 0192 str r2, [sp, #4]
657:Core/Src/main.c **** sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
1486 .loc 1 657 3 is_stmt 1 view .LVU548
657:Core/Src/main.c **** sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
1487 .loc 1 657 25 is_stmt 0 view .LVU549
1488 0046 0123 movs r3, #1
1489 0048 0293 str r3, [sp, #8]
658:Core/Src/main.c **** sConfigIC.ICFilter = 0;
1490 .loc 1 658 3 is_stmt 1 view .LVU550
658:Core/Src/main.c **** sConfigIC.ICFilter = 0;
1491 .loc 1 658 25 is_stmt 0 view .LVU551
1492 004a 0392 str r2, [sp, #12]
659:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim8, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
1493 .loc 1 659 3 is_stmt 1 view .LVU552
659:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim8, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
1494 .loc 1 659 22 is_stmt 0 view .LVU553
1495 004c 0492 str r2, [sp, #16]
660:Core/Src/main.c **** {
1496 .loc 1 660 3 is_stmt 1 view .LVU554
660:Core/Src/main.c **** {
1497 .loc 1 660 7 is_stmt 0 view .LVU555
1498 004e 01A9 add r1, sp, #4
1499 0050 0A48 ldr r0, .L91
1500 0052 FFF7FEFF bl HAL_TIM_IC_ConfigChannel
1501 .LVL63:
660:Core/Src/main.c **** {
1502 .loc 1 660 6 discriminator 1 view .LVU556
1503 0056 68B9 cbnz r0, .L89
664:Core/Src/main.c **** {
1504 .loc 1 664 3 is_stmt 1 view .LVU557
664:Core/Src/main.c **** {
1505 .loc 1 664 7 is_stmt 0 view .LVU558
1506 0058 0422 movs r2, #4
1507 005a 0DEB0201 add r1, sp, r2
1508 005e 0748 ldr r0, .L91
1509 0060 FFF7FEFF bl HAL_TIM_IC_ConfigChannel
ARM GAS /tmp/cckN5aRQ.s page 54
1510 .LVL64:
664:Core/Src/main.c **** {
1511 .loc 1 664 6 discriminator 1 view .LVU559
1512 0064 40B9 cbnz r0, .L90
672:Core/Src/main.c ****
1513 .loc 1 672 1 view .LVU560
1514 0066 09B0 add sp, sp, #36
1515 .cfi_remember_state
1516 .cfi_def_cfa_offset 4
1517 @ sp needed
1518 0068 5DF804FB ldr pc, [sp], #4
1519 .L87:
1520 .cfi_restore_state
647:Core/Src/main.c **** }
1521 .loc 1 647 5 is_stmt 1 view .LVU561
1522 006c FFF7FEFF bl Error_Handler
1523 .LVL65:
1524 .L88:
654:Core/Src/main.c **** }
1525 .loc 1 654 5 view .LVU562
1526 0070 FFF7FEFF bl Error_Handler
1527 .LVL66:
1528 .L89:
662:Core/Src/main.c **** }
1529 .loc 1 662 5 view .LVU563
1530 0074 FFF7FEFF bl Error_Handler
1531 .LVL67:
1532 .L90:
666:Core/Src/main.c **** }
1533 .loc 1 666 5 view .LVU564
1534 0078 FFF7FEFF bl Error_Handler
1535 .LVL68:
1536 .L92:
1537 .align 2
1538 .L91:
1539 007c 00000000 .word htim8
1540 0080 00040140 .word 1073808384
1541 .cfi_endproc
1542 .LFE344:
1544 .section .text.MX_TIM6_Init,"ax",%progbits
1545 .align 1
1546 .syntax unified
1547 .thumb
1548 .thumb_func
1550 MX_TIM6_Init:
1551 .LFB343:
588:Core/Src/main.c ****
1552 .loc 1 588 1 view -0
1553 .cfi_startproc
1554 @ args = 0, pretend = 0, frame = 16
1555 @ frame_needed = 0, uses_anonymous_args = 0
1556 0000 00B5 push {lr}
1557 .cfi_def_cfa_offset 4
1558 .cfi_offset 14, -4
1559 0002 85B0 sub sp, sp, #20
1560 .cfi_def_cfa_offset 24
594:Core/Src/main.c ****
ARM GAS /tmp/cckN5aRQ.s page 55
1561 .loc 1 594 3 view .LVU566
594:Core/Src/main.c ****
1562 .loc 1 594 27 is_stmt 0 view .LVU567
1563 0004 0023 movs r3, #0
1564 0006 0193 str r3, [sp, #4]
1565 0008 0293 str r3, [sp, #8]
1566 000a 0393 str r3, [sp, #12]
599:Core/Src/main.c **** htim6.Init.Prescaler = 2;
1567 .loc 1 599 3 is_stmt 1 view .LVU568
599:Core/Src/main.c **** htim6.Init.Prescaler = 2;
1568 .loc 1 599 18 is_stmt 0 view .LVU569
1569 000c 0D48 ldr r0, .L99
1570 000e 0E4A ldr r2, .L99+4
1571 0010 0260 str r2, [r0]
600:Core/Src/main.c **** htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
1572 .loc 1 600 3 is_stmt 1 view .LVU570
600:Core/Src/main.c **** htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
1573 .loc 1 600 24 is_stmt 0 view .LVU571
1574 0012 0222 movs r2, #2
1575 0014 4260 str r2, [r0, #4]
601:Core/Src/main.c **** htim6.Init.Period = 48000;
1576 .loc 1 601 3 is_stmt 1 view .LVU572
601:Core/Src/main.c **** htim6.Init.Period = 48000;
1577 .loc 1 601 26 is_stmt 0 view .LVU573
1578 0016 8360 str r3, [r0, #8]
602:Core/Src/main.c **** htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1579 .loc 1 602 3 is_stmt 1 view .LVU574
602:Core/Src/main.c **** htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1580 .loc 1 602 21 is_stmt 0 view .LVU575
1581 0018 4BF68032 movw r2, #48000
1582 001c C260 str r2, [r0, #12]
603:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
1583 .loc 1 603 3 is_stmt 1 view .LVU576
603:Core/Src/main.c **** if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
1584 .loc 1 603 32 is_stmt 0 view .LVU577
1585 001e 8361 str r3, [r0, #24]
604:Core/Src/main.c **** {
1586 .loc 1 604 3 is_stmt 1 view .LVU578
604:Core/Src/main.c **** {
1587 .loc 1 604 7 is_stmt 0 view .LVU579
1588 0020 FFF7FEFF bl HAL_TIM_Base_Init
1589 .LVL69:
604:Core/Src/main.c **** {
1590 .loc 1 604 6 discriminator 1 view .LVU580
1591 0024 50B9 cbnz r0, .L97
608:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1592 .loc 1 608 3 is_stmt 1 view .LVU581
608:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1593 .loc 1 608 37 is_stmt 0 view .LVU582
1594 0026 0023 movs r3, #0
1595 0028 0193 str r3, [sp, #4]
609:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
1596 .loc 1 609 3 is_stmt 1 view .LVU583
609:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
1597 .loc 1 609 33 is_stmt 0 view .LVU584
1598 002a 0393 str r3, [sp, #12]
610:Core/Src/main.c **** {
ARM GAS /tmp/cckN5aRQ.s page 56
1599 .loc 1 610 3 is_stmt 1 view .LVU585
610:Core/Src/main.c **** {
1600 .loc 1 610 7 is_stmt 0 view .LVU586
1601 002c 01A9 add r1, sp, #4
1602 002e 0548 ldr r0, .L99
1603 0030 FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
1604 .LVL70:
610:Core/Src/main.c **** {
1605 .loc 1 610 6 discriminator 1 view .LVU587
1606 0034 20B9 cbnz r0, .L98
618:Core/Src/main.c ****
1607 .loc 1 618 1 view .LVU588
1608 0036 05B0 add sp, sp, #20
1609 .cfi_remember_state
1610 .cfi_def_cfa_offset 4
1611 @ sp needed
1612 0038 5DF804FB ldr pc, [sp], #4
1613 .L97:
1614 .cfi_restore_state
606:Core/Src/main.c **** }
1615 .loc 1 606 5 is_stmt 1 view .LVU589
1616 003c FFF7FEFF bl Error_Handler
1617 .LVL71:
1618 .L98:
612:Core/Src/main.c **** }
1619 .loc 1 612 5 view .LVU590
1620 0040 FFF7FEFF bl Error_Handler
1621 .LVL72:
1622 .L100:
1623 .align 2
1624 .L99:
1625 0044 00000000 .word htim6
1626 0048 00100040 .word 1073745920
1627 .cfi_endproc
1628 .LFE343:
1630 .section .text.SystemClock_Config,"ax",%progbits
1631 .align 1
1632 .global SystemClock_Config
1633 .syntax unified
1634 .thumb
1635 .thumb_func
1637 SystemClock_Config:
1638 .LFB336:
154:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
1639 .loc 1 154 1 view -0
1640 .cfi_startproc
1641 @ args = 0, pretend = 0, frame = 112
1642 @ frame_needed = 0, uses_anonymous_args = 0
1643 0000 00B5 push {lr}
1644 .cfi_def_cfa_offset 4
1645 .cfi_offset 14, -4
1646 0002 9DB0 sub sp, sp, #116
1647 .cfi_def_cfa_offset 120
155:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
1648 .loc 1 155 3 view .LVU592
155:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
1649 .loc 1 155 22 is_stmt 0 view .LVU593
ARM GAS /tmp/cckN5aRQ.s page 57
1650 0004 4C22 movs r2, #76
1651 0006 0021 movs r1, #0
1652 0008 09A8 add r0, sp, #36
1653 000a FFF7FEFF bl memset
1654 .LVL73:
156:Core/Src/main.c ****
1655 .loc 1 156 3 is_stmt 1 view .LVU594
156:Core/Src/main.c ****
1656 .loc 1 156 22 is_stmt 0 view .LVU595
1657 000e 2022 movs r2, #32
1658 0010 0021 movs r1, #0
1659 0012 01A8 add r0, sp, #4
1660 0014 FFF7FEFF bl memset
1661 .LVL74:
159:Core/Src/main.c ****
1662 .loc 1 159 3 is_stmt 1 view .LVU596
159:Core/Src/main.c ****
1663 .loc 1 159 16 is_stmt 0 view .LVU597
1664 0018 254B ldr r3, .L108
1665 001a 4FF0FF32 mov r2, #-1
1666 001e C3F8B020 str r2, [r3, #176]
163:Core/Src/main.c ****
1667 .loc 1 163 3 is_stmt 1 view .LVU598
1668 0022 0220 movs r0, #2
1669 0024 FFF7FEFF bl HAL_PWREx_ConfigSupply
1670 .LVL75:
167:Core/Src/main.c ****
1671 .loc 1 167 3 view .LVU599
1672 .LBB12:
167:Core/Src/main.c ****
1673 .loc 1 167 3 view .LVU600
1674 0028 0023 movs r3, #0
1675 002a 0093 str r3, [sp]
167:Core/Src/main.c ****
1676 .loc 1 167 3 view .LVU601
1677 002c 214A ldr r2, .L108+4
1678 002e 9369 ldr r3, [r2, #24]
1679 0030 23F44043 bic r3, r3, #49152
1680 0034 43F40043 orr r3, r3, #32768
1681 0038 9361 str r3, [r2, #24]
167:Core/Src/main.c ****
1682 .loc 1 167 3 view .LVU602
1683 003a 9369 ldr r3, [r2, #24]
1684 003c 03F44043 and r3, r3, #49152
1685 0040 0093 str r3, [sp]
167:Core/Src/main.c ****
1686 .loc 1 167 3 view .LVU603
1687 0042 009B ldr r3, [sp]
1688 .LBE12:
167:Core/Src/main.c ****
1689 .loc 1 167 3 view .LVU604
169:Core/Src/main.c ****
1690 .loc 1 169 3 view .LVU605
1691 .L102:
169:Core/Src/main.c ****
1692 .loc 1 169 48 discriminator 1 view .LVU606
169:Core/Src/main.c ****
ARM GAS /tmp/cckN5aRQ.s page 58
1693 .loc 1 169 9 discriminator 1 view .LVU607
169:Core/Src/main.c ****
1694 .loc 1 169 10 is_stmt 0 discriminator 1 view .LVU608
1695 0044 1B4B ldr r3, .L108+4
1696 0046 9B69 ldr r3, [r3, #24]
169:Core/Src/main.c ****
1697 .loc 1 169 9 discriminator 1 view .LVU609
1698 0048 13F4005F tst r3, #8192
1699 004c FAD0 beq .L102
174:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
1700 .loc 1 174 3 is_stmt 1 view .LVU610
174:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
1701 .loc 1 174 36 is_stmt 0 view .LVU611
1702 004e 0123 movs r3, #1
1703 0050 0993 str r3, [sp, #36]
175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
1704 .loc 1 175 3 is_stmt 1 view .LVU612
175:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
1705 .loc 1 175 30 is_stmt 0 view .LVU613
1706 0052 4FF48033 mov r3, #65536
1707 0056 0A93 str r3, [sp, #40]
176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
1708 .loc 1 176 3 is_stmt 1 view .LVU614
176:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
1709 .loc 1 176 34 is_stmt 0 view .LVU615
1710 0058 0223 movs r3, #2
1711 005a 1293 str r3, [sp, #72]
177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2;
1712 .loc 1 177 3 is_stmt 1 view .LVU616
177:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 2;
1713 .loc 1 177 35 is_stmt 0 view .LVU617
1714 005c 1393 str r3, [sp, #76]
178:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 32;
1715 .loc 1 178 3 is_stmt 1 view .LVU618
178:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 32;
1716 .loc 1 178 30 is_stmt 0 view .LVU619
1717 005e 1493 str r3, [sp, #80]
179:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2;
1718 .loc 1 179 3 is_stmt 1 view .LVU620
179:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2;
1719 .loc 1 179 30 is_stmt 0 view .LVU621
1720 0060 2022 movs r2, #32
1721 0062 1592 str r2, [sp, #84]
180:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 3;
1722 .loc 1 180 3 is_stmt 1 view .LVU622
180:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 3;
1723 .loc 1 180 30 is_stmt 0 view .LVU623
1724 0064 1693 str r3, [sp, #88]
181:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2;
1725 .loc 1 181 3 is_stmt 1 view .LVU624
181:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2;
1726 .loc 1 181 30 is_stmt 0 view .LVU625
1727 0066 0322 movs r2, #3
1728 0068 1792 str r2, [sp, #92]
182:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
1729 .loc 1 182 3 is_stmt 1 view .LVU626
182:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
ARM GAS /tmp/cckN5aRQ.s page 59
1730 .loc 1 182 30 is_stmt 0 view .LVU627
1731 006a 1893 str r3, [sp, #96]
183:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
1732 .loc 1 183 3 is_stmt 1 view .LVU628
183:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
1733 .loc 1 183 32 is_stmt 0 view .LVU629
1734 006c 0C23 movs r3, #12
1735 006e 1993 str r3, [sp, #100]
184:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0;
1736 .loc 1 184 3 is_stmt 1 view .LVU630
184:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0;
1737 .loc 1 184 35 is_stmt 0 view .LVU631
1738 0070 0023 movs r3, #0
1739 0072 1A93 str r3, [sp, #104]
185:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
1740 .loc 1 185 3 is_stmt 1 view .LVU632
185:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
1741 .loc 1 185 34 is_stmt 0 view .LVU633
1742 0074 1B93 str r3, [sp, #108]
186:Core/Src/main.c **** {
1743 .loc 1 186 3 is_stmt 1 view .LVU634
186:Core/Src/main.c **** {
1744 .loc 1 186 7 is_stmt 0 view .LVU635
1745 0076 09A8 add r0, sp, #36
1746 0078 FFF7FEFF bl HAL_RCC_OscConfig
1747 .LVL76:
186:Core/Src/main.c **** {
1748 .loc 1 186 6 discriminator 1 view .LVU636
1749 007c 98B9 cbnz r0, .L106
193:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
1750 .loc 1 193 3 is_stmt 1 view .LVU637
193:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
1751 .loc 1 193 31 is_stmt 0 view .LVU638
1752 007e 3F23 movs r3, #63
1753 0080 0193 str r3, [sp, #4]
196:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
1754 .loc 1 196 3 is_stmt 1 view .LVU639
196:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
1755 .loc 1 196 34 is_stmt 0 view .LVU640
1756 0082 0323 movs r3, #3
1757 0084 0293 str r3, [sp, #8]
197:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
1758 .loc 1 197 3 is_stmt 1 view .LVU641
197:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
1759 .loc 1 197 35 is_stmt 0 view .LVU642
1760 0086 0023 movs r3, #0
1761 0088 0393 str r3, [sp, #12]
198:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
1762 .loc 1 198 3 is_stmt 1 view .LVU643
198:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
1763 .loc 1 198 35 is_stmt 0 view .LVU644
1764 008a 0822 movs r2, #8
1765 008c 0492 str r2, [sp, #16]
199:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
1766 .loc 1 199 3 is_stmt 1 view .LVU645
199:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
1767 .loc 1 199 36 is_stmt 0 view .LVU646
ARM GAS /tmp/cckN5aRQ.s page 60
1768 008e 0593 str r3, [sp, #20]
200:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
1769 .loc 1 200 3 is_stmt 1 view .LVU647
200:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
1770 .loc 1 200 36 is_stmt 0 view .LVU648
1771 0090 0693 str r3, [sp, #24]
201:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
1772 .loc 1 201 3 is_stmt 1 view .LVU649
201:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
1773 .loc 1 201 36 is_stmt 0 view .LVU650
1774 0092 0793 str r3, [sp, #28]
202:Core/Src/main.c ****
1775 .loc 1 202 3 is_stmt 1 view .LVU651
202:Core/Src/main.c ****
1776 .loc 1 202 36 is_stmt 0 view .LVU652
1777 0094 0893 str r3, [sp, #32]
204:Core/Src/main.c **** {
1778 .loc 1 204 3 is_stmt 1 view .LVU653
204:Core/Src/main.c **** {
1779 .loc 1 204 7 is_stmt 0 view .LVU654
1780 0096 0221 movs r1, #2
1781 0098 01A8 add r0, sp, #4
1782 009a FFF7FEFF bl HAL_RCC_ClockConfig
1783 .LVL77:
204:Core/Src/main.c **** {
1784 .loc 1 204 6 discriminator 1 view .LVU655
1785 009e 20B9 cbnz r0, .L107
208:Core/Src/main.c ****
1786 .loc 1 208 1 view .LVU656
1787 00a0 1DB0 add sp, sp, #116
1788 .cfi_remember_state
1789 .cfi_def_cfa_offset 4
1790 @ sp needed
1791 00a2 5DF804FB ldr pc, [sp], #4
1792 .L106:
1793 .cfi_restore_state
188:Core/Src/main.c **** }
1794 .loc 1 188 5 is_stmt 1 view .LVU657
1795 00a6 FFF7FEFF bl Error_Handler
1796 .LVL78:
1797 .L107:
206:Core/Src/main.c **** }
1798 .loc 1 206 5 view .LVU658
1799 00aa FFF7FEFF bl Error_Handler
1800 .LVL79:
1801 .L109:
1802 00ae 00BF .align 2
1803 .L108:
1804 00b0 00440258 .word 1476543488
1805 00b4 00480258 .word 1476544512
1806 .cfi_endproc
1807 .LFE336:
1809 .section .text.main,"ax",%progbits
1810 .align 1
1811 .global main
1812 .syntax unified
1813 .thumb
ARM GAS /tmp/cckN5aRQ.s page 61
1814 .thumb_func
1816 main:
1817 .LFB335:
86:Core/Src/main.c ****
1818 .loc 1 86 1 view -0
1819 .cfi_startproc
1820 @ Volatile: function does not return.
1821 @ args = 0, pretend = 0, frame = 0
1822 @ frame_needed = 0, uses_anonymous_args = 0
1823 0000 08B5 push {r3, lr}
1824 .cfi_def_cfa_offset 8
1825 .cfi_offset 3, -8
1826 .cfi_offset 14, -4
93:Core/Src/main.c ****
1827 .loc 1 93 3 view .LVU660
1828 0002 FFF7FEFF bl MPU_Config
1829 .LVL80:
98:Core/Src/main.c ****
1830 .loc 1 98 3 view .LVU661
1831 0006 FFF7FEFF bl HAL_Init
1832 .LVL81:
105:Core/Src/main.c ****
1833 .loc 1 105 3 view .LVU662
1834 000a FFF7FEFF bl SystemClock_Config
1835 .LVL82:
112:Core/Src/main.c **** MX_DMA_Init();
1836 .loc 1 112 3 view .LVU663
1837 000e FFF7FEFF bl MX_GPIO_Init
1838 .LVL83:
113:Core/Src/main.c **** MX_ADC1_Init();
1839 .loc 1 113 3 view .LVU664
1840 0012 FFF7FEFF bl MX_DMA_Init
1841 .LVL84:
114:Core/Src/main.c **** MX_FDCAN1_Init();
1842 .loc 1 114 3 view .LVU665
1843 0016 FFF7FEFF bl MX_ADC1_Init
1844 .LVL85:
115:Core/Src/main.c **** MX_FDCAN2_Init();
1845 .loc 1 115 3 view .LVU666
1846 001a FFF7FEFF bl MX_FDCAN1_Init
1847 .LVL86:
116:Core/Src/main.c **** MX_TIM1_Init();
1848 .loc 1 116 3 view .LVU667
1849 001e FFF7FEFF bl MX_FDCAN2_Init
1850 .LVL87:
117:Core/Src/main.c **** MX_TIM3_Init();
1851 .loc 1 117 3 view .LVU668
1852 0022 FFF7FEFF bl MX_TIM1_Init
1853 .LVL88:
118:Core/Src/main.c **** MX_TIM4_Init();
1854 .loc 1 118 3 view .LVU669
1855 0026 FFF7FEFF bl MX_TIM3_Init
1856 .LVL89:
119:Core/Src/main.c **** MX_TIM8_Init();
1857 .loc 1 119 3 view .LVU670
1858 002a FFF7FEFF bl MX_TIM4_Init
1859 .LVL90:
ARM GAS /tmp/cckN5aRQ.s page 62
120:Core/Src/main.c **** MX_TIM6_Init();
1860 .loc 1 120 3 view .LVU671
1861 002e FFF7FEFF bl MX_TIM8_Init
1862 .LVL91:
121:Core/Src/main.c **** /* USER CODE BEGIN 2 */
1863 .loc 1 121 3 view .LVU672
1864 0032 FFF7FEFF bl MX_TIM6_Init
1865 .LVL92:
1866 .L111:
128:Core/Src/main.c **** {
1867 .loc 1 128 3 view .LVU673
133:Core/Src/main.c **** HAL_Delay(500);
1868 .loc 1 133 5 view .LVU674
1869 0036 204C ldr r4, .L113
1870 0038 0122 movs r2, #1
1871 003a 4FF48041 mov r1, #16384
1872 003e 2046 mov r0, r4
1873 0040 FFF7FEFF bl HAL_GPIO_WritePin
1874 .LVL93:
134:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_R_GPIO_Port, STATUS_R_Pin, GPIO_PIN_RESET);
1875 .loc 1 134 5 view .LVU675
1876 0044 4FF4FA70 mov r0, #500
1877 0048 FFF7FEFF bl HAL_Delay
1878 .LVL94:
135:Core/Src/main.c **** HAL_Delay(500);
1879 .loc 1 135 5 view .LVU676
1880 004c 0022 movs r2, #0
1881 004e 4FF48041 mov r1, #16384
1882 0052 2046 mov r0, r4
1883 0054 FFF7FEFF bl HAL_GPIO_WritePin
1884 .LVL95:
136:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_G_GPIO_Port, STATUS_G_Pin, GPIO_PIN_SET);
1885 .loc 1 136 5 view .LVU677
1886 0058 4FF4FA70 mov r0, #500
1887 005c FFF7FEFF bl HAL_Delay
1888 .LVL96:
137:Core/Src/main.c **** HAL_Delay(500);
1889 .loc 1 137 5 view .LVU678
1890 0060 0122 movs r2, #1
1891 0062 4FF40041 mov r1, #32768
1892 0066 2046 mov r0, r4
1893 0068 FFF7FEFF bl HAL_GPIO_WritePin
1894 .LVL97:
138:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_G_GPIO_Port, STATUS_G_Pin, GPIO_PIN_RESET);
1895 .loc 1 138 5 view .LVU679
1896 006c 4FF4FA70 mov r0, #500
1897 0070 FFF7FEFF bl HAL_Delay
1898 .LVL98:
139:Core/Src/main.c **** HAL_Delay(500);
1899 .loc 1 139 5 view .LVU680
1900 0074 0022 movs r2, #0
1901 0076 4FF40041 mov r1, #32768
1902 007a 2046 mov r0, r4
1903 007c FFF7FEFF bl HAL_GPIO_WritePin
1904 .LVL99:
140:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_B_GPIO_Port, STATUS_B_Pin, GPIO_PIN_SET);
1905 .loc 1 140 5 view .LVU681
ARM GAS /tmp/cckN5aRQ.s page 63
1906 0080 4FF4FA70 mov r0, #500
1907 0084 FFF7FEFF bl HAL_Delay
1908 .LVL100:
141:Core/Src/main.c **** HAL_Delay(500);
1909 .loc 1 141 5 view .LVU682
1910 0088 A4F58064 sub r4, r4, #1024
1911 008c 0122 movs r2, #1
1912 008e 4FF48051 mov r1, #4096
1913 0092 2046 mov r0, r4
1914 0094 FFF7FEFF bl HAL_GPIO_WritePin
1915 .LVL101:
142:Core/Src/main.c **** HAL_GPIO_WritePin(STATUS_B_GPIO_Port, STATUS_B_Pin, GPIO_PIN_RESET);
1916 .loc 1 142 5 view .LVU683
1917 0098 4FF4FA70 mov r0, #500
1918 009c FFF7FEFF bl HAL_Delay
1919 .LVL102:
143:Core/Src/main.c **** HAL_Delay(500);
1920 .loc 1 143 5 view .LVU684
1921 00a0 0022 movs r2, #0
1922 00a2 4FF48051 mov r1, #4096
1923 00a6 2046 mov r0, r4
1924 00a8 FFF7FEFF bl HAL_GPIO_WritePin
1925 .LVL103:
144:Core/Src/main.c **** /* USER CODE END 3 */
1926 .loc 1 144 5 discriminator 1 view .LVU685
1927 00ac 4FF4FA70 mov r0, #500
1928 00b0 FFF7FEFF bl HAL_Delay
1929 .LVL104:
128:Core/Src/main.c **** {
1930 .loc 1 128 9 view .LVU686
1931 00b4 BFE7 b .L111
1932 .L114:
1933 00b6 00BF .align 2
1934 .L113:
1935 00b8 00040258 .word 1476527104
1936 .cfi_endproc
1937 .LFE335:
1939 .global htim8
1940 .section .bss.htim8,"aw",%nobits
1941 .align 2
1944 htim8:
1945 0000 00000000 .space 76
1945 00000000
1945 00000000
1945 00000000
1945 00000000
1946 .global htim6
1947 .section .bss.htim6,"aw",%nobits
1948 .align 2
1951 htim6:
1952 0000 00000000 .space 76
1952 00000000
1952 00000000
1952 00000000
1952 00000000
1953 .global htim4
1954 .section .bss.htim4,"aw",%nobits
ARM GAS /tmp/cckN5aRQ.s page 64
1955 .align 2
1958 htim4:
1959 0000 00000000 .space 76
1959 00000000
1959 00000000
1959 00000000
1959 00000000
1960 .global htim3
1961 .section .bss.htim3,"aw",%nobits
1962 .align 2
1965 htim3:
1966 0000 00000000 .space 76
1966 00000000
1966 00000000
1966 00000000
1966 00000000
1967 .global htim1
1968 .section .bss.htim1,"aw",%nobits
1969 .align 2
1972 htim1:
1973 0000 00000000 .space 76
1973 00000000
1973 00000000
1973 00000000
1973 00000000
1974 .global hfdcan2
1975 .section .bss.hfdcan2,"aw",%nobits
1976 .align 2
1979 hfdcan2:
1980 0000 00000000 .space 160
1980 00000000
1980 00000000
1980 00000000
1980 00000000
1981 .global hfdcan1
1982 .section .bss.hfdcan1,"aw",%nobits
1983 .align 2
1986 hfdcan1:
1987 0000 00000000 .space 160
1987 00000000
1987 00000000
1987 00000000
1987 00000000
1988 .global hdma_adc1
1989 .section .bss.hdma_adc1,"aw",%nobits
1990 .align 2
1993 hdma_adc1:
1994 0000 00000000 .space 120
1994 00000000
1994 00000000
1994 00000000
1994 00000000
1995 .global hadc1
1996 .section .bss.hadc1,"aw",%nobits
1997 .align 2
2000 hadc1:
2001 0000 00000000 .space 100
ARM GAS /tmp/cckN5aRQ.s page 65
2001 00000000
2001 00000000
2001 00000000
2001 00000000
2002 .text
2003 .Letext0:
2004 .file 3 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h"
2005 .file 4 "/home/k/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-ea
2006 .file 5 "/home/k/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-ea
2007 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h"
2008 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h"
2009 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h"
2010 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h"
2011 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h"
2012 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h"
2013 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h"
2014 .file 13 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h"
2015 .file 14 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h"
2016 .file 15 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h"
2017 .file 16 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h"
2018 .file 17 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h"
2019 .file 18 "Core/Inc/main.h"
2020 .file 19 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h"
2021 .file 20 "<built-in>"
ARM GAS /tmp/cckN5aRQ.s page 66
DEFINED SYMBOLS
*ABS*:00000000 main.c
/tmp/cckN5aRQ.s:20 .text.MPU_Config:00000000 $t
/tmp/cckN5aRQ.s:25 .text.MPU_Config:00000000 MPU_Config
/tmp/cckN5aRQ.s:101 .text.MX_GPIO_Init:00000000 $t
/tmp/cckN5aRQ.s:106 .text.MX_GPIO_Init:00000000 MX_GPIO_Init
/tmp/cckN5aRQ.s:326 .text.MX_GPIO_Init:00000124 $d
/tmp/cckN5aRQ.s:335 .text.MX_DMA_Init:00000000 $t
/tmp/cckN5aRQ.s:340 .text.MX_DMA_Init:00000000 MX_DMA_Init
/tmp/cckN5aRQ.s:385 .text.MX_DMA_Init:00000034 $d
/tmp/cckN5aRQ.s:390 .text.Error_Handler:00000000 $t
/tmp/cckN5aRQ.s:396 .text.Error_Handler:00000000 Error_Handler
/tmp/cckN5aRQ.s:428 .text.MX_ADC1_Init:00000000 $t
/tmp/cckN5aRQ.s:433 .text.MX_ADC1_Init:00000000 MX_ADC1_Init
/tmp/cckN5aRQ.s:586 .text.MX_ADC1_Init:0000009c $d
/tmp/cckN5aRQ.s:2000 .bss.hadc1:00000000 hadc1
/tmp/cckN5aRQ.s:593 .text.MX_FDCAN1_Init:00000000 $t
/tmp/cckN5aRQ.s:598 .text.MX_FDCAN1_Init:00000000 MX_FDCAN1_Init
/tmp/cckN5aRQ.s:715 .text.MX_FDCAN1_Init:00000058 $d
/tmp/cckN5aRQ.s:1986 .bss.hfdcan1:00000000 hfdcan1
/tmp/cckN5aRQ.s:721 .text.MX_FDCAN2_Init:00000000 $t
/tmp/cckN5aRQ.s:726 .text.MX_FDCAN2_Init:00000000 MX_FDCAN2_Init
/tmp/cckN5aRQ.s:843 .text.MX_FDCAN2_Init:00000058 $d
/tmp/cckN5aRQ.s:1979 .bss.hfdcan2:00000000 hfdcan2
/tmp/cckN5aRQ.s:849 .text.MX_TIM1_Init:00000000 $t
/tmp/cckN5aRQ.s:854 .text.MX_TIM1_Init:00000000 MX_TIM1_Init
/tmp/cckN5aRQ.s:1119 .text.MX_TIM1_Init:00000118 $d
/tmp/cckN5aRQ.s:1972 .bss.htim1:00000000 htim1
/tmp/cckN5aRQ.s:1125 .text.MX_TIM3_Init:00000000 $t
/tmp/cckN5aRQ.s:1130 .text.MX_TIM3_Init:00000000 MX_TIM3_Init
/tmp/cckN5aRQ.s:1260 .text.MX_TIM3_Init:00000084 $d
/tmp/cckN5aRQ.s:1965 .bss.htim3:00000000 htim3
/tmp/cckN5aRQ.s:1266 .text.MX_TIM4_Init:00000000 $t
/tmp/cckN5aRQ.s:1271 .text.MX_TIM4_Init:00000000 MX_TIM4_Init
/tmp/cckN5aRQ.s:1400 .text.MX_TIM4_Init:00000084 $d
/tmp/cckN5aRQ.s:1958 .bss.htim4:00000000 htim4
/tmp/cckN5aRQ.s:1406 .text.MX_TIM8_Init:00000000 $t
/tmp/cckN5aRQ.s:1411 .text.MX_TIM8_Init:00000000 MX_TIM8_Init
/tmp/cckN5aRQ.s:1539 .text.MX_TIM8_Init:0000007c $d
/tmp/cckN5aRQ.s:1944 .bss.htim8:00000000 htim8
/tmp/cckN5aRQ.s:1545 .text.MX_TIM6_Init:00000000 $t
/tmp/cckN5aRQ.s:1550 .text.MX_TIM6_Init:00000000 MX_TIM6_Init
/tmp/cckN5aRQ.s:1625 .text.MX_TIM6_Init:00000044 $d
/tmp/cckN5aRQ.s:1951 .bss.htim6:00000000 htim6
/tmp/cckN5aRQ.s:1631 .text.SystemClock_Config:00000000 $t
/tmp/cckN5aRQ.s:1637 .text.SystemClock_Config:00000000 SystemClock_Config
/tmp/cckN5aRQ.s:1804 .text.SystemClock_Config:000000b0 $d
/tmp/cckN5aRQ.s:1810 .text.main:00000000 $t
/tmp/cckN5aRQ.s:1816 .text.main:00000000 main
/tmp/cckN5aRQ.s:1935 .text.main:000000b8 $d
/tmp/cckN5aRQ.s:1941 .bss.htim8:00000000 $d
/tmp/cckN5aRQ.s:1948 .bss.htim6:00000000 $d
/tmp/cckN5aRQ.s:1955 .bss.htim4:00000000 $d
/tmp/cckN5aRQ.s:1962 .bss.htim3:00000000 $d
/tmp/cckN5aRQ.s:1969 .bss.htim1:00000000 $d
/tmp/cckN5aRQ.s:1976 .bss.hfdcan2:00000000 $d
/tmp/cckN5aRQ.s:1983 .bss.hfdcan1:00000000 $d
ARM GAS /tmp/cckN5aRQ.s page 67
/tmp/cckN5aRQ.s:1993 .bss.hdma_adc1:00000000 hdma_adc1
/tmp/cckN5aRQ.s:1990 .bss.hdma_adc1:00000000 $d
/tmp/cckN5aRQ.s:1997 .bss.hadc1:00000000 $d
UNDEFINED SYMBOLS
HAL_MPU_Disable
HAL_MPU_ConfigRegion
HAL_MPU_Enable
HAL_GPIO_WritePin
HAL_GPIO_Init
HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
HAL_ADC_Init
HAL_ADCEx_MultiModeConfigChannel
HAL_ADC_ConfigChannel
HAL_FDCAN_Init
memset
HAL_TIM_Base_Init
HAL_TIM_ConfigClockSource
HAL_TIM_PWM_Init
HAL_TIMEx_MasterConfigSynchronization
HAL_TIM_PWM_ConfigChannel
HAL_TIMEx_ConfigBreakDeadTime
HAL_TIM_MspPostInit
HAL_TIM_IC_Init
HAL_TIM_IC_ConfigChannel
HAL_PWREx_ConfigSupply
HAL_RCC_OscConfig
HAL_RCC_ClockConfig
HAL_Init
HAL_Delay
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