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sensor-node/Software/build/debug/stm32h7xx_hal_msp.lst

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ARM GAS /tmp/cc2Ol4tL.s page 1
1 .cpu cortex-m7
2 .arch armv7e-m
3 .fpu fpv5-d16
4 .eabi_attribute 28, 1
5 .eabi_attribute 20, 1
6 .eabi_attribute 21, 1
7 .eabi_attribute 23, 3
8 .eabi_attribute 24, 1
9 .eabi_attribute 25, 1
10 .eabi_attribute 26, 1
11 .eabi_attribute 30, 1
12 .eabi_attribute 34, 1
13 .eabi_attribute 18, 4
14 .file "stm32h7xx_hal_msp.c"
15 .text
16 .Ltext0:
17 .cfi_sections .debug_frame
18 .file 1 "Core/Src/stm32h7xx_hal_msp.c"
19 .section .text.HAL_MspInit,"ax",%progbits
20 .align 1
21 .global HAL_MspInit
22 .syntax unified
23 .thumb
24 .thumb_func
26 HAL_MspInit:
27 .LFB335:
1:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32h7xx_hal_msp.c **** /**
3:Core/Src/stm32h7xx_hal_msp.c **** ******************************************************************************
4:Core/Src/stm32h7xx_hal_msp.c **** * @file stm32h7xx_hal_msp.c
5:Core/Src/stm32h7xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization
6:Core/Src/stm32h7xx_hal_msp.c **** * and de-Initialization codes.
7:Core/Src/stm32h7xx_hal_msp.c **** ******************************************************************************
8:Core/Src/stm32h7xx_hal_msp.c **** * @attention
9:Core/Src/stm32h7xx_hal_msp.c **** *
10:Core/Src/stm32h7xx_hal_msp.c **** * Copyright (c) 2025 STMicroelectronics.
11:Core/Src/stm32h7xx_hal_msp.c **** * All rights reserved.
12:Core/Src/stm32h7xx_hal_msp.c **** *
13:Core/Src/stm32h7xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file
14:Core/Src/stm32h7xx_hal_msp.c **** * in the root directory of this software component.
15:Core/Src/stm32h7xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
16:Core/Src/stm32h7xx_hal_msp.c **** *
17:Core/Src/stm32h7xx_hal_msp.c **** ******************************************************************************
18:Core/Src/stm32h7xx_hal_msp.c **** */
19:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Header */
20:Core/Src/stm32h7xx_hal_msp.c ****
21:Core/Src/stm32h7xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/
22:Core/Src/stm32h7xx_hal_msp.c **** #include "main.h"
23:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Includes */
24:Core/Src/stm32h7xx_hal_msp.c ****
25:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Includes */
26:Core/Src/stm32h7xx_hal_msp.c **** extern DMA_HandleTypeDef hdma_adc1;
27:Core/Src/stm32h7xx_hal_msp.c ****
28:Core/Src/stm32h7xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/
29:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TD */
30:Core/Src/stm32h7xx_hal_msp.c ****
31:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TD */
ARM GAS /tmp/cc2Ol4tL.s page 2
32:Core/Src/stm32h7xx_hal_msp.c ****
33:Core/Src/stm32h7xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/
34:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Define */
35:Core/Src/stm32h7xx_hal_msp.c ****
36:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Define */
37:Core/Src/stm32h7xx_hal_msp.c ****
38:Core/Src/stm32h7xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/
39:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN Macro */
40:Core/Src/stm32h7xx_hal_msp.c ****
41:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END Macro */
42:Core/Src/stm32h7xx_hal_msp.c ****
43:Core/Src/stm32h7xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/
44:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN PV */
45:Core/Src/stm32h7xx_hal_msp.c ****
46:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END PV */
47:Core/Src/stm32h7xx_hal_msp.c ****
48:Core/Src/stm32h7xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/
49:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN PFP */
50:Core/Src/stm32h7xx_hal_msp.c ****
51:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END PFP */
52:Core/Src/stm32h7xx_hal_msp.c ****
53:Core/Src/stm32h7xx_hal_msp.c **** /* External functions --------------------------------------------------------*/
54:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */
55:Core/Src/stm32h7xx_hal_msp.c ****
56:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END ExternalFunctions */
57:Core/Src/stm32h7xx_hal_msp.c ****
58:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN 0 */
59:Core/Src/stm32h7xx_hal_msp.c ****
60:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END 0 */
61:Core/Src/stm32h7xx_hal_msp.c ****
62:Core/Src/stm32h7xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
63:Core/Src/stm32h7xx_hal_msp.c **** /**
64:Core/Src/stm32h7xx_hal_msp.c **** * Initializes the Global MSP.
65:Core/Src/stm32h7xx_hal_msp.c **** */
66:Core/Src/stm32h7xx_hal_msp.c **** void HAL_MspInit(void)
67:Core/Src/stm32h7xx_hal_msp.c **** {
28 .loc 1 67 1 view -0
29 .cfi_startproc
30 @ args = 0, pretend = 0, frame = 8
31 @ frame_needed = 0, uses_anonymous_args = 0
32 @ link register save eliminated.
33 0000 82B0 sub sp, sp, #8
34 .cfi_def_cfa_offset 8
68:Core/Src/stm32h7xx_hal_msp.c ****
69:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */
70:Core/Src/stm32h7xx_hal_msp.c ****
71:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END MspInit 0 */
72:Core/Src/stm32h7xx_hal_msp.c ****
73:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE();
35 .loc 1 73 3 view .LVU1
36 .LBB2:
37 .loc 1 73 3 view .LVU2
38 .loc 1 73 3 view .LVU3
39 0002 074B ldr r3, .L3
40 0004 D3F85421 ldr r2, [r3, #340]
41 0008 42F00202 orr r2, r2, #2
42 000c C3F85421 str r2, [r3, #340]
ARM GAS /tmp/cc2Ol4tL.s page 3
43 .loc 1 73 3 view .LVU4
44 0010 D3F85431 ldr r3, [r3, #340]
45 0014 03F00203 and r3, r3, #2
46 0018 0193 str r3, [sp, #4]
47 .loc 1 73 3 view .LVU5
48 001a 019B ldr r3, [sp, #4]
49 .LBE2:
50 .loc 1 73 3 view .LVU6
74:Core/Src/stm32h7xx_hal_msp.c ****
75:Core/Src/stm32h7xx_hal_msp.c **** /* System interrupt init*/
76:Core/Src/stm32h7xx_hal_msp.c ****
77:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */
78:Core/Src/stm32h7xx_hal_msp.c ****
79:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END MspInit 1 */
80:Core/Src/stm32h7xx_hal_msp.c **** }
51 .loc 1 80 1 is_stmt 0 view .LVU7
52 001c 02B0 add sp, sp, #8
53 .cfi_def_cfa_offset 0
54 @ sp needed
55 001e 7047 bx lr
56 .L4:
57 .align 2
58 .L3:
59 0020 00440258 .word 1476543488
60 .cfi_endproc
61 .LFE335:
63 .section .text.HAL_ADC_MspInit,"ax",%progbits
64 .align 1
65 .global HAL_ADC_MspInit
66 .syntax unified
67 .thumb
68 .thumb_func
70 HAL_ADC_MspInit:
71 .LVL0:
72 .LFB336:
81:Core/Src/stm32h7xx_hal_msp.c ****
82:Core/Src/stm32h7xx_hal_msp.c **** /**
83:Core/Src/stm32h7xx_hal_msp.c **** * @brief ADC MSP Initialization
84:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example
85:Core/Src/stm32h7xx_hal_msp.c **** * @param hadc: ADC handle pointer
86:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
87:Core/Src/stm32h7xx_hal_msp.c **** */
88:Core/Src/stm32h7xx_hal_msp.c **** void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
89:Core/Src/stm32h7xx_hal_msp.c **** {
73 .loc 1 89 1 is_stmt 1 view -0
74 .cfi_startproc
75 @ args = 0, pretend = 0, frame = 232
76 @ frame_needed = 0, uses_anonymous_args = 0
77 .loc 1 89 1 is_stmt 0 view .LVU9
78 0000 F0B5 push {r4, r5, r6, r7, lr}
79 .cfi_def_cfa_offset 20
80 .cfi_offset 4, -20
81 .cfi_offset 5, -16
82 .cfi_offset 6, -12
83 .cfi_offset 7, -8
84 .cfi_offset 14, -4
85 0002 BBB0 sub sp, sp, #236
ARM GAS /tmp/cc2Ol4tL.s page 4
86 .cfi_def_cfa_offset 256
87 0004 0446 mov r4, r0
90:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
88 .loc 1 90 3 is_stmt 1 view .LVU10
89 .loc 1 90 20 is_stmt 0 view .LVU11
90 0006 0021 movs r1, #0
91 0008 3591 str r1, [sp, #212]
92 000a 3691 str r1, [sp, #216]
93 000c 3791 str r1, [sp, #220]
94 000e 3891 str r1, [sp, #224]
95 0010 3991 str r1, [sp, #228]
91:Core/Src/stm32h7xx_hal_msp.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
96 .loc 1 91 3 is_stmt 1 view .LVU12
97 .loc 1 91 28 is_stmt 0 view .LVU13
98 0012 C022 movs r2, #192
99 0014 04A8 add r0, sp, #16
100 .LVL1:
101 .loc 1 91 28 view .LVU14
102 0016 FFF7FEFF bl memset
103 .LVL2:
92:Core/Src/stm32h7xx_hal_msp.c **** if(hadc->Instance==ADC1)
104 .loc 1 92 3 is_stmt 1 view .LVU15
105 .loc 1 92 10 is_stmt 0 view .LVU16
106 001a 2268 ldr r2, [r4]
107 .loc 1 92 5 view .LVU17
108 001c 474B ldr r3, .L13
109 001e 9A42 cmp r2, r3
110 0020 01D0 beq .L10
111 .L5:
93:Core/Src/stm32h7xx_hal_msp.c **** {
94:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 0 */
95:Core/Src/stm32h7xx_hal_msp.c ****
96:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 0 */
97:Core/Src/stm32h7xx_hal_msp.c ****
98:Core/Src/stm32h7xx_hal_msp.c **** /** Initializes the peripherals clock
99:Core/Src/stm32h7xx_hal_msp.c **** */
100:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
101:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2M = 2;
102:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2N = 20;
103:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2P = 12;
104:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2Q = 2;
105:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2R = 2;
106:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
107:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
108:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
109:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
110:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
111:Core/Src/stm32h7xx_hal_msp.c **** {
112:Core/Src/stm32h7xx_hal_msp.c **** Error_Handler();
113:Core/Src/stm32h7xx_hal_msp.c **** }
114:Core/Src/stm32h7xx_hal_msp.c ****
115:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
116:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_ADC12_CLK_ENABLE();
117:Core/Src/stm32h7xx_hal_msp.c ****
118:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
119:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
120:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
ARM GAS /tmp/cc2Ol4tL.s page 5
121:Core/Src/stm32h7xx_hal_msp.c **** /**ADC1 GPIO Configuration
122:Core/Src/stm32h7xx_hal_msp.c **** PC0 ------> ADC1_INP10
123:Core/Src/stm32h7xx_hal_msp.c **** PC1 ------> ADC1_INP11
124:Core/Src/stm32h7xx_hal_msp.c **** PC2 ------> ADC1_INP12
125:Core/Src/stm32h7xx_hal_msp.c **** PC3 ------> ADC1_INP13
126:Core/Src/stm32h7xx_hal_msp.c **** PA0 ------> ADC1_INP16
127:Core/Src/stm32h7xx_hal_msp.c **** PA1 ------> ADC1_INP17
128:Core/Src/stm32h7xx_hal_msp.c **** PA2 ------> ADC1_INP14
129:Core/Src/stm32h7xx_hal_msp.c **** PA3 ------> ADC1_INP15
130:Core/Src/stm32h7xx_hal_msp.c **** PA4 ------> ADC1_INP18
131:Core/Src/stm32h7xx_hal_msp.c **** PA5 ------> ADC1_INP19
132:Core/Src/stm32h7xx_hal_msp.c **** PA6 ------> ADC1_INP3
133:Core/Src/stm32h7xx_hal_msp.c **** PA7 ------> ADC1_INP7
134:Core/Src/stm32h7xx_hal_msp.c **** PC4 ------> ADC1_INP4
135:Core/Src/stm32h7xx_hal_msp.c **** PC5 ------> ADC1_INP8
136:Core/Src/stm32h7xx_hal_msp.c **** PB0 ------> ADC1_INP9
137:Core/Src/stm32h7xx_hal_msp.c **** PB1 ------> ADC1_INP5
138:Core/Src/stm32h7xx_hal_msp.c **** */
139:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = A16_Pin|A15_Pin|A14_Pin|A13_Pin
140:Core/Src/stm32h7xx_hal_msp.c **** |A4_Pin|A3_Pin;
141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
142:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
143:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
144:Core/Src/stm32h7xx_hal_msp.c ****
145:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = A12_Pin|A11_Pin|A10_Pin|A9_Pin
146:Core/Src/stm32h7xx_hal_msp.c **** |A8_Pin|A7_Pin|A6_Pin|A5_Pin;
147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
148:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
149:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
150:Core/Src/stm32h7xx_hal_msp.c ****
151:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = A2_Pin|A1_Pin;
152:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
153:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
154:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
155:Core/Src/stm32h7xx_hal_msp.c ****
156:Core/Src/stm32h7xx_hal_msp.c **** /* ADC1 DMA Init */
157:Core/Src/stm32h7xx_hal_msp.c **** /* ADC1 Init */
158:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Instance = DMA1_Stream0;
159:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
160:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
161:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
162:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
163:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
164:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
165:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
166:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM;
167:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
168:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
169:Core/Src/stm32h7xx_hal_msp.c **** {
170:Core/Src/stm32h7xx_hal_msp.c **** Error_Handler();
171:Core/Src/stm32h7xx_hal_msp.c **** }
172:Core/Src/stm32h7xx_hal_msp.c ****
173:Core/Src/stm32h7xx_hal_msp.c **** __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
174:Core/Src/stm32h7xx_hal_msp.c ****
175:Core/Src/stm32h7xx_hal_msp.c **** /* ADC1 interrupt Init */
176:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_SetPriority(ADC_IRQn, 0, 0);
177:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(ADC_IRQn);
ARM GAS /tmp/cc2Ol4tL.s page 6
178:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 1 */
179:Core/Src/stm32h7xx_hal_msp.c ****
180:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END ADC1_MspInit 1 */
181:Core/Src/stm32h7xx_hal_msp.c ****
182:Core/Src/stm32h7xx_hal_msp.c **** }
183:Core/Src/stm32h7xx_hal_msp.c ****
184:Core/Src/stm32h7xx_hal_msp.c **** }
112 .loc 1 184 1 view .LVU18
113 0022 3BB0 add sp, sp, #236
114 .cfi_remember_state
115 .cfi_def_cfa_offset 20
116 @ sp needed
117 0024 F0BD pop {r4, r5, r6, r7, pc}
118 .LVL3:
119 .L10:
120 .cfi_restore_state
100:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2M = 2;
121 .loc 1 100 5 is_stmt 1 view .LVU19
100:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2M = 2;
122 .loc 1 100 46 is_stmt 0 view .LVU20
123 0026 4FF40022 mov r2, #524288
124 002a 0023 movs r3, #0
125 002c CDE90423 strd r2, [sp, #16]
101:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2N = 20;
126 .loc 1 101 5 is_stmt 1 view .LVU21
101:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2N = 20;
127 .loc 1 101 36 is_stmt 0 view .LVU22
128 0030 0223 movs r3, #2
129 0032 0693 str r3, [sp, #24]
102:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2P = 12;
130 .loc 1 102 5 is_stmt 1 view .LVU23
102:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2P = 12;
131 .loc 1 102 36 is_stmt 0 view .LVU24
132 0034 1422 movs r2, #20
133 0036 0792 str r2, [sp, #28]
103:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2Q = 2;
134 .loc 1 103 5 is_stmt 1 view .LVU25
103:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2Q = 2;
135 .loc 1 103 36 is_stmt 0 view .LVU26
136 0038 0C22 movs r2, #12
137 003a 0892 str r2, [sp, #32]
104:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2R = 2;
138 .loc 1 104 5 is_stmt 1 view .LVU27
104:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2R = 2;
139 .loc 1 104 36 is_stmt 0 view .LVU28
140 003c 0993 str r3, [sp, #36]
105:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
141 .loc 1 105 5 is_stmt 1 view .LVU29
105:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
142 .loc 1 105 36 is_stmt 0 view .LVU30
143 003e 0A93 str r3, [sp, #40]
106:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
144 .loc 1 106 5 is_stmt 1 view .LVU31
106:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
145 .loc 1 106 38 is_stmt 0 view .LVU32
146 0040 C023 movs r3, #192
147 0042 0B93 str r3, [sp, #44]
ARM GAS /tmp/cc2Ol4tL.s page 7
107:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
148 .loc 1 107 5 is_stmt 1 view .LVU33
108:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
149 .loc 1 108 5 view .LVU34
109:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
150 .loc 1 109 5 view .LVU35
110:Core/Src/stm32h7xx_hal_msp.c **** {
151 .loc 1 110 5 view .LVU36
110:Core/Src/stm32h7xx_hal_msp.c **** {
152 .loc 1 110 9 is_stmt 0 view .LVU37
153 0044 04A8 add r0, sp, #16
154 0046 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig
155 .LVL4:
110:Core/Src/stm32h7xx_hal_msp.c **** {
156 .loc 1 110 8 discriminator 1 view .LVU38
157 004a 0028 cmp r0, #0
158 004c 70D1 bne .L11
159 .L7:
116:Core/Src/stm32h7xx_hal_msp.c ****
160 .loc 1 116 5 is_stmt 1 view .LVU39
161 .LBB3:
116:Core/Src/stm32h7xx_hal_msp.c ****
162 .loc 1 116 5 view .LVU40
116:Core/Src/stm32h7xx_hal_msp.c ****
163 .loc 1 116 5 view .LVU41
164 004e 3C4B ldr r3, .L13+4
165 0050 D3F83821 ldr r2, [r3, #312]
166 0054 42F02002 orr r2, r2, #32
167 0058 C3F83821 str r2, [r3, #312]
116:Core/Src/stm32h7xx_hal_msp.c ****
168 .loc 1 116 5 view .LVU42
169 005c D3F83821 ldr r2, [r3, #312]
170 0060 02F02002 and r2, r2, #32
171 0064 0092 str r2, [sp]
116:Core/Src/stm32h7xx_hal_msp.c ****
172 .loc 1 116 5 view .LVU43
173 0066 009A ldr r2, [sp]
174 .LBE3:
116:Core/Src/stm32h7xx_hal_msp.c ****
175 .loc 1 116 5 view .LVU44
118:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
176 .loc 1 118 5 view .LVU45
177 .LBB4:
118:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
178 .loc 1 118 5 view .LVU46
118:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
179 .loc 1 118 5 view .LVU47
180 0068 D3F84021 ldr r2, [r3, #320]
181 006c 42F00402 orr r2, r2, #4
182 0070 C3F84021 str r2, [r3, #320]
118:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
183 .loc 1 118 5 view .LVU48
184 0074 D3F84021 ldr r2, [r3, #320]
185 0078 02F00402 and r2, r2, #4
186 007c 0192 str r2, [sp, #4]
118:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
187 .loc 1 118 5 view .LVU49
ARM GAS /tmp/cc2Ol4tL.s page 8
188 007e 019A ldr r2, [sp, #4]
189 .LBE4:
118:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
190 .loc 1 118 5 view .LVU50
119:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
191 .loc 1 119 5 view .LVU51
192 .LBB5:
119:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
193 .loc 1 119 5 view .LVU52
119:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
194 .loc 1 119 5 view .LVU53
195 0080 D3F84021 ldr r2, [r3, #320]
196 0084 42F00102 orr r2, r2, #1
197 0088 C3F84021 str r2, [r3, #320]
119:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
198 .loc 1 119 5 view .LVU54
199 008c D3F84021 ldr r2, [r3, #320]
200 0090 02F00102 and r2, r2, #1
201 0094 0292 str r2, [sp, #8]
119:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
202 .loc 1 119 5 view .LVU55
203 0096 029A ldr r2, [sp, #8]
204 .LBE5:
119:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
205 .loc 1 119 5 view .LVU56
120:Core/Src/stm32h7xx_hal_msp.c **** /**ADC1 GPIO Configuration
206 .loc 1 120 5 view .LVU57
207 .LBB6:
120:Core/Src/stm32h7xx_hal_msp.c **** /**ADC1 GPIO Configuration
208 .loc 1 120 5 view .LVU58
120:Core/Src/stm32h7xx_hal_msp.c **** /**ADC1 GPIO Configuration
209 .loc 1 120 5 view .LVU59
210 0098 D3F84021 ldr r2, [r3, #320]
211 009c 42F00202 orr r2, r2, #2
212 00a0 C3F84021 str r2, [r3, #320]
120:Core/Src/stm32h7xx_hal_msp.c **** /**ADC1 GPIO Configuration
213 .loc 1 120 5 view .LVU60
214 00a4 D3F84031 ldr r3, [r3, #320]
215 00a8 03F00203 and r3, r3, #2
216 00ac 0393 str r3, [sp, #12]
120:Core/Src/stm32h7xx_hal_msp.c **** /**ADC1 GPIO Configuration
217 .loc 1 120 5 view .LVU61
218 00ae 039B ldr r3, [sp, #12]
219 .LBE6:
120:Core/Src/stm32h7xx_hal_msp.c **** /**ADC1 GPIO Configuration
220 .loc 1 120 5 view .LVU62
139:Core/Src/stm32h7xx_hal_msp.c **** |A4_Pin|A3_Pin;
221 .loc 1 139 5 view .LVU63
139:Core/Src/stm32h7xx_hal_msp.c **** |A4_Pin|A3_Pin;
222 .loc 1 139 25 is_stmt 0 view .LVU64
223 00b0 3F23 movs r3, #63
224 00b2 3593 str r3, [sp, #212]
141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
225 .loc 1 141 5 is_stmt 1 view .LVU65
141:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
226 .loc 1 141 26 is_stmt 0 view .LVU66
227 00b4 0326 movs r6, #3
ARM GAS /tmp/cc2Ol4tL.s page 9
228 00b6 3696 str r6, [sp, #216]
142:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
229 .loc 1 142 5 is_stmt 1 view .LVU67
142:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
230 .loc 1 142 26 is_stmt 0 view .LVU68
231 00b8 0025 movs r5, #0
232 00ba 3795 str r5, [sp, #220]
143:Core/Src/stm32h7xx_hal_msp.c ****
233 .loc 1 143 5 is_stmt 1 view .LVU69
234 00bc 35AF add r7, sp, #212
235 00be 3946 mov r1, r7
236 00c0 2048 ldr r0, .L13+8
237 00c2 FFF7FEFF bl HAL_GPIO_Init
238 .LVL5:
145:Core/Src/stm32h7xx_hal_msp.c **** |A8_Pin|A7_Pin|A6_Pin|A5_Pin;
239 .loc 1 145 5 view .LVU70
145:Core/Src/stm32h7xx_hal_msp.c **** |A8_Pin|A7_Pin|A6_Pin|A5_Pin;
240 .loc 1 145 25 is_stmt 0 view .LVU71
241 00c6 FF23 movs r3, #255
242 00c8 3593 str r3, [sp, #212]
147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
243 .loc 1 147 5 is_stmt 1 view .LVU72
147:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
244 .loc 1 147 26 is_stmt 0 view .LVU73
245 00ca 3696 str r6, [sp, #216]
148:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
246 .loc 1 148 5 is_stmt 1 view .LVU74
148:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
247 .loc 1 148 26 is_stmt 0 view .LVU75
248 00cc 3795 str r5, [sp, #220]
149:Core/Src/stm32h7xx_hal_msp.c ****
249 .loc 1 149 5 is_stmt 1 view .LVU76
250 00ce 3946 mov r1, r7
251 00d0 1D48 ldr r0, .L13+12
252 00d2 FFF7FEFF bl HAL_GPIO_Init
253 .LVL6:
151:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
254 .loc 1 151 5 view .LVU77
151:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
255 .loc 1 151 25 is_stmt 0 view .LVU78
256 00d6 3596 str r6, [sp, #212]
152:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
257 .loc 1 152 5 is_stmt 1 view .LVU79
152:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
258 .loc 1 152 26 is_stmt 0 view .LVU80
259 00d8 3696 str r6, [sp, #216]
153:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
260 .loc 1 153 5 is_stmt 1 view .LVU81
153:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
261 .loc 1 153 26 is_stmt 0 view .LVU82
262 00da 3795 str r5, [sp, #220]
154:Core/Src/stm32h7xx_hal_msp.c ****
263 .loc 1 154 5 is_stmt 1 view .LVU83
264 00dc 3946 mov r1, r7
265 00de 1B48 ldr r0, .L13+16
266 00e0 FFF7FEFF bl HAL_GPIO_Init
267 .LVL7:
ARM GAS /tmp/cc2Ol4tL.s page 10
158:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
268 .loc 1 158 5 view .LVU84
158:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
269 .loc 1 158 24 is_stmt 0 view .LVU85
270 00e4 1A48 ldr r0, .L13+20
271 00e6 1B4B ldr r3, .L13+24
272 00e8 0360 str r3, [r0]
159:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
273 .loc 1 159 5 is_stmt 1 view .LVU86
159:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
274 .loc 1 159 28 is_stmt 0 view .LVU87
275 00ea 0923 movs r3, #9
276 00ec 4360 str r3, [r0, #4]
160:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
277 .loc 1 160 5 is_stmt 1 view .LVU88
160:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
278 .loc 1 160 30 is_stmt 0 view .LVU89
279 00ee 8560 str r5, [r0, #8]
161:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
280 .loc 1 161 5 is_stmt 1 view .LVU90
161:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
281 .loc 1 161 30 is_stmt 0 view .LVU91
282 00f0 C560 str r5, [r0, #12]
162:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
283 .loc 1 162 5 is_stmt 1 view .LVU92
162:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
284 .loc 1 162 27 is_stmt 0 view .LVU93
285 00f2 4FF48063 mov r3, #1024
286 00f6 0361 str r3, [r0, #16]
163:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
287 .loc 1 163 5 is_stmt 1 view .LVU94
163:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
288 .loc 1 163 40 is_stmt 0 view .LVU95
289 00f8 4FF40063 mov r3, #2048
290 00fc 4361 str r3, [r0, #20]
164:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
291 .loc 1 164 5 is_stmt 1 view .LVU96
164:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Mode = DMA_CIRCULAR;
292 .loc 1 164 37 is_stmt 0 view .LVU97
293 00fe 4FF40053 mov r3, #8192
294 0102 8361 str r3, [r0, #24]
165:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM;
295 .loc 1 165 5 is_stmt 1 view .LVU98
165:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM;
296 .loc 1 165 25 is_stmt 0 view .LVU99
297 0104 4FF48073 mov r3, #256
298 0108 C361 str r3, [r0, #28]
166:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
299 .loc 1 166 5 is_stmt 1 view .LVU100
166:Core/Src/stm32h7xx_hal_msp.c **** hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
300 .loc 1 166 29 is_stmt 0 view .LVU101
301 010a 4FF48033 mov r3, #65536
302 010e 0362 str r3, [r0, #32]
167:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
303 .loc 1 167 5 is_stmt 1 view .LVU102
167:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
304 .loc 1 167 29 is_stmt 0 view .LVU103
ARM GAS /tmp/cc2Ol4tL.s page 11
305 0110 4562 str r5, [r0, #36]
168:Core/Src/stm32h7xx_hal_msp.c **** {
306 .loc 1 168 5 is_stmt 1 view .LVU104
168:Core/Src/stm32h7xx_hal_msp.c **** {
307 .loc 1 168 9 is_stmt 0 view .LVU105
308 0112 FFF7FEFF bl HAL_DMA_Init
309 .LVL8:
168:Core/Src/stm32h7xx_hal_msp.c **** {
310 .loc 1 168 8 discriminator 1 view .LVU106
311 0116 70B9 cbnz r0, .L12
312 .L8:
173:Core/Src/stm32h7xx_hal_msp.c ****
313 .loc 1 173 5 is_stmt 1 view .LVU107
173:Core/Src/stm32h7xx_hal_msp.c ****
314 .loc 1 173 5 view .LVU108
315 0118 0D4B ldr r3, .L13+20
316 011a E364 str r3, [r4, #76]
173:Core/Src/stm32h7xx_hal_msp.c ****
317 .loc 1 173 5 view .LVU109
318 011c 9C63 str r4, [r3, #56]
173:Core/Src/stm32h7xx_hal_msp.c ****
319 .loc 1 173 5 view .LVU110
176:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_EnableIRQ(ADC_IRQn);
320 .loc 1 176 5 view .LVU111
321 011e 0022 movs r2, #0
322 0120 1146 mov r1, r2
323 0122 1220 movs r0, #18
324 0124 FFF7FEFF bl HAL_NVIC_SetPriority
325 .LVL9:
177:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspInit 1 */
326 .loc 1 177 5 view .LVU112
327 0128 1220 movs r0, #18
328 012a FFF7FEFF bl HAL_NVIC_EnableIRQ
329 .LVL10:
330 .loc 1 184 1 is_stmt 0 view .LVU113
331 012e 78E7 b .L5
332 .L11:
112:Core/Src/stm32h7xx_hal_msp.c **** }
333 .loc 1 112 7 is_stmt 1 view .LVU114
334 0130 FFF7FEFF bl Error_Handler
335 .LVL11:
336 0134 8BE7 b .L7
337 .L12:
170:Core/Src/stm32h7xx_hal_msp.c **** }
338 .loc 1 170 7 view .LVU115
339 0136 FFF7FEFF bl Error_Handler
340 .LVL12:
341 013a EDE7 b .L8
342 .L14:
343 .align 2
344 .L13:
345 013c 00200240 .word 1073881088
346 0140 00440258 .word 1476543488
347 0144 00080258 .word 1476528128
348 0148 00000258 .word 1476526080
349 014c 00040258 .word 1476527104
350 0150 00000000 .word hdma_adc1
ARM GAS /tmp/cc2Ol4tL.s page 12
351 0154 10000240 .word 1073872912
352 .cfi_endproc
353 .LFE336:
355 .section .text.HAL_ADC_MspDeInit,"ax",%progbits
356 .align 1
357 .global HAL_ADC_MspDeInit
358 .syntax unified
359 .thumb
360 .thumb_func
362 HAL_ADC_MspDeInit:
363 .LVL13:
364 .LFB337:
185:Core/Src/stm32h7xx_hal_msp.c ****
186:Core/Src/stm32h7xx_hal_msp.c **** /**
187:Core/Src/stm32h7xx_hal_msp.c **** * @brief ADC MSP De-Initialization
188:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
189:Core/Src/stm32h7xx_hal_msp.c **** * @param hadc: ADC handle pointer
190:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
191:Core/Src/stm32h7xx_hal_msp.c **** */
192:Core/Src/stm32h7xx_hal_msp.c **** void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
193:Core/Src/stm32h7xx_hal_msp.c **** {
365 .loc 1 193 1 view -0
366 .cfi_startproc
367 @ args = 0, pretend = 0, frame = 0
368 @ frame_needed = 0, uses_anonymous_args = 0
194:Core/Src/stm32h7xx_hal_msp.c **** if(hadc->Instance==ADC1)
369 .loc 1 194 3 view .LVU117
370 .loc 1 194 10 is_stmt 0 view .LVU118
371 0000 0268 ldr r2, [r0]
372 .loc 1 194 5 view .LVU119
373 0002 104B ldr r3, .L22
374 0004 9A42 cmp r2, r3
375 0006 00D0 beq .L21
376 0008 7047 bx lr
377 .L21:
193:Core/Src/stm32h7xx_hal_msp.c **** if(hadc->Instance==ADC1)
378 .loc 1 193 1 view .LVU120
379 000a 10B5 push {r4, lr}
380 .cfi_def_cfa_offset 8
381 .cfi_offset 4, -8
382 .cfi_offset 14, -4
383 000c 0446 mov r4, r0
195:Core/Src/stm32h7xx_hal_msp.c **** {
196:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 0 */
197:Core/Src/stm32h7xx_hal_msp.c ****
198:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 0 */
199:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
200:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_ADC12_CLK_DISABLE();
384 .loc 1 200 5 is_stmt 1 view .LVU121
385 000e 0E4A ldr r2, .L22+4
386 0010 D2F83831 ldr r3, [r2, #312]
387 0014 23F02003 bic r3, r3, #32
388 0018 C2F83831 str r3, [r2, #312]
201:Core/Src/stm32h7xx_hal_msp.c ****
202:Core/Src/stm32h7xx_hal_msp.c **** /**ADC1 GPIO Configuration
203:Core/Src/stm32h7xx_hal_msp.c **** PC0 ------> ADC1_INP10
204:Core/Src/stm32h7xx_hal_msp.c **** PC1 ------> ADC1_INP11
ARM GAS /tmp/cc2Ol4tL.s page 13
205:Core/Src/stm32h7xx_hal_msp.c **** PC2 ------> ADC1_INP12
206:Core/Src/stm32h7xx_hal_msp.c **** PC3 ------> ADC1_INP13
207:Core/Src/stm32h7xx_hal_msp.c **** PA0 ------> ADC1_INP16
208:Core/Src/stm32h7xx_hal_msp.c **** PA1 ------> ADC1_INP17
209:Core/Src/stm32h7xx_hal_msp.c **** PA2 ------> ADC1_INP14
210:Core/Src/stm32h7xx_hal_msp.c **** PA3 ------> ADC1_INP15
211:Core/Src/stm32h7xx_hal_msp.c **** PA4 ------> ADC1_INP18
212:Core/Src/stm32h7xx_hal_msp.c **** PA5 ------> ADC1_INP19
213:Core/Src/stm32h7xx_hal_msp.c **** PA6 ------> ADC1_INP3
214:Core/Src/stm32h7xx_hal_msp.c **** PA7 ------> ADC1_INP7
215:Core/Src/stm32h7xx_hal_msp.c **** PC4 ------> ADC1_INP4
216:Core/Src/stm32h7xx_hal_msp.c **** PC5 ------> ADC1_INP8
217:Core/Src/stm32h7xx_hal_msp.c **** PB0 ------> ADC1_INP9
218:Core/Src/stm32h7xx_hal_msp.c **** PB1 ------> ADC1_INP5
219:Core/Src/stm32h7xx_hal_msp.c **** */
220:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOC, A16_Pin|A15_Pin|A14_Pin|A13_Pin
389 .loc 1 220 5 view .LVU122
390 001c 3F21 movs r1, #63
391 001e 0B48 ldr r0, .L22+8
392 .LVL14:
393 .loc 1 220 5 is_stmt 0 view .LVU123
394 0020 FFF7FEFF bl HAL_GPIO_DeInit
395 .LVL15:
221:Core/Src/stm32h7xx_hal_msp.c **** |A4_Pin|A3_Pin);
222:Core/Src/stm32h7xx_hal_msp.c ****
223:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, A12_Pin|A11_Pin|A10_Pin|A9_Pin
396 .loc 1 223 5 is_stmt 1 view .LVU124
397 0024 FF21 movs r1, #255
398 0026 0A48 ldr r0, .L22+12
399 0028 FFF7FEFF bl HAL_GPIO_DeInit
400 .LVL16:
224:Core/Src/stm32h7xx_hal_msp.c **** |A8_Pin|A7_Pin|A6_Pin|A5_Pin);
225:Core/Src/stm32h7xx_hal_msp.c ****
226:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, A2_Pin|A1_Pin);
401 .loc 1 226 5 view .LVU125
402 002c 0321 movs r1, #3
403 002e 0948 ldr r0, .L22+16
404 0030 FFF7FEFF bl HAL_GPIO_DeInit
405 .LVL17:
227:Core/Src/stm32h7xx_hal_msp.c ****
228:Core/Src/stm32h7xx_hal_msp.c **** /* ADC1 DMA DeInit */
229:Core/Src/stm32h7xx_hal_msp.c **** HAL_DMA_DeInit(hadc->DMA_Handle);
406 .loc 1 229 5 view .LVU126
407 0034 E06C ldr r0, [r4, #76]
408 0036 FFF7FEFF bl HAL_DMA_DeInit
409 .LVL18:
230:Core/Src/stm32h7xx_hal_msp.c ****
231:Core/Src/stm32h7xx_hal_msp.c **** /* ADC1 interrupt DeInit */
232:Core/Src/stm32h7xx_hal_msp.c **** HAL_NVIC_DisableIRQ(ADC_IRQn);
410 .loc 1 232 5 view .LVU127
411 003a 1220 movs r0, #18
412 003c FFF7FEFF bl HAL_NVIC_DisableIRQ
413 .LVL19:
233:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN ADC1_MspDeInit 1 */
234:Core/Src/stm32h7xx_hal_msp.c ****
235:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END ADC1_MspDeInit 1 */
236:Core/Src/stm32h7xx_hal_msp.c **** }
ARM GAS /tmp/cc2Ol4tL.s page 14
237:Core/Src/stm32h7xx_hal_msp.c ****
238:Core/Src/stm32h7xx_hal_msp.c **** }
414 .loc 1 238 1 is_stmt 0 view .LVU128
415 0040 10BD pop {r4, pc}
416 .LVL20:
417 .L23:
418 .loc 1 238 1 view .LVU129
419 0042 00BF .align 2
420 .L22:
421 0044 00200240 .word 1073881088
422 0048 00440258 .word 1476543488
423 004c 00080258 .word 1476528128
424 0050 00000258 .word 1476526080
425 0054 00040258 .word 1476527104
426 .cfi_endproc
427 .LFE337:
429 .section .text.HAL_FDCAN_MspInit,"ax",%progbits
430 .align 1
431 .global HAL_FDCAN_MspInit
432 .syntax unified
433 .thumb
434 .thumb_func
436 HAL_FDCAN_MspInit:
437 .LVL21:
438 .LFB338:
239:Core/Src/stm32h7xx_hal_msp.c ****
240:Core/Src/stm32h7xx_hal_msp.c **** static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0;
241:Core/Src/stm32h7xx_hal_msp.c ****
242:Core/Src/stm32h7xx_hal_msp.c **** /**
243:Core/Src/stm32h7xx_hal_msp.c **** * @brief FDCAN MSP Initialization
244:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example
245:Core/Src/stm32h7xx_hal_msp.c **** * @param hfdcan: FDCAN handle pointer
246:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
247:Core/Src/stm32h7xx_hal_msp.c **** */
248:Core/Src/stm32h7xx_hal_msp.c **** void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
249:Core/Src/stm32h7xx_hal_msp.c **** {
439 .loc 1 249 1 is_stmt 1 view -0
440 .cfi_startproc
441 @ args = 0, pretend = 0, frame = 232
442 @ frame_needed = 0, uses_anonymous_args = 0
443 .loc 1 249 1 is_stmt 0 view .LVU131
444 0000 10B5 push {r4, lr}
445 .cfi_def_cfa_offset 8
446 .cfi_offset 4, -8
447 .cfi_offset 14, -4
448 0002 BAB0 sub sp, sp, #232
449 .cfi_def_cfa_offset 240
450 0004 0446 mov r4, r0
250:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
451 .loc 1 250 3 is_stmt 1 view .LVU132
452 .loc 1 250 20 is_stmt 0 view .LVU133
453 0006 0021 movs r1, #0
454 0008 3591 str r1, [sp, #212]
455 000a 3691 str r1, [sp, #216]
456 000c 3791 str r1, [sp, #220]
457 000e 3891 str r1, [sp, #224]
458 0010 3991 str r1, [sp, #228]
ARM GAS /tmp/cc2Ol4tL.s page 15
251:Core/Src/stm32h7xx_hal_msp.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
459 .loc 1 251 3 is_stmt 1 view .LVU134
460 .loc 1 251 28 is_stmt 0 view .LVU135
461 0012 C022 movs r2, #192
462 0014 04A8 add r0, sp, #16
463 .LVL22:
464 .loc 1 251 28 view .LVU136
465 0016 FFF7FEFF bl memset
466 .LVL23:
252:Core/Src/stm32h7xx_hal_msp.c **** if(hfdcan->Instance==FDCAN1)
467 .loc 1 252 3 is_stmt 1 view .LVU137
468 .loc 1 252 12 is_stmt 0 view .LVU138
469 001a 2368 ldr r3, [r4]
470 .loc 1 252 5 view .LVU139
471 001c 3F4A ldr r2, .L38
472 001e 9342 cmp r3, r2
473 0020 04D0 beq .L32
253:Core/Src/stm32h7xx_hal_msp.c **** {
254:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN FDCAN1_MspInit 0 */
255:Core/Src/stm32h7xx_hal_msp.c ****
256:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END FDCAN1_MspInit 0 */
257:Core/Src/stm32h7xx_hal_msp.c ****
258:Core/Src/stm32h7xx_hal_msp.c **** /** Initializes the peripherals clock
259:Core/Src/stm32h7xx_hal_msp.c **** */
260:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
261:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
262:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
263:Core/Src/stm32h7xx_hal_msp.c **** {
264:Core/Src/stm32h7xx_hal_msp.c **** Error_Handler();
265:Core/Src/stm32h7xx_hal_msp.c **** }
266:Core/Src/stm32h7xx_hal_msp.c ****
267:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
268:Core/Src/stm32h7xx_hal_msp.c **** HAL_RCC_FDCAN_CLK_ENABLED++;
269:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==1){
270:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_ENABLE();
271:Core/Src/stm32h7xx_hal_msp.c **** }
272:Core/Src/stm32h7xx_hal_msp.c ****
273:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
274:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN1 GPIO Configuration
275:Core/Src/stm32h7xx_hal_msp.c **** PB8 ------> FDCAN1_RX
276:Core/Src/stm32h7xx_hal_msp.c **** PB9 ------> FDCAN1_TX
277:Core/Src/stm32h7xx_hal_msp.c **** */
278:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
279:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
280:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
281:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
282:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
283:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
284:Core/Src/stm32h7xx_hal_msp.c ****
285:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN FDCAN1_MspInit 1 */
286:Core/Src/stm32h7xx_hal_msp.c ****
287:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END FDCAN1_MspInit 1 */
288:Core/Src/stm32h7xx_hal_msp.c **** }
289:Core/Src/stm32h7xx_hal_msp.c **** else if(hfdcan->Instance==FDCAN2)
474 .loc 1 289 8 is_stmt 1 view .LVU140
475 .loc 1 289 10 is_stmt 0 view .LVU141
476 0022 3F4A ldr r2, .L38+4
ARM GAS /tmp/cc2Ol4tL.s page 16
477 0024 9342 cmp r3, r2
478 0026 3DD0 beq .L33
479 .L24:
290:Core/Src/stm32h7xx_hal_msp.c **** {
291:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN FDCAN2_MspInit 0 */
292:Core/Src/stm32h7xx_hal_msp.c ****
293:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END FDCAN2_MspInit 0 */
294:Core/Src/stm32h7xx_hal_msp.c ****
295:Core/Src/stm32h7xx_hal_msp.c **** /** Initializes the peripherals clock
296:Core/Src/stm32h7xx_hal_msp.c **** */
297:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
298:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
299:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
300:Core/Src/stm32h7xx_hal_msp.c **** {
301:Core/Src/stm32h7xx_hal_msp.c **** Error_Handler();
302:Core/Src/stm32h7xx_hal_msp.c **** }
303:Core/Src/stm32h7xx_hal_msp.c ****
304:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
305:Core/Src/stm32h7xx_hal_msp.c **** HAL_RCC_FDCAN_CLK_ENABLED++;
306:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==1){
307:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_ENABLE();
308:Core/Src/stm32h7xx_hal_msp.c **** }
309:Core/Src/stm32h7xx_hal_msp.c ****
310:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
311:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN2 GPIO Configuration
312:Core/Src/stm32h7xx_hal_msp.c **** PB12 ------> FDCAN2_RX
313:Core/Src/stm32h7xx_hal_msp.c **** PB13 ------> FDCAN2_TX
314:Core/Src/stm32h7xx_hal_msp.c **** */
315:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
316:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
317:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
318:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
319:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
320:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
321:Core/Src/stm32h7xx_hal_msp.c ****
322:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN FDCAN2_MspInit 1 */
323:Core/Src/stm32h7xx_hal_msp.c ****
324:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END FDCAN2_MspInit 1 */
325:Core/Src/stm32h7xx_hal_msp.c **** }
326:Core/Src/stm32h7xx_hal_msp.c ****
327:Core/Src/stm32h7xx_hal_msp.c **** }
480 .loc 1 327 1 view .LVU142
481 0028 3AB0 add sp, sp, #232
482 .cfi_remember_state
483 .cfi_def_cfa_offset 8
484 @ sp needed
485 002a 10BD pop {r4, pc}
486 .LVL24:
487 .L32:
488 .cfi_restore_state
260:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
489 .loc 1 260 5 is_stmt 1 view .LVU143
260:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
490 .loc 1 260 46 is_stmt 0 view .LVU144
491 002c 4FF40042 mov r2, #32768
492 0030 0023 movs r3, #0
493 0032 CDE90423 strd r2, [sp, #16]
ARM GAS /tmp/cc2Ol4tL.s page 17
261:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
494 .loc 1 261 5 is_stmt 1 view .LVU145
262:Core/Src/stm32h7xx_hal_msp.c **** {
495 .loc 1 262 5 view .LVU146
262:Core/Src/stm32h7xx_hal_msp.c **** {
496 .loc 1 262 9 is_stmt 0 view .LVU147
497 0036 04A8 add r0, sp, #16
498 0038 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig
499 .LVL25:
262:Core/Src/stm32h7xx_hal_msp.c **** {
500 .loc 1 262 8 discriminator 1 view .LVU148
501 003c 08BB cbnz r0, .L34
502 .L26:
268:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==1){
503 .loc 1 268 5 is_stmt 1 view .LVU149
268:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==1){
504 .loc 1 268 30 is_stmt 0 view .LVU150
505 003e 394A ldr r2, .L38+8
506 0040 1368 ldr r3, [r2]
507 0042 0133 adds r3, r3, #1
508 0044 1360 str r3, [r2]
269:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_ENABLE();
509 .loc 1 269 5 is_stmt 1 view .LVU151
269:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_ENABLE();
510 .loc 1 269 7 is_stmt 0 view .LVU152
511 0046 012B cmp r3, #1
512 0048 1ED0 beq .L35
513 .L27:
270:Core/Src/stm32h7xx_hal_msp.c **** }
514 .loc 1 270 7 is_stmt 1 discriminator 1 view .LVU153
273:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN1 GPIO Configuration
515 .loc 1 273 5 view .LVU154
516 .LBB7:
273:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN1 GPIO Configuration
517 .loc 1 273 5 view .LVU155
273:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN1 GPIO Configuration
518 .loc 1 273 5 view .LVU156
519 004a 374B ldr r3, .L38+12
520 004c D3F84021 ldr r2, [r3, #320]
521 0050 42F00202 orr r2, r2, #2
522 0054 C3F84021 str r2, [r3, #320]
273:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN1 GPIO Configuration
523 .loc 1 273 5 view .LVU157
524 0058 D3F84031 ldr r3, [r3, #320]
525 005c 03F00203 and r3, r3, #2
526 0060 0193 str r3, [sp, #4]
273:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN1 GPIO Configuration
527 .loc 1 273 5 view .LVU158
528 0062 019B ldr r3, [sp, #4]
529 .LBE7:
273:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN1 GPIO Configuration
530 .loc 1 273 5 view .LVU159
278:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
531 .loc 1 278 5 view .LVU160
278:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
532 .loc 1 278 25 is_stmt 0 view .LVU161
533 0064 4FF44073 mov r3, #768
ARM GAS /tmp/cc2Ol4tL.s page 18
534 0068 3593 str r3, [sp, #212]
279:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
535 .loc 1 279 5 is_stmt 1 view .LVU162
279:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
536 .loc 1 279 26 is_stmt 0 view .LVU163
537 006a 0223 movs r3, #2
538 006c 3693 str r3, [sp, #216]
280:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
539 .loc 1 280 5 is_stmt 1 view .LVU164
280:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
540 .loc 1 280 26 is_stmt 0 view .LVU165
541 006e 0023 movs r3, #0
542 0070 3793 str r3, [sp, #220]
281:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
543 .loc 1 281 5 is_stmt 1 view .LVU166
281:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
544 .loc 1 281 27 is_stmt 0 view .LVU167
545 0072 3893 str r3, [sp, #224]
282:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
546 .loc 1 282 5 is_stmt 1 view .LVU168
282:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
547 .loc 1 282 31 is_stmt 0 view .LVU169
548 0074 0923 movs r3, #9
549 0076 3993 str r3, [sp, #228]
283:Core/Src/stm32h7xx_hal_msp.c ****
550 .loc 1 283 5 is_stmt 1 view .LVU170
551 0078 35A9 add r1, sp, #212
552 007a 2C48 ldr r0, .L38+16
553 007c FFF7FEFF bl HAL_GPIO_Init
554 .LVL26:
555 0080 D2E7 b .L24
556 .L34:
264:Core/Src/stm32h7xx_hal_msp.c **** }
557 .loc 1 264 7 view .LVU171
558 0082 FFF7FEFF bl Error_Handler
559 .LVL27:
560 0086 DAE7 b .L26
561 .L35:
270:Core/Src/stm32h7xx_hal_msp.c **** }
562 .loc 1 270 7 view .LVU172
563 .LBB8:
270:Core/Src/stm32h7xx_hal_msp.c **** }
564 .loc 1 270 7 view .LVU173
270:Core/Src/stm32h7xx_hal_msp.c **** }
565 .loc 1 270 7 view .LVU174
566 0088 274B ldr r3, .L38+12
567 008a D3F84C21 ldr r2, [r3, #332]
568 008e 42F48072 orr r2, r2, #256
569 0092 C3F84C21 str r2, [r3, #332]
270:Core/Src/stm32h7xx_hal_msp.c **** }
570 .loc 1 270 7 view .LVU175
571 0096 D3F84C31 ldr r3, [r3, #332]
572 009a 03F48073 and r3, r3, #256
573 009e 0093 str r3, [sp]
270:Core/Src/stm32h7xx_hal_msp.c **** }
574 .loc 1 270 7 view .LVU176
575 00a0 009B ldr r3, [sp]
ARM GAS /tmp/cc2Ol4tL.s page 19
576 00a2 D2E7 b .L27
577 .L33:
578 .LBE8:
297:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
579 .loc 1 297 5 view .LVU177
297:Core/Src/stm32h7xx_hal_msp.c **** PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_HSE;
580 .loc 1 297 46 is_stmt 0 view .LVU178
581 00a4 4FF40042 mov r2, #32768
582 00a8 0023 movs r3, #0
583 00aa CDE90423 strd r2, [sp, #16]
298:Core/Src/stm32h7xx_hal_msp.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
584 .loc 1 298 5 is_stmt 1 view .LVU179
299:Core/Src/stm32h7xx_hal_msp.c **** {
585 .loc 1 299 5 view .LVU180
299:Core/Src/stm32h7xx_hal_msp.c **** {
586 .loc 1 299 9 is_stmt 0 view .LVU181
587 00ae 04A8 add r0, sp, #16
588 00b0 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig
589 .LVL28:
299:Core/Src/stm32h7xx_hal_msp.c **** {
590 .loc 1 299 8 discriminator 1 view .LVU182
591 00b4 08BB cbnz r0, .L36
592 .L29:
305:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==1){
593 .loc 1 305 5 is_stmt 1 view .LVU183
305:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==1){
594 .loc 1 305 30 is_stmt 0 view .LVU184
595 00b6 1B4A ldr r2, .L38+8
596 00b8 1368 ldr r3, [r2]
597 00ba 0133 adds r3, r3, #1
598 00bc 1360 str r3, [r2]
306:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_ENABLE();
599 .loc 1 306 5 is_stmt 1 view .LVU185
306:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_ENABLE();
600 .loc 1 306 7 is_stmt 0 view .LVU186
601 00be 012B cmp r3, #1
602 00c0 1ED0 beq .L37
603 .L30:
307:Core/Src/stm32h7xx_hal_msp.c **** }
604 .loc 1 307 7 is_stmt 1 discriminator 1 view .LVU187
310:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN2 GPIO Configuration
605 .loc 1 310 5 view .LVU188
606 .LBB9:
310:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN2 GPIO Configuration
607 .loc 1 310 5 view .LVU189
310:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN2 GPIO Configuration
608 .loc 1 310 5 view .LVU190
609 00c2 194B ldr r3, .L38+12
610 00c4 D3F84021 ldr r2, [r3, #320]
611 00c8 42F00202 orr r2, r2, #2
612 00cc C3F84021 str r2, [r3, #320]
310:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN2 GPIO Configuration
613 .loc 1 310 5 view .LVU191
614 00d0 D3F84031 ldr r3, [r3, #320]
615 00d4 03F00203 and r3, r3, #2
616 00d8 0393 str r3, [sp, #12]
310:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN2 GPIO Configuration
ARM GAS /tmp/cc2Ol4tL.s page 20
617 .loc 1 310 5 view .LVU192
618 00da 039B ldr r3, [sp, #12]
619 .LBE9:
310:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN2 GPIO Configuration
620 .loc 1 310 5 view .LVU193
315:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
621 .loc 1 315 5 view .LVU194
315:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
622 .loc 1 315 25 is_stmt 0 view .LVU195
623 00dc 4FF44053 mov r3, #12288
624 00e0 3593 str r3, [sp, #212]
316:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
625 .loc 1 316 5 is_stmt 1 view .LVU196
316:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
626 .loc 1 316 26 is_stmt 0 view .LVU197
627 00e2 0223 movs r3, #2
628 00e4 3693 str r3, [sp, #216]
317:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
629 .loc 1 317 5 is_stmt 1 view .LVU198
317:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
630 .loc 1 317 26 is_stmt 0 view .LVU199
631 00e6 0023 movs r3, #0
632 00e8 3793 str r3, [sp, #220]
318:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
633 .loc 1 318 5 is_stmt 1 view .LVU200
318:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
634 .loc 1 318 27 is_stmt 0 view .LVU201
635 00ea 3893 str r3, [sp, #224]
319:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
636 .loc 1 319 5 is_stmt 1 view .LVU202
319:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
637 .loc 1 319 31 is_stmt 0 view .LVU203
638 00ec 0923 movs r3, #9
639 00ee 3993 str r3, [sp, #228]
320:Core/Src/stm32h7xx_hal_msp.c ****
640 .loc 1 320 5 is_stmt 1 view .LVU204
641 00f0 35A9 add r1, sp, #212
642 00f2 0E48 ldr r0, .L38+16
643 00f4 FFF7FEFF bl HAL_GPIO_Init
644 .LVL29:
645 .loc 1 327 1 is_stmt 0 view .LVU205
646 00f8 96E7 b .L24
647 .L36:
301:Core/Src/stm32h7xx_hal_msp.c **** }
648 .loc 1 301 7 is_stmt 1 view .LVU206
649 00fa FFF7FEFF bl Error_Handler
650 .LVL30:
651 00fe DAE7 b .L29
652 .L37:
307:Core/Src/stm32h7xx_hal_msp.c **** }
653 .loc 1 307 7 view .LVU207
654 .LBB10:
307:Core/Src/stm32h7xx_hal_msp.c **** }
655 .loc 1 307 7 view .LVU208
307:Core/Src/stm32h7xx_hal_msp.c **** }
656 .loc 1 307 7 view .LVU209
657 0100 094B ldr r3, .L38+12
ARM GAS /tmp/cc2Ol4tL.s page 21
658 0102 D3F84C21 ldr r2, [r3, #332]
659 0106 42F48072 orr r2, r2, #256
660 010a C3F84C21 str r2, [r3, #332]
307:Core/Src/stm32h7xx_hal_msp.c **** }
661 .loc 1 307 7 view .LVU210
662 010e D3F84C31 ldr r3, [r3, #332]
663 0112 03F48073 and r3, r3, #256
664 0116 0293 str r3, [sp, #8]
307:Core/Src/stm32h7xx_hal_msp.c **** }
665 .loc 1 307 7 view .LVU211
666 0118 029B ldr r3, [sp, #8]
667 011a D2E7 b .L30
668 .L39:
669 .align 2
670 .L38:
671 011c 00A00040 .word 1073782784
672 0120 00A40040 .word 1073783808
673 0124 00000000 .word HAL_RCC_FDCAN_CLK_ENABLED
674 0128 00440258 .word 1476543488
675 012c 00040258 .word 1476527104
676 .LBE10:
677 .cfi_endproc
678 .LFE338:
680 .section .text.HAL_FDCAN_MspDeInit,"ax",%progbits
681 .align 1
682 .global HAL_FDCAN_MspDeInit
683 .syntax unified
684 .thumb
685 .thumb_func
687 HAL_FDCAN_MspDeInit:
688 .LVL31:
689 .LFB339:
328:Core/Src/stm32h7xx_hal_msp.c ****
329:Core/Src/stm32h7xx_hal_msp.c **** /**
330:Core/Src/stm32h7xx_hal_msp.c **** * @brief FDCAN MSP De-Initialization
331:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
332:Core/Src/stm32h7xx_hal_msp.c **** * @param hfdcan: FDCAN handle pointer
333:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
334:Core/Src/stm32h7xx_hal_msp.c **** */
335:Core/Src/stm32h7xx_hal_msp.c **** void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
336:Core/Src/stm32h7xx_hal_msp.c **** {
690 .loc 1 336 1 view -0
691 .cfi_startproc
692 @ args = 0, pretend = 0, frame = 0
693 @ frame_needed = 0, uses_anonymous_args = 0
694 .loc 1 336 1 is_stmt 0 view .LVU213
695 0000 08B5 push {r3, lr}
696 .cfi_def_cfa_offset 8
697 .cfi_offset 3, -8
698 .cfi_offset 14, -4
337:Core/Src/stm32h7xx_hal_msp.c **** if(hfdcan->Instance==FDCAN1)
699 .loc 1 337 3 is_stmt 1 view .LVU214
700 .loc 1 337 12 is_stmt 0 view .LVU215
701 0002 0368 ldr r3, [r0]
702 .loc 1 337 5 view .LVU216
703 0004 154A ldr r2, .L48
704 0006 9342 cmp r3, r2
ARM GAS /tmp/cc2Ol4tL.s page 22
705 0008 03D0 beq .L46
338:Core/Src/stm32h7xx_hal_msp.c **** {
339:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN FDCAN1_MspDeInit 0 */
340:Core/Src/stm32h7xx_hal_msp.c ****
341:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END FDCAN1_MspDeInit 0 */
342:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
343:Core/Src/stm32h7xx_hal_msp.c **** HAL_RCC_FDCAN_CLK_ENABLED--;
344:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==0){
345:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_DISABLE();
346:Core/Src/stm32h7xx_hal_msp.c **** }
347:Core/Src/stm32h7xx_hal_msp.c ****
348:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN1 GPIO Configuration
349:Core/Src/stm32h7xx_hal_msp.c **** PB8 ------> FDCAN1_RX
350:Core/Src/stm32h7xx_hal_msp.c **** PB9 ------> FDCAN1_TX
351:Core/Src/stm32h7xx_hal_msp.c **** */
352:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
353:Core/Src/stm32h7xx_hal_msp.c ****
354:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN FDCAN1_MspDeInit 1 */
355:Core/Src/stm32h7xx_hal_msp.c ****
356:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END FDCAN1_MspDeInit 1 */
357:Core/Src/stm32h7xx_hal_msp.c **** }
358:Core/Src/stm32h7xx_hal_msp.c **** else if(hfdcan->Instance==FDCAN2)
706 .loc 1 358 8 is_stmt 1 view .LVU217
707 .loc 1 358 10 is_stmt 0 view .LVU218
708 000a 154A ldr r2, .L48+4
709 000c 9342 cmp r3, r2
710 000e 12D0 beq .L47
711 .LVL32:
712 .L40:
359:Core/Src/stm32h7xx_hal_msp.c **** {
360:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN FDCAN2_MspDeInit 0 */
361:Core/Src/stm32h7xx_hal_msp.c ****
362:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END FDCAN2_MspDeInit 0 */
363:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
364:Core/Src/stm32h7xx_hal_msp.c **** HAL_RCC_FDCAN_CLK_ENABLED--;
365:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==0){
366:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_DISABLE();
367:Core/Src/stm32h7xx_hal_msp.c **** }
368:Core/Src/stm32h7xx_hal_msp.c ****
369:Core/Src/stm32h7xx_hal_msp.c **** /**FDCAN2 GPIO Configuration
370:Core/Src/stm32h7xx_hal_msp.c **** PB12 ------> FDCAN2_RX
371:Core/Src/stm32h7xx_hal_msp.c **** PB13 ------> FDCAN2_TX
372:Core/Src/stm32h7xx_hal_msp.c **** */
373:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13);
374:Core/Src/stm32h7xx_hal_msp.c ****
375:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN FDCAN2_MspDeInit 1 */
376:Core/Src/stm32h7xx_hal_msp.c ****
377:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END FDCAN2_MspDeInit 1 */
378:Core/Src/stm32h7xx_hal_msp.c **** }
379:Core/Src/stm32h7xx_hal_msp.c ****
380:Core/Src/stm32h7xx_hal_msp.c **** }
713 .loc 1 380 1 view .LVU219
714 0010 08BD pop {r3, pc}
715 .LVL33:
716 .L46:
343:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==0){
717 .loc 1 343 5 is_stmt 1 view .LVU220
ARM GAS /tmp/cc2Ol4tL.s page 23
343:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==0){
718 .loc 1 343 30 is_stmt 0 view .LVU221
719 0012 144A ldr r2, .L48+8
720 0014 1368 ldr r3, [r2]
721 0016 013B subs r3, r3, #1
722 0018 1360 str r3, [r2]
344:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_DISABLE();
723 .loc 1 344 5 is_stmt 1 view .LVU222
344:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_DISABLE();
724 .loc 1 344 7 is_stmt 0 view .LVU223
725 001a 33B9 cbnz r3, .L42
345:Core/Src/stm32h7xx_hal_msp.c **** }
726 .loc 1 345 7 is_stmt 1 view .LVU224
727 001c 124A ldr r2, .L48+12
728 001e D2F84C31 ldr r3, [r2, #332]
729 0022 23F48073 bic r3, r3, #256
730 0026 C2F84C31 str r3, [r2, #332]
731 .L42:
352:Core/Src/stm32h7xx_hal_msp.c ****
732 .loc 1 352 5 view .LVU225
733 002a 4FF44071 mov r1, #768
734 002e 0F48 ldr r0, .L48+16
735 .LVL34:
352:Core/Src/stm32h7xx_hal_msp.c ****
736 .loc 1 352 5 is_stmt 0 view .LVU226
737 0030 FFF7FEFF bl HAL_GPIO_DeInit
738 .LVL35:
739 0034 ECE7 b .L40
740 .LVL36:
741 .L47:
364:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==0){
742 .loc 1 364 5 is_stmt 1 view .LVU227
364:Core/Src/stm32h7xx_hal_msp.c **** if(HAL_RCC_FDCAN_CLK_ENABLED==0){
743 .loc 1 364 30 is_stmt 0 view .LVU228
744 0036 0B4A ldr r2, .L48+8
745 0038 1368 ldr r3, [r2]
746 003a 013B subs r3, r3, #1
747 003c 1360 str r3, [r2]
365:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_DISABLE();
748 .loc 1 365 5 is_stmt 1 view .LVU229
365:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_FDCAN_CLK_DISABLE();
749 .loc 1 365 7 is_stmt 0 view .LVU230
750 003e 33B9 cbnz r3, .L44
366:Core/Src/stm32h7xx_hal_msp.c **** }
751 .loc 1 366 7 is_stmt 1 view .LVU231
752 0040 094A ldr r2, .L48+12
753 0042 D2F84C31 ldr r3, [r2, #332]
754 0046 23F48073 bic r3, r3, #256
755 004a C2F84C31 str r3, [r2, #332]
756 .L44:
373:Core/Src/stm32h7xx_hal_msp.c ****
757 .loc 1 373 5 view .LVU232
758 004e 4FF44051 mov r1, #12288
759 0052 0648 ldr r0, .L48+16
760 .LVL37:
373:Core/Src/stm32h7xx_hal_msp.c ****
761 .loc 1 373 5 is_stmt 0 view .LVU233
ARM GAS /tmp/cc2Ol4tL.s page 24
762 0054 FFF7FEFF bl HAL_GPIO_DeInit
763 .LVL38:
764 .loc 1 380 1 view .LVU234
765 0058 DAE7 b .L40
766 .L49:
767 005a 00BF .align 2
768 .L48:
769 005c 00A00040 .word 1073782784
770 0060 00A40040 .word 1073783808
771 0064 00000000 .word HAL_RCC_FDCAN_CLK_ENABLED
772 0068 00440258 .word 1476543488
773 006c 00040258 .word 1476527104
774 .cfi_endproc
775 .LFE339:
777 .section .text.HAL_TIM_Base_MspInit,"ax",%progbits
778 .align 1
779 .global HAL_TIM_Base_MspInit
780 .syntax unified
781 .thumb
782 .thumb_func
784 HAL_TIM_Base_MspInit:
785 .LVL39:
786 .LFB340:
381:Core/Src/stm32h7xx_hal_msp.c ****
382:Core/Src/stm32h7xx_hal_msp.c **** /**
383:Core/Src/stm32h7xx_hal_msp.c **** * @brief TIM_Base MSP Initialization
384:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example
385:Core/Src/stm32h7xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer
386:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
387:Core/Src/stm32h7xx_hal_msp.c **** */
388:Core/Src/stm32h7xx_hal_msp.c **** void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
389:Core/Src/stm32h7xx_hal_msp.c **** {
787 .loc 1 389 1 is_stmt 1 view -0
788 .cfi_startproc
789 @ args = 0, pretend = 0, frame = 8
790 @ frame_needed = 0, uses_anonymous_args = 0
791 @ link register save eliminated.
792 .loc 1 389 1 is_stmt 0 view .LVU236
793 0000 82B0 sub sp, sp, #8
794 .cfi_def_cfa_offset 8
390:Core/Src/stm32h7xx_hal_msp.c **** if(htim_base->Instance==TIM1)
795 .loc 1 390 3 is_stmt 1 view .LVU237
796 .loc 1 390 15 is_stmt 0 view .LVU238
797 0002 0368 ldr r3, [r0]
798 .loc 1 390 5 view .LVU239
799 0004 114A ldr r2, .L56
800 0006 9342 cmp r3, r2
801 0008 04D0 beq .L54
391:Core/Src/stm32h7xx_hal_msp.c **** {
392:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspInit 0 */
393:Core/Src/stm32h7xx_hal_msp.c ****
394:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM1_MspInit 0 */
395:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
396:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM1_CLK_ENABLE();
397:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspInit 1 */
398:Core/Src/stm32h7xx_hal_msp.c ****
399:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM1_MspInit 1 */
ARM GAS /tmp/cc2Ol4tL.s page 25
400:Core/Src/stm32h7xx_hal_msp.c **** }
401:Core/Src/stm32h7xx_hal_msp.c **** else if(htim_base->Instance==TIM6)
802 .loc 1 401 8 is_stmt 1 view .LVU240
803 .loc 1 401 10 is_stmt 0 view .LVU241
804 000a 114A ldr r2, .L56+4
805 000c 9342 cmp r3, r2
806 000e 0FD0 beq .L55
807 .L50:
402:Core/Src/stm32h7xx_hal_msp.c **** {
403:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspInit 0 */
404:Core/Src/stm32h7xx_hal_msp.c ****
405:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM6_MspInit 0 */
406:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
407:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM6_CLK_ENABLE();
408:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspInit 1 */
409:Core/Src/stm32h7xx_hal_msp.c ****
410:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM6_MspInit 1 */
411:Core/Src/stm32h7xx_hal_msp.c **** }
412:Core/Src/stm32h7xx_hal_msp.c ****
413:Core/Src/stm32h7xx_hal_msp.c **** }
808 .loc 1 413 1 view .LVU242
809 0010 02B0 add sp, sp, #8
810 .cfi_remember_state
811 .cfi_def_cfa_offset 0
812 @ sp needed
813 0012 7047 bx lr
814 .L54:
815 .cfi_restore_state
396:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspInit 1 */
816 .loc 1 396 5 is_stmt 1 view .LVU243
817 .LBB11:
396:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspInit 1 */
818 .loc 1 396 5 view .LVU244
396:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspInit 1 */
819 .loc 1 396 5 view .LVU245
820 0014 0F4B ldr r3, .L56+8
821 0016 D3F85021 ldr r2, [r3, #336]
822 001a 42F00102 orr r2, r2, #1
823 001e C3F85021 str r2, [r3, #336]
396:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspInit 1 */
824 .loc 1 396 5 view .LVU246
825 0022 D3F85031 ldr r3, [r3, #336]
826 0026 03F00103 and r3, r3, #1
827 002a 0093 str r3, [sp]
396:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspInit 1 */
828 .loc 1 396 5 view .LVU247
829 002c 009B ldr r3, [sp]
830 .LBE11:
396:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspInit 1 */
831 .loc 1 396 5 view .LVU248
832 002e EFE7 b .L50
833 .L55:
407:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspInit 1 */
834 .loc 1 407 5 view .LVU249
835 .LBB12:
407:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspInit 1 */
836 .loc 1 407 5 view .LVU250
ARM GAS /tmp/cc2Ol4tL.s page 26
407:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspInit 1 */
837 .loc 1 407 5 view .LVU251
838 0030 084B ldr r3, .L56+8
839 0032 D3F84821 ldr r2, [r3, #328]
840 0036 42F01002 orr r2, r2, #16
841 003a C3F84821 str r2, [r3, #328]
407:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspInit 1 */
842 .loc 1 407 5 view .LVU252
843 003e D3F84831 ldr r3, [r3, #328]
844 0042 03F01003 and r3, r3, #16
845 0046 0193 str r3, [sp, #4]
407:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspInit 1 */
846 .loc 1 407 5 view .LVU253
847 0048 019B ldr r3, [sp, #4]
848 .LBE12:
407:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspInit 1 */
849 .loc 1 407 5 discriminator 1 view .LVU254
850 .loc 1 413 1 is_stmt 0 view .LVU255
851 004a E1E7 b .L50
852 .L57:
853 .align 2
854 .L56:
855 004c 00000140 .word 1073807360
856 0050 00100040 .word 1073745920
857 0054 00440258 .word 1476543488
858 .cfi_endproc
859 .LFE340:
861 .section .text.HAL_TIM_PWM_MspInit,"ax",%progbits
862 .align 1
863 .global HAL_TIM_PWM_MspInit
864 .syntax unified
865 .thumb
866 .thumb_func
868 HAL_TIM_PWM_MspInit:
869 .LVL40:
870 .LFB341:
414:Core/Src/stm32h7xx_hal_msp.c ****
415:Core/Src/stm32h7xx_hal_msp.c **** /**
416:Core/Src/stm32h7xx_hal_msp.c **** * @brief TIM_PWM MSP Initialization
417:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example
418:Core/Src/stm32h7xx_hal_msp.c **** * @param htim_pwm: TIM_PWM handle pointer
419:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
420:Core/Src/stm32h7xx_hal_msp.c **** */
421:Core/Src/stm32h7xx_hal_msp.c **** void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
422:Core/Src/stm32h7xx_hal_msp.c **** {
871 .loc 1 422 1 is_stmt 1 view -0
872 .cfi_startproc
873 @ args = 0, pretend = 0, frame = 8
874 @ frame_needed = 0, uses_anonymous_args = 0
875 @ link register save eliminated.
876 .loc 1 422 1 is_stmt 0 view .LVU257
877 0000 82B0 sub sp, sp, #8
878 .cfi_def_cfa_offset 8
423:Core/Src/stm32h7xx_hal_msp.c **** if(htim_pwm->Instance==TIM3)
879 .loc 1 423 3 is_stmt 1 view .LVU258
880 .loc 1 423 14 is_stmt 0 view .LVU259
881 0002 0368 ldr r3, [r0]
ARM GAS /tmp/cc2Ol4tL.s page 27
882 .loc 1 423 5 view .LVU260
883 0004 114A ldr r2, .L64
884 0006 9342 cmp r3, r2
885 0008 04D0 beq .L62
424:Core/Src/stm32h7xx_hal_msp.c **** {
425:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 0 */
426:Core/Src/stm32h7xx_hal_msp.c ****
427:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM3_MspInit 0 */
428:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
429:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM3_CLK_ENABLE();
430:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
431:Core/Src/stm32h7xx_hal_msp.c ****
432:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM3_MspInit 1 */
433:Core/Src/stm32h7xx_hal_msp.c **** }
434:Core/Src/stm32h7xx_hal_msp.c **** else if(htim_pwm->Instance==TIM4)
886 .loc 1 434 8 is_stmt 1 view .LVU261
887 .loc 1 434 10 is_stmt 0 view .LVU262
888 000a 114A ldr r2, .L64+4
889 000c 9342 cmp r3, r2
890 000e 0FD0 beq .L63
891 .L58:
435:Core/Src/stm32h7xx_hal_msp.c **** {
436:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 0 */
437:Core/Src/stm32h7xx_hal_msp.c ****
438:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 0 */
439:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
440:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_ENABLE();
441:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
442:Core/Src/stm32h7xx_hal_msp.c ****
443:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 1 */
444:Core/Src/stm32h7xx_hal_msp.c **** }
445:Core/Src/stm32h7xx_hal_msp.c ****
446:Core/Src/stm32h7xx_hal_msp.c **** }
892 .loc 1 446 1 view .LVU263
893 0010 02B0 add sp, sp, #8
894 .cfi_remember_state
895 .cfi_def_cfa_offset 0
896 @ sp needed
897 0012 7047 bx lr
898 .L62:
899 .cfi_restore_state
429:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
900 .loc 1 429 5 is_stmt 1 view .LVU264
901 .LBB13:
429:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
902 .loc 1 429 5 view .LVU265
429:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
903 .loc 1 429 5 view .LVU266
904 0014 0F4B ldr r3, .L64+8
905 0016 D3F84821 ldr r2, [r3, #328]
906 001a 42F00202 orr r2, r2, #2
907 001e C3F84821 str r2, [r3, #328]
429:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
908 .loc 1 429 5 view .LVU267
909 0022 D3F84831 ldr r3, [r3, #328]
910 0026 03F00203 and r3, r3, #2
911 002a 0093 str r3, [sp]
ARM GAS /tmp/cc2Ol4tL.s page 28
429:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
912 .loc 1 429 5 view .LVU268
913 002c 009B ldr r3, [sp]
914 .LBE13:
429:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */
915 .loc 1 429 5 view .LVU269
916 002e EFE7 b .L58
917 .L63:
440:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
918 .loc 1 440 5 view .LVU270
919 .LBB14:
440:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
920 .loc 1 440 5 view .LVU271
440:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
921 .loc 1 440 5 view .LVU272
922 0030 084B ldr r3, .L64+8
923 0032 D3F84821 ldr r2, [r3, #328]
924 0036 42F00402 orr r2, r2, #4
925 003a C3F84821 str r2, [r3, #328]
440:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
926 .loc 1 440 5 view .LVU273
927 003e D3F84831 ldr r3, [r3, #328]
928 0042 03F00403 and r3, r3, #4
929 0046 0193 str r3, [sp, #4]
440:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
930 .loc 1 440 5 view .LVU274
931 0048 019B ldr r3, [sp, #4]
932 .LBE14:
440:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */
933 .loc 1 440 5 discriminator 1 view .LVU275
934 .loc 1 446 1 is_stmt 0 view .LVU276
935 004a E1E7 b .L58
936 .L65:
937 .align 2
938 .L64:
939 004c 00040040 .word 1073742848
940 0050 00080040 .word 1073743872
941 0054 00440258 .word 1476543488
942 .cfi_endproc
943 .LFE341:
945 .section .text.HAL_TIM_IC_MspInit,"ax",%progbits
946 .align 1
947 .global HAL_TIM_IC_MspInit
948 .syntax unified
949 .thumb
950 .thumb_func
952 HAL_TIM_IC_MspInit:
953 .LVL41:
954 .LFB342:
447:Core/Src/stm32h7xx_hal_msp.c ****
448:Core/Src/stm32h7xx_hal_msp.c **** /**
449:Core/Src/stm32h7xx_hal_msp.c **** * @brief TIM_IC MSP Initialization
450:Core/Src/stm32h7xx_hal_msp.c **** * This function configures the hardware resources used in this example
451:Core/Src/stm32h7xx_hal_msp.c **** * @param htim_ic: TIM_IC handle pointer
452:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
453:Core/Src/stm32h7xx_hal_msp.c **** */
454:Core/Src/stm32h7xx_hal_msp.c **** void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* htim_ic)
ARM GAS /tmp/cc2Ol4tL.s page 29
455:Core/Src/stm32h7xx_hal_msp.c **** {
955 .loc 1 455 1 is_stmt 1 view -0
956 .cfi_startproc
957 @ args = 0, pretend = 0, frame = 32
958 @ frame_needed = 0, uses_anonymous_args = 0
959 .loc 1 455 1 is_stmt 0 view .LVU278
960 0000 00B5 push {lr}
961 .cfi_def_cfa_offset 4
962 .cfi_offset 14, -4
963 0002 89B0 sub sp, sp, #36
964 .cfi_def_cfa_offset 40
456:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
965 .loc 1 456 3 is_stmt 1 view .LVU279
966 .loc 1 456 20 is_stmt 0 view .LVU280
967 0004 0023 movs r3, #0
968 0006 0393 str r3, [sp, #12]
969 0008 0493 str r3, [sp, #16]
970 000a 0593 str r3, [sp, #20]
971 000c 0693 str r3, [sp, #24]
972 000e 0793 str r3, [sp, #28]
457:Core/Src/stm32h7xx_hal_msp.c **** if(htim_ic->Instance==TIM8)
973 .loc 1 457 3 is_stmt 1 view .LVU281
974 .loc 1 457 13 is_stmt 0 view .LVU282
975 0010 0268 ldr r2, [r0]
976 .loc 1 457 5 view .LVU283
977 0012 03F18043 add r3, r3, #1073741824
978 0016 03F58233 add r3, r3, #66560
979 001a 9A42 cmp r2, r3
980 001c 02D0 beq .L69
981 .LVL42:
982 .L66:
458:Core/Src/stm32h7xx_hal_msp.c **** {
459:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspInit 0 */
460:Core/Src/stm32h7xx_hal_msp.c ****
461:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM8_MspInit 0 */
462:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock enable */
463:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM8_CLK_ENABLE();
464:Core/Src/stm32h7xx_hal_msp.c ****
465:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
466:Core/Src/stm32h7xx_hal_msp.c **** /**TIM8 GPIO Configuration
467:Core/Src/stm32h7xx_hal_msp.c **** PC6 ------> TIM8_CH1
468:Core/Src/stm32h7xx_hal_msp.c **** PC7 ------> TIM8_CH2
469:Core/Src/stm32h7xx_hal_msp.c **** */
470:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = WS1_Pin|WS2_Pin;
471:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
472:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
473:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
474:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
475:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
476:Core/Src/stm32h7xx_hal_msp.c ****
477:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspInit 1 */
478:Core/Src/stm32h7xx_hal_msp.c ****
479:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM8_MspInit 1 */
480:Core/Src/stm32h7xx_hal_msp.c ****
481:Core/Src/stm32h7xx_hal_msp.c **** }
482:Core/Src/stm32h7xx_hal_msp.c ****
483:Core/Src/stm32h7xx_hal_msp.c **** }
ARM GAS /tmp/cc2Ol4tL.s page 30
983 .loc 1 483 1 view .LVU284
984 001e 09B0 add sp, sp, #36
985 .cfi_remember_state
986 .cfi_def_cfa_offset 4
987 @ sp needed
988 0020 5DF804FB ldr pc, [sp], #4
989 .LVL43:
990 .L69:
991 .cfi_restore_state
463:Core/Src/stm32h7xx_hal_msp.c ****
992 .loc 1 463 5 is_stmt 1 view .LVU285
993 .LBB15:
463:Core/Src/stm32h7xx_hal_msp.c ****
994 .loc 1 463 5 view .LVU286
463:Core/Src/stm32h7xx_hal_msp.c ****
995 .loc 1 463 5 view .LVU287
996 0024 114B ldr r3, .L70
997 0026 D3F85021 ldr r2, [r3, #336]
998 002a 42F00202 orr r2, r2, #2
999 002e C3F85021 str r2, [r3, #336]
463:Core/Src/stm32h7xx_hal_msp.c ****
1000 .loc 1 463 5 view .LVU288
1001 0032 D3F85021 ldr r2, [r3, #336]
1002 0036 02F00202 and r2, r2, #2
1003 003a 0192 str r2, [sp, #4]
463:Core/Src/stm32h7xx_hal_msp.c ****
1004 .loc 1 463 5 view .LVU289
1005 003c 019A ldr r2, [sp, #4]
1006 .LBE15:
463:Core/Src/stm32h7xx_hal_msp.c ****
1007 .loc 1 463 5 view .LVU290
465:Core/Src/stm32h7xx_hal_msp.c **** /**TIM8 GPIO Configuration
1008 .loc 1 465 5 view .LVU291
1009 .LBB16:
465:Core/Src/stm32h7xx_hal_msp.c **** /**TIM8 GPIO Configuration
1010 .loc 1 465 5 view .LVU292
465:Core/Src/stm32h7xx_hal_msp.c **** /**TIM8 GPIO Configuration
1011 .loc 1 465 5 view .LVU293
1012 003e D3F84021 ldr r2, [r3, #320]
1013 0042 42F00402 orr r2, r2, #4
1014 0046 C3F84021 str r2, [r3, #320]
465:Core/Src/stm32h7xx_hal_msp.c **** /**TIM8 GPIO Configuration
1015 .loc 1 465 5 view .LVU294
1016 004a D3F84031 ldr r3, [r3, #320]
1017 004e 03F00403 and r3, r3, #4
1018 0052 0293 str r3, [sp, #8]
465:Core/Src/stm32h7xx_hal_msp.c **** /**TIM8 GPIO Configuration
1019 .loc 1 465 5 view .LVU295
1020 0054 029B ldr r3, [sp, #8]
1021 .LBE16:
465:Core/Src/stm32h7xx_hal_msp.c **** /**TIM8 GPIO Configuration
1022 .loc 1 465 5 view .LVU296
470:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1023 .loc 1 470 5 view .LVU297
470:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1024 .loc 1 470 25 is_stmt 0 view .LVU298
1025 0056 C023 movs r3, #192
ARM GAS /tmp/cc2Ol4tL.s page 31
1026 0058 0393 str r3, [sp, #12]
471:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1027 .loc 1 471 5 is_stmt 1 view .LVU299
471:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1028 .loc 1 471 26 is_stmt 0 view .LVU300
1029 005a 0223 movs r3, #2
1030 005c 0493 str r3, [sp, #16]
472:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
1031 .loc 1 472 5 is_stmt 1 view .LVU301
473:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
1032 .loc 1 473 5 view .LVU302
474:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
1033 .loc 1 474 5 view .LVU303
474:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
1034 .loc 1 474 31 is_stmt 0 view .LVU304
1035 005e 0323 movs r3, #3
1036 0060 0793 str r3, [sp, #28]
475:Core/Src/stm32h7xx_hal_msp.c ****
1037 .loc 1 475 5 is_stmt 1 view .LVU305
1038 0062 03A9 add r1, sp, #12
1039 0064 0248 ldr r0, .L70+4
1040 .LVL44:
475:Core/Src/stm32h7xx_hal_msp.c ****
1041 .loc 1 475 5 is_stmt 0 view .LVU306
1042 0066 FFF7FEFF bl HAL_GPIO_Init
1043 .LVL45:
1044 .loc 1 483 1 view .LVU307
1045 006a D8E7 b .L66
1046 .L71:
1047 .align 2
1048 .L70:
1049 006c 00440258 .word 1476543488
1050 0070 00080258 .word 1476528128
1051 .cfi_endproc
1052 .LFE342:
1054 .section .text.HAL_TIM_MspPostInit,"ax",%progbits
1055 .align 1
1056 .global HAL_TIM_MspPostInit
1057 .syntax unified
1058 .thumb
1059 .thumb_func
1061 HAL_TIM_MspPostInit:
1062 .LVL46:
1063 .LFB343:
484:Core/Src/stm32h7xx_hal_msp.c ****
485:Core/Src/stm32h7xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
486:Core/Src/stm32h7xx_hal_msp.c **** {
1064 .loc 1 486 1 is_stmt 1 view -0
1065 .cfi_startproc
1066 @ args = 0, pretend = 0, frame = 40
1067 @ frame_needed = 0, uses_anonymous_args = 0
1068 .loc 1 486 1 is_stmt 0 view .LVU309
1069 0000 30B5 push {r4, r5, lr}
1070 .cfi_def_cfa_offset 12
1071 .cfi_offset 4, -12
1072 .cfi_offset 5, -8
1073 .cfi_offset 14, -4
ARM GAS /tmp/cc2Ol4tL.s page 32
1074 0002 8BB0 sub sp, sp, #44
1075 .cfi_def_cfa_offset 56
487:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
1076 .loc 1 487 3 is_stmt 1 view .LVU310
1077 .loc 1 487 20 is_stmt 0 view .LVU311
1078 0004 0023 movs r3, #0
1079 0006 0593 str r3, [sp, #20]
1080 0008 0693 str r3, [sp, #24]
1081 000a 0793 str r3, [sp, #28]
1082 000c 0893 str r3, [sp, #32]
1083 000e 0993 str r3, [sp, #36]
488:Core/Src/stm32h7xx_hal_msp.c **** if(htim->Instance==TIM1)
1084 .loc 1 488 3 is_stmt 1 view .LVU312
1085 .loc 1 488 10 is_stmt 0 view .LVU313
1086 0010 0368 ldr r3, [r0]
1087 .loc 1 488 5 view .LVU314
1088 0012 354A ldr r2, .L80
1089 0014 9342 cmp r3, r2
1090 0016 07D0 beq .L77
489:Core/Src/stm32h7xx_hal_msp.c **** {
490:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspPostInit 0 */
491:Core/Src/stm32h7xx_hal_msp.c ****
492:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM1_MspPostInit 0 */
493:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
494:Core/Src/stm32h7xx_hal_msp.c **** /**TIM1 GPIO Configuration
495:Core/Src/stm32h7xx_hal_msp.c **** PA8 ------> TIM1_CH1
496:Core/Src/stm32h7xx_hal_msp.c **** PA9 ------> TIM1_CH2
497:Core/Src/stm32h7xx_hal_msp.c **** PA10 ------> TIM1_CH3
498:Core/Src/stm32h7xx_hal_msp.c **** PA11 ------> TIM1_CH4
499:Core/Src/stm32h7xx_hal_msp.c **** */
500:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = PWM1_1_Pin|PWM1_2_Pin|PWM1_3_Pin|PWM1_4_Pin;
501:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
502:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
503:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
504:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
505:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
506:Core/Src/stm32h7xx_hal_msp.c ****
507:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspPostInit 1 */
508:Core/Src/stm32h7xx_hal_msp.c ****
509:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM1_MspPostInit 1 */
510:Core/Src/stm32h7xx_hal_msp.c **** }
511:Core/Src/stm32h7xx_hal_msp.c **** else if(htim->Instance==TIM3)
1091 .loc 1 511 8 is_stmt 1 view .LVU315
1092 .loc 1 511 10 is_stmt 0 view .LVU316
1093 0018 344A ldr r2, .L80+4
1094 001a 9342 cmp r3, r2
1095 001c 1DD0 beq .L78
512:Core/Src/stm32h7xx_hal_msp.c **** {
513:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspPostInit 0 */
514:Core/Src/stm32h7xx_hal_msp.c ****
515:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM3_MspPostInit 0 */
516:Core/Src/stm32h7xx_hal_msp.c ****
517:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
518:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
519:Core/Src/stm32h7xx_hal_msp.c **** /**TIM3 GPIO Configuration
520:Core/Src/stm32h7xx_hal_msp.c **** PC9 ------> TIM3_CH4
521:Core/Src/stm32h7xx_hal_msp.c **** PB5 ------> TIM3_CH2
ARM GAS /tmp/cc2Ol4tL.s page 33
522:Core/Src/stm32h7xx_hal_msp.c **** */
523:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = PWM2_2_Pin;
524:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
525:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
526:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
527:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
528:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(PWM2_2_GPIO_Port, &GPIO_InitStruct);
529:Core/Src/stm32h7xx_hal_msp.c ****
530:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = PWM2_1_Pin;
531:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
532:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
533:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
534:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
535:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(PWM2_1_GPIO_Port, &GPIO_InitStruct);
536:Core/Src/stm32h7xx_hal_msp.c ****
537:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspPostInit 1 */
538:Core/Src/stm32h7xx_hal_msp.c ****
539:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM3_MspPostInit 1 */
540:Core/Src/stm32h7xx_hal_msp.c **** }
541:Core/Src/stm32h7xx_hal_msp.c **** else if(htim->Instance==TIM4)
1096 .loc 1 541 8 is_stmt 1 view .LVU317
1097 .loc 1 541 10 is_stmt 0 view .LVU318
1098 001e 344A ldr r2, .L80+8
1099 0020 9342 cmp r3, r2
1100 0022 4AD0 beq .L79
1101 .LVL47:
1102 .L72:
542:Core/Src/stm32h7xx_hal_msp.c **** {
543:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspPostInit 0 */
544:Core/Src/stm32h7xx_hal_msp.c ****
545:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM4_MspPostInit 0 */
546:Core/Src/stm32h7xx_hal_msp.c ****
547:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
548:Core/Src/stm32h7xx_hal_msp.c **** /**TIM4 GPIO Configuration
549:Core/Src/stm32h7xx_hal_msp.c **** PB6 ------> TIM4_CH1
550:Core/Src/stm32h7xx_hal_msp.c **** PB7 ------> TIM4_CH2
551:Core/Src/stm32h7xx_hal_msp.c **** */
552:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pin = PWM3_2_Pin|PWM3_2B7_Pin;
553:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
554:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
555:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
556:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
557:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
558:Core/Src/stm32h7xx_hal_msp.c ****
559:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspPostInit 1 */
560:Core/Src/stm32h7xx_hal_msp.c ****
561:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM4_MspPostInit 1 */
562:Core/Src/stm32h7xx_hal_msp.c **** }
563:Core/Src/stm32h7xx_hal_msp.c ****
564:Core/Src/stm32h7xx_hal_msp.c **** }
1103 .loc 1 564 1 view .LVU319
1104 0024 0BB0 add sp, sp, #44
1105 .cfi_remember_state
1106 .cfi_def_cfa_offset 12
1107 @ sp needed
1108 0026 30BD pop {r4, r5, pc}
1109 .LVL48:
ARM GAS /tmp/cc2Ol4tL.s page 34
1110 .L77:
1111 .cfi_restore_state
493:Core/Src/stm32h7xx_hal_msp.c **** /**TIM1 GPIO Configuration
1112 .loc 1 493 5 is_stmt 1 view .LVU320
1113 .LBB17:
493:Core/Src/stm32h7xx_hal_msp.c **** /**TIM1 GPIO Configuration
1114 .loc 1 493 5 view .LVU321
493:Core/Src/stm32h7xx_hal_msp.c **** /**TIM1 GPIO Configuration
1115 .loc 1 493 5 view .LVU322
1116 0028 324B ldr r3, .L80+12
1117 002a D3F84021 ldr r2, [r3, #320]
1118 002e 42F00102 orr r2, r2, #1
1119 0032 C3F84021 str r2, [r3, #320]
493:Core/Src/stm32h7xx_hal_msp.c **** /**TIM1 GPIO Configuration
1120 .loc 1 493 5 view .LVU323
1121 0036 D3F84031 ldr r3, [r3, #320]
1122 003a 03F00103 and r3, r3, #1
1123 003e 0193 str r3, [sp, #4]
493:Core/Src/stm32h7xx_hal_msp.c **** /**TIM1 GPIO Configuration
1124 .loc 1 493 5 view .LVU324
1125 0040 019B ldr r3, [sp, #4]
1126 .LBE17:
493:Core/Src/stm32h7xx_hal_msp.c **** /**TIM1 GPIO Configuration
1127 .loc 1 493 5 view .LVU325
500:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1128 .loc 1 500 5 view .LVU326
500:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1129 .loc 1 500 25 is_stmt 0 view .LVU327
1130 0042 4FF47063 mov r3, #3840
1131 0046 0593 str r3, [sp, #20]
501:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1132 .loc 1 501 5 is_stmt 1 view .LVU328
501:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1133 .loc 1 501 26 is_stmt 0 view .LVU329
1134 0048 0223 movs r3, #2
1135 004a 0693 str r3, [sp, #24]
502:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
1136 .loc 1 502 5 is_stmt 1 view .LVU330
503:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
1137 .loc 1 503 5 view .LVU331
504:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
1138 .loc 1 504 5 view .LVU332
504:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
1139 .loc 1 504 31 is_stmt 0 view .LVU333
1140 004c 0123 movs r3, #1
1141 004e 0993 str r3, [sp, #36]
505:Core/Src/stm32h7xx_hal_msp.c ****
1142 .loc 1 505 5 is_stmt 1 view .LVU334
1143 0050 05A9 add r1, sp, #20
1144 0052 2948 ldr r0, .L80+16
1145 .LVL49:
505:Core/Src/stm32h7xx_hal_msp.c ****
1146 .loc 1 505 5 is_stmt 0 view .LVU335
1147 0054 FFF7FEFF bl HAL_GPIO_Init
1148 .LVL50:
1149 0058 E4E7 b .L72
1150 .LVL51:
ARM GAS /tmp/cc2Ol4tL.s page 35
1151 .L78:
517:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
1152 .loc 1 517 5 is_stmt 1 view .LVU336
1153 .LBB18:
517:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
1154 .loc 1 517 5 view .LVU337
517:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
1155 .loc 1 517 5 view .LVU338
1156 005a 264B ldr r3, .L80+12
1157 005c D3F84021 ldr r2, [r3, #320]
1158 0060 42F00402 orr r2, r2, #4
1159 0064 C3F84021 str r2, [r3, #320]
517:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
1160 .loc 1 517 5 view .LVU339
1161 0068 D3F84021 ldr r2, [r3, #320]
1162 006c 02F00402 and r2, r2, #4
1163 0070 0292 str r2, [sp, #8]
517:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
1164 .loc 1 517 5 view .LVU340
1165 0072 029A ldr r2, [sp, #8]
1166 .LBE18:
517:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
1167 .loc 1 517 5 view .LVU341
518:Core/Src/stm32h7xx_hal_msp.c **** /**TIM3 GPIO Configuration
1168 .loc 1 518 5 view .LVU342
1169 .LBB19:
518:Core/Src/stm32h7xx_hal_msp.c **** /**TIM3 GPIO Configuration
1170 .loc 1 518 5 view .LVU343
518:Core/Src/stm32h7xx_hal_msp.c **** /**TIM3 GPIO Configuration
1171 .loc 1 518 5 view .LVU344
1172 0074 D3F84021 ldr r2, [r3, #320]
1173 0078 42F00202 orr r2, r2, #2
1174 007c C3F84021 str r2, [r3, #320]
518:Core/Src/stm32h7xx_hal_msp.c **** /**TIM3 GPIO Configuration
1175 .loc 1 518 5 view .LVU345
1176 0080 D3F84031 ldr r3, [r3, #320]
1177 0084 03F00203 and r3, r3, #2
1178 0088 0393 str r3, [sp, #12]
518:Core/Src/stm32h7xx_hal_msp.c **** /**TIM3 GPIO Configuration
1179 .loc 1 518 5 view .LVU346
1180 008a 039B ldr r3, [sp, #12]
1181 .LBE19:
518:Core/Src/stm32h7xx_hal_msp.c **** /**TIM3 GPIO Configuration
1182 .loc 1 518 5 view .LVU347
523:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1183 .loc 1 523 5 view .LVU348
523:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1184 .loc 1 523 25 is_stmt 0 view .LVU349
1185 008c 4FF40073 mov r3, #512
1186 0090 0593 str r3, [sp, #20]
524:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1187 .loc 1 524 5 is_stmt 1 view .LVU350
524:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1188 .loc 1 524 26 is_stmt 0 view .LVU351
1189 0092 0224 movs r4, #2
1190 0094 0694 str r4, [sp, #24]
525:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
ARM GAS /tmp/cc2Ol4tL.s page 36
1191 .loc 1 525 5 is_stmt 1 view .LVU352
526:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
1192 .loc 1 526 5 view .LVU353
527:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(PWM2_2_GPIO_Port, &GPIO_InitStruct);
1193 .loc 1 527 5 view .LVU354
527:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(PWM2_2_GPIO_Port, &GPIO_InitStruct);
1194 .loc 1 527 31 is_stmt 0 view .LVU355
1195 0096 0994 str r4, [sp, #36]
528:Core/Src/stm32h7xx_hal_msp.c ****
1196 .loc 1 528 5 is_stmt 1 view .LVU356
1197 0098 05AD add r5, sp, #20
1198 009a 2946 mov r1, r5
1199 009c 1748 ldr r0, .L80+20
1200 .LVL52:
528:Core/Src/stm32h7xx_hal_msp.c ****
1201 .loc 1 528 5 is_stmt 0 view .LVU357
1202 009e FFF7FEFF bl HAL_GPIO_Init
1203 .LVL53:
530:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1204 .loc 1 530 5 is_stmt 1 view .LVU358
530:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1205 .loc 1 530 25 is_stmt 0 view .LVU359
1206 00a2 2023 movs r3, #32
1207 00a4 0593 str r3, [sp, #20]
531:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1208 .loc 1 531 5 is_stmt 1 view .LVU360
531:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1209 .loc 1 531 26 is_stmt 0 view .LVU361
1210 00a6 0694 str r4, [sp, #24]
532:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
1211 .loc 1 532 5 is_stmt 1 view .LVU362
532:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
1212 .loc 1 532 26 is_stmt 0 view .LVU363
1213 00a8 0023 movs r3, #0
1214 00aa 0793 str r3, [sp, #28]
533:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
1215 .loc 1 533 5 is_stmt 1 view .LVU364
533:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
1216 .loc 1 533 27 is_stmt 0 view .LVU365
1217 00ac 0893 str r3, [sp, #32]
534:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(PWM2_1_GPIO_Port, &GPIO_InitStruct);
1218 .loc 1 534 5 is_stmt 1 view .LVU366
534:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(PWM2_1_GPIO_Port, &GPIO_InitStruct);
1219 .loc 1 534 31 is_stmt 0 view .LVU367
1220 00ae 0994 str r4, [sp, #36]
535:Core/Src/stm32h7xx_hal_msp.c ****
1221 .loc 1 535 5 is_stmt 1 view .LVU368
1222 00b0 2946 mov r1, r5
1223 00b2 1348 ldr r0, .L80+24
1224 00b4 FFF7FEFF bl HAL_GPIO_Init
1225 .LVL54:
1226 00b8 B4E7 b .L72
1227 .LVL55:
1228 .L79:
547:Core/Src/stm32h7xx_hal_msp.c **** /**TIM4 GPIO Configuration
1229 .loc 1 547 5 view .LVU369
1230 .LBB20:
ARM GAS /tmp/cc2Ol4tL.s page 37
547:Core/Src/stm32h7xx_hal_msp.c **** /**TIM4 GPIO Configuration
1231 .loc 1 547 5 view .LVU370
547:Core/Src/stm32h7xx_hal_msp.c **** /**TIM4 GPIO Configuration
1232 .loc 1 547 5 view .LVU371
1233 00ba 0E4B ldr r3, .L80+12
1234 00bc D3F84021 ldr r2, [r3, #320]
1235 00c0 42F00202 orr r2, r2, #2
1236 00c4 C3F84021 str r2, [r3, #320]
547:Core/Src/stm32h7xx_hal_msp.c **** /**TIM4 GPIO Configuration
1237 .loc 1 547 5 view .LVU372
1238 00c8 D3F84031 ldr r3, [r3, #320]
1239 00cc 03F00203 and r3, r3, #2
1240 00d0 0493 str r3, [sp, #16]
547:Core/Src/stm32h7xx_hal_msp.c **** /**TIM4 GPIO Configuration
1241 .loc 1 547 5 view .LVU373
1242 00d2 049B ldr r3, [sp, #16]
1243 .LBE20:
547:Core/Src/stm32h7xx_hal_msp.c **** /**TIM4 GPIO Configuration
1244 .loc 1 547 5 view .LVU374
552:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1245 .loc 1 552 5 view .LVU375
552:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
1246 .loc 1 552 25 is_stmt 0 view .LVU376
1247 00d4 C023 movs r3, #192
1248 00d6 0593 str r3, [sp, #20]
553:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1249 .loc 1 553 5 is_stmt 1 view .LVU377
553:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
1250 .loc 1 553 26 is_stmt 0 view .LVU378
1251 00d8 0223 movs r3, #2
1252 00da 0693 str r3, [sp, #24]
554:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
1253 .loc 1 554 5 is_stmt 1 view .LVU379
555:Core/Src/stm32h7xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
1254 .loc 1 555 5 view .LVU380
556:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
1255 .loc 1 556 5 view .LVU381
556:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
1256 .loc 1 556 31 is_stmt 0 view .LVU382
1257 00dc 0993 str r3, [sp, #36]
557:Core/Src/stm32h7xx_hal_msp.c ****
1258 .loc 1 557 5 is_stmt 1 view .LVU383
1259 00de 05A9 add r1, sp, #20
1260 00e0 0748 ldr r0, .L80+24
1261 .LVL56:
557:Core/Src/stm32h7xx_hal_msp.c ****
1262 .loc 1 557 5 is_stmt 0 view .LVU384
1263 00e2 FFF7FEFF bl HAL_GPIO_Init
1264 .LVL57:
1265 .loc 1 564 1 view .LVU385
1266 00e6 9DE7 b .L72
1267 .L81:
1268 .align 2
1269 .L80:
1270 00e8 00000140 .word 1073807360
1271 00ec 00040040 .word 1073742848
1272 00f0 00080040 .word 1073743872
ARM GAS /tmp/cc2Ol4tL.s page 38
1273 00f4 00440258 .word 1476543488
1274 00f8 00000258 .word 1476526080
1275 00fc 00080258 .word 1476528128
1276 0100 00040258 .word 1476527104
1277 .cfi_endproc
1278 .LFE343:
1280 .section .text.HAL_TIM_Base_MspDeInit,"ax",%progbits
1281 .align 1
1282 .global HAL_TIM_Base_MspDeInit
1283 .syntax unified
1284 .thumb
1285 .thumb_func
1287 HAL_TIM_Base_MspDeInit:
1288 .LVL58:
1289 .LFB344:
565:Core/Src/stm32h7xx_hal_msp.c **** /**
566:Core/Src/stm32h7xx_hal_msp.c **** * @brief TIM_Base MSP De-Initialization
567:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
568:Core/Src/stm32h7xx_hal_msp.c **** * @param htim_base: TIM_Base handle pointer
569:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
570:Core/Src/stm32h7xx_hal_msp.c **** */
571:Core/Src/stm32h7xx_hal_msp.c **** void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
572:Core/Src/stm32h7xx_hal_msp.c **** {
1290 .loc 1 572 1 is_stmt 1 view -0
1291 .cfi_startproc
1292 @ args = 0, pretend = 0, frame = 0
1293 @ frame_needed = 0, uses_anonymous_args = 0
1294 @ link register save eliminated.
573:Core/Src/stm32h7xx_hal_msp.c **** if(htim_base->Instance==TIM1)
1295 .loc 1 573 3 view .LVU387
1296 .loc 1 573 15 is_stmt 0 view .LVU388
1297 0000 0368 ldr r3, [r0]
1298 .loc 1 573 5 view .LVU389
1299 0002 0B4A ldr r2, .L87
1300 0004 9342 cmp r3, r2
1301 0006 03D0 beq .L85
574:Core/Src/stm32h7xx_hal_msp.c **** {
575:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspDeInit 0 */
576:Core/Src/stm32h7xx_hal_msp.c ****
577:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM1_MspDeInit 0 */
578:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
579:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM1_CLK_DISABLE();
580:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspDeInit 1 */
581:Core/Src/stm32h7xx_hal_msp.c ****
582:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM1_MspDeInit 1 */
583:Core/Src/stm32h7xx_hal_msp.c **** }
584:Core/Src/stm32h7xx_hal_msp.c **** else if(htim_base->Instance==TIM6)
1302 .loc 1 584 8 is_stmt 1 view .LVU390
1303 .loc 1 584 10 is_stmt 0 view .LVU391
1304 0008 0A4A ldr r2, .L87+4
1305 000a 9342 cmp r3, r2
1306 000c 08D0 beq .L86
1307 .L82:
585:Core/Src/stm32h7xx_hal_msp.c **** {
586:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspDeInit 0 */
587:Core/Src/stm32h7xx_hal_msp.c ****
588:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM6_MspDeInit 0 */
ARM GAS /tmp/cc2Ol4tL.s page 39
589:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
590:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM6_CLK_DISABLE();
591:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspDeInit 1 */
592:Core/Src/stm32h7xx_hal_msp.c ****
593:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM6_MspDeInit 1 */
594:Core/Src/stm32h7xx_hal_msp.c **** }
595:Core/Src/stm32h7xx_hal_msp.c ****
596:Core/Src/stm32h7xx_hal_msp.c **** }
1308 .loc 1 596 1 view .LVU392
1309 000e 7047 bx lr
1310 .L85:
579:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM1_MspDeInit 1 */
1311 .loc 1 579 5 is_stmt 1 view .LVU393
1312 0010 094A ldr r2, .L87+8
1313 0012 D2F85031 ldr r3, [r2, #336]
1314 0016 23F00103 bic r3, r3, #1
1315 001a C2F85031 str r3, [r2, #336]
1316 001e 7047 bx lr
1317 .L86:
590:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM6_MspDeInit 1 */
1318 .loc 1 590 5 view .LVU394
1319 0020 054A ldr r2, .L87+8
1320 0022 D2F84831 ldr r3, [r2, #328]
1321 0026 23F01003 bic r3, r3, #16
1322 002a C2F84831 str r3, [r2, #328]
1323 .loc 1 596 1 is_stmt 0 view .LVU395
1324 002e EEE7 b .L82
1325 .L88:
1326 .align 2
1327 .L87:
1328 0030 00000140 .word 1073807360
1329 0034 00100040 .word 1073745920
1330 0038 00440258 .word 1476543488
1331 .cfi_endproc
1332 .LFE344:
1334 .section .text.HAL_TIM_PWM_MspDeInit,"ax",%progbits
1335 .align 1
1336 .global HAL_TIM_PWM_MspDeInit
1337 .syntax unified
1338 .thumb
1339 .thumb_func
1341 HAL_TIM_PWM_MspDeInit:
1342 .LVL59:
1343 .LFB345:
597:Core/Src/stm32h7xx_hal_msp.c ****
598:Core/Src/stm32h7xx_hal_msp.c **** /**
599:Core/Src/stm32h7xx_hal_msp.c **** * @brief TIM_PWM MSP De-Initialization
600:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
601:Core/Src/stm32h7xx_hal_msp.c **** * @param htim_pwm: TIM_PWM handle pointer
602:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
603:Core/Src/stm32h7xx_hal_msp.c **** */
604:Core/Src/stm32h7xx_hal_msp.c **** void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
605:Core/Src/stm32h7xx_hal_msp.c **** {
1344 .loc 1 605 1 is_stmt 1 view -0
1345 .cfi_startproc
1346 @ args = 0, pretend = 0, frame = 0
1347 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS /tmp/cc2Ol4tL.s page 40
1348 @ link register save eliminated.
606:Core/Src/stm32h7xx_hal_msp.c **** if(htim_pwm->Instance==TIM3)
1349 .loc 1 606 3 view .LVU397
1350 .loc 1 606 14 is_stmt 0 view .LVU398
1351 0000 0368 ldr r3, [r0]
1352 .loc 1 606 5 view .LVU399
1353 0002 0B4A ldr r2, .L94
1354 0004 9342 cmp r3, r2
1355 0006 03D0 beq .L92
607:Core/Src/stm32h7xx_hal_msp.c **** {
608:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 0 */
609:Core/Src/stm32h7xx_hal_msp.c ****
610:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM3_MspDeInit 0 */
611:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
612:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM3_CLK_DISABLE();
613:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 1 */
614:Core/Src/stm32h7xx_hal_msp.c ****
615:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM3_MspDeInit 1 */
616:Core/Src/stm32h7xx_hal_msp.c **** }
617:Core/Src/stm32h7xx_hal_msp.c **** else if(htim_pwm->Instance==TIM4)
1356 .loc 1 617 8 is_stmt 1 view .LVU400
1357 .loc 1 617 10 is_stmt 0 view .LVU401
1358 0008 0A4A ldr r2, .L94+4
1359 000a 9342 cmp r3, r2
1360 000c 08D0 beq .L93
1361 .L89:
618:Core/Src/stm32h7xx_hal_msp.c **** {
619:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 0 */
620:Core/Src/stm32h7xx_hal_msp.c ****
621:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 0 */
622:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
623:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_DISABLE();
624:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */
625:Core/Src/stm32h7xx_hal_msp.c ****
626:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 1 */
627:Core/Src/stm32h7xx_hal_msp.c **** }
628:Core/Src/stm32h7xx_hal_msp.c ****
629:Core/Src/stm32h7xx_hal_msp.c **** }
1362 .loc 1 629 1 view .LVU402
1363 000e 7047 bx lr
1364 .L92:
612:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 1 */
1365 .loc 1 612 5 is_stmt 1 view .LVU403
1366 0010 094A ldr r2, .L94+8
1367 0012 D2F84831 ldr r3, [r2, #328]
1368 0016 23F00203 bic r3, r3, #2
1369 001a C2F84831 str r3, [r2, #328]
1370 001e 7047 bx lr
1371 .L93:
623:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */
1372 .loc 1 623 5 view .LVU404
1373 0020 054A ldr r2, .L94+8
1374 0022 D2F84831 ldr r3, [r2, #328]
1375 0026 23F00403 bic r3, r3, #4
1376 002a C2F84831 str r3, [r2, #328]
1377 .loc 1 629 1 is_stmt 0 view .LVU405
1378 002e EEE7 b .L89
ARM GAS /tmp/cc2Ol4tL.s page 41
1379 .L95:
1380 .align 2
1381 .L94:
1382 0030 00040040 .word 1073742848
1383 0034 00080040 .word 1073743872
1384 0038 00440258 .word 1476543488
1385 .cfi_endproc
1386 .LFE345:
1388 .section .text.HAL_TIM_IC_MspDeInit,"ax",%progbits
1389 .align 1
1390 .global HAL_TIM_IC_MspDeInit
1391 .syntax unified
1392 .thumb
1393 .thumb_func
1395 HAL_TIM_IC_MspDeInit:
1396 .LVL60:
1397 .LFB346:
630:Core/Src/stm32h7xx_hal_msp.c ****
631:Core/Src/stm32h7xx_hal_msp.c **** /**
632:Core/Src/stm32h7xx_hal_msp.c **** * @brief TIM_IC MSP De-Initialization
633:Core/Src/stm32h7xx_hal_msp.c **** * This function freeze the hardware resources used in this example
634:Core/Src/stm32h7xx_hal_msp.c **** * @param htim_ic: TIM_IC handle pointer
635:Core/Src/stm32h7xx_hal_msp.c **** * @retval None
636:Core/Src/stm32h7xx_hal_msp.c **** */
637:Core/Src/stm32h7xx_hal_msp.c **** void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef* htim_ic)
638:Core/Src/stm32h7xx_hal_msp.c **** {
1398 .loc 1 638 1 is_stmt 1 view -0
1399 .cfi_startproc
1400 @ args = 0, pretend = 0, frame = 0
1401 @ frame_needed = 0, uses_anonymous_args = 0
1402 .loc 1 638 1 is_stmt 0 view .LVU407
1403 0000 08B5 push {r3, lr}
1404 .cfi_def_cfa_offset 8
1405 .cfi_offset 3, -8
1406 .cfi_offset 14, -4
639:Core/Src/stm32h7xx_hal_msp.c **** if(htim_ic->Instance==TIM8)
1407 .loc 1 639 3 is_stmt 1 view .LVU408
1408 .loc 1 639 13 is_stmt 0 view .LVU409
1409 0002 0268 ldr r2, [r0]
1410 .loc 1 639 5 view .LVU410
1411 0004 074B ldr r3, .L100
1412 0006 9A42 cmp r2, r3
1413 0008 00D0 beq .L99
1414 .LVL61:
1415 .L96:
640:Core/Src/stm32h7xx_hal_msp.c **** {
641:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspDeInit 0 */
642:Core/Src/stm32h7xx_hal_msp.c ****
643:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM8_MspDeInit 0 */
644:Core/Src/stm32h7xx_hal_msp.c **** /* Peripheral clock disable */
645:Core/Src/stm32h7xx_hal_msp.c **** __HAL_RCC_TIM8_CLK_DISABLE();
646:Core/Src/stm32h7xx_hal_msp.c ****
647:Core/Src/stm32h7xx_hal_msp.c **** /**TIM8 GPIO Configuration
648:Core/Src/stm32h7xx_hal_msp.c **** PC6 ------> TIM8_CH1
649:Core/Src/stm32h7xx_hal_msp.c **** PC7 ------> TIM8_CH2
650:Core/Src/stm32h7xx_hal_msp.c **** */
651:Core/Src/stm32h7xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOC, WS1_Pin|WS2_Pin);
ARM GAS /tmp/cc2Ol4tL.s page 42
652:Core/Src/stm32h7xx_hal_msp.c ****
653:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE BEGIN TIM8_MspDeInit 1 */
654:Core/Src/stm32h7xx_hal_msp.c ****
655:Core/Src/stm32h7xx_hal_msp.c **** /* USER CODE END TIM8_MspDeInit 1 */
656:Core/Src/stm32h7xx_hal_msp.c **** }
657:Core/Src/stm32h7xx_hal_msp.c ****
658:Core/Src/stm32h7xx_hal_msp.c **** }
1416 .loc 1 658 1 view .LVU411
1417 000a 08BD pop {r3, pc}
1418 .LVL62:
1419 .L99:
645:Core/Src/stm32h7xx_hal_msp.c ****
1420 .loc 1 645 5 is_stmt 1 view .LVU412
1421 000c 064A ldr r2, .L100+4
1422 000e D2F85031 ldr r3, [r2, #336]
1423 0012 23F00203 bic r3, r3, #2
1424 0016 C2F85031 str r3, [r2, #336]
651:Core/Src/stm32h7xx_hal_msp.c ****
1425 .loc 1 651 5 view .LVU413
1426 001a C021 movs r1, #192
1427 001c 0348 ldr r0, .L100+8
1428 .LVL63:
651:Core/Src/stm32h7xx_hal_msp.c ****
1429 .loc 1 651 5 is_stmt 0 view .LVU414
1430 001e FFF7FEFF bl HAL_GPIO_DeInit
1431 .LVL64:
1432 .loc 1 658 1 view .LVU415
1433 0022 F2E7 b .L96
1434 .L101:
1435 .align 2
1436 .L100:
1437 0024 00040140 .word 1073808384
1438 0028 00440258 .word 1476543488
1439 002c 00080258 .word 1476528128
1440 .cfi_endproc
1441 .LFE346:
1443 .section .bss.HAL_RCC_FDCAN_CLK_ENABLED,"aw",%nobits
1444 .align 2
1447 HAL_RCC_FDCAN_CLK_ENABLED:
1448 0000 00000000 .space 4
1449 .text
1450 .Letext0:
1451 .file 2 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h"
1452 .file 3 "/home/k/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-ea
1453 .file 4 "/home/k/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-none-ea
1454 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h"
1455 .file 6 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h"
1456 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h"
1457 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h"
1458 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h"
1459 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h"
1460 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h"
1461 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h"
1462 .file 13 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h"
1463 .file 14 "Core/Inc/main.h"
1464 .file 15 "<built-in>"
ARM GAS /tmp/cc2Ol4tL.s page 43
DEFINED SYMBOLS
*ABS*:00000000 stm32h7xx_hal_msp.c
/tmp/cc2Ol4tL.s:20 .text.HAL_MspInit:00000000 $t
/tmp/cc2Ol4tL.s:26 .text.HAL_MspInit:00000000 HAL_MspInit
/tmp/cc2Ol4tL.s:59 .text.HAL_MspInit:00000020 $d
/tmp/cc2Ol4tL.s:64 .text.HAL_ADC_MspInit:00000000 $t
/tmp/cc2Ol4tL.s:70 .text.HAL_ADC_MspInit:00000000 HAL_ADC_MspInit
/tmp/cc2Ol4tL.s:345 .text.HAL_ADC_MspInit:0000013c $d
/tmp/cc2Ol4tL.s:356 .text.HAL_ADC_MspDeInit:00000000 $t
/tmp/cc2Ol4tL.s:362 .text.HAL_ADC_MspDeInit:00000000 HAL_ADC_MspDeInit
/tmp/cc2Ol4tL.s:421 .text.HAL_ADC_MspDeInit:00000044 $d
/tmp/cc2Ol4tL.s:430 .text.HAL_FDCAN_MspInit:00000000 $t
/tmp/cc2Ol4tL.s:436 .text.HAL_FDCAN_MspInit:00000000 HAL_FDCAN_MspInit
/tmp/cc2Ol4tL.s:671 .text.HAL_FDCAN_MspInit:0000011c $d
/tmp/cc2Ol4tL.s:1447 .bss.HAL_RCC_FDCAN_CLK_ENABLED:00000000 HAL_RCC_FDCAN_CLK_ENABLED
/tmp/cc2Ol4tL.s:681 .text.HAL_FDCAN_MspDeInit:00000000 $t
/tmp/cc2Ol4tL.s:687 .text.HAL_FDCAN_MspDeInit:00000000 HAL_FDCAN_MspDeInit
/tmp/cc2Ol4tL.s:769 .text.HAL_FDCAN_MspDeInit:0000005c $d
/tmp/cc2Ol4tL.s:778 .text.HAL_TIM_Base_MspInit:00000000 $t
/tmp/cc2Ol4tL.s:784 .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit
/tmp/cc2Ol4tL.s:855 .text.HAL_TIM_Base_MspInit:0000004c $d
/tmp/cc2Ol4tL.s:862 .text.HAL_TIM_PWM_MspInit:00000000 $t
/tmp/cc2Ol4tL.s:868 .text.HAL_TIM_PWM_MspInit:00000000 HAL_TIM_PWM_MspInit
/tmp/cc2Ol4tL.s:939 .text.HAL_TIM_PWM_MspInit:0000004c $d
/tmp/cc2Ol4tL.s:946 .text.HAL_TIM_IC_MspInit:00000000 $t
/tmp/cc2Ol4tL.s:952 .text.HAL_TIM_IC_MspInit:00000000 HAL_TIM_IC_MspInit
/tmp/cc2Ol4tL.s:1049 .text.HAL_TIM_IC_MspInit:0000006c $d
/tmp/cc2Ol4tL.s:1055 .text.HAL_TIM_MspPostInit:00000000 $t
/tmp/cc2Ol4tL.s:1061 .text.HAL_TIM_MspPostInit:00000000 HAL_TIM_MspPostInit
/tmp/cc2Ol4tL.s:1270 .text.HAL_TIM_MspPostInit:000000e8 $d
/tmp/cc2Ol4tL.s:1281 .text.HAL_TIM_Base_MspDeInit:00000000 $t
/tmp/cc2Ol4tL.s:1287 .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit
/tmp/cc2Ol4tL.s:1328 .text.HAL_TIM_Base_MspDeInit:00000030 $d
/tmp/cc2Ol4tL.s:1335 .text.HAL_TIM_PWM_MspDeInit:00000000 $t
/tmp/cc2Ol4tL.s:1341 .text.HAL_TIM_PWM_MspDeInit:00000000 HAL_TIM_PWM_MspDeInit
/tmp/cc2Ol4tL.s:1382 .text.HAL_TIM_PWM_MspDeInit:00000030 $d
/tmp/cc2Ol4tL.s:1389 .text.HAL_TIM_IC_MspDeInit:00000000 $t
/tmp/cc2Ol4tL.s:1395 .text.HAL_TIM_IC_MspDeInit:00000000 HAL_TIM_IC_MspDeInit
/tmp/cc2Ol4tL.s:1437 .text.HAL_TIM_IC_MspDeInit:00000024 $d
/tmp/cc2Ol4tL.s:1444 .bss.HAL_RCC_FDCAN_CLK_ENABLED:00000000 $d
UNDEFINED SYMBOLS
memset
HAL_RCCEx_PeriphCLKConfig
HAL_GPIO_Init
HAL_DMA_Init
HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
Error_Handler
hdma_adc1
HAL_GPIO_DeInit
HAL_DMA_DeInit
HAL_NVIC_DisableIRQ
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