build/debug/sensor-node.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000002ac 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000060b8 080002ac 080002ac 000012ac 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000064 08006364 08006364 00007364 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .init_array 00000004 080063c8 080063c8 000073c8 2**2 CONTENTS, ALLOC, LOAD, DATA 4 .fini_array 00000004 080063cc 080063cc 000073cc 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .data 00000010 20000000 080063d0 00008000 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .bss 000003bc 20000010 080063e0 00008010 2**2 ALLOC 7 ._user_heap_stack 00000604 200003cc 080063e0 000083cc 2**0 ALLOC 8 .ARM.attributes 0000002e 00000000 00000000 00008010 2**0 CONTENTS, READONLY 9 .comment 00000039 00000000 00000000 0000803e 2**0 CONTENTS, READONLY 10 .debug_info 0001daf7 00000000 00000000 00008077 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 00002b08 00000000 00000000 00025b6e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00001358 00000000 00000000 00028678 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_rnglists 000010e4 00000000 00000000 000299d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 000180d2 00000000 00000000 0002aab4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00007f00 00000000 00000000 00042b86 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_frame 0000327c 00000000 00000000 0004aa88 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_loclists 0000e530 00000000 00000000 0004dd04 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line_str 0000003d 00000000 00000000 0005c234 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002ac <__do_global_dtors_aux>: 80002ac: b510 push {r4, lr} 80002ae: 4c05 ldr r4, [pc, #20] @ (80002c4 <__do_global_dtors_aux+0x18>) 80002b0: 7823 ldrb r3, [r4, #0] 80002b2: b933 cbnz r3, 80002c2 <__do_global_dtors_aux+0x16> 80002b4: 4b04 ldr r3, [pc, #16] @ (80002c8 <__do_global_dtors_aux+0x1c>) 80002b6: b113 cbz r3, 80002be <__do_global_dtors_aux+0x12> 80002b8: 4804 ldr r0, [pc, #16] @ (80002cc <__do_global_dtors_aux+0x20>) 80002ba: f3af 8000 nop.w 80002be: 2301 movs r3, #1 80002c0: 7023 strb r3, [r4, #0] 80002c2: bd10 pop {r4, pc} 80002c4: 20000010 .word 0x20000010 80002c8: 00000000 .word 0x00000000 80002cc: 0800634c .word 0x0800634c 080002d0 : 80002d0: b508 push {r3, lr} 80002d2: 4b03 ldr r3, [pc, #12] @ (80002e0 ) 80002d4: b11b cbz r3, 80002de 80002d6: 4903 ldr r1, [pc, #12] @ (80002e4 ) 80002d8: 4803 ldr r0, [pc, #12] @ (80002e8 ) 80002da: f3af 8000 nop.w 80002de: bd08 pop {r3, pc} 80002e0: 00000000 .word 0x00000000 80002e4: 20000014 .word 0x20000014 80002e8: 0800634c .word 0x0800634c 080002ec : /* USER CODE END 4 */ /* MPU Configuration */ void MPU_Config(void) { 80002ec: b530 push {r4, r5, lr} 80002ee: b085 sub sp, #20 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 80002f0: 2400 movs r4, #0 80002f2: 9400 str r4, [sp, #0] 80002f4: 9401 str r4, [sp, #4] 80002f6: 9402 str r4, [sp, #8] 80002f8: 9403 str r4, [sp, #12] /* Disables the MPU */ HAL_MPU_Disable(); 80002fa: f001 fa77 bl 80017ec /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 80002fe: 2301 movs r3, #1 8000300: f88d 3000 strb.w r3, [sp] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8000304: f88d 4001 strb.w r4, [sp, #1] MPU_InitStruct.BaseAddress = 0x0; 8000308: 9401 str r4, [sp, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 800030a: 221f movs r2, #31 800030c: f88d 2008 strb.w r2, [sp, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8000310: 2287 movs r2, #135 @ 0x87 8000312: f88d 2009 strb.w r2, [sp, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8000316: f88d 400a strb.w r4, [sp, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 800031a: f88d 400b strb.w r4, [sp, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 800031e: f88d 300c strb.w r3, [sp, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8000322: f88d 300d strb.w r3, [sp, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8000326: f88d 400e strb.w r4, [sp, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 800032a: f88d 400f strb.w r4, [sp, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 800032e: 4668 mov r0, sp 8000330: f001 fa7a bl 8001828 /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8000334: 2004 movs r0, #4 8000336: f001 fa67 bl 8001808 } 800033a: b005 add sp, #20 800033c: bd30 pop {r4, r5, pc} ... 08000340 : { 8000340: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8000344: b08a sub sp, #40 @ 0x28 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000346: ad05 add r5, sp, #20 8000348: 2400 movs r4, #0 800034a: 9405 str r4, [sp, #20] 800034c: 9406 str r4, [sp, #24] 800034e: 9407 str r4, [sp, #28] 8000350: 9408 str r4, [sp, #32] 8000352: 9409 str r4, [sp, #36] @ 0x24 __HAL_RCC_GPIOH_CLK_ENABLE(); 8000354: 4b43 ldr r3, [pc, #268] @ (8000464 ) 8000356: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 800035a: f042 0280 orr.w r2, r2, #128 @ 0x80 800035e: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8000362: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8000366: f002 0280 and.w r2, r2, #128 @ 0x80 800036a: 9200 str r2, [sp, #0] 800036c: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOC_CLK_ENABLE(); 800036e: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8000372: f042 0204 orr.w r2, r2, #4 8000376: f8c3 2140 str.w r2, [r3, #320] @ 0x140 800037a: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 800037e: f002 0204 and.w r2, r2, #4 8000382: 9201 str r2, [sp, #4] 8000384: 9a01 ldr r2, [sp, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000386: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 800038a: f042 0201 orr.w r2, r2, #1 800038e: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8000392: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8000396: f002 0201 and.w r2, r2, #1 800039a: 9202 str r2, [sp, #8] 800039c: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 800039e: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 80003a2: f042 0202 orr.w r2, r2, #2 80003a6: f8c3 2140 str.w r2, [r3, #320] @ 0x140 80003aa: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 80003ae: f002 0202 and.w r2, r2, #2 80003b2: 9203 str r2, [sp, #12] 80003b4: 9a03 ldr r2, [sp, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 80003b6: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 80003ba: f042 0208 orr.w r2, r2, #8 80003be: f8c3 2140 str.w r2, [r3, #320] @ 0x140 80003c2: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80003c6: f003 0308 and.w r3, r3, #8 80003ca: 9304 str r3, [sp, #16] 80003cc: 9b04 ldr r3, [sp, #16] HAL_GPIO_WritePin(GPIOB, STATUS1_Pin|STATUS2_Pin|STATUS_R_Pin|STATUS_G_Pin, GPIO_PIN_RESET); 80003ce: 4e26 ldr r6, [pc, #152] @ (8000468 ) 80003d0: 4622 mov r2, r4 80003d2: f24c 4104 movw r1, #50180 @ 0xc404 80003d6: 4630 mov r0, r6 80003d8: f002 fc70 bl 8002cbc HAL_GPIO_WritePin(STATUS_B_GPIO_Port, STATUS_B_Pin, GPIO_PIN_RESET); 80003dc: 4f23 ldr r7, [pc, #140] @ (800046c ) 80003de: 4622 mov r2, r4 80003e0: f44f 5180 mov.w r1, #4096 @ 0x1000 80003e4: 4638 mov r0, r7 80003e6: f002 fc69 bl 8002cbc GPIO_InitStruct.Pin = STATUS1_Pin|STATUS2_Pin|STATUS_R_Pin|STATUS_G_Pin; 80003ea: f24c 4304 movw r3, #50180 @ 0xc404 80003ee: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80003f0: f04f 0801 mov.w r8, #1 80003f4: f8cd 8018 str.w r8, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80003f8: 9407 str r4, [sp, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80003fa: 9408 str r4, [sp, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80003fc: 4629 mov r1, r5 80003fe: 4630 mov r0, r6 8000400: f002 fb4c bl 8002a9c GPIO_InitStruct.Pin = STATUS_B_Pin; 8000404: f44f 5380 mov.w r3, #4096 @ 0x1000 8000408: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800040a: f8cd 8018 str.w r8, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800040e: 9407 str r4, [sp, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000410: 9408 str r4, [sp, #32] HAL_GPIO_Init(STATUS_B_GPIO_Port, &GPIO_InitStruct); 8000412: 4629 mov r1, r5 8000414: 4638 mov r0, r7 8000416: f002 fb41 bl 8002a9c GPIO_InitStruct.Pin = D1_IC_Pin; 800041a: f44f 4300 mov.w r3, #32768 @ 0x8000 800041e: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000420: 9406 str r4, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000422: 9407 str r4, [sp, #28] HAL_GPIO_Init(D1_IC_GPIO_Port, &GPIO_InitStruct); 8000424: 4629 mov r1, r5 8000426: 4638 mov r0, r7 8000428: f002 fb38 bl 8002a9c GPIO_InitStruct.Pin = D2_Pin|D3_Pin|D4_IC_Pin; 800042c: f44f 53e0 mov.w r3, #7168 @ 0x1c00 8000430: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000432: 9406 str r4, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000434: 9407 str r4, [sp, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000436: 4629 mov r1, r5 8000438: 480d ldr r0, [pc, #52] @ (8000470 ) 800043a: f002 fb2f bl 8002a9c GPIO_InitStruct.Pin = D5_Pin; 800043e: 2304 movs r3, #4 8000440: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000442: 9406 str r4, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000444: 9407 str r4, [sp, #28] HAL_GPIO_Init(D5_GPIO_Port, &GPIO_InitStruct); 8000446: 4629 mov r1, r5 8000448: 480a ldr r0, [pc, #40] @ (8000474 ) 800044a: f002 fb27 bl 8002a9c GPIO_InitStruct.Pin = D6_Pin; 800044e: 2310 movs r3, #16 8000450: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000452: 9406 str r4, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000454: 9407 str r4, [sp, #28] HAL_GPIO_Init(D6_GPIO_Port, &GPIO_InitStruct); 8000456: 4629 mov r1, r5 8000458: 4630 mov r0, r6 800045a: f002 fb1f bl 8002a9c } 800045e: b00a add sp, #40 @ 0x28 8000460: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8000464: 58024400 .word 0x58024400 8000468: 58020400 .word 0x58020400 800046c: 58020000 .word 0x58020000 8000470: 58020800 .word 0x58020800 8000474: 58020c00 .word 0x58020c00 08000478 : { 8000478: b500 push {lr} 800047a: b083 sub sp, #12 __HAL_RCC_DMA1_CLK_ENABLE(); 800047c: 4b0b ldr r3, [pc, #44] @ (80004ac ) 800047e: f8d3 2138 ldr.w r2, [r3, #312] @ 0x138 8000482: f042 0201 orr.w r2, r2, #1 8000486: f8c3 2138 str.w r2, [r3, #312] @ 0x138 800048a: f8d3 3138 ldr.w r3, [r3, #312] @ 0x138 800048e: f003 0301 and.w r3, r3, #1 8000492: 9301 str r3, [sp, #4] 8000494: 9b01 ldr r3, [sp, #4] HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); 8000496: 2200 movs r2, #0 8000498: 4611 mov r1, r2 800049a: 200b movs r0, #11 800049c: f001 f97e bl 800179c HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 80004a0: 200b movs r0, #11 80004a2: f001 f98b bl 80017bc } 80004a6: b003 add sp, #12 80004a8: f85d fb04 ldr.w pc, [sp], #4 80004ac: 58024400 .word 0x58024400 080004b0 : \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80004b0: b672 cpsid i void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80004b2: e7fe b.n 80004b2 080004b4 : { 80004b4: b500 push {lr} 80004b6: b08b sub sp, #44 @ 0x2c ADC_MultiModeTypeDef multimode = {0}; 80004b8: 2300 movs r3, #0 80004ba: 9307 str r3, [sp, #28] 80004bc: 9308 str r3, [sp, #32] 80004be: 9309 str r3, [sp, #36] @ 0x24 ADC_ChannelConfTypeDef sConfig = {0}; 80004c0: 9300 str r3, [sp, #0] 80004c2: 9301 str r3, [sp, #4] 80004c4: 9302 str r3, [sp, #8] 80004c6: 9303 str r3, [sp, #12] 80004c8: 9304 str r3, [sp, #16] 80004ca: 9305 str r3, [sp, #20] 80004cc: 9306 str r3, [sp, #24] hadc1.Instance = ADC1; 80004ce: 4820 ldr r0, [pc, #128] @ (8000550 ) 80004d0: 4a20 ldr r2, [pc, #128] @ (8000554 ) 80004d2: 6002 str r2, [r0, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80004d4: 6043 str r3, [r0, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 80004d6: 6083 str r3, [r0, #8] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 80004d8: 60c3 str r3, [r0, #12] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 80004da: 2208 movs r2, #8 80004dc: 6102 str r2, [r0, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 80004de: 7503 strb r3, [r0, #20] hadc1.Init.ContinuousConvMode = DISABLE; 80004e0: 7543 strb r3, [r0, #21] hadc1.Init.NbrOfConversion = 1; 80004e2: 2201 movs r2, #1 80004e4: 6182 str r2, [r0, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 80004e6: 7703 strb r3, [r0, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T6_TRGO; 80004e8: f44f 62b4 mov.w r2, #1440 @ 0x5a0 80004ec: 6242 str r2, [r0, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 80004ee: f44f 6280 mov.w r2, #1024 @ 0x400 80004f2: 6282 str r2, [r0, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; 80004f4: 62c3 str r3, [r0, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; 80004f6: f44f 5280 mov.w r2, #4096 @ 0x1000 80004fa: 6302 str r2, [r0, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 80004fc: 6343 str r3, [r0, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 80004fe: f880 3038 strb.w r3, [r0, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000502: f000 ff71 bl 80013e8 8000506: b9e8 cbnz r0, 8000544 multimode.Mode = ADC_MODE_INDEPENDENT; 8000508: 2300 movs r3, #0 800050a: 9307 str r3, [sp, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 800050c: a907 add r1, sp, #28 800050e: 4810 ldr r0, [pc, #64] @ (8000550 ) 8000510: f001 f86c bl 80015ec 8000514: b9c0 cbnz r0, 8000548 sConfig.Channel = ADC_CHANNEL_3; 8000516: 4b10 ldr r3, [pc, #64] @ (8000558 ) 8000518: 9300 str r3, [sp, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 800051a: 2306 movs r3, #6 800051c: 9301 str r3, [sp, #4] sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES_5; 800051e: 2303 movs r3, #3 8000520: 9302 str r3, [sp, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000522: f240 73ff movw r3, #2047 @ 0x7ff 8000526: 9303 str r3, [sp, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000528: 2304 movs r3, #4 800052a: 9304 str r3, [sp, #16] sConfig.Offset = 0; 800052c: 2300 movs r3, #0 800052e: 9305 str r3, [sp, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000530: f88d 3019 strb.w r3, [sp, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000534: 4669 mov r1, sp 8000536: 4806 ldr r0, [pc, #24] @ (8000550 ) 8000538: f000 fcc6 bl 8000ec8 800053c: b930 cbnz r0, 800054c } 800053e: b00b add sp, #44 @ 0x2c 8000540: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8000544: f7ff ffb4 bl 80004b0 Error_Handler(); 8000548: f7ff ffb2 bl 80004b0 Error_Handler(); 800054c: f7ff ffb0 bl 80004b0 8000550: 20000360 .word 0x20000360 8000554: 40022000 .word 0x40022000 8000558: 0c900008 .word 0x0c900008 0800055c : { 800055c: b508 push {r3, lr} hfdcan1.Instance = FDCAN1; 800055e: 4815 ldr r0, [pc, #84] @ (80005b4 ) 8000560: 4b15 ldr r3, [pc, #84] @ (80005b8 ) 8000562: 6003 str r3, [r0, #0] hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; 8000564: 2300 movs r3, #0 8000566: 6083 str r3, [r0, #8] hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; 8000568: 60c3 str r3, [r0, #12] hfdcan1.Init.AutoRetransmission = DISABLE; 800056a: 7403 strb r3, [r0, #16] hfdcan1.Init.TransmitPause = DISABLE; 800056c: 7443 strb r3, [r0, #17] hfdcan1.Init.ProtocolException = DISABLE; 800056e: 7483 strb r3, [r0, #18] hfdcan1.Init.NominalPrescaler = 3; 8000570: 2203 movs r2, #3 8000572: 6142 str r2, [r0, #20] hfdcan1.Init.NominalSyncJumpWidth = 1; 8000574: 2201 movs r2, #1 8000576: 6182 str r2, [r0, #24] hfdcan1.Init.NominalTimeSeg1 = 13; 8000578: 210d movs r1, #13 800057a: 61c1 str r1, [r0, #28] hfdcan1.Init.NominalTimeSeg2 = 2; 800057c: 2102 movs r1, #2 800057e: 6201 str r1, [r0, #32] hfdcan1.Init.DataPrescaler = 1; 8000580: 6242 str r2, [r0, #36] @ 0x24 hfdcan1.Init.DataSyncJumpWidth = 1; 8000582: 6282 str r2, [r0, #40] @ 0x28 hfdcan1.Init.DataTimeSeg1 = 1; 8000584: 62c2 str r2, [r0, #44] @ 0x2c hfdcan1.Init.DataTimeSeg2 = 1; 8000586: 6302 str r2, [r0, #48] @ 0x30 hfdcan1.Init.MessageRAMOffset = 0; 8000588: 6343 str r3, [r0, #52] @ 0x34 hfdcan1.Init.StdFiltersNbr = 0; 800058a: 6383 str r3, [r0, #56] @ 0x38 hfdcan1.Init.ExtFiltersNbr = 0; 800058c: 63c3 str r3, [r0, #60] @ 0x3c hfdcan1.Init.RxFifo0ElmtsNbr = 0; 800058e: 6403 str r3, [r0, #64] @ 0x40 hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; 8000590: 2204 movs r2, #4 8000592: 6442 str r2, [r0, #68] @ 0x44 hfdcan1.Init.RxFifo1ElmtsNbr = 0; 8000594: 6483 str r3, [r0, #72] @ 0x48 hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8; 8000596: 64c2 str r2, [r0, #76] @ 0x4c hfdcan1.Init.RxBuffersNbr = 0; 8000598: 6503 str r3, [r0, #80] @ 0x50 hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8; 800059a: 6542 str r2, [r0, #84] @ 0x54 hfdcan1.Init.TxEventsNbr = 0; 800059c: 6583 str r3, [r0, #88] @ 0x58 hfdcan1.Init.TxBuffersNbr = 0; 800059e: 65c3 str r3, [r0, #92] @ 0x5c hfdcan1.Init.TxFifoQueueElmtsNbr = 0; 80005a0: 6603 str r3, [r0, #96] @ 0x60 hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 80005a2: 6643 str r3, [r0, #100] @ 0x64 hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8; 80005a4: 6682 str r2, [r0, #104] @ 0x68 if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) 80005a6: f002 f92f bl 8002808 80005aa: b900 cbnz r0, 80005ae } 80005ac: bd08 pop {r3, pc} Error_Handler(); 80005ae: f7ff ff7f bl 80004b0 80005b2: bf00 nop 80005b4: 20000248 .word 0x20000248 80005b8: 4000a000 .word 0x4000a000 080005bc : { 80005bc: b508 push {r3, lr} hfdcan2.Instance = FDCAN2; 80005be: 4815 ldr r0, [pc, #84] @ (8000614 ) 80005c0: 4b15 ldr r3, [pc, #84] @ (8000618 ) 80005c2: 6003 str r3, [r0, #0] hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; 80005c4: 2300 movs r3, #0 80005c6: 6083 str r3, [r0, #8] hfdcan2.Init.Mode = FDCAN_MODE_NORMAL; 80005c8: 60c3 str r3, [r0, #12] hfdcan2.Init.AutoRetransmission = DISABLE; 80005ca: 7403 strb r3, [r0, #16] hfdcan2.Init.TransmitPause = DISABLE; 80005cc: 7443 strb r3, [r0, #17] hfdcan2.Init.ProtocolException = DISABLE; 80005ce: 7483 strb r3, [r0, #18] hfdcan2.Init.NominalPrescaler = 3; 80005d0: 2203 movs r2, #3 80005d2: 6142 str r2, [r0, #20] hfdcan2.Init.NominalSyncJumpWidth = 1; 80005d4: 2201 movs r2, #1 80005d6: 6182 str r2, [r0, #24] hfdcan2.Init.NominalTimeSeg1 = 13; 80005d8: 210d movs r1, #13 80005da: 61c1 str r1, [r0, #28] hfdcan2.Init.NominalTimeSeg2 = 2; 80005dc: 2102 movs r1, #2 80005de: 6201 str r1, [r0, #32] hfdcan2.Init.DataPrescaler = 1; 80005e0: 6242 str r2, [r0, #36] @ 0x24 hfdcan2.Init.DataSyncJumpWidth = 1; 80005e2: 6282 str r2, [r0, #40] @ 0x28 hfdcan2.Init.DataTimeSeg1 = 1; 80005e4: 62c2 str r2, [r0, #44] @ 0x2c hfdcan2.Init.DataTimeSeg2 = 1; 80005e6: 6302 str r2, [r0, #48] @ 0x30 hfdcan2.Init.MessageRAMOffset = 0; 80005e8: 6343 str r3, [r0, #52] @ 0x34 hfdcan2.Init.StdFiltersNbr = 0; 80005ea: 6383 str r3, [r0, #56] @ 0x38 hfdcan2.Init.ExtFiltersNbr = 0; 80005ec: 63c3 str r3, [r0, #60] @ 0x3c hfdcan2.Init.RxFifo0ElmtsNbr = 0; 80005ee: 6403 str r3, [r0, #64] @ 0x40 hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; 80005f0: 2204 movs r2, #4 80005f2: 6442 str r2, [r0, #68] @ 0x44 hfdcan2.Init.RxFifo1ElmtsNbr = 0; 80005f4: 6483 str r3, [r0, #72] @ 0x48 hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8; 80005f6: 64c2 str r2, [r0, #76] @ 0x4c hfdcan2.Init.RxBuffersNbr = 0; 80005f8: 6503 str r3, [r0, #80] @ 0x50 hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8; 80005fa: 6542 str r2, [r0, #84] @ 0x54 hfdcan2.Init.TxEventsNbr = 0; 80005fc: 6583 str r3, [r0, #88] @ 0x58 hfdcan2.Init.TxBuffersNbr = 0; 80005fe: 65c3 str r3, [r0, #92] @ 0x5c hfdcan2.Init.TxFifoQueueElmtsNbr = 0; 8000600: 6603 str r3, [r0, #96] @ 0x60 hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 8000602: 6643 str r3, [r0, #100] @ 0x64 hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8; 8000604: 6682 str r2, [r0, #104] @ 0x68 if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) 8000606: f002 f8ff bl 8002808 800060a: b900 cbnz r0, 800060e } 800060c: bd08 pop {r3, pc} Error_Handler(); 800060e: f7ff ff4f bl 80004b0 8000612: bf00 nop 8000614: 200001a8 .word 0x200001a8 8000618: 4000a400 .word 0x4000a400 0800061c : { 800061c: b510 push {r4, lr} 800061e: b09c sub sp, #112 @ 0x70 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000620: 2400 movs r4, #0 8000622: 9418 str r4, [sp, #96] @ 0x60 8000624: 9419 str r4, [sp, #100] @ 0x64 8000626: 941a str r4, [sp, #104] @ 0x68 8000628: 941b str r4, [sp, #108] @ 0x6c TIM_MasterConfigTypeDef sMasterConfig = {0}; 800062a: 9415 str r4, [sp, #84] @ 0x54 800062c: 9416 str r4, [sp, #88] @ 0x58 800062e: 9417 str r4, [sp, #92] @ 0x5c TIM_OC_InitTypeDef sConfigOC = {0}; 8000630: 940e str r4, [sp, #56] @ 0x38 8000632: 940f str r4, [sp, #60] @ 0x3c 8000634: 9410 str r4, [sp, #64] @ 0x40 8000636: 9411 str r4, [sp, #68] @ 0x44 8000638: 9412 str r4, [sp, #72] @ 0x48 800063a: 9413 str r4, [sp, #76] @ 0x4c 800063c: 9414 str r4, [sp, #80] @ 0x50 TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 800063e: 2234 movs r2, #52 @ 0x34 8000640: 4621 mov r1, r4 8000642: a801 add r0, sp, #4 8000644: f005 fe47 bl 80062d6 htim1.Instance = TIM1; 8000648: 483a ldr r0, [pc, #232] @ (8000734 ) 800064a: 4b3b ldr r3, [pc, #236] @ (8000738 ) 800064c: 6003 str r3, [r0, #0] htim1.Init.Prescaler = 0; 800064e: 6044 str r4, [r0, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000650: 6084 str r4, [r0, #8] htim1.Init.Period = 65535; 8000652: f64f 73ff movw r3, #65535 @ 0xffff 8000656: 60c3 str r3, [r0, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000658: 6104 str r4, [r0, #16] htim1.Init.RepetitionCounter = 0; 800065a: 6144 str r4, [r0, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800065c: 6184 str r4, [r0, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 800065e: f005 fa0b bl 8005a78 8000662: 2800 cmp r0, #0 8000664: d153 bne.n 800070e sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000666: f44f 5380 mov.w r3, #4096 @ 0x1000 800066a: 9318 str r3, [sp, #96] @ 0x60 if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 800066c: a918 add r1, sp, #96 @ 0x60 800066e: 4831 ldr r0, [pc, #196] @ (8000734 ) 8000670: f005 fc38 bl 8005ee4 8000674: 2800 cmp r0, #0 8000676: d14c bne.n 8000712 if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8000678: 482e ldr r0, [pc, #184] @ (8000734 ) 800067a: f005 fa2d bl 8005ad8 800067e: 2800 cmp r0, #0 8000680: d149 bne.n 8000716 sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000682: 2300 movs r3, #0 8000684: 9315 str r3, [sp, #84] @ 0x54 sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000686: 9316 str r3, [sp, #88] @ 0x58 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000688: 9317 str r3, [sp, #92] @ 0x5c if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 800068a: a915 add r1, sp, #84 @ 0x54 800068c: 4829 ldr r0, [pc, #164] @ (8000734 ) 800068e: f005 fcc5 bl 800601c 8000692: 2800 cmp r0, #0 8000694: d141 bne.n 800071a sConfigOC.OCMode = TIM_OCMODE_PWM1; 8000696: 2360 movs r3, #96 @ 0x60 8000698: 930e str r3, [sp, #56] @ 0x38 sConfigOC.Pulse = 0; 800069a: 2200 movs r2, #0 800069c: 920f str r2, [sp, #60] @ 0x3c sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800069e: 9210 str r2, [sp, #64] @ 0x40 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 80006a0: 9211 str r2, [sp, #68] @ 0x44 sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80006a2: 9212 str r2, [sp, #72] @ 0x48 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 80006a4: 9213 str r2, [sp, #76] @ 0x4c sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 80006a6: 9214 str r2, [sp, #80] @ 0x50 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80006a8: a90e add r1, sp, #56 @ 0x38 80006aa: 4822 ldr r0, [pc, #136] @ (8000734 ) 80006ac: f005 fabe bl 8005c2c 80006b0: 2800 cmp r0, #0 80006b2: d134 bne.n 800071e if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 80006b4: 2204 movs r2, #4 80006b6: a90e add r1, sp, #56 @ 0x38 80006b8: 481e ldr r0, [pc, #120] @ (8000734 ) 80006ba: f005 fab7 bl 8005c2c 80006be: 2800 cmp r0, #0 80006c0: d12f bne.n 8000722 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 80006c2: 2208 movs r2, #8 80006c4: a90e add r1, sp, #56 @ 0x38 80006c6: 481b ldr r0, [pc, #108] @ (8000734 ) 80006c8: f005 fab0 bl 8005c2c 80006cc: bb58 cbnz r0, 8000726 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 80006ce: 220c movs r2, #12 80006d0: a90e add r1, sp, #56 @ 0x38 80006d2: 4818 ldr r0, [pc, #96] @ (8000734 ) 80006d4: f005 faaa bl 8005c2c 80006d8: bb38 cbnz r0, 800072a sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 80006da: 2300 movs r3, #0 80006dc: 9301 str r3, [sp, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 80006de: 9302 str r3, [sp, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 80006e0: 9303 str r3, [sp, #12] sBreakDeadTimeConfig.DeadTime = 0; 80006e2: 9304 str r3, [sp, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 80006e4: 9305 str r3, [sp, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 80006e6: f44f 5200 mov.w r2, #8192 @ 0x2000 80006ea: 9206 str r2, [sp, #24] sBreakDeadTimeConfig.BreakFilter = 0; 80006ec: 9307 str r3, [sp, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 80006ee: 9309 str r3, [sp, #36] @ 0x24 sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 80006f0: f04f 7200 mov.w r2, #33554432 @ 0x2000000 80006f4: 920a str r2, [sp, #40] @ 0x28 sBreakDeadTimeConfig.Break2Filter = 0; 80006f6: 930b str r3, [sp, #44] @ 0x2c sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 80006f8: 930d str r3, [sp, #52] @ 0x34 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 80006fa: a901 add r1, sp, #4 80006fc: 480d ldr r0, [pc, #52] @ (8000734 ) 80006fe: f005 fcdd bl 80060bc 8000702: b9a0 cbnz r0, 800072e HAL_TIM_MspPostInit(&htim1); 8000704: 480b ldr r0, [pc, #44] @ (8000734 ) 8000706: f002 fcc7 bl 8003098 } 800070a: b01c add sp, #112 @ 0x70 800070c: bd10 pop {r4, pc} Error_Handler(); 800070e: f7ff fecf bl 80004b0 Error_Handler(); 8000712: f7ff fecd bl 80004b0 Error_Handler(); 8000716: f7ff fecb bl 80004b0 Error_Handler(); 800071a: f7ff fec9 bl 80004b0 Error_Handler(); 800071e: f7ff fec7 bl 80004b0 Error_Handler(); 8000722: f7ff fec5 bl 80004b0 Error_Handler(); 8000726: f7ff fec3 bl 80004b0 Error_Handler(); 800072a: f7ff fec1 bl 80004b0 Error_Handler(); 800072e: f7ff febf bl 80004b0 8000732: bf00 nop 8000734: 2000015c .word 0x2000015c 8000738: 40010000 .word 0x40010000 0800073c : { 800073c: b500 push {lr} 800073e: b08b sub sp, #44 @ 0x2c TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000740: 2300 movs r3, #0 8000742: 9307 str r3, [sp, #28] 8000744: 9308 str r3, [sp, #32] 8000746: 9309 str r3, [sp, #36] @ 0x24 TIM_OC_InitTypeDef sConfigOC = {0}; 8000748: 9300 str r3, [sp, #0] 800074a: 9301 str r3, [sp, #4] 800074c: 9302 str r3, [sp, #8] 800074e: 9303 str r3, [sp, #12] 8000750: 9304 str r3, [sp, #16] 8000752: 9305 str r3, [sp, #20] 8000754: 9306 str r3, [sp, #24] htim3.Instance = TIM3; 8000756: 481a ldr r0, [pc, #104] @ (80007c0 ) 8000758: 4a1a ldr r2, [pc, #104] @ (80007c4 ) 800075a: 6002 str r2, [r0, #0] htim3.Init.Prescaler = 0; 800075c: 6043 str r3, [r0, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800075e: 6083 str r3, [r0, #8] htim3.Init.Period = 65535; 8000760: f64f 72ff movw r2, #65535 @ 0xffff 8000764: 60c2 str r2, [r0, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000766: 6103 str r3, [r0, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000768: 6183 str r3, [r0, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 800076a: f005 f9b5 bl 8005ad8 800076e: b9f8 cbnz r0, 80007b0 sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000770: 2300 movs r3, #0 8000772: 9307 str r3, [sp, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000774: 9309 str r3, [sp, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8000776: a907 add r1, sp, #28 8000778: 4811 ldr r0, [pc, #68] @ (80007c0 ) 800077a: f005 fc4f bl 800601c 800077e: b9c8 cbnz r0, 80007b4 sConfigOC.OCMode = TIM_OCMODE_PWM1; 8000780: 2360 movs r3, #96 @ 0x60 8000782: 9300 str r3, [sp, #0] sConfigOC.Pulse = 0; 8000784: 2300 movs r3, #0 8000786: 9301 str r3, [sp, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000788: 9302 str r3, [sp, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800078a: 9304 str r3, [sp, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800078c: 2204 movs r2, #4 800078e: 4669 mov r1, sp 8000790: 480b ldr r0, [pc, #44] @ (80007c0 ) 8000792: f005 fa4b bl 8005c2c 8000796: b978 cbnz r0, 80007b8 if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 8000798: 220c movs r2, #12 800079a: 4669 mov r1, sp 800079c: 4808 ldr r0, [pc, #32] @ (80007c0 ) 800079e: f005 fa45 bl 8005c2c 80007a2: b958 cbnz r0, 80007bc HAL_TIM_MspPostInit(&htim3); 80007a4: 4806 ldr r0, [pc, #24] @ (80007c0 ) 80007a6: f002 fc77 bl 8003098 } 80007aa: b00b add sp, #44 @ 0x2c 80007ac: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 80007b0: f7ff fe7e bl 80004b0 Error_Handler(); 80007b4: f7ff fe7c bl 80004b0 Error_Handler(); 80007b8: f7ff fe7a bl 80004b0 Error_Handler(); 80007bc: f7ff fe78 bl 80004b0 80007c0: 20000110 .word 0x20000110 80007c4: 40000400 .word 0x40000400 080007c8 : { 80007c8: b500 push {lr} 80007ca: b08b sub sp, #44 @ 0x2c TIM_MasterConfigTypeDef sMasterConfig = {0}; 80007cc: 2300 movs r3, #0 80007ce: 9307 str r3, [sp, #28] 80007d0: 9308 str r3, [sp, #32] 80007d2: 9309 str r3, [sp, #36] @ 0x24 TIM_OC_InitTypeDef sConfigOC = {0}; 80007d4: 9300 str r3, [sp, #0] 80007d6: 9301 str r3, [sp, #4] 80007d8: 9302 str r3, [sp, #8] 80007da: 9303 str r3, [sp, #12] 80007dc: 9304 str r3, [sp, #16] 80007de: 9305 str r3, [sp, #20] 80007e0: 9306 str r3, [sp, #24] htim4.Instance = TIM4; 80007e2: 481a ldr r0, [pc, #104] @ (800084c ) 80007e4: 4a1a ldr r2, [pc, #104] @ (8000850 ) 80007e6: 6002 str r2, [r0, #0] htim4.Init.Prescaler = 0; 80007e8: 6043 str r3, [r0, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 80007ea: 6083 str r3, [r0, #8] htim4.Init.Period = 65535; 80007ec: f64f 72ff movw r2, #65535 @ 0xffff 80007f0: 60c2 str r2, [r0, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80007f2: 6103 str r3, [r0, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80007f4: 6183 str r3, [r0, #24] if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) 80007f6: f005 f96f bl 8005ad8 80007fa: b9f0 cbnz r0, 800083a sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80007fc: 2300 movs r3, #0 80007fe: 9307 str r3, [sp, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000800: 9309 str r3, [sp, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 8000802: a907 add r1, sp, #28 8000804: 4811 ldr r0, [pc, #68] @ (800084c ) 8000806: f005 fc09 bl 800601c 800080a: b9c0 cbnz r0, 800083e sConfigOC.OCMode = TIM_OCMODE_PWM1; 800080c: 2360 movs r3, #96 @ 0x60 800080e: 9300 str r3, [sp, #0] sConfigOC.Pulse = 0; 8000810: 2200 movs r2, #0 8000812: 9201 str r2, [sp, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8000814: 9202 str r2, [sp, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8000816: 9204 str r2, [sp, #16] if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8000818: 4669 mov r1, sp 800081a: 480c ldr r0, [pc, #48] @ (800084c ) 800081c: f005 fa06 bl 8005c2c 8000820: b978 cbnz r0, 8000842 if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8000822: 2204 movs r2, #4 8000824: 4669 mov r1, sp 8000826: 4809 ldr r0, [pc, #36] @ (800084c ) 8000828: f005 fa00 bl 8005c2c 800082c: b958 cbnz r0, 8000846 HAL_TIM_MspPostInit(&htim4); 800082e: 4807 ldr r0, [pc, #28] @ (800084c ) 8000830: f002 fc32 bl 8003098 } 8000834: b00b add sp, #44 @ 0x2c 8000836: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 800083a: f7ff fe39 bl 80004b0 Error_Handler(); 800083e: f7ff fe37 bl 80004b0 Error_Handler(); 8000842: f7ff fe35 bl 80004b0 Error_Handler(); 8000846: f7ff fe33 bl 80004b0 800084a: bf00 nop 800084c: 200000c4 .word 0x200000c4 8000850: 40000800 .word 0x40000800 08000854 : { 8000854: b500 push {lr} 8000856: b089 sub sp, #36 @ 0x24 TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000858: 2300 movs r3, #0 800085a: 9305 str r3, [sp, #20] 800085c: 9306 str r3, [sp, #24] 800085e: 9307 str r3, [sp, #28] TIM_IC_InitTypeDef sConfigIC = {0}; 8000860: 9301 str r3, [sp, #4] 8000862: 9302 str r3, [sp, #8] 8000864: 9303 str r3, [sp, #12] 8000866: 9304 str r3, [sp, #16] htim8.Instance = TIM8; 8000868: 4819 ldr r0, [pc, #100] @ (80008d0 ) 800086a: 4a1a ldr r2, [pc, #104] @ (80008d4 ) 800086c: 6002 str r2, [r0, #0] htim8.Init.Prescaler = 0; 800086e: 6043 str r3, [r0, #4] htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 8000870: 6083 str r3, [r0, #8] htim8.Init.Period = 65535; 8000872: f64f 72ff movw r2, #65535 @ 0xffff 8000876: 60c2 str r2, [r0, #12] htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000878: 6103 str r3, [r0, #16] htim8.Init.RepetitionCounter = 0; 800087a: 6143 str r3, [r0, #20] htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800087c: 6183 str r3, [r0, #24] if (HAL_TIM_IC_Init(&htim8) != HAL_OK) 800087e: f005 f95b bl 8005b38 8000882: b9e8 cbnz r0, 80008c0 sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000884: 2300 movs r3, #0 8000886: 9305 str r3, [sp, #20] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000888: 9306 str r3, [sp, #24] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800088a: 9307 str r3, [sp, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 800088c: a905 add r1, sp, #20 800088e: 4810 ldr r0, [pc, #64] @ (80008d0 ) 8000890: f005 fbc4 bl 800601c 8000894: b9b0 cbnz r0, 80008c4 sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 8000896: 2200 movs r2, #0 8000898: 9201 str r2, [sp, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 800089a: 2301 movs r3, #1 800089c: 9302 str r3, [sp, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 800089e: 9203 str r2, [sp, #12] sConfigIC.ICFilter = 0; 80008a0: 9204 str r2, [sp, #16] if (HAL_TIM_IC_ConfigChannel(&htim8, &sConfigIC, TIM_CHANNEL_1) != HAL_OK) 80008a2: a901 add r1, sp, #4 80008a4: 480a ldr r0, [pc, #40] @ (80008d0 ) 80008a6: f005 faa9 bl 8005dfc 80008aa: b968 cbnz r0, 80008c8 if (HAL_TIM_IC_ConfigChannel(&htim8, &sConfigIC, TIM_CHANNEL_2) != HAL_OK) 80008ac: 2204 movs r2, #4 80008ae: eb0d 0102 add.w r1, sp, r2 80008b2: 4807 ldr r0, [pc, #28] @ (80008d0 ) 80008b4: f005 faa2 bl 8005dfc 80008b8: b940 cbnz r0, 80008cc } 80008ba: b009 add sp, #36 @ 0x24 80008bc: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 80008c0: f7ff fdf6 bl 80004b0 Error_Handler(); 80008c4: f7ff fdf4 bl 80004b0 Error_Handler(); 80008c8: f7ff fdf2 bl 80004b0 Error_Handler(); 80008cc: f7ff fdf0 bl 80004b0 80008d0: 2000002c .word 0x2000002c 80008d4: 40010400 .word 0x40010400 080008d8 : { 80008d8: b500 push {lr} 80008da: b085 sub sp, #20 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80008dc: 2300 movs r3, #0 80008de: 9301 str r3, [sp, #4] 80008e0: 9302 str r3, [sp, #8] 80008e2: 9303 str r3, [sp, #12] htim6.Instance = TIM6; 80008e4: 480d ldr r0, [pc, #52] @ (800091c ) 80008e6: 4a0e ldr r2, [pc, #56] @ (8000920 ) 80008e8: 6002 str r2, [r0, #0] htim6.Init.Prescaler = 2; 80008ea: 2202 movs r2, #2 80008ec: 6042 str r2, [r0, #4] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 80008ee: 6083 str r3, [r0, #8] htim6.Init.Period = 48000; 80008f0: f64b 3280 movw r2, #48000 @ 0xbb80 80008f4: 60c2 str r2, [r0, #12] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80008f6: 6183 str r3, [r0, #24] if (HAL_TIM_Base_Init(&htim6) != HAL_OK) 80008f8: f005 f8be bl 8005a78 80008fc: b950 cbnz r0, 8000914 sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80008fe: 2300 movs r3, #0 8000900: 9301 str r3, [sp, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000902: 9303 str r3, [sp, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) 8000904: a901 add r1, sp, #4 8000906: 4805 ldr r0, [pc, #20] @ (800091c ) 8000908: f005 fb88 bl 800601c 800090c: b920 cbnz r0, 8000918 } 800090e: b005 add sp, #20 8000910: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8000914: f7ff fdcc bl 80004b0 Error_Handler(); 8000918: f7ff fdca bl 80004b0 800091c: 20000078 .word 0x20000078 8000920: 40001000 .word 0x40001000 08000924 : { 8000924: b500 push {lr} 8000926: b09d sub sp, #116 @ 0x74 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000928: 224c movs r2, #76 @ 0x4c 800092a: 2100 movs r1, #0 800092c: a809 add r0, sp, #36 @ 0x24 800092e: f005 fcd2 bl 80062d6 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000932: 2220 movs r2, #32 8000934: 2100 movs r1, #0 8000936: a801 add r0, sp, #4 8000938: f005 fccd bl 80062d6 RCC->CKGAENR = 0xFFFFFFFF; 800093c: 4b25 ldr r3, [pc, #148] @ (80009d4 ) 800093e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000942: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000946: 2002 movs r0, #2 8000948: f002 fc28 bl 800319c __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 800094c: 2300 movs r3, #0 800094e: 9300 str r3, [sp, #0] 8000950: 4a21 ldr r2, [pc, #132] @ (80009d8 ) 8000952: 6993 ldr r3, [r2, #24] 8000954: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000958: f443 4300 orr.w r3, r3, #32768 @ 0x8000 800095c: 6193 str r3, [r2, #24] 800095e: 6993 ldr r3, [r2, #24] 8000960: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000964: 9300 str r3, [sp, #0] 8000966: 9b00 ldr r3, [sp, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000968: 4b1b ldr r3, [pc, #108] @ (80009d8 ) 800096a: 699b ldr r3, [r3, #24] 800096c: f413 5f00 tst.w r3, #8192 @ 0x2000 8000970: d0fa beq.n 8000968 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000972: 2301 movs r3, #1 8000974: 9309 str r3, [sp, #36] @ 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000976: f44f 3380 mov.w r3, #65536 @ 0x10000 800097a: 930a str r3, [sp, #40] @ 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800097c: 2302 movs r3, #2 800097e: 9312 str r3, [sp, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000980: 9313 str r3, [sp, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 2; 8000982: 9314 str r3, [sp, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 32; 8000984: 2220 movs r2, #32 8000986: 9215 str r2, [sp, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 8000988: 9316 str r3, [sp, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 3; 800098a: 2203 movs r2, #3 800098c: 9217 str r2, [sp, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 800098e: 9318 str r3, [sp, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; 8000990: 230c movs r3, #12 8000992: 9319 str r3, [sp, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000994: 2300 movs r3, #0 8000996: 931a str r3, [sp, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000998: 931b str r3, [sp, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800099a: a809 add r0, sp, #36 @ 0x24 800099c: f002 fc28 bl 80031f0 80009a0: b998 cbnz r0, 80009ca RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80009a2: 233f movs r3, #63 @ 0x3f 80009a4: 9301 str r3, [sp, #4] RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80009a6: 2303 movs r3, #3 80009a8: 9302 str r3, [sp, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80009aa: 2300 movs r3, #0 80009ac: 9303 str r3, [sp, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 80009ae: 2208 movs r2, #8 80009b0: 9204 str r2, [sp, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; 80009b2: 9305 str r3, [sp, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; 80009b4: 9306 str r3, [sp, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; 80009b6: 9307 str r3, [sp, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; 80009b8: 9308 str r3, [sp, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80009ba: 2102 movs r1, #2 80009bc: a801 add r0, sp, #4 80009be: f003 f843 bl 8003a48 80009c2: b920 cbnz r0, 80009ce } 80009c4: b01d add sp, #116 @ 0x74 80009c6: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 80009ca: f7ff fd71 bl 80004b0 Error_Handler(); 80009ce: f7ff fd6f bl 80004b0 80009d2: bf00 nop 80009d4: 58024400 .word 0x58024400 80009d8: 58024800 .word 0x58024800 080009dc
: { 80009dc: b508 push {r3, lr} MPU_Config(); 80009de: f7ff fc85 bl 80002ec HAL_Init(); 80009e2: f000 f881 bl 8000ae8 SystemClock_Config(); 80009e6: f7ff ff9d bl 8000924 MX_GPIO_Init(); 80009ea: f7ff fca9 bl 8000340 MX_DMA_Init(); 80009ee: f7ff fd43 bl 8000478 MX_ADC1_Init(); 80009f2: f7ff fd5f bl 80004b4 MX_FDCAN1_Init(); 80009f6: f7ff fdb1 bl 800055c MX_FDCAN2_Init(); 80009fa: f7ff fddf bl 80005bc MX_TIM1_Init(); 80009fe: f7ff fe0d bl 800061c MX_TIM3_Init(); 8000a02: f7ff fe9b bl 800073c MX_TIM4_Init(); 8000a06: f7ff fedf bl 80007c8 MX_TIM8_Init(); 8000a0a: f7ff ff23 bl 8000854 MX_TIM6_Init(); 8000a0e: f7ff ff63 bl 80008d8 HAL_GPIO_WritePin(STATUS_R_GPIO_Port, STATUS_R_Pin, GPIO_PIN_SET); 8000a12: 4c20 ldr r4, [pc, #128] @ (8000a94 ) 8000a14: 2201 movs r2, #1 8000a16: f44f 4180 mov.w r1, #16384 @ 0x4000 8000a1a: 4620 mov r0, r4 8000a1c: f002 f94e bl 8002cbc HAL_Delay(500); 8000a20: f44f 70fa mov.w r0, #500 @ 0x1f4 8000a24: f000 f8a0 bl 8000b68 HAL_GPIO_WritePin(STATUS_R_GPIO_Port, STATUS_R_Pin, GPIO_PIN_RESET); 8000a28: 2200 movs r2, #0 8000a2a: f44f 4180 mov.w r1, #16384 @ 0x4000 8000a2e: 4620 mov r0, r4 8000a30: f002 f944 bl 8002cbc HAL_Delay(500); 8000a34: f44f 70fa mov.w r0, #500 @ 0x1f4 8000a38: f000 f896 bl 8000b68 HAL_GPIO_WritePin(STATUS_G_GPIO_Port, STATUS_G_Pin, GPIO_PIN_SET); 8000a3c: 2201 movs r2, #1 8000a3e: f44f 4100 mov.w r1, #32768 @ 0x8000 8000a42: 4620 mov r0, r4 8000a44: f002 f93a bl 8002cbc HAL_Delay(500); 8000a48: f44f 70fa mov.w r0, #500 @ 0x1f4 8000a4c: f000 f88c bl 8000b68 HAL_GPIO_WritePin(STATUS_G_GPIO_Port, STATUS_G_Pin, GPIO_PIN_RESET); 8000a50: 2200 movs r2, #0 8000a52: f44f 4100 mov.w r1, #32768 @ 0x8000 8000a56: 4620 mov r0, r4 8000a58: f002 f930 bl 8002cbc HAL_Delay(500); 8000a5c: f44f 70fa mov.w r0, #500 @ 0x1f4 8000a60: f000 f882 bl 8000b68 HAL_GPIO_WritePin(STATUS_B_GPIO_Port, STATUS_B_Pin, GPIO_PIN_SET); 8000a64: f5a4 6480 sub.w r4, r4, #1024 @ 0x400 8000a68: 2201 movs r2, #1 8000a6a: f44f 5180 mov.w r1, #4096 @ 0x1000 8000a6e: 4620 mov r0, r4 8000a70: f002 f924 bl 8002cbc HAL_Delay(500); 8000a74: f44f 70fa mov.w r0, #500 @ 0x1f4 8000a78: f000 f876 bl 8000b68 HAL_GPIO_WritePin(STATUS_B_GPIO_Port, STATUS_B_Pin, GPIO_PIN_RESET); 8000a7c: 2200 movs r2, #0 8000a7e: f44f 5180 mov.w r1, #4096 @ 0x1000 8000a82: 4620 mov r0, r4 8000a84: f002 f91a bl 8002cbc HAL_Delay(500); 8000a88: f44f 70fa mov.w r0, #500 @ 0x1f4 8000a8c: f000 f86c bl 8000b68 while (1) 8000a90: e7bf b.n 8000a12 8000a92: bf00 nop 8000a94: 58020400 .word 0x58020400 08000a98 : * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if((uint32_t)uwTickFreq == 0UL) 8000a98: 4b10 ldr r3, [pc, #64] @ (8000adc ) 8000a9a: 781b ldrb r3, [r3, #0] 8000a9c: b90b cbnz r3, 8000aa2 { return HAL_ERROR; 8000a9e: 2001 movs r0, #1 return HAL_ERROR; } /* Return function status */ return HAL_OK; } 8000aa0: 4770 bx lr { 8000aa2: b510 push {r4, lr} 8000aa4: 4604 mov r4, r0 if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) 8000aa6: f44f 707a mov.w r0, #1000 @ 0x3e8 8000aaa: fbb0 f3f3 udiv r3, r0, r3 8000aae: 4a0c ldr r2, [pc, #48] @ (8000ae0 ) 8000ab0: 6810 ldr r0, [r2, #0] 8000ab2: fbb0 f0f3 udiv r0, r0, r3 8000ab6: f000 fe85 bl 80017c4 8000aba: b968 cbnz r0, 8000ad8 if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000abc: 2c0f cmp r4, #15 8000abe: d901 bls.n 8000ac4 return HAL_ERROR; 8000ac0: 2001 movs r0, #1 8000ac2: e00a b.n 8000ada HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000ac4: 2200 movs r2, #0 8000ac6: 4621 mov r1, r4 8000ac8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8000acc: f000 fe66 bl 800179c uwTickPrio = TickPriority; 8000ad0: 4b04 ldr r3, [pc, #16] @ (8000ae4 ) 8000ad2: 601c str r4, [r3, #0] return HAL_OK; 8000ad4: 2000 movs r0, #0 8000ad6: e000 b.n 8000ada return HAL_ERROR; 8000ad8: 2001 movs r0, #1 } 8000ada: bd10 pop {r4, pc} 8000adc: 20000000 .word 0x20000000 8000ae0: 2000000c .word 0x2000000c 8000ae4: 20000004 .word 0x20000004 08000ae8 : { 8000ae8: b510 push {r4, lr} HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000aea: 2003 movs r0, #3 8000aec: f000 fe44 bl 8001778 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); 8000af0: f002 feae bl 8003850 8000af4: 490f ldr r1, [pc, #60] @ (8000b34 ) 8000af6: 698b ldr r3, [r1, #24] 8000af8: f3c3 2303 ubfx r3, r3, #8, #4 8000afc: 4a0e ldr r2, [pc, #56] @ (8000b38 ) 8000afe: 5cd3 ldrb r3, [r2, r3] 8000b00: f003 031f and.w r3, r3, #31 8000b04: 40d8 lsrs r0, r3 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 8000b06: 698b ldr r3, [r1, #24] 8000b08: f003 030f and.w r3, r3, #15 8000b0c: 5cd3 ldrb r3, [r2, r3] 8000b0e: f003 031f and.w r3, r3, #31 8000b12: fa20 f303 lsr.w r3, r0, r3 8000b16: 4a09 ldr r2, [pc, #36] @ (8000b3c ) 8000b18: 6013 str r3, [r2, #0] SystemCoreClock = common_system_clock; 8000b1a: 4b09 ldr r3, [pc, #36] @ (8000b40 ) 8000b1c: 6018 str r0, [r3, #0] if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8000b1e: 200f movs r0, #15 8000b20: f7ff ffba bl 8000a98 8000b24: b110 cbz r0, 8000b2c return HAL_ERROR; 8000b26: 2401 movs r4, #1 } 8000b28: 4620 mov r0, r4 8000b2a: bd10 pop {r4, pc} 8000b2c: 4604 mov r4, r0 HAL_MspInit(); 8000b2e: f002 f8cb bl 8002cc8 return HAL_OK; 8000b32: e7f9 b.n 8000b28 8000b34: 58024400 .word 0x58024400 8000b38: 080063b8 .word 0x080063b8 8000b3c: 20000008 .word 0x20000008 8000b40: 2000000c .word 0x2000000c 08000b44 : * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += (uint32_t)uwTickFreq; 8000b44: 4b03 ldr r3, [pc, #12] @ (8000b54 ) 8000b46: 781b ldrb r3, [r3, #0] 8000b48: 4a03 ldr r2, [pc, #12] @ (8000b58 ) 8000b4a: 6811 ldr r1, [r2, #0] 8000b4c: 440b add r3, r1 8000b4e: 6013 str r3, [r2, #0] } 8000b50: 4770 bx lr 8000b52: bf00 nop 8000b54: 20000000 .word 0x20000000 8000b58: 200003c4 .word 0x200003c4 08000b5c : * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; 8000b5c: 4b01 ldr r3, [pc, #4] @ (8000b64 ) 8000b5e: 6818 ldr r0, [r3, #0] } 8000b60: 4770 bx lr 8000b62: bf00 nop 8000b64: 200003c4 .word 0x200003c4 08000b68 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000b68: b538 push {r3, r4, r5, lr} 8000b6a: 4604 mov r4, r0 uint32_t tickstart = HAL_GetTick(); 8000b6c: f7ff fff6 bl 8000b5c 8000b70: 4605 mov r5, r0 uint32_t wait = Delay; /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8000b72: f1b4 3fff cmp.w r4, #4294967295 @ 0xffffffff 8000b76: d002 beq.n 8000b7e { wait += (uint32_t)(uwTickFreq); 8000b78: 4b04 ldr r3, [pc, #16] @ (8000b8c ) 8000b7a: 781b ldrb r3, [r3, #0] 8000b7c: 441c add r4, r3 } while ((HAL_GetTick() - tickstart) < wait) 8000b7e: f7ff ffed bl 8000b5c 8000b82: 1b40 subs r0, r0, r5 8000b84: 42a0 cmp r0, r4 8000b86: d3fa bcc.n 8000b7e { } } 8000b88: bd38 pop {r3, r4, r5, pc} 8000b8a: bf00 nop 8000b8c: 20000000 .word 0x20000000 08000b90 : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8000b90: b410 push {r4} /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 8000b92: 3030 adds r0, #48 @ 0x30 8000b94: 0a0b lsrs r3, r1, #8 8000b96: 009b lsls r3, r3, #2 8000b98: f003 030c and.w r3, r3, #12 MODIFY_REG(*preg, 8000b9c: 58c4 ldr r4, [r0, r3] 8000b9e: f001 011f and.w r1, r1, #31 8000ba2: f04f 0c1f mov.w ip, #31 8000ba6: fa0c fc01 lsl.w ip, ip, r1 8000baa: ea24 0c0c bic.w ip, r4, ip 8000bae: f3c2 6284 ubfx r2, r2, #26, #5 8000bb2: 408a lsls r2, r1 8000bb4: ea4c 0202 orr.w r2, ip, r2 8000bb8: 50c2 str r2, [r0, r3] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8000bba: f85d 4b04 ldr.w r4, [sp], #4 8000bbe: 4770 bx lr 08000bc0 : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 8000bc0: b410 push {r4} /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8000bc2: 3014 adds r0, #20 8000bc4: 0e4b lsrs r3, r1, #25 8000bc6: 009b lsls r3, r3, #2 8000bc8: f003 0304 and.w r3, r3, #4 MODIFY_REG(*preg, 8000bcc: 58c4 ldr r4, [r0, r3] 8000bce: f3c1 5104 ubfx r1, r1, #20, #5 8000bd2: f04f 0c07 mov.w ip, #7 8000bd6: fa0c fc01 lsl.w ip, ip, r1 8000bda: ea24 0c0c bic.w ip, r4, ip 8000bde: 408a lsls r2, r1 8000be0: ea4c 0202 orr.w r2, ip, r2 8000be4: 50c2 str r2, [r0, r3] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 8000be6: f85d 4b04 ldr.w r4, [sp], #4 8000bea: 4770 bx lr 08000bec : ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)); 8000bec: f3c1 0313 ubfx r3, r1, #0, #20 8000bf0: b93b cbnz r3, 8000c02 8000bf2: f3c1 6184 ubfx r1, r1, #26, #5 8000bf6: 2201 movs r2, #1 8000bf8: 408a lsls r2, r1 8000bfa: 69c3 ldr r3, [r0, #28] 8000bfc: 4313 orrs r3, r2 8000bfe: 61c3 str r3, [r0, #28] } 8000c00: 4770 bx lr uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8000c02: fa91 f1a1 rbit r1, r1 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8000c06: b131 cbz r1, 8000c16 { return 32U; } return __builtin_clz(value); 8000c08: fab1 f181 clz r1, r1 ADCx->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)); 8000c0c: f001 011f and.w r1, r1, #31 8000c10: 2201 movs r2, #1 8000c12: 408a lsls r2, r1 8000c14: e7f1 b.n 8000bfa return 32U; 8000c16: 2120 movs r1, #32 8000c18: e7f8 b.n 8000c0c 08000c1a : UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } 8000c1a: 4770 bx lr 08000c1c : UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } 8000c1c: 4770 bx lr 08000c1e : UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 8000c1e: 4770 bx lr 08000c20 : { 8000c20: b5f8 push {r3, r4, r5, r6, r7, lr} 8000c22: 4604 mov r4, r0 uint32_t tmp_isr = hadc->Instance->ISR; 8000c24: 6803 ldr r3, [r0, #0] 8000c26: 681f ldr r7, [r3, #0] uint32_t tmp_ier = hadc->Instance->IER; 8000c28: 685d ldr r5, [r3, #4] * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8000c2a: 4b9a ldr r3, [pc, #616] @ (8000e94 ) 8000c2c: 689e ldr r6, [r3, #8] 8000c2e: f006 061f and.w r6, r6, #31 if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) 8000c32: f017 0f02 tst.w r7, #2 8000c36: d010 beq.n 8000c5a 8000c38: f015 0f02 tst.w r5, #2 8000c3c: d00d beq.n 8000c5a if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8000c3e: 6d43 ldr r3, [r0, #84] @ 0x54 8000c40: f013 0f10 tst.w r3, #16 8000c44: d103 bne.n 8000c4e SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); 8000c46: 6d43 ldr r3, [r0, #84] @ 0x54 8000c48: f443 6300 orr.w r3, r3, #2048 @ 0x800 8000c4c: 6543 str r3, [r0, #84] @ 0x54 HAL_ADCEx_EndOfSamplingCallback(hadc); 8000c4e: 4620 mov r0, r4 8000c50: f000 fcca bl 80015e8 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); 8000c54: 6823 ldr r3, [r4, #0] 8000c56: 2202 movs r2, #2 8000c58: 601a str r2, [r3, #0] if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || 8000c5a: f017 0f04 tst.w r7, #4 8000c5e: d002 beq.n 8000c66 8000c60: f015 0f04 tst.w r5, #4 8000c64: d105 bne.n 8000c72 8000c66: f017 0f08 tst.w r7, #8 8000c6a: d04d beq.n 8000d08 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) 8000c6c: f015 0f08 tst.w r5, #8 8000c70: d04a beq.n 8000d08 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8000c72: 6d63 ldr r3, [r4, #84] @ 0x54 8000c74: f013 0f10 tst.w r3, #16 8000c78: d103 bne.n 8000c82 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8000c7a: 6d63 ldr r3, [r4, #84] @ 0x54 8000c7c: f443 7300 orr.w r3, r3, #512 @ 0x200 8000c80: 6563 str r3, [r4, #84] @ 0x54 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 8000c82: 6823 ldr r3, [r4, #0] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8000c84: 68da ldr r2, [r3, #12] 8000c86: f412 6f40 tst.w r2, #3072 @ 0xc00 8000c8a: d137 bne.n 8000cfc if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8000c8c: 4a82 ldr r2, [pc, #520] @ (8000e98 ) 8000c8e: 4293 cmp r3, r2 8000c90: d027 beq.n 8000ce2 8000c92: 461a mov r2, r3 8000c94: 4293 cmp r3, r2 8000c96: d007 beq.n 8000ca8 8000c98: 2e09 cmp r6, #9 8000c9a: d825 bhi.n 8000ce8 8000c9c: f240 2121 movw r1, #545 @ 0x221 8000ca0: 40f1 lsrs r1, r6 8000ca2: f011 0f01 tst.w r1, #1 8000ca6: d01f beq.n 8000ce8 tmp_cfgr = READ_REG(hadc->Instance->CFGR); 8000ca8: 68da ldr r2, [r3, #12] if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) 8000caa: f412 5f00 tst.w r2, #8192 @ 0x2000 8000cae: d125 bne.n 8000cfc if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) 8000cb0: 681a ldr r2, [r3, #0] 8000cb2: f012 0f08 tst.w r2, #8 8000cb6: d021 beq.n 8000cfc * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8000cb8: 689a ldr r2, [r3, #8] 8000cba: f012 0f04 tst.w r2, #4 8000cbe: d115 bne.n 8000cec __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); 8000cc0: 685a ldr r2, [r3, #4] 8000cc2: f022 020c bic.w r2, r2, #12 8000cc6: 605a str r2, [r3, #4] CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8000cc8: 6d63 ldr r3, [r4, #84] @ 0x54 8000cca: f423 7380 bic.w r3, r3, #256 @ 0x100 8000cce: 6563 str r3, [r4, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8000cd0: 6d63 ldr r3, [r4, #84] @ 0x54 8000cd2: f413 5f80 tst.w r3, #4096 @ 0x1000 8000cd6: d111 bne.n 8000cfc SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8000cd8: 6d63 ldr r3, [r4, #84] @ 0x54 8000cda: f043 0301 orr.w r3, r3, #1 8000cde: 6563 str r3, [r4, #84] @ 0x54 8000ce0: e00c b.n 8000cfc if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8000ce2: f5a2 7280 sub.w r2, r2, #256 @ 0x100 8000ce6: e7d5 b.n 8000c94 tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 8000ce8: 68d2 ldr r2, [r2, #12] 8000cea: e7de b.n 8000caa SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000cec: 6d63 ldr r3, [r4, #84] @ 0x54 8000cee: f043 0310 orr.w r3, r3, #16 8000cf2: 6563 str r3, [r4, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000cf4: 6da3 ldr r3, [r4, #88] @ 0x58 8000cf6: f043 0301 orr.w r3, r3, #1 8000cfa: 65a3 str r3, [r4, #88] @ 0x58 HAL_ADC_ConvCpltCallback(hadc); 8000cfc: 4620 mov r0, r4 8000cfe: f7ff ff8c bl 8000c1a __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); 8000d02: 6823 ldr r3, [r4, #0] 8000d04: 220c movs r2, #12 8000d06: 601a str r2, [r3, #0] if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || 8000d08: f017 0f20 tst.w r7, #32 8000d0c: d002 beq.n 8000d14 8000d0e: f015 0f20 tst.w r5, #32 8000d12: d105 bne.n 8000d20 8000d14: f017 0f40 tst.w r7, #64 @ 0x40 8000d18: d063 beq.n 8000de2 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) 8000d1a: f015 0f40 tst.w r5, #64 @ 0x40 8000d1e: d060 beq.n 8000de2 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8000d20: 6d63 ldr r3, [r4, #84] @ 0x54 8000d22: f013 0f10 tst.w r3, #16 8000d26: d103 bne.n 8000d30 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 8000d28: 6d63 ldr r3, [r4, #84] @ 0x54 8000d2a: f443 5300 orr.w r3, r3, #8192 @ 0x2000 8000d2e: 6563 str r3, [r4, #84] @ 0x54 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); 8000d30: 6823 ldr r3, [r4, #0] return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); 8000d32: 6cda ldr r2, [r3, #76] @ 0x4c 8000d34: f412 7fc0 tst.w r2, #384 @ 0x180 8000d38: d119 bne.n 8000d6e 8000d3a: 2101 movs r1, #1 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8000d3c: 68da ldr r2, [r3, #12] 8000d3e: f412 6f40 tst.w r2, #3072 @ 0xc00 8000d42: d116 bne.n 8000d72 8000d44: 2001 movs r0, #1 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8000d46: 4a54 ldr r2, [pc, #336] @ (8000e98 ) 8000d48: 4293 cmp r3, r2 8000d4a: d014 beq.n 8000d76 8000d4c: 461a mov r2, r3 8000d4e: 4293 cmp r3, r2 8000d50: d014 beq.n 8000d7c || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) 8000d52: 2e06 cmp r6, #6 8000d54: bf14 ite ne 8000d56: f04f 0c00 movne.w ip, #0 8000d5a: f04f 0c01 moveq.w ip, #1 8000d5e: b16e cbz r6, 8000d7c 8000d60: f1bc 0f00 cmp.w ip, #0 8000d64: d10a bne.n 8000d7c || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) 8000d66: 2e07 cmp r6, #7 8000d68: d008 beq.n 8000d7c tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 8000d6a: 68d2 ldr r2, [r2, #12] 8000d6c: e007 b.n 8000d7e return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); 8000d6e: 2100 movs r1, #0 8000d70: e7e4 b.n 8000d3c return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8000d72: 2000 movs r0, #0 8000d74: e7e7 b.n 8000d46 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8000d76: f5a2 7280 sub.w r2, r2, #256 @ 0x100 8000d7a: e7e8 b.n 8000d4e tmp_cfgr = READ_REG(hadc->Instance->CFGR); 8000d7c: 68da ldr r2, [r3, #12] if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) 8000d7e: b351 cbz r1, 8000dd6 if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || 8000d80: f012 7f00 tst.w r2, #33554432 @ 0x2000000 8000d84: d003 beq.n 8000d8e 8000d86: b330 cbz r0, 8000dd6 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && 8000d88: f412 5f00 tst.w r2, #8192 @ 0x2000 8000d8c: d123 bne.n 8000dd6 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) 8000d8e: 6819 ldr r1, [r3, #0] 8000d90: f011 0f40 tst.w r1, #64 @ 0x40 8000d94: d01f beq.n 8000dd6 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) 8000d96: f412 1f00 tst.w r2, #2097152 @ 0x200000 8000d9a: d11c bne.n 8000dd6 * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8000d9c: 689a ldr r2, [r3, #8] 8000d9e: f012 0f08 tst.w r2, #8 8000da2: d110 bne.n 8000dc6 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); 8000da4: 685a ldr r2, [r3, #4] 8000da6: f022 0260 bic.w r2, r2, #96 @ 0x60 8000daa: 605a str r2, [r3, #4] CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 8000dac: 6d63 ldr r3, [r4, #84] @ 0x54 8000dae: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8000db2: 6563 str r3, [r4, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) 8000db4: 6d63 ldr r3, [r4, #84] @ 0x54 8000db6: f413 7f80 tst.w r3, #256 @ 0x100 8000dba: d10c bne.n 8000dd6 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8000dbc: 6d63 ldr r3, [r4, #84] @ 0x54 8000dbe: f043 0301 orr.w r3, r3, #1 8000dc2: 6563 str r3, [r4, #84] @ 0x54 8000dc4: e007 b.n 8000dd6 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8000dc6: 6d63 ldr r3, [r4, #84] @ 0x54 8000dc8: f043 0310 orr.w r3, r3, #16 8000dcc: 6563 str r3, [r4, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8000dce: 6da3 ldr r3, [r4, #88] @ 0x58 8000dd0: f043 0301 orr.w r3, r3, #1 8000dd4: 65a3 str r3, [r4, #88] @ 0x58 HAL_ADCEx_InjectedConvCpltCallback(hadc); 8000dd6: 4620 mov r0, r4 8000dd8: f000 fc02 bl 80015e0 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); 8000ddc: 6823 ldr r3, [r4, #0] 8000dde: 2260 movs r2, #96 @ 0x60 8000de0: 601a str r2, [r3, #0] if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) 8000de2: f017 0f80 tst.w r7, #128 @ 0x80 8000de6: d002 beq.n 8000dee 8000de8: f015 0f80 tst.w r5, #128 @ 0x80 8000dec: d12f bne.n 8000e4e if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) 8000dee: f417 7f80 tst.w r7, #256 @ 0x100 8000df2: d002 beq.n 8000dfa 8000df4: f415 7f80 tst.w r5, #256 @ 0x100 8000df8: d134 bne.n 8000e64 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) 8000dfa: f417 7f00 tst.w r7, #512 @ 0x200 8000dfe: d002 beq.n 8000e06 8000e00: f415 7f00 tst.w r5, #512 @ 0x200 8000e04: d13a bne.n 8000e7c if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) 8000e06: f017 0f10 tst.w r7, #16 8000e0a: d019 beq.n 8000e40 8000e0c: f015 0f10 tst.w r5, #16 8000e10: d016 beq.n 8000e40 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) 8000e12: 6b23 ldr r3, [r4, #48] @ 0x30 8000e14: b133 cbz r3, 8000e24 if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) 8000e16: 2e00 cmp r6, #0 8000e18: d040 beq.n 8000e9c return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF)); 8000e1a: 4b1e ldr r3, [pc, #120] @ (8000e94 ) 8000e1c: 689b ldr r3, [r3, #8] if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) 8000e1e: f413 4f40 tst.w r3, #49152 @ 0xc000 8000e22: d00a beq.n 8000e3a SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); 8000e24: 6d63 ldr r3, [r4, #84] @ 0x54 8000e26: f443 6380 orr.w r3, r3, #1024 @ 0x400 8000e2a: 6563 str r3, [r4, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); 8000e2c: 6da3 ldr r3, [r4, #88] @ 0x58 8000e2e: f043 0302 orr.w r3, r3, #2 8000e32: 65a3 str r3, [r4, #88] @ 0x58 HAL_ADC_ErrorCallback(hadc); 8000e34: 4620 mov r0, r4 8000e36: f7ff fef2 bl 8000c1e __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 8000e3a: 6823 ldr r3, [r4, #0] 8000e3c: 2210 movs r2, #16 8000e3e: 601a str r2, [r3, #0] if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) 8000e40: f417 6f80 tst.w r7, #1024 @ 0x400 8000e44: d002 beq.n 8000e4c 8000e46: f415 6f80 tst.w r5, #1024 @ 0x400 8000e4a: d12d bne.n 8000ea8 } 8000e4c: bdf8 pop {r3, r4, r5, r6, r7, pc} SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 8000e4e: 6d63 ldr r3, [r4, #84] @ 0x54 8000e50: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000e54: 6563 str r3, [r4, #84] @ 0x54 HAL_ADC_LevelOutOfWindowCallback(hadc); 8000e56: 4620 mov r0, r4 8000e58: f7ff fee0 bl 8000c1c __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); 8000e5c: 6823 ldr r3, [r4, #0] 8000e5e: 2280 movs r2, #128 @ 0x80 8000e60: 601a str r2, [r3, #0] 8000e62: e7c4 b.n 8000dee SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); 8000e64: 6d63 ldr r3, [r4, #84] @ 0x54 8000e66: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000e6a: 6563 str r3, [r4, #84] @ 0x54 HAL_ADCEx_LevelOutOfWindow2Callback(hadc); 8000e6c: 4620 mov r0, r4 8000e6e: f000 fbb9 bl 80015e4 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); 8000e72: 6823 ldr r3, [r4, #0] 8000e74: f44f 7280 mov.w r2, #256 @ 0x100 8000e78: 601a str r2, [r3, #0] 8000e7a: e7be b.n 8000dfa SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); 8000e7c: 6d63 ldr r3, [r4, #84] @ 0x54 8000e7e: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8000e82: 6563 str r3, [r4, #84] @ 0x54 HAL_ADCEx_LevelOutOfWindow3Callback(hadc); 8000e84: 4620 mov r0, r4 8000e86: f000 fbae bl 80015e6 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); 8000e8a: 6823 ldr r3, [r4, #0] 8000e8c: f44f 7200 mov.w r2, #512 @ 0x200 8000e90: 601a str r2, [r3, #0] 8000e92: e7b8 b.n 8000e06 8000e94: 40022300 .word 0x40022300 8000e98: 40022100 .word 0x40022100 if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL) 8000e9c: 6823 ldr r3, [r4, #0] 8000e9e: 68db ldr r3, [r3, #12] 8000ea0: f013 0f03 tst.w r3, #3 8000ea4: d0c9 beq.n 8000e3a 8000ea6: e7bd b.n 8000e24 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); 8000ea8: 6d63 ldr r3, [r4, #84] @ 0x54 8000eaa: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000eae: 6563 str r3, [r4, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); 8000eb0: 6da3 ldr r3, [r4, #88] @ 0x58 8000eb2: f043 0308 orr.w r3, r3, #8 8000eb6: 65a3 str r3, [r4, #88] @ 0x58 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); 8000eb8: 6823 ldr r3, [r4, #0] 8000eba: f44f 6280 mov.w r2, #1024 @ 0x400 8000ebe: 601a str r2, [r3, #0] HAL_ADCEx_InjectedQueueOverflowCallback(hadc); 8000ec0: 4620 mov r0, r4 8000ec2: f000 fb8e bl 80015e2 } 8000ec6: e7c1 b.n 8000e4c 08000ec8 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 8000ec8: b5f0 push {r4, r5, r6, r7, lr} 8000eca: b083 sub sp, #12 HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 8000ecc: 2300 movs r3, #0 8000ece: 9301 str r3, [sp, #4] } #endif } /* Process locked */ __HAL_LOCK(hadc); 8000ed0: f890 3050 ldrb.w r3, [r0, #80] @ 0x50 8000ed4: 2b01 cmp r3, #1 8000ed6: f000 81fd beq.w 80012d4 8000eda: 4604 mov r4, r0 8000edc: 460d mov r5, r1 8000ede: 2301 movs r3, #1 8000ee0: f880 3050 strb.w r3, [r0, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8000ee4: 6802 ldr r2, [r0, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8000ee6: 6893 ldr r3, [r2, #8] 8000ee8: f013 0f04 tst.w r3, #4 8000eec: d009 beq.n 8000f02 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8000eee: 6d43 ldr r3, [r0, #84] @ 0x54 8000ef0: f043 0320 orr.w r3, r3, #32 8000ef4: 6543 str r3, [r0, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8000ef6: 2001 movs r0, #1 } /* Process unlocked */ __HAL_UNLOCK(hadc); 8000ef8: 2300 movs r3, #0 8000efa: f884 3050 strb.w r3, [r4, #80] @ 0x50 /* Return function status */ return tmp_hal_status; } 8000efe: b003 add sp, #12 8000f00: bdf0 pop {r4, r5, r6, r7, pc} if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 8000f02: 680b ldr r3, [r1, #0] 8000f04: 2b00 cmp r3, #0 8000f06: db0a blt.n 8000f1e hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 8000f08: f3c3 0113 ubfx r1, r3, #0, #20 8000f0c: 2900 cmp r1, #0 8000f0e: d13a bne.n 8000f86 8000f10: f3c3 6384 ubfx r3, r3, #26, #5 8000f14: 2101 movs r1, #1 8000f16: 4099 lsls r1, r3 8000f18: 69d3 ldr r3, [r2, #28] 8000f1a: 430b orrs r3, r1 8000f1c: 61d3 str r3, [r2, #28] LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 8000f1e: 682a ldr r2, [r5, #0] 8000f20: 6869 ldr r1, [r5, #4] 8000f22: 6820 ldr r0, [r4, #0] 8000f24: f7ff fe34 bl 8000b90 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8000f28: 6820 ldr r0, [r4, #0] 8000f2a: 6886 ldr r6, [r0, #8] 8000f2c: f016 0604 ands.w r6, r6, #4 8000f30: d000 beq.n 8000f34 8000f32: 2601 movs r6, #1 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8000f34: 6883 ldr r3, [r0, #8] 8000f36: f013 0f08 tst.w r3, #8 8000f3a: d100 bne.n 8000f3e if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8000f3c: b37e cbz r6, 8000f9e if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8000f3e: 6820 ldr r0, [r4, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8000f40: 6881 ldr r1, [r0, #8] 8000f42: f011 0101 ands.w r1, r1, #1 8000f46: f040 81c1 bne.w 80012cc LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 8000f4a: 682b ldr r3, [r5, #0] 8000f4c: 68ee ldr r6, [r5, #12] MODIFY_REG(ADCx->DIFSEL, 8000f4e: f8d0 20c0 ldr.w r2, [r0, #192] @ 0xc0 8000f52: f3c3 0c13 ubfx ip, r3, #0, #20 8000f56: ea22 020c bic.w r2, r2, ip 8000f5a: f006 0c18 and.w ip, r6, #24 8000f5e: 4e9b ldr r6, [pc, #620] @ (80011cc ) 8000f60: fa26 f60c lsr.w r6, r6, ip 8000f64: 4033 ands r3, r6 8000f66: f3c3 0313 ubfx r3, r3, #0, #20 8000f6a: 4313 orrs r3, r2 8000f6c: f8c0 30c0 str.w r3, [r0, #192] @ 0xc0 if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 8000f70: 68ea ldr r2, [r5, #12] 8000f72: 4b97 ldr r3, [pc, #604] @ (80011d0 ) 8000f74: 429a cmp r2, r3 8000f76: f000 808f beq.w 8001098 if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8000f7a: 682b ldr r3, [r5, #0] 8000f7c: 2b00 cmp r3, #0 8000f7e: f2c0 8106 blt.w 800118e HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8000f82: 2000 movs r0, #0 8000f84: e7b8 b.n 8000ef8 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8000f86: fa93 f3a3 rbit r3, r3 if (value == 0U) 8000f8a: b133 cbz r3, 8000f9a return __builtin_clz(value); 8000f8c: fab3 f383 clz r3, r3 hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 8000f90: f003 031f and.w r3, r3, #31 8000f94: 2101 movs r1, #1 8000f96: 4099 lsls r1, r3 8000f98: e7be b.n 8000f18 return 32U; 8000f9a: 2320 movs r3, #32 8000f9c: e7f8 b.n 8000f90 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 8000f9e: 68aa ldr r2, [r5, #8] 8000fa0: 6829 ldr r1, [r5, #0] 8000fa2: f7ff fe0d bl 8000bc0 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8000fa6: 6823 ldr r3, [r4, #0] 8000fa8: 68da ldr r2, [r3, #12] 8000faa: f012 0f10 tst.w r2, #16 8000fae: d131 bne.n 8001014 8000fb0: 696a ldr r2, [r5, #20] 8000fb2: 68d9 ldr r1, [r3, #12] 8000fb4: f3c1 0182 ubfx r1, r1, #2, #3 8000fb8: 0049 lsls r1, r1, #1 8000fba: 408a lsls r2, r1 if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 8000fbc: 692f ldr r7, [r5, #16] 8000fbe: 2f04 cmp r7, #4 8000fc0: d036 beq.n 8001030 LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 8000fc2: 6828 ldr r0, [r5, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8000fc4: 3360 adds r3, #96 @ 0x60 MODIFY_REG(*preg, 8000fc6: f853 1027 ldr.w r1, [r3, r7, lsl #2] 8000fca: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000 8000fce: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000 8000fd2: 4302 orrs r2, r0 8000fd4: 430a orrs r2, r1 8000fd6: f843 2027 str.w r2, [r3, r7, lsl #2] LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 8000fda: 6823 ldr r3, [r4, #0] 8000fdc: 6928 ldr r0, [r5, #16] 8000fde: 7e6a ldrb r2, [r5, #25] 8000fe0: 2a01 cmp r2, #1 8000fe2: d01f beq.n 8001024 8000fe4: 4632 mov r2, r6 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8000fe6: 3360 adds r3, #96 @ 0x60 MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8000fe8: f853 1020 ldr.w r1, [r3, r0, lsl #2] 8000fec: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 8000ff0: 430a orrs r2, r1 8000ff2: f843 2020 str.w r2, [r3, r0, lsl #2] LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 8000ff6: 6820 ldr r0, [r4, #0] 8000ff8: 6929 ldr r1, [r5, #16] 8000ffa: 7e2b ldrb r3, [r5, #24] 8000ffc: 2b01 cmp r3, #1 8000ffe: d014 beq.n 800102a MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 8001000: 6902 ldr r2, [r0, #16] 8001002: f422 42f0 bic.w r2, r2, #30720 @ 0x7800 8001006: f001 031f and.w r3, r1, #31 800100a: fa06 f303 lsl.w r3, r6, r3 800100e: 4313 orrs r3, r2 8001010: 6103 str r3, [r0, #16] } 8001012: e794 b.n 8000f3e tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8001014: 696a ldr r2, [r5, #20] 8001016: 68d9 ldr r1, [r3, #12] 8001018: 0889 lsrs r1, r1, #2 800101a: f001 0104 and.w r1, r1, #4 800101e: 0049 lsls r1, r1, #1 8001020: 408a lsls r2, r1 8001022: e7cb b.n 8000fbc LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 8001024: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 8001028: e7dd b.n 8000fe6 LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 800102a: f44f 6600 mov.w r6, #2048 @ 0x800 800102e: e7e7 b.n 8001000 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8001030: 6e1a ldr r2, [r3, #96] @ 0x60 8001032: f002 42f8 and.w r2, r2, #2080374784 @ 0x7c000000 8001036: 6829 ldr r1, [r5, #0] 8001038: ebb2 6f81 cmp.w r2, r1, lsl #26 800103c: d01d beq.n 800107a if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 800103e: 6822 ldr r2, [r4, #0] 8001040: 6e53 ldr r3, [r2, #100] @ 0x64 8001042: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000 8001046: 6829 ldr r1, [r5, #0] 8001048: ebb3 6f81 cmp.w r3, r1, lsl #26 800104c: d01a beq.n 8001084 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 800104e: 6822 ldr r2, [r4, #0] 8001050: 6e93 ldr r3, [r2, #104] @ 0x68 8001052: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000 8001056: 6829 ldr r1, [r5, #0] 8001058: ebb3 6f81 cmp.w r3, r1, lsl #26 800105c: d017 beq.n 800108e if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 800105e: 6822 ldr r2, [r4, #0] 8001060: 6ed3 ldr r3, [r2, #108] @ 0x6c 8001062: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000 8001066: 6829 ldr r1, [r5, #0] 8001068: ebb3 6f81 cmp.w r3, r1, lsl #26 800106c: f47f af67 bne.w 8000f3e CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8001070: 6ed3 ldr r3, [r2, #108] @ 0x6c 8001072: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8001076: 66d3 str r3, [r2, #108] @ 0x6c 8001078: e761 b.n 8000f3e CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 800107a: 6e1a ldr r2, [r3, #96] @ 0x60 800107c: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8001080: 661a str r2, [r3, #96] @ 0x60 8001082: e7dc b.n 800103e CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 8001084: 6e53 ldr r3, [r2, #100] @ 0x64 8001086: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 800108a: 6653 str r3, [r2, #100] @ 0x64 800108c: e7df b.n 800104e CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 800108e: 6e93 ldr r3, [r2, #104] @ 0x68 8001090: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8001094: 6693 str r3, [r2, #104] @ 0x68 8001096: e7e2 b.n 800105e LL_ADC_SetChannelPreselection(hadc->Instance, ADC_CHANNEL_DIFF_NEG_INPUT(hadc, sConfig->Channel)); 8001098: 6820 ldr r0, [r4, #0] 800109a: 4b4e ldr r3, [pc, #312] @ (80011d4 ) 800109c: 4298 cmp r0, r3 800109e: d005 beq.n 80010ac 80010a0: 4b4d ldr r3, [pc, #308] @ (80011d8 ) 80010a2: 4298 cmp r0, r3 80010a4: d02b beq.n 80010fe 80010a6: f7ff fda1 bl 8000bec 80010aa: e766 b.n 8000f7a 80010ac: 682b ldr r3, [r5, #0] 80010ae: 4a4b ldr r2, [pc, #300] @ (80011dc ) 80010b0: 4293 cmp r3, r2 80010b2: d04a beq.n 800114a 80010b4: 4a4a ldr r2, [pc, #296] @ (80011e0 ) 80010b6: 4293 cmp r3, r2 80010b8: d049 beq.n 800114e 80010ba: 4a4a ldr r2, [pc, #296] @ (80011e4 ) 80010bc: 4293 cmp r3, r2 80010be: d048 beq.n 8001152 80010c0: 4a49 ldr r2, [pc, #292] @ (80011e8 ) 80010c2: 4293 cmp r3, r2 80010c4: d047 beq.n 8001156 80010c6: f102 6286 add.w r2, r2, #70254592 @ 0x4300000 80010ca: 3210 adds r2, #16 80010cc: 4293 cmp r3, r2 80010ce: d044 beq.n 800115a 80010d0: 4a46 ldr r2, [pc, #280] @ (80011ec ) 80010d2: 4293 cmp r3, r2 80010d4: d043 beq.n 800115e 80010d6: f102 2204 add.w r2, r2, #67109888 @ 0x4000400 80010da: f502 1240 add.w r2, r2, #3145728 @ 0x300000 80010de: 4293 cmp r3, r2 80010e0: d03f beq.n 8001162 80010e2: f102 6286 add.w r2, r2, #70254592 @ 0x4300000 80010e6: f502 6200 add.w r2, r2, #2048 @ 0x800 80010ea: 4293 cmp r3, r2 80010ec: d03b beq.n 8001166 80010ee: 4a40 ldr r2, [pc, #256] @ (80011f0 ) 80010f0: 4293 cmp r3, r2 80010f2: d03a beq.n 800116a 80010f4: 4a3f ldr r2, [pc, #252] @ (80011f4 ) 80010f6: 4293 cmp r3, r2 80010f8: d1d5 bne.n 80010a6 80010fa: 493f ldr r1, [pc, #252] @ (80011f8 ) 80010fc: e7d3 b.n 80010a6 80010fe: 682b ldr r3, [r5, #0] 8001100: 4a36 ldr r2, [pc, #216] @ (80011dc ) 8001102: 4293 cmp r3, r2 8001104: d033 beq.n 800116e 8001106: 4a36 ldr r2, [pc, #216] @ (80011e0 ) 8001108: 4293 cmp r3, r2 800110a: d032 beq.n 8001172 800110c: 4a35 ldr r2, [pc, #212] @ (80011e4 ) 800110e: 4293 cmp r3, r2 8001110: d031 beq.n 8001176 8001112: 4a35 ldr r2, [pc, #212] @ (80011e8 ) 8001114: 4293 cmp r3, r2 8001116: d030 beq.n 800117a 8001118: f102 6286 add.w r2, r2, #70254592 @ 0x4300000 800111c: 3210 adds r2, #16 800111e: 4293 cmp r3, r2 8001120: d02d beq.n 800117e 8001122: 4a32 ldr r2, [pc, #200] @ (80011ec ) 8001124: 4293 cmp r3, r2 8001126: d02c beq.n 8001182 8001128: f102 2204 add.w r2, r2, #67109888 @ 0x4000400 800112c: f502 1240 add.w r2, r2, #3145728 @ 0x300000 8001130: 4293 cmp r3, r2 8001132: d028 beq.n 8001186 8001134: f102 6286 add.w r2, r2, #70254592 @ 0x4300000 8001138: f502 6200 add.w r2, r2, #2048 @ 0x800 800113c: 4293 cmp r3, r2 800113e: d024 beq.n 800118a 8001140: 4a2c ldr r2, [pc, #176] @ (80011f4 ) 8001142: 4293 cmp r3, r2 8001144: d1af bne.n 80010a6 8001146: 492c ldr r1, [pc, #176] @ (80011f8 ) 8001148: e7ad b.n 80010a6 800114a: 2101 movs r1, #1 800114c: e7ab b.n 80010a6 800114e: 492b ldr r1, [pc, #172] @ (80011fc ) 8001150: e7a9 b.n 80010a6 8001152: 492b ldr r1, [pc, #172] @ (8001200 ) 8001154: e7a7 b.n 80010a6 8001156: 492b ldr r1, [pc, #172] @ (8001204 ) 8001158: e7a5 b.n 80010a6 800115a: 492b ldr r1, [pc, #172] @ (8001208 ) 800115c: e7a3 b.n 80010a6 800115e: 492b ldr r1, [pc, #172] @ (800120c ) 8001160: e7a1 b.n 80010a6 8001162: 492b ldr r1, [pc, #172] @ (8001210 ) 8001164: e79f b.n 80010a6 8001166: 492b ldr r1, [pc, #172] @ (8001214 ) 8001168: e79d b.n 80010a6 800116a: 492b ldr r1, [pc, #172] @ (8001218 ) 800116c: e79b b.n 80010a6 800116e: 2101 movs r1, #1 8001170: e799 b.n 80010a6 8001172: 4922 ldr r1, [pc, #136] @ (80011fc ) 8001174: e797 b.n 80010a6 8001176: 4922 ldr r1, [pc, #136] @ (8001200 ) 8001178: e795 b.n 80010a6 800117a: 4922 ldr r1, [pc, #136] @ (8001204 ) 800117c: e793 b.n 80010a6 800117e: 4922 ldr r1, [pc, #136] @ (8001208 ) 8001180: e791 b.n 80010a6 8001182: 4922 ldr r1, [pc, #136] @ (800120c ) 8001184: e78f b.n 80010a6 8001186: 4922 ldr r1, [pc, #136] @ (8001210 ) 8001188: e78d b.n 80010a6 800118a: 4922 ldr r1, [pc, #136] @ (8001214 ) 800118c: e78b b.n 80010a6 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 800118e: 4a23 ldr r2, [pc, #140] @ (800121c ) 8001190: 6891 ldr r1, [r2, #8] 8001192: f001 75e0 and.w r5, r1, #29360128 @ 0x1c00000 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001196: f5a2 7240 sub.w r2, r2, #768 @ 0x300 800119a: 6892 ldr r2, [r2, #8] 800119c: f012 0201 ands.w r2, r2, #1 80011a0: d000 beq.n 80011a4 80011a2: 2201 movs r2, #1 80011a4: 480c ldr r0, [pc, #48] @ (80011d8 ) 80011a6: 6880 ldr r0, [r0, #8] 80011a8: f010 0f01 tst.w r0, #1 80011ac: f040 8088 bne.w 80012c0 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80011b0: 2a00 cmp r2, #0 80011b2: f040 8085 bne.w 80012c0 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 80011b6: 4a1a ldr r2, [pc, #104] @ (8001220 ) 80011b8: 4293 cmp r3, r2 80011ba: d037 beq.n 800122c else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 80011bc: 4a19 ldr r2, [pc, #100] @ (8001224 ) 80011be: 4293 cmp r3, r2 80011c0: d058 beq.n 8001274 else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 80011c2: 4a19 ldr r2, [pc, #100] @ (8001228 ) 80011c4: 4293 cmp r3, r2 80011c6: d068 beq.n 800129a HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80011c8: 2000 movs r0, #0 80011ca: e695 b.n 8000ef8 80011cc: 000fffff .word 0x000fffff 80011d0: 47ff0000 .word 0x47ff0000 80011d4: 40022000 .word 0x40022000 80011d8: 40022100 .word 0x40022100 80011dc: 04300002 .word 0x04300002 80011e0: 08600004 .word 0x08600004 80011e4: 0c900008 .word 0x0c900008 80011e8: 10c00010 .word 0x10c00010 80011ec: 2a000400 .word 0x2a000400 80011f0: 43210000 .word 0x43210000 80011f4: 4b840000 .word 0x4b840000 80011f8: 4fb80000 .word 0x4fb80000 80011fc: 19200040 .word 0x19200040 8001200: 1d500080 .word 0x1d500080 8001204: 21800100 .word 0x21800100 8001208: 25b00200 .word 0x25b00200 800120c: 2e300800 .word 0x2e300800 8001210: 32601000 .word 0x32601000 8001214: 36902000 .word 0x36902000 8001218: 47520000 .word 0x47520000 800121c: 40022300 .word 0x40022300 8001220: cb840000 .word 0xcb840000 8001224: bac04000 .word 0xbac04000 8001228: cfb80000 .word 0xcfb80000 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 800122c: f411 0f00 tst.w r1, #8388608 @ 0x800000 8001230: d1c4 bne.n 80011bc if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8001232: 6822 ldr r2, [r4, #0] 8001234: 4b28 ldr r3, [pc, #160] @ (80012d8 ) 8001236: 429a cmp r2, r3 8001238: d001 beq.n 800123e HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800123a: 2000 movs r0, #0 800123c: e65c b.n 8000ef8 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 800123e: f445 0300 orr.w r3, r5, #8388608 @ 0x800000 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8001242: 4926 ldr r1, [pc, #152] @ (80012dc ) 8001244: 688a ldr r2, [r1, #8] 8001246: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000 800124a: 4313 orrs r3, r2 800124c: 608b str r3, [r1, #8] wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800124e: 4b24 ldr r3, [pc, #144] @ (80012e0 ) 8001250: 681b ldr r3, [r3, #0] 8001252: 099b lsrs r3, r3, #6 8001254: 4a23 ldr r2, [pc, #140] @ (80012e4 ) 8001256: fba2 2303 umull r2, r3, r2, r3 800125a: 099b lsrs r3, r3, #6 800125c: 3301 adds r3, #1 800125e: 005b lsls r3, r3, #1 8001260: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 8001262: e002 b.n 800126a wait_loop_index--; 8001264: 9b01 ldr r3, [sp, #4] 8001266: 3b01 subs r3, #1 8001268: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 800126a: 9b01 ldr r3, [sp, #4] 800126c: 2b00 cmp r3, #0 800126e: d1f9 bne.n 8001264 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001270: 2000 movs r0, #0 8001272: e641 b.n 8000ef8 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8001274: f011 7f80 tst.w r1, #16777216 @ 0x1000000 8001278: d1a3 bne.n 80011c2 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800127a: 6822 ldr r2, [r4, #0] 800127c: 4b16 ldr r3, [pc, #88] @ (80012d8 ) 800127e: 429a cmp r2, r3 8001280: d001 beq.n 8001286 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001282: 2000 movs r0, #0 8001284: e638 b.n 8000ef8 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8001286: f045 7380 orr.w r3, r5, #16777216 @ 0x1000000 800128a: 4914 ldr r1, [pc, #80] @ (80012dc ) 800128c: 688a ldr r2, [r1, #8] 800128e: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000 8001292: 4313 orrs r3, r2 8001294: 608b str r3, [r1, #8] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001296: 2000 movs r0, #0 } 8001298: e62e b.n 8000ef8 else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 800129a: f411 0f80 tst.w r1, #4194304 @ 0x400000 800129e: d117 bne.n 80012d0 if (ADC_VREFINT_INSTANCE(hadc)) 80012a0: 6822 ldr r2, [r4, #0] 80012a2: 4b0d ldr r3, [pc, #52] @ (80012d8 ) 80012a4: 429a cmp r2, r3 80012a6: d001 beq.n 80012ac HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80012a8: 2000 movs r0, #0 80012aa: e625 b.n 8000ef8 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 80012ac: f445 0380 orr.w r3, r5, #4194304 @ 0x400000 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 80012b0: 490a ldr r1, [pc, #40] @ (80012dc ) 80012b2: 688a ldr r2, [r1, #8] 80012b4: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000 80012b8: 4313 orrs r3, r2 80012ba: 608b str r3, [r1, #8] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80012bc: 2000 movs r0, #0 } 80012be: e61b b.n 8000ef8 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80012c0: 6d63 ldr r3, [r4, #84] @ 0x54 80012c2: f043 0320 orr.w r3, r3, #32 80012c6: 6563 str r3, [r4, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80012c8: 2001 movs r0, #1 80012ca: e615 b.n 8000ef8 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80012cc: 2000 movs r0, #0 80012ce: e613 b.n 8000ef8 80012d0: 2000 movs r0, #0 80012d2: e611 b.n 8000ef8 __HAL_LOCK(hadc); 80012d4: 2002 movs r0, #2 80012d6: e612 b.n 8000efe 80012d8: 40022100 .word 0x40022100 80012dc: 40022300 .word 0x40022300 80012e0: 2000000c .word 0x2000000c 80012e4: 053e2d63 .word 0x053e2d63 080012e8 : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 80012e8: b510 push {r4, lr} 80012ea: 4604 mov r4, r0 uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 80012ec: 4b3a ldr r3, [pc, #232] @ (80013d8 ) 80012ee: 689b ldr r3, [r3, #8] 80012f0: f413 3f40 tst.w r3, #196608 @ 0x30000 80012f4: d019 beq.n 800132a { freq = HAL_RCC_GetHCLKFreq(); 80012f6: f002 fcf1 bl 8003cdc switch (hadc->Init.ClockPrescaler) 80012fa: 6863 ldr r3, [r4, #4] 80012fc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8001300: d005 beq.n 800130e 8001302: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8001306: d00e beq.n 8001326 8001308: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800130c: d102 bne.n 8001314 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 800130e: 0c1b lsrs r3, r3, #16 8001310: fbb0 f0f3 udiv r0, r0, r3 } } #if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90) freq /= 2U; if (freq <= 6250000UL) 8001314: 4b31 ldr r3, [pc, #196] @ (80013dc ) 8001316: 4298 cmp r0, r3 8001318: d841 bhi.n 800139e { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 800131a: 6822 ldr r2, [r4, #0] 800131c: 6893 ldr r3, [r2, #8] 800131e: f423 7340 bic.w r3, r3, #768 @ 0x300 8001322: 6093 str r3, [r2, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 8001324: bd10 pop {r4, pc} freq /= 4UL; 8001326: 0880 lsrs r0, r0, #2 break; 8001328: e7f4 b.n 8001314 freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 800132a: f44f 2000 mov.w r0, #524288 @ 0x80000 800132e: 2100 movs r1, #0 8001330: f003 fe4c bl 8004fcc switch (hadc->Init.ClockPrescaler) 8001334: 6863 ldr r3, [r4, #4] 8001336: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 800133a: d02c beq.n 8001396 800133c: d821 bhi.n 8001382 800133e: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8001342: d026 beq.n 8001392 8001344: d904 bls.n 8001350 8001346: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800134a: d1e3 bne.n 8001314 freq /= 32UL; 800134c: 0940 lsrs r0, r0, #5 break; 800134e: e7e1 b.n 8001314 switch (hadc->Init.ClockPrescaler) 8001350: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8001354: d010 beq.n 8001378 8001356: d809 bhi.n 800136c 8001358: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 800135c: d00c beq.n 8001378 800135e: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8001362: d009 beq.n 8001378 8001364: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8001368: d006 beq.n 8001378 800136a: e7d3 b.n 8001314 800136c: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8001370: d002 beq.n 8001378 8001372: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8001376: d1cd bne.n 8001314 freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 8001378: 0c9b lsrs r3, r3, #18 800137a: 005b lsls r3, r3, #1 800137c: fbb0 f0f3 udiv r0, r0, r3 break; 8001380: e7c8 b.n 8001314 switch (hadc->Init.ClockPrescaler) 8001382: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8001386: d008 beq.n 800139a 8001388: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 800138c: d1c2 bne.n 8001314 freq /= 256UL; 800138e: 0a00 lsrs r0, r0, #8 break; 8001390: e7c0 b.n 8001314 freq /= 16UL; 8001392: 0900 lsrs r0, r0, #4 break; 8001394: e7be b.n 8001314 freq /= 64UL; 8001396: 0980 lsrs r0, r0, #6 break; 8001398: e7bc b.n 8001314 freq /= 128UL; 800139a: 09c0 lsrs r0, r0, #7 break; 800139c: e7ba b.n 8001314 else if (freq <= 12500000UL) 800139e: 4b10 ldr r3, [pc, #64] @ (80013e0 ) 80013a0: 4298 cmp r0, r3 80013a2: d807 bhi.n 80013b4 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 80013a4: 6822 ldr r2, [r4, #0] 80013a6: 6893 ldr r3, [r2, #8] 80013a8: f423 7340 bic.w r3, r3, #768 @ 0x300 80013ac: f443 7380 orr.w r3, r3, #256 @ 0x100 80013b0: 6093 str r3, [r2, #8] 80013b2: e7b7 b.n 8001324 else if (freq <= 25000000UL) 80013b4: 4b0b ldr r3, [pc, #44] @ (80013e4 ) 80013b6: 4298 cmp r0, r3 80013b8: d807 bhi.n 80013ca MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 80013ba: 6822 ldr r2, [r4, #0] 80013bc: 6893 ldr r3, [r2, #8] 80013be: f423 7340 bic.w r3, r3, #768 @ 0x300 80013c2: f443 7300 orr.w r3, r3, #512 @ 0x200 80013c6: 6093 str r3, [r2, #8] 80013c8: e7ac b.n 8001324 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 80013ca: 6822 ldr r2, [r4, #0] 80013cc: 6893 ldr r3, [r2, #8] 80013ce: f443 7340 orr.w r3, r3, #768 @ 0x300 80013d2: 6093 str r3, [r2, #8] } 80013d4: e7a6 b.n 8001324 80013d6: bf00 nop 80013d8: 40022300 .word 0x40022300 80013dc: 00bebc21 .word 0x00bebc21 80013e0: 017d7841 .word 0x017d7841 80013e4: 02faf081 .word 0x02faf081 080013e8 : { 80013e8: b530 push {r4, r5, lr} 80013ea: b083 sub sp, #12 __IO uint32_t wait_loop_index = 0UL; 80013ec: 2300 movs r3, #0 80013ee: 9301 str r3, [sp, #4] if (hadc == NULL) 80013f0: 2800 cmp r0, #0 80013f2: f000 80df beq.w 80015b4 80013f6: 4604 mov r4, r0 if (hadc->State == HAL_ADC_STATE_RESET) 80013f8: 6d43 ldr r3, [r0, #84] @ 0x54 80013fa: b1eb cbz r3, 8001438 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 80013fc: 6823 ldr r3, [r4, #0] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 80013fe: 689a ldr r2, [r3, #8] 8001400: f012 5f00 tst.w r2, #536870912 @ 0x20000000 8001404: d003 beq.n 800140e CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8001406: 6899 ldr r1, [r3, #8] 8001408: 4a6b ldr r2, [pc, #428] @ (80015b8 ) 800140a: 400a ands r2, r1 800140c: 609a str r2, [r3, #8] if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 800140e: 6823 ldr r3, [r4, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8001410: 689a ldr r2, [r3, #8] 8001412: f012 5f80 tst.w r2, #268435456 @ 0x10000000 8001416: d11c bne.n 8001452 MODIFY_REG(ADCx->CR, 8001418: 6899 ldr r1, [r3, #8] 800141a: 4a68 ldr r2, [pc, #416] @ (80015bc ) 800141c: 400a ands r2, r1 800141e: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000 8001422: 609a str r2, [r3, #8] wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8001424: 4b66 ldr r3, [pc, #408] @ (80015c0 ) 8001426: 681b ldr r3, [r3, #0] 8001428: 099b lsrs r3, r3, #6 800142a: 4a66 ldr r2, [pc, #408] @ (80015c4 ) 800142c: fba2 2303 umull r2, r3, r2, r3 8001430: 099b lsrs r3, r3, #6 8001432: 3301 adds r3, #1 8001434: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 8001436: e009 b.n 800144c HAL_ADC_MspInit(hadc); 8001438: f001 fc58 bl 8002cec ADC_CLEAR_ERRORCODE(hadc); 800143c: 2300 movs r3, #0 800143e: 65a3 str r3, [r4, #88] @ 0x58 hadc->Lock = HAL_UNLOCKED; 8001440: f884 3050 strb.w r3, [r4, #80] @ 0x50 8001444: e7da b.n 80013fc wait_loop_index--; 8001446: 9b01 ldr r3, [sp, #4] 8001448: 3b01 subs r3, #1 800144a: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 800144c: 9b01 ldr r3, [sp, #4] 800144e: 2b00 cmp r3, #0 8001450: d1f9 bne.n 8001446 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8001452: 6822 ldr r2, [r4, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8001454: 6893 ldr r3, [r2, #8] 8001456: f013 5f80 tst.w r3, #268435456 @ 0x10000000 800145a: f040 8081 bne.w 8001560 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800145e: 6d63 ldr r3, [r4, #84] @ 0x54 8001460: f043 0310 orr.w r3, r3, #16 8001464: 6563 str r3, [r4, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001466: 6da3 ldr r3, [r4, #88] @ 0x58 8001468: f043 0301 orr.w r3, r3, #1 800146c: 65a3 str r3, [r4, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 800146e: 2501 movs r5, #1 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8001470: 6893 ldr r3, [r2, #8] 8001472: f013 0304 ands.w r3, r3, #4 8001476: d000 beq.n 800147a 8001478: 2301 movs r3, #1 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 800147a: 6d61 ldr r1, [r4, #84] @ 0x54 800147c: f011 0f10 tst.w r1, #16 8001480: f040 8090 bne.w 80015a4 && (tmp_adc_reg_is_conversion_on_going == 0UL) 8001484: 2b00 cmp r3, #0 8001486: f040 808d bne.w 80015a4 ADC_STATE_CLR_SET(hadc->State, 800148a: 6d63 ldr r3, [r4, #84] @ 0x54 800148c: f423 7381 bic.w r3, r3, #258 @ 0x102 8001490: f043 0302 orr.w r3, r3, #2 8001494: 6563 str r3, [r4, #84] @ 0x54 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001496: 6893 ldr r3, [r2, #8] 8001498: f013 0f01 tst.w r3, #1 800149c: d112 bne.n 80014c4 800149e: 4b4a ldr r3, [pc, #296] @ (80015c8 ) 80014a0: 689b ldr r3, [r3, #8] 80014a2: f013 0301 ands.w r3, r3, #1 80014a6: d000 beq.n 80014aa 80014a8: 2301 movs r3, #1 80014aa: 4a48 ldr r2, [pc, #288] @ (80015cc ) 80014ac: 6892 ldr r2, [r2, #8] 80014ae: f012 0f01 tst.w r2, #1 80014b2: d107 bne.n 80014c4 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80014b4: b933 cbnz r3, 80014c4 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 80014b6: 6863 ldr r3, [r4, #4] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 80014b8: 4945 ldr r1, [pc, #276] @ (80015d0 ) 80014ba: 688a ldr r2, [r1, #8] 80014bc: f422 127c bic.w r2, r2, #4128768 @ 0x3f0000 80014c0: 4313 orrs r3, r2 80014c2: 608b str r3, [r1, #8] tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80014c4: 7d62 ldrb r2, [r4, #21] hadc->Init.Overrun | 80014c6: 6b23 ldr r3, [r4, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80014c8: ea43 3342 orr.w r3, r3, r2, lsl #13 hadc->Init.Resolution | 80014cc: 68a2 ldr r2, [r4, #8] hadc->Init.Overrun | 80014ce: 4313 orrs r3, r2 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 80014d0: 7f22 ldrb r2, [r4, #28] tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80014d2: ea43 4302 orr.w r3, r3, r2, lsl #16 if (hadc->Init.DiscontinuousConvMode == ENABLE) 80014d6: 2a01 cmp r2, #1 80014d8: d044 beq.n 8001564 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 80014da: 6a62 ldr r2, [r4, #36] @ 0x24 80014dc: b122 cbz r2, 80014e8 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 80014de: f402 7278 and.w r2, r2, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 80014e2: 6aa1 ldr r1, [r4, #40] @ 0x28 80014e4: 430a orrs r2, r1 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 80014e6: 4313 orrs r3, r2 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 80014e8: 6821 ldr r1, [r4, #0] 80014ea: 68c8 ldr r0, [r1, #12] 80014ec: 4a39 ldr r2, [pc, #228] @ (80015d4 ) 80014ee: 4002 ands r2, r0 80014f0: 431a orrs r2, r3 80014f2: 60ca str r2, [r1, #12] tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80014f4: 6822 ldr r2, [r4, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80014f6: 6893 ldr r3, [r2, #8] 80014f8: f013 0304 ands.w r3, r3, #4 80014fc: d000 beq.n 8001500 80014fe: 2301 movs r3, #1 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8001500: 6891 ldr r1, [r2, #8] 8001502: f011 0f08 tst.w r1, #8 8001506: d11c bne.n 8001542 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8001508: b9db cbnz r3, 8001542 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 800150a: 7d21 ldrb r1, [r4, #20] ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 800150c: 6ae3 ldr r3, [r4, #44] @ 0x2c tmpCFGR = ( 800150e: ea43 3181 orr.w r1, r3, r1, lsl #14 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8001512: 68d0 ldr r0, [r2, #12] 8001514: 4b30 ldr r3, [pc, #192] @ (80015d8 ) 8001516: 4003 ands r3, r0 8001518: 430b orrs r3, r1 800151a: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 800151c: f894 3038 ldrb.w r3, [r4, #56] @ 0x38 8001520: 2b01 cmp r3, #1 8001522: d024 beq.n 800156e CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8001524: 6822 ldr r2, [r4, #0] 8001526: 6913 ldr r3, [r2, #16] 8001528: f023 0301 bic.w r3, r3, #1 800152c: 6113 str r3, [r2, #16] MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 800152e: 6822 ldr r2, [r4, #0] 8001530: 6913 ldr r3, [r2, #16] 8001532: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 8001536: 6b61 ldr r1, [r4, #52] @ 0x34 8001538: 430b orrs r3, r1 800153a: 6113 str r3, [r2, #16] ADC_ConfigureBoostMode(hadc); 800153c: 4620 mov r0, r4 800153e: f7ff fed3 bl 80012e8 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8001542: 68e3 ldr r3, [r4, #12] 8001544: 2b01 cmp r3, #1 8001546: d024 beq.n 8001592 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 8001548: 6822 ldr r2, [r4, #0] 800154a: 6b13 ldr r3, [r2, #48] @ 0x30 800154c: f023 030f bic.w r3, r3, #15 8001550: 6313 str r3, [r2, #48] @ 0x30 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 8001552: 6d63 ldr r3, [r4, #84] @ 0x54 8001554: f023 0303 bic.w r3, r3, #3 8001558: f043 0301 orr.w r3, r3, #1 800155c: 6563 str r3, [r4, #84] @ 0x54 800155e: e026 b.n 80015ae HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001560: 2500 movs r5, #0 8001562: e785 b.n 8001470 tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8001564: 6a22 ldr r2, [r4, #32] 8001566: 3a01 subs r2, #1 8001568: ea43 4342 orr.w r3, r3, r2, lsl #17 800156c: e7b5 b.n 80014da MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 800156e: 6820 ldr r0, [r4, #0] 8001570: 6902 ldr r2, [r0, #16] 8001572: 4b1a ldr r3, [pc, #104] @ (80015dc ) 8001574: 4013 ands r3, r2 8001576: 6be2 ldr r2, [r4, #60] @ 0x3c 8001578: 1e51 subs r1, r2, #1 800157a: 6c22 ldr r2, [r4, #64] @ 0x40 800157c: ea42 4201 orr.w r2, r2, r1, lsl #16 8001580: 6c61 ldr r1, [r4, #68] @ 0x44 8001582: 430a orrs r2, r1 8001584: 6ca1 ldr r1, [r4, #72] @ 0x48 8001586: 430a orrs r2, r1 8001588: 4313 orrs r3, r2 800158a: f043 0301 orr.w r3, r3, #1 800158e: 6103 str r3, [r0, #16] 8001590: e7cd b.n 800152e MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8001592: 6821 ldr r1, [r4, #0] 8001594: 6b0b ldr r3, [r1, #48] @ 0x30 8001596: f023 030f bic.w r3, r3, #15 800159a: 69a2 ldr r2, [r4, #24] 800159c: 3a01 subs r2, #1 800159e: 4313 orrs r3, r2 80015a0: 630b str r3, [r1, #48] @ 0x30 80015a2: e7d6 b.n 8001552 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80015a4: 6d63 ldr r3, [r4, #84] @ 0x54 80015a6: f043 0310 orr.w r3, r3, #16 80015aa: 6563 str r3, [r4, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80015ac: 2501 movs r5, #1 } 80015ae: 4628 mov r0, r5 80015b0: b003 add sp, #12 80015b2: bd30 pop {r4, r5, pc} return HAL_ERROR; 80015b4: 2501 movs r5, #1 80015b6: e7fa b.n 80015ae 80015b8: 5fffffc0 .word 0x5fffffc0 80015bc: 6fffffc0 .word 0x6fffffc0 80015c0: 2000000c .word 0x2000000c 80015c4: 053e2d63 .word 0x053e2d63 80015c8: 40022000 .word 0x40022000 80015cc: 40022100 .word 0x40022100 80015d0: 40022300 .word 0x40022300 80015d4: fff0c003 .word 0xfff0c003 80015d8: ffffbffc .word 0xffffbffc 80015dc: fc00f81e .word 0xfc00f81e 080015e0 : UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. */ } 80015e0: 4770 bx lr 080015e2 : UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } 80015e2: 4770 bx lr 080015e4 : UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. */ } 80015e4: 4770 bx lr 080015e6 : UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. */ } 80015e6: 4770 bx lr 080015e8 : UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. */ } 80015e8: 4770 bx lr ... 080015ec : assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 80015ec: f890 2050 ldrb.w r2, [r0, #80] @ 0x50 80015f0: 2a01 cmp r2, #1 80015f2: d078 beq.n 80016e6 { 80015f4: b410 push {r4} 80015f6: b09b sub sp, #108 @ 0x6c 80015f8: 4603 mov r3, r0 __HAL_LOCK(hadc); 80015fa: 2201 movs r2, #1 80015fc: f880 2050 strb.w r2, [r0, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 8001600: 2200 movs r2, #0 8001602: 9216 str r2, [sp, #88] @ 0x58 tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 8001604: 9217 str r2, [sp, #92] @ 0x5c ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8001606: 6800 ldr r0, [r0, #0] 8001608: 4a38 ldr r2, [pc, #224] @ (80016ec ) 800160a: 4290 cmp r0, r2 800160c: d031 beq.n 8001672 800160e: 2200 movs r2, #0 8001610: 9201 str r2, [sp, #4] if (tmphadcSlave.Instance == NULL) 8001612: 9a01 ldr r2, [sp, #4] 8001614: 2a00 cmp r2, #0 8001616: d030 beq.n 800167a return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8001618: 6892 ldr r2, [r2, #8] 800161a: f012 0204 ands.w r2, r2, #4 800161e: d000 beq.n 8001622 8001620: 2201 movs r2, #1 8001622: 6880 ldr r0, [r0, #8] 8001624: f010 0f04 tst.w r0, #4 8001628: d149 bne.n 80016be /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) && (tmphadcSlave_conversion_on_going == 0UL)) 800162a: 2a00 cmp r2, #0 800162c: d147 bne.n 80016be tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 800162e: 680a ldr r2, [r1, #0] 8001630: b362 cbz r2, 800168c { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 8001632: 482f ldr r0, [pc, #188] @ (80016f0 ) 8001634: 6882 ldr r2, [r0, #8] 8001636: f422 4240 bic.w r2, r2, #49152 @ 0xc000 800163a: 684c ldr r4, [r1, #4] 800163c: 4322 orrs r2, r4 800163e: 6082 str r2, [r0, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001640: 4a2a ldr r2, [pc, #168] @ (80016ec ) 8001642: 6892 ldr r2, [r2, #8] 8001644: f012 0201 ands.w r2, r2, #1 8001648: d000 beq.n 800164c 800164a: 2201 movs r2, #1 800164c: 4829 ldr r0, [pc, #164] @ (80016f4 ) 800164e: 6880 ldr r0, [r0, #8] 8001650: f010 0f01 tst.w r0, #1 8001654: d13f bne.n 80016d6 /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8001656: 2a00 cmp r2, #0 8001658: d13f bne.n 80016da { MODIFY_REG(tmpADC_Common->CCR, 800165a: 4c25 ldr r4, [pc, #148] @ (80016f0 ) 800165c: 68a0 ldr r0, [r4, #8] 800165e: f5a2 6272 sub.w r2, r2, #3872 @ 0xf20 8001662: 4002 ands r2, r0 8001664: 6808 ldr r0, [r1, #0] 8001666: 6889 ldr r1, [r1, #8] 8001668: 4301 orrs r1, r0 800166a: 430a orrs r2, r1 800166c: 60a2 str r2, [r4, #8] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800166e: 2000 movs r0, #0 8001670: e02a b.n 80016c8 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8001672: f502 7280 add.w r2, r2, #256 @ 0x100 8001676: 9201 str r2, [sp, #4] 8001678: e7cb b.n 8001612 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800167a: 6d5a ldr r2, [r3, #84] @ 0x54 800167c: f042 0220 orr.w r2, r2, #32 8001680: 655a str r2, [r3, #84] @ 0x54 __HAL_UNLOCK(hadc); 8001682: 2200 movs r2, #0 8001684: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8001688: 2001 movs r0, #1 800168a: e020 b.n 80016ce ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 800168c: 4918 ldr r1, [pc, #96] @ (80016f0 ) 800168e: 688a ldr r2, [r1, #8] 8001690: f422 4240 bic.w r2, r2, #49152 @ 0xc000 8001694: 608a str r2, [r1, #8] 8001696: 4a15 ldr r2, [pc, #84] @ (80016ec ) 8001698: 6892 ldr r2, [r2, #8] 800169a: f012 0201 ands.w r2, r2, #1 800169e: d000 beq.n 80016a2 80016a0: 2201 movs r2, #1 80016a2: 4914 ldr r1, [pc, #80] @ (80016f4 ) 80016a4: 6889 ldr r1, [r1, #8] 80016a6: f011 0f01 tst.w r1, #1 80016aa: d118 bne.n 80016de /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80016ac: b9ca cbnz r2, 80016e2 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 80016ae: 4910 ldr r1, [pc, #64] @ (80016f0 ) 80016b0: 6888 ldr r0, [r1, #8] 80016b2: f5a2 6272 sub.w r2, r2, #3872 @ 0xf20 80016b6: 4002 ands r2, r0 80016b8: 608a str r2, [r1, #8] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80016ba: 2000 movs r0, #0 80016bc: e004 b.n 80016c8 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80016be: 6d5a ldr r2, [r3, #84] @ 0x54 80016c0: f042 0220 orr.w r2, r2, #32 80016c4: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80016c6: 2001 movs r0, #1 } /* Process unlocked */ __HAL_UNLOCK(hadc); 80016c8: 2200 movs r2, #0 80016ca: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; } 80016ce: b01b add sp, #108 @ 0x6c 80016d0: f85d 4b04 ldr.w r4, [sp], #4 80016d4: 4770 bx lr HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80016d6: 2000 movs r0, #0 80016d8: e7f6 b.n 80016c8 80016da: 2000 movs r0, #0 80016dc: e7f4 b.n 80016c8 80016de: 2000 movs r0, #0 80016e0: e7f2 b.n 80016c8 80016e2: 2000 movs r0, #0 80016e4: e7f0 b.n 80016c8 __HAL_LOCK(hadc); 80016e6: 2002 movs r0, #2 } 80016e8: 4770 bx lr 80016ea: bf00 nop 80016ec: 40022000 .word 0x40022000 80016f0: 40022300 .word 0x40022300 80016f4: 40022100 .word 0x40022100 080016f8 <__NVIC_EnableIRQ>: \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) 80016f8: 2800 cmp r0, #0 80016fa: db07 blt.n 800170c <__NVIC_EnableIRQ+0x14> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80016fc: f000 021f and.w r2, r0, #31 8001700: 0940 lsrs r0, r0, #5 8001702: 2301 movs r3, #1 8001704: 4093 lsls r3, r2 8001706: 4a02 ldr r2, [pc, #8] @ (8001710 <__NVIC_EnableIRQ+0x18>) 8001708: f842 3020 str.w r3, [r2, r0, lsl #2] __COMPILER_BARRIER(); } } 800170c: 4770 bx lr 800170e: bf00 nop 8001710: e000e100 .word 0xe000e100 08001714 <__NVIC_SetPriority>: \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) 8001714: 2800 cmp r0, #0 8001716: db04 blt.n 8001722 <__NVIC_SetPriority+0xe> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001718: 0109 lsls r1, r1, #4 800171a: b2c9 uxtb r1, r1 800171c: 4b04 ldr r3, [pc, #16] @ (8001730 <__NVIC_SetPriority+0x1c>) 800171e: 5419 strb r1, [r3, r0] 8001720: 4770 bx lr } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001722: f000 000f and.w r0, r0, #15 8001726: 0109 lsls r1, r1, #4 8001728: b2c9 uxtb r1, r1 800172a: 4b02 ldr r3, [pc, #8] @ (8001734 <__NVIC_SetPriority+0x20>) 800172c: 5419 strb r1, [r3, r0] } } 800172e: 4770 bx lr 8001730: e000e400 .word 0xe000e400 8001734: e000ed14 .word 0xe000ed14 08001738 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001738: b500 push {lr} uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 800173a: f000 0007 and.w r0, r0, #7 uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800173e: f1c0 0c07 rsb ip, r0, #7 8001742: f1bc 0f04 cmp.w ip, #4 8001746: bf28 it cs 8001748: f04f 0c04 movcs.w ip, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800174c: 1d03 adds r3, r0, #4 800174e: 2b06 cmp r3, #6 8001750: d90f bls.n 8001772 8001752: 1ec3 subs r3, r0, #3 return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001754: f04f 3eff mov.w lr, #4294967295 @ 0xffffffff 8001758: fa0e f00c lsl.w r0, lr, ip 800175c: ea21 0100 bic.w r1, r1, r0 8001760: 4099 lsls r1, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001762: fa0e fe03 lsl.w lr, lr, r3 8001766: ea22 020e bic.w r2, r2, lr ); } 800176a: ea41 0002 orr.w r0, r1, r2 800176e: f85d fb04 ldr.w pc, [sp], #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001772: 2300 movs r3, #0 8001774: e7ee b.n 8001754 ... 08001778 : reg_value = SCB->AIRCR; /* read old register configuration */ 8001778: 4906 ldr r1, [pc, #24] @ (8001794 ) 800177a: 68cb ldr r3, [r1, #12] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800177c: f423 63e0 bic.w r3, r3, #1792 @ 0x700 8001780: 041b lsls r3, r3, #16 8001782: 0c1b lsrs r3, r3, #16 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001784: 0200 lsls r0, r0, #8 8001786: f400 60e0 and.w r0, r0, #1792 @ 0x700 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800178a: 4303 orrs r3, r0 reg_value = (reg_value | 800178c: 4a02 ldr r2, [pc, #8] @ (8001798 ) 800178e: 431a orrs r2, r3 SCB->AIRCR = reg_value; 8001790: 60ca str r2, [r1, #12] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } 8001792: 4770 bx lr 8001794: e000ed00 .word 0xe000ed00 8001798: 05fa0000 .word 0x05fa0000 0800179c : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800179c: b510 push {r4, lr} 800179e: 4604 mov r4, r0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80017a0: 4b05 ldr r3, [pc, #20] @ (80017b8 ) 80017a2: 68d8 ldr r0, [r3, #12] assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80017a4: f3c0 2002 ubfx r0, r0, #8, #3 80017a8: f7ff ffc6 bl 8001738 80017ac: 4601 mov r1, r0 80017ae: 4620 mov r0, r4 80017b0: f7ff ffb0 bl 8001714 <__NVIC_SetPriority> } 80017b4: bd10 pop {r4, pc} 80017b6: bf00 nop 80017b8: e000ed00 .word 0xe000ed00 080017bc : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80017bc: b508 push {r3, lr} /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80017be: f7ff ff9b bl 80016f8 <__NVIC_EnableIRQ> } 80017c2: bd08 pop {r3, pc} 080017c4 : function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80017c4: 3801 subs r0, #1 80017c6: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000 80017ca: d20b bcs.n 80017e4 { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80017cc: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 80017d0: 6158 str r0, [r3, #20] SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80017d2: 4a05 ldr r2, [pc, #20] @ (80017e8 ) 80017d4: 21f0 movs r1, #240 @ 0xf0 80017d6: f882 1023 strb.w r1, [r2, #35] @ 0x23 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80017da: 2000 movs r0, #0 80017dc: 6198 str r0, [r3, #24] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80017de: 2207 movs r2, #7 80017e0: 611a str r2, [r3, #16] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80017e2: 4770 bx lr return (1UL); /* Reload value impossible */ 80017e4: 2001 movs r0, #1 * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } 80017e6: 4770 bx lr 80017e8: e000ed00 .word 0xe000ed00 080017ec : __ASM volatile ("dmb 0xF":::"memory"); 80017ec: f3bf 8f5f dmb sy { /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 80017f0: 4b04 ldr r3, [pc, #16] @ (8001804 ) 80017f2: 6a5a ldr r2, [r3, #36] @ 0x24 80017f4: f422 3280 bic.w r2, r2, #65536 @ 0x10000 80017f8: 625a str r2, [r3, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 80017fa: 2200 movs r2, #0 80017fc: f8c3 2094 str.w r2, [r3, #148] @ 0x94 } 8001800: 4770 bx lr 8001802: bf00 nop 8001804: e000ed00 .word 0xe000ed00 08001808 : * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8001808: f040 0001 orr.w r0, r0, #1 800180c: 4b05 ldr r3, [pc, #20] @ (8001824 ) 800180e: f8c3 0094 str.w r0, [r3, #148] @ 0x94 /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 8001812: 6a5a ldr r2, [r3, #36] @ 0x24 8001814: f442 3280 orr.w r2, r2, #65536 @ 0x10000 8001818: 625a str r2, [r3, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 800181a: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 800181e: f3bf 8f6f isb sy /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8001822: 4770 bx lr 8001824: e000ed00 .word 0xe000ed00 08001828 : assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8001828: 7843 ldrb r3, [r0, #1] 800182a: 4a14 ldr r2, [pc, #80] @ (800187c ) 800182c: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 8001830: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0 8001834: f023 0301 bic.w r3, r3, #1 8001838: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 800183c: 6843 ldr r3, [r0, #4] 800183e: f8c2 309c str.w r3, [r2, #156] @ 0x9c MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8001842: 7b01 ldrb r1, [r0, #12] ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8001844: 7ac3 ldrb r3, [r0, #11] 8001846: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8001848: ea43 7301 orr.w r3, r3, r1, lsl #28 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 800184c: 7a81 ldrb r1, [r0, #10] ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 800184e: ea43 43c1 orr.w r3, r3, r1, lsl #19 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8001852: 7b41 ldrb r1, [r0, #13] ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8001854: ea43 4381 orr.w r3, r3, r1, lsl #18 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8001858: 7b81 ldrb r1, [r0, #14] ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 800185a: ea43 4341 orr.w r3, r3, r1, lsl #17 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 800185e: 7bc1 ldrb r1, [r0, #15] ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8001860: ea43 4301 orr.w r3, r3, r1, lsl #16 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8001864: 7a41 ldrb r1, [r0, #9] ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8001866: ea43 2301 orr.w r3, r3, r1, lsl #8 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 800186a: 7a01 ldrb r1, [r0, #8] ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 800186c: ea43 0341 orr.w r3, r3, r1, lsl #1 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 8001870: 7801 ldrb r1, [r0, #0] ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8001872: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8001874: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 } 8001878: 4770 bx lr 800187a: bf00 nop 800187c: e000ed00 .word 0xe000ed00 08001880 : * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8001880: 6803 ldr r3, [r0, #0] 8001882: 4927 ldr r1, [pc, #156] @ (8001920 ) 8001884: 4a27 ldr r2, [pc, #156] @ (8001924 ) 8001886: 4293 cmp r3, r2 8001888: bf18 it ne 800188a: 428b cmpne r3, r1 800188c: d02f beq.n 80018ee 800188e: 3218 adds r2, #24 8001890: 4293 cmp r3, r2 8001892: d02c beq.n 80018ee 8001894: 3218 adds r2, #24 8001896: 4293 cmp r3, r2 8001898: d029 beq.n 80018ee 800189a: 3218 adds r2, #24 800189c: 4293 cmp r3, r2 800189e: d026 beq.n 80018ee 80018a0: 3218 adds r2, #24 80018a2: 4293 cmp r3, r2 80018a4: d023 beq.n 80018ee 80018a6: 3218 adds r2, #24 80018a8: 4293 cmp r3, r2 80018aa: d020 beq.n 80018ee 80018ac: 3218 adds r2, #24 80018ae: 4293 cmp r3, r2 80018b0: d01d beq.n 80018ee 80018b2: f502 7256 add.w r2, r2, #856 @ 0x358 80018b6: 4293 cmp r3, r2 80018b8: d019 beq.n 80018ee 80018ba: 3218 adds r2, #24 80018bc: 4293 cmp r3, r2 80018be: d016 beq.n 80018ee 80018c0: 3218 adds r2, #24 80018c2: 4293 cmp r3, r2 80018c4: d013 beq.n 80018ee 80018c6: 3218 adds r2, #24 80018c8: 4293 cmp r3, r2 80018ca: d010 beq.n 80018ee 80018cc: 3218 adds r2, #24 80018ce: 4293 cmp r3, r2 80018d0: d00d beq.n 80018ee 80018d2: 3218 adds r2, #24 80018d4: 4293 cmp r3, r2 80018d6: d00a beq.n 80018ee 80018d8: 3218 adds r2, #24 80018da: 4293 cmp r3, r2 80018dc: d007 beq.n 80018ee 80018de: 3218 adds r2, #24 80018e0: 4293 cmp r3, r2 80018e2: d004 beq.n 80018ee } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 80018e4: f023 03ff bic.w r3, r3, #255 @ 0xff 80018e8: 6583 str r3, [r0, #88] @ 0x58 } return hdma->StreamBaseAddress; } 80018ea: 6d80 ldr r0, [r0, #88] @ 0x58 80018ec: 4770 bx lr { 80018ee: b410 push {r4} uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 80018f0: b2d9 uxtb r1, r3 80018f2: 3910 subs r1, #16 80018f4: 4a0c ldr r2, [pc, #48] @ (8001928 ) 80018f6: fba2 4201 umull r4, r2, r2, r1 hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 80018fa: f3c2 1202 ubfx r2, r2, #4, #3 80018fe: 4c0b ldr r4, [pc, #44] @ (800192c ) 8001900: 5ca2 ldrb r2, [r4, r2] 8001902: 65c2 str r2, [r0, #92] @ 0x5c if (stream_number > 3U) 8001904: 295f cmp r1, #95 @ 0x5f 8001906: d907 bls.n 8001918 hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 8001908: f36f 0309 bfc r3, #0, #10 800190c: 3304 adds r3, #4 800190e: 6583 str r3, [r0, #88] @ 0x58 } 8001910: 6d80 ldr r0, [r0, #88] @ 0x58 8001912: f85d 4b04 ldr.w r4, [sp], #4 8001916: 4770 bx lr hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 8001918: f36f 0309 bfc r3, #0, #10 800191c: 6583 str r3, [r0, #88] @ 0x58 800191e: e7f7 b.n 8001910 8001920: 40020010 .word 0x40020010 8001924: 40020028 .word 0x40020028 8001928: aaaaaaab .word 0xaaaaaaab 800192c: 080063b0 .word 0x080063b0 08001930 : static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 8001930: 6983 ldr r3, [r0, #24] 8001932: b99b cbnz r3, 800195c { switch (hdma->Init.FIFOThreshold) 8001934: 6a83 ldr r3, [r0, #40] @ 0x28 8001936: 2b01 cmp r3, #1 8001938: d00a beq.n 8001950 800193a: 2b02 cmp r3, #2 800193c: d002 beq.n 8001944 800193e: b10b cbz r3, 8001944 8001940: 2000 movs r0, #0 8001942: 4770 bx lr { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8001944: 6ac3 ldr r3, [r0, #44] @ 0x2c 8001946: f013 7f80 tst.w r3, #16777216 @ 0x1000000 800194a: d12a bne.n 80019a2 HAL_StatusTypeDef status = HAL_OK; 800194c: 2000 movs r0, #0 800194e: 4770 bx lr status = HAL_ERROR; } break; case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8001950: 6ac3 ldr r3, [r0, #44] @ 0x2c 8001952: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 8001956: d026 beq.n 80019a6 HAL_StatusTypeDef status = HAL_OK; 8001958: 2000 movs r0, #0 800195a: 4770 bx lr break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800195c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8001960: d00a beq.n 8001978 } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 8001962: 6a83 ldr r3, [r0, #40] @ 0x28 8001964: 2b02 cmp r3, #2 8001966: d926 bls.n 80019b6 8001968: 2b03 cmp r3, #3 800196a: d126 bne.n 80019ba case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; break; case DMA_FIFO_THRESHOLD_FULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800196c: 6ac3 ldr r3, [r0, #44] @ 0x2c 800196e: f013 7f80 tst.w r3, #16777216 @ 0x1000000 8001972: d124 bne.n 80019be HAL_StatusTypeDef status = HAL_OK; 8001974: 2000 movs r0, #0 8001976: 4770 bx lr switch (hdma->Init.FIFOThreshold) 8001978: 6a83 ldr r3, [r0, #40] @ 0x28 800197a: 2b03 cmp r3, #3 800197c: d803 bhi.n 8001986 800197e: e8df f003 tbb [pc, r3] 8001982: 0414 .short 0x0414 8001984: 0a14 .short 0x0a14 8001986: 2000 movs r0, #0 8001988: 4770 bx lr if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800198a: 6ac3 ldr r3, [r0, #44] @ 0x2c 800198c: f013 7f80 tst.w r3, #16777216 @ 0x1000000 8001990: d10d bne.n 80019ae HAL_StatusTypeDef status = HAL_OK; 8001992: 2000 movs r0, #0 8001994: 4770 bx lr if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8001996: 6ac3 ldr r3, [r0, #44] @ 0x2c 8001998: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800199c: d009 beq.n 80019b2 HAL_StatusTypeDef status = HAL_OK; 800199e: 2000 movs r0, #0 80019a0: 4770 bx lr status = HAL_ERROR; 80019a2: 2001 movs r0, #1 80019a4: 4770 bx lr status = HAL_ERROR; 80019a6: 2001 movs r0, #1 80019a8: 4770 bx lr status = HAL_ERROR; 80019aa: 2001 movs r0, #1 80019ac: 4770 bx lr status = HAL_ERROR; 80019ae: 2001 movs r0, #1 80019b0: 4770 bx lr status = HAL_ERROR; 80019b2: 2001 movs r0, #1 80019b4: 4770 bx lr status = HAL_ERROR; 80019b6: 2001 movs r0, #1 80019b8: 4770 bx lr switch (hdma->Init.FIFOThreshold) 80019ba: 2000 movs r0, #0 80019bc: 4770 bx lr { status = HAL_ERROR; 80019be: 2001 movs r0, #1 break; } } return status; } 80019c0: 4770 bx lr ... 080019c4 : * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 80019c4: 6803 ldr r3, [r0, #0] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80019c6: 4921 ldr r1, [pc, #132] @ (8001a4c ) 80019c8: 4a21 ldr r2, [pc, #132] @ (8001a50 ) 80019ca: 4293 cmp r3, r2 80019cc: bf18 it ne 80019ce: 428b cmpne r3, r1 80019d0: d027 beq.n 8001a22 80019d2: 3214 adds r2, #20 80019d4: 4293 cmp r3, r2 80019d6: d024 beq.n 8001a22 80019d8: 3214 adds r2, #20 80019da: 4293 cmp r3, r2 80019dc: d021 beq.n 8001a22 80019de: 3214 adds r2, #20 80019e0: 4293 cmp r3, r2 80019e2: d01e beq.n 8001a22 80019e4: 3214 adds r2, #20 80019e6: 4293 cmp r3, r2 80019e8: d01b beq.n 8001a22 80019ea: 3214 adds r2, #20 80019ec: 4293 cmp r3, r2 80019ee: d018 beq.n 8001a22 80019f0: 3214 adds r2, #20 80019f2: 4293 cmp r3, r2 80019f4: d015 beq.n 8001a22 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } else { /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 80019f6: b2da uxtb r2, r3 80019f8: 3a10 subs r2, #16 80019fa: 4916 ldr r1, [pc, #88] @ (8001a54 ) 80019fc: fba1 1202 umull r1, r2, r1, r2 8001a00: 0912 lsrs r2, r2, #4 if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 8001a02: 4915 ldr r1, [pc, #84] @ (8001a58 ) 8001a04: 4419 add r1, r3 8001a06: 29a8 cmp r1, #168 @ 0xa8 8001a08: d91e bls.n 8001a48 (stream_baseaddress >= ((uint32_t)DMA2_Stream0))) { stream_number += 8U; } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 8001a0a: 4b14 ldr r3, [pc, #80] @ (8001a5c ) 8001a0c: 4413 add r3, r2 8001a0e: 009b lsls r3, r3, #2 8001a10: 6603 str r3, [r0, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8001a12: 4b13 ldr r3, [pc, #76] @ (8001a60 ) 8001a14: 6643 str r3, [r0, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8001a16: f002 021f and.w r2, r2, #31 8001a1a: 2301 movs r3, #1 8001a1c: 4093 lsls r3, r2 8001a1e: 6683 str r3, [r0, #104] @ 0x68 } } 8001a20: 4770 bx lr stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 8001a22: b2db uxtb r3, r3 8001a24: 3b08 subs r3, #8 8001a26: 4a0f ldr r2, [pc, #60] @ (8001a64 ) 8001a28: fba2 2303 umull r2, r3, r2, r3 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 8001a2c: 4a0e ldr r2, [pc, #56] @ (8001a68 ) 8001a2e: eb02 1213 add.w r2, r2, r3, lsr #4 8001a32: 0092 lsls r2, r2, #2 8001a34: 6602 str r2, [r0, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 8001a36: 4a0d ldr r2, [pc, #52] @ (8001a6c ) 8001a38: 6642 str r2, [r0, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8001a3a: f3c3 1304 ubfx r3, r3, #4, #5 8001a3e: 2201 movs r2, #1 8001a40: fa02 f303 lsl.w r3, r2, r3 8001a44: 6683 str r3, [r0, #104] @ 0x68 8001a46: 4770 bx lr stream_number += 8U; 8001a48: 3208 adds r2, #8 8001a4a: e7de b.n 8001a0a 8001a4c: 58025408 .word 0x58025408 8001a50: 5802541c .word 0x5802541c 8001a54: aaaaaaab .word 0xaaaaaaab 8001a58: bffdfbf0 .word 0xbffdfbf0 8001a5c: 10008200 .word 0x10008200 8001a60: 40020880 .word 0x40020880 8001a64: cccccccd .word 0xcccccccd 8001a68: 16009600 .word 0x16009600 8001a6c: 58025880 .word 0x58025880 08001a70 : * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8001a70: 7901 ldrb r1, [r0, #4] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 8001a72: 1e4a subs r2, r1, #1 8001a74: 2a07 cmp r2, #7 8001a76: d82b bhi.n 8001ad0 { 8001a78: b430 push {r4, r5} { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8001a7a: 6803 ldr r3, [r0, #0] 8001a7c: 4d15 ldr r5, [pc, #84] @ (8001ad4 ) 8001a7e: 4c16 ldr r4, [pc, #88] @ (8001ad8 ) 8001a80: 42a3 cmp r3, r4 8001a82: bf18 it ne 8001a84: 42ab cmpne r3, r5 8001a86: d018 beq.n 8001aba 8001a88: 3414 adds r4, #20 8001a8a: 42a3 cmp r3, r4 8001a8c: d015 beq.n 8001aba 8001a8e: 3414 adds r4, #20 8001a90: 42a3 cmp r3, r4 8001a92: d012 beq.n 8001aba 8001a94: 3414 adds r4, #20 8001a96: 42a3 cmp r3, r4 8001a98: d00f beq.n 8001aba 8001a9a: 3414 adds r4, #20 8001a9c: 42a3 cmp r3, r4 8001a9e: d00c beq.n 8001aba 8001aa0: 3414 adds r4, #20 8001aa2: 42a3 cmp r3, r4 8001aa4: d009 beq.n 8001aba 8001aa6: 3414 adds r4, #20 8001aa8: 42a3 cmp r3, r4 8001aaa: d006 beq.n 8001aba hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8001aac: 4b0b ldr r3, [pc, #44] @ (8001adc ) 8001aae: 440b add r3, r1 8001ab0: 009b lsls r3, r3, #2 8001ab2: 66c3 str r3, [r0, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8001ab4: 4b0a ldr r3, [pc, #40] @ (8001ae0 ) 8001ab6: 6703 str r3, [r0, #112] @ 0x70 8001ab8: e005 b.n 8001ac6 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 8001aba: 4b0a ldr r3, [pc, #40] @ (8001ae4 ) 8001abc: 440b add r3, r1 8001abe: 009b lsls r3, r3, #2 8001ac0: 66c3 str r3, [r0, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 8001ac2: 4b09 ldr r3, [pc, #36] @ (8001ae8 ) 8001ac4: 6703 str r3, [r0, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 8001ac6: 2301 movs r3, #1 8001ac8: 4093 lsls r3, r2 8001aca: 6743 str r3, [r0, #116] @ 0x74 } } 8001acc: bc30 pop {r4, r5} 8001ace: 4770 bx lr 8001ad0: 4770 bx lr 8001ad2: bf00 nop 8001ad4: 58025408 .word 0x58025408 8001ad8: 5802541c .word 0x5802541c 8001adc: 1000823f .word 0x1000823f 8001ae0: 40020940 .word 0x40020940 8001ae4: 1600963f .word 0x1600963f 8001ae8: 58025940 .word 0x58025940 08001aec : { 8001aec: b570 push {r4, r5, r6, lr} 8001aee: 4604 mov r4, r0 uint32_t tickstart = HAL_GetTick(); 8001af0: f7ff f834 bl 8000b5c if(hdma == NULL) 8001af4: 2c00 cmp r4, #0 8001af6: f000 81d9 beq.w 8001eac 8001afa: 4605 mov r5, r0 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8001afc: 6823 ldr r3, [r4, #0] 8001afe: 4963 ldr r1, [pc, #396] @ (8001c8c ) 8001b00: 4a63 ldr r2, [pc, #396] @ (8001c90 ) 8001b02: 4293 cmp r3, r2 8001b04: bf18 it ne 8001b06: 428b cmpne r3, r1 8001b08: bf0c ite eq 8001b0a: 2101 moveq r1, #1 8001b0c: 2100 movne r1, #0 8001b0e: d070 beq.n 8001bf2 8001b10: 3218 adds r2, #24 8001b12: 4293 cmp r3, r2 8001b14: d06d beq.n 8001bf2 8001b16: 3218 adds r2, #24 8001b18: 4293 cmp r3, r2 8001b1a: d06a beq.n 8001bf2 8001b1c: 3218 adds r2, #24 8001b1e: 4293 cmp r3, r2 8001b20: d067 beq.n 8001bf2 8001b22: 3218 adds r2, #24 8001b24: 4293 cmp r3, r2 8001b26: d064 beq.n 8001bf2 8001b28: 3218 adds r2, #24 8001b2a: 4293 cmp r3, r2 8001b2c: d061 beq.n 8001bf2 8001b2e: 3218 adds r2, #24 8001b30: 4293 cmp r3, r2 8001b32: d05e beq.n 8001bf2 8001b34: f502 7256 add.w r2, r2, #856 @ 0x358 8001b38: 4293 cmp r3, r2 8001b3a: d05a beq.n 8001bf2 8001b3c: 3218 adds r2, #24 8001b3e: 4293 cmp r3, r2 8001b40: d057 beq.n 8001bf2 8001b42: 3218 adds r2, #24 8001b44: 4293 cmp r3, r2 8001b46: d054 beq.n 8001bf2 8001b48: 3218 adds r2, #24 8001b4a: 4293 cmp r3, r2 8001b4c: d051 beq.n 8001bf2 8001b4e: 3218 adds r2, #24 8001b50: 4293 cmp r3, r2 8001b52: d04e beq.n 8001bf2 8001b54: 3218 adds r2, #24 8001b56: 4293 cmp r3, r2 8001b58: d04b beq.n 8001bf2 8001b5a: 3218 adds r2, #24 8001b5c: 4293 cmp r3, r2 8001b5e: d048 beq.n 8001bf2 8001b60: 3218 adds r2, #24 8001b62: 4293 cmp r3, r2 8001b64: d045 beq.n 8001bf2 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8001b66: 494b ldr r1, [pc, #300] @ (8001c94 ) 8001b68: 4a4b ldr r2, [pc, #300] @ (8001c98 ) 8001b6a: 4293 cmp r3, r2 8001b6c: bf18 it ne 8001b6e: 428b cmpne r3, r1 8001b70: f000 8154 beq.w 8001e1c 8001b74: 4a49 ldr r2, [pc, #292] @ (8001c9c ) 8001b76: 4293 cmp r3, r2 8001b78: f000 8150 beq.w 8001e1c 8001b7c: 3214 adds r2, #20 8001b7e: 4293 cmp r3, r2 8001b80: f000 814c beq.w 8001e1c 8001b84: 3214 adds r2, #20 8001b86: 4293 cmp r3, r2 8001b88: f000 8148 beq.w 8001e1c 8001b8c: 3214 adds r2, #20 8001b8e: 4293 cmp r3, r2 8001b90: f000 8144 beq.w 8001e1c 8001b94: 3214 adds r2, #20 8001b96: 4293 cmp r3, r2 8001b98: f000 8140 beq.w 8001e1c 8001b9c: 3214 adds r2, #20 8001b9e: 4293 cmp r3, r2 8001ba0: f000 813c beq.w 8001e1c 8001ba4: 4a3e ldr r2, [pc, #248] @ (8001ca0 ) 8001ba6: 4293 cmp r3, r2 8001ba8: f000 8138 beq.w 8001e1c 8001bac: 3214 adds r2, #20 8001bae: 4293 cmp r3, r2 8001bb0: f000 8134 beq.w 8001e1c 8001bb4: 3214 adds r2, #20 8001bb6: 4293 cmp r3, r2 8001bb8: f000 8130 beq.w 8001e1c 8001bbc: 3214 adds r2, #20 8001bbe: 4293 cmp r3, r2 8001bc0: f000 812c beq.w 8001e1c 8001bc4: 3214 adds r2, #20 8001bc6: 4293 cmp r3, r2 8001bc8: f000 8128 beq.w 8001e1c 8001bcc: 3214 adds r2, #20 8001bce: 4293 cmp r3, r2 8001bd0: f000 8124 beq.w 8001e1c 8001bd4: 3214 adds r2, #20 8001bd6: 4293 cmp r3, r2 8001bd8: f000 8120 beq.w 8001e1c 8001bdc: 3214 adds r2, #20 8001bde: 4293 cmp r3, r2 8001be0: f000 811c beq.w 8001e1c hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8001be4: 2340 movs r3, #64 @ 0x40 8001be6: 6563 str r3, [r4, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8001be8: 2303 movs r3, #3 8001bea: f884 3035 strb.w r3, [r4, #53] @ 0x35 return HAL_ERROR; 8001bee: 2001 movs r0, #1 8001bf0: e04a b.n 8001c88 hdma->State = HAL_DMA_STATE_BUSY; 8001bf2: 2202 movs r2, #2 8001bf4: f884 2035 strb.w r2, [r4, #53] @ 0x35 __HAL_UNLOCK(hdma); 8001bf8: 2200 movs r2, #0 8001bfa: f884 2034 strb.w r2, [r4, #52] @ 0x34 __HAL_DMA_DISABLE(hdma); 8001bfe: bb79 cbnz r1, 8001c60 8001c00: 4a28 ldr r2, [pc, #160] @ (8001ca4 ) 8001c02: 4293 cmp r3, r2 8001c04: d02c beq.n 8001c60 8001c06: 3218 adds r2, #24 8001c08: 4293 cmp r3, r2 8001c0a: d029 beq.n 8001c60 8001c0c: 3218 adds r2, #24 8001c0e: 4293 cmp r3, r2 8001c10: d026 beq.n 8001c60 8001c12: 3218 adds r2, #24 8001c14: 4293 cmp r3, r2 8001c16: d023 beq.n 8001c60 8001c18: 3218 adds r2, #24 8001c1a: 4293 cmp r3, r2 8001c1c: d020 beq.n 8001c60 8001c1e: 3218 adds r2, #24 8001c20: 4293 cmp r3, r2 8001c22: d01d beq.n 8001c60 8001c24: f502 7256 add.w r2, r2, #856 @ 0x358 8001c28: 4293 cmp r3, r2 8001c2a: d019 beq.n 8001c60 8001c2c: 3218 adds r2, #24 8001c2e: 4293 cmp r3, r2 8001c30: d016 beq.n 8001c60 8001c32: 3218 adds r2, #24 8001c34: 4293 cmp r3, r2 8001c36: d013 beq.n 8001c60 8001c38: 3218 adds r2, #24 8001c3a: 4293 cmp r3, r2 8001c3c: d010 beq.n 8001c60 8001c3e: 3218 adds r2, #24 8001c40: 4293 cmp r3, r2 8001c42: d00d beq.n 8001c60 8001c44: 3218 adds r2, #24 8001c46: 4293 cmp r3, r2 8001c48: d00a beq.n 8001c60 8001c4a: 3218 adds r2, #24 8001c4c: 4293 cmp r3, r2 8001c4e: d007 beq.n 8001c60 8001c50: 3218 adds r2, #24 8001c52: 4293 cmp r3, r2 8001c54: d004 beq.n 8001c60 8001c56: 681a ldr r2, [r3, #0] 8001c58: f022 0201 bic.w r2, r2, #1 8001c5c: 601a str r2, [r3, #0] 8001c5e: e003 b.n 8001c68 8001c60: 681a ldr r2, [r3, #0] 8001c62: f022 0201 bic.w r2, r2, #1 8001c66: 601a str r2, [r3, #0] while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8001c68: 6823 ldr r3, [r4, #0] 8001c6a: 681a ldr r2, [r3, #0] 8001c6c: f012 0f01 tst.w r2, #1 8001c70: d01a beq.n 8001ca8 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8001c72: f7fe ff73 bl 8000b5c 8001c76: 1b43 subs r3, r0, r5 8001c78: 2b05 cmp r3, #5 8001c7a: d9f5 bls.n 8001c68 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8001c7c: 2320 movs r3, #32 8001c7e: 6563 str r3, [r4, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8001c80: 2303 movs r3, #3 8001c82: f884 3035 strb.w r3, [r4, #53] @ 0x35 return HAL_ERROR; 8001c86: 2001 movs r0, #1 } 8001c88: bd70 pop {r4, r5, r6, pc} 8001c8a: bf00 nop 8001c8c: 40020010 .word 0x40020010 8001c90: 40020028 .word 0x40020028 8001c94: 48022c08 .word 0x48022c08 8001c98: 48022c1c .word 0x48022c1c 8001c9c: 48022c30 .word 0x48022c30 8001ca0: 58025408 .word 0x58025408 8001ca4: 40020040 .word 0x40020040 registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 8001ca8: 681a ldr r2, [r3, #0] registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8001caa: 4981 ldr r1, [pc, #516] @ (8001eb0 ) 8001cac: 4011 ands r1, r2 registerValue |= hdma->Init.Direction | 8001cae: 68a2 ldr r2, [r4, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001cb0: 68e0 ldr r0, [r4, #12] registerValue |= hdma->Init.Direction | 8001cb2: 4302 orrs r2, r0 hdma->Init.PeriphInc | hdma->Init.MemInc | 8001cb4: 6920 ldr r0, [r4, #16] 8001cb6: 4302 orrs r2, r0 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001cb8: 6960 ldr r0, [r4, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001cba: 4302 orrs r2, r0 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001cbc: 69a0 ldr r0, [r4, #24] 8001cbe: 4302 orrs r2, r0 hdma->Init.Mode | hdma->Init.Priority; 8001cc0: 69e0 ldr r0, [r4, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001cc2: 4302 orrs r2, r0 hdma->Init.Mode | hdma->Init.Priority; 8001cc4: 6a20 ldr r0, [r4, #32] 8001cc6: 4302 orrs r2, r0 registerValue |= hdma->Init.Direction | 8001cc8: 430a orrs r2, r1 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001cca: 6a61 ldr r1, [r4, #36] @ 0x24 8001ccc: 2904 cmp r1, #4 8001cce: f000 8090 beq.w 8001df2 if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8001cd2: 6861 ldr r1, [r4, #4] 8001cd4: 2952 cmp r1, #82 @ 0x52 8001cd6: f200 8096 bhi.w 8001e06 8001cda: 293f cmp r1, #63 @ 0x3f 8001cdc: f0c0 808e bcc.w 8001dfc 8001ce0: 393f subs r1, #63 @ 0x3f 8001ce2: 4874 ldr r0, [pc, #464] @ (8001eb4 ) 8001ce4: fa20 f101 lsr.w r1, r0, r1 8001ce8: f011 0f01 tst.w r1, #1 8001cec: d001 beq.n 8001cf2 registerValue |= DMA_SxCR_TRBUFF; 8001cee: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8001cf2: 601a str r2, [r3, #0] registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 8001cf4: 6826 ldr r6, [r4, #0] 8001cf6: 6975 ldr r5, [r6, #20] registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8001cf8: f025 0507 bic.w r5, r5, #7 registerValue |= hdma->Init.FIFOMode; 8001cfc: 6a63 ldr r3, [r4, #36] @ 0x24 8001cfe: 431d orrs r5, r3 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8001d00: 2b04 cmp r3, #4 8001d02: d108 bne.n 8001d16 registerValue |= hdma->Init.FIFOThreshold; 8001d04: 6aa3 ldr r3, [r4, #40] @ 0x28 8001d06: 431d orrs r5, r3 if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8001d08: 6ae3 ldr r3, [r4, #44] @ 0x2c 8001d0a: b123 cbz r3, 8001d16 if (DMA_CheckFifoParam(hdma) != HAL_OK) 8001d0c: 4620 mov r0, r4 8001d0e: f7ff fe0f bl 8001930 8001d12: 2800 cmp r0, #0 8001d14: d17c bne.n 8001e10 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 8001d16: 6175 str r5, [r6, #20] regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8001d18: 4620 mov r0, r4 8001d1a: f7ff fdb1 bl 8001880 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8001d1e: 6de3 ldr r3, [r4, #92] @ 0x5c 8001d20: f003 021f and.w r2, r3, #31 8001d24: 233f movs r3, #63 @ 0x3f 8001d26: 4093 lsls r3, r2 8001d28: 6083 str r3, [r0, #8] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8001d2a: 6823 ldr r3, [r4, #0] 8001d2c: 4962 ldr r1, [pc, #392] @ (8001eb8 ) 8001d2e: 4a63 ldr r2, [pc, #396] @ (8001ebc ) 8001d30: 4293 cmp r3, r2 8001d32: bf18 it ne 8001d34: 428b cmpne r3, r1 8001d36: d042 beq.n 8001dbe 8001d38: 3218 adds r2, #24 8001d3a: 4293 cmp r3, r2 8001d3c: d03f beq.n 8001dbe 8001d3e: 3218 adds r2, #24 8001d40: 4293 cmp r3, r2 8001d42: d03c beq.n 8001dbe 8001d44: 3218 adds r2, #24 8001d46: 4293 cmp r3, r2 8001d48: d039 beq.n 8001dbe 8001d4a: 3218 adds r2, #24 8001d4c: 4293 cmp r3, r2 8001d4e: d036 beq.n 8001dbe 8001d50: 3218 adds r2, #24 8001d52: 4293 cmp r3, r2 8001d54: d033 beq.n 8001dbe 8001d56: 3218 adds r2, #24 8001d58: 4293 cmp r3, r2 8001d5a: d030 beq.n 8001dbe 8001d5c: f502 7256 add.w r2, r2, #856 @ 0x358 8001d60: 4293 cmp r3, r2 8001d62: d02c beq.n 8001dbe 8001d64: 3218 adds r2, #24 8001d66: 4293 cmp r3, r2 8001d68: d029 beq.n 8001dbe 8001d6a: 3218 adds r2, #24 8001d6c: 4293 cmp r3, r2 8001d6e: d026 beq.n 8001dbe 8001d70: 3218 adds r2, #24 8001d72: 4293 cmp r3, r2 8001d74: d023 beq.n 8001dbe 8001d76: 3218 adds r2, #24 8001d78: 4293 cmp r3, r2 8001d7a: d020 beq.n 8001dbe 8001d7c: 3218 adds r2, #24 8001d7e: 4293 cmp r3, r2 8001d80: d01d beq.n 8001dbe 8001d82: 3218 adds r2, #24 8001d84: 4293 cmp r3, r2 8001d86: d01a beq.n 8001dbe 8001d88: 3218 adds r2, #24 8001d8a: 4293 cmp r3, r2 8001d8c: d017 beq.n 8001dbe 8001d8e: 4a4c ldr r2, [pc, #304] @ (8001ec0 ) 8001d90: 4293 cmp r3, r2 8001d92: d014 beq.n 8001dbe 8001d94: 3214 adds r2, #20 8001d96: 4293 cmp r3, r2 8001d98: d011 beq.n 8001dbe 8001d9a: 3214 adds r2, #20 8001d9c: 4293 cmp r3, r2 8001d9e: d00e beq.n 8001dbe 8001da0: 3214 adds r2, #20 8001da2: 4293 cmp r3, r2 8001da4: d00b beq.n 8001dbe 8001da6: 3214 adds r2, #20 8001da8: 4293 cmp r3, r2 8001daa: d008 beq.n 8001dbe 8001dac: 3214 adds r2, #20 8001dae: 4293 cmp r3, r2 8001db0: d005 beq.n 8001dbe 8001db2: 3214 adds r2, #20 8001db4: 4293 cmp r3, r2 8001db6: d002 beq.n 8001dbe 8001db8: 3214 adds r2, #20 8001dba: 4293 cmp r3, r2 8001dbc: d113 bne.n 8001de6 DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8001dbe: 4620 mov r0, r4 8001dc0: f7ff fe00 bl 80019c4 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8001dc4: 68a3 ldr r3, [r4, #8] 8001dc6: 2b80 cmp r3, #128 @ 0x80 8001dc8: d063 beq.n 8001e92 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8001dca: 6e23 ldr r3, [r4, #96] @ 0x60 8001dcc: 7922 ldrb r2, [r4, #4] 8001dce: 601a str r2, [r3, #0] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001dd0: 6e63 ldr r3, [r4, #100] @ 0x64 8001dd2: 6ea2 ldr r2, [r4, #104] @ 0x68 8001dd4: 605a str r2, [r3, #4] if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8001dd6: 6863 ldr r3, [r4, #4] 8001dd8: 3b01 subs r3, #1 8001dda: 2b07 cmp r3, #7 8001ddc: d95c bls.n 8001e98 hdma->DMAmuxRequestGen = 0U; 8001dde: 2300 movs r3, #0 8001de0: 66e3 str r3, [r4, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8001de2: 6723 str r3, [r4, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8001de4: 6763 str r3, [r4, #116] @ 0x74 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001de6: 2000 movs r0, #0 8001de8: 6560 str r0, [r4, #84] @ 0x54 hdma->State = HAL_DMA_STATE_READY; 8001dea: 2301 movs r3, #1 8001dec: f884 3035 strb.w r3, [r4, #53] @ 0x35 return HAL_OK; 8001df0: e74a b.n 8001c88 registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8001df2: 6ae1 ldr r1, [r4, #44] @ 0x2c 8001df4: 6b20 ldr r0, [r4, #48] @ 0x30 8001df6: 4301 orrs r1, r0 8001df8: 430a orrs r2, r1 8001dfa: e76a b.n 8001cd2 8001dfc: 3929 subs r1, #41 @ 0x29 8001dfe: 2905 cmp r1, #5 8001e00: f63f af77 bhi.w 8001cf2 8001e04: e773 b.n 8001cee 8001e06: 3974 subs r1, #116 @ 0x74 8001e08: 2903 cmp r1, #3 8001e0a: f63f af72 bhi.w 8001cf2 8001e0e: e76e b.n 8001cee hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8001e10: 2340 movs r3, #64 @ 0x40 8001e12: 6563 str r3, [r4, #84] @ 0x54 hdma->State = HAL_DMA_STATE_READY; 8001e14: 2001 movs r0, #1 8001e16: f884 0035 strb.w r0, [r4, #53] @ 0x35 return HAL_ERROR; 8001e1a: e735 b.n 8001c88 hdma->State = HAL_DMA_STATE_BUSY; 8001e1c: 2202 movs r2, #2 8001e1e: f884 2035 strb.w r2, [r4, #53] @ 0x35 __HAL_UNLOCK(hdma); 8001e22: 2200 movs r2, #0 8001e24: f884 2034 strb.w r2, [r4, #52] @ 0x34 registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 8001e28: 6819 ldr r1, [r3, #0] registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8001e2a: f36f 1110 bfc r1, #4, #13 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8001e2e: 68a2 ldr r2, [r4, #8] 8001e30: 2a40 cmp r2, #64 @ 0x40 8001e32: d02c beq.n 8001e8e 8001e34: 2a80 cmp r2, #128 @ 0x80 8001e36: d027 beq.n 8001e88 8001e38: 2200 movs r2, #0 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8001e3a: 68e0 ldr r0, [r4, #12] registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8001e3c: ea42 02d0 orr.w r2, r2, r0, lsr #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8001e40: 6920 ldr r0, [r4, #16] DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8001e42: ea42 02d0 orr.w r2, r2, r0, lsr #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8001e46: 6960 ldr r0, [r4, #20] DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8001e48: ea42 02d0 orr.w r2, r2, r0, lsr #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8001e4c: 69a0 ldr r0, [r4, #24] DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8001e4e: ea42 02d0 orr.w r2, r2, r0, lsr #3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8001e52: 69e0 ldr r0, [r4, #28] DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8001e54: ea42 02d0 orr.w r2, r2, r0, lsr #3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8001e58: 6a20 ldr r0, [r4, #32] DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8001e5a: ea42 1210 orr.w r2, r2, r0, lsr #4 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8001e5e: 430a orrs r2, r1 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8001e60: 601a str r2, [r3, #0] hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8001e62: 6822 ldr r2, [r4, #0] 8001e64: 4b17 ldr r3, [pc, #92] @ (8001ec4 ) 8001e66: 4413 add r3, r2 8001e68: 4a17 ldr r2, [pc, #92] @ (8001ec8 ) 8001e6a: fba2 2303 umull r2, r3, r2, r3 8001e6e: 091b lsrs r3, r3, #4 8001e70: 009b lsls r3, r3, #2 8001e72: 65e3 str r3, [r4, #92] @ 0x5c regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8001e74: 4620 mov r0, r4 8001e76: f7ff fd03 bl 8001880 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8001e7a: 6de2 ldr r2, [r4, #92] @ 0x5c 8001e7c: f002 011f and.w r1, r2, #31 8001e80: 2201 movs r2, #1 8001e82: 408a lsls r2, r1 8001e84: 6042 str r2, [r0, #4] 8001e86: e750 b.n 8001d2a registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8001e88: f44f 4280 mov.w r2, #16384 @ 0x4000 8001e8c: e7d5 b.n 8001e3a 8001e8e: 2210 movs r2, #16 8001e90: e7d3 b.n 8001e3a hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8001e92: 2300 movs r3, #0 8001e94: 6063 str r3, [r4, #4] 8001e96: e798 b.n 8001dca DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8001e98: 4620 mov r0, r4 8001e9a: f7ff fde9 bl 8001a70 hdma->DMAmuxRequestGen->RGCR = 0U; 8001e9e: 6ee3 ldr r3, [r4, #108] @ 0x6c 8001ea0: 2200 movs r2, #0 8001ea2: 601a str r2, [r3, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001ea4: 6f23 ldr r3, [r4, #112] @ 0x70 8001ea6: 6f62 ldr r2, [r4, #116] @ 0x74 8001ea8: 605a str r2, [r3, #4] 8001eaa: e79c b.n 8001de6 return HAL_ERROR; 8001eac: 2001 movs r0, #1 8001eae: e6eb b.n 8001c88 8001eb0: fe10803f .word 0xfe10803f 8001eb4: 000f030f .word 0x000f030f 8001eb8: 40020010 .word 0x40020010 8001ebc: 40020028 .word 0x40020028 8001ec0: 58025408 .word 0x58025408 8001ec4: a7fdabf8 .word 0xa7fdabf8 8001ec8: cccccccd .word 0xcccccccd 08001ecc : { 8001ecc: b5f0 push {r4, r5, r6, r7, lr} 8001ece: b083 sub sp, #12 8001ed0: 4604 mov r4, r0 __IO uint32_t count = 0U; 8001ed2: 2300 movs r3, #0 8001ed4: 9301 str r3, [sp, #4] uint32_t timeout = SystemCoreClock / 9600U; 8001ed6: 4b89 ldr r3, [pc, #548] @ (80020fc ) 8001ed8: 681d ldr r5, [r3, #0] 8001eda: 4b89 ldr r3, [pc, #548] @ (8002100 ) 8001edc: fba3 3505 umull r3, r5, r3, r5 8001ee0: 0aad lsrs r5, r5, #10 DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8001ee2: 6d87 ldr r7, [r0, #88] @ 0x58 tmpisr_dma = regs_dma->ISR; 8001ee4: 683e ldr r6, [r7, #0] tmpisr_bdma = regs_bdma->ISR; 8001ee6: f8d7 c000 ldr.w ip, [r7] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8001eea: 6803 ldr r3, [r0, #0] 8001eec: 4985 ldr r1, [pc, #532] @ (8002104 ) 8001eee: 4886 ldr r0, [pc, #536] @ (8002108 ) 8001ef0: 4283 cmp r3, r0 8001ef2: bf18 it ne 8001ef4: 428b cmpne r3, r1 8001ef6: bf0c ite eq 8001ef8: 2001 moveq r0, #1 8001efa: 2000 movne r0, #0 8001efc: d079 beq.n 8001ff2 8001efe: 4a83 ldr r2, [pc, #524] @ (800210c ) 8001f00: 4293 cmp r3, r2 8001f02: d076 beq.n 8001ff2 8001f04: 3218 adds r2, #24 8001f06: 4293 cmp r3, r2 8001f08: d073 beq.n 8001ff2 8001f0a: 3218 adds r2, #24 8001f0c: 4293 cmp r3, r2 8001f0e: d070 beq.n 8001ff2 8001f10: 3218 adds r2, #24 8001f12: 4293 cmp r3, r2 8001f14: d06d beq.n 8001ff2 8001f16: 3218 adds r2, #24 8001f18: 4293 cmp r3, r2 8001f1a: d06a beq.n 8001ff2 8001f1c: 3218 adds r2, #24 8001f1e: 4293 cmp r3, r2 8001f20: d067 beq.n 8001ff2 8001f22: f502 7256 add.w r2, r2, #856 @ 0x358 8001f26: 4293 cmp r3, r2 8001f28: d063 beq.n 8001ff2 8001f2a: 3218 adds r2, #24 8001f2c: 4293 cmp r3, r2 8001f2e: d060 beq.n 8001ff2 8001f30: 3218 adds r2, #24 8001f32: 4293 cmp r3, r2 8001f34: d05d beq.n 8001ff2 8001f36: 3218 adds r2, #24 8001f38: 4293 cmp r3, r2 8001f3a: d05a beq.n 8001ff2 8001f3c: 3218 adds r2, #24 8001f3e: 4293 cmp r3, r2 8001f40: d057 beq.n 8001ff2 8001f42: 3218 adds r2, #24 8001f44: 4293 cmp r3, r2 8001f46: d054 beq.n 8001ff2 8001f48: 3218 adds r2, #24 8001f4a: 4293 cmp r3, r2 8001f4c: d051 beq.n 8001ff2 8001f4e: 3218 adds r2, #24 8001f50: 4293 cmp r3, r2 8001f52: d04e beq.n 8001ff2 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8001f54: 496e ldr r1, [pc, #440] @ (8002110 ) 8001f56: 4a6f ldr r2, [pc, #444] @ (8002114 ) 8001f58: 4293 cmp r3, r2 8001f5a: bf18 it ne 8001f5c: 428b cmpne r3, r1 8001f5e: d02a beq.n 8001fb6 8001f60: 4a6d ldr r2, [pc, #436] @ (8002118 ) 8001f62: 4293 cmp r3, r2 8001f64: d027 beq.n 8001fb6 8001f66: 3214 adds r2, #20 8001f68: 4293 cmp r3, r2 8001f6a: d024 beq.n 8001fb6 8001f6c: 3214 adds r2, #20 8001f6e: 4293 cmp r3, r2 8001f70: d021 beq.n 8001fb6 8001f72: 3214 adds r2, #20 8001f74: 4293 cmp r3, r2 8001f76: d01e beq.n 8001fb6 8001f78: 3214 adds r2, #20 8001f7a: 4293 cmp r3, r2 8001f7c: d01b beq.n 8001fb6 8001f7e: 3214 adds r2, #20 8001f80: 4293 cmp r3, r2 8001f82: d018 beq.n 8001fb6 8001f84: 4a65 ldr r2, [pc, #404] @ (800211c ) 8001f86: 4293 cmp r3, r2 8001f88: d015 beq.n 8001fb6 8001f8a: 3214 adds r2, #20 8001f8c: 4293 cmp r3, r2 8001f8e: d012 beq.n 8001fb6 8001f90: 3214 adds r2, #20 8001f92: 4293 cmp r3, r2 8001f94: d00f beq.n 8001fb6 8001f96: 3214 adds r2, #20 8001f98: 4293 cmp r3, r2 8001f9a: d00c beq.n 8001fb6 8001f9c: 3214 adds r2, #20 8001f9e: 4293 cmp r3, r2 8001fa0: d009 beq.n 8001fb6 8001fa2: 3214 adds r2, #20 8001fa4: 4293 cmp r3, r2 8001fa6: d006 beq.n 8001fb6 8001fa8: 3214 adds r2, #20 8001faa: 4293 cmp r3, r2 8001fac: d003 beq.n 8001fb6 8001fae: 3214 adds r2, #20 8001fb0: 4293 cmp r3, r2 8001fb2: f040 8261 bne.w 8002478 ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 8001fb6: 681a ldr r2, [r3, #0] if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 8001fb8: 6de1 ldr r1, [r4, #92] @ 0x5c 8001fba: f001 011f and.w r1, r1, #31 8001fbe: 2004 movs r0, #4 8001fc0: 4088 lsls r0, r1 8001fc2: ea10 0f0c tst.w r0, ip 8001fc6: f000 82a7 beq.w 8002518 8001fca: f012 0f04 tst.w r2, #4 8001fce: f000 82a3 beq.w 8002518 regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 8001fd2: 6078 str r0, [r7, #4] if((ccr_reg & BDMA_CCR_DBM) != 0U) 8001fd4: f412 4f00 tst.w r2, #32768 @ 0x8000 8001fd8: f000 825a beq.w 8002490 if((ccr_reg & BDMA_CCR_CT) == 0U) 8001fdc: f412 3f80 tst.w r2, #65536 @ 0x10000 8001fe0: f040 8250 bne.w 8002484 if(hdma->XferM1HalfCpltCallback != NULL) 8001fe4: 6ca3 ldr r3, [r4, #72] @ 0x48 8001fe6: 2b00 cmp r3, #0 8001fe8: f000 8246 beq.w 8002478 hdma->XferM1HalfCpltCallback(hdma); 8001fec: 4620 mov r0, r4 8001fee: 4798 blx r3 8001ff0: e242 b.n 8002478 if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8001ff2: 6de2 ldr r2, [r4, #92] @ 0x5c 8001ff4: f002 011f and.w r1, r2, #31 8001ff8: 2208 movs r2, #8 8001ffa: 408a lsls r2, r1 8001ffc: 4232 tst r2, r6 8001ffe: d041 beq.n 8002084 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8002000: bb70 cbnz r0, 8002060 8002002: 4a42 ldr r2, [pc, #264] @ (800210c ) 8002004: 4293 cmp r3, r2 8002006: d02b beq.n 8002060 8002008: 3218 adds r2, #24 800200a: 4293 cmp r3, r2 800200c: d028 beq.n 8002060 800200e: 3218 adds r2, #24 8002010: 4293 cmp r3, r2 8002012: d025 beq.n 8002060 8002014: 3218 adds r2, #24 8002016: 4293 cmp r3, r2 8002018: d022 beq.n 8002060 800201a: 3218 adds r2, #24 800201c: 4293 cmp r3, r2 800201e: d01f beq.n 8002060 8002020: 3218 adds r2, #24 8002022: 4293 cmp r3, r2 8002024: d01c beq.n 8002060 8002026: f502 7256 add.w r2, r2, #856 @ 0x358 800202a: 4293 cmp r3, r2 800202c: d018 beq.n 8002060 800202e: 3218 adds r2, #24 8002030: 4293 cmp r3, r2 8002032: d015 beq.n 8002060 8002034: 3218 adds r2, #24 8002036: 4293 cmp r3, r2 8002038: d012 beq.n 8002060 800203a: 3218 adds r2, #24 800203c: 4293 cmp r3, r2 800203e: d00f beq.n 8002060 8002040: 3218 adds r2, #24 8002042: 4293 cmp r3, r2 8002044: d00c beq.n 8002060 8002046: 3218 adds r2, #24 8002048: 4293 cmp r3, r2 800204a: d009 beq.n 8002060 800204c: 3218 adds r2, #24 800204e: 4293 cmp r3, r2 8002050: d006 beq.n 8002060 8002052: 3218 adds r2, #24 8002054: 4293 cmp r3, r2 8002056: d003 beq.n 8002060 8002058: 681a ldr r2, [r3, #0] 800205a: f3c2 02c0 ubfx r2, r2, #3, #1 800205e: e002 b.n 8002066 8002060: 681a ldr r2, [r3, #0] 8002062: f3c2 0280 ubfx r2, r2, #2, #1 8002066: b16a cbz r2, 8002084 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8002068: 681a ldr r2, [r3, #0] 800206a: f022 0204 bic.w r2, r2, #4 800206e: 601a str r2, [r3, #0] regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8002070: 6de3 ldr r3, [r4, #92] @ 0x5c 8002072: f003 021f and.w r2, r3, #31 8002076: 2308 movs r3, #8 8002078: 4093 lsls r3, r2 800207a: 60bb str r3, [r7, #8] hdma->ErrorCode |= HAL_DMA_ERROR_TE; 800207c: 6d63 ldr r3, [r4, #84] @ 0x54 800207e: f043 0301 orr.w r3, r3, #1 8002082: 6563 str r3, [r4, #84] @ 0x54 if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8002084: 6de2 ldr r2, [r4, #92] @ 0x5c 8002086: f002 021f and.w r2, r2, #31 800208a: fa26 f302 lsr.w r3, r6, r2 800208e: f013 0f01 tst.w r3, #1 8002092: d049 beq.n 8002128 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8002094: 6823 ldr r3, [r4, #0] 8002096: 481b ldr r0, [pc, #108] @ (8002104 ) 8002098: 491b ldr r1, [pc, #108] @ (8002108 ) 800209a: 428b cmp r3, r1 800209c: bf18 it ne 800209e: 4283 cmpne r3, r0 80020a0: d03e beq.n 8002120 80020a2: 3118 adds r1, #24 80020a4: 428b cmp r3, r1 80020a6: d03b beq.n 8002120 80020a8: 3118 adds r1, #24 80020aa: 428b cmp r3, r1 80020ac: d038 beq.n 8002120 80020ae: 3118 adds r1, #24 80020b0: 428b cmp r3, r1 80020b2: d035 beq.n 8002120 80020b4: 3118 adds r1, #24 80020b6: 428b cmp r3, r1 80020b8: d032 beq.n 8002120 80020ba: 3118 adds r1, #24 80020bc: 428b cmp r3, r1 80020be: d02f beq.n 8002120 80020c0: 3118 adds r1, #24 80020c2: 428b cmp r3, r1 80020c4: d02c beq.n 8002120 80020c6: f501 7156 add.w r1, r1, #856 @ 0x358 80020ca: 428b cmp r3, r1 80020cc: d028 beq.n 8002120 80020ce: 3118 adds r1, #24 80020d0: 428b cmp r3, r1 80020d2: d025 beq.n 8002120 80020d4: 3118 adds r1, #24 80020d6: 428b cmp r3, r1 80020d8: d022 beq.n 8002120 80020da: 3118 adds r1, #24 80020dc: 428b cmp r3, r1 80020de: d01f beq.n 8002120 80020e0: 3118 adds r1, #24 80020e2: 428b cmp r3, r1 80020e4: d01c beq.n 8002120 80020e6: 3118 adds r1, #24 80020e8: 428b cmp r3, r1 80020ea: d019 beq.n 8002120 80020ec: 3118 adds r1, #24 80020ee: 428b cmp r3, r1 80020f0: d016 beq.n 8002120 80020f2: 3118 adds r1, #24 80020f4: 428b cmp r3, r1 80020f6: d013 beq.n 8002120 80020f8: 681b ldr r3, [r3, #0] 80020fa: e015 b.n 8002128 80020fc: 2000000c .word 0x2000000c 8002100: 1b4e81b5 .word 0x1b4e81b5 8002104: 40020010 .word 0x40020010 8002108: 40020028 .word 0x40020028 800210c: 40020040 .word 0x40020040 8002110: 48022c08 .word 0x48022c08 8002114: 48022c1c .word 0x48022c1c 8002118: 48022c30 .word 0x48022c30 800211c: 58025408 .word 0x58025408 8002120: 695b ldr r3, [r3, #20] 8002122: f013 0f80 tst.w r3, #128 @ 0x80 8002126: d13b bne.n 80021a0 if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8002128: 6de3 ldr r3, [r4, #92] @ 0x5c 800212a: f003 031f and.w r3, r3, #31 800212e: 2204 movs r2, #4 8002130: fa02 f303 lsl.w r3, r2, r3 8002134: 4233 tst r3, r6 8002136: d03f beq.n 80021b8 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8002138: 6822 ldr r2, [r4, #0] 800213a: 4895 ldr r0, [pc, #596] @ (8002390 ) 800213c: 4995 ldr r1, [pc, #596] @ (8002394 ) 800213e: 428a cmp r2, r1 8002140: bf18 it ne 8002142: 4282 cmpne r2, r0 8002144: d034 beq.n 80021b0 8002146: 3118 adds r1, #24 8002148: 428a cmp r2, r1 800214a: d031 beq.n 80021b0 800214c: 3118 adds r1, #24 800214e: 428a cmp r2, r1 8002150: d02e beq.n 80021b0 8002152: 3118 adds r1, #24 8002154: 428a cmp r2, r1 8002156: d02b beq.n 80021b0 8002158: 3118 adds r1, #24 800215a: 428a cmp r2, r1 800215c: d028 beq.n 80021b0 800215e: 3118 adds r1, #24 8002160: 428a cmp r2, r1 8002162: d025 beq.n 80021b0 8002164: 3118 adds r1, #24 8002166: 428a cmp r2, r1 8002168: d022 beq.n 80021b0 800216a: f501 7156 add.w r1, r1, #856 @ 0x358 800216e: 428a cmp r2, r1 8002170: d01e beq.n 80021b0 8002172: 3118 adds r1, #24 8002174: 428a cmp r2, r1 8002176: d01b beq.n 80021b0 8002178: 3118 adds r1, #24 800217a: 428a cmp r2, r1 800217c: d018 beq.n 80021b0 800217e: 3118 adds r1, #24 8002180: 428a cmp r2, r1 8002182: d015 beq.n 80021b0 8002184: 3118 adds r1, #24 8002186: 428a cmp r2, r1 8002188: d012 beq.n 80021b0 800218a: 3118 adds r1, #24 800218c: 428a cmp r2, r1 800218e: d00f beq.n 80021b0 8002190: 3118 adds r1, #24 8002192: 428a cmp r2, r1 8002194: d00c beq.n 80021b0 8002196: 3118 adds r1, #24 8002198: 428a cmp r2, r1 800219a: d009 beq.n 80021b0 800219c: 6813 ldr r3, [r2, #0] 800219e: e00b b.n 80021b8 regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 80021a0: 2301 movs r3, #1 80021a2: 4093 lsls r3, r2 80021a4: 60bb str r3, [r7, #8] hdma->ErrorCode |= HAL_DMA_ERROR_FE; 80021a6: 6d63 ldr r3, [r4, #84] @ 0x54 80021a8: f043 0302 orr.w r3, r3, #2 80021ac: 6563 str r3, [r4, #84] @ 0x54 80021ae: e7bb b.n 8002128 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 80021b0: 6812 ldr r2, [r2, #0] 80021b2: f012 0f02 tst.w r2, #2 80021b6: d13d bne.n 8002234 if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80021b8: 6de3 ldr r3, [r4, #92] @ 0x5c 80021ba: f003 031f and.w r3, r3, #31 80021be: 2210 movs r2, #16 80021c0: fa02 f303 lsl.w r3, r2, r3 80021c4: 4233 tst r3, r6 80021c6: d05f beq.n 8002288 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 80021c8: 6822 ldr r2, [r4, #0] 80021ca: 4871 ldr r0, [pc, #452] @ (8002390 ) 80021cc: 4971 ldr r1, [pc, #452] @ (8002394 ) 80021ce: 428a cmp r2, r1 80021d0: bf18 it ne 80021d2: 4282 cmpne r2, r0 80021d4: d034 beq.n 8002240 80021d6: 3118 adds r1, #24 80021d8: 428a cmp r2, r1 80021da: d031 beq.n 8002240 80021dc: 3118 adds r1, #24 80021de: 428a cmp r2, r1 80021e0: d02e beq.n 8002240 80021e2: 3118 adds r1, #24 80021e4: 428a cmp r2, r1 80021e6: d02b beq.n 8002240 80021e8: 3118 adds r1, #24 80021ea: 428a cmp r2, r1 80021ec: d028 beq.n 8002240 80021ee: 3118 adds r1, #24 80021f0: 428a cmp r2, r1 80021f2: d025 beq.n 8002240 80021f4: 3118 adds r1, #24 80021f6: 428a cmp r2, r1 80021f8: d022 beq.n 8002240 80021fa: f501 7156 add.w r1, r1, #856 @ 0x358 80021fe: 428a cmp r2, r1 8002200: d01e beq.n 8002240 8002202: 3118 adds r1, #24 8002204: 428a cmp r2, r1 8002206: d01b beq.n 8002240 8002208: 3118 adds r1, #24 800220a: 428a cmp r2, r1 800220c: d018 beq.n 8002240 800220e: 3118 adds r1, #24 8002210: 428a cmp r2, r1 8002212: d015 beq.n 8002240 8002214: 3118 adds r1, #24 8002216: 428a cmp r2, r1 8002218: d012 beq.n 8002240 800221a: 3118 adds r1, #24 800221c: 428a cmp r2, r1 800221e: d00f beq.n 8002240 8002220: 3118 adds r1, #24 8002222: 428a cmp r2, r1 8002224: d00c beq.n 8002240 8002226: 3118 adds r1, #24 8002228: 428a cmp r2, r1 800222a: d009 beq.n 8002240 800222c: 6812 ldr r2, [r2, #0] 800222e: f3c2 0280 ubfx r2, r2, #2, #1 8002232: e008 b.n 8002246 regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8002234: 60bb str r3, [r7, #8] hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8002236: 6d63 ldr r3, [r4, #84] @ 0x54 8002238: f043 0304 orr.w r3, r3, #4 800223c: 6563 str r3, [r4, #84] @ 0x54 800223e: e7bb b.n 80021b8 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8002240: 6812 ldr r2, [r2, #0] 8002242: f3c2 02c0 ubfx r2, r2, #3, #1 8002246: b1fa cbz r2, 8002288 regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 8002248: 60bb str r3, [r7, #8] if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800224a: 6823 ldr r3, [r4, #0] 800224c: 681a ldr r2, [r3, #0] 800224e: f412 2f80 tst.w r2, #262144 @ 0x40000 8002252: d00d beq.n 8002270 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8002254: 681b ldr r3, [r3, #0] 8002256: f413 2f00 tst.w r3, #524288 @ 0x80000 800225a: d104 bne.n 8002266 if(hdma->XferHalfCpltCallback != NULL) 800225c: 6c23 ldr r3, [r4, #64] @ 0x40 800225e: b19b cbz r3, 8002288 hdma->XferHalfCpltCallback(hdma); 8002260: 4620 mov r0, r4 8002262: 4798 blx r3 8002264: e010 b.n 8002288 if(hdma->XferM1HalfCpltCallback != NULL) 8002266: 6ca3 ldr r3, [r4, #72] @ 0x48 8002268: b173 cbz r3, 8002288 hdma->XferM1HalfCpltCallback(hdma); 800226a: 4620 mov r0, r4 800226c: 4798 blx r3 800226e: e00b b.n 8002288 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8002270: 681a ldr r2, [r3, #0] 8002272: f412 7f80 tst.w r2, #256 @ 0x100 8002276: d103 bne.n 8002280 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8002278: 681a ldr r2, [r3, #0] 800227a: f022 0208 bic.w r2, r2, #8 800227e: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8002280: 6c23 ldr r3, [r4, #64] @ 0x40 8002282: b10b cbz r3, 8002288 hdma->XferHalfCpltCallback(hdma); 8002284: 4620 mov r0, r4 8002286: 4798 blx r3 if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8002288: 6de3 ldr r3, [r4, #92] @ 0x5c 800228a: f003 031f and.w r3, r3, #31 800228e: 2220 movs r2, #32 8002290: fa02 f303 lsl.w r3, r2, r3 8002294: 4233 tst r3, r6 8002296: f000 8091 beq.w 80023bc if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 800229a: 6822 ldr r2, [r4, #0] 800229c: 483c ldr r0, [pc, #240] @ (8002390 ) 800229e: 493d ldr r1, [pc, #244] @ (8002394 ) 80022a0: 428a cmp r2, r1 80022a2: bf18 it ne 80022a4: 4282 cmpne r2, r0 80022a6: d02e beq.n 8002306 80022a8: 3118 adds r1, #24 80022aa: 428a cmp r2, r1 80022ac: d02b beq.n 8002306 80022ae: 3118 adds r1, #24 80022b0: 428a cmp r2, r1 80022b2: d028 beq.n 8002306 80022b4: 3118 adds r1, #24 80022b6: 428a cmp r2, r1 80022b8: d025 beq.n 8002306 80022ba: 3118 adds r1, #24 80022bc: 428a cmp r2, r1 80022be: d022 beq.n 8002306 80022c0: 3118 adds r1, #24 80022c2: 428a cmp r2, r1 80022c4: d01f beq.n 8002306 80022c6: 3118 adds r1, #24 80022c8: 428a cmp r2, r1 80022ca: d01c beq.n 8002306 80022cc: f501 7156 add.w r1, r1, #856 @ 0x358 80022d0: 428a cmp r2, r1 80022d2: d018 beq.n 8002306 80022d4: 3118 adds r1, #24 80022d6: 428a cmp r2, r1 80022d8: d015 beq.n 8002306 80022da: 3118 adds r1, #24 80022dc: 428a cmp r2, r1 80022de: d012 beq.n 8002306 80022e0: 3118 adds r1, #24 80022e2: 428a cmp r2, r1 80022e4: d00f beq.n 8002306 80022e6: 3118 adds r1, #24 80022e8: 428a cmp r2, r1 80022ea: d00c beq.n 8002306 80022ec: 3118 adds r1, #24 80022ee: 428a cmp r2, r1 80022f0: d009 beq.n 8002306 80022f2: 3118 adds r1, #24 80022f4: 428a cmp r2, r1 80022f6: d006 beq.n 8002306 80022f8: 3118 adds r1, #24 80022fa: 428a cmp r2, r1 80022fc: d003 beq.n 8002306 80022fe: 6812 ldr r2, [r2, #0] 8002300: f3c2 0240 ubfx r2, r2, #1, #1 8002304: e002 b.n 800230c 8002306: 6812 ldr r2, [r2, #0] 8002308: f3c2 1200 ubfx r2, r2, #4, #1 800230c: 2a00 cmp r2, #0 800230e: d055 beq.n 80023bc regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 8002310: 60bb str r3, [r7, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8002312: f894 3035 ldrb.w r3, [r4, #53] @ 0x35 8002316: 2b04 cmp r3, #4 8002318: d00e beq.n 8002338 if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800231a: 6823 ldr r3, [r4, #0] 800231c: 681a ldr r2, [r3, #0] 800231e: f412 2f80 tst.w r2, #262144 @ 0x40000 8002322: d039 beq.n 8002398 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8002324: 681b ldr r3, [r3, #0] 8002326: f413 2f00 tst.w r3, #524288 @ 0x80000 800232a: d12c bne.n 8002386 if(hdma->XferM1CpltCallback != NULL) 800232c: 6c63 ldr r3, [r4, #68] @ 0x44 800232e: 2b00 cmp r3, #0 8002330: d044 beq.n 80023bc hdma->XferM1CpltCallback(hdma); 8002332: 4620 mov r0, r4 8002334: 4798 blx r3 8002336: e041 b.n 80023bc ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8002338: 6822 ldr r2, [r4, #0] 800233a: 6813 ldr r3, [r2, #0] 800233c: f023 0316 bic.w r3, r3, #22 8002340: 6013 str r3, [r2, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8002342: 6822 ldr r2, [r4, #0] 8002344: 6953 ldr r3, [r2, #20] 8002346: f023 0380 bic.w r3, r3, #128 @ 0x80 800234a: 6153 str r3, [r2, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800234c: 6c23 ldr r3, [r4, #64] @ 0x40 800234e: b1b3 cbz r3, 800237e ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8002350: 6822 ldr r2, [r4, #0] 8002352: 6813 ldr r3, [r2, #0] 8002354: f023 0308 bic.w r3, r3, #8 8002358: 6013 str r3, [r2, #0] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800235a: 6de3 ldr r3, [r4, #92] @ 0x5c 800235c: f003 021f and.w r2, r3, #31 8002360: 233f movs r3, #63 @ 0x3f 8002362: 4093 lsls r3, r2 8002364: 60bb str r3, [r7, #8] hdma->State = HAL_DMA_STATE_READY; 8002366: 2301 movs r3, #1 8002368: f884 3035 strb.w r3, [r4, #53] @ 0x35 __HAL_UNLOCK(hdma); 800236c: 2300 movs r3, #0 800236e: f884 3034 strb.w r3, [r4, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8002372: 6d23 ldr r3, [r4, #80] @ 0x50 8002374: 2b00 cmp r3, #0 8002376: d07f beq.n 8002478 hdma->XferAbortCallback(hdma); 8002378: 4620 mov r0, r4 800237a: 4798 blx r3 return; 800237c: e07c b.n 8002478 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800237e: 6ca3 ldr r3, [r4, #72] @ 0x48 8002380: 2b00 cmp r3, #0 8002382: d1e5 bne.n 8002350 8002384: e7e9 b.n 800235a if(hdma->XferCpltCallback != NULL) 8002386: 6be3 ldr r3, [r4, #60] @ 0x3c 8002388: b1c3 cbz r3, 80023bc hdma->XferCpltCallback(hdma); 800238a: 4620 mov r0, r4 800238c: 4798 blx r3 800238e: e015 b.n 80023bc 8002390: 40020010 .word 0x40020010 8002394: 40020028 .word 0x40020028 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8002398: 681a ldr r2, [r3, #0] 800239a: f412 7f80 tst.w r2, #256 @ 0x100 800239e: d109 bne.n 80023b4 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 80023a0: 681a ldr r2, [r3, #0] 80023a2: f022 0210 bic.w r2, r2, #16 80023a6: 601a str r2, [r3, #0] hdma->State = HAL_DMA_STATE_READY; 80023a8: 2301 movs r3, #1 80023aa: f884 3035 strb.w r3, [r4, #53] @ 0x35 __HAL_UNLOCK(hdma); 80023ae: 2300 movs r3, #0 80023b0: f884 3034 strb.w r3, [r4, #52] @ 0x34 if(hdma->XferCpltCallback != NULL) 80023b4: 6be3 ldr r3, [r4, #60] @ 0x3c 80023b6: b10b cbz r3, 80023bc hdma->XferCpltCallback(hdma); 80023b8: 4620 mov r0, r4 80023ba: 4798 blx r3 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 80023bc: 6d63 ldr r3, [r4, #84] @ 0x54 80023be: 2b00 cmp r3, #0 80023c0: d05a beq.n 8002478 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 80023c2: 6d63 ldr r3, [r4, #84] @ 0x54 80023c4: f013 0f01 tst.w r3, #1 80023c8: d052 beq.n 8002470 hdma->State = HAL_DMA_STATE_ABORT; 80023ca: 2304 movs r3, #4 80023cc: f884 3035 strb.w r3, [r4, #53] @ 0x35 __HAL_DMA_DISABLE(hdma); 80023d0: 6823 ldr r3, [r4, #0] 80023d2: 4996 ldr r1, [pc, #600] @ (800262c ) 80023d4: 4a96 ldr r2, [pc, #600] @ (8002630 ) 80023d6: 4293 cmp r3, r2 80023d8: bf18 it ne 80023da: 428b cmpne r3, r1 80023dc: d02f beq.n 800243e 80023de: 3218 adds r2, #24 80023e0: 4293 cmp r3, r2 80023e2: d02c beq.n 800243e 80023e4: 3218 adds r2, #24 80023e6: 4293 cmp r3, r2 80023e8: d029 beq.n 800243e 80023ea: 3218 adds r2, #24 80023ec: 4293 cmp r3, r2 80023ee: d026 beq.n 800243e 80023f0: 3218 adds r2, #24 80023f2: 4293 cmp r3, r2 80023f4: d023 beq.n 800243e 80023f6: 3218 adds r2, #24 80023f8: 4293 cmp r3, r2 80023fa: d020 beq.n 800243e 80023fc: 3218 adds r2, #24 80023fe: 4293 cmp r3, r2 8002400: d01d beq.n 800243e 8002402: f502 7256 add.w r2, r2, #856 @ 0x358 8002406: 4293 cmp r3, r2 8002408: d019 beq.n 800243e 800240a: 3218 adds r2, #24 800240c: 4293 cmp r3, r2 800240e: d016 beq.n 800243e 8002410: 3218 adds r2, #24 8002412: 4293 cmp r3, r2 8002414: d013 beq.n 800243e 8002416: 3218 adds r2, #24 8002418: 4293 cmp r3, r2 800241a: d010 beq.n 800243e 800241c: 3218 adds r2, #24 800241e: 4293 cmp r3, r2 8002420: d00d beq.n 800243e 8002422: 3218 adds r2, #24 8002424: 4293 cmp r3, r2 8002426: d00a beq.n 800243e 8002428: 3218 adds r2, #24 800242a: 4293 cmp r3, r2 800242c: d007 beq.n 800243e 800242e: 3218 adds r2, #24 8002430: 4293 cmp r3, r2 8002432: d004 beq.n 800243e 8002434: 681a ldr r2, [r3, #0] 8002436: f022 0201 bic.w r2, r2, #1 800243a: 601a str r2, [r3, #0] 800243c: e003 b.n 8002446 800243e: 681a ldr r2, [r3, #0] 8002440: f022 0201 bic.w r2, r2, #1 8002444: 601a str r2, [r3, #0] if (++count > timeout) 8002446: 9b01 ldr r3, [sp, #4] 8002448: 3301 adds r3, #1 800244a: 9301 str r3, [sp, #4] 800244c: 42ab cmp r3, r5 800244e: d804 bhi.n 800245a while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 8002450: 6823 ldr r3, [r4, #0] 8002452: 681b ldr r3, [r3, #0] 8002454: f013 0f01 tst.w r3, #1 8002458: d1f5 bne.n 8002446 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800245a: 6823 ldr r3, [r4, #0] 800245c: 681b ldr r3, [r3, #0] 800245e: f013 0f01 tst.w r3, #1 8002462: d00b beq.n 800247c hdma->State = HAL_DMA_STATE_ERROR; 8002464: 2303 movs r3, #3 8002466: f884 3035 strb.w r3, [r4, #53] @ 0x35 __HAL_UNLOCK(hdma); 800246a: 2300 movs r3, #0 800246c: f884 3034 strb.w r3, [r4, #52] @ 0x34 if(hdma->XferErrorCallback != NULL) 8002470: 6ce3 ldr r3, [r4, #76] @ 0x4c 8002472: b10b cbz r3, 8002478 hdma->XferErrorCallback(hdma); 8002474: 4620 mov r0, r4 8002476: 4798 blx r3 } 8002478: b003 add sp, #12 800247a: bdf0 pop {r4, r5, r6, r7, pc} hdma->State = HAL_DMA_STATE_READY; 800247c: 2301 movs r3, #1 800247e: f884 3035 strb.w r3, [r4, #53] @ 0x35 8002482: e7f2 b.n 800246a if(hdma->XferHalfCpltCallback != NULL) 8002484: 6c23 ldr r3, [r4, #64] @ 0x40 8002486: 2b00 cmp r3, #0 8002488: d0f6 beq.n 8002478 hdma->XferHalfCpltCallback(hdma); 800248a: 4620 mov r0, r4 800248c: 4798 blx r3 800248e: e7f3 b.n 8002478 if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8002490: f012 0f20 tst.w r2, #32 8002494: d13a bne.n 800250c __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8002496: 6823 ldr r3, [r4, #0] 8002498: 4964 ldr r1, [pc, #400] @ (800262c ) 800249a: 4a65 ldr r2, [pc, #404] @ (8002630 ) 800249c: 4293 cmp r3, r2 800249e: bf18 it ne 80024a0: 428b cmpne r3, r1 80024a2: d02f beq.n 8002504 80024a4: 3218 adds r2, #24 80024a6: 4293 cmp r3, r2 80024a8: d02c beq.n 8002504 80024aa: 3218 adds r2, #24 80024ac: 4293 cmp r3, r2 80024ae: d029 beq.n 8002504 80024b0: 3218 adds r2, #24 80024b2: 4293 cmp r3, r2 80024b4: d026 beq.n 8002504 80024b6: 3218 adds r2, #24 80024b8: 4293 cmp r3, r2 80024ba: d023 beq.n 8002504 80024bc: 3218 adds r2, #24 80024be: 4293 cmp r3, r2 80024c0: d020 beq.n 8002504 80024c2: 3218 adds r2, #24 80024c4: 4293 cmp r3, r2 80024c6: d01d beq.n 8002504 80024c8: f502 7256 add.w r2, r2, #856 @ 0x358 80024cc: 4293 cmp r3, r2 80024ce: d019 beq.n 8002504 80024d0: 3218 adds r2, #24 80024d2: 4293 cmp r3, r2 80024d4: d016 beq.n 8002504 80024d6: 3218 adds r2, #24 80024d8: 4293 cmp r3, r2 80024da: d013 beq.n 8002504 80024dc: 3218 adds r2, #24 80024de: 4293 cmp r3, r2 80024e0: d010 beq.n 8002504 80024e2: 3218 adds r2, #24 80024e4: 4293 cmp r3, r2 80024e6: d00d beq.n 8002504 80024e8: 3218 adds r2, #24 80024ea: 4293 cmp r3, r2 80024ec: d00a beq.n 8002504 80024ee: 3218 adds r2, #24 80024f0: 4293 cmp r3, r2 80024f2: d007 beq.n 8002504 80024f4: 3218 adds r2, #24 80024f6: 4293 cmp r3, r2 80024f8: d004 beq.n 8002504 80024fa: 681a ldr r2, [r3, #0] 80024fc: f022 0204 bic.w r2, r2, #4 8002500: 601a str r2, [r3, #0] 8002502: e003 b.n 800250c 8002504: 681a ldr r2, [r3, #0] 8002506: f022 0208 bic.w r2, r2, #8 800250a: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 800250c: 6c23 ldr r3, [r4, #64] @ 0x40 800250e: 2b00 cmp r3, #0 8002510: d0b2 beq.n 8002478 hdma->XferHalfCpltCallback(hdma); 8002512: 4620 mov r0, r4 8002514: 4798 blx r3 8002516: e7af b.n 8002478 else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 8002518: 2002 movs r0, #2 800251a: 4088 lsls r0, r1 800251c: ea10 0f0c tst.w r0, ip 8002520: d060 beq.n 80025e4 8002522: f012 0f02 tst.w r2, #2 8002526: d05d beq.n 80025e4 regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 8002528: 6078 str r0, [r7, #4] if((ccr_reg & BDMA_CCR_DBM) != 0U) 800252a: f412 4f00 tst.w r2, #32768 @ 0x8000 800252e: d00e beq.n 800254e if((ccr_reg & BDMA_CCR_CT) == 0U) 8002530: f412 3f80 tst.w r2, #65536 @ 0x10000 8002534: d105 bne.n 8002542 if(hdma->XferM1CpltCallback != NULL) 8002536: 6c63 ldr r3, [r4, #68] @ 0x44 8002538: 2b00 cmp r3, #0 800253a: d09d beq.n 8002478 hdma->XferM1CpltCallback(hdma); 800253c: 4620 mov r0, r4 800253e: 4798 blx r3 8002540: e79a b.n 8002478 if(hdma->XferCpltCallback != NULL) 8002542: 6be3 ldr r3, [r4, #60] @ 0x3c 8002544: 2b00 cmp r3, #0 8002546: d097 beq.n 8002478 hdma->XferCpltCallback(hdma); 8002548: 4620 mov r0, r4 800254a: 4798 blx r3 800254c: e794 b.n 8002478 if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800254e: f012 0f20 tst.w r2, #32 8002552: d140 bne.n 80025d6 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8002554: 6823 ldr r3, [r4, #0] 8002556: 4935 ldr r1, [pc, #212] @ (800262c ) 8002558: 4a35 ldr r2, [pc, #212] @ (8002630 ) 800255a: 4293 cmp r3, r2 800255c: bf18 it ne 800255e: 428b cmpne r3, r1 8002560: d02f beq.n 80025c2 8002562: 3218 adds r2, #24 8002564: 4293 cmp r3, r2 8002566: d02c beq.n 80025c2 8002568: 3218 adds r2, #24 800256a: 4293 cmp r3, r2 800256c: d029 beq.n 80025c2 800256e: 3218 adds r2, #24 8002570: 4293 cmp r3, r2 8002572: d026 beq.n 80025c2 8002574: 3218 adds r2, #24 8002576: 4293 cmp r3, r2 8002578: d023 beq.n 80025c2 800257a: 3218 adds r2, #24 800257c: 4293 cmp r3, r2 800257e: d020 beq.n 80025c2 8002580: 3218 adds r2, #24 8002582: 4293 cmp r3, r2 8002584: d01d beq.n 80025c2 8002586: f502 7256 add.w r2, r2, #856 @ 0x358 800258a: 4293 cmp r3, r2 800258c: d019 beq.n 80025c2 800258e: 3218 adds r2, #24 8002590: 4293 cmp r3, r2 8002592: d016 beq.n 80025c2 8002594: 3218 adds r2, #24 8002596: 4293 cmp r3, r2 8002598: d013 beq.n 80025c2 800259a: 3218 adds r2, #24 800259c: 4293 cmp r3, r2 800259e: d010 beq.n 80025c2 80025a0: 3218 adds r2, #24 80025a2: 4293 cmp r3, r2 80025a4: d00d beq.n 80025c2 80025a6: 3218 adds r2, #24 80025a8: 4293 cmp r3, r2 80025aa: d00a beq.n 80025c2 80025ac: 3218 adds r2, #24 80025ae: 4293 cmp r3, r2 80025b0: d007 beq.n 80025c2 80025b2: 3218 adds r2, #24 80025b4: 4293 cmp r3, r2 80025b6: d004 beq.n 80025c2 80025b8: 681a ldr r2, [r3, #0] 80025ba: f022 020a bic.w r2, r2, #10 80025be: 601a str r2, [r3, #0] 80025c0: e003 b.n 80025ca 80025c2: 681a ldr r2, [r3, #0] 80025c4: f022 0214 bic.w r2, r2, #20 80025c8: 601a str r2, [r3, #0] hdma->State = HAL_DMA_STATE_READY; 80025ca: 2301 movs r3, #1 80025cc: f884 3035 strb.w r3, [r4, #53] @ 0x35 __HAL_UNLOCK(hdma); 80025d0: 2300 movs r3, #0 80025d2: f884 3034 strb.w r3, [r4, #52] @ 0x34 if(hdma->XferCpltCallback != NULL) 80025d6: 6be3 ldr r3, [r4, #60] @ 0x3c 80025d8: 2b00 cmp r3, #0 80025da: f43f af4d beq.w 8002478 hdma->XferCpltCallback(hdma); 80025de: 4620 mov r0, r4 80025e0: 4798 blx r3 80025e2: e749 b.n 8002478 else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 80025e4: 2008 movs r0, #8 80025e6: fa00 f101 lsl.w r1, r0, r1 80025ea: ea11 0f0c tst.w r1, ip 80025ee: f43f af43 beq.w 8002478 80025f2: f012 0f08 tst.w r2, #8 80025f6: f43f af3f beq.w 8002478 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80025fa: 681a ldr r2, [r3, #0] 80025fc: f022 020e bic.w r2, r2, #14 8002600: 601a str r2, [r3, #0] regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8002602: 6de3 ldr r3, [r4, #92] @ 0x5c 8002604: f003 031f and.w r3, r3, #31 8002608: 2201 movs r2, #1 800260a: fa02 f303 lsl.w r3, r2, r3 800260e: 607b str r3, [r7, #4] hdma->ErrorCode = HAL_DMA_ERROR_TE; 8002610: 6562 str r2, [r4, #84] @ 0x54 hdma->State = HAL_DMA_STATE_READY; 8002612: f884 2035 strb.w r2, [r4, #53] @ 0x35 __HAL_UNLOCK(hdma); 8002616: 2300 movs r3, #0 8002618: f884 3034 strb.w r3, [r4, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 800261c: 6ce3 ldr r3, [r4, #76] @ 0x4c 800261e: 2b00 cmp r3, #0 8002620: f43f af2a beq.w 8002478 hdma->XferErrorCallback(hdma); 8002624: 4620 mov r0, r4 8002626: 4798 blx r3 } 8002628: e726 b.n 8002478 800262a: bf00 nop 800262c: 40020010 .word 0x40020010 8002630: 40020028 .word 0x40020028 08002634 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval HAL status */ static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) { 8002634: b430 push {r4, r5} uint32_t RAMcounter; uint32_t StartAddress; StartAddress = hfdcan->Init.MessageRAMOffset; 8002636: 6b41 ldr r1, [r0, #52] @ 0x34 /* Standard filter list start address */ MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos)); 8002638: 6804 ldr r4, [r0, #0] 800263a: f8d4 3084 ldr.w r3, [r4, #132] @ 0x84 800263e: 4a6f ldr r2, [pc, #444] @ (80027fc ) 8002640: 4013 ands r3, r2 8002642: ea43 0381 orr.w r3, r3, r1, lsl #2 8002646: f8c4 3084 str.w r3, [r4, #132] @ 0x84 /* Standard filter elements number */ MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos)); 800264a: 6804 ldr r4, [r0, #0] 800264c: f8d4 3084 ldr.w r3, [r4, #132] @ 0x84 8002650: f423 037f bic.w r3, r3, #16711680 @ 0xff0000 8002654: 6b85 ldr r5, [r0, #56] @ 0x38 8002656: ea43 4305 orr.w r3, r3, r5, lsl #16 800265a: f8c4 3084 str.w r3, [r4, #132] @ 0x84 /* Extended filter list start address */ StartAddress += hfdcan->Init.StdFiltersNbr; 800265e: 6b83 ldr r3, [r0, #56] @ 0x38 8002660: 440b add r3, r1 MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos)); 8002662: 6804 ldr r4, [r0, #0] 8002664: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88 8002668: 4011 ands r1, r2 800266a: ea41 0183 orr.w r1, r1, r3, lsl #2 800266e: f8c4 1088 str.w r1, [r4, #136] @ 0x88 /* Extended filter elements number */ MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos)); 8002672: 6804 ldr r4, [r0, #0] 8002674: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88 8002678: f421 01fe bic.w r1, r1, #8323072 @ 0x7f0000 800267c: 6bc5 ldr r5, [r0, #60] @ 0x3c 800267e: ea41 4105 orr.w r1, r1, r5, lsl #16 8002682: f8c4 1088 str.w r1, [r4, #136] @ 0x88 /* Rx FIFO 0 start address */ StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U); 8002686: 6bc1 ldr r1, [r0, #60] @ 0x3c 8002688: eb03 0341 add.w r3, r3, r1, lsl #1 MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos)); 800268c: 6804 ldr r4, [r0, #0] 800268e: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0 8002692: 4011 ands r1, r2 8002694: ea41 0183 orr.w r1, r1, r3, lsl #2 8002698: f8c4 10a0 str.w r1, [r4, #160] @ 0xa0 /* Rx FIFO 0 elements number */ MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos)); 800269c: 6804 ldr r4, [r0, #0] 800269e: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0 80026a2: f421 01fe bic.w r1, r1, #8323072 @ 0x7f0000 80026a6: 6c05 ldr r5, [r0, #64] @ 0x40 80026a8: ea41 4105 orr.w r1, r1, r5, lsl #16 80026ac: f8c4 10a0 str.w r1, [r4, #160] @ 0xa0 /* Rx FIFO 1 start address */ StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize); 80026b0: 6c01 ldr r1, [r0, #64] @ 0x40 80026b2: 6c44 ldr r4, [r0, #68] @ 0x44 80026b4: fb04 3301 mla r3, r4, r1, r3 MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos)); 80026b8: 6804 ldr r4, [r0, #0] 80026ba: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0 80026be: 4011 ands r1, r2 80026c0: ea41 0183 orr.w r1, r1, r3, lsl #2 80026c4: f8c4 10b0 str.w r1, [r4, #176] @ 0xb0 /* Rx FIFO 1 elements number */ MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos)); 80026c8: 6804 ldr r4, [r0, #0] 80026ca: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0 80026ce: f421 01fe bic.w r1, r1, #8323072 @ 0x7f0000 80026d2: 6c85 ldr r5, [r0, #72] @ 0x48 80026d4: ea41 4105 orr.w r1, r1, r5, lsl #16 80026d8: f8c4 10b0 str.w r1, [r4, #176] @ 0xb0 /* Rx buffer list start address */ StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize); 80026dc: 6c81 ldr r1, [r0, #72] @ 0x48 80026de: 6cc4 ldr r4, [r0, #76] @ 0x4c 80026e0: fb04 3301 mla r3, r4, r1, r3 MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos)); 80026e4: 6804 ldr r4, [r0, #0] 80026e6: f8d4 10ac ldr.w r1, [r4, #172] @ 0xac 80026ea: 4011 ands r1, r2 80026ec: ea41 0183 orr.w r1, r1, r3, lsl #2 80026f0: f8c4 10ac str.w r1, [r4, #172] @ 0xac /* Tx event FIFO start address */ StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize); 80026f4: 6d01 ldr r1, [r0, #80] @ 0x50 80026f6: 6d44 ldr r4, [r0, #84] @ 0x54 80026f8: fb04 3301 mla r3, r4, r1, r3 MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos)); 80026fc: 6804 ldr r4, [r0, #0] 80026fe: f8d4 10f0 ldr.w r1, [r4, #240] @ 0xf0 8002702: 4011 ands r1, r2 8002704: ea41 0183 orr.w r1, r1, r3, lsl #2 8002708: f8c4 10f0 str.w r1, [r4, #240] @ 0xf0 /* Tx event FIFO elements number */ MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos)); 800270c: 6804 ldr r4, [r0, #0] 800270e: f8d4 10f0 ldr.w r1, [r4, #240] @ 0xf0 8002712: f421 117c bic.w r1, r1, #4128768 @ 0x3f0000 8002716: 6d85 ldr r5, [r0, #88] @ 0x58 8002718: ea41 4105 orr.w r1, r1, r5, lsl #16 800271c: f8c4 10f0 str.w r1, [r4, #240] @ 0xf0 /* Tx buffer list start address */ StartAddress += (hfdcan->Init.TxEventsNbr * 2U); 8002720: 6d81 ldr r1, [r0, #88] @ 0x58 8002722: eb03 0341 add.w r3, r3, r1, lsl #1 MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos)); 8002726: 6804 ldr r4, [r0, #0] 8002728: f8d4 10c0 ldr.w r1, [r4, #192] @ 0xc0 800272c: 400a ands r2, r1 800272e: ea42 0383 orr.w r3, r2, r3, lsl #2 8002732: f8c4 30c0 str.w r3, [r4, #192] @ 0xc0 /* Dedicated Tx buffers number */ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos)); 8002736: 6802 ldr r2, [r0, #0] 8002738: f8d2 30c0 ldr.w r3, [r2, #192] @ 0xc0 800273c: f423 137c bic.w r3, r3, #4128768 @ 0x3f0000 8002740: 6dc1 ldr r1, [r0, #92] @ 0x5c 8002742: ea43 4301 orr.w r3, r3, r1, lsl #16 8002746: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 /* Tx FIFO/queue elements number */ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos)); 800274a: 6802 ldr r2, [r0, #0] 800274c: f8d2 30c0 ldr.w r3, [r2, #192] @ 0xc0 8002750: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000 8002754: 6e01 ldr r1, [r0, #96] @ 0x60 8002756: ea43 6301 orr.w r3, r3, r1, lsl #24 800275a: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U); 800275e: 6b43 ldr r3, [r0, #52] @ 0x34 8002760: 4a27 ldr r2, [pc, #156] @ (8002800 ) 8002762: 441a add r2, r3 8002764: 0092 lsls r2, r2, #2 8002766: 66c2 str r2, [r0, #108] @ 0x6c hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U); 8002768: 6b83 ldr r3, [r0, #56] @ 0x38 800276a: eb02 0383 add.w r3, r2, r3, lsl #2 800276e: 6703 str r3, [r0, #112] @ 0x70 hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U); 8002770: 6bc1 ldr r1, [r0, #60] @ 0x3c 8002772: eb03 03c1 add.w r3, r3, r1, lsl #3 8002776: 6743 str r3, [r0, #116] @ 0x74 hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U); 8002778: 6c01 ldr r1, [r0, #64] @ 0x40 800277a: 6c44 ldr r4, [r0, #68] @ 0x44 800277c: fb04 f101 mul.w r1, r4, r1 hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + 8002780: eb03 0381 add.w r3, r3, r1, lsl #2 8002784: 6783 str r3, [r0, #120] @ 0x78 hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U); 8002786: 6c81 ldr r1, [r0, #72] @ 0x48 8002788: 6cc4 ldr r4, [r0, #76] @ 0x4c 800278a: fb04 f101 mul.w r1, r4, r1 hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + 800278e: eb03 0381 add.w r3, r3, r1, lsl #2 8002792: 67c3 str r3, [r0, #124] @ 0x7c hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U); 8002794: 6d01 ldr r1, [r0, #80] @ 0x50 8002796: 6d44 ldr r4, [r0, #84] @ 0x54 8002798: fb04 f101 mul.w r1, r4, r1 hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + 800279c: eb03 0381 add.w r3, r3, r1, lsl #2 80027a0: f8c0 3080 str.w r3, [r0, #128] @ 0x80 hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U); 80027a4: 6d81 ldr r1, [r0, #88] @ 0x58 80027a6: eb03 03c1 add.w r3, r3, r1, lsl #3 80027aa: f8c0 3084 str.w r3, [r0, #132] @ 0x84 hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U); 80027ae: 6e81 ldr r1, [r0, #104] @ 0x68 80027b0: 6dc4 ldr r4, [r0, #92] @ 0x5c 80027b2: fb01 fc04 mul.w ip, r1, r4 80027b6: eb03 038c add.w r3, r3, ip, lsl #2 80027ba: f8c0 3088 str.w r3, [r0, #136] @ 0x88 hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U); 80027be: 6e04 ldr r4, [r0, #96] @ 0x60 80027c0: fb04 f101 mul.w r1, r4, r1 hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + 80027c4: eb03 0381 add.w r3, r3, r1, lsl #2 80027c8: f8c0 3090 str.w r3, [r0, #144] @ 0x90 if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */ 80027cc: 490d ldr r1, [pc, #52] @ (8002804 ) 80027ce: 428b cmp r3, r1 80027d0: d90d bls.n 80027ee { /* Update error code. Message RAM overflow */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; 80027d2: f8d0 309c ldr.w r3, [r0, #156] @ 0x9c 80027d6: f043 0320 orr.w r3, r3, #32 80027da: f8c0 309c str.w r3, [r0, #156] @ 0x9c /* Change FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_ERROR; 80027de: 2303 movs r3, #3 80027e0: f880 3098 strb.w r3, [r0, #152] @ 0x98 return HAL_ERROR; 80027e4: 2001 movs r0, #1 80027e6: e007 b.n 80027f8 else { /* Flush the allocated Message RAM area */ for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) { *(uint32_t *)(RAMcounter) = 0x00000000; 80027e8: 2300 movs r3, #0 80027ea: f842 3b04 str.w r3, [r2], #4 for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) 80027ee: f8d0 3090 ldr.w r3, [r0, #144] @ 0x90 80027f2: 4293 cmp r3, r2 80027f4: d8f8 bhi.n 80027e8 } } /* Return function status */ return HAL_OK; 80027f6: 2000 movs r0, #0 } 80027f8: bc30 pop {r4, r5} 80027fa: 4770 bx lr 80027fc: ffff0003 .word 0xffff0003 8002800: 10002b00 .word 0x10002b00 8002804: 4000d3fc .word 0x4000d3fc 08002808 : { 8002808: b530 push {r4, r5, lr} 800280a: b095 sub sp, #84 @ 0x54 800280c: 4604 mov r4, r0 const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7}; 800280e: 224c movs r2, #76 @ 0x4c 8002810: 49a0 ldr r1, [pc, #640] @ (8002a94 ) 8002812: a801 add r0, sp, #4 8002814: f003 fd8c bl 8006330 if (hfdcan == NULL) 8002818: 2c00 cmp r4, #0 800281a: f000 8138 beq.w 8002a8e if (hfdcan->Instance == FDCAN1) 800281e: 6823 ldr r3, [r4, #0] 8002820: 4a9d ldr r2, [pc, #628] @ (8002a98 ) 8002822: 4293 cmp r3, r2 8002824: d020 beq.n 8002868 if (hfdcan->State == HAL_FDCAN_STATE_RESET) 8002826: f894 3098 ldrb.w r3, [r4, #152] @ 0x98 800282a: b30b cbz r3, 8002870 CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); 800282c: 6822 ldr r2, [r4, #0] 800282e: 6993 ldr r3, [r2, #24] 8002830: f023 0310 bic.w r3, r3, #16 8002834: 6193 str r3, [r2, #24] tickstart = HAL_GetTick(); 8002836: f7fe f991 bl 8000b5c 800283a: 4605 mov r5, r0 while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) 800283c: 6823 ldr r3, [r4, #0] 800283e: 699a ldr r2, [r3, #24] 8002840: f012 0f08 tst.w r2, #8 8002844: d01a beq.n 800287c if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) 8002846: f7fe f989 bl 8000b5c 800284a: 1b43 subs r3, r0, r5 800284c: 2b0a cmp r3, #10 800284e: d9f5 bls.n 800283c hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; 8002850: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c 8002854: f043 0301 orr.w r3, r3, #1 8002858: f8c4 309c str.w r3, [r4, #156] @ 0x9c hfdcan->State = HAL_FDCAN_STATE_ERROR; 800285c: 2303 movs r3, #3 800285e: f884 3098 strb.w r3, [r4, #152] @ 0x98 return HAL_ERROR; 8002862: 2001 movs r0, #1 } 8002864: b015 add sp, #84 @ 0x54 8002866: bd30 pop {r4, r5, pc} hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U); 8002868: f503 7380 add.w r3, r3, #256 @ 0x100 800286c: 6063 str r3, [r4, #4] 800286e: e7da b.n 8002826 hfdcan->Lock = HAL_UNLOCKED; 8002870: f884 3099 strb.w r3, [r4, #153] @ 0x99 HAL_FDCAN_MspInit(hfdcan); 8002874: 4620 mov r0, r4 8002876: f000 fae5 bl 8002e44 800287a: e7d7 b.n 800282c SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); 800287c: 699a ldr r2, [r3, #24] 800287e: f042 0201 orr.w r2, r2, #1 8002882: 619a str r2, [r3, #24] tickstart = HAL_GetTick(); 8002884: f7fe f96a bl 8000b5c 8002888: 4605 mov r5, r0 while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) 800288a: 6823 ldr r3, [r4, #0] 800288c: 699a ldr r2, [r3, #24] 800288e: f012 0f01 tst.w r2, #1 8002892: d10f bne.n 80028b4 if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) 8002894: f7fe f962 bl 8000b5c 8002898: 1b40 subs r0, r0, r5 800289a: 280a cmp r0, #10 800289c: d9f5 bls.n 800288a hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; 800289e: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c 80028a2: f043 0301 orr.w r3, r3, #1 80028a6: f8c4 309c str.w r3, [r4, #156] @ 0x9c hfdcan->State = HAL_FDCAN_STATE_ERROR; 80028aa: 2303 movs r3, #3 80028ac: f884 3098 strb.w r3, [r4, #152] @ 0x98 return HAL_ERROR; 80028b0: 2001 movs r0, #1 80028b2: e7d7 b.n 8002864 SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); 80028b4: 699a ldr r2, [r3, #24] 80028b6: f042 0202 orr.w r2, r2, #2 80028ba: 619a str r2, [r3, #24] if (hfdcan->Init.AutoRetransmission == ENABLE) 80028bc: 7c23 ldrb r3, [r4, #16] 80028be: 2b01 cmp r3, #1 80028c0: d040 beq.n 8002944 SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); 80028c2: 6822 ldr r2, [r4, #0] 80028c4: 6993 ldr r3, [r2, #24] 80028c6: f043 0340 orr.w r3, r3, #64 @ 0x40 80028ca: 6193 str r3, [r2, #24] if (hfdcan->Init.TransmitPause == ENABLE) 80028cc: 7c63 ldrb r3, [r4, #17] 80028ce: 2b01 cmp r3, #1 80028d0: d03e beq.n 8002950 CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); 80028d2: 6822 ldr r2, [r4, #0] 80028d4: 6993 ldr r3, [r2, #24] 80028d6: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80028da: 6193 str r3, [r2, #24] if (hfdcan->Init.ProtocolException == ENABLE) 80028dc: 7ca3 ldrb r3, [r4, #18] 80028de: 2b01 cmp r3, #1 80028e0: d03c beq.n 800295c SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); 80028e2: 6822 ldr r2, [r4, #0] 80028e4: 6993 ldr r3, [r2, #24] 80028e6: f443 5380 orr.w r3, r3, #4096 @ 0x1000 80028ea: 6193 str r3, [r2, #24] MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat); 80028ec: 6822 ldr r2, [r4, #0] 80028ee: 6993 ldr r3, [r2, #24] 80028f0: f423 7340 bic.w r3, r3, #768 @ 0x300 80028f4: 68a1 ldr r1, [r4, #8] 80028f6: 430b orrs r3, r1 80028f8: 6193 str r3, [r2, #24] CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM)); 80028fa: 6822 ldr r2, [r4, #0] 80028fc: 6993 ldr r3, [r2, #24] 80028fe: f023 03a4 bic.w r3, r3, #164 @ 0xa4 8002902: 6193 str r3, [r2, #24] CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); 8002904: 6822 ldr r2, [r4, #0] 8002906: 6913 ldr r3, [r2, #16] 8002908: f023 0310 bic.w r3, r3, #16 800290c: 6113 str r3, [r2, #16] if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) 800290e: 68e3 ldr r3, [r4, #12] 8002910: 2b01 cmp r3, #1 8002912: d029 beq.n 8002968 else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) 8002914: 2b00 cmp r3, #0 8002916: d02c beq.n 8002972 if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) 8002918: 2b02 cmp r3, #2 800291a: f000 809b beq.w 8002a54 SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST); 800291e: 6822 ldr r2, [r4, #0] 8002920: 6993 ldr r3, [r2, #24] 8002922: f043 0380 orr.w r3, r3, #128 @ 0x80 8002926: 6193 str r3, [r2, #24] SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); 8002928: 6822 ldr r2, [r4, #0] 800292a: 6913 ldr r3, [r2, #16] 800292c: f043 0310 orr.w r3, r3, #16 8002930: 6113 str r3, [r2, #16] if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) 8002932: 68e3 ldr r3, [r4, #12] 8002934: 2b03 cmp r3, #3 8002936: d11c bne.n 8002972 SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); 8002938: 6822 ldr r2, [r4, #0] 800293a: 6993 ldr r3, [r2, #24] 800293c: f043 0320 orr.w r3, r3, #32 8002940: 6193 str r3, [r2, #24] 8002942: e016 b.n 8002972 CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); 8002944: 6822 ldr r2, [r4, #0] 8002946: 6993 ldr r3, [r2, #24] 8002948: f023 0340 bic.w r3, r3, #64 @ 0x40 800294c: 6193 str r3, [r2, #24] 800294e: e7bd b.n 80028cc SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); 8002950: 6822 ldr r2, [r4, #0] 8002952: 6993 ldr r3, [r2, #24] 8002954: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8002958: 6193 str r3, [r2, #24] 800295a: e7bf b.n 80028dc CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); 800295c: 6822 ldr r2, [r4, #0] 800295e: 6993 ldr r3, [r2, #24] 8002960: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8002964: 6193 str r3, [r2, #24] 8002966: e7c1 b.n 80028ec SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); 8002968: 6822 ldr r2, [r4, #0] 800296a: 6993 ldr r3, [r2, #24] 800296c: f043 0304 orr.w r3, r3, #4 8002970: 6193 str r3, [r2, #24] hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 8002972: 69a3 ldr r3, [r4, #24] 8002974: 1e5a subs r2, r3, #1 (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ 8002976: 69e3 ldr r3, [r4, #28] 8002978: 3b01 subs r3, #1 800297a: 021b lsls r3, r3, #8 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 800297c: ea43 6342 orr.w r3, r3, r2, lsl #25 (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ 8002980: 6a22 ldr r2, [r4, #32] 8002982: 3a01 subs r2, #1 (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ 8002984: 4313 orrs r3, r2 (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos)); 8002986: 6962 ldr r2, [r4, #20] 8002988: 3a01 subs r2, #1 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 800298a: 6821 ldr r1, [r4, #0] (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ 800298c: ea43 4302 orr.w r3, r3, r2, lsl #16 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 8002990: 61cb str r3, [r1, #28] if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) 8002992: 68a3 ldr r3, [r4, #8] 8002994: f5b3 7f40 cmp.w r3, #768 @ 0x300 8002998: d062 beq.n 8002a60 if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U) 800299a: 6e23 ldr r3, [r4, #96] @ 0x60 800299c: b133 cbz r3, 80029ac SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode); 800299e: 6822 ldr r2, [r4, #0] 80029a0: f8d2 30c0 ldr.w r3, [r2, #192] @ 0xc0 80029a4: 6e61 ldr r1, [r4, #100] @ 0x64 80029a6: 430b orrs r3, r1 80029a8: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U) 80029ac: 6de3 ldr r3, [r4, #92] @ 0x5c 80029ae: 6e22 ldr r2, [r4, #96] @ 0x60 80029b0: 42d3 cmn r3, r2 80029b2: d00d beq.n 80029d0 MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]); 80029b4: 6821 ldr r1, [r4, #0] 80029b6: f8d1 30c8 ldr.w r3, [r1, #200] @ 0xc8 80029ba: f023 0307 bic.w r3, r3, #7 80029be: 6ea2 ldr r2, [r4, #104] @ 0x68 80029c0: a814 add r0, sp, #80 @ 0x50 80029c2: eb00 0282 add.w r2, r0, r2, lsl #2 80029c6: f852 2c4c ldr.w r2, [r2, #-76] 80029ca: 4313 orrs r3, r2 80029cc: f8c1 30c8 str.w r3, [r1, #200] @ 0xc8 if (hfdcan->Init.RxFifo0ElmtsNbr > 0U) 80029d0: 6c23 ldr r3, [r4, #64] @ 0x40 80029d2: b16b cbz r3, 80029f0 MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, 80029d4: 6821 ldr r1, [r4, #0] 80029d6: f8d1 30bc ldr.w r3, [r1, #188] @ 0xbc 80029da: f023 0307 bic.w r3, r3, #7 80029de: 6c62 ldr r2, [r4, #68] @ 0x44 80029e0: a814 add r0, sp, #80 @ 0x50 80029e2: eb00 0282 add.w r2, r0, r2, lsl #2 80029e6: f852 2c4c ldr.w r2, [r2, #-76] 80029ea: 4313 orrs r3, r2 80029ec: f8c1 30bc str.w r3, [r1, #188] @ 0xbc if (hfdcan->Init.RxFifo1ElmtsNbr > 0U) 80029f0: 6ca3 ldr r3, [r4, #72] @ 0x48 80029f2: b173 cbz r3, 8002a12 MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, 80029f4: 6821 ldr r1, [r4, #0] 80029f6: f8d1 30bc ldr.w r3, [r1, #188] @ 0xbc 80029fa: f023 0370 bic.w r3, r3, #112 @ 0x70 80029fe: 6ce2 ldr r2, [r4, #76] @ 0x4c 8002a00: a814 add r0, sp, #80 @ 0x50 8002a02: eb00 0282 add.w r2, r0, r2, lsl #2 8002a06: f852 2c4c ldr.w r2, [r2, #-76] 8002a0a: ea43 1302 orr.w r3, r3, r2, lsl #4 8002a0e: f8c1 30bc str.w r3, [r1, #188] @ 0xbc if (hfdcan->Init.RxBuffersNbr > 0U) 8002a12: 6d23 ldr r3, [r4, #80] @ 0x50 8002a14: b173 cbz r3, 8002a34 MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, 8002a16: 6821 ldr r1, [r4, #0] 8002a18: f8d1 30bc ldr.w r3, [r1, #188] @ 0xbc 8002a1c: f423 63e0 bic.w r3, r3, #1792 @ 0x700 8002a20: 6d62 ldr r2, [r4, #84] @ 0x54 8002a22: a814 add r0, sp, #80 @ 0x50 8002a24: eb00 0282 add.w r2, r0, r2, lsl #2 8002a28: f852 2c4c ldr.w r2, [r2, #-76] 8002a2c: ea43 2302 orr.w r3, r3, r2, lsl #8 8002a30: f8c1 30bc str.w r3, [r1, #188] @ 0xbc if (hfdcan->Instance == FDCAN1) 8002a34: 6822 ldr r2, [r4, #0] 8002a36: 4b18 ldr r3, [pc, #96] @ (8002a98 ) 8002a38: 429a cmp r2, r3 8002a3a: d022 beq.n 8002a82 hfdcan->LatestTxFifoQRequest = 0U; 8002a3c: 2300 movs r3, #0 8002a3e: f8c4 3094 str.w r3, [r4, #148] @ 0x94 hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; 8002a42: f8c4 309c str.w r3, [r4, #156] @ 0x9c hfdcan->State = HAL_FDCAN_STATE_READY; 8002a46: 2301 movs r3, #1 8002a48: f884 3098 strb.w r3, [r4, #152] @ 0x98 status = FDCAN_CalcultateRamBlockAddresses(hfdcan); 8002a4c: 4620 mov r0, r4 8002a4e: f7ff fdf1 bl 8002634 return status; 8002a52: e707 b.n 8002864 SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); 8002a54: 6822 ldr r2, [r4, #0] 8002a56: 6993 ldr r3, [r2, #24] 8002a58: f043 0320 orr.w r3, r3, #32 8002a5c: 6193 str r3, [r2, #24] 8002a5e: e788 b.n 8002972 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8002a60: 6aa3 ldr r3, [r4, #40] @ 0x28 8002a62: 3b01 subs r3, #1 (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ 8002a64: 6ae2 ldr r2, [r4, #44] @ 0x2c 8002a66: 3a01 subs r2, #1 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8002a68: ea43 2302 orr.w r3, r3, r2, lsl #8 (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ 8002a6c: 6b22 ldr r2, [r4, #48] @ 0x30 8002a6e: 3a01 subs r2, #1 (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ 8002a70: ea43 1302 orr.w r3, r3, r2, lsl #4 (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos)); 8002a74: 6a62 ldr r2, [r4, #36] @ 0x24 8002a76: 3a01 subs r2, #1 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8002a78: 6821 ldr r1, [r4, #0] (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ 8002a7a: ea43 4302 orr.w r3, r3, r2, lsl #16 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8002a7e: 60cb str r3, [r1, #12] 8002a80: e78b b.n 800299a CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM); 8002a82: 6862 ldr r2, [r4, #4] 8002a84: 6893 ldr r3, [r2, #8] 8002a86: f023 0303 bic.w r3, r3, #3 8002a8a: 6093 str r3, [r2, #8] 8002a8c: e7d6 b.n 8002a3c return HAL_ERROR; 8002a8e: 2001 movs r0, #1 8002a90: e6e8 b.n 8002864 8002a92: bf00 nop 8002a94: 08006364 .word 0x08006364 8002a98: 4000a000 .word 0x4000a000 08002a9c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { 8002a9c: b5f0 push {r4, r5, r6, r7, lr} 8002a9e: b083 sub sp, #12 uint32_t position = 0x00U; 8002aa0: 2300 movs r3, #0 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 8002aa2: e06b b.n 8002b7c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002aa4: 6885 ldr r5, [r0, #8] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8002aa6: 005e lsls r6, r3, #1 8002aa8: 2403 movs r4, #3 8002aaa: 40b4 lsls r4, r6 8002aac: ea25 0504 bic.w r5, r5, r4 temp |= (GPIO_Init->Speed << (position * 2U)); 8002ab0: 68cc ldr r4, [r1, #12] 8002ab2: 40b4 lsls r4, r6 8002ab4: 432c orrs r4, r5 GPIOx->OSPEEDR = temp; 8002ab6: 6084 str r4, [r0, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002ab8: 6845 ldr r5, [r0, #4] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8002aba: ea25 050c bic.w r5, r5, ip temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002abe: 684c ldr r4, [r1, #4] 8002ac0: f3c4 1400 ubfx r4, r4, #4, #1 8002ac4: 409c lsls r4, r3 8002ac6: 432c orrs r4, r5 GPIOx->OTYPER = temp; 8002ac8: 6044 str r4, [r0, #4] 8002aca: e069 b.n 8002ba0 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8002acc: 08dd lsrs r5, r3, #3 8002ace: 3508 adds r5, #8 8002ad0: f850 4025 ldr.w r4, [r0, r5, lsl #2] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8002ad4: f003 0c07 and.w ip, r3, #7 8002ad8: ea4f 0c8c mov.w ip, ip, lsl #2 8002adc: f04f 0e0f mov.w lr, #15 8002ae0: fa0e fe0c lsl.w lr, lr, ip 8002ae4: ea24 0e0e bic.w lr, r4, lr temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8002ae8: 690c ldr r4, [r1, #16] 8002aea: fa04 f40c lsl.w r4, r4, ip 8002aee: ea44 040e orr.w r4, r4, lr GPIOx->AFR[position >> 3U] = temp; 8002af2: f840 4025 str.w r4, [r0, r5, lsl #2] 8002af6: e06b b.n 8002bd0 /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); temp = SYSCFG->EXTICR[position >> 2U]; temp &= ~(0x0FUL << (4U * (position & 0x03U))); temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8002af8: 2409 movs r4, #9 8002afa: e000 b.n 8002afe 8002afc: 2400 movs r4, #0 8002afe: fa04 f40e lsl.w r4, r4, lr 8002b02: 432c orrs r4, r5 SYSCFG->EXTICR[position >> 2U] = temp; 8002b04: f10c 0c02 add.w ip, ip, #2 8002b08: 4d69 ldr r5, [pc, #420] @ (8002cb0 ) 8002b0a: f845 402c str.w r4, [r5, ip, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8002b0e: f04f 44b0 mov.w r4, #1476395008 @ 0x58000000 8002b12: 6825 ldr r5, [r4, #0] temp &= ~(iocurrent); 8002b14: 43d4 mvns r4, r2 8002b16: ea25 0602 bic.w r6, r5, r2 if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8002b1a: 684f ldr r7, [r1, #4] 8002b1c: f417 1f80 tst.w r7, #1048576 @ 0x100000 8002b20: d001 beq.n 8002b26 { temp |= iocurrent; 8002b22: ea42 0605 orr.w r6, r2, r5 } EXTI->RTSR1 = temp; 8002b26: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000 8002b2a: 602e str r6, [r5, #0] temp = EXTI->FTSR1; 8002b2c: 686d ldr r5, [r5, #4] temp &= ~(iocurrent); 8002b2e: ea04 0605 and.w r6, r4, r5 if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8002b32: 684f ldr r7, [r1, #4] 8002b34: f417 1f00 tst.w r7, #2097152 @ 0x200000 8002b38: d001 beq.n 8002b3e { temp |= iocurrent; 8002b3a: ea42 0605 orr.w r6, r2, r5 } EXTI->FTSR1 = temp; 8002b3e: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000 8002b42: 606e str r6, [r5, #4] temp = EXTI_CurrentCPU->EMR1; 8002b44: f8d5 5084 ldr.w r5, [r5, #132] @ 0x84 temp &= ~(iocurrent); 8002b48: ea04 0605 and.w r6, r4, r5 if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8002b4c: 684f ldr r7, [r1, #4] 8002b4e: f417 3f00 tst.w r7, #131072 @ 0x20000 8002b52: d001 beq.n 8002b58 { temp |= iocurrent; 8002b54: ea42 0605 orr.w r6, r2, r5 } EXTI_CurrentCPU->EMR1 = temp; 8002b58: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000 8002b5c: f8c5 6084 str.w r6, [r5, #132] @ 0x84 /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 8002b60: f8d5 5080 ldr.w r5, [r5, #128] @ 0x80 temp &= ~(iocurrent); 8002b64: 402c ands r4, r5 if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002b66: 684e ldr r6, [r1, #4] 8002b68: f416 3f80 tst.w r6, #65536 @ 0x10000 8002b6c: d001 beq.n 8002b72 { temp |= iocurrent; 8002b6e: ea42 0405 orr.w r4, r2, r5 } EXTI_CurrentCPU->IMR1 = temp; 8002b72: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8002b76: f8c2 4080 str.w r4, [r2, #128] @ 0x80 } } position++; 8002b7a: 3301 adds r3, #1 while (((GPIO_Init->Pin) >> position) != 0x00U) 8002b7c: 680a ldr r2, [r1, #0] 8002b7e: fa32 f403 lsrs.w r4, r2, r3 8002b82: f000 8092 beq.w 8002caa iocurrent = (GPIO_Init->Pin) & (1UL << position); 8002b86: f04f 0c01 mov.w ip, #1 8002b8a: fa0c fc03 lsl.w ip, ip, r3 if (iocurrent != 0x00U) 8002b8e: ea1c 0202 ands.w r2, ip, r2 8002b92: d0f2 beq.n 8002b7a if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8002b94: 684c ldr r4, [r1, #4] 8002b96: f004 0403 and.w r4, r4, #3 8002b9a: 3c01 subs r4, #1 8002b9c: 2c01 cmp r4, #1 8002b9e: d981 bls.n 8002aa4 if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002ba0: 684c ldr r4, [r1, #4] 8002ba2: f004 0403 and.w r4, r4, #3 8002ba6: 2c03 cmp r4, #3 8002ba8: d00c beq.n 8002bc4 temp = GPIOx->PUPDR; 8002baa: 68c4 ldr r4, [r0, #12] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8002bac: 005d lsls r5, r3, #1 8002bae: f04f 0c03 mov.w ip, #3 8002bb2: fa0c fc05 lsl.w ip, ip, r5 8002bb6: ea24 0c0c bic.w ip, r4, ip temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002bba: 688c ldr r4, [r1, #8] 8002bbc: 40ac lsls r4, r5 8002bbe: ea44 040c orr.w r4, r4, ip GPIOx->PUPDR = temp; 8002bc2: 60c4 str r4, [r0, #12] if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002bc4: 684c ldr r4, [r1, #4] 8002bc6: f004 0403 and.w r4, r4, #3 8002bca: 2c02 cmp r4, #2 8002bcc: f43f af7e beq.w 8002acc temp = GPIOx->MODER; 8002bd0: 6804 ldr r4, [r0, #0] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8002bd2: ea4f 0e43 mov.w lr, r3, lsl #1 8002bd6: f04f 0c03 mov.w ip, #3 8002bda: fa0c fc0e lsl.w ip, ip, lr 8002bde: ea24 0c0c bic.w ip, r4, ip temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8002be2: 684c ldr r4, [r1, #4] 8002be4: f004 0403 and.w r4, r4, #3 8002be8: fa04 f40e lsl.w r4, r4, lr 8002bec: ea44 040c orr.w r4, r4, ip GPIOx->MODER = temp; 8002bf0: 6004 str r4, [r0, #0] if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002bf2: 684c ldr r4, [r1, #4] 8002bf4: f414 3f40 tst.w r4, #196608 @ 0x30000 8002bf8: d0bf beq.n 8002b7a __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002bfa: 4c2e ldr r4, [pc, #184] @ (8002cb4 ) 8002bfc: f8d4 5154 ldr.w r5, [r4, #340] @ 0x154 8002c00: f045 0502 orr.w r5, r5, #2 8002c04: f8c4 5154 str.w r5, [r4, #340] @ 0x154 8002c08: f8d4 4154 ldr.w r4, [r4, #340] @ 0x154 8002c0c: f004 0402 and.w r4, r4, #2 8002c10: 9401 str r4, [sp, #4] 8002c12: 9c01 ldr r4, [sp, #4] temp = SYSCFG->EXTICR[position >> 2U]; 8002c14: ea4f 0c93 mov.w ip, r3, lsr #2 8002c18: f10c 0502 add.w r5, ip, #2 8002c1c: 4c24 ldr r4, [pc, #144] @ (8002cb0 ) 8002c1e: f854 5025 ldr.w r5, [r4, r5, lsl #2] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8002c22: f003 0e03 and.w lr, r3, #3 8002c26: ea4f 0e8e mov.w lr, lr, lsl #2 8002c2a: 240f movs r4, #15 8002c2c: fa04 f40e lsl.w r4, r4, lr 8002c30: ea25 0504 bic.w r5, r5, r4 temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8002c34: 4c20 ldr r4, [pc, #128] @ (8002cb8 ) 8002c36: 42a0 cmp r0, r4 8002c38: f43f af60 beq.w 8002afc 8002c3c: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c40: 42a0 cmp r0, r4 8002c42: d022 beq.n 8002c8a 8002c44: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c48: 42a0 cmp r0, r4 8002c4a: d020 beq.n 8002c8e 8002c4c: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c50: 42a0 cmp r0, r4 8002c52: d01e beq.n 8002c92 8002c54: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c58: 42a0 cmp r0, r4 8002c5a: d01c beq.n 8002c96 8002c5c: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c60: 42a0 cmp r0, r4 8002c62: d01a beq.n 8002c9a 8002c64: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c68: 42a0 cmp r0, r4 8002c6a: d018 beq.n 8002c9e 8002c6c: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c70: 42a0 cmp r0, r4 8002c72: d016 beq.n 8002ca2 8002c74: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c78: 42a0 cmp r0, r4 8002c7a: d014 beq.n 8002ca6 8002c7c: f504 6480 add.w r4, r4, #1024 @ 0x400 8002c80: 42a0 cmp r0, r4 8002c82: f43f af39 beq.w 8002af8 8002c86: 240a movs r4, #10 8002c88: e739 b.n 8002afe 8002c8a: 2401 movs r4, #1 8002c8c: e737 b.n 8002afe 8002c8e: 2402 movs r4, #2 8002c90: e735 b.n 8002afe 8002c92: 2403 movs r4, #3 8002c94: e733 b.n 8002afe 8002c96: 2404 movs r4, #4 8002c98: e731 b.n 8002afe 8002c9a: 2405 movs r4, #5 8002c9c: e72f b.n 8002afe 8002c9e: 2406 movs r4, #6 8002ca0: e72d b.n 8002afe 8002ca2: 2407 movs r4, #7 8002ca4: e72b b.n 8002afe 8002ca6: 2408 movs r4, #8 8002ca8: e729 b.n 8002afe } } 8002caa: b003 add sp, #12 8002cac: bdf0 pop {r4, r5, r6, r7, pc} 8002cae: bf00 nop 8002cb0: 58000400 .word 0x58000400 8002cb4: 58024400 .word 0x58024400 8002cb8: 58020000 .word 0x58020000 08002cbc : { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8002cbc: b10a cbz r2, 8002cc2 { GPIOx->BSRR = GPIO_Pin; 8002cbe: 6181 str r1, [r0, #24] 8002cc0: 4770 bx lr } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 8002cc2: 0409 lsls r1, r1, #16 8002cc4: 6181 str r1, [r0, #24] } } 8002cc6: 4770 bx lr 08002cc8 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002cc8: b082 sub sp, #8 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002cca: 4b07 ldr r3, [pc, #28] @ (8002ce8 ) 8002ccc: f8d3 2154 ldr.w r2, [r3, #340] @ 0x154 8002cd0: f042 0202 orr.w r2, r2, #2 8002cd4: f8c3 2154 str.w r2, [r3, #340] @ 0x154 8002cd8: f8d3 3154 ldr.w r3, [r3, #340] @ 0x154 8002cdc: f003 0302 and.w r3, r3, #2 8002ce0: 9301 str r3, [sp, #4] 8002ce2: 9b01 ldr r3, [sp, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8002ce4: b002 add sp, #8 8002ce6: 4770 bx lr 8002ce8: 58024400 .word 0x58024400 08002cec : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8002cec: b5f0 push {r4, r5, r6, r7, lr} 8002cee: b0bb sub sp, #236 @ 0xec 8002cf0: 4604 mov r4, r0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002cf2: 2100 movs r1, #0 8002cf4: 9135 str r1, [sp, #212] @ 0xd4 8002cf6: 9136 str r1, [sp, #216] @ 0xd8 8002cf8: 9137 str r1, [sp, #220] @ 0xdc 8002cfa: 9138 str r1, [sp, #224] @ 0xe0 8002cfc: 9139 str r1, [sp, #228] @ 0xe4 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8002cfe: 22c0 movs r2, #192 @ 0xc0 8002d00: a804 add r0, sp, #16 8002d02: f003 fae8 bl 80062d6 if(hadc->Instance==ADC1) 8002d06: 6822 ldr r2, [r4, #0] 8002d08: 4b47 ldr r3, [pc, #284] @ (8002e28 ) 8002d0a: 429a cmp r2, r3 8002d0c: d001 beq.n 8002d12 /* USER CODE END ADC1_MspInit 1 */ } } 8002d0e: b03b add sp, #236 @ 0xec 8002d10: bdf0 pop {r4, r5, r6, r7, pc} PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8002d12: f44f 2200 mov.w r2, #524288 @ 0x80000 8002d16: 2300 movs r3, #0 8002d18: e9cd 2304 strd r2, r3, [sp, #16] PeriphClkInitStruct.PLL2.PLL2M = 2; 8002d1c: 2302 movs r3, #2 8002d1e: 9306 str r3, [sp, #24] PeriphClkInitStruct.PLL2.PLL2N = 20; 8002d20: 2214 movs r2, #20 8002d22: 9207 str r2, [sp, #28] PeriphClkInitStruct.PLL2.PLL2P = 12; 8002d24: 220c movs r2, #12 8002d26: 9208 str r2, [sp, #32] PeriphClkInitStruct.PLL2.PLL2Q = 2; 8002d28: 9309 str r3, [sp, #36] @ 0x24 PeriphClkInitStruct.PLL2.PLL2R = 2; 8002d2a: 930a str r3, [sp, #40] @ 0x28 PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; 8002d2c: 23c0 movs r3, #192 @ 0xc0 8002d2e: 930b str r3, [sp, #44] @ 0x2c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002d30: a804 add r0, sp, #16 8002d32: f001 f90f bl 8003f54 8002d36: 2800 cmp r0, #0 8002d38: d170 bne.n 8002e1c __HAL_RCC_ADC12_CLK_ENABLE(); 8002d3a: 4b3c ldr r3, [pc, #240] @ (8002e2c ) 8002d3c: f8d3 2138 ldr.w r2, [r3, #312] @ 0x138 8002d40: f042 0220 orr.w r2, r2, #32 8002d44: f8c3 2138 str.w r2, [r3, #312] @ 0x138 8002d48: f8d3 2138 ldr.w r2, [r3, #312] @ 0x138 8002d4c: f002 0220 and.w r2, r2, #32 8002d50: 9200 str r2, [sp, #0] 8002d52: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOC_CLK_ENABLE(); 8002d54: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8002d58: f042 0204 orr.w r2, r2, #4 8002d5c: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8002d60: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8002d64: f002 0204 and.w r2, r2, #4 8002d68: 9201 str r2, [sp, #4] 8002d6a: 9a01 ldr r2, [sp, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002d6c: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8002d70: f042 0201 orr.w r2, r2, #1 8002d74: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8002d78: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8002d7c: f002 0201 and.w r2, r2, #1 8002d80: 9202 str r2, [sp, #8] 8002d82: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002d84: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8002d88: f042 0202 orr.w r2, r2, #2 8002d8c: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8002d90: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8002d94: f003 0302 and.w r3, r3, #2 8002d98: 9303 str r3, [sp, #12] 8002d9a: 9b03 ldr r3, [sp, #12] GPIO_InitStruct.Pin = A16_Pin|A15_Pin|A14_Pin|A13_Pin 8002d9c: 233f movs r3, #63 @ 0x3f 8002d9e: 9335 str r3, [sp, #212] @ 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8002da0: 2603 movs r6, #3 8002da2: 9636 str r6, [sp, #216] @ 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002da4: 2500 movs r5, #0 8002da6: 9537 str r5, [sp, #220] @ 0xdc HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002da8: af35 add r7, sp, #212 @ 0xd4 8002daa: 4639 mov r1, r7 8002dac: 4820 ldr r0, [pc, #128] @ (8002e30 ) 8002dae: f7ff fe75 bl 8002a9c GPIO_InitStruct.Pin = A12_Pin|A11_Pin|A10_Pin|A9_Pin 8002db2: 23ff movs r3, #255 @ 0xff 8002db4: 9335 str r3, [sp, #212] @ 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8002db6: 9636 str r6, [sp, #216] @ 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002db8: 9537 str r5, [sp, #220] @ 0xdc HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002dba: 4639 mov r1, r7 8002dbc: 481d ldr r0, [pc, #116] @ (8002e34 ) 8002dbe: f7ff fe6d bl 8002a9c GPIO_InitStruct.Pin = A2_Pin|A1_Pin; 8002dc2: 9635 str r6, [sp, #212] @ 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8002dc4: 9636 str r6, [sp, #216] @ 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002dc6: 9537 str r5, [sp, #220] @ 0xdc HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002dc8: 4639 mov r1, r7 8002dca: 481b ldr r0, [pc, #108] @ (8002e38 ) 8002dcc: f7ff fe66 bl 8002a9c hdma_adc1.Instance = DMA1_Stream0; 8002dd0: 481a ldr r0, [pc, #104] @ (8002e3c ) 8002dd2: 4b1b ldr r3, [pc, #108] @ (8002e40 ) 8002dd4: 6003 str r3, [r0, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8002dd6: 2309 movs r3, #9 8002dd8: 6043 str r3, [r0, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8002dda: 6085 str r5, [r0, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8002ddc: 60c5 str r5, [r0, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8002dde: f44f 6380 mov.w r3, #1024 @ 0x400 8002de2: 6103 str r3, [r0, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8002de4: f44f 6300 mov.w r3, #2048 @ 0x800 8002de8: 6143 str r3, [r0, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8002dea: f44f 5300 mov.w r3, #8192 @ 0x2000 8002dee: 6183 str r3, [r0, #24] hdma_adc1.Init.Mode = DMA_CIRCULAR; 8002df0: f44f 7380 mov.w r3, #256 @ 0x100 8002df4: 61c3 str r3, [r0, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; 8002df6: f44f 3380 mov.w r3, #65536 @ 0x10000 8002dfa: 6203 str r3, [r0, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8002dfc: 6245 str r5, [r0, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8002dfe: f7fe fe75 bl 8001aec 8002e02: b970 cbnz r0, 8002e22 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8002e04: 4b0d ldr r3, [pc, #52] @ (8002e3c ) 8002e06: 64e3 str r3, [r4, #76] @ 0x4c 8002e08: 639c str r4, [r3, #56] @ 0x38 HAL_NVIC_SetPriority(ADC_IRQn, 0, 0); 8002e0a: 2200 movs r2, #0 8002e0c: 4611 mov r1, r2 8002e0e: 2012 movs r0, #18 8002e10: f7fe fcc4 bl 800179c HAL_NVIC_EnableIRQ(ADC_IRQn); 8002e14: 2012 movs r0, #18 8002e16: f7fe fcd1 bl 80017bc } 8002e1a: e778 b.n 8002d0e Error_Handler(); 8002e1c: f7fd fb48 bl 80004b0 8002e20: e78b b.n 8002d3a Error_Handler(); 8002e22: f7fd fb45 bl 80004b0 8002e26: e7ed b.n 8002e04 8002e28: 40022000 .word 0x40022000 8002e2c: 58024400 .word 0x58024400 8002e30: 58020800 .word 0x58020800 8002e34: 58020000 .word 0x58020000 8002e38: 58020400 .word 0x58020400 8002e3c: 200002e8 .word 0x200002e8 8002e40: 40020010 .word 0x40020010 08002e44 : * This function configures the hardware resources used in this example * @param hfdcan: FDCAN handle pointer * @retval None */ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan) { 8002e44: b510 push {r4, lr} 8002e46: b0ba sub sp, #232 @ 0xe8 8002e48: 4604 mov r4, r0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002e4a: 2100 movs r1, #0 8002e4c: 9135 str r1, [sp, #212] @ 0xd4 8002e4e: 9136 str r1, [sp, #216] @ 0xd8 8002e50: 9137 str r1, [sp, #220] @ 0xdc 8002e52: 9138 str r1, [sp, #224] @ 0xe0 8002e54: 9139 str r1, [sp, #228] @ 0xe4 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8002e56: 22c0 movs r2, #192 @ 0xc0 8002e58: a804 add r0, sp, #16 8002e5a: f003 fa3c bl 80062d6 if(hfdcan->Instance==FDCAN1) 8002e5e: 6823 ldr r3, [r4, #0] 8002e60: 4a3f ldr r2, [pc, #252] @ (8002f60 ) 8002e62: 4293 cmp r3, r2 8002e64: d004 beq.n 8002e70 /* USER CODE BEGIN FDCAN1_MspInit 1 */ /* USER CODE END FDCAN1_MspInit 1 */ } else if(hfdcan->Instance==FDCAN2) 8002e66: 4a3f ldr r2, [pc, #252] @ (8002f64 ) 8002e68: 4293 cmp r3, r2 8002e6a: d03d beq.n 8002ee8 /* USER CODE BEGIN FDCAN2_MspInit 1 */ /* USER CODE END FDCAN2_MspInit 1 */ } } 8002e6c: b03a add sp, #232 @ 0xe8 8002e6e: bd10 pop {r4, pc} PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; 8002e70: f44f 4200 mov.w r2, #32768 @ 0x8000 8002e74: 2300 movs r3, #0 8002e76: e9cd 2304 strd r2, r3, [sp, #16] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002e7a: a804 add r0, sp, #16 8002e7c: f001 f86a bl 8003f54 8002e80: bb08 cbnz r0, 8002ec6 HAL_RCC_FDCAN_CLK_ENABLED++; 8002e82: 4a39 ldr r2, [pc, #228] @ (8002f68 ) 8002e84: 6813 ldr r3, [r2, #0] 8002e86: 3301 adds r3, #1 8002e88: 6013 str r3, [r2, #0] if(HAL_RCC_FDCAN_CLK_ENABLED==1){ 8002e8a: 2b01 cmp r3, #1 8002e8c: d01e beq.n 8002ecc __HAL_RCC_GPIOB_CLK_ENABLE(); 8002e8e: 4b37 ldr r3, [pc, #220] @ (8002f6c ) 8002e90: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8002e94: f042 0202 orr.w r2, r2, #2 8002e98: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8002e9c: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8002ea0: f003 0302 and.w r3, r3, #2 8002ea4: 9301 str r3, [sp, #4] 8002ea6: 9b01 ldr r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; 8002ea8: f44f 7340 mov.w r3, #768 @ 0x300 8002eac: 9335 str r3, [sp, #212] @ 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002eae: 2302 movs r3, #2 8002eb0: 9336 str r3, [sp, #216] @ 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002eb2: 2300 movs r3, #0 8002eb4: 9337 str r3, [sp, #220] @ 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002eb6: 9338 str r3, [sp, #224] @ 0xe0 GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1; 8002eb8: 2309 movs r3, #9 8002eba: 9339 str r3, [sp, #228] @ 0xe4 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002ebc: a935 add r1, sp, #212 @ 0xd4 8002ebe: 482c ldr r0, [pc, #176] @ (8002f70 ) 8002ec0: f7ff fdec bl 8002a9c 8002ec4: e7d2 b.n 8002e6c Error_Handler(); 8002ec6: f7fd faf3 bl 80004b0 8002eca: e7da b.n 8002e82 __HAL_RCC_FDCAN_CLK_ENABLE(); 8002ecc: 4b27 ldr r3, [pc, #156] @ (8002f6c ) 8002ece: f8d3 214c ldr.w r2, [r3, #332] @ 0x14c 8002ed2: f442 7280 orr.w r2, r2, #256 @ 0x100 8002ed6: f8c3 214c str.w r2, [r3, #332] @ 0x14c 8002eda: f8d3 314c ldr.w r3, [r3, #332] @ 0x14c 8002ede: f403 7380 and.w r3, r3, #256 @ 0x100 8002ee2: 9300 str r3, [sp, #0] 8002ee4: 9b00 ldr r3, [sp, #0] 8002ee6: e7d2 b.n 8002e8e PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; 8002ee8: f44f 4200 mov.w r2, #32768 @ 0x8000 8002eec: 2300 movs r3, #0 8002eee: e9cd 2304 strd r2, r3, [sp, #16] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002ef2: a804 add r0, sp, #16 8002ef4: f001 f82e bl 8003f54 8002ef8: bb08 cbnz r0, 8002f3e HAL_RCC_FDCAN_CLK_ENABLED++; 8002efa: 4a1b ldr r2, [pc, #108] @ (8002f68 ) 8002efc: 6813 ldr r3, [r2, #0] 8002efe: 3301 adds r3, #1 8002f00: 6013 str r3, [r2, #0] if(HAL_RCC_FDCAN_CLK_ENABLED==1){ 8002f02: 2b01 cmp r3, #1 8002f04: d01e beq.n 8002f44 __HAL_RCC_GPIOB_CLK_ENABLE(); 8002f06: 4b19 ldr r3, [pc, #100] @ (8002f6c ) 8002f08: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8002f0c: f042 0202 orr.w r2, r2, #2 8002f10: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8002f14: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8002f18: f003 0302 and.w r3, r3, #2 8002f1c: 9303 str r3, [sp, #12] 8002f1e: 9b03 ldr r3, [sp, #12] GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; 8002f20: f44f 5340 mov.w r3, #12288 @ 0x3000 8002f24: 9335 str r3, [sp, #212] @ 0xd4 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8002f26: 2302 movs r3, #2 8002f28: 9336 str r3, [sp, #216] @ 0xd8 GPIO_InitStruct.Pull = GPIO_NOPULL; 8002f2a: 2300 movs r3, #0 8002f2c: 9337 str r3, [sp, #220] @ 0xdc GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8002f2e: 9338 str r3, [sp, #224] @ 0xe0 GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; 8002f30: 2309 movs r3, #9 8002f32: 9339 str r3, [sp, #228] @ 0xe4 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002f34: a935 add r1, sp, #212 @ 0xd4 8002f36: 480e ldr r0, [pc, #56] @ (8002f70 ) 8002f38: f7ff fdb0 bl 8002a9c } 8002f3c: e796 b.n 8002e6c Error_Handler(); 8002f3e: f7fd fab7 bl 80004b0 8002f42: e7da b.n 8002efa __HAL_RCC_FDCAN_CLK_ENABLE(); 8002f44: 4b09 ldr r3, [pc, #36] @ (8002f6c ) 8002f46: f8d3 214c ldr.w r2, [r3, #332] @ 0x14c 8002f4a: f442 7280 orr.w r2, r2, #256 @ 0x100 8002f4e: f8c3 214c str.w r2, [r3, #332] @ 0x14c 8002f52: f8d3 314c ldr.w r3, [r3, #332] @ 0x14c 8002f56: f403 7380 and.w r3, r3, #256 @ 0x100 8002f5a: 9302 str r3, [sp, #8] 8002f5c: 9b02 ldr r3, [sp, #8] 8002f5e: e7d2 b.n 8002f06 8002f60: 4000a000 .word 0x4000a000 8002f64: 4000a400 .word 0x4000a400 8002f68: 200003c8 .word 0x200003c8 8002f6c: 58024400 .word 0x58024400 8002f70: 58020400 .word 0x58020400 08002f74 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8002f74: b082 sub sp, #8 if(htim_base->Instance==TIM1) 8002f76: 6803 ldr r3, [r0, #0] 8002f78: 4a11 ldr r2, [pc, #68] @ (8002fc0 ) 8002f7a: 4293 cmp r3, r2 8002f7c: d004 beq.n 8002f88 __HAL_RCC_TIM1_CLK_ENABLE(); /* USER CODE BEGIN TIM1_MspInit 1 */ /* USER CODE END TIM1_MspInit 1 */ } else if(htim_base->Instance==TIM6) 8002f7e: 4a11 ldr r2, [pc, #68] @ (8002fc4 ) 8002f80: 4293 cmp r3, r2 8002f82: d00f beq.n 8002fa4 /* USER CODE BEGIN TIM6_MspInit 1 */ /* USER CODE END TIM6_MspInit 1 */ } } 8002f84: b002 add sp, #8 8002f86: 4770 bx lr __HAL_RCC_TIM1_CLK_ENABLE(); 8002f88: 4b0f ldr r3, [pc, #60] @ (8002fc8 ) 8002f8a: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 8002f8e: f042 0201 orr.w r2, r2, #1 8002f92: f8c3 2150 str.w r2, [r3, #336] @ 0x150 8002f96: f8d3 3150 ldr.w r3, [r3, #336] @ 0x150 8002f9a: f003 0301 and.w r3, r3, #1 8002f9e: 9300 str r3, [sp, #0] 8002fa0: 9b00 ldr r3, [sp, #0] 8002fa2: e7ef b.n 8002f84 __HAL_RCC_TIM6_CLK_ENABLE(); 8002fa4: 4b08 ldr r3, [pc, #32] @ (8002fc8 ) 8002fa6: f8d3 2148 ldr.w r2, [r3, #328] @ 0x148 8002faa: f042 0210 orr.w r2, r2, #16 8002fae: f8c3 2148 str.w r2, [r3, #328] @ 0x148 8002fb2: f8d3 3148 ldr.w r3, [r3, #328] @ 0x148 8002fb6: f003 0310 and.w r3, r3, #16 8002fba: 9301 str r3, [sp, #4] 8002fbc: 9b01 ldr r3, [sp, #4] } 8002fbe: e7e1 b.n 8002f84 8002fc0: 40010000 .word 0x40010000 8002fc4: 40001000 .word 0x40001000 8002fc8: 58024400 .word 0x58024400 08002fcc : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 8002fcc: b082 sub sp, #8 if(htim_pwm->Instance==TIM3) 8002fce: 6803 ldr r3, [r0, #0] 8002fd0: 4a11 ldr r2, [pc, #68] @ (8003018 ) 8002fd2: 4293 cmp r3, r2 8002fd4: d004 beq.n 8002fe0 __HAL_RCC_TIM3_CLK_ENABLE(); /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } else if(htim_pwm->Instance==TIM4) 8002fd6: 4a11 ldr r2, [pc, #68] @ (800301c ) 8002fd8: 4293 cmp r3, r2 8002fda: d00f beq.n 8002ffc /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 8002fdc: b002 add sp, #8 8002fde: 4770 bx lr __HAL_RCC_TIM3_CLK_ENABLE(); 8002fe0: 4b0f ldr r3, [pc, #60] @ (8003020 ) 8002fe2: f8d3 2148 ldr.w r2, [r3, #328] @ 0x148 8002fe6: f042 0202 orr.w r2, r2, #2 8002fea: f8c3 2148 str.w r2, [r3, #328] @ 0x148 8002fee: f8d3 3148 ldr.w r3, [r3, #328] @ 0x148 8002ff2: f003 0302 and.w r3, r3, #2 8002ff6: 9300 str r3, [sp, #0] 8002ff8: 9b00 ldr r3, [sp, #0] 8002ffa: e7ef b.n 8002fdc __HAL_RCC_TIM4_CLK_ENABLE(); 8002ffc: 4b08 ldr r3, [pc, #32] @ (8003020 ) 8002ffe: f8d3 2148 ldr.w r2, [r3, #328] @ 0x148 8003002: f042 0204 orr.w r2, r2, #4 8003006: f8c3 2148 str.w r2, [r3, #328] @ 0x148 800300a: f8d3 3148 ldr.w r3, [r3, #328] @ 0x148 800300e: f003 0304 and.w r3, r3, #4 8003012: 9301 str r3, [sp, #4] 8003014: 9b01 ldr r3, [sp, #4] } 8003016: e7e1 b.n 8002fdc 8003018: 40000400 .word 0x40000400 800301c: 40000800 .word 0x40000800 8003020: 58024400 .word 0x58024400 08003024 : * This function configures the hardware resources used in this example * @param htim_ic: TIM_IC handle pointer * @retval None */ void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* htim_ic) { 8003024: b500 push {lr} 8003026: b089 sub sp, #36 @ 0x24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003028: 2300 movs r3, #0 800302a: 9303 str r3, [sp, #12] 800302c: 9304 str r3, [sp, #16] 800302e: 9305 str r3, [sp, #20] 8003030: 9306 str r3, [sp, #24] 8003032: 9307 str r3, [sp, #28] if(htim_ic->Instance==TIM8) 8003034: 6802 ldr r2, [r0, #0] 8003036: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000 800303a: f503 3382 add.w r3, r3, #66560 @ 0x10400 800303e: 429a cmp r2, r3 8003040: d002 beq.n 8003048 /* USER CODE END TIM8_MspInit 1 */ } } 8003042: b009 add sp, #36 @ 0x24 8003044: f85d fb04 ldr.w pc, [sp], #4 __HAL_RCC_TIM8_CLK_ENABLE(); 8003048: 4b11 ldr r3, [pc, #68] @ (8003090 ) 800304a: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 800304e: f042 0202 orr.w r2, r2, #2 8003052: f8c3 2150 str.w r2, [r3, #336] @ 0x150 8003056: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150 800305a: f002 0202 and.w r2, r2, #2 800305e: 9201 str r2, [sp, #4] 8003060: 9a01 ldr r2, [sp, #4] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003062: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8003066: f042 0204 orr.w r2, r2, #4 800306a: f8c3 2140 str.w r2, [r3, #320] @ 0x140 800306e: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8003072: f003 0304 and.w r3, r3, #4 8003076: 9302 str r3, [sp, #8] 8003078: 9b02 ldr r3, [sp, #8] GPIO_InitStruct.Pin = WS1_Pin|WS2_Pin; 800307a: 23c0 movs r3, #192 @ 0xc0 800307c: 9303 str r3, [sp, #12] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800307e: 2302 movs r3, #2 8003080: 9304 str r3, [sp, #16] GPIO_InitStruct.Alternate = GPIO_AF3_TIM8; 8003082: 2303 movs r3, #3 8003084: 9307 str r3, [sp, #28] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003086: a903 add r1, sp, #12 8003088: 4802 ldr r0, [pc, #8] @ (8003094 ) 800308a: f7ff fd07 bl 8002a9c } 800308e: e7d8 b.n 8003042 8003090: 58024400 .word 0x58024400 8003094: 58020800 .word 0x58020800 08003098 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8003098: b530 push {r4, r5, lr} 800309a: b08b sub sp, #44 @ 0x2c GPIO_InitTypeDef GPIO_InitStruct = {0}; 800309c: 2300 movs r3, #0 800309e: 9305 str r3, [sp, #20] 80030a0: 9306 str r3, [sp, #24] 80030a2: 9307 str r3, [sp, #28] 80030a4: 9308 str r3, [sp, #32] 80030a6: 9309 str r3, [sp, #36] @ 0x24 if(htim->Instance==TIM1) 80030a8: 6803 ldr r3, [r0, #0] 80030aa: 4a35 ldr r2, [pc, #212] @ (8003180 ) 80030ac: 4293 cmp r3, r2 80030ae: d007 beq.n 80030c0 /* USER CODE BEGIN TIM1_MspPostInit 1 */ /* USER CODE END TIM1_MspPostInit 1 */ } else if(htim->Instance==TIM3) 80030b0: 4a34 ldr r2, [pc, #208] @ (8003184 ) 80030b2: 4293 cmp r3, r2 80030b4: d01d beq.n 80030f2 /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } else if(htim->Instance==TIM4) 80030b6: 4a34 ldr r2, [pc, #208] @ (8003188 ) 80030b8: 4293 cmp r3, r2 80030ba: d04a beq.n 8003152 /* USER CODE BEGIN TIM4_MspPostInit 1 */ /* USER CODE END TIM4_MspPostInit 1 */ } } 80030bc: b00b add sp, #44 @ 0x2c 80030be: bd30 pop {r4, r5, pc} __HAL_RCC_GPIOA_CLK_ENABLE(); 80030c0: 4b32 ldr r3, [pc, #200] @ (800318c ) 80030c2: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 80030c6: f042 0201 orr.w r2, r2, #1 80030ca: f8c3 2140 str.w r2, [r3, #320] @ 0x140 80030ce: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 80030d2: f003 0301 and.w r3, r3, #1 80030d6: 9301 str r3, [sp, #4] 80030d8: 9b01 ldr r3, [sp, #4] GPIO_InitStruct.Pin = PWM1_1_Pin|PWM1_2_Pin|PWM1_3_Pin|PWM1_4_Pin; 80030da: f44f 6370 mov.w r3, #3840 @ 0xf00 80030de: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80030e0: 2302 movs r3, #2 80030e2: 9306 str r3, [sp, #24] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 80030e4: 2301 movs r3, #1 80030e6: 9309 str r3, [sp, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80030e8: a905 add r1, sp, #20 80030ea: 4829 ldr r0, [pc, #164] @ (8003190 ) 80030ec: f7ff fcd6 bl 8002a9c 80030f0: e7e4 b.n 80030bc __HAL_RCC_GPIOC_CLK_ENABLE(); 80030f2: 4b26 ldr r3, [pc, #152] @ (800318c ) 80030f4: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 80030f8: f042 0204 orr.w r2, r2, #4 80030fc: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8003100: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8003104: f002 0204 and.w r2, r2, #4 8003108: 9202 str r2, [sp, #8] 800310a: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 800310c: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8003110: f042 0202 orr.w r2, r2, #2 8003114: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8003118: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 800311c: f003 0302 and.w r3, r3, #2 8003120: 9303 str r3, [sp, #12] 8003122: 9b03 ldr r3, [sp, #12] GPIO_InitStruct.Pin = PWM2_2_Pin; 8003124: f44f 7300 mov.w r3, #512 @ 0x200 8003128: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800312a: 2402 movs r4, #2 800312c: 9406 str r4, [sp, #24] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 800312e: 9409 str r4, [sp, #36] @ 0x24 HAL_GPIO_Init(PWM2_2_GPIO_Port, &GPIO_InitStruct); 8003130: ad05 add r5, sp, #20 8003132: 4629 mov r1, r5 8003134: 4817 ldr r0, [pc, #92] @ (8003194 ) 8003136: f7ff fcb1 bl 8002a9c GPIO_InitStruct.Pin = PWM2_1_Pin; 800313a: 2320 movs r3, #32 800313c: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800313e: 9406 str r4, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003140: 2300 movs r3, #0 8003142: 9307 str r3, [sp, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003144: 9308 str r3, [sp, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 8003146: 9409 str r4, [sp, #36] @ 0x24 HAL_GPIO_Init(PWM2_1_GPIO_Port, &GPIO_InitStruct); 8003148: 4629 mov r1, r5 800314a: 4813 ldr r0, [pc, #76] @ (8003198 ) 800314c: f7ff fca6 bl 8002a9c 8003150: e7b4 b.n 80030bc __HAL_RCC_GPIOB_CLK_ENABLE(); 8003152: 4b0e ldr r3, [pc, #56] @ (800318c ) 8003154: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140 8003158: f042 0202 orr.w r2, r2, #2 800315c: f8c3 2140 str.w r2, [r3, #320] @ 0x140 8003160: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140 8003164: f003 0302 and.w r3, r3, #2 8003168: 9304 str r3, [sp, #16] 800316a: 9b04 ldr r3, [sp, #16] GPIO_InitStruct.Pin = PWM3_2_Pin|PWM3_2B7_Pin; 800316c: 23c0 movs r3, #192 @ 0xc0 800316e: 9305 str r3, [sp, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003170: 2302 movs r3, #2 8003172: 9306 str r3, [sp, #24] GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; 8003174: 9309 str r3, [sp, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003176: a905 add r1, sp, #20 8003178: 4807 ldr r0, [pc, #28] @ (8003198 ) 800317a: f7ff fc8f bl 8002a9c } 800317e: e79d b.n 80030bc 8003180: 40010000 .word 0x40010000 8003184: 40000400 .word 0x40000400 8003188: 40000800 .word 0x40000800 800318c: 58024400 .word 0x58024400 8003190: 58020000 .word 0x58020000 8003194: 58020800 .word 0x58020800 8003198: 58020400 .word 0x58020400 0800319c : /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800319c: 4b13 ldr r3, [pc, #76] @ (80031ec ) 800319e: 68db ldr r3, [r3, #12] 80031a0: f013 0f04 tst.w r3, #4 80031a4: d107 bne.n 80031b6 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 80031a6: 4b11 ldr r3, [pc, #68] @ (80031ec ) 80031a8: 68db ldr r3, [r3, #12] 80031aa: f003 0307 and.w r3, r3, #7 80031ae: 4283 cmp r3, r0 80031b0: d01a beq.n 80031e8 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 80031b2: 2001 movs r0, #1 80031b4: 4770 bx lr { 80031b6: b510 push {r4, lr} return HAL_OK; } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 80031b8: 4a0c ldr r2, [pc, #48] @ (80031ec ) 80031ba: 68d3 ldr r3, [r2, #12] 80031bc: f023 0307 bic.w r3, r3, #7 80031c0: 4303 orrs r3, r0 80031c2: 60d3 str r3, [r2, #12] /* Get tick */ tickstart = HAL_GetTick (); 80031c4: f7fd fcca bl 8000b5c 80031c8: 4604 mov r4, r0 /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 80031ca: 4b08 ldr r3, [pc, #32] @ (80031ec ) 80031cc: 685b ldr r3, [r3, #4] 80031ce: f413 5f00 tst.w r3, #8192 @ 0x2000 80031d2: d107 bne.n 80031e4 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 80031d4: f7fd fcc2 bl 8000b5c 80031d8: 1b00 subs r0, r0, r4 80031da: f5b0 7f7a cmp.w r0, #1000 @ 0x3e8 80031de: d9f4 bls.n 80031ca { return HAL_ERROR; 80031e0: 2001 movs r0, #1 80031e2: e000 b.n 80031e6 } } } #endif /* defined (SMPS) */ return HAL_OK; 80031e4: 2000 movs r0, #0 } 80031e6: bd10 pop {r4, pc} return HAL_OK; 80031e8: 2000 movs r0, #0 } 80031ea: 4770 bx lr 80031ec: 58024800 .word 0x58024800 080031f0 : { uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80031f0: 2800 cmp r0, #0 80031f2: f000 8311 beq.w 8003818 { 80031f6: b538 push {r3, r4, r5, lr} 80031f8: 4604 mov r4, r0 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80031fa: 6803 ldr r3, [r0, #0] 80031fc: f013 0f01 tst.w r3, #1 8003200: d029 beq.n 8003256 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003202: 4aa1 ldr r2, [pc, #644] @ (8003488 ) 8003204: 6913 ldr r3, [r2, #16] 8003206: f003 0338 and.w r3, r3, #56 @ 0x38 const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800320a: 6a92 ldr r2, [r2, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800320c: 2b10 cmp r3, #16 800320e: d019 beq.n 8003244 8003210: 2b18 cmp r3, #24 8003212: d013 beq.n 800323c } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8003214: 6863 ldr r3, [r4, #4] 8003216: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800321a: d043 beq.n 80032a4 800321c: 2b00 cmp r3, #0 800321e: d158 bne.n 80032d2 8003220: 4b99 ldr r3, [pc, #612] @ (8003488 ) 8003222: 681a ldr r2, [r3, #0] 8003224: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8003228: 601a str r2, [r3, #0] 800322a: 681a ldr r2, [r3, #0] 800322c: f422 1280 bic.w r2, r2, #1048576 @ 0x100000 8003230: 601a str r2, [r3, #0] 8003232: 681a ldr r2, [r3, #0] 8003234: f422 2280 bic.w r2, r2, #262144 @ 0x40000 8003238: 601a str r2, [r3, #0] 800323a: e038 b.n 80032ae if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800323c: f002 0203 and.w r2, r2, #3 8003240: 2a02 cmp r2, #2 8003242: d1e7 bne.n 8003214 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003244: 4b90 ldr r3, [pc, #576] @ (8003488 ) 8003246: 681b ldr r3, [r3, #0] 8003248: f413 3f00 tst.w r3, #131072 @ 0x20000 800324c: d003 beq.n 8003256 800324e: 6863 ldr r3, [r4, #4] 8003250: 2b00 cmp r3, #0 8003252: f000 82e3 beq.w 800381c } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8003256: 6823 ldr r3, [r4, #0] 8003258: f013 0f02 tst.w r3, #2 800325c: f000 80a2 beq.w 80033a4 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003260: 4a89 ldr r2, [pc, #548] @ (8003488 ) 8003262: 6913 ldr r3, [r2, #16] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8003264: 6a92 ldr r2, [r2, #40] @ 0x28 if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 8003266: f013 0338 ands.w r3, r3, #56 @ 0x38 800326a: d074 beq.n 8003356 800326c: 2b18 cmp r3, #24 800326e: d06f beq.n 8003350 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8003270: 68e3 ldr r3, [r4, #12] 8003272: 2b00 cmp r3, #0 8003274: f000 80c3 beq.w 80033fe { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 8003278: 4983 ldr r1, [pc, #524] @ (8003488 ) 800327a: 680a ldr r2, [r1, #0] 800327c: f022 0219 bic.w r2, r2, #25 8003280: 4313 orrs r3, r2 8003282: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003284: f7fd fc6a bl 8000b5c 8003288: 4605 mov r5, r0 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800328a: 4b7f ldr r3, [pc, #508] @ (8003488 ) 800328c: 681b ldr r3, [r3, #0] 800328e: f013 0f04 tst.w r3, #4 8003292: f040 80ab bne.w 80033ec { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003296: f7fd fc61 bl 8000b5c 800329a: 1b40 subs r0, r0, r5 800329c: 2802 cmp r0, #2 800329e: d9f4 bls.n 800328a { return HAL_TIMEOUT; 80032a0: 2003 movs r0, #3 80032a2: e2c2 b.n 800382a __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80032a4: 4a78 ldr r2, [pc, #480] @ (8003488 ) 80032a6: 6813 ldr r3, [r2, #0] 80032a8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80032ac: 6013 str r3, [r2, #0] if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80032ae: 6863 ldr r3, [r4, #4] 80032b0: 2b00 cmp r3, #0 80032b2: d03e beq.n 8003332 tickstart = HAL_GetTick(); 80032b4: f7fd fc52 bl 8000b5c 80032b8: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80032ba: 4b73 ldr r3, [pc, #460] @ (8003488 ) 80032bc: 681b ldr r3, [r3, #0] 80032be: f413 3f00 tst.w r3, #131072 @ 0x20000 80032c2: d1c8 bne.n 8003256 if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80032c4: f7fd fc4a bl 8000b5c 80032c8: 1b40 subs r0, r0, r5 80032ca: 2864 cmp r0, #100 @ 0x64 80032cc: d9f5 bls.n 80032ba return HAL_TIMEOUT; 80032ce: 2003 movs r0, #3 80032d0: e2ab b.n 800382a __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80032d2: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80032d6: d010 beq.n 80032fa 80032d8: f5b3 1fa8 cmp.w r3, #1376256 @ 0x150000 80032dc: d01b beq.n 8003316 80032de: 4b6a ldr r3, [pc, #424] @ (8003488 ) 80032e0: 681a ldr r2, [r3, #0] 80032e2: f422 3280 bic.w r2, r2, #65536 @ 0x10000 80032e6: 601a str r2, [r3, #0] 80032e8: 681a ldr r2, [r3, #0] 80032ea: f422 2280 bic.w r2, r2, #262144 @ 0x40000 80032ee: 601a str r2, [r3, #0] 80032f0: 681a ldr r2, [r3, #0] 80032f2: f422 1280 bic.w r2, r2, #1048576 @ 0x100000 80032f6: 601a str r2, [r3, #0] 80032f8: e7d9 b.n 80032ae 80032fa: 4b63 ldr r3, [pc, #396] @ (8003488 ) 80032fc: 681a ldr r2, [r3, #0] 80032fe: f442 2280 orr.w r2, r2, #262144 @ 0x40000 8003302: 601a str r2, [r3, #0] 8003304: 681a ldr r2, [r3, #0] 8003306: f422 1280 bic.w r2, r2, #1048576 @ 0x100000 800330a: 601a str r2, [r3, #0] 800330c: 681a ldr r2, [r3, #0] 800330e: f442 3280 orr.w r2, r2, #65536 @ 0x10000 8003312: 601a str r2, [r3, #0] 8003314: e7cb b.n 80032ae 8003316: 4b5c ldr r3, [pc, #368] @ (8003488 ) 8003318: 681a ldr r2, [r3, #0] 800331a: f442 2280 orr.w r2, r2, #262144 @ 0x40000 800331e: 601a str r2, [r3, #0] 8003320: 681a ldr r2, [r3, #0] 8003322: f442 1280 orr.w r2, r2, #1048576 @ 0x100000 8003326: 601a str r2, [r3, #0] 8003328: 681a ldr r2, [r3, #0] 800332a: f442 3280 orr.w r2, r2, #65536 @ 0x10000 800332e: 601a str r2, [r3, #0] 8003330: e7bd b.n 80032ae tickstart = HAL_GetTick(); 8003332: f7fd fc13 bl 8000b5c 8003336: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8003338: 4b53 ldr r3, [pc, #332] @ (8003488 ) 800333a: 681b ldr r3, [r3, #0] 800333c: f413 3f00 tst.w r3, #131072 @ 0x20000 8003340: d089 beq.n 8003256 if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003342: f7fd fc0b bl 8000b5c 8003346: 1b40 subs r0, r0, r5 8003348: 2864 cmp r0, #100 @ 0x64 800334a: d9f5 bls.n 8003338 return HAL_TIMEOUT; 800334c: 2003 movs r0, #3 800334e: e26c b.n 800382a if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 8003350: f012 0f03 tst.w r2, #3 8003354: d18c bne.n 8003270 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003356: 4b4c ldr r3, [pc, #304] @ (8003488 ) 8003358: 681b ldr r3, [r3, #0] 800335a: f013 0f04 tst.w r3, #4 800335e: d003 beq.n 8003368 8003360: 68e3 ldr r3, [r4, #12] 8003362: 2b00 cmp r3, #0 8003364: f000 825c beq.w 8003820 __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 8003368: 4a47 ldr r2, [pc, #284] @ (8003488 ) 800336a: 6813 ldr r3, [r2, #0] 800336c: f023 0319 bic.w r3, r3, #25 8003370: 68e1 ldr r1, [r4, #12] 8003372: 430b orrs r3, r1 8003374: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 8003376: f7fd fbf1 bl 8000b5c 800337a: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800337c: 4b42 ldr r3, [pc, #264] @ (8003488 ) 800337e: 681b ldr r3, [r3, #0] 8003380: f013 0f04 tst.w r3, #4 8003384: d106 bne.n 8003394 if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003386: f7fd fbe9 bl 8000b5c 800338a: 1b40 subs r0, r0, r5 800338c: 2802 cmp r0, #2 800338e: d9f5 bls.n 800337c return HAL_TIMEOUT; 8003390: 2003 movs r0, #3 8003392: e24a b.n 800382a __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003394: 4a3c ldr r2, [pc, #240] @ (8003488 ) 8003396: 6853 ldr r3, [r2, #4] 8003398: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000 800339c: 6921 ldr r1, [r4, #16] 800339e: ea43 6301 orr.w r3, r3, r1, lsl #24 80033a2: 6053 str r3, [r2, #4] } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 80033a4: 6823 ldr r3, [r4, #0] 80033a6: f013 0f10 tst.w r3, #16 80033aa: d051 beq.n 8003450 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80033ac: 4a36 ldr r2, [pc, #216] @ (8003488 ) 80033ae: 6913 ldr r3, [r2, #16] 80033b0: f003 0338 and.w r3, r3, #56 @ 0x38 const uint32_t temp_pllckselr = RCC->PLLCKSELR; 80033b4: 6a92 ldr r2, [r2, #40] @ 0x28 if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 80033b6: 2b08 cmp r3, #8 80033b8: d039 beq.n 800342e 80033ba: 2b18 cmp r3, #24 80033bc: d033 beq.n 8003426 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 80033be: 69e3 ldr r3, [r4, #28] 80033c0: 2b00 cmp r3, #0 80033c2: d06c beq.n 800349e { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 80033c4: 4a30 ldr r2, [pc, #192] @ (8003488 ) 80033c6: 6813 ldr r3, [r2, #0] 80033c8: f043 0380 orr.w r3, r3, #128 @ 0x80 80033cc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80033ce: f7fd fbc5 bl 8000b5c 80033d2: 4605 mov r5, r0 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80033d4: 4b2c ldr r3, [pc, #176] @ (8003488 ) 80033d6: 681b ldr r3, [r3, #0] 80033d8: f413 7f80 tst.w r3, #256 @ 0x100 80033dc: d156 bne.n 800348c { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 80033de: f7fd fbbd bl 8000b5c 80033e2: 1b40 subs r0, r0, r5 80033e4: 2802 cmp r0, #2 80033e6: d9f5 bls.n 80033d4 { return HAL_TIMEOUT; 80033e8: 2003 movs r0, #3 80033ea: e21e b.n 800382a __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80033ec: 4a26 ldr r2, [pc, #152] @ (8003488 ) 80033ee: 6853 ldr r3, [r2, #4] 80033f0: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000 80033f4: 6921 ldr r1, [r4, #16] 80033f6: ea43 6301 orr.w r3, r3, r1, lsl #24 80033fa: 6053 str r3, [r2, #4] 80033fc: e7d2 b.n 80033a4 __HAL_RCC_HSI_DISABLE(); 80033fe: 4a22 ldr r2, [pc, #136] @ (8003488 ) 8003400: 6813 ldr r3, [r2, #0] 8003402: f023 0301 bic.w r3, r3, #1 8003406: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 8003408: f7fd fba8 bl 8000b5c 800340c: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800340e: 4b1e ldr r3, [pc, #120] @ (8003488 ) 8003410: 681b ldr r3, [r3, #0] 8003412: f013 0f04 tst.w r3, #4 8003416: d0c5 beq.n 80033a4 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003418: f7fd fba0 bl 8000b5c 800341c: 1b40 subs r0, r0, r5 800341e: 2802 cmp r0, #2 8003420: d9f5 bls.n 800340e return HAL_TIMEOUT; 8003422: 2003 movs r0, #3 8003424: e201 b.n 800382a if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 8003426: f002 0203 and.w r2, r2, #3 800342a: 2a01 cmp r2, #1 800342c: d1c7 bne.n 80033be if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800342e: 4b16 ldr r3, [pc, #88] @ (8003488 ) 8003430: 681b ldr r3, [r3, #0] 8003432: f413 7f80 tst.w r3, #256 @ 0x100 8003436: d003 beq.n 8003440 8003438: 69e3 ldr r3, [r4, #28] 800343a: 2b80 cmp r3, #128 @ 0x80 800343c: f040 81f2 bne.w 8003824 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 8003440: 4a11 ldr r2, [pc, #68] @ (8003488 ) 8003442: 68d3 ldr r3, [r2, #12] 8003444: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000 8003448: 6a21 ldr r1, [r4, #32] 800344a: ea43 6301 orr.w r3, r3, r1, lsl #24 800344e: 60d3 str r3, [r2, #12] } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003450: 6823 ldr r3, [r4, #0] 8003452: f013 0f08 tst.w r3, #8 8003456: d04a beq.n 80034ee { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8003458: 6963 ldr r3, [r4, #20] 800345a: 2b00 cmp r3, #0 800345c: d033 beq.n 80034c6 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800345e: 4a0a ldr r2, [pc, #40] @ (8003488 ) 8003460: 6f53 ldr r3, [r2, #116] @ 0x74 8003462: f043 0301 orr.w r3, r3, #1 8003466: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003468: f7fd fb78 bl 8000b5c 800346c: 4605 mov r5, r0 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800346e: 4b06 ldr r3, [pc, #24] @ (8003488 ) 8003470: 6f5b ldr r3, [r3, #116] @ 0x74 8003472: f013 0f02 tst.w r3, #2 8003476: d13a bne.n 80034ee { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003478: f7fd fb70 bl 8000b5c 800347c: 1b40 subs r0, r0, r5 800347e: 2802 cmp r0, #2 8003480: d9f5 bls.n 800346e { return HAL_TIMEOUT; 8003482: 2003 movs r0, #3 8003484: e1d1 b.n 800382a 8003486: bf00 nop 8003488: 58024400 .word 0x58024400 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800348c: 4a8c ldr r2, [pc, #560] @ (80036c0 ) 800348e: 68d3 ldr r3, [r2, #12] 8003490: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000 8003494: 6a21 ldr r1, [r4, #32] 8003496: ea43 6301 orr.w r3, r3, r1, lsl #24 800349a: 60d3 str r3, [r2, #12] 800349c: e7d8 b.n 8003450 __HAL_RCC_CSI_DISABLE(); 800349e: 4a88 ldr r2, [pc, #544] @ (80036c0 ) 80034a0: 6813 ldr r3, [r2, #0] 80034a2: f023 0380 bic.w r3, r3, #128 @ 0x80 80034a6: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 80034a8: f7fd fb58 bl 8000b5c 80034ac: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 80034ae: 4b84 ldr r3, [pc, #528] @ (80036c0 ) 80034b0: 681b ldr r3, [r3, #0] 80034b2: f413 7f80 tst.w r3, #256 @ 0x100 80034b6: d0cb beq.n 8003450 if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 80034b8: f7fd fb50 bl 8000b5c 80034bc: 1b40 subs r0, r0, r5 80034be: 2802 cmp r0, #2 80034c0: d9f5 bls.n 80034ae return HAL_TIMEOUT; 80034c2: 2003 movs r0, #3 80034c4: e1b1 b.n 800382a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80034c6: 4a7e ldr r2, [pc, #504] @ (80036c0 ) 80034c8: 6f53 ldr r3, [r2, #116] @ 0x74 80034ca: f023 0301 bic.w r3, r3, #1 80034ce: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80034d0: f7fd fb44 bl 8000b5c 80034d4: 4605 mov r5, r0 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 80034d6: 4b7a ldr r3, [pc, #488] @ (80036c0 ) 80034d8: 6f5b ldr r3, [r3, #116] @ 0x74 80034da: f013 0f02 tst.w r3, #2 80034de: d006 beq.n 80034ee { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80034e0: f7fd fb3c bl 8000b5c 80034e4: 1b40 subs r0, r0, r5 80034e6: 2802 cmp r0, #2 80034e8: d9f5 bls.n 80034d6 { return HAL_TIMEOUT; 80034ea: 2003 movs r0, #3 80034ec: e19d b.n 800382a } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 80034ee: 6823 ldr r3, [r4, #0] 80034f0: f013 0f20 tst.w r3, #32 80034f4: d029 beq.n 800354a { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 80034f6: 69a3 ldr r3, [r4, #24] 80034f8: b19b cbz r3, 8003522 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 80034fa: 4a71 ldr r2, [pc, #452] @ (80036c0 ) 80034fc: 6813 ldr r3, [r2, #0] 80034fe: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8003502: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 8003504: f7fd fb2a bl 8000b5c 8003508: 4605 mov r5, r0 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800350a: 4b6d ldr r3, [pc, #436] @ (80036c0 ) 800350c: 681b ldr r3, [r3, #0] 800350e: f413 5f00 tst.w r3, #8192 @ 0x2000 8003512: d11a bne.n 800354a { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8003514: f7fd fb22 bl 8000b5c 8003518: 1b40 subs r0, r0, r5 800351a: 2802 cmp r0, #2 800351c: d9f5 bls.n 800350a { return HAL_TIMEOUT; 800351e: 2003 movs r0, #3 8003520: e183 b.n 800382a } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8003522: 4a67 ldr r2, [pc, #412] @ (80036c0 ) 8003524: 6813 ldr r3, [r2, #0] 8003526: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800352a: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800352c: f7fd fb16 bl 8000b5c 8003530: 4605 mov r5, r0 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8003532: 4b63 ldr r3, [pc, #396] @ (80036c0 ) 8003534: 681b ldr r3, [r3, #0] 8003536: f413 5f00 tst.w r3, #8192 @ 0x2000 800353a: d006 beq.n 800354a { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800353c: f7fd fb0e bl 8000b5c 8003540: 1b40 subs r0, r0, r5 8003542: 2802 cmp r0, #2 8003544: d9f5 bls.n 8003532 { return HAL_TIMEOUT; 8003546: 2003 movs r0, #3 8003548: e16f b.n 800382a } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800354a: 6823 ldr r3, [r4, #0] 800354c: f013 0f04 tst.w r3, #4 8003550: d122 bne.n 8003598 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8003552: 6a63 ldr r3, [r4, #36] @ 0x24 8003554: 2b00 cmp r3, #0 8003556: f000 8167 beq.w 8003828 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800355a: 4a59 ldr r2, [pc, #356] @ (80036c0 ) 800355c: 6912 ldr r2, [r2, #16] 800355e: f002 0238 and.w r2, r2, #56 @ 0x38 8003562: 2a18 cmp r2, #24 8003564: f000 810e beq.w 8003784 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8003568: 2b02 cmp r3, #2 800356a: f000 8094 beq.w 8003696 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800356e: 4a54 ldr r2, [pc, #336] @ (80036c0 ) 8003570: 6813 ldr r3, [r2, #0] 8003572: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8003576: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003578: f7fd faf0 bl 8000b5c 800357c: 4604 mov r4, r0 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800357e: 4b50 ldr r3, [pc, #320] @ (80036c0 ) 8003580: 681b ldr r3, [r3, #0] 8003582: f013 7f00 tst.w r3, #33554432 @ 0x2000000 8003586: f000 80fb beq.w 8003780 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800358a: f7fd fae7 bl 8000b5c 800358e: 1b00 subs r0, r0, r4 8003590: 2802 cmp r0, #2 8003592: d9f4 bls.n 800357e { return HAL_TIMEOUT; 8003594: 2003 movs r0, #3 8003596: e148 b.n 800382a PWR->CR1 |= PWR_CR1_DBP; 8003598: 4a4a ldr r2, [pc, #296] @ (80036c4 ) 800359a: 6813 ldr r3, [r2, #0] 800359c: f443 7380 orr.w r3, r3, #256 @ 0x100 80035a0: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 80035a2: f7fd fadb bl 8000b5c 80035a6: 4605 mov r5, r0 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 80035a8: 4b46 ldr r3, [pc, #280] @ (80036c4 ) 80035aa: 681b ldr r3, [r3, #0] 80035ac: f413 7f80 tst.w r3, #256 @ 0x100 80035b0: d106 bne.n 80035c0 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80035b2: f7fd fad3 bl 8000b5c 80035b6: 1b40 subs r0, r0, r5 80035b8: 2864 cmp r0, #100 @ 0x64 80035ba: d9f5 bls.n 80035a8 return HAL_TIMEOUT; 80035bc: 2003 movs r0, #3 80035be: e134 b.n 800382a __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80035c0: 68a3 ldr r3, [r4, #8] 80035c2: 2b01 cmp r3, #1 80035c4: d00e beq.n 80035e4 80035c6: bb33 cbnz r3, 8003616 80035c8: 4b3d ldr r3, [pc, #244] @ (80036c0 ) 80035ca: 6f1a ldr r2, [r3, #112] @ 0x70 80035cc: f022 0201 bic.w r2, r2, #1 80035d0: 671a str r2, [r3, #112] @ 0x70 80035d2: 6f1a ldr r2, [r3, #112] @ 0x70 80035d4: f022 0280 bic.w r2, r2, #128 @ 0x80 80035d8: 671a str r2, [r3, #112] @ 0x70 80035da: 6f1a ldr r2, [r3, #112] @ 0x70 80035dc: f022 0204 bic.w r2, r2, #4 80035e0: 671a str r2, [r3, #112] @ 0x70 80035e2: e004 b.n 80035ee 80035e4: 4a36 ldr r2, [pc, #216] @ (80036c0 ) 80035e6: 6f13 ldr r3, [r2, #112] @ 0x70 80035e8: f043 0301 orr.w r3, r3, #1 80035ec: 6713 str r3, [r2, #112] @ 0x70 if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 80035ee: 68a3 ldr r3, [r4, #8] 80035f0: 2b00 cmp r3, #0 80035f2: d03e beq.n 8003672 tickstart = HAL_GetTick(); 80035f4: f7fd fab2 bl 8000b5c 80035f8: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80035fa: 4b31 ldr r3, [pc, #196] @ (80036c0 ) 80035fc: 6f1b ldr r3, [r3, #112] @ 0x70 80035fe: f013 0f02 tst.w r3, #2 8003602: d1a6 bne.n 8003552 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003604: f7fd faaa bl 8000b5c 8003608: 1b40 subs r0, r0, r5 800360a: f241 3388 movw r3, #5000 @ 0x1388 800360e: 4298 cmp r0, r3 8003610: d9f3 bls.n 80035fa return HAL_TIMEOUT; 8003612: 2003 movs r0, #3 8003614: e109 b.n 800382a __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003616: 2b05 cmp r3, #5 8003618: d00f beq.n 800363a 800361a: 2b85 cmp r3, #133 @ 0x85 800361c: d01b beq.n 8003656 800361e: 4b28 ldr r3, [pc, #160] @ (80036c0 ) 8003620: 6f1a ldr r2, [r3, #112] @ 0x70 8003622: f022 0201 bic.w r2, r2, #1 8003626: 671a str r2, [r3, #112] @ 0x70 8003628: 6f1a ldr r2, [r3, #112] @ 0x70 800362a: f022 0204 bic.w r2, r2, #4 800362e: 671a str r2, [r3, #112] @ 0x70 8003630: 6f1a ldr r2, [r3, #112] @ 0x70 8003632: f022 0280 bic.w r2, r2, #128 @ 0x80 8003636: 671a str r2, [r3, #112] @ 0x70 8003638: e7d9 b.n 80035ee 800363a: 4b21 ldr r3, [pc, #132] @ (80036c0 ) 800363c: 6f1a ldr r2, [r3, #112] @ 0x70 800363e: f042 0204 orr.w r2, r2, #4 8003642: 671a str r2, [r3, #112] @ 0x70 8003644: 6f1a ldr r2, [r3, #112] @ 0x70 8003646: f022 0280 bic.w r2, r2, #128 @ 0x80 800364a: 671a str r2, [r3, #112] @ 0x70 800364c: 6f1a ldr r2, [r3, #112] @ 0x70 800364e: f042 0201 orr.w r2, r2, #1 8003652: 671a str r2, [r3, #112] @ 0x70 8003654: e7cb b.n 80035ee 8003656: 4b1a ldr r3, [pc, #104] @ (80036c0 ) 8003658: 6f1a ldr r2, [r3, #112] @ 0x70 800365a: f042 0204 orr.w r2, r2, #4 800365e: 671a str r2, [r3, #112] @ 0x70 8003660: 6f1a ldr r2, [r3, #112] @ 0x70 8003662: f042 0280 orr.w r2, r2, #128 @ 0x80 8003666: 671a str r2, [r3, #112] @ 0x70 8003668: 6f1a ldr r2, [r3, #112] @ 0x70 800366a: f042 0201 orr.w r2, r2, #1 800366e: 671a str r2, [r3, #112] @ 0x70 8003670: e7bd b.n 80035ee tickstart = HAL_GetTick(); 8003672: f7fd fa73 bl 8000b5c 8003676: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8003678: 4b11 ldr r3, [pc, #68] @ (80036c0 ) 800367a: 6f1b ldr r3, [r3, #112] @ 0x70 800367c: f013 0f02 tst.w r3, #2 8003680: f43f af67 beq.w 8003552 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003684: f7fd fa6a bl 8000b5c 8003688: 1b40 subs r0, r0, r5 800368a: f241 3388 movw r3, #5000 @ 0x1388 800368e: 4298 cmp r0, r3 8003690: d9f2 bls.n 8003678 return HAL_TIMEOUT; 8003692: 2003 movs r0, #3 8003694: e0c9 b.n 800382a __HAL_RCC_PLL_DISABLE(); 8003696: 4a0a ldr r2, [pc, #40] @ (80036c0 ) 8003698: 6813 ldr r3, [r2, #0] 800369a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800369e: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 80036a0: f7fd fa5c bl 8000b5c 80036a4: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80036a6: 4b06 ldr r3, [pc, #24] @ (80036c0 ) 80036a8: 681b ldr r3, [r3, #0] 80036aa: f013 7f00 tst.w r3, #33554432 @ 0x2000000 80036ae: d00b beq.n 80036c8 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80036b0: f7fd fa54 bl 8000b5c 80036b4: 1b40 subs r0, r0, r5 80036b6: 2802 cmp r0, #2 80036b8: d9f5 bls.n 80036a6 return HAL_TIMEOUT; 80036ba: 2003 movs r0, #3 80036bc: e0b5 b.n 800382a 80036be: bf00 nop 80036c0: 58024400 .word 0x58024400 80036c4: 58024800 .word 0x58024800 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80036c8: 4b5f ldr r3, [pc, #380] @ (8003848 ) 80036ca: 6a99 ldr r1, [r3, #40] @ 0x28 80036cc: 4a5f ldr r2, [pc, #380] @ (800384c ) 80036ce: 400a ands r2, r1 80036d0: 6aa1 ldr r1, [r4, #40] @ 0x28 80036d2: 6ae0 ldr r0, [r4, #44] @ 0x2c 80036d4: ea41 1100 orr.w r1, r1, r0, lsl #4 80036d8: 430a orrs r2, r1 80036da: 629a str r2, [r3, #40] @ 0x28 80036dc: 6b22 ldr r2, [r4, #48] @ 0x30 80036de: 3a01 subs r2, #1 80036e0: f3c2 0208 ubfx r2, r2, #0, #9 80036e4: 6b61 ldr r1, [r4, #52] @ 0x34 80036e6: 3901 subs r1, #1 80036e8: 0249 lsls r1, r1, #9 80036ea: b289 uxth r1, r1 80036ec: 430a orrs r2, r1 80036ee: 6ba1 ldr r1, [r4, #56] @ 0x38 80036f0: 3901 subs r1, #1 80036f2: 0409 lsls r1, r1, #16 80036f4: f401 01fe and.w r1, r1, #8323072 @ 0x7f0000 80036f8: 430a orrs r2, r1 80036fa: 6be1 ldr r1, [r4, #60] @ 0x3c 80036fc: 3901 subs r1, #1 80036fe: 0609 lsls r1, r1, #24 8003700: f001 41fe and.w r1, r1, #2130706432 @ 0x7f000000 8003704: 430a orrs r2, r1 8003706: 631a str r2, [r3, #48] @ 0x30 __HAL_RCC_PLLFRACN_DISABLE(); 8003708: 6ada ldr r2, [r3, #44] @ 0x2c 800370a: f022 0201 bic.w r2, r2, #1 800370e: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 8003710: 6b5a ldr r2, [r3, #52] @ 0x34 8003712: f36f 02cf bfc r2, #3, #13 8003716: 6ca1 ldr r1, [r4, #72] @ 0x48 8003718: ea42 02c1 orr.w r2, r2, r1, lsl #3 800371c: 635a str r2, [r3, #52] @ 0x34 __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800371e: 6ada ldr r2, [r3, #44] @ 0x2c 8003720: f022 020c bic.w r2, r2, #12 8003724: 6c21 ldr r1, [r4, #64] @ 0x40 8003726: 430a orrs r2, r1 8003728: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800372a: 6ada ldr r2, [r3, #44] @ 0x2c 800372c: f022 0202 bic.w r2, r2, #2 8003730: 6c61 ldr r1, [r4, #68] @ 0x44 8003732: 430a orrs r2, r1 8003734: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 8003736: 6ada ldr r2, [r3, #44] @ 0x2c 8003738: f442 3280 orr.w r2, r2, #65536 @ 0x10000 800373c: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800373e: 6ada ldr r2, [r3, #44] @ 0x2c 8003740: f442 3200 orr.w r2, r2, #131072 @ 0x20000 8003744: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 8003746: 6ada ldr r2, [r3, #44] @ 0x2c 8003748: f442 2280 orr.w r2, r2, #262144 @ 0x40000 800374c: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLLFRACN_ENABLE(); 800374e: 6ada ldr r2, [r3, #44] @ 0x2c 8003750: f042 0201 orr.w r2, r2, #1 8003754: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLL_ENABLE(); 8003756: 681a ldr r2, [r3, #0] 8003758: f042 7280 orr.w r2, r2, #16777216 @ 0x1000000 800375c: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 800375e: f7fd f9fd bl 8000b5c 8003762: 4604 mov r4, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8003764: 4b38 ldr r3, [pc, #224] @ (8003848 ) 8003766: 681b ldr r3, [r3, #0] 8003768: f013 7f00 tst.w r3, #33554432 @ 0x2000000 800376c: d106 bne.n 800377c if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800376e: f7fd f9f5 bl 8000b5c 8003772: 1b00 subs r0, r0, r4 8003774: 2802 cmp r0, #2 8003776: d9f5 bls.n 8003764 return HAL_TIMEOUT; 8003778: 2003 movs r0, #3 800377a: e056 b.n 800382a __HAL_RCC_PLLFRACN_ENABLE(); } } } } return HAL_OK; 800377c: 2000 movs r0, #0 800377e: e054 b.n 800382a 8003780: 2000 movs r0, #0 8003782: e052 b.n 800382a temp1_pllckcfg = RCC->PLLCKSELR; 8003784: 4930 ldr r1, [pc, #192] @ (8003848 ) 8003786: 6a8a ldr r2, [r1, #40] @ 0x28 temp2_pllckcfg = RCC->PLL1DIVR; 8003788: 6b08 ldr r0, [r1, #48] @ 0x30 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800378a: 2b01 cmp r3, #1 800378c: d04e beq.n 800382c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800378e: f002 0303 and.w r3, r2, #3 8003792: 6aa1 ldr r1, [r4, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8003794: 428b cmp r3, r1 8003796: d14b bne.n 8003830 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8003798: f3c2 1205 ubfx r2, r2, #4, #6 800379c: 6ae3 ldr r3, [r4, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800379e: 429a cmp r2, r3 80037a0: d148 bne.n 8003834 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 80037a2: f3c0 0208 ubfx r2, r0, #0, #9 80037a6: 6b23 ldr r3, [r4, #48] @ 0x30 80037a8: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 80037aa: 429a cmp r2, r3 80037ac: d144 bne.n 8003838 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 80037ae: f3c0 2246 ubfx r2, r0, #9, #7 80037b2: 6b63 ldr r3, [r4, #52] @ 0x34 80037b4: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 80037b6: 429a cmp r2, r3 80037b8: d140 bne.n 800383c ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 80037ba: f3c0 4206 ubfx r2, r0, #16, #7 80037be: 6ba3 ldr r3, [r4, #56] @ 0x38 80037c0: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 80037c2: 429a cmp r2, r3 80037c4: d13c bne.n 8003840 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 80037c6: f3c0 6006 ubfx r0, r0, #24, #7 80037ca: 6be3 ldr r3, [r4, #60] @ 0x3c 80037cc: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 80037ce: 4298 cmp r0, r3 80037d0: d138 bne.n 8003844 temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 80037d2: 4b1d ldr r3, [pc, #116] @ (8003848 ) 80037d4: 6b5b ldr r3, [r3, #52] @ 0x34 80037d6: f3c3 03cc ubfx r3, r3, #3, #13 if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 80037da: 6ca2 ldr r2, [r4, #72] @ 0x48 80037dc: 429a cmp r2, r3 80037de: d101 bne.n 80037e4 return HAL_OK; 80037e0: 2000 movs r0, #0 80037e2: e022 b.n 800382a __HAL_RCC_PLLFRACN_DISABLE(); 80037e4: 4a18 ldr r2, [pc, #96] @ (8003848 ) 80037e6: 6ad3 ldr r3, [r2, #44] @ 0x2c 80037e8: f023 0301 bic.w r3, r3, #1 80037ec: 62d3 str r3, [r2, #44] @ 0x2c tickstart = HAL_GetTick(); 80037ee: f7fd f9b5 bl 8000b5c 80037f2: 4605 mov r5, r0 while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 80037f4: f7fd f9b2 bl 8000b5c 80037f8: 42a8 cmp r0, r5 80037fa: d0fb beq.n 80037f4 __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 80037fc: 4a12 ldr r2, [pc, #72] @ (8003848 ) 80037fe: 6b53 ldr r3, [r2, #52] @ 0x34 8003800: f36f 03cf bfc r3, #3, #13 8003804: 6ca1 ldr r1, [r4, #72] @ 0x48 8003806: ea43 03c1 orr.w r3, r3, r1, lsl #3 800380a: 6353 str r3, [r2, #52] @ 0x34 __HAL_RCC_PLLFRACN_ENABLE(); 800380c: 6ad3 ldr r3, [r2, #44] @ 0x2c 800380e: f043 0301 orr.w r3, r3, #1 8003812: 62d3 str r3, [r2, #44] @ 0x2c return HAL_OK; 8003814: 2000 movs r0, #0 8003816: e008 b.n 800382a return HAL_ERROR; 8003818: 2001 movs r0, #1 } 800381a: 4770 bx lr return HAL_ERROR; 800381c: 2001 movs r0, #1 800381e: e004 b.n 800382a return HAL_ERROR; 8003820: 2001 movs r0, #1 8003822: e002 b.n 800382a return HAL_ERROR; 8003824: 2001 movs r0, #1 8003826: e000 b.n 800382a return HAL_OK; 8003828: 2000 movs r0, #0 } 800382a: bd38 pop {r3, r4, r5, pc} return HAL_ERROR; 800382c: 2001 movs r0, #1 800382e: e7fc b.n 800382a 8003830: 2001 movs r0, #1 8003832: e7fa b.n 800382a 8003834: 2001 movs r0, #1 8003836: e7f8 b.n 800382a 8003838: 2001 movs r0, #1 800383a: e7f6 b.n 800382a 800383c: 2001 movs r0, #1 800383e: e7f4 b.n 800382a 8003840: 2001 movs r0, #1 8003842: e7f2 b.n 800382a 8003844: 2001 movs r0, #1 8003846: e7f0 b.n 800382a 8003848: 58024400 .word 0x58024400 800384c: fffffc0c .word 0xfffffc0c 08003850 : float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8003850: 4b75 ldr r3, [pc, #468] @ (8003a28 ) 8003852: 691b ldr r3, [r3, #16] 8003854: f003 0338 and.w r3, r3, #56 @ 0x38 8003858: 2b10 cmp r3, #16 800385a: f000 80de beq.w 8003a1a 800385e: 2b18 cmp r3, #24 8003860: d00f beq.n 8003882 8003862: 2b00 cmp r3, #0 8003864: f040 80db bne.w 8003a1e { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8003868: 4b6f ldr r3, [pc, #444] @ (8003a28 ) 800386a: 681b ldr r3, [r3, #0] 800386c: f013 0f20 tst.w r3, #32 8003870: f000 80d7 beq.w 8003a22 { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8003874: 4b6c ldr r3, [pc, #432] @ (8003a28 ) 8003876: 681b ldr r3, [r3, #0] 8003878: f3c3 03c1 ubfx r3, r3, #3, #2 800387c: 486b ldr r0, [pc, #428] @ (8003a2c ) 800387e: 40d8 lsrs r0, r3 8003880: 4770 bx lr { 8003882: b410 push {r4} case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8003884: 4b68 ldr r3, [pc, #416] @ (8003a28 ) 8003886: 6a9a ldr r2, [r3, #40] @ 0x28 8003888: f002 0203 and.w r2, r2, #3 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800388c: 6a9c ldr r4, [r3, #40] @ 0x28 800388e: f3c4 1005 ubfx r0, r4, #4, #6 pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 8003892: 6ad9 ldr r1, [r3, #44] @ 0x2c 8003894: f001 0101 and.w r1, r1, #1 fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 8003898: 6b5b ldr r3, [r3, #52] @ 0x34 800389a: f3c3 03cc ubfx r3, r3, #3, #13 800389e: fb01 f303 mul.w r3, r1, r3 80038a2: ee07 3a90 vmov s15, r3 80038a6: eef8 7a67 vcvt.f32.u32 s15, s15 if (pllm != 0U) 80038aa: f414 7f7c tst.w r4, #1008 @ 0x3f0 80038ae: d077 beq.n 80039a0 { switch (pllsource) 80038b0: 2a01 cmp r2, #1 80038b2: d04a beq.n 800394a 80038b4: 2a02 cmp r2, #2 80038b6: d076 beq.n 80039a6 80038b8: 2a00 cmp r2, #0 80038ba: f040 8091 bne.w 80039e0 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80038be: 4b5a ldr r3, [pc, #360] @ (8003a28 ) 80038c0: 681b ldr r3, [r3, #0] 80038c2: f013 0f20 tst.w r3, #32 80038c6: d023 beq.n 8003910 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80038c8: 4957 ldr r1, [pc, #348] @ (8003a28 ) 80038ca: 680a ldr r2, [r1, #0] 80038cc: f3c2 02c1 ubfx r2, r2, #3, #2 80038d0: 4b56 ldr r3, [pc, #344] @ (8003a2c ) 80038d2: 40d3 lsrs r3, r2 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80038d4: ee07 3a10 vmov s14, r3 80038d8: eef8 6a47 vcvt.f32.u32 s13, s14 80038dc: ee07 0a10 vmov s14, r0 80038e0: eeb8 6a47 vcvt.f32.u32 s12, s14 80038e4: ee86 7a86 vdiv.f32 s14, s13, s12 80038e8: 6b0b ldr r3, [r1, #48] @ 0x30 80038ea: f3c3 0308 ubfx r3, r3, #0, #9 80038ee: ee06 3a90 vmov s13, r3 80038f2: eef8 6a66 vcvt.f32.u32 s13, s13 80038f6: ed9f 6a4e vldr s12, [pc, #312] @ 8003a30 80038fa: ee67 7a86 vmul.f32 s15, s15, s12 80038fe: ee76 7aa7 vadd.f32 s15, s13, s15 8003902: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8003906: ee77 7aa6 vadd.f32 s15, s15, s13 800390a: ee27 7a27 vmul.f32 s14, s14, s15 800390e: e038 b.n 8003982 } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8003910: ee07 0a10 vmov s14, r0 8003914: eef8 6a47 vcvt.f32.u32 s13, s14 8003918: ed9f 6a46 vldr s12, [pc, #280] @ 8003a34 800391c: ee86 7a26 vdiv.f32 s14, s12, s13 8003920: 4b41 ldr r3, [pc, #260] @ (8003a28 ) 8003922: 6b1b ldr r3, [r3, #48] @ 0x30 8003924: f3c3 0308 ubfx r3, r3, #0, #9 8003928: ee06 3a90 vmov s13, r3 800392c: eef8 6a66 vcvt.f32.u32 s13, s13 8003930: ed9f 6a3f vldr s12, [pc, #252] @ 8003a30 8003934: ee67 7a86 vmul.f32 s15, s15, s12 8003938: ee76 7aa7 vadd.f32 s15, s13, s15 800393c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8003940: ee77 7aa6 vadd.f32 s15, s15, s13 8003944: ee27 7a27 vmul.f32 s14, s14, s15 8003948: e01b b.n 8003982 } break; case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800394a: ee07 0a10 vmov s14, r0 800394e: eef8 6a47 vcvt.f32.u32 s13, s14 8003952: ed9f 6a39 vldr s12, [pc, #228] @ 8003a38 8003956: ee86 7a26 vdiv.f32 s14, s12, s13 800395a: 4b33 ldr r3, [pc, #204] @ (8003a28 ) 800395c: 6b1b ldr r3, [r3, #48] @ 0x30 800395e: f3c3 0308 ubfx r3, r3, #0, #9 8003962: ee06 3a90 vmov s13, r3 8003966: eef8 6a66 vcvt.f32.u32 s13, s13 800396a: ed9f 6a31 vldr s12, [pc, #196] @ 8003a30 800396e: ee67 7a86 vmul.f32 s15, s15, s12 8003972: ee76 7aa7 vadd.f32 s15, s13, s15 8003976: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800397a: ee77 7aa6 vadd.f32 s15, s15, s13 800397e: ee27 7a27 vmul.f32 s14, s14, s15 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 8003982: 4b29 ldr r3, [pc, #164] @ (8003a28 ) 8003984: 6b1b ldr r3, [r3, #48] @ 0x30 8003986: f3c3 2346 ubfx r3, r3, #9, #7 800398a: 3301 adds r3, #1 sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800398c: ee07 3a90 vmov s15, r3 8003990: eef8 7a67 vcvt.f32.u32 s15, s15 8003994: eec7 6a27 vdiv.f32 s13, s14, s15 8003998: eefc 7ae6 vcvt.u32.f32 s15, s13 800399c: ee17 0a90 vmov r0, s15 sysclockfreq = CSI_VALUE; break; } return sysclockfreq; } 80039a0: f85d 4b04 ldr.w r4, [sp], #4 80039a4: 4770 bx lr pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80039a6: ee07 0a10 vmov s14, r0 80039aa: eef8 6a47 vcvt.f32.u32 s13, s14 80039ae: ed9f 6a23 vldr s12, [pc, #140] @ 8003a3c 80039b2: ee86 7a26 vdiv.f32 s14, s12, s13 80039b6: 4b1c ldr r3, [pc, #112] @ (8003a28 ) 80039b8: 6b1b ldr r3, [r3, #48] @ 0x30 80039ba: f3c3 0308 ubfx r3, r3, #0, #9 80039be: ee06 3a90 vmov s13, r3 80039c2: eef8 6a66 vcvt.f32.u32 s13, s13 80039c6: ed9f 6a1a vldr s12, [pc, #104] @ 8003a30 80039ca: ee67 7a86 vmul.f32 s15, s15, s12 80039ce: ee76 7aa7 vadd.f32 s15, s13, s15 80039d2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80039d6: ee77 7aa6 vadd.f32 s15, s15, s13 80039da: ee27 7a27 vmul.f32 s14, s14, s15 break; 80039de: e7d0 b.n 8003982 pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80039e0: ee07 0a10 vmov s14, r0 80039e4: eef8 6a47 vcvt.f32.u32 s13, s14 80039e8: ed9f 6a13 vldr s12, [pc, #76] @ 8003a38 80039ec: ee86 7a26 vdiv.f32 s14, s12, s13 80039f0: 4b0d ldr r3, [pc, #52] @ (8003a28 ) 80039f2: 6b1b ldr r3, [r3, #48] @ 0x30 80039f4: f3c3 0308 ubfx r3, r3, #0, #9 80039f8: ee06 3a90 vmov s13, r3 80039fc: eef8 6a66 vcvt.f32.u32 s13, s13 8003a00: ed9f 6a0b vldr s12, [pc, #44] @ 8003a30 8003a04: ee67 7a86 vmul.f32 s15, s15, s12 8003a08: ee76 7aa7 vadd.f32 s15, s13, s15 8003a0c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8003a10: ee77 7aa6 vadd.f32 s15, s15, s13 8003a14: ee27 7a27 vmul.f32 s14, s14, s15 break; 8003a18: e7b3 b.n 8003982 sysclockfreq = HSE_VALUE; 8003a1a: 4809 ldr r0, [pc, #36] @ (8003a40 ) 8003a1c: 4770 bx lr switch (RCC->CFGR & RCC_CFGR_SWS) 8003a1e: 4809 ldr r0, [pc, #36] @ (8003a44 ) 8003a20: 4770 bx lr sysclockfreq = (uint32_t) HSI_VALUE; 8003a22: 4802 ldr r0, [pc, #8] @ (8003a2c ) } 8003a24: 4770 bx lr 8003a26: bf00 nop 8003a28: 58024400 .word 0x58024400 8003a2c: 03d09000 .word 0x03d09000 8003a30: 39000000 .word 0x39000000 8003a34: 4c742400 .word 0x4c742400 8003a38: 4a742400 .word 0x4a742400 8003a3c: 4bb71b00 .word 0x4bb71b00 8003a40: 016e3600 .word 0x016e3600 8003a44: 003d0900 .word 0x003d0900 08003a48 : if (RCC_ClkInitStruct == NULL) 8003a48: 2800 cmp r0, #0 8003a4a: f000 8132 beq.w 8003cb2 { 8003a4e: b570 push {r4, r5, r6, lr} 8003a50: 460d mov r5, r1 8003a52: 4604 mov r4, r0 if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003a54: 4b9b ldr r3, [pc, #620] @ (8003cc4 ) 8003a56: 681b ldr r3, [r3, #0] 8003a58: f003 030f and.w r3, r3, #15 8003a5c: 428b cmp r3, r1 8003a5e: d20b bcs.n 8003a78 __HAL_FLASH_SET_LATENCY(FLatency); 8003a60: 4a98 ldr r2, [pc, #608] @ (8003cc4 ) 8003a62: 6813 ldr r3, [r2, #0] 8003a64: f023 030f bic.w r3, r3, #15 8003a68: 430b orrs r3, r1 8003a6a: 6013 str r3, [r2, #0] if (__HAL_FLASH_GET_LATENCY() != FLatency) 8003a6c: 6813 ldr r3, [r2, #0] 8003a6e: f003 030f and.w r3, r3, #15 8003a72: 428b cmp r3, r1 8003a74: f040 811f bne.w 8003cb6 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8003a78: 6823 ldr r3, [r4, #0] 8003a7a: f013 0f04 tst.w r3, #4 8003a7e: d00c beq.n 8003a9a if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) 8003a80: 6922 ldr r2, [r4, #16] 8003a82: 4b91 ldr r3, [pc, #580] @ (8003cc8 ) 8003a84: 699b ldr r3, [r3, #24] 8003a86: f003 0370 and.w r3, r3, #112 @ 0x70 8003a8a: 429a cmp r2, r3 8003a8c: d905 bls.n 8003a9a MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); 8003a8e: 498e ldr r1, [pc, #568] @ (8003cc8 ) 8003a90: 698b ldr r3, [r1, #24] 8003a92: f023 0370 bic.w r3, r3, #112 @ 0x70 8003a96: 431a orrs r2, r3 8003a98: 618a str r2, [r1, #24] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003a9a: 6823 ldr r3, [r4, #0] 8003a9c: f013 0f08 tst.w r3, #8 8003aa0: d00c beq.n 8003abc if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) 8003aa2: 6962 ldr r2, [r4, #20] 8003aa4: 4b88 ldr r3, [pc, #544] @ (8003cc8 ) 8003aa6: 69db ldr r3, [r3, #28] 8003aa8: f003 0370 and.w r3, r3, #112 @ 0x70 8003aac: 429a cmp r2, r3 8003aae: d905 bls.n 8003abc MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8003ab0: 4985 ldr r1, [pc, #532] @ (8003cc8 ) 8003ab2: 69cb ldr r3, [r1, #28] 8003ab4: f023 0370 bic.w r3, r3, #112 @ 0x70 8003ab8: 431a orrs r2, r3 8003aba: 61ca str r2, [r1, #28] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003abc: 6823 ldr r3, [r4, #0] 8003abe: f013 0f10 tst.w r3, #16 8003ac2: d00c beq.n 8003ade if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) 8003ac4: 69a2 ldr r2, [r4, #24] 8003ac6: 4b80 ldr r3, [pc, #512] @ (8003cc8 ) 8003ac8: 69db ldr r3, [r3, #28] 8003aca: f403 63e0 and.w r3, r3, #1792 @ 0x700 8003ace: 429a cmp r2, r3 8003ad0: d905 bls.n 8003ade MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8003ad2: 497d ldr r1, [pc, #500] @ (8003cc8 ) 8003ad4: 69cb ldr r3, [r1, #28] 8003ad6: f423 63e0 bic.w r3, r3, #1792 @ 0x700 8003ada: 431a orrs r2, r3 8003adc: 61ca str r2, [r1, #28] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8003ade: 6823 ldr r3, [r4, #0] 8003ae0: f013 0f20 tst.w r3, #32 8003ae4: d00c beq.n 8003b00 if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) 8003ae6: 69e2 ldr r2, [r4, #28] 8003ae8: 4b77 ldr r3, [pc, #476] @ (8003cc8 ) 8003aea: 6a1b ldr r3, [r3, #32] 8003aec: f003 0370 and.w r3, r3, #112 @ 0x70 8003af0: 429a cmp r2, r3 8003af2: d905 bls.n 8003b00 MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 8003af4: 4974 ldr r1, [pc, #464] @ (8003cc8 ) 8003af6: 6a0b ldr r3, [r1, #32] 8003af8: f023 0370 bic.w r3, r3, #112 @ 0x70 8003afc: 431a orrs r2, r3 8003afe: 620a str r2, [r1, #32] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003b00: 6823 ldr r3, [r4, #0] 8003b02: f013 0f02 tst.w r3, #2 8003b06: d00c beq.n 8003b22 if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) 8003b08: 68e2 ldr r2, [r4, #12] 8003b0a: 4b6f ldr r3, [pc, #444] @ (8003cc8 ) 8003b0c: 699b ldr r3, [r3, #24] 8003b0e: f003 030f and.w r3, r3, #15 8003b12: 429a cmp r2, r3 8003b14: d905 bls.n 8003b22 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003b16: 496c ldr r1, [pc, #432] @ (8003cc8 ) 8003b18: 698b ldr r3, [r1, #24] 8003b1a: f023 030f bic.w r3, r3, #15 8003b1e: 431a orrs r2, r3 8003b20: 618a str r2, [r1, #24] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003b22: 6823 ldr r3, [r4, #0] 8003b24: f013 0f01 tst.w r3, #1 8003b28: d041 beq.n 8003bae MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); 8003b2a: 4a67 ldr r2, [pc, #412] @ (8003cc8 ) 8003b2c: 6993 ldr r3, [r2, #24] 8003b2e: f423 6370 bic.w r3, r3, #3840 @ 0xf00 8003b32: 68a1 ldr r1, [r4, #8] 8003b34: 430b orrs r3, r1 8003b36: 6193 str r3, [r2, #24] if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003b38: 6863 ldr r3, [r4, #4] 8003b3a: 2b02 cmp r3, #2 8003b3c: d00a beq.n 8003b54 else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8003b3e: 2b03 cmp r3, #3 8003b40: d027 beq.n 8003b92 else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 8003b42: 2b01 cmp r3, #1 8003b44: d02c beq.n 8003ba0 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8003b46: 4a60 ldr r2, [pc, #384] @ (8003cc8 ) 8003b48: 6812 ldr r2, [r2, #0] 8003b4a: f012 0f04 tst.w r2, #4 8003b4e: d106 bne.n 8003b5e return HAL_ERROR; 8003b50: 2001 movs r0, #1 8003b52: e0ad b.n 8003cb0 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8003b54: 6812 ldr r2, [r2, #0] 8003b56: f412 3f00 tst.w r2, #131072 @ 0x20000 8003b5a: f000 80ae beq.w 8003cba MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8003b5e: 495a ldr r1, [pc, #360] @ (8003cc8 ) 8003b60: 690a ldr r2, [r1, #16] 8003b62: f022 0207 bic.w r2, r2, #7 8003b66: 4313 orrs r3, r2 8003b68: 610b str r3, [r1, #16] tickstart = HAL_GetTick(); 8003b6a: f7fc fff7 bl 8000b5c 8003b6e: 4606 mov r6, r0 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003b70: 4b55 ldr r3, [pc, #340] @ (8003cc8 ) 8003b72: 691b ldr r3, [r3, #16] 8003b74: f003 0338 and.w r3, r3, #56 @ 0x38 8003b78: 6862 ldr r2, [r4, #4] 8003b7a: ebb3 0fc2 cmp.w r3, r2, lsl #3 8003b7e: d016 beq.n 8003bae if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003b80: f7fc ffec bl 8000b5c 8003b84: 1b80 subs r0, r0, r6 8003b86: f241 3388 movw r3, #5000 @ 0x1388 8003b8a: 4298 cmp r0, r3 8003b8c: d9f0 bls.n 8003b70 return HAL_TIMEOUT; 8003b8e: 2003 movs r0, #3 8003b90: e08e b.n 8003cb0 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8003b92: 4a4d ldr r2, [pc, #308] @ (8003cc8 ) 8003b94: 6812 ldr r2, [r2, #0] 8003b96: f012 7f00 tst.w r2, #33554432 @ 0x2000000 8003b9a: d1e0 bne.n 8003b5e return HAL_ERROR; 8003b9c: 2001 movs r0, #1 8003b9e: e087 b.n 8003cb0 if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8003ba0: 4a49 ldr r2, [pc, #292] @ (8003cc8 ) 8003ba2: 6812 ldr r2, [r2, #0] 8003ba4: f412 7f80 tst.w r2, #256 @ 0x100 8003ba8: d1d9 bne.n 8003b5e return HAL_ERROR; 8003baa: 2001 movs r0, #1 8003bac: e080 b.n 8003cb0 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003bae: 6823 ldr r3, [r4, #0] 8003bb0: f013 0f02 tst.w r3, #2 8003bb4: d00c beq.n 8003bd0 if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) 8003bb6: 68e2 ldr r2, [r4, #12] 8003bb8: 4b43 ldr r3, [pc, #268] @ (8003cc8 ) 8003bba: 699b ldr r3, [r3, #24] 8003bbc: f003 030f and.w r3, r3, #15 8003bc0: 429a cmp r2, r3 8003bc2: d205 bcs.n 8003bd0 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003bc4: 4940 ldr r1, [pc, #256] @ (8003cc8 ) 8003bc6: 698b ldr r3, [r1, #24] 8003bc8: f023 030f bic.w r3, r3, #15 8003bcc: 431a orrs r2, r3 8003bce: 618a str r2, [r1, #24] if (FLatency < __HAL_FLASH_GET_LATENCY()) 8003bd0: 4b3c ldr r3, [pc, #240] @ (8003cc4 ) 8003bd2: 681b ldr r3, [r3, #0] 8003bd4: f003 030f and.w r3, r3, #15 8003bd8: 42ab cmp r3, r5 8003bda: d90a bls.n 8003bf2 __HAL_FLASH_SET_LATENCY(FLatency); 8003bdc: 4a39 ldr r2, [pc, #228] @ (8003cc4 ) 8003bde: 6813 ldr r3, [r2, #0] 8003be0: f023 030f bic.w r3, r3, #15 8003be4: 432b orrs r3, r5 8003be6: 6013 str r3, [r2, #0] if (__HAL_FLASH_GET_LATENCY() != FLatency) 8003be8: 6813 ldr r3, [r2, #0] 8003bea: f003 030f and.w r3, r3, #15 8003bee: 42ab cmp r3, r5 8003bf0: d165 bne.n 8003cbe if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8003bf2: 6823 ldr r3, [r4, #0] 8003bf4: f013 0f04 tst.w r3, #4 8003bf8: d00c beq.n 8003c14 if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) 8003bfa: 6922 ldr r2, [r4, #16] 8003bfc: 4b32 ldr r3, [pc, #200] @ (8003cc8 ) 8003bfe: 699b ldr r3, [r3, #24] 8003c00: f003 0370 and.w r3, r3, #112 @ 0x70 8003c04: 429a cmp r2, r3 8003c06: d205 bcs.n 8003c14 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); 8003c08: 492f ldr r1, [pc, #188] @ (8003cc8 ) 8003c0a: 698b ldr r3, [r1, #24] 8003c0c: f023 0370 bic.w r3, r3, #112 @ 0x70 8003c10: 431a orrs r2, r3 8003c12: 618a str r2, [r1, #24] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003c14: 6823 ldr r3, [r4, #0] 8003c16: f013 0f08 tst.w r3, #8 8003c1a: d00c beq.n 8003c36 if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) 8003c1c: 6962 ldr r2, [r4, #20] 8003c1e: 4b2a ldr r3, [pc, #168] @ (8003cc8 ) 8003c20: 69db ldr r3, [r3, #28] 8003c22: f003 0370 and.w r3, r3, #112 @ 0x70 8003c26: 429a cmp r2, r3 8003c28: d205 bcs.n 8003c36 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8003c2a: 4927 ldr r1, [pc, #156] @ (8003cc8 ) 8003c2c: 69cb ldr r3, [r1, #28] 8003c2e: f023 0370 bic.w r3, r3, #112 @ 0x70 8003c32: 431a orrs r2, r3 8003c34: 61ca str r2, [r1, #28] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003c36: 6823 ldr r3, [r4, #0] 8003c38: f013 0f10 tst.w r3, #16 8003c3c: d00c beq.n 8003c58 if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) 8003c3e: 69a2 ldr r2, [r4, #24] 8003c40: 4b21 ldr r3, [pc, #132] @ (8003cc8 ) 8003c42: 69db ldr r3, [r3, #28] 8003c44: f403 63e0 and.w r3, r3, #1792 @ 0x700 8003c48: 429a cmp r2, r3 8003c4a: d205 bcs.n 8003c58 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8003c4c: 491e ldr r1, [pc, #120] @ (8003cc8 ) 8003c4e: 69cb ldr r3, [r1, #28] 8003c50: f423 63e0 bic.w r3, r3, #1792 @ 0x700 8003c54: 431a orrs r2, r3 8003c56: 61ca str r2, [r1, #28] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8003c58: 6823 ldr r3, [r4, #0] 8003c5a: f013 0f20 tst.w r3, #32 8003c5e: d00c beq.n 8003c7a if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) 8003c60: 69e2 ldr r2, [r4, #28] 8003c62: 4b19 ldr r3, [pc, #100] @ (8003cc8 ) 8003c64: 6a1b ldr r3, [r3, #32] 8003c66: f003 0370 and.w r3, r3, #112 @ 0x70 8003c6a: 429a cmp r2, r3 8003c6c: d205 bcs.n 8003c7a MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 8003c6e: 4916 ldr r1, [pc, #88] @ (8003cc8 ) 8003c70: 6a0b ldr r3, [r1, #32] 8003c72: f023 0370 bic.w r3, r3, #112 @ 0x70 8003c76: 431a orrs r2, r3 8003c78: 620a str r2, [r1, #32] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); 8003c7a: f7ff fde9 bl 8003850 8003c7e: 4912 ldr r1, [pc, #72] @ (8003cc8 ) 8003c80: 698b ldr r3, [r1, #24] 8003c82: f3c3 2303 ubfx r3, r3, #8, #4 8003c86: 4a11 ldr r2, [pc, #68] @ (8003ccc ) 8003c88: 5cd3 ldrb r3, [r2, r3] 8003c8a: f003 031f and.w r3, r3, #31 8003c8e: 40d8 lsrs r0, r3 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 8003c90: 698b ldr r3, [r1, #24] 8003c92: f003 030f and.w r3, r3, #15 8003c96: 5cd3 ldrb r3, [r2, r3] 8003c98: f003 031f and.w r3, r3, #31 8003c9c: fa20 f303 lsr.w r3, r0, r3 8003ca0: 4a0b ldr r2, [pc, #44] @ (8003cd0 ) 8003ca2: 6013 str r3, [r2, #0] SystemCoreClock = common_system_clock; 8003ca4: 4b0b ldr r3, [pc, #44] @ (8003cd4 ) 8003ca6: 6018 str r0, [r3, #0] halstatus = HAL_InitTick(uwTickPrio); 8003ca8: 4b0b ldr r3, [pc, #44] @ (8003cd8 ) 8003caa: 6818 ldr r0, [r3, #0] 8003cac: f7fc fef4 bl 8000a98 } 8003cb0: bd70 pop {r4, r5, r6, pc} return HAL_ERROR; 8003cb2: 2001 movs r0, #1 } 8003cb4: 4770 bx lr return HAL_ERROR; 8003cb6: 2001 movs r0, #1 8003cb8: e7fa b.n 8003cb0 return HAL_ERROR; 8003cba: 2001 movs r0, #1 8003cbc: e7f8 b.n 8003cb0 return HAL_ERROR; 8003cbe: 2001 movs r0, #1 8003cc0: e7f6 b.n 8003cb0 8003cc2: bf00 nop 8003cc4: 52002000 .word 0x52002000 8003cc8: 58024400 .word 0x58024400 8003ccc: 080063b8 .word 0x080063b8 8003cd0: 20000008 .word 0x20000008 8003cd4: 2000000c .word 0x2000000c 8003cd8: 20000004 .word 0x20000004 08003cdc : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003cdc: b508 push {r3, lr} uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); 8003cde: f7ff fdb7 bl 8003850 8003ce2: 4a0b ldr r2, [pc, #44] @ (8003d10 ) 8003ce4: 6993 ldr r3, [r2, #24] 8003ce6: f3c3 2303 ubfx r3, r3, #8, #4 8003cea: 490a ldr r1, [pc, #40] @ (8003d14 ) 8003cec: 5ccb ldrb r3, [r1, r3] 8003cee: f003 031f and.w r3, r3, #31 8003cf2: fa20 f303 lsr.w r3, r0, r3 #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); 8003cf6: 6992 ldr r2, [r2, #24] 8003cf8: f002 020f and.w r2, r2, #15 8003cfc: 5c88 ldrb r0, [r1, r2] 8003cfe: f000 001f and.w r0, r0, #31 8003d02: fa23 f000 lsr.w r0, r3, r0 8003d06: 4a04 ldr r2, [pc, #16] @ (8003d18 ) 8003d08: 6010 str r0, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8003d0a: 4a04 ldr r2, [pc, #16] @ (8003d1c ) 8003d0c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; } 8003d0e: bd08 pop {r3, pc} 8003d10: 58024400 .word 0x58024400 8003d14: 080063b8 .word 0x080063b8 8003d18: 20000008 .word 0x20000008 8003d1c: 2000000c .word 0x2000000c 08003d20 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003d20: b508 push {r3, lr} #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); 8003d22: f7ff ffdb bl 8003cdc 8003d26: 4b05 ldr r3, [pc, #20] @ (8003d3c ) 8003d28: 69db ldr r3, [r3, #28] 8003d2a: f3c3 1302 ubfx r3, r3, #4, #3 8003d2e: 4a04 ldr r2, [pc, #16] @ (8003d40 ) 8003d30: 5cd3 ldrb r3, [r2, r3] 8003d32: f003 031f and.w r3, r3, #31 #endif } 8003d36: 40d8 lsrs r0, r3 8003d38: bd08 pop {r3, pc} 8003d3a: bf00 nop 8003d3c: 58024400 .word 0x58024400 8003d40: 080063b8 .word 0x080063b8 08003d44 : assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8003d44: 4b40 ldr r3, [pc, #256] @ (8003e48 ) 8003d46: 6a9b ldr r3, [r3, #40] @ 0x28 8003d48: f003 0303 and.w r3, r3, #3 8003d4c: 2b03 cmp r3, #3 8003d4e: d079 beq.n 8003e44 { 8003d50: b570 push {r4, r5, r6, lr} 8003d52: 4605 mov r5, r0 8003d54: 460e mov r6, r1 else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8003d56: 4a3c ldr r2, [pc, #240] @ (8003e48 ) 8003d58: 6813 ldr r3, [r2, #0] 8003d5a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8003d5e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003d60: f7fc fefc bl 8000b5c 8003d64: 4604 mov r4, r0 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 8003d66: 4b38 ldr r3, [pc, #224] @ (8003e48 ) 8003d68: 681b ldr r3, [r3, #0] 8003d6a: f013 6f00 tst.w r3, #134217728 @ 0x8000000 8003d6e: d006 beq.n 8003d7e { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8003d70: f7fc fef4 bl 8000b5c 8003d74: 1b03 subs r3, r0, r4 8003d76: 2b02 cmp r3, #2 8003d78: d9f5 bls.n 8003d66 { return HAL_TIMEOUT; 8003d7a: 2003 movs r0, #3 } return status; } 8003d7c: bd70 pop {r4, r5, r6, pc} __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 8003d7e: 4b32 ldr r3, [pc, #200] @ (8003e48 ) 8003d80: 6a9a ldr r2, [r3, #40] @ 0x28 8003d82: f422 327c bic.w r2, r2, #258048 @ 0x3f000 8003d86: 6829 ldr r1, [r5, #0] 8003d88: ea42 3201 orr.w r2, r2, r1, lsl #12 8003d8c: 629a str r2, [r3, #40] @ 0x28 8003d8e: 686a ldr r2, [r5, #4] 8003d90: 3a01 subs r2, #1 8003d92: f3c2 0208 ubfx r2, r2, #0, #9 8003d96: 68a9 ldr r1, [r5, #8] 8003d98: 3901 subs r1, #1 8003d9a: 0249 lsls r1, r1, #9 8003d9c: b289 uxth r1, r1 8003d9e: 430a orrs r2, r1 8003da0: 68e9 ldr r1, [r5, #12] 8003da2: 3901 subs r1, #1 8003da4: 0409 lsls r1, r1, #16 8003da6: f401 01fe and.w r1, r1, #8323072 @ 0x7f0000 8003daa: 430a orrs r2, r1 8003dac: 6929 ldr r1, [r5, #16] 8003dae: 3901 subs r1, #1 8003db0: 0609 lsls r1, r1, #24 8003db2: f001 41fe and.w r1, r1, #2130706432 @ 0x7f000000 8003db6: 430a orrs r2, r1 8003db8: 639a str r2, [r3, #56] @ 0x38 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 8003dba: 6ada ldr r2, [r3, #44] @ 0x2c 8003dbc: f022 02c0 bic.w r2, r2, #192 @ 0xc0 8003dc0: 6969 ldr r1, [r5, #20] 8003dc2: 430a orrs r2, r1 8003dc4: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8003dc6: 6ada ldr r2, [r3, #44] @ 0x2c 8003dc8: f022 0220 bic.w r2, r2, #32 8003dcc: 69a9 ldr r1, [r5, #24] 8003dce: 430a orrs r2, r1 8003dd0: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLL2FRACN_DISABLE(); 8003dd2: 6ada ldr r2, [r3, #44] @ 0x2c 8003dd4: f022 0210 bic.w r2, r2, #16 8003dd8: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 8003dda: 6bda ldr r2, [r3, #60] @ 0x3c 8003ddc: f36f 02cf bfc r2, #3, #13 8003de0: 69e9 ldr r1, [r5, #28] 8003de2: ea42 02c1 orr.w r2, r2, r1, lsl #3 8003de6: 63da str r2, [r3, #60] @ 0x3c __HAL_RCC_PLL2FRACN_ENABLE(); 8003de8: 6ada ldr r2, [r3, #44] @ 0x2c 8003dea: f042 0210 orr.w r2, r2, #16 8003dee: 62da str r2, [r3, #44] @ 0x2c if (Divider == DIVIDER_P_UPDATE) 8003df0: b9c6 cbnz r6, 8003e24 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 8003df2: 461a mov r2, r3 8003df4: 6adb ldr r3, [r3, #44] @ 0x2c 8003df6: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8003dfa: 62d3 str r3, [r2, #44] @ 0x2c __HAL_RCC_PLL2_ENABLE(); 8003dfc: 4a12 ldr r2, [pc, #72] @ (8003e48 ) 8003dfe: 6813 ldr r3, [r2, #0] 8003e00: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8003e04: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 8003e06: f7fc fea9 bl 8000b5c 8003e0a: 4604 mov r4, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 8003e0c: 4b0e ldr r3, [pc, #56] @ (8003e48 ) 8003e0e: 681b ldr r3, [r3, #0] 8003e10: f013 6f00 tst.w r3, #134217728 @ 0x8000000 8003e14: d114 bne.n 8003e40 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8003e16: f7fc fea1 bl 8000b5c 8003e1a: 1b00 subs r0, r0, r4 8003e1c: 2802 cmp r0, #2 8003e1e: d9f5 bls.n 8003e0c return HAL_TIMEOUT; 8003e20: 2003 movs r0, #3 8003e22: e7ab b.n 8003d7c else if (Divider == DIVIDER_Q_UPDATE) 8003e24: 2e01 cmp r6, #1 8003e26: d005 beq.n 8003e34 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 8003e28: 4a07 ldr r2, [pc, #28] @ (8003e48 ) 8003e2a: 6ad3 ldr r3, [r2, #44] @ 0x2c 8003e2c: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8003e30: 62d3 str r3, [r2, #44] @ 0x2c 8003e32: e7e3 b.n 8003dfc __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 8003e34: 4a04 ldr r2, [pc, #16] @ (8003e48 ) 8003e36: 6ad3 ldr r3, [r2, #44] @ 0x2c 8003e38: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8003e3c: 62d3 str r3, [r2, #44] @ 0x2c 8003e3e: e7dd b.n 8003dfc return status; 8003e40: 2000 movs r0, #0 8003e42: e79b b.n 8003d7c return HAL_ERROR; 8003e44: 2001 movs r0, #1 } 8003e46: 4770 bx lr 8003e48: 58024400 .word 0x58024400 08003e4c : assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8003e4c: 4b40 ldr r3, [pc, #256] @ (8003f50 ) 8003e4e: 6a9b ldr r3, [r3, #40] @ 0x28 8003e50: f003 0303 and.w r3, r3, #3 8003e54: 2b03 cmp r3, #3 8003e56: d079 beq.n 8003f4c { 8003e58: b570 push {r4, r5, r6, lr} 8003e5a: 4605 mov r5, r0 8003e5c: 460e mov r6, r1 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 8003e5e: 4a3c ldr r2, [pc, #240] @ (8003f50 ) 8003e60: 6813 ldr r3, [r2, #0] 8003e62: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8003e66: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003e68: f7fc fe78 bl 8000b5c 8003e6c: 4604 mov r4, r0 /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8003e6e: 4b38 ldr r3, [pc, #224] @ (8003f50 ) 8003e70: 681b ldr r3, [r3, #0] 8003e72: f013 5f00 tst.w r3, #536870912 @ 0x20000000 8003e76: d006 beq.n 8003e86 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 8003e78: f7fc fe70 bl 8000b5c 8003e7c: 1b03 subs r3, r0, r4 8003e7e: 2b02 cmp r3, #2 8003e80: d9f5 bls.n 8003e6e { return HAL_TIMEOUT; 8003e82: 2003 movs r0, #3 } return status; } 8003e84: bd70 pop {r4, r5, r6, pc} __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 8003e86: 4b32 ldr r3, [pc, #200] @ (8003f50 ) 8003e88: 6a9a ldr r2, [r3, #40] @ 0x28 8003e8a: f022 727c bic.w r2, r2, #66060288 @ 0x3f00000 8003e8e: 6829 ldr r1, [r5, #0] 8003e90: ea42 5201 orr.w r2, r2, r1, lsl #20 8003e94: 629a str r2, [r3, #40] @ 0x28 8003e96: 686a ldr r2, [r5, #4] 8003e98: 3a01 subs r2, #1 8003e9a: f3c2 0208 ubfx r2, r2, #0, #9 8003e9e: 68a9 ldr r1, [r5, #8] 8003ea0: 3901 subs r1, #1 8003ea2: 0249 lsls r1, r1, #9 8003ea4: b289 uxth r1, r1 8003ea6: 430a orrs r2, r1 8003ea8: 68e9 ldr r1, [r5, #12] 8003eaa: 3901 subs r1, #1 8003eac: 0409 lsls r1, r1, #16 8003eae: f401 01fe and.w r1, r1, #8323072 @ 0x7f0000 8003eb2: 430a orrs r2, r1 8003eb4: 6929 ldr r1, [r5, #16] 8003eb6: 3901 subs r1, #1 8003eb8: 0609 lsls r1, r1, #24 8003eba: f001 41fe and.w r1, r1, #2130706432 @ 0x7f000000 8003ebe: 430a orrs r2, r1 8003ec0: 641a str r2, [r3, #64] @ 0x40 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 8003ec2: 6ada ldr r2, [r3, #44] @ 0x2c 8003ec4: f422 6240 bic.w r2, r2, #3072 @ 0xc00 8003ec8: 6969 ldr r1, [r5, #20] 8003eca: 430a orrs r2, r1 8003ecc: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 8003ece: 6ada ldr r2, [r3, #44] @ 0x2c 8003ed0: f422 7200 bic.w r2, r2, #512 @ 0x200 8003ed4: 69a9 ldr r1, [r5, #24] 8003ed6: 430a orrs r2, r1 8003ed8: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLL3FRACN_DISABLE(); 8003eda: 6ada ldr r2, [r3, #44] @ 0x2c 8003edc: f422 7280 bic.w r2, r2, #256 @ 0x100 8003ee0: 62da str r2, [r3, #44] @ 0x2c __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 8003ee2: 6c5a ldr r2, [r3, #68] @ 0x44 8003ee4: f36f 02cf bfc r2, #3, #13 8003ee8: 69e9 ldr r1, [r5, #28] 8003eea: ea42 02c1 orr.w r2, r2, r1, lsl #3 8003eee: 645a str r2, [r3, #68] @ 0x44 __HAL_RCC_PLL3FRACN_ENABLE(); 8003ef0: 6ada ldr r2, [r3, #44] @ 0x2c 8003ef2: f442 7280 orr.w r2, r2, #256 @ 0x100 8003ef6: 62da str r2, [r3, #44] @ 0x2c if (Divider == DIVIDER_P_UPDATE) 8003ef8: b9c6 cbnz r6, 8003f2c __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 8003efa: 461a mov r2, r3 8003efc: 6adb ldr r3, [r3, #44] @ 0x2c 8003efe: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8003f02: 62d3 str r3, [r2, #44] @ 0x2c __HAL_RCC_PLL3_ENABLE(); 8003f04: 4a12 ldr r2, [pc, #72] @ (8003f50 ) 8003f06: 6813 ldr r3, [r2, #0] 8003f08: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003f0c: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 8003f0e: f7fc fe25 bl 8000b5c 8003f12: 4604 mov r4, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8003f14: 4b0e ldr r3, [pc, #56] @ (8003f50 ) 8003f16: 681b ldr r3, [r3, #0] 8003f18: f013 5f00 tst.w r3, #536870912 @ 0x20000000 8003f1c: d114 bne.n 8003f48 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 8003f1e: f7fc fe1d bl 8000b5c 8003f22: 1b00 subs r0, r0, r4 8003f24: 2802 cmp r0, #2 8003f26: d9f5 bls.n 8003f14 return HAL_TIMEOUT; 8003f28: 2003 movs r0, #3 8003f2a: e7ab b.n 8003e84 else if (Divider == DIVIDER_Q_UPDATE) 8003f2c: 2e01 cmp r6, #1 8003f2e: d005 beq.n 8003f3c __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 8003f30: 4a07 ldr r2, [pc, #28] @ (8003f50 ) 8003f32: 6ad3 ldr r3, [r2, #44] @ 0x2c 8003f34: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8003f38: 62d3 str r3, [r2, #44] @ 0x2c 8003f3a: e7e3 b.n 8003f04 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 8003f3c: 4a04 ldr r2, [pc, #16] @ (8003f50 ) 8003f3e: 6ad3 ldr r3, [r2, #44] @ 0x2c 8003f40: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8003f44: 62d3 str r3, [r2, #44] @ 0x2c 8003f46: e7dd b.n 8003f04 return status; 8003f48: 2000 movs r0, #0 8003f4a: e79b b.n 8003e84 return HAL_ERROR; 8003f4c: 2001 movs r0, #1 } 8003f4e: 4770 bx lr 8003f50: 58024400 .word 0x58024400 08003f54 : { 8003f54: b5f8 push {r3, r4, r5, r6, r7, lr} 8003f56: 4604 mov r4, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8003f58: 6803 ldr r3, [r0, #0] 8003f5a: f013 6f00 tst.w r3, #134217728 @ 0x8000000 8003f5e: d030 beq.n 8003fc2 switch (PeriphClkInit->SpdifrxClockSelection) 8003f60: 6ec3 ldr r3, [r0, #108] @ 0x6c 8003f62: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8003f66: d026 beq.n 8003fb6 8003f68: d80e bhi.n 8003f88 8003f6a: b1ab cbz r3, 8003f98 8003f6c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003f70: d107 bne.n 8003f82 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8003f72: 2102 movs r1, #2 8003f74: 3008 adds r0, #8 8003f76: f7ff fee5 bl 8003d44 8003f7a: 4605 mov r5, r0 if (ret == HAL_OK) 8003f7c: b195 cbz r5, 8003fa4 status = ret; 8003f7e: 462e mov r6, r5 8003f80: e021 b.n 8003fc6 switch (PeriphClkInit->SpdifrxClockSelection) 8003f82: 2601 movs r6, #1 8003f84: 4635 mov r5, r6 8003f86: e01e b.n 8003fc6 8003f88: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8003f8c: d101 bne.n 8003f92 8003f8e: 2500 movs r5, #0 8003f90: e008 b.n 8003fa4 8003f92: 2601 movs r6, #1 8003f94: 4635 mov r5, r6 8003f96: e016 b.n 8003fc6 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003f98: 4a97 ldr r2, [pc, #604] @ (80041f8 ) 8003f9a: 6ad3 ldr r3, [r2, #44] @ 0x2c 8003f9c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003fa0: 62d3 str r3, [r2, #44] @ 0x2c HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8003fa2: 2500 movs r5, #0 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 8003fa4: 4a94 ldr r2, [pc, #592] @ (80041f8 ) 8003fa6: 6d13 ldr r3, [r2, #80] @ 0x50 8003fa8: f423 1340 bic.w r3, r3, #3145728 @ 0x300000 8003fac: 6ee1 ldr r1, [r4, #108] @ 0x6c 8003fae: 430b orrs r3, r1 8003fb0: 6513 str r3, [r2, #80] @ 0x50 HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003fb2: 2600 movs r6, #0 8003fb4: e007 b.n 8003fc6 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8003fb6: 2102 movs r1, #2 8003fb8: 3028 adds r0, #40 @ 0x28 8003fba: f7ff ff47 bl 8003e4c 8003fbe: 4605 mov r5, r0 break; 8003fc0: e7dc b.n 8003f7c HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003fc2: 2600 movs r6, #0 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8003fc4: 4635 mov r5, r6 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8003fc6: 6823 ldr r3, [r4, #0] 8003fc8: f413 7f80 tst.w r3, #256 @ 0x100 8003fcc: d014 beq.n 8003ff8 switch (PeriphClkInit->Sai1ClockSelection) 8003fce: 6da3 ldr r3, [r4, #88] @ 0x58 8003fd0: 2b04 cmp r3, #4 8003fd2: d831 bhi.n 8004038 8003fd4: e8df f003 tbb [pc, r3] 8003fd8: 08292203 .word 0x08292203 8003fdc: 08 .byte 0x08 8003fdd: 00 .byte 0x00 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003fde: 4a86 ldr r2, [pc, #536] @ (80041f8 ) 8003fe0: 6ad3 ldr r3, [r2, #44] @ 0x2c 8003fe2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8003fe6: 62d3 str r3, [r2, #44] @ 0x2c if (ret == HAL_OK) 8003fe8: bb4d cbnz r5, 800403e __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8003fea: 4a83 ldr r2, [pc, #524] @ (80041f8 ) 8003fec: 6d13 ldr r3, [r2, #80] @ 0x50 8003fee: f023 0307 bic.w r3, r3, #7 8003ff2: 6da1 ldr r1, [r4, #88] @ 0x58 8003ff4: 430b orrs r3, r1 8003ff6: 6513 str r3, [r2, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) 8003ff8: 6823 ldr r3, [r4, #0] 8003ffa: f413 7f00 tst.w r3, #512 @ 0x200 8003ffe: d042 beq.n 8004086 switch (PeriphClkInit->Sai2AClockSelection) 8004000: 6de3 ldr r3, [r4, #92] @ 0x5c 8004002: 2b80 cmp r3, #128 @ 0x80 8004004: d031 beq.n 800406a 8004006: d81f bhi.n 8004048 8004008: b34b cbz r3, 800405e 800400a: 2b40 cmp r3, #64 @ 0x40 800400c: d119 bne.n 8004042 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800400e: 2100 movs r1, #0 8004010: f104 0008 add.w r0, r4, #8 8004014: f7ff fe96 bl 8003d44 8004018: 4605 mov r5, r0 break; 800401a: e02c b.n 8004076 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800401c: 2100 movs r1, #0 800401e: f104 0008 add.w r0, r4, #8 8004022: f7ff fe8f bl 8003d44 8004026: 4605 mov r5, r0 break; 8004028: e7de b.n 8003fe8 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800402a: 2100 movs r1, #0 800402c: f104 0028 add.w r0, r4, #40 @ 0x28 8004030: f7ff ff0c bl 8003e4c 8004034: 4605 mov r5, r0 break; 8004036: e7d7 b.n 8003fe8 switch (PeriphClkInit->Sai1ClockSelection) 8004038: 2601 movs r6, #1 800403a: 4635 mov r5, r6 800403c: e7dc b.n 8003ff8 status = ret; 800403e: 462e mov r6, r5 8004040: e7da b.n 8003ff8 switch (PeriphClkInit->Sai2AClockSelection) 8004042: 2601 movs r6, #1 8004044: 4635 mov r5, r6 8004046: e01e b.n 8004086 8004048: f5b3 7f80 cmp.w r3, #256 @ 0x100 800404c: d013 beq.n 8004076 800404e: f5b3 7fa0 cmp.w r3, #320 @ 0x140 8004052: d010 beq.n 8004076 8004054: 2bc0 cmp r3, #192 @ 0xc0 8004056: d00e beq.n 8004076 8004058: 2601 movs r6, #1 800405a: 4635 mov r5, r6 800405c: e013 b.n 8004086 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800405e: 4a66 ldr r2, [pc, #408] @ (80041f8 ) 8004060: 6ad3 ldr r3, [r2, #44] @ 0x2c 8004062: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8004066: 62d3 str r3, [r2, #44] @ 0x2c break; 8004068: e005 b.n 8004076 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800406a: 2100 movs r1, #0 800406c: f104 0028 add.w r0, r4, #40 @ 0x28 8004070: f7ff feec bl 8003e4c 8004074: 4605 mov r5, r0 if (ret == HAL_OK) 8004076: b9d5 cbnz r5, 80040ae __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); 8004078: 4a5f ldr r2, [pc, #380] @ (80041f8 ) 800407a: 6d13 ldr r3, [r2, #80] @ 0x50 800407c: f423 73e0 bic.w r3, r3, #448 @ 0x1c0 8004080: 6de1 ldr r1, [r4, #92] @ 0x5c 8004082: 430b orrs r3, r1 8004084: 6513 str r3, [r2, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) 8004086: 6823 ldr r3, [r4, #0] 8004088: f413 6f80 tst.w r3, #1024 @ 0x400 800408c: d034 beq.n 80040f8 switch (PeriphClkInit->Sai2BClockSelection) 800408e: 6e23 ldr r3, [r4, #96] @ 0x60 8004090: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004094: d022 beq.n 80040dc 8004096: d80f bhi.n 80040b8 8004098: b1d3 cbz r3, 80040d0 800409a: f5b3 7f00 cmp.w r3, #512 @ 0x200 800409e: d108 bne.n 80040b2 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80040a0: 2100 movs r1, #0 80040a2: f104 0008 add.w r0, r4, #8 80040a6: f7ff fe4d bl 8003d44 80040aa: 4605 mov r5, r0 break; 80040ac: e01c b.n 80040e8 status = ret; 80040ae: 462e mov r6, r5 80040b0: e7e9 b.n 8004086 switch (PeriphClkInit->Sai2BClockSelection) 80040b2: 2601 movs r6, #1 80040b4: 4635 mov r5, r6 80040b6: e01f b.n 80040f8 80040b8: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80040bc: d014 beq.n 80040e8 80040be: f5b3 6f20 cmp.w r3, #2560 @ 0xa00 80040c2: d011 beq.n 80040e8 80040c4: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 80040c8: d00e beq.n 80040e8 80040ca: 2601 movs r6, #1 80040cc: 4635 mov r5, r6 80040ce: e013 b.n 80040f8 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80040d0: 4a49 ldr r2, [pc, #292] @ (80041f8 ) 80040d2: 6ad3 ldr r3, [r2, #44] @ 0x2c 80040d4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80040d8: 62d3 str r3, [r2, #44] @ 0x2c break; 80040da: e005 b.n 80040e8 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 80040dc: 2100 movs r1, #0 80040de: f104 0028 add.w r0, r4, #40 @ 0x28 80040e2: f7ff feb3 bl 8003e4c 80040e6: 4605 mov r5, r0 if (ret == HAL_OK) 80040e8: b9bd cbnz r5, 800411a __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); 80040ea: 4a43 ldr r2, [pc, #268] @ (80041f8 ) 80040ec: 6d13 ldr r3, [r2, #80] @ 0x50 80040ee: f423 6360 bic.w r3, r3, #3584 @ 0xe00 80040f2: 6e21 ldr r1, [r4, #96] @ 0x60 80040f4: 430b orrs r3, r1 80040f6: 6513 str r3, [r2, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) 80040f8: 6823 ldr r3, [r4, #0] 80040fa: f013 7f00 tst.w r3, #33554432 @ 0x2000000 80040fe: d024 beq.n 800414a switch (PeriphClkInit->OspiClockSelection) 8004100: 6ce3 ldr r3, [r4, #76] @ 0x4c 8004102: 2b20 cmp r3, #32 8004104: d013 beq.n 800412e 8004106: d80d bhi.n 8004124 8004108: b1bb cbz r3, 800413a 800410a: 2b10 cmp r3, #16 800410c: d107 bne.n 800411e __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800410e: 4a3a ldr r2, [pc, #232] @ (80041f8 ) 8004110: 6ad3 ldr r3, [r2, #44] @ 0x2c 8004112: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8004116: 62d3 str r3, [r2, #44] @ 0x2c break; 8004118: e00f b.n 800413a status = ret; 800411a: 462e mov r6, r5 800411c: e7ec b.n 80040f8 switch (PeriphClkInit->OspiClockSelection) 800411e: 2601 movs r6, #1 8004120: 4635 mov r5, r6 8004122: e012 b.n 800414a 8004124: 2b30 cmp r3, #48 @ 0x30 8004126: d008 beq.n 800413a 8004128: 2601 movs r6, #1 800412a: 4635 mov r5, r6 800412c: e00d b.n 800414a ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800412e: 2102 movs r1, #2 8004130: f104 0008 add.w r0, r4, #8 8004134: f7ff fe06 bl 8003d44 8004138: 4605 mov r5, r0 if (ret == HAL_OK) 800413a: b9d5 cbnz r5, 8004172 __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); 800413c: 4a2e ldr r2, [pc, #184] @ (80041f8 ) 800413e: 6cd3 ldr r3, [r2, #76] @ 0x4c 8004140: f023 0330 bic.w r3, r3, #48 @ 0x30 8004144: 6ce1 ldr r1, [r4, #76] @ 0x4c 8004146: 430b orrs r3, r1 8004148: 64d3 str r3, [r2, #76] @ 0x4c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800414a: 6823 ldr r3, [r4, #0] 800414c: f413 5f80 tst.w r3, #4096 @ 0x1000 8004150: d031 beq.n 80041b6 switch (PeriphClkInit->Spi123ClockSelection) 8004152: 6e63 ldr r3, [r4, #100] @ 0x64 8004154: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004158: d01f beq.n 800419a 800415a: d80f bhi.n 800417c 800415c: b1bb cbz r3, 800418e 800415e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004162: d108 bne.n 8004176 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8004164: 2100 movs r1, #0 8004166: f104 0008 add.w r0, r4, #8 800416a: f7ff fdeb bl 8003d44 800416e: 4605 mov r5, r0 break; 8004170: e019 b.n 80041a6 status = ret; 8004172: 462e mov r6, r5 8004174: e7e9 b.n 800414a switch (PeriphClkInit->Spi123ClockSelection) 8004176: 2601 movs r6, #1 8004178: 4635 mov r5, r6 800417a: e01c b.n 80041b6 800417c: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8004180: d011 beq.n 80041a6 8004182: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8004186: d00e beq.n 80041a6 8004188: 2601 movs r6, #1 800418a: 4635 mov r5, r6 800418c: e013 b.n 80041b6 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800418e: 4a1a ldr r2, [pc, #104] @ (80041f8 ) 8004190: 6ad3 ldr r3, [r2, #44] @ 0x2c 8004192: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8004196: 62d3 str r3, [r2, #44] @ 0x2c break; 8004198: e005 b.n 80041a6 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800419a: 2100 movs r1, #0 800419c: f104 0028 add.w r0, r4, #40 @ 0x28 80041a0: f7ff fe54 bl 8003e4c 80041a4: 4605 mov r5, r0 if (ret == HAL_OK) 80041a6: bb15 cbnz r5, 80041ee __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 80041a8: 4a13 ldr r2, [pc, #76] @ (80041f8 ) 80041aa: 6d13 ldr r3, [r2, #80] @ 0x50 80041ac: f423 43e0 bic.w r3, r3, #28672 @ 0x7000 80041b0: 6e61 ldr r1, [r4, #100] @ 0x64 80041b2: 430b orrs r3, r1 80041b4: 6513 str r3, [r2, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 80041b6: 6823 ldr r3, [r4, #0] 80041b8: f413 5f00 tst.w r3, #8192 @ 0x2000 80041bc: d032 beq.n 8004224 switch (PeriphClkInit->Spi45ClockSelection) 80041be: 6ea3 ldr r3, [r4, #104] @ 0x68 80041c0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80041c4: d026 beq.n 8004214 80041c6: d819 bhi.n 80041fc 80041c8: b143 cbz r3, 80041dc 80041ca: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80041ce: d110 bne.n 80041f2 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 80041d0: 2101 movs r1, #1 80041d2: f104 0008 add.w r0, r4, #8 80041d6: f7ff fdb5 bl 8003d44 80041da: 4605 mov r5, r0 if (ret == HAL_OK) 80041dc: bb0d cbnz r5, 8004222 __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 80041de: 4a06 ldr r2, [pc, #24] @ (80041f8 ) 80041e0: 6d13 ldr r3, [r2, #80] @ 0x50 80041e2: f423 23e0 bic.w r3, r3, #458752 @ 0x70000 80041e6: 6ea1 ldr r1, [r4, #104] @ 0x68 80041e8: 430b orrs r3, r1 80041ea: 6513 str r3, [r2, #80] @ 0x50 80041ec: e01a b.n 8004224 status = ret; 80041ee: 462e mov r6, r5 80041f0: e7e1 b.n 80041b6 switch (PeriphClkInit->Spi45ClockSelection) 80041f2: 2601 movs r6, #1 80041f4: 4635 mov r5, r6 80041f6: e015 b.n 8004224 80041f8: 58024400 .word 0x58024400 80041fc: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8004200: d0ec beq.n 80041dc 8004202: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8004206: d0e9 beq.n 80041dc 8004208: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800420c: d0e6 beq.n 80041dc 800420e: 2601 movs r6, #1 8004210: 4635 mov r5, r6 8004212: e007 b.n 8004224 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8004214: 2101 movs r1, #1 8004216: f104 0028 add.w r0, r4, #40 @ 0x28 800421a: f7ff fe17 bl 8003e4c 800421e: 4605 mov r5, r0 break; 8004220: e7dc b.n 80041dc status = ret; 8004222: 462e mov r6, r5 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 8004224: 6823 ldr r3, [r4, #0] 8004226: f413 4f80 tst.w r3, #16384 @ 0x4000 800422a: d018 beq.n 800425e switch (PeriphClkInit->Spi6ClockSelection) 800422c: f8d4 30b0 ldr.w r3, [r4, #176] @ 0xb0 8004230: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004234: d038 beq.n 80042a8 8004236: d824 bhi.n 8004282 8004238: b143 cbz r3, 800424c 800423a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800423e: d11d bne.n 800427c ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8004240: 2101 movs r1, #1 8004242: f104 0008 add.w r0, r4, #8 8004246: f7ff fd7d bl 8003d44 800424a: 4605 mov r5, r0 if (ret == HAL_OK) 800424c: bb9d cbnz r5, 80042b6 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800424e: 4a90 ldr r2, [pc, #576] @ (8004490 ) 8004250: 6d93 ldr r3, [r2, #88] @ 0x58 8004252: f023 43e0 bic.w r3, r3, #1879048192 @ 0x70000000 8004256: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0 800425a: 430b orrs r3, r1 800425c: 6593 str r3, [r2, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800425e: 6823 ldr r3, [r4, #0] 8004260: f413 4f00 tst.w r3, #32768 @ 0x8000 8004264: d03f beq.n 80042e6 switch (PeriphClkInit->FdcanClockSelection) 8004266: 6fa3 ldr r3, [r4, #120] @ 0x78 8004268: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800426c: d025 beq.n 80042ba 800426e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004272: d030 beq.n 80042d6 8004274: b333 cbz r3, 80042c4 8004276: 2601 movs r6, #1 8004278: 4635 mov r5, r6 800427a: e034 b.n 80042e6 switch (PeriphClkInit->Spi6ClockSelection) 800427c: 2601 movs r6, #1 800427e: 4635 mov r5, r6 8004280: e7ed b.n 800425e 8004282: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8004286: d0e1 beq.n 800424c 8004288: d808 bhi.n 800429c 800428a: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800428e: d0dd beq.n 800424c 8004290: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8004294: d0da beq.n 800424c 8004296: 2601 movs r6, #1 8004298: 4635 mov r5, r6 800429a: e7e0 b.n 800425e 800429c: f1b3 4fc0 cmp.w r3, #1610612736 @ 0x60000000 80042a0: d0d4 beq.n 800424c 80042a2: 2601 movs r6, #1 80042a4: 4635 mov r5, r6 80042a6: e7da b.n 800425e ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80042a8: 2101 movs r1, #1 80042aa: f104 0028 add.w r0, r4, #40 @ 0x28 80042ae: f7ff fdcd bl 8003e4c 80042b2: 4605 mov r5, r0 break; 80042b4: e7ca b.n 800424c status = ret; 80042b6: 462e mov r6, r5 80042b8: e7d1 b.n 800425e __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80042ba: 4a75 ldr r2, [pc, #468] @ (8004490 ) 80042bc: 6ad3 ldr r3, [r2, #44] @ 0x2c 80042be: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80042c2: 62d3 str r3, [r2, #44] @ 0x2c if (ret == HAL_OK) 80042c4: b975 cbnz r5, 80042e4 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 80042c6: 4a72 ldr r2, [pc, #456] @ (8004490 ) 80042c8: 6d13 ldr r3, [r2, #80] @ 0x50 80042ca: f023 5340 bic.w r3, r3, #805306368 @ 0x30000000 80042ce: 6fa1 ldr r1, [r4, #120] @ 0x78 80042d0: 430b orrs r3, r1 80042d2: 6513 str r3, [r2, #80] @ 0x50 80042d4: e007 b.n 80042e6 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 80042d6: 2101 movs r1, #1 80042d8: f104 0008 add.w r0, r4, #8 80042dc: f7ff fd32 bl 8003d44 80042e0: 4605 mov r5, r0 break; 80042e2: e7ef b.n 80042c4 status = ret; 80042e4: 462e mov r6, r5 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 80042e6: 6823 ldr r3, [r4, #0] 80042e8: f013 7f80 tst.w r3, #16777216 @ 0x1000000 80042ec: d013 beq.n 8004316 switch (PeriphClkInit->FmcClockSelection) 80042ee: 6ca3 ldr r3, [r4, #72] @ 0x48 80042f0: 2b03 cmp r3, #3 80042f2: d83c bhi.n 800436e 80042f4: e8df f003 tbb [pc, r3] 80042f8: 07340207 .word 0x07340207 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80042fc: 4a64 ldr r2, [pc, #400] @ (8004490 ) 80042fe: 6ad3 ldr r3, [r2, #44] @ 0x2c 8004300: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8004304: 62d3 str r3, [r2, #44] @ 0x2c if (ret == HAL_OK) 8004306: bbad cbnz r5, 8004374 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 8004308: 4a61 ldr r2, [pc, #388] @ (8004490 ) 800430a: 6cd3 ldr r3, [r2, #76] @ 0x4c 800430c: f023 0303 bic.w r3, r3, #3 8004310: 6ca1 ldr r1, [r4, #72] @ 0x48 8004312: 430b orrs r3, r1 8004314: 64d3 str r3, [r2, #76] @ 0x4c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8004316: 6823 ldr r3, [r4, #0] 8004318: f413 0f80 tst.w r3, #4194304 @ 0x400000 800431c: d12c bne.n 8004378 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800431e: 6823 ldr r3, [r4, #0] 8004320: f013 0f01 tst.w r3, #1 8004324: f000 80a5 beq.w 8004472 switch (PeriphClkInit->Usart16ClockSelection) 8004328: f8d4 3084 ldr.w r3, [r4, #132] @ 0x84 800432c: 2b28 cmp r3, #40 @ 0x28 800432e: f200 809e bhi.w 800446e 8004332: e8df f003 tbb [pc, r3] 8004336: 9c8b .short 0x9c8b 8004338: 9c9c9c9c .word 0x9c9c9c9c 800433c: 9c859c9c .word 0x9c859c9c 8004340: 9c9c9c9c .word 0x9c9c9c9c 8004344: 9c959c9c .word 0x9c959c9c 8004348: 9c9c9c9c .word 0x9c9c9c9c 800434c: 9c8b9c9c .word 0x9c8b9c9c 8004350: 9c9c9c9c .word 0x9c9c9c9c 8004354: 9c8b9c9c .word 0x9c8b9c9c 8004358: 9c9c9c9c .word 0x9c9c9c9c 800435c: 9c9c .short 0x9c9c 800435e: 8b .byte 0x8b 800435f: 00 .byte 0x00 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8004360: 2102 movs r1, #2 8004362: f104 0008 add.w r0, r4, #8 8004366: f7ff fced bl 8003d44 800436a: 4605 mov r5, r0 break; 800436c: e7cb b.n 8004306 switch (PeriphClkInit->FmcClockSelection) 800436e: 2601 movs r6, #1 8004370: 4635 mov r5, r6 8004372: e7d0 b.n 8004316 status = ret; 8004374: 462e mov r6, r5 8004376: e7ce b.n 8004316 SET_BIT(PWR->CR1, PWR_CR1_DBP); 8004378: 4a46 ldr r2, [pc, #280] @ (8004494 ) 800437a: 6813 ldr r3, [r2, #0] 800437c: f443 7380 orr.w r3, r3, #256 @ 0x100 8004380: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 8004382: f7fc fbeb bl 8000b5c 8004386: 4607 mov r7, r0 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8004388: 4b42 ldr r3, [pc, #264] @ (8004494 ) 800438a: 681b ldr r3, [r3, #0] 800438c: f413 7f80 tst.w r3, #256 @ 0x100 8004390: d105 bne.n 800439e if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004392: f7fc fbe3 bl 8000b5c 8004396: 1bc0 subs r0, r0, r7 8004398: 2864 cmp r0, #100 @ 0x64 800439a: d9f5 bls.n 8004388 ret = HAL_TIMEOUT; 800439c: 2503 movs r5, #3 if (ret == HAL_OK) 800439e: 2d00 cmp r5, #0 80043a0: d14a bne.n 8004438 if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 80043a2: 4b3b ldr r3, [pc, #236] @ (8004490 ) 80043a4: 6f1b ldr r3, [r3, #112] @ 0x70 80043a6: f8d4 20b4 ldr.w r2, [r4, #180] @ 0xb4 80043aa: 4053 eors r3, r2 80043ac: f413 7f40 tst.w r3, #768 @ 0x300 80043b0: d00c beq.n 80043cc tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80043b2: 4b37 ldr r3, [pc, #220] @ (8004490 ) 80043b4: 6f1a ldr r2, [r3, #112] @ 0x70 80043b6: f422 7240 bic.w r2, r2, #768 @ 0x300 __HAL_RCC_BACKUPRESET_FORCE(); 80043ba: 6f19 ldr r1, [r3, #112] @ 0x70 80043bc: f441 3180 orr.w r1, r1, #65536 @ 0x10000 80043c0: 6719 str r1, [r3, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 80043c2: 6f19 ldr r1, [r3, #112] @ 0x70 80043c4: f421 3180 bic.w r1, r1, #65536 @ 0x10000 80043c8: 6719 str r1, [r3, #112] @ 0x70 RCC->BDCR = tmpreg; 80043ca: 671a str r2, [r3, #112] @ 0x70 if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 80043cc: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4 80043d0: f5b3 7f80 cmp.w r3, #256 @ 0x100 80043d4: d015 beq.n 8004402 if (ret == HAL_OK) 80043d6: bb8d cbnz r5, 800443c __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80043d8: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4 80043dc: f403 7240 and.w r2, r3, #768 @ 0x300 80043e0: f5b2 7f40 cmp.w r2, #768 @ 0x300 80043e4: d01e beq.n 8004424 80043e6: 4a2a ldr r2, [pc, #168] @ (8004490 ) 80043e8: 6913 ldr r3, [r2, #16] 80043ea: f423 537c bic.w r3, r3, #16128 @ 0x3f00 80043ee: 6113 str r3, [r2, #16] 80043f0: 4927 ldr r1, [pc, #156] @ (8004490 ) 80043f2: 6f0b ldr r3, [r1, #112] @ 0x70 80043f4: f8d4 20b4 ldr.w r2, [r4, #180] @ 0xb4 80043f8: f3c2 020b ubfx r2, r2, #0, #12 80043fc: 4313 orrs r3, r2 80043fe: 670b str r3, [r1, #112] @ 0x70 8004400: e78d b.n 800431e tickstart = HAL_GetTick(); 8004402: f7fc fbab bl 8000b5c 8004406: 4607 mov r7, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8004408: 4b21 ldr r3, [pc, #132] @ (8004490 ) 800440a: 6f1b ldr r3, [r3, #112] @ 0x70 800440c: f013 0f02 tst.w r3, #2 8004410: d1e1 bne.n 80043d6 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004412: f7fc fba3 bl 8000b5c 8004416: 1bc0 subs r0, r0, r7 8004418: f241 3388 movw r3, #5000 @ 0x1388 800441c: 4298 cmp r0, r3 800441e: d9f3 bls.n 8004408 ret = HAL_TIMEOUT; 8004420: 2503 movs r5, #3 8004422: e7d8 b.n 80043d6 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004424: 481a ldr r0, [pc, #104] @ (8004490 ) 8004426: 6902 ldr r2, [r0, #16] 8004428: f422 527c bic.w r2, r2, #16128 @ 0x3f00 800442c: 491a ldr r1, [pc, #104] @ (8004498 ) 800442e: ea01 1313 and.w r3, r1, r3, lsr #4 8004432: 4313 orrs r3, r2 8004434: 6103 str r3, [r0, #16] 8004436: e7db b.n 80043f0 status = ret; 8004438: 462e mov r6, r5 800443a: e770 b.n 800431e status = ret; 800443c: 462e mov r6, r5 800443e: e76e b.n 800431e ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8004440: 2101 movs r1, #1 8004442: f104 0008 add.w r0, r4, #8 8004446: f7ff fc7d bl 8003d44 800444a: 4605 mov r5, r0 if (ret == HAL_OK) 800444c: b9f5 cbnz r5, 800448c __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800444e: 4a10 ldr r2, [pc, #64] @ (8004490 ) 8004450: 6d53 ldr r3, [r2, #84] @ 0x54 8004452: f023 0338 bic.w r3, r3, #56 @ 0x38 8004456: f8d4 1084 ldr.w r1, [r4, #132] @ 0x84 800445a: 430b orrs r3, r1 800445c: 6553 str r3, [r2, #84] @ 0x54 800445e: e008 b.n 8004472 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8004460: 2101 movs r1, #1 8004462: f104 0028 add.w r0, r4, #40 @ 0x28 8004466: f7ff fcf1 bl 8003e4c 800446a: 4605 mov r5, r0 break; 800446c: e7ee b.n 800444c switch (PeriphClkInit->Usart16ClockSelection) 800446e: 2601 movs r6, #1 8004470: 4635 mov r5, r6 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8004472: 6823 ldr r3, [r4, #0] 8004474: f013 0f02 tst.w r3, #2 8004478: d01f beq.n 80044ba switch (PeriphClkInit->Usart234578ClockSelection) 800447a: f8d4 3080 ldr.w r3, [r4, #128] @ 0x80 800447e: 2b05 cmp r3, #5 8004480: d833 bhi.n 80044ea 8004482: e8df f003 tbb [pc, r3] 8004486: 0b11 .short 0x0b11 8004488: 1111112b .word 0x1111112b status = ret; 800448c: 462e mov r6, r5 800448e: e7f0 b.n 8004472 8004490: 58024400 .word 0x58024400 8004494: 58024800 .word 0x58024800 8004498: 00ffffcf .word 0x00ffffcf ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800449c: 2101 movs r1, #1 800449e: f104 0008 add.w r0, r4, #8 80044a2: f7ff fc4f bl 8003d44 80044a6: 4605 mov r5, r0 if (ret == HAL_OK) 80044a8: bb15 cbnz r5, 80044f0 __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 80044aa: 4ab7 ldr r2, [pc, #732] @ (8004788 ) 80044ac: 6d53 ldr r3, [r2, #84] @ 0x54 80044ae: f023 0307 bic.w r3, r3, #7 80044b2: f8d4 1080 ldr.w r1, [r4, #128] @ 0x80 80044b6: 430b orrs r3, r1 80044b8: 6553 str r3, [r2, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 80044ba: 6823 ldr r3, [r4, #0] 80044bc: f013 0f04 tst.w r3, #4 80044c0: d029 beq.n 8004516 switch (PeriphClkInit->Lpuart1ClockSelection) 80044c2: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c 80044c6: 2b05 cmp r3, #5 80044c8: f200 8108 bhi.w 80046dc 80044cc: e8df f013 tbh [pc, r3, lsl #1] 80044d0: 00120018 .word 0x00120018 80044d4: 001800ff .word 0x001800ff 80044d8: 00180018 .word 0x00180018 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80044dc: 2101 movs r1, #1 80044de: f104 0028 add.w r0, r4, #40 @ 0x28 80044e2: f7ff fcb3 bl 8003e4c 80044e6: 4605 mov r5, r0 break; 80044e8: e7de b.n 80044a8 switch (PeriphClkInit->Usart234578ClockSelection) 80044ea: 2601 movs r6, #1 80044ec: 4635 mov r5, r6 80044ee: e7e4 b.n 80044ba status = ret; 80044f0: 462e mov r6, r5 80044f2: e7e2 b.n 80044ba ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 80044f4: 2101 movs r1, #1 80044f6: f104 0008 add.w r0, r4, #8 80044fa: f7ff fc23 bl 8003d44 80044fe: 4605 mov r5, r0 if (ret == HAL_OK) 8004500: 2d00 cmp r5, #0 8004502: f040 80ee bne.w 80046e2 __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8004506: 4aa0 ldr r2, [pc, #640] @ (8004788 ) 8004508: 6d93 ldr r3, [r2, #88] @ 0x58 800450a: f023 0307 bic.w r3, r3, #7 800450e: f8d4 109c ldr.w r1, [r4, #156] @ 0x9c 8004512: 430b orrs r3, r1 8004514: 6593 str r3, [r2, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8004516: 6823 ldr r3, [r4, #0] 8004518: f013 0f20 tst.w r3, #32 800451c: d01d beq.n 800455a switch (PeriphClkInit->Lptim1ClockSelection) 800451e: f8d4 3098 ldr.w r3, [r4, #152] @ 0x98 8004522: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004526: f000 80f0 beq.w 800470a 800452a: f200 80df bhi.w 80046ec 800452e: b14b cbz r3, 8004544 8004530: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8004534: f040 80d7 bne.w 80046e6 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8004538: 2100 movs r1, #0 800453a: f104 0008 add.w r0, r4, #8 800453e: f7ff fc01 bl 8003d44 8004542: 4605 mov r5, r0 if (ret == HAL_OK) 8004544: 2d00 cmp r5, #0 8004546: f040 80e7 bne.w 8004718 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800454a: 4a8f ldr r2, [pc, #572] @ (8004788 ) 800454c: 6d53 ldr r3, [r2, #84] @ 0x54 800454e: f023 43e0 bic.w r3, r3, #1879048192 @ 0x70000000 8004552: f8d4 1098 ldr.w r1, [r4, #152] @ 0x98 8004556: 430b orrs r3, r1 8004558: 6553 str r3, [r2, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800455a: 6823 ldr r3, [r4, #0] 800455c: f013 0f40 tst.w r3, #64 @ 0x40 8004560: d01d beq.n 800459e switch (PeriphClkInit->Lptim2ClockSelection) 8004562: f8d4 30a4 ldr.w r3, [r4, #164] @ 0xa4 8004566: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800456a: f000 80e9 beq.w 8004740 800456e: f200 80d8 bhi.w 8004722 8004572: b14b cbz r3, 8004588 8004574: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8004578: f040 80d0 bne.w 800471c ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800457c: 2100 movs r1, #0 800457e: f104 0008 add.w r0, r4, #8 8004582: f7ff fbdf bl 8003d44 8004586: 4605 mov r5, r0 if (ret == HAL_OK) 8004588: 2d00 cmp r5, #0 800458a: f040 80e0 bne.w 800474e __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800458e: 4a7e ldr r2, [pc, #504] @ (8004788 ) 8004590: 6d93 ldr r3, [r2, #88] @ 0x58 8004592: f423 53e0 bic.w r3, r3, #7168 @ 0x1c00 8004596: f8d4 10a4 ldr.w r1, [r4, #164] @ 0xa4 800459a: 430b orrs r3, r1 800459c: 6593 str r3, [r2, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800459e: 6823 ldr r3, [r4, #0] 80045a0: f013 0f80 tst.w r3, #128 @ 0x80 80045a4: d01d beq.n 80045e2 switch (PeriphClkInit->Lptim345ClockSelection) 80045a6: f8d4 30a8 ldr.w r3, [r4, #168] @ 0xa8 80045aa: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80045ae: f000 80e2 beq.w 8004776 80045b2: f200 80d1 bhi.w 8004758 80045b6: b14b cbz r3, 80045cc 80045b8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80045bc: f040 80c9 bne.w 8004752 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80045c0: 2100 movs r1, #0 80045c2: f104 0008 add.w r0, r4, #8 80045c6: f7ff fbbd bl 8003d44 80045ca: 4605 mov r5, r0 if (ret == HAL_OK) 80045cc: 2d00 cmp r5, #0 80045ce: f040 80d9 bne.w 8004784 __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 80045d2: 4a6d ldr r2, [pc, #436] @ (8004788 ) 80045d4: 6d93 ldr r3, [r2, #88] @ 0x58 80045d6: f423 4360 bic.w r3, r3, #57344 @ 0xe000 80045da: f8d4 10a8 ldr.w r1, [r4, #168] @ 0xa8 80045de: 430b orrs r3, r1 80045e0: 6593 str r3, [r2, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 80045e2: 6823 ldr r3, [r4, #0] 80045e4: f013 0f08 tst.w r3, #8 80045e8: d00d beq.n 8004606 if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 80045ea: f8d4 308c ldr.w r3, [r4, #140] @ 0x8c 80045ee: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80045f2: f000 80cb beq.w 800478c __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 80045f6: 4a64 ldr r2, [pc, #400] @ (8004788 ) 80045f8: 6d53 ldr r3, [r2, #84] @ 0x54 80045fa: f423 5340 bic.w r3, r3, #12288 @ 0x3000 80045fe: f8d4 108c ldr.w r1, [r4, #140] @ 0x8c 8004602: 430b orrs r3, r1 8004604: 6553 str r3, [r2, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 8004606: 6823 ldr r3, [r4, #0] 8004608: f013 0f10 tst.w r3, #16 800460c: d00d beq.n 800462a if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800460e: f8d4 30a0 ldr.w r3, [r4, #160] @ 0xa0 8004612: f5b3 7f80 cmp.w r3, #256 @ 0x100 8004616: f000 80c3 beq.w 80047a0 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800461a: 4a5b ldr r2, [pc, #364] @ (8004788 ) 800461c: 6d93 ldr r3, [r2, #88] @ 0x58 800461e: f423 7340 bic.w r3, r3, #768 @ 0x300 8004622: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0 8004626: 430b orrs r3, r1 8004628: 6593 str r3, [r2, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800462a: 6823 ldr r3, [r4, #0] 800462c: f413 2f00 tst.w r3, #524288 @ 0x80000 8004630: d01c beq.n 800466c switch (PeriphClkInit->AdcClockSelection) 8004632: f8d4 30ac ldr.w r3, [r4, #172] @ 0xac 8004636: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800463a: f000 80bb beq.w 80047b4 800463e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8004642: d008 beq.n 8004656 8004644: 2b00 cmp r3, #0 8004646: f040 80bc bne.w 80047c2 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800464a: 2100 movs r1, #0 800464c: f104 0008 add.w r0, r4, #8 8004650: f7ff fb78 bl 8003d44 8004654: 4605 mov r5, r0 if (ret == HAL_OK) 8004656: 2d00 cmp r5, #0 8004658: f040 80b6 bne.w 80047c8 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800465c: 4a4a ldr r2, [pc, #296] @ (8004788 ) 800465e: 6d93 ldr r3, [r2, #88] @ 0x58 8004660: f423 3340 bic.w r3, r3, #196608 @ 0x30000 8004664: f8d4 10ac ldr.w r1, [r4, #172] @ 0xac 8004668: 430b orrs r3, r1 800466a: 6593 str r3, [r2, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800466c: 6823 ldr r3, [r4, #0] 800466e: f413 2f80 tst.w r3, #262144 @ 0x40000 8004672: d01c beq.n 80046ae switch (PeriphClkInit->UsbClockSelection) 8004674: f8d4 3090 ldr.w r3, [r4, #144] @ 0x90 8004678: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800467c: f000 80a6 beq.w 80047cc 8004680: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8004684: d008 beq.n 8004698 8004686: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800468a: f040 80a6 bne.w 80047da __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800468e: 4a3e ldr r2, [pc, #248] @ (8004788 ) 8004690: 6ad3 ldr r3, [r2, #44] @ 0x2c 8004692: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8004696: 62d3 str r3, [r2, #44] @ 0x2c if (ret == HAL_OK) 8004698: 2d00 cmp r5, #0 800469a: f040 80a1 bne.w 80047e0 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800469e: 4a3a ldr r2, [pc, #232] @ (8004788 ) 80046a0: 6d53 ldr r3, [r2, #84] @ 0x54 80046a2: f423 1340 bic.w r3, r3, #3145728 @ 0x300000 80046a6: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90 80046aa: 430b orrs r3, r1 80046ac: 6553 str r3, [r2, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 80046ae: 6823 ldr r3, [r4, #0] 80046b0: f413 3f80 tst.w r3, #65536 @ 0x10000 80046b4: f000 80ac beq.w 8004810 switch (PeriphClkInit->SdmmcClockSelection) 80046b8: 6d23 ldr r3, [r4, #80] @ 0x50 80046ba: 2b00 cmp r3, #0 80046bc: f000 8092 beq.w 80047e4 80046c0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80046c4: f000 809c beq.w 8004800 80046c8: 2601 movs r6, #1 80046ca: 4635 mov r5, r6 80046cc: e0a0 b.n 8004810 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80046ce: 2101 movs r1, #1 80046d0: f104 0028 add.w r0, r4, #40 @ 0x28 80046d4: f7ff fbba bl 8003e4c 80046d8: 4605 mov r5, r0 break; 80046da: e711 b.n 8004500 switch (PeriphClkInit->Lpuart1ClockSelection) 80046dc: 2601 movs r6, #1 80046de: 4635 mov r5, r6 80046e0: e719 b.n 8004516 status = ret; 80046e2: 462e mov r6, r5 80046e4: e717 b.n 8004516 switch (PeriphClkInit->Lptim1ClockSelection) 80046e6: 2601 movs r6, #1 80046e8: 4635 mov r5, r6 80046ea: e736 b.n 800455a 80046ec: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80046f0: f43f af28 beq.w 8004544 80046f4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 80046f8: f43f af24 beq.w 8004544 80046fc: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8004700: f43f af20 beq.w 8004544 8004704: 2601 movs r6, #1 8004706: 4635 mov r5, r6 8004708: e727 b.n 800455a ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800470a: 2102 movs r1, #2 800470c: f104 0028 add.w r0, r4, #40 @ 0x28 8004710: f7ff fb9c bl 8003e4c 8004714: 4605 mov r5, r0 break; 8004716: e715 b.n 8004544 status = ret; 8004718: 462e mov r6, r5 800471a: e71e b.n 800455a switch (PeriphClkInit->Lptim2ClockSelection) 800471c: 2601 movs r6, #1 800471e: 4635 mov r5, r6 8004720: e73d b.n 800459e 8004722: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004726: f43f af2f beq.w 8004588 800472a: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800472e: f43f af2b beq.w 8004588 8004732: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8004736: f43f af27 beq.w 8004588 800473a: 2601 movs r6, #1 800473c: 4635 mov r5, r6 800473e: e72e b.n 800459e ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8004740: 2102 movs r1, #2 8004742: f104 0028 add.w r0, r4, #40 @ 0x28 8004746: f7ff fb81 bl 8003e4c 800474a: 4605 mov r5, r0 break; 800474c: e71c b.n 8004588 status = ret; 800474e: 462e mov r6, r5 8004750: e725 b.n 800459e switch (PeriphClkInit->Lptim345ClockSelection) 8004752: 2601 movs r6, #1 8004754: 4635 mov r5, r6 8004756: e744 b.n 80045e2 8004758: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800475c: f43f af36 beq.w 80045cc 8004760: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 8004764: f43f af32 beq.w 80045cc 8004768: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800476c: f43f af2e beq.w 80045cc 8004770: 2601 movs r6, #1 8004772: 4635 mov r5, r6 8004774: e735 b.n 80045e2 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8004776: 2102 movs r1, #2 8004778: f104 0028 add.w r0, r4, #40 @ 0x28 800477c: f7ff fb66 bl 8003e4c 8004780: 4605 mov r5, r0 break; 8004782: e723 b.n 80045cc status = ret; 8004784: 462e mov r6, r5 8004786: e72c b.n 80045e2 8004788: 58024400 .word 0x58024400 if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800478c: 2102 movs r1, #2 800478e: f104 0028 add.w r0, r4, #40 @ 0x28 8004792: f7ff fb5b bl 8003e4c 8004796: 2800 cmp r0, #0 8004798: f43f af2d beq.w 80045f6 status = HAL_ERROR; 800479c: 2601 movs r6, #1 800479e: e72a b.n 80045f6 if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 80047a0: 2102 movs r1, #2 80047a2: f104 0028 add.w r0, r4, #40 @ 0x28 80047a6: f7ff fb51 bl 8003e4c 80047aa: 2800 cmp r0, #0 80047ac: f43f af35 beq.w 800461a status = HAL_ERROR; 80047b0: 2601 movs r6, #1 80047b2: e732 b.n 800461a ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 80047b4: 2102 movs r1, #2 80047b6: f104 0028 add.w r0, r4, #40 @ 0x28 80047ba: f7ff fb47 bl 8003e4c 80047be: 4605 mov r5, r0 break; 80047c0: e749 b.n 8004656 switch (PeriphClkInit->AdcClockSelection) 80047c2: 2601 movs r6, #1 80047c4: 4635 mov r5, r6 80047c6: e751 b.n 800466c status = ret; 80047c8: 462e mov r6, r5 80047ca: e74f b.n 800466c ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 80047cc: 2101 movs r1, #1 80047ce: f104 0028 add.w r0, r4, #40 @ 0x28 80047d2: f7ff fb3b bl 8003e4c 80047d6: 4605 mov r5, r0 break; 80047d8: e75e b.n 8004698 switch (PeriphClkInit->UsbClockSelection) 80047da: 2601 movs r6, #1 80047dc: 4635 mov r5, r6 80047de: e766 b.n 80046ae status = ret; 80047e0: 462e mov r6, r5 80047e2: e764 b.n 80046ae __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80047e4: 4a6f ldr r2, [pc, #444] @ (80049a4 ) 80047e6: 6ad3 ldr r3, [r2, #44] @ 0x2c 80047e8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80047ec: 62d3 str r3, [r2, #44] @ 0x2c if (ret == HAL_OK) 80047ee: b975 cbnz r5, 800480e __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 80047f0: 4a6c ldr r2, [pc, #432] @ (80049a4 ) 80047f2: 6cd3 ldr r3, [r2, #76] @ 0x4c 80047f4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80047f8: 6d21 ldr r1, [r4, #80] @ 0x50 80047fa: 430b orrs r3, r1 80047fc: 64d3 str r3, [r2, #76] @ 0x4c 80047fe: e007 b.n 8004810 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8004800: 2102 movs r1, #2 8004802: f104 0008 add.w r0, r4, #8 8004806: f7ff fa9d bl 8003d44 800480a: 4605 mov r5, r0 break; 800480c: e7ef b.n 80047ee status = ret; 800480e: 462e mov r6, r5 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 8004810: 6823 ldr r3, [r4, #0] 8004812: f013 5f00 tst.w r3, #536870912 @ 0x20000000 8004816: d111 bne.n 800483c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8004818: 6823 ldr r3, [r4, #0] 800481a: f413 3f00 tst.w r3, #131072 @ 0x20000 800481e: d028 beq.n 8004872 switch (PeriphClkInit->RngClockSelection) 8004820: f8d4 3088 ldr.w r3, [r4, #136] @ 0x88 8004824: f5b3 7f80 cmp.w r3, #256 @ 0x100 8004828: d014 beq.n 8004854 800482a: d910 bls.n 800484e 800482c: f5b3 7f00 cmp.w r3, #512 @ 0x200 8004830: d015 beq.n 800485e 8004832: f5b3 7f40 cmp.w r3, #768 @ 0x300 8004836: d012 beq.n 800485e 8004838: 2601 movs r6, #1 800483a: e01a b.n 8004872 if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800483c: 2102 movs r1, #2 800483e: f104 0028 add.w r0, r4, #40 @ 0x28 8004842: f7ff fb03 bl 8003e4c 8004846: 2800 cmp r0, #0 8004848: d0e6 beq.n 8004818 status = HAL_ERROR; 800484a: 2601 movs r6, #1 800484c: e7e4 b.n 8004818 switch (PeriphClkInit->RngClockSelection) 800484e: b133 cbz r3, 800485e 8004850: 2601 movs r6, #1 8004852: e00e b.n 8004872 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004854: 4a53 ldr r2, [pc, #332] @ (80049a4 ) 8004856: 6ad3 ldr r3, [r2, #44] @ 0x2c 8004858: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800485c: 62d3 str r3, [r2, #44] @ 0x2c if (ret == HAL_OK) 800485e: 2d00 cmp r5, #0 8004860: d168 bne.n 8004934 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8004862: 4a50 ldr r2, [pc, #320] @ (80049a4 ) 8004864: 6d53 ldr r3, [r2, #84] @ 0x54 8004866: f423 7340 bic.w r3, r3, #768 @ 0x300 800486a: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88 800486e: 430b orrs r3, r1 8004870: 6553 str r3, [r2, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 8004872: 6823 ldr r3, [r4, #0] 8004874: f413 1f80 tst.w r3, #1048576 @ 0x100000 8004878: d006 beq.n 8004888 __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800487a: 4a4a ldr r2, [pc, #296] @ (80049a4 ) 800487c: 6d13 ldr r3, [r2, #80] @ 0x50 800487e: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8004882: 6fe1 ldr r1, [r4, #124] @ 0x7c 8004884: 430b orrs r3, r1 8004886: 6513 str r3, [r2, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8004888: 6823 ldr r3, [r4, #0] 800488a: f413 1f00 tst.w r3, #2097152 @ 0x200000 800488e: d006 beq.n 800489e __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 8004890: 4a44 ldr r2, [pc, #272] @ (80049a4 ) 8004892: 6d13 ldr r3, [r2, #80] @ 0x50 8004894: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8004898: 6f21 ldr r1, [r4, #112] @ 0x70 800489a: 430b orrs r3, r1 800489c: 6513 str r3, [r2, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) 800489e: 6823 ldr r3, [r4, #0] 80048a0: f413 6f00 tst.w r3, #2048 @ 0x800 80048a4: d006 beq.n 80048b4 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); 80048a6: 4a3f ldr r2, [pc, #252] @ (80049a4 ) 80048a8: 6d93 ldr r3, [r2, #88] @ 0x58 80048aa: f023 6300 bic.w r3, r3, #134217728 @ 0x8000000 80048ae: 6f61 ldr r1, [r4, #116] @ 0x74 80048b0: 430b orrs r3, r1 80048b2: 6593 str r3, [r2, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 80048b4: 6823 ldr r3, [r4, #0] 80048b6: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 80048ba: d009 beq.n 80048d0 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 80048bc: 4b39 ldr r3, [pc, #228] @ (80049a4 ) 80048be: 691a ldr r2, [r3, #16] 80048c0: f422 4200 bic.w r2, r2, #32768 @ 0x8000 80048c4: 611a str r2, [r3, #16] 80048c6: 691a ldr r2, [r3, #16] 80048c8: f8d4 10b8 ldr.w r1, [r4, #184] @ 0xb8 80048cc: 430a orrs r2, r1 80048ce: 611a str r2, [r3, #16] if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 80048d0: 6823 ldr r3, [r4, #0] 80048d2: 2b00 cmp r3, #0 80048d4: da06 bge.n 80048e4 __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 80048d6: 4a33 ldr r2, [pc, #204] @ (80049a4 ) 80048d8: 6cd3 ldr r3, [r2, #76] @ 0x4c 80048da: f023 5340 bic.w r3, r3, #805306368 @ 0x30000000 80048de: 6d61 ldr r1, [r4, #84] @ 0x54 80048e0: 430b orrs r3, r1 80048e2: 64d3 str r3, [r2, #76] @ 0x4c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80048e4: 6823 ldr r3, [r4, #0] 80048e6: f413 0f00 tst.w r3, #8388608 @ 0x800000 80048ea: d007 beq.n 80048fc __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80048ec: 4a2d ldr r2, [pc, #180] @ (80049a4 ) 80048ee: 6d53 ldr r3, [r2, #84] @ 0x54 80048f0: f423 0340 bic.w r3, r3, #12582912 @ 0xc00000 80048f4: f8d4 1094 ldr.w r1, [r4, #148] @ 0x94 80048f8: 430b orrs r3, r1 80048fa: 6553 str r3, [r2, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 80048fc: 6863 ldr r3, [r4, #4] 80048fe: f013 0f01 tst.w r3, #1 8004902: d119 bne.n 8004938 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 8004904: 6863 ldr r3, [r4, #4] 8004906: f013 0f02 tst.w r3, #2 800490a: d11e bne.n 800494a if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800490c: 6863 ldr r3, [r4, #4] 800490e: f013 0f04 tst.w r3, #4 8004912: d123 bne.n 800495c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 8004914: 6863 ldr r3, [r4, #4] 8004916: f013 0f08 tst.w r3, #8 800491a: d128 bne.n 800496e if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800491c: 6863 ldr r3, [r4, #4] 800491e: f013 0f10 tst.w r3, #16 8004922: d12d bne.n 8004980 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 8004924: 6863 ldr r3, [r4, #4] 8004926: f013 0f20 tst.w r3, #32 800492a: d132 bne.n 8004992 if (status == HAL_OK) 800492c: b106 cbz r6, 8004930 return HAL_ERROR; 800492e: 2601 movs r6, #1 } 8004930: 4630 mov r0, r6 8004932: bdf8 pop {r3, r4, r5, r6, r7, pc} status = ret; 8004934: 462e mov r6, r5 8004936: e79c b.n 8004872 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8004938: 2100 movs r1, #0 800493a: f104 0008 add.w r0, r4, #8 800493e: f7ff fa01 bl 8003d44 if (ret == HAL_OK) 8004942: 2800 cmp r0, #0 8004944: d0de beq.n 8004904 status = ret; 8004946: 4606 mov r6, r0 8004948: e7dc b.n 8004904 ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800494a: 2101 movs r1, #1 800494c: f104 0008 add.w r0, r4, #8 8004950: f7ff f9f8 bl 8003d44 if (ret == HAL_OK) 8004954: 2800 cmp r0, #0 8004956: d0d9 beq.n 800490c status = ret; 8004958: 4606 mov r6, r0 800495a: e7d7 b.n 800490c ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800495c: 2102 movs r1, #2 800495e: f104 0008 add.w r0, r4, #8 8004962: f7ff f9ef bl 8003d44 if (ret == HAL_OK) 8004966: 2800 cmp r0, #0 8004968: d0d4 beq.n 8004914 status = ret; 800496a: 4606 mov r6, r0 800496c: e7d2 b.n 8004914 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800496e: 2100 movs r1, #0 8004970: f104 0028 add.w r0, r4, #40 @ 0x28 8004974: f7ff fa6a bl 8003e4c if (ret == HAL_OK) 8004978: 2800 cmp r0, #0 800497a: d0cf beq.n 800491c status = ret; 800497c: 4606 mov r6, r0 800497e: e7cd b.n 800491c ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8004980: 2101 movs r1, #1 8004982: f104 0028 add.w r0, r4, #40 @ 0x28 8004986: f7ff fa61 bl 8003e4c if (ret == HAL_OK) 800498a: 2800 cmp r0, #0 800498c: d0ca beq.n 8004924 status = ret; 800498e: 4606 mov r6, r0 8004990: e7c8 b.n 8004924 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8004992: 2102 movs r1, #2 8004994: f104 0028 add.w r0, r4, #40 @ 0x28 8004998: f7ff fa58 bl 8003e4c if (ret == HAL_OK) 800499c: 2800 cmp r0, #0 800499e: d0c5 beq.n 800492c return HAL_ERROR; 80049a0: 2601 movs r6, #1 80049a2: e7c5 b.n 8004930 80049a4: 58024400 .word 0x58024400 080049a8 : { 80049a8: b508 push {r3, lr} return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); 80049aa: f7ff f997 bl 8003cdc 80049ae: 4b05 ldr r3, [pc, #20] @ (80049c4 ) 80049b0: 6a1b ldr r3, [r3, #32] 80049b2: f3c3 1302 ubfx r3, r3, #4, #3 80049b6: 4a04 ldr r2, [pc, #16] @ (80049c8 ) 80049b8: 5cd3 ldrb r3, [r2, r3] 80049ba: f003 031f and.w r3, r3, #31 } 80049be: 40d8 lsrs r0, r3 80049c0: bd08 pop {r3, pc} 80049c2: bf00 nop 80049c4: 58024400 .word 0x58024400 80049c8: 080063b8 .word 0x080063b8 080049cc : { 80049cc: b410 push {r4} pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80049ce: 4b79 ldr r3, [pc, #484] @ (8004bb4 ) 80049d0: 6a9a ldr r2, [r3, #40] @ 0x28 pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 80049d2: 6a9c ldr r4, [r3, #40] @ 0x28 80049d4: f3c4 3c05 ubfx ip, r4, #12, #6 pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 80049d8: 6ad9 ldr r1, [r3, #44] @ 0x2c 80049da: f3c1 1100 ubfx r1, r1, #4, #1 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 80049de: 6bdb ldr r3, [r3, #60] @ 0x3c 80049e0: f3c3 03cc ubfx r3, r3, #3, #13 80049e4: fb01 f303 mul.w r3, r1, r3 if (pll2m != 0U) 80049e8: f414 3f7c tst.w r4, #258048 @ 0x3f000 80049ec: f000 80dd beq.w 8004baa 80049f0: f002 0203 and.w r2, r2, #3 80049f4: ee07 3a90 vmov s15, r3 80049f8: eef8 7a67 vcvt.f32.u32 s15, s15 switch (pllsource) 80049fc: 2a01 cmp r2, #1 80049fe: d04b beq.n 8004a98 8004a00: 2a02 cmp r2, #2 8004a02: f000 8098 beq.w 8004b36 8004a06: 2a00 cmp r2, #0 8004a08: f040 80b2 bne.w 8004b70 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8004a0c: 4b69 ldr r3, [pc, #420] @ (8004bb4 ) 8004a0e: 681b ldr r3, [r3, #0] 8004a10: f013 0f20 tst.w r3, #32 8004a14: d023 beq.n 8004a5e hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8004a16: 4967 ldr r1, [pc, #412] @ (8004bb4 ) 8004a18: 680a ldr r2, [r1, #0] 8004a1a: f3c2 02c1 ubfx r2, r2, #3, #2 8004a1e: 4b66 ldr r3, [pc, #408] @ (8004bb8 ) 8004a20: 40d3 lsrs r3, r2 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8004a22: ee07 3a10 vmov s14, r3 8004a26: eef8 6a47 vcvt.f32.u32 s13, s14 8004a2a: ee07 ca10 vmov s14, ip 8004a2e: eeb8 6a47 vcvt.f32.u32 s12, s14 8004a32: ee86 7a86 vdiv.f32 s14, s13, s12 8004a36: 6b8b ldr r3, [r1, #56] @ 0x38 8004a38: f3c3 0308 ubfx r3, r3, #0, #9 8004a3c: ee06 3a90 vmov s13, r3 8004a40: eef8 6a66 vcvt.f32.u32 s13, s13 8004a44: ed9f 6a5d vldr s12, [pc, #372] @ 8004bbc 8004a48: ee67 7a86 vmul.f32 s15, s15, s12 8004a4c: ee76 7aa7 vadd.f32 s15, s13, s15 8004a50: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004a54: ee77 7aa6 vadd.f32 s15, s15, s13 8004a58: ee27 7a27 vmul.f32 s14, s14, s15 8004a5c: e038 b.n 8004ad0 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8004a5e: ee07 ca10 vmov s14, ip 8004a62: eef8 6a47 vcvt.f32.u32 s13, s14 8004a66: ed9f 6a56 vldr s12, [pc, #344] @ 8004bc0 8004a6a: ee86 7a26 vdiv.f32 s14, s12, s13 8004a6e: 4b51 ldr r3, [pc, #324] @ (8004bb4 ) 8004a70: 6b9b ldr r3, [r3, #56] @ 0x38 8004a72: f3c3 0308 ubfx r3, r3, #0, #9 8004a76: ee06 3a90 vmov s13, r3 8004a7a: eef8 6a66 vcvt.f32.u32 s13, s13 8004a7e: ed9f 6a4f vldr s12, [pc, #316] @ 8004bbc 8004a82: ee67 7a86 vmul.f32 s15, s15, s12 8004a86: ee76 7aa7 vadd.f32 s15, s13, s15 8004a8a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004a8e: ee77 7aa6 vadd.f32 s15, s15, s13 8004a92: ee27 7a27 vmul.f32 s14, s14, s15 8004a96: e01b b.n 8004ad0 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8004a98: ee07 ca10 vmov s14, ip 8004a9c: eef8 6a47 vcvt.f32.u32 s13, s14 8004aa0: ed9f 6a48 vldr s12, [pc, #288] @ 8004bc4 8004aa4: ee86 7a26 vdiv.f32 s14, s12, s13 8004aa8: 4b42 ldr r3, [pc, #264] @ (8004bb4 ) 8004aaa: 6b9b ldr r3, [r3, #56] @ 0x38 8004aac: f3c3 0308 ubfx r3, r3, #0, #9 8004ab0: ee06 3a90 vmov s13, r3 8004ab4: eef8 6a66 vcvt.f32.u32 s13, s13 8004ab8: ed9f 6a40 vldr s12, [pc, #256] @ 8004bbc 8004abc: ee67 7a86 vmul.f32 s15, s15, s12 8004ac0: ee76 7aa7 vadd.f32 s15, s13, s15 8004ac4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004ac8: ee77 7aa6 vadd.f32 s15, s15, s13 8004acc: ee27 7a27 vmul.f32 s14, s14, s15 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 8004ad0: 4a38 ldr r2, [pc, #224] @ (8004bb4 ) 8004ad2: 6b93 ldr r3, [r2, #56] @ 0x38 8004ad4: f3c3 2346 ubfx r3, r3, #9, #7 8004ad8: ee07 3a90 vmov s15, r3 8004adc: eef8 7a67 vcvt.f32.u32 s15, s15 8004ae0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004ae4: ee77 7aa6 vadd.f32 s15, s15, s13 8004ae8: ee87 6a27 vdiv.f32 s12, s14, s15 8004aec: eebc 6ac6 vcvt.u32.f32 s12, s12 8004af0: ed80 6a00 vstr s12, [r0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 8004af4: 6b93 ldr r3, [r2, #56] @ 0x38 8004af6: f3c3 4306 ubfx r3, r3, #16, #7 8004afa: ee07 3a90 vmov s15, r3 8004afe: eef8 7a67 vcvt.f32.u32 s15, s15 8004b02: ee77 7aa6 vadd.f32 s15, s15, s13 8004b06: ee87 6a27 vdiv.f32 s12, s14, s15 8004b0a: eebc 6ac6 vcvt.u32.f32 s12, s12 8004b0e: ed80 6a01 vstr s12, [r0, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 8004b12: 6b93 ldr r3, [r2, #56] @ 0x38 8004b14: f3c3 6306 ubfx r3, r3, #24, #7 8004b18: ee07 3a90 vmov s15, r3 8004b1c: eef8 7a67 vcvt.f32.u32 s15, s15 8004b20: ee77 7aa6 vadd.f32 s15, s15, s13 8004b24: eec7 6a27 vdiv.f32 s13, s14, s15 8004b28: eefc 6ae6 vcvt.u32.f32 s13, s13 8004b2c: edc0 6a02 vstr s13, [r0, #8] } 8004b30: f85d 4b04 ldr.w r4, [sp], #4 8004b34: 4770 bx lr pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8004b36: ee07 ca10 vmov s14, ip 8004b3a: eef8 6a47 vcvt.f32.u32 s13, s14 8004b3e: ed9f 6a22 vldr s12, [pc, #136] @ 8004bc8 8004b42: ee86 7a26 vdiv.f32 s14, s12, s13 8004b46: 4b1b ldr r3, [pc, #108] @ (8004bb4 ) 8004b48: 6b9b ldr r3, [r3, #56] @ 0x38 8004b4a: f3c3 0308 ubfx r3, r3, #0, #9 8004b4e: ee06 3a90 vmov s13, r3 8004b52: eef8 6a66 vcvt.f32.u32 s13, s13 8004b56: ed9f 6a19 vldr s12, [pc, #100] @ 8004bbc 8004b5a: ee67 7a86 vmul.f32 s15, s15, s12 8004b5e: ee76 7aa7 vadd.f32 s15, s13, s15 8004b62: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004b66: ee77 7aa6 vadd.f32 s15, s15, s13 8004b6a: ee27 7a27 vmul.f32 s14, s14, s15 break; 8004b6e: e7af b.n 8004ad0 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8004b70: ee07 ca10 vmov s14, ip 8004b74: eef8 6a47 vcvt.f32.u32 s13, s14 8004b78: ed9f 6a12 vldr s12, [pc, #72] @ 8004bc4 8004b7c: ee86 7a26 vdiv.f32 s14, s12, s13 8004b80: 4b0c ldr r3, [pc, #48] @ (8004bb4 ) 8004b82: 6b9b ldr r3, [r3, #56] @ 0x38 8004b84: f3c3 0308 ubfx r3, r3, #0, #9 8004b88: ee06 3a90 vmov s13, r3 8004b8c: eef8 6a66 vcvt.f32.u32 s13, s13 8004b90: ed9f 6a0a vldr s12, [pc, #40] @ 8004bbc 8004b94: ee67 7a86 vmul.f32 s15, s15, s12 8004b98: ee76 7aa7 vadd.f32 s15, s13, s15 8004b9c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004ba0: ee77 7aa6 vadd.f32 s15, s15, s13 8004ba4: ee27 7a27 vmul.f32 s14, s14, s15 break; 8004ba8: e792 b.n 8004ad0 PLL2_Clocks->PLL2_P_Frequency = 0U; 8004baa: 2300 movs r3, #0 8004bac: 6003 str r3, [r0, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 8004bae: 6043 str r3, [r0, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 8004bb0: 6083 str r3, [r0, #8] } 8004bb2: e7bd b.n 8004b30 8004bb4: 58024400 .word 0x58024400 8004bb8: 03d09000 .word 0x03d09000 8004bbc: 39000000 .word 0x39000000 8004bc0: 4c742400 .word 0x4c742400 8004bc4: 4a742400 .word 0x4a742400 8004bc8: 4bb71b00 .word 0x4bb71b00 08004bcc : { 8004bcc: b410 push {r4} pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8004bce: 4b79 ldr r3, [pc, #484] @ (8004db4 ) 8004bd0: 6a9a ldr r2, [r3, #40] @ 0x28 pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 8004bd2: 6a9c ldr r4, [r3, #40] @ 0x28 8004bd4: f3c4 5c05 ubfx ip, r4, #20, #6 pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 8004bd8: 6ad9 ldr r1, [r3, #44] @ 0x2c 8004bda: f3c1 2100 ubfx r1, r1, #8, #1 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 8004bde: 6c5b ldr r3, [r3, #68] @ 0x44 8004be0: f3c3 03cc ubfx r3, r3, #3, #13 8004be4: fb01 f303 mul.w r3, r1, r3 if (pll3m != 0U) 8004be8: f014 7f7c tst.w r4, #66060288 @ 0x3f00000 8004bec: f000 80dd beq.w 8004daa 8004bf0: f002 0203 and.w r2, r2, #3 8004bf4: ee07 3a90 vmov s15, r3 8004bf8: eef8 7a67 vcvt.f32.u32 s15, s15 switch (pllsource) 8004bfc: 2a01 cmp r2, #1 8004bfe: d04b beq.n 8004c98 8004c00: 2a02 cmp r2, #2 8004c02: f000 8098 beq.w 8004d36 8004c06: 2a00 cmp r2, #0 8004c08: f040 80b2 bne.w 8004d70 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8004c0c: 4b69 ldr r3, [pc, #420] @ (8004db4 ) 8004c0e: 681b ldr r3, [r3, #0] 8004c10: f013 0f20 tst.w r3, #32 8004c14: d023 beq.n 8004c5e hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8004c16: 4967 ldr r1, [pc, #412] @ (8004db4 ) 8004c18: 680a ldr r2, [r1, #0] 8004c1a: f3c2 02c1 ubfx r2, r2, #3, #2 8004c1e: 4b66 ldr r3, [pc, #408] @ (8004db8 ) 8004c20: 40d3 lsrs r3, r2 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8004c22: ee07 3a10 vmov s14, r3 8004c26: eef8 6a47 vcvt.f32.u32 s13, s14 8004c2a: ee07 ca10 vmov s14, ip 8004c2e: eeb8 6a47 vcvt.f32.u32 s12, s14 8004c32: ee86 7a86 vdiv.f32 s14, s13, s12 8004c36: 6c0b ldr r3, [r1, #64] @ 0x40 8004c38: f3c3 0308 ubfx r3, r3, #0, #9 8004c3c: ee06 3a90 vmov s13, r3 8004c40: eef8 6a66 vcvt.f32.u32 s13, s13 8004c44: ed9f 6a5d vldr s12, [pc, #372] @ 8004dbc 8004c48: ee67 7a86 vmul.f32 s15, s15, s12 8004c4c: ee76 7aa7 vadd.f32 s15, s13, s15 8004c50: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004c54: ee77 7aa6 vadd.f32 s15, s15, s13 8004c58: ee27 7a27 vmul.f32 s14, s14, s15 8004c5c: e038 b.n 8004cd0 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8004c5e: ee07 ca10 vmov s14, ip 8004c62: eef8 6a47 vcvt.f32.u32 s13, s14 8004c66: ed9f 6a56 vldr s12, [pc, #344] @ 8004dc0 8004c6a: ee86 7a26 vdiv.f32 s14, s12, s13 8004c6e: 4b51 ldr r3, [pc, #324] @ (8004db4 ) 8004c70: 6c1b ldr r3, [r3, #64] @ 0x40 8004c72: f3c3 0308 ubfx r3, r3, #0, #9 8004c76: ee06 3a90 vmov s13, r3 8004c7a: eef8 6a66 vcvt.f32.u32 s13, s13 8004c7e: ed9f 6a4f vldr s12, [pc, #316] @ 8004dbc 8004c82: ee67 7a86 vmul.f32 s15, s15, s12 8004c86: ee76 7aa7 vadd.f32 s15, s13, s15 8004c8a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004c8e: ee77 7aa6 vadd.f32 s15, s15, s13 8004c92: ee27 7a27 vmul.f32 s14, s14, s15 8004c96: e01b b.n 8004cd0 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8004c98: ee07 ca10 vmov s14, ip 8004c9c: eef8 6a47 vcvt.f32.u32 s13, s14 8004ca0: ed9f 6a48 vldr s12, [pc, #288] @ 8004dc4 8004ca4: ee86 7a26 vdiv.f32 s14, s12, s13 8004ca8: 4b42 ldr r3, [pc, #264] @ (8004db4 ) 8004caa: 6c1b ldr r3, [r3, #64] @ 0x40 8004cac: f3c3 0308 ubfx r3, r3, #0, #9 8004cb0: ee06 3a90 vmov s13, r3 8004cb4: eef8 6a66 vcvt.f32.u32 s13, s13 8004cb8: ed9f 6a40 vldr s12, [pc, #256] @ 8004dbc 8004cbc: ee67 7a86 vmul.f32 s15, s15, s12 8004cc0: ee76 7aa7 vadd.f32 s15, s13, s15 8004cc4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004cc8: ee77 7aa6 vadd.f32 s15, s15, s13 8004ccc: ee27 7a27 vmul.f32 s14, s14, s15 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 8004cd0: 4a38 ldr r2, [pc, #224] @ (8004db4 ) 8004cd2: 6c13 ldr r3, [r2, #64] @ 0x40 8004cd4: f3c3 2346 ubfx r3, r3, #9, #7 8004cd8: ee07 3a90 vmov s15, r3 8004cdc: eef8 7a67 vcvt.f32.u32 s15, s15 8004ce0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004ce4: ee77 7aa6 vadd.f32 s15, s15, s13 8004ce8: ee87 6a27 vdiv.f32 s12, s14, s15 8004cec: eebc 6ac6 vcvt.u32.f32 s12, s12 8004cf0: ed80 6a00 vstr s12, [r0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 8004cf4: 6c13 ldr r3, [r2, #64] @ 0x40 8004cf6: f3c3 4306 ubfx r3, r3, #16, #7 8004cfa: ee07 3a90 vmov s15, r3 8004cfe: eef8 7a67 vcvt.f32.u32 s15, s15 8004d02: ee77 7aa6 vadd.f32 s15, s15, s13 8004d06: ee87 6a27 vdiv.f32 s12, s14, s15 8004d0a: eebc 6ac6 vcvt.u32.f32 s12, s12 8004d0e: ed80 6a01 vstr s12, [r0, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 8004d12: 6c13 ldr r3, [r2, #64] @ 0x40 8004d14: f3c3 6306 ubfx r3, r3, #24, #7 8004d18: ee07 3a90 vmov s15, r3 8004d1c: eef8 7a67 vcvt.f32.u32 s15, s15 8004d20: ee77 7aa6 vadd.f32 s15, s15, s13 8004d24: eec7 6a27 vdiv.f32 s13, s14, s15 8004d28: eefc 6ae6 vcvt.u32.f32 s13, s13 8004d2c: edc0 6a02 vstr s13, [r0, #8] } 8004d30: f85d 4b04 ldr.w r4, [sp], #4 8004d34: 4770 bx lr pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8004d36: ee07 ca10 vmov s14, ip 8004d3a: eef8 6a47 vcvt.f32.u32 s13, s14 8004d3e: ed9f 6a22 vldr s12, [pc, #136] @ 8004dc8 8004d42: ee86 7a26 vdiv.f32 s14, s12, s13 8004d46: 4b1b ldr r3, [pc, #108] @ (8004db4 ) 8004d48: 6c1b ldr r3, [r3, #64] @ 0x40 8004d4a: f3c3 0308 ubfx r3, r3, #0, #9 8004d4e: ee06 3a90 vmov s13, r3 8004d52: eef8 6a66 vcvt.f32.u32 s13, s13 8004d56: ed9f 6a19 vldr s12, [pc, #100] @ 8004dbc 8004d5a: ee67 7a86 vmul.f32 s15, s15, s12 8004d5e: ee76 7aa7 vadd.f32 s15, s13, s15 8004d62: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004d66: ee77 7aa6 vadd.f32 s15, s15, s13 8004d6a: ee27 7a27 vmul.f32 s14, s14, s15 break; 8004d6e: e7af b.n 8004cd0 pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8004d70: ee07 ca10 vmov s14, ip 8004d74: eef8 6a47 vcvt.f32.u32 s13, s14 8004d78: ed9f 6a12 vldr s12, [pc, #72] @ 8004dc4 8004d7c: ee86 7a26 vdiv.f32 s14, s12, s13 8004d80: 4b0c ldr r3, [pc, #48] @ (8004db4 ) 8004d82: 6c1b ldr r3, [r3, #64] @ 0x40 8004d84: f3c3 0308 ubfx r3, r3, #0, #9 8004d88: ee06 3a90 vmov s13, r3 8004d8c: eef8 6a66 vcvt.f32.u32 s13, s13 8004d90: ed9f 6a0a vldr s12, [pc, #40] @ 8004dbc 8004d94: ee67 7a86 vmul.f32 s15, s15, s12 8004d98: ee76 7aa7 vadd.f32 s15, s13, s15 8004d9c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004da0: ee77 7aa6 vadd.f32 s15, s15, s13 8004da4: ee27 7a27 vmul.f32 s14, s14, s15 break; 8004da8: e792 b.n 8004cd0 PLL3_Clocks->PLL3_P_Frequency = 0U; 8004daa: 2300 movs r3, #0 8004dac: 6003 str r3, [r0, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 8004dae: 6043 str r3, [r0, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 8004db0: 6083 str r3, [r0, #8] } 8004db2: e7bd b.n 8004d30 8004db4: 58024400 .word 0x58024400 8004db8: 03d09000 .word 0x03d09000 8004dbc: 39000000 .word 0x39000000 8004dc0: 4c742400 .word 0x4c742400 8004dc4: 4a742400 .word 0x4a742400 8004dc8: 4bb71b00 .word 0x4bb71b00 08004dcc : { 8004dcc: b410 push {r4} pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8004dce: 4b79 ldr r3, [pc, #484] @ (8004fb4 ) 8004dd0: 6a9a ldr r2, [r3, #40] @ 0x28 pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 8004dd2: 6a9c ldr r4, [r3, #40] @ 0x28 8004dd4: f3c4 1c05 ubfx ip, r4, #4, #6 pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 8004dd8: 6ad9 ldr r1, [r3, #44] @ 0x2c 8004dda: f001 0101 and.w r1, r1, #1 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 8004dde: 6b5b ldr r3, [r3, #52] @ 0x34 8004de0: f3c3 03cc ubfx r3, r3, #3, #13 8004de4: fb01 f303 mul.w r3, r1, r3 if (pll1m != 0U) 8004de8: f414 7f7c tst.w r4, #1008 @ 0x3f0 8004dec: f000 80dd beq.w 8004faa 8004df0: f002 0203 and.w r2, r2, #3 8004df4: ee07 3a90 vmov s15, r3 8004df8: eef8 7a67 vcvt.f32.u32 s15, s15 switch (pllsource) 8004dfc: 2a01 cmp r2, #1 8004dfe: d04b beq.n 8004e98 8004e00: 2a02 cmp r2, #2 8004e02: f000 8098 beq.w 8004f36 8004e06: 2a00 cmp r2, #0 8004e08: f040 80b2 bne.w 8004f70 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8004e0c: 4b69 ldr r3, [pc, #420] @ (8004fb4 ) 8004e0e: 681b ldr r3, [r3, #0] 8004e10: f013 0f20 tst.w r3, #32 8004e14: d023 beq.n 8004e5e hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8004e16: 4967 ldr r1, [pc, #412] @ (8004fb4 ) 8004e18: 680a ldr r2, [r1, #0] 8004e1a: f3c2 02c1 ubfx r2, r2, #3, #2 8004e1e: 4b66 ldr r3, [pc, #408] @ (8004fb8 ) 8004e20: 40d3 lsrs r3, r2 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8004e22: ee07 3a10 vmov s14, r3 8004e26: eef8 6a47 vcvt.f32.u32 s13, s14 8004e2a: ee07 ca10 vmov s14, ip 8004e2e: eeb8 6a47 vcvt.f32.u32 s12, s14 8004e32: ee86 7a86 vdiv.f32 s14, s13, s12 8004e36: 6b0b ldr r3, [r1, #48] @ 0x30 8004e38: f3c3 0308 ubfx r3, r3, #0, #9 8004e3c: ee06 3a90 vmov s13, r3 8004e40: eef8 6a66 vcvt.f32.u32 s13, s13 8004e44: ed9f 6a5d vldr s12, [pc, #372] @ 8004fbc 8004e48: ee67 7a86 vmul.f32 s15, s15, s12 8004e4c: ee76 7aa7 vadd.f32 s15, s13, s15 8004e50: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004e54: ee77 7aa6 vadd.f32 s15, s15, s13 8004e58: ee27 7a27 vmul.f32 s14, s14, s15 8004e5c: e038 b.n 8004ed0 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8004e5e: ee07 ca10 vmov s14, ip 8004e62: eef8 6a47 vcvt.f32.u32 s13, s14 8004e66: ed9f 6a56 vldr s12, [pc, #344] @ 8004fc0 8004e6a: ee86 7a26 vdiv.f32 s14, s12, s13 8004e6e: 4b51 ldr r3, [pc, #324] @ (8004fb4 ) 8004e70: 6b1b ldr r3, [r3, #48] @ 0x30 8004e72: f3c3 0308 ubfx r3, r3, #0, #9 8004e76: ee06 3a90 vmov s13, r3 8004e7a: eef8 6a66 vcvt.f32.u32 s13, s13 8004e7e: ed9f 6a4f vldr s12, [pc, #316] @ 8004fbc 8004e82: ee67 7a86 vmul.f32 s15, s15, s12 8004e86: ee76 7aa7 vadd.f32 s15, s13, s15 8004e8a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004e8e: ee77 7aa6 vadd.f32 s15, s15, s13 8004e92: ee27 7a27 vmul.f32 s14, s14, s15 8004e96: e01b b.n 8004ed0 pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8004e98: ee07 ca10 vmov s14, ip 8004e9c: eef8 6a47 vcvt.f32.u32 s13, s14 8004ea0: ed9f 6a48 vldr s12, [pc, #288] @ 8004fc4 8004ea4: ee86 7a26 vdiv.f32 s14, s12, s13 8004ea8: 4b42 ldr r3, [pc, #264] @ (8004fb4 ) 8004eaa: 6b1b ldr r3, [r3, #48] @ 0x30 8004eac: f3c3 0308 ubfx r3, r3, #0, #9 8004eb0: ee06 3a90 vmov s13, r3 8004eb4: eef8 6a66 vcvt.f32.u32 s13, s13 8004eb8: ed9f 6a40 vldr s12, [pc, #256] @ 8004fbc 8004ebc: ee67 7a86 vmul.f32 s15, s15, s12 8004ec0: ee76 7aa7 vadd.f32 s15, s13, s15 8004ec4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004ec8: ee77 7aa6 vadd.f32 s15, s15, s13 8004ecc: ee27 7a27 vmul.f32 s14, s14, s15 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 8004ed0: 4a38 ldr r2, [pc, #224] @ (8004fb4 ) 8004ed2: 6b13 ldr r3, [r2, #48] @ 0x30 8004ed4: f3c3 2346 ubfx r3, r3, #9, #7 8004ed8: ee07 3a90 vmov s15, r3 8004edc: eef8 7a67 vcvt.f32.u32 s15, s15 8004ee0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004ee4: ee77 7aa6 vadd.f32 s15, s15, s13 8004ee8: ee87 6a27 vdiv.f32 s12, s14, s15 8004eec: eebc 6ac6 vcvt.u32.f32 s12, s12 8004ef0: ed80 6a00 vstr s12, [r0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 8004ef4: 6b13 ldr r3, [r2, #48] @ 0x30 8004ef6: f3c3 4306 ubfx r3, r3, #16, #7 8004efa: ee07 3a90 vmov s15, r3 8004efe: eef8 7a67 vcvt.f32.u32 s15, s15 8004f02: ee77 7aa6 vadd.f32 s15, s15, s13 8004f06: ee87 6a27 vdiv.f32 s12, s14, s15 8004f0a: eebc 6ac6 vcvt.u32.f32 s12, s12 8004f0e: ed80 6a01 vstr s12, [r0, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 8004f12: 6b13 ldr r3, [r2, #48] @ 0x30 8004f14: f3c3 6306 ubfx r3, r3, #24, #7 8004f18: ee07 3a90 vmov s15, r3 8004f1c: eef8 7a67 vcvt.f32.u32 s15, s15 8004f20: ee77 7aa6 vadd.f32 s15, s15, s13 8004f24: eec7 6a27 vdiv.f32 s13, s14, s15 8004f28: eefc 6ae6 vcvt.u32.f32 s13, s13 8004f2c: edc0 6a02 vstr s13, [r0, #8] } 8004f30: f85d 4b04 ldr.w r4, [sp], #4 8004f34: 4770 bx lr pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8004f36: ee07 ca10 vmov s14, ip 8004f3a: eef8 6a47 vcvt.f32.u32 s13, s14 8004f3e: ed9f 6a22 vldr s12, [pc, #136] @ 8004fc8 8004f42: ee86 7a26 vdiv.f32 s14, s12, s13 8004f46: 4b1b ldr r3, [pc, #108] @ (8004fb4 ) 8004f48: 6b1b ldr r3, [r3, #48] @ 0x30 8004f4a: f3c3 0308 ubfx r3, r3, #0, #9 8004f4e: ee06 3a90 vmov s13, r3 8004f52: eef8 6a66 vcvt.f32.u32 s13, s13 8004f56: ed9f 6a19 vldr s12, [pc, #100] @ 8004fbc 8004f5a: ee67 7a86 vmul.f32 s15, s15, s12 8004f5e: ee76 7aa7 vadd.f32 s15, s13, s15 8004f62: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004f66: ee77 7aa6 vadd.f32 s15, s15, s13 8004f6a: ee27 7a27 vmul.f32 s14, s14, s15 break; 8004f6e: e7af b.n 8004ed0 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8004f70: ee07 ca10 vmov s14, ip 8004f74: eef8 6a47 vcvt.f32.u32 s13, s14 8004f78: ed9f 6a11 vldr s12, [pc, #68] @ 8004fc0 8004f7c: ee86 7a26 vdiv.f32 s14, s12, s13 8004f80: 4b0c ldr r3, [pc, #48] @ (8004fb4 ) 8004f82: 6b1b ldr r3, [r3, #48] @ 0x30 8004f84: f3c3 0308 ubfx r3, r3, #0, #9 8004f88: ee06 3a90 vmov s13, r3 8004f8c: eef8 6a66 vcvt.f32.u32 s13, s13 8004f90: ed9f 6a0a vldr s12, [pc, #40] @ 8004fbc 8004f94: ee67 7a86 vmul.f32 s15, s15, s12 8004f98: ee76 7aa7 vadd.f32 s15, s13, s15 8004f9c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8004fa0: ee77 7aa6 vadd.f32 s15, s15, s13 8004fa4: ee27 7a27 vmul.f32 s14, s14, s15 break; 8004fa8: e792 b.n 8004ed0 PLL1_Clocks->PLL1_P_Frequency = 0U; 8004faa: 2300 movs r3, #0 8004fac: 6003 str r3, [r0, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 8004fae: 6043 str r3, [r0, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 8004fb0: 6083 str r3, [r0, #8] } 8004fb2: e7bd b.n 8004f30 8004fb4: 58024400 .word 0x58024400 8004fb8: 03d09000 .word 0x03d09000 8004fbc: 39000000 .word 0x39000000 8004fc0: 4c742400 .word 0x4c742400 8004fc4: 4a742400 .word 0x4a742400 8004fc8: 4bb71b00 .word 0x4bb71b00 08004fcc : { 8004fcc: b500 push {lr} 8004fce: b08b sub sp, #44 @ 0x2c if (PeriphClk == RCC_PERIPHCLK_SAI1) 8004fd0: f5a0 7380 sub.w r3, r0, #256 @ 0x100 8004fd4: 430b orrs r3, r1 8004fd6: d028 beq.n 800502a else if (PeriphClk == RCC_PERIPHCLK_SAI2A) 8004fd8: f5a0 7300 sub.w r3, r0, #512 @ 0x200 8004fdc: 430b orrs r3, r1 8004fde: d077 beq.n 80050d0 else if (PeriphClk == RCC_PERIPHCLK_SAI2B) 8004fe0: f5a0 6380 sub.w r3, r0, #1024 @ 0x400 8004fe4: 430b orrs r3, r1 8004fe6: f000 80cb beq.w 8005180 else if (PeriphClk == RCC_PERIPHCLK_SPI123) 8004fea: f5a0 5380 sub.w r3, r0, #4096 @ 0x1000 8004fee: 430b orrs r3, r1 8004ff0: f000 8123 beq.w 800523a else if (PeriphClk == RCC_PERIPHCLK_SPI45) 8004ff4: f5a0 5300 sub.w r3, r0, #8192 @ 0x2000 8004ff8: 430b orrs r3, r1 8004ffa: f000 8183 beq.w 8005304 else if (PeriphClk == RCC_PERIPHCLK_ADC) 8004ffe: f5a0 2300 sub.w r3, r0, #524288 @ 0x80000 8005002: 430b orrs r3, r1 8005004: f000 81cc beq.w 80053a0 else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 8005008: f5a0 3380 sub.w r3, r0, #65536 @ 0x10000 800500c: 430b orrs r3, r1 800500e: f000 820f beq.w 8005430 else if (PeriphClk == RCC_PERIPHCLK_SPI6) 8005012: f5a0 4380 sub.w r3, r0, #16384 @ 0x4000 8005016: 430b orrs r3, r1 8005018: f000 8228 beq.w 800546c else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800501c: f5a0 4000 sub.w r0, r0, #32768 @ 0x8000 8005020: 4308 orrs r0, r1 8005022: f000 827d beq.w 8005520 frequency = 0; 8005026: 2000 movs r0, #0 8005028: e00c b.n 8005044 saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800502a: 4b94 ldr r3, [pc, #592] @ (800527c ) 800502c: 6d1b ldr r3, [r3, #80] @ 0x50 800502e: f003 0307 and.w r3, r3, #7 switch (saiclocksource) 8005032: 2b04 cmp r3, #4 8005034: f200 829e bhi.w 8005574 8005038: e8df f003 tbb [pc, r3] 800503c: 031b1107 .word 0x031b1107 8005040: 25 .byte 0x25 8005041: 00 .byte 0x00 8005042: 488f ldr r0, [pc, #572] @ (8005280 ) } 8005044: b00b add sp, #44 @ 0x2c 8005046: f85d fb04 ldr.w pc, [sp], #4 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800504a: 4b8c ldr r3, [pc, #560] @ (800527c ) 800504c: 6818 ldr r0, [r3, #0] 800504e: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000 8005052: d0f7 beq.n 8005044 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8005054: a807 add r0, sp, #28 8005056: f7ff feb9 bl 8004dcc frequency = pll1_clocks.PLL1_Q_Frequency; 800505a: 9808 ldr r0, [sp, #32] 800505c: e7f2 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800505e: 4b87 ldr r3, [pc, #540] @ (800527c ) 8005060: 6818 ldr r0, [r3, #0] 8005062: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 8005066: d0ed beq.n 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8005068: a804 add r0, sp, #16 800506a: f7ff fcaf bl 80049cc frequency = pll2_clocks.PLL2_P_Frequency; 800506e: 9804 ldr r0, [sp, #16] 8005070: e7e8 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8005072: 4b82 ldr r3, [pc, #520] @ (800527c ) 8005074: 6818 ldr r0, [r3, #0] 8005076: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 800507a: d0e3 beq.n 8005044 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800507c: a801 add r0, sp, #4 800507e: f7ff fda5 bl 8004bcc frequency = pll3_clocks.PLL3_P_Frequency; 8005082: 9801 ldr r0, [sp, #4] 8005084: e7de b.n 8005044 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8005086: 4a7d ldr r2, [pc, #500] @ (800527c ) 8005088: 6cd3 ldr r3, [r2, #76] @ 0x4c 800508a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800508e: 6812 ldr r2, [r2, #0] 8005090: f012 0f04 tst.w r2, #4 8005094: d007 beq.n 80050a6 8005096: b933 cbnz r3, 80050a6 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8005098: 4b78 ldr r3, [pc, #480] @ (800527c ) 800509a: 681b ldr r3, [r3, #0] 800509c: f3c3 03c1 ubfx r3, r3, #3, #2 80050a0: 4878 ldr r0, [pc, #480] @ (8005284 ) 80050a2: 40d8 lsrs r0, r3 80050a4: e7ce b.n 8005044 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 80050a6: 4a75 ldr r2, [pc, #468] @ (800527c ) 80050a8: 6812 ldr r2, [r2, #0] 80050aa: f412 7f80 tst.w r2, #256 @ 0x100 80050ae: d003 beq.n 80050b8 80050b0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80050b4: f000 8260 beq.w 8005578 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 80050b8: 4a70 ldr r2, [pc, #448] @ (800527c ) 80050ba: 6812 ldr r2, [r2, #0] 80050bc: f412 3f00 tst.w r2, #131072 @ 0x20000 80050c0: f000 825c beq.w 800557c 80050c4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80050c8: f000 825a beq.w 8005580 frequency = 0; 80050cc: 2000 movs r0, #0 80050ce: e7b9 b.n 8005044 saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE(); 80050d0: 4b6a ldr r3, [pc, #424] @ (800527c ) 80050d2: 6d1b ldr r3, [r3, #80] @ 0x50 80050d4: f403 73e0 and.w r3, r3, #448 @ 0x1c0 switch (saiclocksource) 80050d8: 2b80 cmp r3, #128 @ 0x80 80050da: d031 beq.n 8005140 80050dc: d915 bls.n 800510a 80050de: 2bc0 cmp r3, #192 @ 0xc0 80050e0: f000 8250 beq.w 8005584 80050e4: f5b3 7f80 cmp.w r3, #256 @ 0x100 80050e8: d11e bne.n 8005128 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 80050ea: 4a64 ldr r2, [pc, #400] @ (800527c ) 80050ec: 6cd3 ldr r3, [r2, #76] @ 0x4c 80050ee: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 80050f2: 6812 ldr r2, [r2, #0] 80050f4: f012 0f04 tst.w r2, #4 80050f8: d02d beq.n 8005156 80050fa: bb63 cbnz r3, 8005156 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80050fc: 4b5f ldr r3, [pc, #380] @ (800527c ) 80050fe: 681b ldr r3, [r3, #0] 8005100: f3c3 03c1 ubfx r3, r3, #3, #2 8005104: 485f ldr r0, [pc, #380] @ (8005284 ) 8005106: 40d8 lsrs r0, r3 8005108: e79c b.n 8005044 switch (saiclocksource) 800510a: b17b cbz r3, 800512c 800510c: 2b40 cmp r3, #64 @ 0x40 800510e: d109 bne.n 8005124 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8005110: 4b5a ldr r3, [pc, #360] @ (800527c ) 8005112: 6818 ldr r0, [r3, #0] 8005114: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 8005118: d094 beq.n 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800511a: a804 add r0, sp, #16 800511c: f7ff fc56 bl 80049cc frequency = pll2_clocks.PLL2_P_Frequency; 8005120: 9804 ldr r0, [sp, #16] 8005122: e78f b.n 8005044 frequency = 0; 8005124: 2000 movs r0, #0 8005126: e78d b.n 8005044 8005128: 2000 movs r0, #0 800512a: e78b b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800512c: 4b53 ldr r3, [pc, #332] @ (800527c ) 800512e: 6818 ldr r0, [r3, #0] 8005130: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000 8005134: d086 beq.n 8005044 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8005136: a807 add r0, sp, #28 8005138: f7ff fe48 bl 8004dcc frequency = pll1_clocks.PLL1_Q_Frequency; 800513c: 9808 ldr r0, [sp, #32] 800513e: e781 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8005140: 4b4e ldr r3, [pc, #312] @ (800527c ) 8005142: 6818 ldr r0, [r3, #0] 8005144: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 8005148: f43f af7c beq.w 8005044 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800514c: a801 add r0, sp, #4 800514e: f7ff fd3d bl 8004bcc frequency = pll3_clocks.PLL3_P_Frequency; 8005152: 9801 ldr r0, [sp, #4] 8005154: e776 b.n 8005044 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8005156: 4a49 ldr r2, [pc, #292] @ (800527c ) 8005158: 6812 ldr r2, [r2, #0] 800515a: f412 7f80 tst.w r2, #256 @ 0x100 800515e: d003 beq.n 8005168 8005160: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005164: f000 8210 beq.w 8005588 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8005168: 4a44 ldr r2, [pc, #272] @ (800527c ) 800516a: 6812 ldr r2, [r2, #0] 800516c: f412 3f00 tst.w r2, #131072 @ 0x20000 8005170: f000 820c beq.w 800558c 8005174: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005178: f000 820a beq.w 8005590 frequency = 0; 800517c: 2000 movs r0, #0 800517e: e761 b.n 8005044 saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE(); 8005180: 4b3e ldr r3, [pc, #248] @ (800527c ) 8005182: 6d1b ldr r3, [r3, #80] @ 0x50 8005184: f403 6360 and.w r3, r3, #3584 @ 0xe00 switch (saiclocksource) 8005188: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800518c: d035 beq.n 80051fa 800518e: d916 bls.n 80051be 8005190: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 8005194: f000 81fe beq.w 8005594 8005198: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800519c: d120 bne.n 80051e0 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800519e: 4a37 ldr r2, [pc, #220] @ (800527c ) 80051a0: 6cd3 ldr r3, [r2, #76] @ 0x4c 80051a2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 80051a6: 6812 ldr r2, [r2, #0] 80051a8: f012 0f04 tst.w r2, #4 80051ac: d030 beq.n 8005210 80051ae: bb7b cbnz r3, 8005210 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80051b0: 4b32 ldr r3, [pc, #200] @ (800527c ) 80051b2: 681b ldr r3, [r3, #0] 80051b4: f3c3 03c1 ubfx r3, r3, #3, #2 80051b8: 4832 ldr r0, [pc, #200] @ (8005284 ) 80051ba: 40d8 lsrs r0, r3 80051bc: e742 b.n 8005044 switch (saiclocksource) 80051be: b18b cbz r3, 80051e4 80051c0: f5b3 7f00 cmp.w r3, #512 @ 0x200 80051c4: d10a bne.n 80051dc if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80051c6: 4b2d ldr r3, [pc, #180] @ (800527c ) 80051c8: 6818 ldr r0, [r3, #0] 80051ca: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 80051ce: f43f af39 beq.w 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80051d2: a804 add r0, sp, #16 80051d4: f7ff fbfa bl 80049cc frequency = pll2_clocks.PLL2_P_Frequency; 80051d8: 9804 ldr r0, [sp, #16] 80051da: e733 b.n 8005044 frequency = 0; 80051dc: 2000 movs r0, #0 80051de: e731 b.n 8005044 80051e0: 2000 movs r0, #0 80051e2: e72f b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80051e4: 4b25 ldr r3, [pc, #148] @ (800527c ) 80051e6: 6818 ldr r0, [r3, #0] 80051e8: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000 80051ec: f43f af2a beq.w 8005044 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 80051f0: a807 add r0, sp, #28 80051f2: f7ff fdeb bl 8004dcc frequency = pll1_clocks.PLL1_Q_Frequency; 80051f6: 9808 ldr r0, [sp, #32] 80051f8: e724 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80051fa: 4b20 ldr r3, [pc, #128] @ (800527c ) 80051fc: 6818 ldr r0, [r3, #0] 80051fe: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 8005202: f43f af1f beq.w 8005044 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8005206: a801 add r0, sp, #4 8005208: f7ff fce0 bl 8004bcc frequency = pll3_clocks.PLL3_P_Frequency; 800520c: 9801 ldr r0, [sp, #4] 800520e: e719 b.n 8005044 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8005210: 4a1a ldr r2, [pc, #104] @ (800527c ) 8005212: 6812 ldr r2, [r2, #0] 8005214: f412 7f80 tst.w r2, #256 @ 0x100 8005218: d003 beq.n 8005222 800521a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800521e: f000 81bb beq.w 8005598 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8005222: 4a16 ldr r2, [pc, #88] @ (800527c ) 8005224: 6812 ldr r2, [r2, #0] 8005226: f412 3f00 tst.w r2, #131072 @ 0x20000 800522a: f000 81b7 beq.w 800559c 800522e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005232: f000 81b5 beq.w 80055a0 frequency = 0; 8005236: 2000 movs r0, #0 8005238: e704 b.n 8005044 srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800523a: 4b10 ldr r3, [pc, #64] @ (800527c ) 800523c: 6d1b ldr r3, [r3, #80] @ 0x50 800523e: f403 43e0 and.w r3, r3, #28672 @ 0x7000 switch (srcclk) 8005242: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8005246: d03d beq.n 80052c4 8005248: d91e bls.n 8005288 800524a: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800524e: f000 81a9 beq.w 80055a4 8005252: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8005256: d128 bne.n 80052aa ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8005258: 4a08 ldr r2, [pc, #32] @ (800527c ) 800525a: 6cd3 ldr r3, [r2, #76] @ 0x4c 800525c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8005260: 6812 ldr r2, [r2, #0] 8005262: f012 0f04 tst.w r2, #4 8005266: d038 beq.n 80052da 8005268: 2b00 cmp r3, #0 800526a: d136 bne.n 80052da frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800526c: 4b03 ldr r3, [pc, #12] @ (800527c ) 800526e: 681b ldr r3, [r3, #0] 8005270: f3c3 03c1 ubfx r3, r3, #3, #2 8005274: 4803 ldr r0, [pc, #12] @ (8005284 ) 8005276: 40d8 lsrs r0, r3 8005278: e6e4 b.n 8005044 800527a: bf00 nop 800527c: 58024400 .word 0x58024400 8005280: 00bb8000 .word 0x00bb8000 8005284: 03d09000 .word 0x03d09000 switch (srcclk) 8005288: b18b cbz r3, 80052ae 800528a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800528e: d10a bne.n 80052a6 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8005290: 4b9f ldr r3, [pc, #636] @ (8005510 ) 8005292: 6818 ldr r0, [r3, #0] 8005294: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 8005298: f43f aed4 beq.w 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800529c: a804 add r0, sp, #16 800529e: f7ff fb95 bl 80049cc frequency = pll2_clocks.PLL2_P_Frequency; 80052a2: 9804 ldr r0, [sp, #16] 80052a4: e6ce b.n 8005044 frequency = 0; 80052a6: 2000 movs r0, #0 80052a8: e6cc b.n 8005044 80052aa: 2000 movs r0, #0 80052ac: e6ca b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80052ae: 4b98 ldr r3, [pc, #608] @ (8005510 ) 80052b0: 6818 ldr r0, [r3, #0] 80052b2: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000 80052b6: f43f aec5 beq.w 8005044 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 80052ba: a807 add r0, sp, #28 80052bc: f7ff fd86 bl 8004dcc frequency = pll1_clocks.PLL1_Q_Frequency; 80052c0: 9808 ldr r0, [sp, #32] 80052c2: e6bf b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80052c4: 4b92 ldr r3, [pc, #584] @ (8005510 ) 80052c6: 6818 ldr r0, [r3, #0] 80052c8: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 80052cc: f43f aeba beq.w 8005044 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80052d0: a801 add r0, sp, #4 80052d2: f7ff fc7b bl 8004bcc frequency = pll3_clocks.PLL3_P_Frequency; 80052d6: 9801 ldr r0, [sp, #4] 80052d8: e6b4 b.n 8005044 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 80052da: 4a8d ldr r2, [pc, #564] @ (8005510 ) 80052dc: 6812 ldr r2, [r2, #0] 80052de: f412 7f80 tst.w r2, #256 @ 0x100 80052e2: d003 beq.n 80052ec 80052e4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80052e8: f000 815e beq.w 80055a8 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 80052ec: 4a88 ldr r2, [pc, #544] @ (8005510 ) 80052ee: 6812 ldr r2, [r2, #0] 80052f0: f412 3f00 tst.w r2, #131072 @ 0x20000 80052f4: f000 815a beq.w 80055ac 80052f8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80052fc: f000 8158 beq.w 80055b0 frequency = 0; 8005300: 2000 movs r0, #0 8005302: e69f b.n 8005044 srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 8005304: 4b82 ldr r3, [pc, #520] @ (8005510 ) 8005306: 6d1b ldr r3, [r3, #80] @ 0x50 8005308: f403 23e0 and.w r3, r3, #458752 @ 0x70000 switch (srcclk) 800530c: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8005310: d032 beq.n 8005378 8005312: d80b bhi.n 800532c 8005314: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8005318: d018 beq.n 800534c 800531a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800531e: d020 beq.n 8005362 8005320: b913 cbnz r3, 8005328 frequency = HAL_RCC_GetPCLK1Freq(); 8005322: f7fe fcfd bl 8003d20 break; 8005326: e68d b.n 8005044 switch (srcclk) 8005328: 2000 movs r0, #0 800532a: e68b b.n 8005044 800532c: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8005330: d02e beq.n 8005390 8005332: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8005336: d107 bne.n 8005348 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8005338: 4b75 ldr r3, [pc, #468] @ (8005510 ) 800533a: 6818 ldr r0, [r3, #0] 800533c: f410 3000 ands.w r0, r0, #131072 @ 0x20000 8005340: f43f ae80 beq.w 8005044 frequency = HSE_VALUE; 8005344: 4873 ldr r0, [pc, #460] @ (8005514 ) 8005346: e67d b.n 8005044 switch (srcclk) 8005348: 2000 movs r0, #0 800534a: e67b b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800534c: 4b70 ldr r3, [pc, #448] @ (8005510 ) 800534e: 6818 ldr r0, [r3, #0] 8005350: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 8005354: f43f ae76 beq.w 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8005358: a804 add r0, sp, #16 800535a: f7ff fb37 bl 80049cc frequency = pll2_clocks.PLL2_Q_Frequency; 800535e: 9805 ldr r0, [sp, #20] 8005360: e670 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8005362: 4b6b ldr r3, [pc, #428] @ (8005510 ) 8005364: 6818 ldr r0, [r3, #0] 8005366: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 800536a: f43f ae6b beq.w 8005044 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800536e: a801 add r0, sp, #4 8005370: f7ff fc2c bl 8004bcc frequency = pll3_clocks.PLL3_Q_Frequency; 8005374: 9802 ldr r0, [sp, #8] 8005376: e665 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 8005378: 4b65 ldr r3, [pc, #404] @ (8005510 ) 800537a: 6818 ldr r0, [r3, #0] 800537c: f010 0004 ands.w r0, r0, #4 8005380: f43f ae60 beq.w 8005044 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8005384: 681b ldr r3, [r3, #0] 8005386: f3c3 03c1 ubfx r3, r3, #3, #2 800538a: 4863 ldr r0, [pc, #396] @ (8005518 ) 800538c: 40d8 lsrs r0, r3 800538e: e659 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 8005390: 4b5f ldr r3, [pc, #380] @ (8005510 ) 8005392: 6818 ldr r0, [r3, #0] 8005394: f410 7080 ands.w r0, r0, #256 @ 0x100 8005398: f43f ae54 beq.w 8005044 frequency = CSI_VALUE; 800539c: 485f ldr r0, [pc, #380] @ (800551c ) 800539e: e651 b.n 8005044 srcclk = __HAL_RCC_GET_ADC_SOURCE(); 80053a0: 4b5b ldr r3, [pc, #364] @ (8005510 ) 80053a2: 6d9b ldr r3, [r3, #88] @ 0x58 80053a4: f403 3340 and.w r3, r3, #196608 @ 0x30000 switch (srcclk) 80053a8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80053ac: d010 beq.n 80053d0 80053ae: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80053b2: d018 beq.n 80053e6 80053b4: 2b00 cmp r3, #0 80053b6: f040 80fd bne.w 80055b4 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80053ba: 4b55 ldr r3, [pc, #340] @ (8005510 ) 80053bc: 6818 ldr r0, [r3, #0] 80053be: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 80053c2: f43f ae3f beq.w 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80053c6: a804 add r0, sp, #16 80053c8: f7ff fb00 bl 80049cc frequency = pll2_clocks.PLL2_P_Frequency; 80053cc: 9804 ldr r0, [sp, #16] 80053ce: e639 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80053d0: 4b4f ldr r3, [pc, #316] @ (8005510 ) 80053d2: 6818 ldr r0, [r3, #0] 80053d4: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 80053d8: f43f ae34 beq.w 8005044 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80053dc: a801 add r0, sp, #4 80053de: f7ff fbf5 bl 8004bcc frequency = pll3_clocks.PLL3_R_Frequency; 80053e2: 9803 ldr r0, [sp, #12] 80053e4: e62e b.n 8005044 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 80053e6: 4a4a ldr r2, [pc, #296] @ (8005510 ) 80053e8: 6cd3 ldr r3, [r2, #76] @ 0x4c 80053ea: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 80053ee: 6812 ldr r2, [r2, #0] 80053f0: f012 0f04 tst.w r2, #4 80053f4: d007 beq.n 8005406 80053f6: b933 cbnz r3, 8005406 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80053f8: 4b45 ldr r3, [pc, #276] @ (8005510 ) 80053fa: 681b ldr r3, [r3, #0] 80053fc: f3c3 03c1 ubfx r3, r3, #3, #2 8005400: 4845 ldr r0, [pc, #276] @ (8005518 ) 8005402: 40d8 lsrs r0, r3 8005404: e61e b.n 8005044 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 8005406: 4a42 ldr r2, [pc, #264] @ (8005510 ) 8005408: 6812 ldr r2, [r2, #0] 800540a: f412 7f80 tst.w r2, #256 @ 0x100 800540e: d003 beq.n 8005418 8005410: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005414: f000 80d0 beq.w 80055b8 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8005418: 4a3d ldr r2, [pc, #244] @ (8005510 ) 800541a: 6812 ldr r2, [r2, #0] 800541c: f412 3f00 tst.w r2, #131072 @ 0x20000 8005420: f000 80cc beq.w 80055bc 8005424: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005428: f000 80ca beq.w 80055c0 frequency = 0; 800542c: 2000 movs r0, #0 800542e: e609 b.n 8005044 srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 8005430: 4b37 ldr r3, [pc, #220] @ (8005510 ) 8005432: 6cdb ldr r3, [r3, #76] @ 0x4c switch (srcclk) 8005434: f413 3380 ands.w r3, r3, #65536 @ 0x10000 8005438: d002 beq.n 8005440 800543a: b963 cbnz r3, 8005456 800543c: 2000 movs r0, #0 800543e: e601 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8005440: 4b33 ldr r3, [pc, #204] @ (8005510 ) 8005442: 6818 ldr r0, [r3, #0] 8005444: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000 8005448: f43f adfc beq.w 8005044 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800544c: a807 add r0, sp, #28 800544e: f7ff fcbd bl 8004dcc frequency = pll1_clocks.PLL1_Q_Frequency; 8005452: 9808 ldr r0, [sp, #32] 8005454: e5f6 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8005456: 4b2e ldr r3, [pc, #184] @ (8005510 ) 8005458: 6818 ldr r0, [r3, #0] 800545a: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 800545e: f43f adf1 beq.w 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8005462: a804 add r0, sp, #16 8005464: f7ff fab2 bl 80049cc frequency = pll2_clocks.PLL2_R_Frequency; 8005468: 9806 ldr r0, [sp, #24] 800546a: e5eb b.n 8005044 srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800546c: 4b28 ldr r3, [pc, #160] @ (8005510 ) 800546e: 6d9b ldr r3, [r3, #88] @ 0x58 8005470: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 switch (srcclk) 8005474: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8005478: d036 beq.n 80054e8 800547a: d80b bhi.n 8005494 800547c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005480: d01c beq.n 80054bc 8005482: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005486: d024 beq.n 80054d2 8005488: b913 cbnz r3, 8005490 frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800548a: f7ff fa8d bl 80049a8 break; 800548e: e5d9 b.n 8005044 frequency = 0; 8005490: 2000 movs r0, #0 8005492: e5d7 b.n 8005044 switch (srcclk) 8005494: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8005498: d032 beq.n 8005500 800549a: f1b3 4fc0 cmp.w r3, #1610612736 @ 0x60000000 800549e: f000 8091 beq.w 80055c4 80054a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80054a6: d107 bne.n 80054b8 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 80054a8: 4b19 ldr r3, [pc, #100] @ (8005510 ) 80054aa: 6818 ldr r0, [r3, #0] 80054ac: f410 7080 ands.w r0, r0, #256 @ 0x100 80054b0: f43f adc8 beq.w 8005044 frequency = CSI_VALUE; 80054b4: 4819 ldr r0, [pc, #100] @ (800551c ) 80054b6: e5c5 b.n 8005044 frequency = 0; 80054b8: 2000 movs r0, #0 80054ba: e5c3 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80054bc: 4b14 ldr r3, [pc, #80] @ (8005510 ) 80054be: 6818 ldr r0, [r3, #0] 80054c0: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 80054c4: f43f adbe beq.w 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80054c8: a804 add r0, sp, #16 80054ca: f7ff fa7f bl 80049cc frequency = pll2_clocks.PLL2_Q_Frequency; 80054ce: 9805 ldr r0, [sp, #20] 80054d0: e5b8 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80054d2: 4b0f ldr r3, [pc, #60] @ (8005510 ) 80054d4: 6818 ldr r0, [r3, #0] 80054d6: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 80054da: f43f adb3 beq.w 8005044 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80054de: a801 add r0, sp, #4 80054e0: f7ff fb74 bl 8004bcc frequency = pll3_clocks.PLL3_Q_Frequency; 80054e4: 9802 ldr r0, [sp, #8] 80054e6: e5ad b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 80054e8: 4b09 ldr r3, [pc, #36] @ (8005510 ) 80054ea: 6818 ldr r0, [r3, #0] 80054ec: f010 0004 ands.w r0, r0, #4 80054f0: f43f ada8 beq.w 8005044 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80054f4: 681b ldr r3, [r3, #0] 80054f6: f3c3 03c1 ubfx r3, r3, #3, #2 80054fa: 4807 ldr r0, [pc, #28] @ (8005518 ) 80054fc: 40d8 lsrs r0, r3 80054fe: e5a1 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8005500: 4b03 ldr r3, [pc, #12] @ (8005510 ) 8005502: 6818 ldr r0, [r3, #0] 8005504: f410 3000 ands.w r0, r0, #131072 @ 0x20000 8005508: f43f ad9c beq.w 8005044 frequency = HSE_VALUE; 800550c: 4801 ldr r0, [pc, #4] @ (8005514 ) 800550e: e599 b.n 8005044 8005510: 58024400 .word 0x58024400 8005514: 016e3600 .word 0x016e3600 8005518: 03d09000 .word 0x03d09000 800551c: 003d0900 .word 0x003d0900 srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 8005520: 4b2a ldr r3, [pc, #168] @ (80055cc ) 8005522: 6d1b ldr r3, [r3, #80] @ 0x50 8005524: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 switch (srcclk) 8005528: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800552c: d00c beq.n 8005548 800552e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005532: d014 beq.n 800555e 8005534: 2b00 cmp r3, #0 8005536: d147 bne.n 80055c8 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 8005538: 4b24 ldr r3, [pc, #144] @ (80055cc ) 800553a: 6818 ldr r0, [r3, #0] 800553c: f410 3000 ands.w r0, r0, #131072 @ 0x20000 8005540: f43f ad80 beq.w 8005044 frequency = HSE_VALUE; 8005544: 4822 ldr r0, [pc, #136] @ (80055d0 ) 8005546: e57d b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8005548: 4b20 ldr r3, [pc, #128] @ (80055cc ) 800554a: 6818 ldr r0, [r3, #0] 800554c: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000 8005550: f43f ad78 beq.w 8005044 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 8005554: a807 add r0, sp, #28 8005556: f7ff fc39 bl 8004dcc frequency = pll1_clocks.PLL1_Q_Frequency; 800555a: 9808 ldr r0, [sp, #32] 800555c: e572 b.n 8005044 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800555e: 4b1b ldr r3, [pc, #108] @ (80055cc ) 8005560: 6818 ldr r0, [r3, #0] 8005562: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 8005566: f43f ad6d beq.w 8005044 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800556a: a804 add r0, sp, #16 800556c: f7ff fa2e bl 80049cc frequency = pll2_clocks.PLL2_Q_Frequency; 8005570: 9805 ldr r0, [sp, #20] 8005572: e567 b.n 8005044 frequency = 0; 8005574: 2000 movs r0, #0 8005576: e565 b.n 8005044 frequency = CSI_VALUE; 8005578: 4816 ldr r0, [pc, #88] @ (80055d4 ) 800557a: e563 b.n 8005044 frequency = 0; 800557c: 2000 movs r0, #0 800557e: e561 b.n 8005044 frequency = HSE_VALUE; 8005580: 4813 ldr r0, [pc, #76] @ (80055d0 ) 8005582: e55f b.n 8005044 switch (saiclocksource) 8005584: 4814 ldr r0, [pc, #80] @ (80055d8 ) 8005586: e55d b.n 8005044 frequency = CSI_VALUE; 8005588: 4812 ldr r0, [pc, #72] @ (80055d4 ) 800558a: e55b b.n 8005044 frequency = 0; 800558c: 2000 movs r0, #0 800558e: e559 b.n 8005044 frequency = HSE_VALUE; 8005590: 480f ldr r0, [pc, #60] @ (80055d0 ) 8005592: e557 b.n 8005044 switch (saiclocksource) 8005594: 4810 ldr r0, [pc, #64] @ (80055d8 ) 8005596: e555 b.n 8005044 frequency = CSI_VALUE; 8005598: 480e ldr r0, [pc, #56] @ (80055d4 ) 800559a: e553 b.n 8005044 frequency = 0; 800559c: 2000 movs r0, #0 800559e: e551 b.n 8005044 frequency = HSE_VALUE; 80055a0: 480b ldr r0, [pc, #44] @ (80055d0 ) 80055a2: e54f b.n 8005044 switch (srcclk) 80055a4: 480c ldr r0, [pc, #48] @ (80055d8 ) 80055a6: e54d b.n 8005044 frequency = CSI_VALUE; 80055a8: 480a ldr r0, [pc, #40] @ (80055d4 ) 80055aa: e54b b.n 8005044 frequency = 0; 80055ac: 2000 movs r0, #0 80055ae: e549 b.n 8005044 frequency = HSE_VALUE; 80055b0: 4807 ldr r0, [pc, #28] @ (80055d0 ) 80055b2: e547 b.n 8005044 switch (srcclk) 80055b4: 2000 movs r0, #0 80055b6: e545 b.n 8005044 frequency = CSI_VALUE; 80055b8: 4806 ldr r0, [pc, #24] @ (80055d4 ) 80055ba: e543 b.n 8005044 frequency = 0; 80055bc: 2000 movs r0, #0 80055be: e541 b.n 8005044 frequency = HSE_VALUE; 80055c0: 4803 ldr r0, [pc, #12] @ (80055d0 ) 80055c2: e53f b.n 8005044 switch (srcclk) 80055c4: 4804 ldr r0, [pc, #16] @ (80055d8 ) 80055c6: e53d b.n 8005044 switch (srcclk) 80055c8: 2000 movs r0, #0 return frequency; 80055ca: e53b b.n 8005044 80055cc: 58024400 .word 0x58024400 80055d0: 016e3600 .word 0x016e3600 80055d4: 003d0900 .word 0x003d0900 80055d8: 00bb8000 .word 0x00bb8000 080055dc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80055dc: b4f0 push {r4, r5, r6, r7} uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80055de: 6a02 ldr r2, [r0, #32] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80055e0: 6a03 ldr r3, [r0, #32] 80055e2: f023 0301 bic.w r3, r3, #1 80055e6: 6203 str r3, [r0, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80055e8: 6846 ldr r6, [r0, #4] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 80055ea: 6984 ldr r4, [r0, #24] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; tmpccmrx &= ~TIM_CCMR1_CC1S; 80055ec: 4b1e ldr r3, [pc, #120] @ (8005668 ) 80055ee: 4023 ands r3, r4 /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80055f0: 680d ldr r5, [r1, #0] 80055f2: 431d orrs r5, r3 /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 80055f4: f022 0202 bic.w r2, r2, #2 /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 80055f8: 688b ldr r3, [r1, #8] 80055fa: 4313 orrs r3, r2 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 80055fc: 4a1b ldr r2, [pc, #108] @ (800566c ) 80055fe: 4c1c ldr r4, [pc, #112] @ (8005670 ) 8005600: 42a0 cmp r0, r4 8005602: bf18 it ne 8005604: 4290 cmpne r0, r2 8005606: bf0c ite eq 8005608: 2201 moveq r2, #1 800560a: 2200 movne r2, #0 800560c: d00c beq.n 8005628 800560e: f504 4480 add.w r4, r4, #16384 @ 0x4000 8005612: 42a0 cmp r0, r4 8005614: bf14 ite ne 8005616: 2400 movne r4, #0 8005618: 2401 moveq r4, #1 800561a: 4f16 ldr r7, [pc, #88] @ (8005674 ) 800561c: 42b8 cmp r0, r7 800561e: d003 beq.n 8005628 8005620: b914 cbnz r4, 8005628 8005622: 4c15 ldr r4, [pc, #84] @ (8005678 ) 8005624: 42a0 cmp r0, r4 8005626: d105 bne.n 8005634 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8005628: f023 0308 bic.w r3, r3, #8 /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 800562c: 68cc ldr r4, [r1, #12] 800562e: 4323 orrs r3, r4 /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8005630: f023 0304 bic.w r3, r3, #4 } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005634: b95a cbnz r2, 800564e 8005636: 4a11 ldr r2, [pc, #68] @ (800567c ) 8005638: 4290 cmp r0, r2 800563a: bf14 ite ne 800563c: 2200 movne r2, #0 800563e: 2201 moveq r2, #1 8005640: 4c0c ldr r4, [pc, #48] @ (8005674 ) 8005642: 42a0 cmp r0, r4 8005644: d003 beq.n 800564e 8005646: b912 cbnz r2, 800564e 8005648: 4a0b ldr r2, [pc, #44] @ (8005678 ) 800564a: 4290 cmp r0, r2 800564c: d105 bne.n 800565a assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; tmpcr2 &= ~TIM_CR2_OIS1N; 800564e: f426 7640 bic.w r6, r6, #768 @ 0x300 /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 8005652: 694a ldr r2, [r1, #20] 8005654: 4332 orrs r2, r6 /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 8005656: 698e ldr r6, [r1, #24] 8005658: 4316 orrs r6, r2 } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800565a: 6046 str r6, [r0, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800565c: 6185 str r5, [r0, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800565e: 684a ldr r2, [r1, #4] 8005660: 6342 str r2, [r0, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005662: 6203 str r3, [r0, #32] } 8005664: bcf0 pop {r4, r5, r6, r7} 8005666: 4770 bx lr 8005668: fffeff8c .word 0xfffeff8c 800566c: 40010000 .word 0x40010000 8005670: 40010400 .word 0x40010400 8005674: 40014000 .word 0x40014000 8005678: 40014800 .word 0x40014800 800567c: 40014400 .word 0x40014400 08005680 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005680: b470 push {r4, r5, r6} uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005682: 6a03 ldr r3, [r0, #32] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8005684: 6a02 ldr r2, [r0, #32] 8005686: f422 7280 bic.w r2, r2, #256 @ 0x100 800568a: 6202 str r2, [r0, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800568c: 6845 ldr r5, [r0, #4] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800568e: 69c4 ldr r4, [r0, #28] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; tmpccmrx &= ~TIM_CCMR2_CC3S; 8005690: 4a1a ldr r2, [pc, #104] @ (80056fc ) 8005692: 4022 ands r2, r4 /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8005694: 680e ldr r6, [r1, #0] 8005696: 4316 orrs r6, r2 /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8005698: f423 7300 bic.w r3, r3, #512 @ 0x200 /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800569c: 688a ldr r2, [r1, #8] 800569e: ea43 2302 orr.w r3, r3, r2, lsl #8 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80056a2: 4a17 ldr r2, [pc, #92] @ (8005700 ) 80056a4: 4c17 ldr r4, [pc, #92] @ (8005704 ) 80056a6: 42a0 cmp r0, r4 80056a8: bf18 it ne 80056aa: 4290 cmpne r0, r2 80056ac: bf0c ite eq 80056ae: 2201 moveq r2, #1 80056b0: 2200 movne r2, #0 80056b2: d106 bne.n 80056c2 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 80056b4: f423 6300 bic.w r3, r3, #2048 @ 0x800 /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 80056b8: 68cc ldr r4, [r1, #12] 80056ba: ea43 2304 orr.w r3, r3, r4, lsl #8 /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 80056be: f423 6380 bic.w r3, r3, #1024 @ 0x400 } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80056c2: b95a cbnz r2, 80056dc 80056c4: 4a10 ldr r2, [pc, #64] @ (8005708 ) 80056c6: 4290 cmp r0, r2 80056c8: bf14 ite ne 80056ca: 2200 movne r2, #0 80056cc: 2201 moveq r2, #1 80056ce: 4c0f ldr r4, [pc, #60] @ (800570c ) 80056d0: 42a0 cmp r0, r4 80056d2: d003 beq.n 80056dc 80056d4: b912 cbnz r2, 80056dc 80056d6: 4a0e ldr r2, [pc, #56] @ (8005710 ) 80056d8: 4290 cmp r0, r2 80056da: d107 bne.n 80056ec assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; 80056dc: f425 5240 bic.w r2, r5, #12288 @ 0x3000 /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 80056e0: 694c ldr r4, [r1, #20] 80056e2: ea42 1204 orr.w r2, r2, r4, lsl #4 /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80056e6: 698c ldr r4, [r1, #24] 80056e8: ea42 1504 orr.w r5, r2, r4, lsl #4 } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80056ec: 6045 str r5, [r0, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80056ee: 61c6 str r6, [r0, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 80056f0: 684a ldr r2, [r1, #4] 80056f2: 63c2 str r2, [r0, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80056f4: 6203 str r3, [r0, #32] } 80056f6: bc70 pop {r4, r5, r6} 80056f8: 4770 bx lr 80056fa: bf00 nop 80056fc: fffeff8c .word 0xfffeff8c 8005700: 40010000 .word 0x40010000 8005704: 40010400 .word 0x40010400 8005708: 40014400 .word 0x40014400 800570c: 40014000 .word 0x40014000 8005710: 40014800 .word 0x40014800 08005714 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005714: b470 push {r4, r5, r6} uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8005716: 6a03 ldr r3, [r0, #32] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8005718: 6a02 ldr r2, [r0, #32] 800571a: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800571e: 6202 str r2, [r0, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005720: 6844 ldr r4, [r0, #4] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8005722: 69c5 ldr r5, [r0, #28] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; tmpccmrx &= ~TIM_CCMR2_CC4S; 8005724: 4a14 ldr r2, [pc, #80] @ (8005778 ) 8005726: 402a ands r2, r5 /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8005728: 680d ldr r5, [r1, #0] 800572a: ea42 2205 orr.w r2, r2, r5, lsl #8 /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 800572e: f423 5300 bic.w r3, r3, #8192 @ 0x2000 /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8005732: 688d ldr r5, [r1, #8] 8005734: ea43 3305 orr.w r3, r3, r5, lsl #12 if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005738: 4e10 ldr r6, [pc, #64] @ (800577c ) 800573a: 4d11 ldr r5, [pc, #68] @ (8005780 ) 800573c: 42a8 cmp r0, r5 800573e: bf18 it ne 8005740: 42b0 cmpne r0, r6 8005742: d00d beq.n 8005760 8005744: f505 4580 add.w r5, r5, #16384 @ 0x4000 8005748: 42a8 cmp r0, r5 800574a: bf14 ite ne 800574c: 2500 movne r5, #0 800574e: 2501 moveq r5, #1 8005750: f506 4680 add.w r6, r6, #16384 @ 0x4000 8005754: 42b0 cmp r0, r6 8005756: d003 beq.n 8005760 8005758: b915 cbnz r5, 8005760 800575a: 4d0a ldr r5, [pc, #40] @ (8005784 ) 800575c: 42a8 cmp r0, r5 800575e: d104 bne.n 800576a { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8005760: f424 4480 bic.w r4, r4, #16384 @ 0x4000 /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8005764: 694d ldr r5, [r1, #20] 8005766: ea44 1485 orr.w r4, r4, r5, lsl #6 } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800576a: 6044 str r4, [r0, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800576c: 61c2 str r2, [r0, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 800576e: 684a ldr r2, [r1, #4] 8005770: 6402 str r2, [r0, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8005772: 6203 str r3, [r0, #32] } 8005774: bc70 pop {r4, r5, r6} 8005776: 4770 bx lr 8005778: feff8cff .word 0xfeff8cff 800577c: 40010000 .word 0x40010000 8005780: 40010400 .word 0x40010400 8005784: 40014800 .word 0x40014800 08005788 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8005788: b470 push {r4, r5, r6} uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800578a: 6a03 ldr r3, [r0, #32] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 800578c: 6a02 ldr r2, [r0, #32] 800578e: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8005792: 6202 str r2, [r0, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005794: 6842 ldr r2, [r0, #4] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8005796: 6d45 ldr r5, [r0, #84] @ 0x54 /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8005798: 4e14 ldr r6, [pc, #80] @ (80057ec ) 800579a: 402e ands r6, r5 /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800579c: 680d ldr r5, [r1, #0] 800579e: 432e orrs r6, r5 /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 80057a0: f423 3300 bic.w r3, r3, #131072 @ 0x20000 /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 80057a4: 688c ldr r4, [r1, #8] 80057a6: ea43 4304 orr.w r3, r3, r4, lsl #16 if (IS_TIM_BREAK_INSTANCE(TIMx)) 80057aa: 4d11 ldr r5, [pc, #68] @ (80057f0 ) 80057ac: 4c11 ldr r4, [pc, #68] @ (80057f4 ) 80057ae: 42a0 cmp r0, r4 80057b0: bf18 it ne 80057b2: 42a8 cmpne r0, r5 80057b4: d00d beq.n 80057d2 80057b6: f504 4480 add.w r4, r4, #16384 @ 0x4000 80057ba: 42a0 cmp r0, r4 80057bc: bf14 ite ne 80057be: 2400 movne r4, #0 80057c0: 2401 moveq r4, #1 80057c2: f505 4580 add.w r5, r5, #16384 @ 0x4000 80057c6: 42a8 cmp r0, r5 80057c8: d003 beq.n 80057d2 80057ca: b914 cbnz r4, 80057d2 80057cc: 4c0a ldr r4, [pc, #40] @ (80057f8 ) 80057ce: 42a0 cmp r0, r4 80057d0: d104 bne.n 80057dc { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 80057d2: f422 3280 bic.w r2, r2, #65536 @ 0x10000 /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 80057d6: 694c ldr r4, [r1, #20] 80057d8: ea42 2204 orr.w r2, r2, r4, lsl #8 } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80057dc: 6042 str r2, [r0, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 80057de: 6546 str r6, [r0, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 80057e0: 684a ldr r2, [r1, #4] 80057e2: 6582 str r2, [r0, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80057e4: 6203 str r3, [r0, #32] } 80057e6: bc70 pop {r4, r5, r6} 80057e8: 4770 bx lr 80057ea: bf00 nop 80057ec: fffeff8f .word 0xfffeff8f 80057f0: 40010000 .word 0x40010000 80057f4: 40010400 .word 0x40010400 80057f8: 40014800 .word 0x40014800 080057fc : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80057fc: b470 push {r4, r5, r6} uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80057fe: 6a03 ldr r3, [r0, #32] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8005800: 6a02 ldr r2, [r0, #32] 8005802: f422 1280 bic.w r2, r2, #1048576 @ 0x100000 8005806: 6202 str r2, [r0, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8005808: 6844 ldr r4, [r0, #4] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 800580a: 6d45 ldr r5, [r0, #84] @ 0x54 /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 800580c: 4a14 ldr r2, [pc, #80] @ (8005860 ) 800580e: 402a ands r2, r5 /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8005810: 680d ldr r5, [r1, #0] 8005812: ea42 2205 orr.w r2, r2, r5, lsl #8 /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8005816: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 800581a: 688d ldr r5, [r1, #8] 800581c: ea43 5305 orr.w r3, r3, r5, lsl #20 if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005820: 4e10 ldr r6, [pc, #64] @ (8005864 ) 8005822: 4d11 ldr r5, [pc, #68] @ (8005868 ) 8005824: 42a8 cmp r0, r5 8005826: bf18 it ne 8005828: 42b0 cmpne r0, r6 800582a: d00d beq.n 8005848 800582c: f505 4580 add.w r5, r5, #16384 @ 0x4000 8005830: 42a8 cmp r0, r5 8005832: bf14 ite ne 8005834: 2500 movne r5, #0 8005836: 2501 moveq r5, #1 8005838: f506 4680 add.w r6, r6, #16384 @ 0x4000 800583c: 42b0 cmp r0, r6 800583e: d003 beq.n 8005848 8005840: b915 cbnz r5, 8005848 8005842: 4d0a ldr r5, [pc, #40] @ (800586c ) 8005844: 42a8 cmp r0, r5 8005846: d104 bne.n 8005852 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 8005848: f424 2480 bic.w r4, r4, #262144 @ 0x40000 /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 800584c: 694d ldr r5, [r1, #20] 800584e: ea44 2485 orr.w r4, r4, r5, lsl #10 } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8005852: 6044 str r4, [r0, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8005854: 6542 str r2, [r0, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8005856: 684a ldr r2, [r1, #4] 8005858: 65c2 str r2, [r0, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800585a: 6203 str r3, [r0, #32] } 800585c: bc70 pop {r4, r5, r6} 800585e: 4770 bx lr 8005860: feff8fff .word 0xfeff8fff 8005864: 40010000 .word 0x40010000 8005868: 40010400 .word 0x40010400 800586c: 40014800 .word 0x40014800 08005870 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8005870: b410 push {r4} uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8005872: 6a03 ldr r3, [r0, #32] TIMx->CCER &= ~TIM_CCER_CC1E; 8005874: 6a04 ldr r4, [r0, #32] 8005876: f024 0401 bic.w r4, r4, #1 800587a: 6204 str r4, [r0, #32] tmpccmr1 = TIMx->CCMR1; 800587c: 6984 ldr r4, [r0, #24] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 800587e: f024 0cf0 bic.w ip, r4, #240 @ 0xf0 tmpccmr1 |= (TIM_ICFilter << 4U); 8005882: ea4c 1202 orr.w r2, ip, r2, lsl #4 /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8005886: f023 030a bic.w r3, r3, #10 tmpccer |= TIM_ICPolarity; 800588a: 430b orrs r3, r1 /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 800588c: 6182 str r2, [r0, #24] TIMx->CCER = tmpccer; 800588e: 6203 str r3, [r0, #32] } 8005890: f85d 4b04 ldr.w r4, [sp], #4 8005894: 4770 bx lr 08005896 : * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8005896: b430 push {r4, r5} uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8005898: 6a05 ldr r5, [r0, #32] TIMx->CCER &= ~TIM_CCER_CC2E; 800589a: 6a04 ldr r4, [r0, #32] 800589c: f024 0410 bic.w r4, r4, #16 80058a0: 6204 str r4, [r0, #32] tmpccmr1 = TIMx->CCMR1; 80058a2: 6984 ldr r4, [r0, #24] /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; 80058a4: f424 7c40 bic.w ip, r4, #768 @ 0x300 tmpccmr1 |= (TIM_ICSelection << 8U); 80058a8: ea4c 2c02 orr.w ip, ip, r2, lsl #8 /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 80058ac: f42c 4c70 bic.w ip, ip, #61440 @ 0xf000 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); 80058b0: 031b lsls r3, r3, #12 80058b2: b29b uxth r3, r3 80058b4: ea43 030c orr.w r3, r3, ip /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 80058b8: f025 05a0 bic.w r5, r5, #160 @ 0xa0 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 80058bc: 0109 lsls r1, r1, #4 80058be: f001 01a0 and.w r1, r1, #160 @ 0xa0 80058c2: 4329 orrs r1, r5 /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 80058c4: 6183 str r3, [r0, #24] TIMx->CCER = tmpccer; 80058c6: 6201 str r1, [r0, #32] } 80058c8: bc30 pop {r4, r5} 80058ca: 4770 bx lr 080058cc : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80058cc: b410 push {r4} uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 80058ce: 6a03 ldr r3, [r0, #32] TIMx->CCER &= ~TIM_CCER_CC2E; 80058d0: 6a04 ldr r4, [r0, #32] 80058d2: f024 0410 bic.w r4, r4, #16 80058d6: 6204 str r4, [r0, #32] tmpccmr1 = TIMx->CCMR1; 80058d8: 6984 ldr r4, [r0, #24] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 80058da: f424 4c70 bic.w ip, r4, #61440 @ 0xf000 tmpccmr1 |= (TIM_ICFilter << 12U); 80058de: ea4c 3202 orr.w r2, ip, r2, lsl #12 /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 80058e2: f023 03a0 bic.w r3, r3, #160 @ 0xa0 tmpccer |= (TIM_ICPolarity << 4U); 80058e6: ea43 1301 orr.w r3, r3, r1, lsl #4 /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 80058ea: 6182 str r2, [r0, #24] TIMx->CCER = tmpccer; 80058ec: 6203 str r3, [r0, #32] } 80058ee: f85d 4b04 ldr.w r4, [sp], #4 80058f2: 4770 bx lr 080058f4 : * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 80058f4: b430 push {r4, r5} uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ tmpccer = TIMx->CCER; 80058f6: 6a05 ldr r5, [r0, #32] TIMx->CCER &= ~TIM_CCER_CC3E; 80058f8: 6a04 ldr r4, [r0, #32] 80058fa: f424 7480 bic.w r4, r4, #256 @ 0x100 80058fe: 6204 str r4, [r0, #32] tmpccmr2 = TIMx->CCMR2; 8005900: 69c4 ldr r4, [r0, #28] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; 8005902: f024 0c03 bic.w ip, r4, #3 tmpccmr2 |= TIM_ICSelection; 8005906: ea4c 0c02 orr.w ip, ip, r2 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; 800590a: f02c 0cf0 bic.w ip, ip, #240 @ 0xf0 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); 800590e: 011b lsls r3, r3, #4 8005910: b2db uxtb r3, r3 8005912: ea43 030c orr.w r3, r3, ip /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 8005916: f425 6520 bic.w r5, r5, #2560 @ 0xa00 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 800591a: 0209 lsls r1, r1, #8 800591c: f401 6120 and.w r1, r1, #2560 @ 0xa00 8005920: 4329 orrs r1, r5 /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 8005922: 61c3 str r3, [r0, #28] TIMx->CCER = tmpccer; 8005924: 6201 str r1, [r0, #32] } 8005926: bc30 pop {r4, r5} 8005928: 4770 bx lr 0800592a : * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 800592a: b430 push {r4, r5} uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ tmpccer = TIMx->CCER; 800592c: 6a05 ldr r5, [r0, #32] TIMx->CCER &= ~TIM_CCER_CC4E; 800592e: 6a04 ldr r4, [r0, #32] 8005930: f424 5480 bic.w r4, r4, #4096 @ 0x1000 8005934: 6204 str r4, [r0, #32] tmpccmr2 = TIMx->CCMR2; 8005936: 69c4 ldr r4, [r0, #28] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; 8005938: f424 7c40 bic.w ip, r4, #768 @ 0x300 tmpccmr2 |= (TIM_ICSelection << 8U); 800593c: ea4c 2c02 orr.w ip, ip, r2, lsl #8 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; 8005940: f42c 4c70 bic.w ip, ip, #61440 @ 0xf000 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); 8005944: 031b lsls r3, r3, #12 8005946: b29b uxth r3, r3 8005948: ea43 030c orr.w r3, r3, ip /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 800594c: f425 4520 bic.w r5, r5, #40960 @ 0xa000 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 8005950: 0309 lsls r1, r1, #12 8005952: f401 4120 and.w r1, r1, #40960 @ 0xa000 8005956: 4329 orrs r1, r5 /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 8005958: 61c3 str r3, [r0, #28] TIMx->CCER = tmpccer ; 800595a: 6201 str r1, [r0, #32] } 800595c: bc30 pop {r4, r5} 800595e: 4770 bx lr 08005960 : static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8005960: 6882 ldr r2, [r0, #8] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8005962: 4b03 ldr r3, [pc, #12] @ (8005970 ) 8005964: 4013 ands r3, r2 /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8005966: 430b orrs r3, r1 8005968: f043 0307 orr.w r3, r3, #7 /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800596c: 6083 str r3, [r0, #8] } 800596e: 4770 bx lr 8005970: ffcfff8f .word 0xffcfff8f 08005974 : { 8005974: b470 push {r4, r5, r6} tmpcr1 = TIMx->CR1; 8005976: 6803 ldr r3, [r0, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8005978: 4a39 ldr r2, [pc, #228] @ (8005a60 ) 800597a: 4290 cmp r0, r2 800597c: bf14 ite ne 800597e: 2200 movne r2, #0 8005980: 2201 moveq r2, #1 8005982: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000 8005986: bf14 ite ne 8005988: 4614 movne r4, r2 800598a: f042 0401 orreq.w r4, r2, #1 800598e: b9ac cbnz r4, 80059bc 8005990: 4d34 ldr r5, [pc, #208] @ (8005a64 ) 8005992: 42a8 cmp r0, r5 8005994: bf14 ite ne 8005996: 2500 movne r5, #0 8005998: 2501 moveq r5, #1 800599a: 4e33 ldr r6, [pc, #204] @ (8005a68 ) 800599c: 42b0 cmp r0, r6 800599e: d00d beq.n 80059bc 80059a0: b965 cbnz r5, 80059bc 80059a2: f105 4580 add.w r5, r5, #1073741824 @ 0x40000000 80059a6: f505 3582 add.w r5, r5, #66560 @ 0x10400 80059aa: 42a8 cmp r0, r5 80059ac: bf14 ite ne 80059ae: 2500 movne r5, #0 80059b0: 2501 moveq r5, #1 80059b2: f506 6600 add.w r6, r6, #2048 @ 0x800 80059b6: 42b0 cmp r0, r6 80059b8: d000 beq.n 80059bc 80059ba: b11d cbz r5, 80059c4 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80059bc: f023 0370 bic.w r3, r3, #112 @ 0x70 tmpcr1 |= Structure->CounterMode; 80059c0: 684d ldr r5, [r1, #4] 80059c2: 432b orrs r3, r5 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80059c4: bb14 cbnz r4, 8005a0c 80059c6: 4c27 ldr r4, [pc, #156] @ (8005a64 ) 80059c8: 42a0 cmp r0, r4 80059ca: bf14 ite ne 80059cc: 2400 movne r4, #0 80059ce: 2401 moveq r4, #1 80059d0: 4d25 ldr r5, [pc, #148] @ (8005a68 ) 80059d2: 42a8 cmp r0, r5 80059d4: d01a beq.n 8005a0c 80059d6: b9cc cbnz r4, 8005a0c 80059d8: f104 4480 add.w r4, r4, #1073741824 @ 0x40000000 80059dc: f504 3482 add.w r4, r4, #66560 @ 0x10400 80059e0: 42a0 cmp r0, r4 80059e2: bf14 ite ne 80059e4: 2400 movne r4, #0 80059e6: 2401 moveq r4, #1 80059e8: f505 6500 add.w r5, r5, #2048 @ 0x800 80059ec: 42a8 cmp r0, r5 80059ee: d00d beq.n 8005a0c 80059f0: b964 cbnz r4, 8005a0c 80059f2: 4c1e ldr r4, [pc, #120] @ (8005a6c ) 80059f4: 42a0 cmp r0, r4 80059f6: bf14 ite ne 80059f8: 2400 movne r4, #0 80059fa: 2401 moveq r4, #1 80059fc: f505 359a add.w r5, r5, #78848 @ 0x13400 8005a00: 42a8 cmp r0, r5 8005a02: d003 beq.n 8005a0c 8005a04: b914 cbnz r4, 8005a0c 8005a06: 4c1a ldr r4, [pc, #104] @ (8005a70 ) 8005a08: 42a0 cmp r0, r4 8005a0a: d103 bne.n 8005a14 tmpcr1 &= ~TIM_CR1_CKD; 8005a0c: f423 7340 bic.w r3, r3, #768 @ 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005a10: 68cc ldr r4, [r1, #12] 8005a12: 4323 orrs r3, r4 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8005a14: f023 0380 bic.w r3, r3, #128 @ 0x80 8005a18: 694c ldr r4, [r1, #20] 8005a1a: 4323 orrs r3, r4 TIMx->ARR = (uint32_t)Structure->Period ; 8005a1c: 688c ldr r4, [r1, #8] 8005a1e: 62c4 str r4, [r0, #44] @ 0x2c TIMx->PSC = Structure->Prescaler; 8005a20: 680c ldr r4, [r1, #0] 8005a22: 6284 str r4, [r0, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8005a24: 4c13 ldr r4, [pc, #76] @ (8005a74 ) 8005a26: 42a0 cmp r0, r4 8005a28: bf08 it eq 8005a2a: f042 0201 orreq.w r2, r2, #1 8005a2e: b962 cbnz r2, 8005a4a 8005a30: 4a0e ldr r2, [pc, #56] @ (8005a6c ) 8005a32: 4290 cmp r0, r2 8005a34: bf14 ite ne 8005a36: 2200 movne r2, #0 8005a38: 2201 moveq r2, #1 8005a3a: f504 5470 add.w r4, r4, #15360 @ 0x3c00 8005a3e: 42a0 cmp r0, r4 8005a40: d003 beq.n 8005a4a 8005a42: b912 cbnz r2, 8005a4a 8005a44: 4a0a ldr r2, [pc, #40] @ (8005a70 ) 8005a46: 4290 cmp r0, r2 8005a48: d101 bne.n 8005a4e TIMx->RCR = Structure->RepetitionCounter; 8005a4a: 690a ldr r2, [r1, #16] 8005a4c: 6302 str r2, [r0, #48] @ 0x30 SET_BIT(TIMx->CR1, TIM_CR1_URS); 8005a4e: 6802 ldr r2, [r0, #0] 8005a50: f042 0204 orr.w r2, r2, #4 8005a54: 6002 str r2, [r0, #0] TIMx->EGR = TIM_EGR_UG; 8005a56: 2201 movs r2, #1 8005a58: 6142 str r2, [r0, #20] TIMx->CR1 = tmpcr1; 8005a5a: 6003 str r3, [r0, #0] } 8005a5c: bc70 pop {r4, r5, r6} 8005a5e: 4770 bx lr 8005a60: 40010000 .word 0x40010000 8005a64: 40000800 .word 0x40000800 8005a68: 40000400 .word 0x40000400 8005a6c: 40014400 .word 0x40014400 8005a70: 40014800 .word 0x40014800 8005a74: 40010400 .word 0x40010400 08005a78 : if (htim == NULL) 8005a78: b360 cbz r0, 8005ad4 { 8005a7a: b510 push {r4, lr} 8005a7c: 4604 mov r4, r0 if (htim->State == HAL_TIM_STATE_RESET) 8005a7e: f890 303d ldrb.w r3, [r0, #61] @ 0x3d 8005a82: b313 cbz r3, 8005aca htim->State = HAL_TIM_STATE_BUSY; 8005a84: 2302 movs r3, #2 8005a86: f884 303d strb.w r3, [r4, #61] @ 0x3d TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005a8a: 4621 mov r1, r4 8005a8c: f851 0b04 ldr.w r0, [r1], #4 8005a90: f7ff ff70 bl 8005974 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005a94: 2301 movs r3, #1 8005a96: f884 3048 strb.w r3, [r4, #72] @ 0x48 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005a9a: f884 303e strb.w r3, [r4, #62] @ 0x3e 8005a9e: f884 303f strb.w r3, [r4, #63] @ 0x3f 8005aa2: f884 3040 strb.w r3, [r4, #64] @ 0x40 8005aa6: f884 3041 strb.w r3, [r4, #65] @ 0x41 8005aaa: f884 3042 strb.w r3, [r4, #66] @ 0x42 8005aae: f884 3043 strb.w r3, [r4, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005ab2: f884 3044 strb.w r3, [r4, #68] @ 0x44 8005ab6: f884 3045 strb.w r3, [r4, #69] @ 0x45 8005aba: f884 3046 strb.w r3, [r4, #70] @ 0x46 8005abe: f884 3047 strb.w r3, [r4, #71] @ 0x47 htim->State = HAL_TIM_STATE_READY; 8005ac2: f884 303d strb.w r3, [r4, #61] @ 0x3d return HAL_OK; 8005ac6: 2000 movs r0, #0 } 8005ac8: bd10 pop {r4, pc} htim->Lock = HAL_UNLOCKED; 8005aca: f880 303c strb.w r3, [r0, #60] @ 0x3c HAL_TIM_Base_MspInit(htim); 8005ace: f7fd fa51 bl 8002f74 8005ad2: e7d7 b.n 8005a84 return HAL_ERROR; 8005ad4: 2001 movs r0, #1 } 8005ad6: 4770 bx lr 08005ad8 : if (htim == NULL) 8005ad8: b360 cbz r0, 8005b34 { 8005ada: b510 push {r4, lr} 8005adc: 4604 mov r4, r0 if (htim->State == HAL_TIM_STATE_RESET) 8005ade: f890 303d ldrb.w r3, [r0, #61] @ 0x3d 8005ae2: b313 cbz r3, 8005b2a htim->State = HAL_TIM_STATE_BUSY; 8005ae4: 2302 movs r3, #2 8005ae6: f884 303d strb.w r3, [r4, #61] @ 0x3d TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005aea: 4621 mov r1, r4 8005aec: f851 0b04 ldr.w r0, [r1], #4 8005af0: f7ff ff40 bl 8005974 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005af4: 2301 movs r3, #1 8005af6: f884 3048 strb.w r3, [r4, #72] @ 0x48 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005afa: f884 303e strb.w r3, [r4, #62] @ 0x3e 8005afe: f884 303f strb.w r3, [r4, #63] @ 0x3f 8005b02: f884 3040 strb.w r3, [r4, #64] @ 0x40 8005b06: f884 3041 strb.w r3, [r4, #65] @ 0x41 8005b0a: f884 3042 strb.w r3, [r4, #66] @ 0x42 8005b0e: f884 3043 strb.w r3, [r4, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005b12: f884 3044 strb.w r3, [r4, #68] @ 0x44 8005b16: f884 3045 strb.w r3, [r4, #69] @ 0x45 8005b1a: f884 3046 strb.w r3, [r4, #70] @ 0x46 8005b1e: f884 3047 strb.w r3, [r4, #71] @ 0x47 htim->State = HAL_TIM_STATE_READY; 8005b22: f884 303d strb.w r3, [r4, #61] @ 0x3d return HAL_OK; 8005b26: 2000 movs r0, #0 } 8005b28: bd10 pop {r4, pc} htim->Lock = HAL_UNLOCKED; 8005b2a: f880 303c strb.w r3, [r0, #60] @ 0x3c HAL_TIM_PWM_MspInit(htim); 8005b2e: f7fd fa4d bl 8002fcc 8005b32: e7d7 b.n 8005ae4 return HAL_ERROR; 8005b34: 2001 movs r0, #1 } 8005b36: 4770 bx lr 08005b38 : if (htim == NULL) 8005b38: b360 cbz r0, 8005b94 { 8005b3a: b510 push {r4, lr} 8005b3c: 4604 mov r4, r0 if (htim->State == HAL_TIM_STATE_RESET) 8005b3e: f890 303d ldrb.w r3, [r0, #61] @ 0x3d 8005b42: b313 cbz r3, 8005b8a htim->State = HAL_TIM_STATE_BUSY; 8005b44: 2302 movs r3, #2 8005b46: f884 303d strb.w r3, [r4, #61] @ 0x3d TIM_Base_SetConfig(htim->Instance, &htim->Init); 8005b4a: 4621 mov r1, r4 8005b4c: f851 0b04 ldr.w r0, [r1], #4 8005b50: f7ff ff10 bl 8005974 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005b54: 2301 movs r3, #1 8005b56: f884 3048 strb.w r3, [r4, #72] @ 0x48 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005b5a: f884 303e strb.w r3, [r4, #62] @ 0x3e 8005b5e: f884 303f strb.w r3, [r4, #63] @ 0x3f 8005b62: f884 3040 strb.w r3, [r4, #64] @ 0x40 8005b66: f884 3041 strb.w r3, [r4, #65] @ 0x41 8005b6a: f884 3042 strb.w r3, [r4, #66] @ 0x42 8005b6e: f884 3043 strb.w r3, [r4, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005b72: f884 3044 strb.w r3, [r4, #68] @ 0x44 8005b76: f884 3045 strb.w r3, [r4, #69] @ 0x45 8005b7a: f884 3046 strb.w r3, [r4, #70] @ 0x46 8005b7e: f884 3047 strb.w r3, [r4, #71] @ 0x47 htim->State = HAL_TIM_STATE_READY; 8005b82: f884 303d strb.w r3, [r4, #61] @ 0x3d return HAL_OK; 8005b86: 2000 movs r0, #0 } 8005b88: bd10 pop {r4, pc} htim->Lock = HAL_UNLOCKED; 8005b8a: f880 303c strb.w r3, [r0, #60] @ 0x3c HAL_TIM_IC_MspInit(htim); 8005b8e: f7fd fa49 bl 8003024 8005b92: e7d7 b.n 8005b44 return HAL_ERROR; 8005b94: 2001 movs r0, #1 } 8005b96: 4770 bx lr 08005b98 : { 8005b98: b470 push {r4, r5, r6} tmpccer = TIMx->CCER; 8005b9a: 6a03 ldr r3, [r0, #32] TIMx->CCER &= ~TIM_CCER_CC2E; 8005b9c: 6a02 ldr r2, [r0, #32] 8005b9e: f022 0210 bic.w r2, r2, #16 8005ba2: 6202 str r2, [r0, #32] tmpcr2 = TIMx->CR2; 8005ba4: 6845 ldr r5, [r0, #4] tmpccmrx = TIMx->CCMR1; 8005ba6: 6984 ldr r4, [r0, #24] tmpccmrx &= ~TIM_CCMR1_CC2S; 8005ba8: 4e1a ldr r6, [pc, #104] @ (8005c14 ) 8005baa: 4026 ands r6, r4 tmpccmrx |= (OC_Config->OCMode << 8U); 8005bac: 680c ldr r4, [r1, #0] 8005bae: ea46 2604 orr.w r6, r6, r4, lsl #8 tmpccer &= ~TIM_CCER_CC2P; 8005bb2: f023 0320 bic.w r3, r3, #32 tmpccer |= (OC_Config->OCPolarity << 4U); 8005bb6: 688a ldr r2, [r1, #8] 8005bb8: ea43 1302 orr.w r3, r3, r2, lsl #4 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8005bbc: 4a16 ldr r2, [pc, #88] @ (8005c18 ) 8005bbe: 4c17 ldr r4, [pc, #92] @ (8005c1c ) 8005bc0: 42a0 cmp r0, r4 8005bc2: bf18 it ne 8005bc4: 4290 cmpne r0, r2 8005bc6: bf0c ite eq 8005bc8: 2201 moveq r2, #1 8005bca: 2200 movne r2, #0 8005bcc: d106 bne.n 8005bdc tmpccer &= ~TIM_CCER_CC2NP; 8005bce: f023 0380 bic.w r3, r3, #128 @ 0x80 tmpccer |= (OC_Config->OCNPolarity << 4U); 8005bd2: 68cc ldr r4, [r1, #12] 8005bd4: ea43 1304 orr.w r3, r3, r4, lsl #4 tmpccer &= ~TIM_CCER_CC2NE; 8005bd8: f023 0340 bic.w r3, r3, #64 @ 0x40 if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005bdc: b95a cbnz r2, 8005bf6 8005bde: 4a10 ldr r2, [pc, #64] @ (8005c20 ) 8005be0: 4290 cmp r0, r2 8005be2: bf14 ite ne 8005be4: 2200 movne r2, #0 8005be6: 2201 moveq r2, #1 8005be8: 4c0e ldr r4, [pc, #56] @ (8005c24 ) 8005bea: 42a0 cmp r0, r4 8005bec: d003 beq.n 8005bf6 8005bee: b912 cbnz r2, 8005bf6 8005bf0: 4a0d ldr r2, [pc, #52] @ (8005c28 ) 8005bf2: 4290 cmp r0, r2 8005bf4: d107 bne.n 8005c06 tmpcr2 &= ~TIM_CR2_OIS2N; 8005bf6: f425 6c40 bic.w ip, r5, #3072 @ 0xc00 tmpcr2 |= (OC_Config->OCIdleState << 2U); 8005bfa: 694a ldr r2, [r1, #20] 8005bfc: ea4c 0c82 orr.w ip, ip, r2, lsl #2 tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8005c00: 698a ldr r2, [r1, #24] 8005c02: ea4c 0582 orr.w r5, ip, r2, lsl #2 TIMx->CR2 = tmpcr2; 8005c06: 6045 str r5, [r0, #4] TIMx->CCMR1 = tmpccmrx; 8005c08: 6186 str r6, [r0, #24] TIMx->CCR2 = OC_Config->Pulse; 8005c0a: 684a ldr r2, [r1, #4] 8005c0c: 6382 str r2, [r0, #56] @ 0x38 TIMx->CCER = tmpccer; 8005c0e: 6203 str r3, [r0, #32] } 8005c10: bc70 pop {r4, r5, r6} 8005c12: 4770 bx lr 8005c14: feff8cff .word 0xfeff8cff 8005c18: 40010000 .word 0x40010000 8005c1c: 40010400 .word 0x40010400 8005c20: 40014400 .word 0x40014400 8005c24: 40014000 .word 0x40014000 8005c28: 40014800 .word 0x40014800 08005c2c : { 8005c2c: b538 push {r3, r4, r5, lr} __HAL_LOCK(htim); 8005c2e: f890 303c ldrb.w r3, [r0, #60] @ 0x3c 8005c32: 2b01 cmp r3, #1 8005c34: f000 8095 beq.w 8005d62 8005c38: 4604 mov r4, r0 8005c3a: 460d mov r5, r1 8005c3c: 2301 movs r3, #1 8005c3e: f880 303c strb.w r3, [r0, #60] @ 0x3c switch (Channel) 8005c42: 2a14 cmp r2, #20 8005c44: f200 8088 bhi.w 8005d58 8005c48: e8df f002 tbb [pc, r2] 8005c4c: 8686860b .word 0x8686860b 8005c50: 8686861f .word 0x8686861f 8005c54: 86868634 .word 0x86868634 8005c58: 86868648 .word 0x86868648 8005c5c: 8686865d .word 0x8686865d 8005c60: 71 .byte 0x71 8005c61: 00 .byte 0x00 TIM_OC1_SetConfig(htim->Instance, sConfig); 8005c62: 6800 ldr r0, [r0, #0] 8005c64: f7ff fcba bl 80055dc htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8005c68: 6822 ldr r2, [r4, #0] 8005c6a: 6993 ldr r3, [r2, #24] 8005c6c: f043 0308 orr.w r3, r3, #8 8005c70: 6193 str r3, [r2, #24] htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8005c72: 6822 ldr r2, [r4, #0] 8005c74: 6993 ldr r3, [r2, #24] 8005c76: f023 0304 bic.w r3, r3, #4 8005c7a: 6193 str r3, [r2, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8005c7c: 6822 ldr r2, [r4, #0] 8005c7e: 6993 ldr r3, [r2, #24] 8005c80: 6929 ldr r1, [r5, #16] 8005c82: 430b orrs r3, r1 8005c84: 6193 str r3, [r2, #24] HAL_StatusTypeDef status = HAL_OK; 8005c86: 2000 movs r0, #0 break; 8005c88: e067 b.n 8005d5a TIM_OC2_SetConfig(htim->Instance, sConfig); 8005c8a: 6800 ldr r0, [r0, #0] 8005c8c: f7ff ff84 bl 8005b98 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8005c90: 6822 ldr r2, [r4, #0] 8005c92: 6993 ldr r3, [r2, #24] 8005c94: f443 6300 orr.w r3, r3, #2048 @ 0x800 8005c98: 6193 str r3, [r2, #24] htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8005c9a: 6822 ldr r2, [r4, #0] 8005c9c: 6993 ldr r3, [r2, #24] 8005c9e: f423 6380 bic.w r3, r3, #1024 @ 0x400 8005ca2: 6193 str r3, [r2, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8005ca4: 6822 ldr r2, [r4, #0] 8005ca6: 6993 ldr r3, [r2, #24] 8005ca8: 6929 ldr r1, [r5, #16] 8005caa: ea43 2301 orr.w r3, r3, r1, lsl #8 8005cae: 6193 str r3, [r2, #24] HAL_StatusTypeDef status = HAL_OK; 8005cb0: 2000 movs r0, #0 break; 8005cb2: e052 b.n 8005d5a TIM_OC3_SetConfig(htim->Instance, sConfig); 8005cb4: 6800 ldr r0, [r0, #0] 8005cb6: f7ff fce3 bl 8005680 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8005cba: 6822 ldr r2, [r4, #0] 8005cbc: 69d3 ldr r3, [r2, #28] 8005cbe: f043 0308 orr.w r3, r3, #8 8005cc2: 61d3 str r3, [r2, #28] htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8005cc4: 6822 ldr r2, [r4, #0] 8005cc6: 69d3 ldr r3, [r2, #28] 8005cc8: f023 0304 bic.w r3, r3, #4 8005ccc: 61d3 str r3, [r2, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8005cce: 6822 ldr r2, [r4, #0] 8005cd0: 69d3 ldr r3, [r2, #28] 8005cd2: 6929 ldr r1, [r5, #16] 8005cd4: 430b orrs r3, r1 8005cd6: 61d3 str r3, [r2, #28] HAL_StatusTypeDef status = HAL_OK; 8005cd8: 2000 movs r0, #0 break; 8005cda: e03e b.n 8005d5a TIM_OC4_SetConfig(htim->Instance, sConfig); 8005cdc: 6800 ldr r0, [r0, #0] 8005cde: f7ff fd19 bl 8005714 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8005ce2: 6822 ldr r2, [r4, #0] 8005ce4: 69d3 ldr r3, [r2, #28] 8005ce6: f443 6300 orr.w r3, r3, #2048 @ 0x800 8005cea: 61d3 str r3, [r2, #28] htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8005cec: 6822 ldr r2, [r4, #0] 8005cee: 69d3 ldr r3, [r2, #28] 8005cf0: f423 6380 bic.w r3, r3, #1024 @ 0x400 8005cf4: 61d3 str r3, [r2, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8005cf6: 6822 ldr r2, [r4, #0] 8005cf8: 69d3 ldr r3, [r2, #28] 8005cfa: 6929 ldr r1, [r5, #16] 8005cfc: ea43 2301 orr.w r3, r3, r1, lsl #8 8005d00: 61d3 str r3, [r2, #28] HAL_StatusTypeDef status = HAL_OK; 8005d02: 2000 movs r0, #0 break; 8005d04: e029 b.n 8005d5a TIM_OC5_SetConfig(htim->Instance, sConfig); 8005d06: 6800 ldr r0, [r0, #0] 8005d08: f7ff fd3e bl 8005788 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 8005d0c: 6822 ldr r2, [r4, #0] 8005d0e: 6d53 ldr r3, [r2, #84] @ 0x54 8005d10: f043 0308 orr.w r3, r3, #8 8005d14: 6553 str r3, [r2, #84] @ 0x54 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 8005d16: 6822 ldr r2, [r4, #0] 8005d18: 6d53 ldr r3, [r2, #84] @ 0x54 8005d1a: f023 0304 bic.w r3, r3, #4 8005d1e: 6553 str r3, [r2, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 8005d20: 6822 ldr r2, [r4, #0] 8005d22: 6d53 ldr r3, [r2, #84] @ 0x54 8005d24: 6929 ldr r1, [r5, #16] 8005d26: 430b orrs r3, r1 8005d28: 6553 str r3, [r2, #84] @ 0x54 HAL_StatusTypeDef status = HAL_OK; 8005d2a: 2000 movs r0, #0 break; 8005d2c: e015 b.n 8005d5a TIM_OC6_SetConfig(htim->Instance, sConfig); 8005d2e: 6800 ldr r0, [r0, #0] 8005d30: f7ff fd64 bl 80057fc htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 8005d34: 6822 ldr r2, [r4, #0] 8005d36: 6d53 ldr r3, [r2, #84] @ 0x54 8005d38: f443 6300 orr.w r3, r3, #2048 @ 0x800 8005d3c: 6553 str r3, [r2, #84] @ 0x54 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 8005d3e: 6822 ldr r2, [r4, #0] 8005d40: 6d53 ldr r3, [r2, #84] @ 0x54 8005d42: f423 6380 bic.w r3, r3, #1024 @ 0x400 8005d46: 6553 str r3, [r2, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 8005d48: 6822 ldr r2, [r4, #0] 8005d4a: 6d53 ldr r3, [r2, #84] @ 0x54 8005d4c: 6929 ldr r1, [r5, #16] 8005d4e: ea43 2301 orr.w r3, r3, r1, lsl #8 8005d52: 6553 str r3, [r2, #84] @ 0x54 HAL_StatusTypeDef status = HAL_OK; 8005d54: 2000 movs r0, #0 break; 8005d56: e000 b.n 8005d5a switch (Channel) 8005d58: 2001 movs r0, #1 __HAL_UNLOCK(htim); 8005d5a: 2300 movs r3, #0 8005d5c: f884 303c strb.w r3, [r4, #60] @ 0x3c } 8005d60: bd38 pop {r3, r4, r5, pc} __HAL_LOCK(htim); 8005d62: 2002 movs r0, #2 8005d64: e7fc b.n 8005d60 ... 08005d68 : { 8005d68: b470 push {r4, r5, r6} 8005d6a: 4694 mov ip, r2 tmpccer = TIMx->CCER; 8005d6c: 6a06 ldr r6, [r0, #32] TIMx->CCER &= ~TIM_CCER_CC1E; 8005d6e: 6a04 ldr r4, [r0, #32] 8005d70: f024 0401 bic.w r4, r4, #1 8005d74: 6204 str r4, [r0, #32] tmpccmr1 = TIMx->CCMR1; 8005d76: 6984 ldr r4, [r0, #24] if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) 8005d78: 4d1d ldr r5, [pc, #116] @ (8005df0 ) 8005d7a: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000 8005d7e: bf18 it ne 8005d80: 42a8 cmpne r0, r5 8005d82: d023 beq.n 8005dcc 8005d84: 4a1b ldr r2, [pc, #108] @ (8005df4 ) 8005d86: 4290 cmp r0, r2 8005d88: bf14 ite ne 8005d8a: 2200 movne r2, #0 8005d8c: 2201 moveq r2, #1 8005d8e: f5a5 457c sub.w r5, r5, #64512 @ 0xfc00 8005d92: 42a8 cmp r0, r5 8005d94: d01a beq.n 8005dcc 8005d96: b9ca cbnz r2, 8005dcc 8005d98: f102 4280 add.w r2, r2, #1073741824 @ 0x40000000 8005d9c: f502 3282 add.w r2, r2, #66560 @ 0x10400 8005da0: 4290 cmp r0, r2 8005da2: bf14 ite ne 8005da4: 2200 movne r2, #0 8005da6: 2201 moveq r2, #1 8005da8: f505 6500 add.w r5, r5, #2048 @ 0x800 8005dac: 42a8 cmp r0, r5 8005dae: d00d beq.n 8005dcc 8005db0: b962 cbnz r2, 8005dcc 8005db2: 4a11 ldr r2, [pc, #68] @ (8005df8 ) 8005db4: 4290 cmp r0, r2 8005db6: bf14 ite ne 8005db8: 2200 movne r2, #0 8005dba: 2201 moveq r2, #1 8005dbc: f505 6540 add.w r5, r5, #3072 @ 0xc00 8005dc0: 42a8 cmp r0, r5 8005dc2: d003 beq.n 8005dcc 8005dc4: b912 cbnz r2, 8005dcc tmpccmr1 |= TIM_CCMR1_CC1S_0; 8005dc6: f044 0201 orr.w r2, r4, #1 8005dca: e003 b.n 8005dd4 tmpccmr1 &= ~TIM_CCMR1_CC1S; 8005dcc: f024 0203 bic.w r2, r4, #3 tmpccmr1 |= TIM_ICSelection; 8005dd0: ea42 020c orr.w r2, r2, ip tmpccmr1 &= ~TIM_CCMR1_IC1F; 8005dd4: f022 02f0 bic.w r2, r2, #240 @ 0xf0 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); 8005dd8: 011b lsls r3, r3, #4 8005dda: b2db uxtb r3, r3 8005ddc: 4313 orrs r3, r2 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8005dde: f026 020a bic.w r2, r6, #10 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 8005de2: f001 010a and.w r1, r1, #10 8005de6: 4311 orrs r1, r2 TIMx->CCMR1 = tmpccmr1; 8005de8: 6183 str r3, [r0, #24] TIMx->CCER = tmpccer; 8005dea: 6201 str r1, [r0, #32] } 8005dec: bc70 pop {r4, r5, r6} 8005dee: 4770 bx lr 8005df0: 40010000 .word 0x40010000 8005df4: 40000800 .word 0x40000800 8005df8: 40014000 .word 0x40014000 08005dfc : { 8005dfc: b538 push {r3, r4, r5, lr} __HAL_LOCK(htim); 8005dfe: f890 303c ldrb.w r3, [r0, #60] @ 0x3c 8005e02: 2b01 cmp r3, #1 8005e04: d05e beq.n 8005ec4 8005e06: 4604 mov r4, r0 8005e08: 460d mov r5, r1 8005e0a: 2301 movs r3, #1 8005e0c: f880 303c strb.w r3, [r0, #60] @ 0x3c if (Channel == TIM_CHANNEL_1) 8005e10: 2a0c cmp r2, #12 8005e12: d852 bhi.n 8005eba 8005e14: e8df f002 tbb [pc, r2] 8005e18: 51515107 .word 0x51515107 8005e1c: 51515119 .word 0x51515119 8005e20: 5151512c .word 0x5151512c 8005e24: 3e .byte 0x3e 8005e25: 00 .byte 0x00 TIM_TI1_SetConfig(htim->Instance, 8005e26: 68cb ldr r3, [r1, #12] 8005e28: 684a ldr r2, [r1, #4] 8005e2a: 6809 ldr r1, [r1, #0] 8005e2c: 6800 ldr r0, [r0, #0] 8005e2e: f7ff ff9b bl 8005d68 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 8005e32: 6822 ldr r2, [r4, #0] 8005e34: 6993 ldr r3, [r2, #24] 8005e36: f023 030c bic.w r3, r3, #12 8005e3a: 6193 str r3, [r2, #24] htim->Instance->CCMR1 |= sConfig->ICPrescaler; 8005e3c: 6822 ldr r2, [r4, #0] 8005e3e: 6993 ldr r3, [r2, #24] 8005e40: 68a9 ldr r1, [r5, #8] 8005e42: 430b orrs r3, r1 8005e44: 6193 str r3, [r2, #24] HAL_StatusTypeDef status = HAL_OK; 8005e46: 2000 movs r0, #0 8005e48: e038 b.n 8005ebc TIM_TI2_SetConfig(htim->Instance, 8005e4a: 68cb ldr r3, [r1, #12] 8005e4c: 684a ldr r2, [r1, #4] 8005e4e: 6809 ldr r1, [r1, #0] 8005e50: 6800 ldr r0, [r0, #0] 8005e52: f7ff fd20 bl 8005896 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 8005e56: 6822 ldr r2, [r4, #0] 8005e58: 6993 ldr r3, [r2, #24] 8005e5a: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005e5e: 6193 str r3, [r2, #24] htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); 8005e60: 6822 ldr r2, [r4, #0] 8005e62: 6993 ldr r3, [r2, #24] 8005e64: 68a9 ldr r1, [r5, #8] 8005e66: ea43 2301 orr.w r3, r3, r1, lsl #8 8005e6a: 6193 str r3, [r2, #24] HAL_StatusTypeDef status = HAL_OK; 8005e6c: 2000 movs r0, #0 8005e6e: e025 b.n 8005ebc TIM_TI3_SetConfig(htim->Instance, 8005e70: 68cb ldr r3, [r1, #12] 8005e72: 684a ldr r2, [r1, #4] 8005e74: 6809 ldr r1, [r1, #0] 8005e76: 6800 ldr r0, [r0, #0] 8005e78: f7ff fd3c bl 80058f4 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 8005e7c: 6822 ldr r2, [r4, #0] 8005e7e: 69d3 ldr r3, [r2, #28] 8005e80: f023 030c bic.w r3, r3, #12 8005e84: 61d3 str r3, [r2, #28] htim->Instance->CCMR2 |= sConfig->ICPrescaler; 8005e86: 6822 ldr r2, [r4, #0] 8005e88: 69d3 ldr r3, [r2, #28] 8005e8a: 68a9 ldr r1, [r5, #8] 8005e8c: 430b orrs r3, r1 8005e8e: 61d3 str r3, [r2, #28] HAL_StatusTypeDef status = HAL_OK; 8005e90: 2000 movs r0, #0 8005e92: e013 b.n 8005ebc TIM_TI4_SetConfig(htim->Instance, 8005e94: 68cb ldr r3, [r1, #12] 8005e96: 684a ldr r2, [r1, #4] 8005e98: 6809 ldr r1, [r1, #0] 8005e9a: 6800 ldr r0, [r0, #0] 8005e9c: f7ff fd45 bl 800592a htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 8005ea0: 6822 ldr r2, [r4, #0] 8005ea2: 69d3 ldr r3, [r2, #28] 8005ea4: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8005ea8: 61d3 str r3, [r2, #28] htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); 8005eaa: 6822 ldr r2, [r4, #0] 8005eac: 69d3 ldr r3, [r2, #28] 8005eae: 68a9 ldr r1, [r5, #8] 8005eb0: ea43 2301 orr.w r3, r3, r1, lsl #8 8005eb4: 61d3 str r3, [r2, #28] HAL_StatusTypeDef status = HAL_OK; 8005eb6: 2000 movs r0, #0 8005eb8: e000 b.n 8005ebc __HAL_LOCK(htim); 8005eba: 2001 movs r0, #1 __HAL_UNLOCK(htim); 8005ebc: 2300 movs r3, #0 8005ebe: f884 303c strb.w r3, [r4, #60] @ 0x3c } 8005ec2: bd38 pop {r3, r4, r5, pc} __HAL_LOCK(htim); 8005ec4: 2002 movs r0, #2 8005ec6: e7fc b.n 8005ec2 08005ec8 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8005ec8: b410 push {r4} uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8005eca: 6884 ldr r4, [r0, #8] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8005ecc: f424 4c7f bic.w ip, r4, #65280 @ 0xff00 /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8005ed0: ea42 2203 orr.w r2, r2, r3, lsl #8 8005ed4: 430a orrs r2, r1 8005ed6: ea42 020c orr.w r2, r2, ip /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005eda: 6082 str r2, [r0, #8] } 8005edc: f85d 4b04 ldr.w r4, [sp], #4 8005ee0: 4770 bx lr ... 08005ee4 : __HAL_LOCK(htim); 8005ee4: f890 303c ldrb.w r3, [r0, #60] @ 0x3c 8005ee8: 2b01 cmp r3, #1 8005eea: f000 808f beq.w 800600c { 8005eee: b510 push {r4, lr} 8005ef0: 4604 mov r4, r0 __HAL_LOCK(htim); 8005ef2: 2301 movs r3, #1 8005ef4: f880 303c strb.w r3, [r0, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8005ef8: 2302 movs r3, #2 8005efa: f880 303d strb.w r3, [r0, #61] @ 0x3d tmpsmcr = htim->Instance->SMCR; 8005efe: 6802 ldr r2, [r0, #0] 8005f00: 6890 ldr r0, [r2, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8005f02: 4b43 ldr r3, [pc, #268] @ (8006010 ) 8005f04: 4003 ands r3, r0 htim->Instance->SMCR = tmpsmcr; 8005f06: 6093 str r3, [r2, #8] switch (sClockSourceConfig->ClockSource) 8005f08: 680b ldr r3, [r1, #0] 8005f0a: 2b70 cmp r3, #112 @ 0x70 8005f0c: d055 beq.n 8005fba 8005f0e: d831 bhi.n 8005f74 8005f10: 2b50 cmp r3, #80 @ 0x50 8005f12: d06c beq.n 8005fee 8005f14: d81f bhi.n 8005f56 8005f16: 2b40 cmp r3, #64 @ 0x40 8005f18: d10a bne.n 8005f30 TIM_TI1_ConfigInputStage(htim->Instance, 8005f1a: 68ca ldr r2, [r1, #12] 8005f1c: 6849 ldr r1, [r1, #4] 8005f1e: 6820 ldr r0, [r4, #0] 8005f20: f7ff fca6 bl 8005870 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8005f24: 2140 movs r1, #64 @ 0x40 8005f26: 6820 ldr r0, [r4, #0] 8005f28: f7ff fd1a bl 8005960 HAL_StatusTypeDef status = HAL_OK; 8005f2c: 2000 movs r0, #0 break; 8005f2e: e029 b.n 8005f84 switch (sClockSourceConfig->ClockSource) 8005f30: d868 bhi.n 8006004 8005f32: 2b20 cmp r3, #32 8005f34: d003 beq.n 8005f3e 8005f36: d80a bhi.n 8005f4e 8005f38: b10b cbz r3, 8005f3e 8005f3a: 2b10 cmp r3, #16 8005f3c: d105 bne.n 8005f4a TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8005f3e: 4619 mov r1, r3 8005f40: 6820 ldr r0, [r4, #0] 8005f42: f7ff fd0d bl 8005960 HAL_StatusTypeDef status = HAL_OK; 8005f46: 2000 movs r0, #0 break; 8005f48: e01c b.n 8005f84 status = HAL_ERROR; 8005f4a: 2001 movs r0, #1 8005f4c: e01a b.n 8005f84 switch (sClockSourceConfig->ClockSource) 8005f4e: 2b30 cmp r3, #48 @ 0x30 8005f50: d0f5 beq.n 8005f3e status = HAL_ERROR; 8005f52: 2001 movs r0, #1 8005f54: e016 b.n 8005f84 switch (sClockSourceConfig->ClockSource) 8005f56: 2b60 cmp r3, #96 @ 0x60 8005f58: d10a bne.n 8005f70 TIM_TI2_ConfigInputStage(htim->Instance, 8005f5a: 68ca ldr r2, [r1, #12] 8005f5c: 6849 ldr r1, [r1, #4] 8005f5e: 6820 ldr r0, [r4, #0] 8005f60: f7ff fcb4 bl 80058cc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8005f64: 2160 movs r1, #96 @ 0x60 8005f66: 6820 ldr r0, [r4, #0] 8005f68: f7ff fcfa bl 8005960 HAL_StatusTypeDef status = HAL_OK; 8005f6c: 2000 movs r0, #0 break; 8005f6e: e009 b.n 8005f84 status = HAL_ERROR; 8005f70: 2001 movs r0, #1 8005f72: e007 b.n 8005f84 switch (sClockSourceConfig->ClockSource) 8005f74: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8005f78: d02c beq.n 8005fd4 8005f7a: d80a bhi.n 8005f92 8005f7c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005f80: d142 bne.n 8006008 8005f82: 2000 movs r0, #0 htim->State = HAL_TIM_STATE_READY; 8005f84: 2301 movs r3, #1 8005f86: f884 303d strb.w r3, [r4, #61] @ 0x3d __HAL_UNLOCK(htim); 8005f8a: 2300 movs r3, #0 8005f8c: f884 303c strb.w r3, [r4, #60] @ 0x3c } 8005f90: bd10 pop {r4, pc} switch (sClockSourceConfig->ClockSource) 8005f92: 4a20 ldr r2, [pc, #128] @ (8006014 ) 8005f94: 4293 cmp r3, r2 8005f96: d0d2 beq.n 8005f3e 8005f98: d807 bhi.n 8005faa 8005f9a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8005f9e: d0ce beq.n 8005f3e 8005fa0: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 8005fa4: d0cb beq.n 8005f3e status = HAL_ERROR; 8005fa6: 2001 movs r0, #1 8005fa8: e7ec b.n 8005f84 switch (sClockSourceConfig->ClockSource) 8005faa: 4a1b ldr r2, [pc, #108] @ (8006018 ) 8005fac: 4293 cmp r3, r2 8005fae: d0c6 beq.n 8005f3e 8005fb0: 3210 adds r2, #16 8005fb2: 4293 cmp r3, r2 8005fb4: d0c3 beq.n 8005f3e status = HAL_ERROR; 8005fb6: 2001 movs r0, #1 8005fb8: e7e4 b.n 8005f84 TIM_ETR_SetConfig(htim->Instance, 8005fba: 68cb ldr r3, [r1, #12] 8005fbc: 684a ldr r2, [r1, #4] 8005fbe: 6889 ldr r1, [r1, #8] 8005fc0: 6820 ldr r0, [r4, #0] 8005fc2: f7ff ff81 bl 8005ec8 tmpsmcr = htim->Instance->SMCR; 8005fc6: 6822 ldr r2, [r4, #0] 8005fc8: 6893 ldr r3, [r2, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8005fca: f043 0377 orr.w r3, r3, #119 @ 0x77 htim->Instance->SMCR = tmpsmcr; 8005fce: 6093 str r3, [r2, #8] HAL_StatusTypeDef status = HAL_OK; 8005fd0: 2000 movs r0, #0 break; 8005fd2: e7d7 b.n 8005f84 TIM_ETR_SetConfig(htim->Instance, 8005fd4: 68cb ldr r3, [r1, #12] 8005fd6: 684a ldr r2, [r1, #4] 8005fd8: 6889 ldr r1, [r1, #8] 8005fda: 6820 ldr r0, [r4, #0] 8005fdc: f7ff ff74 bl 8005ec8 htim->Instance->SMCR |= TIM_SMCR_ECE; 8005fe0: 6822 ldr r2, [r4, #0] 8005fe2: 6893 ldr r3, [r2, #8] 8005fe4: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8005fe8: 6093 str r3, [r2, #8] HAL_StatusTypeDef status = HAL_OK; 8005fea: 2000 movs r0, #0 break; 8005fec: e7ca b.n 8005f84 TIM_TI1_ConfigInputStage(htim->Instance, 8005fee: 68ca ldr r2, [r1, #12] 8005ff0: 6849 ldr r1, [r1, #4] 8005ff2: 6820 ldr r0, [r4, #0] 8005ff4: f7ff fc3c bl 8005870 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8005ff8: 2150 movs r1, #80 @ 0x50 8005ffa: 6820 ldr r0, [r4, #0] 8005ffc: f7ff fcb0 bl 8005960 HAL_StatusTypeDef status = HAL_OK; 8006000: 2000 movs r0, #0 break; 8006002: e7bf b.n 8005f84 status = HAL_ERROR; 8006004: 2001 movs r0, #1 8006006: e7bd b.n 8005f84 8006008: 2001 movs r0, #1 800600a: e7bb b.n 8005f84 __HAL_LOCK(htim); 800600c: 2002 movs r0, #2 } 800600e: 4770 bx lr 8006010: ffce0088 .word 0xffce0088 8006014: 00100020 .word 0x00100020 8006018: 00100030 .word 0x00100030 0800601c : assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800601c: f890 203c ldrb.w r2, [r0, #60] @ 0x3c 8006020: 2a01 cmp r2, #1 8006022: d045 beq.n 80060b0 { 8006024: b470 push {r4, r5, r6} 8006026: 4603 mov r3, r0 __HAL_LOCK(htim); 8006028: 2201 movs r2, #1 800602a: f880 203c strb.w r2, [r0, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 800602e: 2202 movs r2, #2 8006030: f880 203d strb.w r2, [r0, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8006034: 6802 ldr r2, [r0, #0] 8006036: 6850 ldr r0, [r2, #4] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8006038: 6894 ldr r4, [r2, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800603a: 4e1e ldr r6, [pc, #120] @ (80060b4 ) 800603c: 4d1e ldr r5, [pc, #120] @ (80060b8 ) 800603e: 42aa cmp r2, r5 8006040: bf18 it ne 8006042: 42b2 cmpne r2, r6 8006044: d103 bne.n 800604e { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 8006046: f420 0070 bic.w r0, r0, #15728640 @ 0xf00000 /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 800604a: 684d ldr r5, [r1, #4] 800604c: 4328 orrs r0, r5 } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800604e: f020 0070 bic.w r0, r0, #112 @ 0x70 /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8006052: 680d ldr r5, [r1, #0] 8006054: 4328 orrs r0, r5 /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8006056: 6050 str r0, [r2, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8006058: 681a ldr r2, [r3, #0] 800605a: 4816 ldr r0, [pc, #88] @ (80060b4 ) 800605c: f1b2 4f80 cmp.w r2, #1073741824 @ 0x40000000 8006060: bf18 it ne 8006062: 4282 cmpne r2, r0 8006064: d017 beq.n 8006096 8006066: f5a0 407c sub.w r0, r0, #64512 @ 0xfc00 800606a: 4282 cmp r2, r0 800606c: d013 beq.n 8006096 800606e: f500 6080 add.w r0, r0, #1024 @ 0x400 8006072: 4282 cmp r2, r0 8006074: d00f beq.n 8006096 8006076: f500 6080 add.w r0, r0, #1024 @ 0x400 800607a: 4282 cmp r2, r0 800607c: d00b beq.n 8006096 800607e: f500 4078 add.w r0, r0, #63488 @ 0xf800 8006082: 4282 cmp r2, r0 8006084: d007 beq.n 8006096 8006086: f5a0 406c sub.w r0, r0, #60416 @ 0xec00 800608a: 4282 cmp r2, r0 800608c: d003 beq.n 8006096 800608e: f500 3094 add.w r0, r0, #75776 @ 0x12800 8006092: 4282 cmp r2, r0 8006094: d104 bne.n 80060a0 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8006096: f024 0480 bic.w r4, r4, #128 @ 0x80 /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800609a: 6889 ldr r1, [r1, #8] 800609c: 4321 orrs r1, r4 /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800609e: 6091 str r1, [r2, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80060a0: 2201 movs r2, #1 80060a2: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80060a6: 2000 movs r0, #0 80060a8: f883 003c strb.w r0, [r3, #60] @ 0x3c return HAL_OK; } 80060ac: bc70 pop {r4, r5, r6} 80060ae: 4770 bx lr __HAL_LOCK(htim); 80060b0: 2002 movs r0, #2 } 80060b2: 4770 bx lr 80060b4: 40010000 .word 0x40010000 80060b8: 40010400 .word 0x40010400 080060bc : #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 80060bc: f890 303c ldrb.w r3, [r0, #60] @ 0x3c 80060c0: 2b01 cmp r3, #1 80060c2: d044 beq.n 800614e { 80060c4: b430 push {r4, r5} 80060c6: 4602 mov r2, r0 __HAL_LOCK(htim); 80060c8: 2301 movs r3, #1 80060ca: f880 303c strb.w r3, [r0, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 80060ce: 68cb ldr r3, [r1, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 80060d0: f423 7340 bic.w r3, r3, #768 @ 0x300 80060d4: 6888 ldr r0, [r1, #8] 80060d6: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 80060d8: f423 6380 bic.w r3, r3, #1024 @ 0x400 80060dc: 6848 ldr r0, [r1, #4] 80060de: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 80060e0: f423 6300 bic.w r3, r3, #2048 @ 0x800 80060e4: 6808 ldr r0, [r1, #0] 80060e6: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 80060e8: f423 5380 bic.w r3, r3, #4096 @ 0x1000 80060ec: 6908 ldr r0, [r1, #16] 80060ee: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 80060f0: f423 5300 bic.w r3, r3, #8192 @ 0x2000 80060f4: 6948 ldr r0, [r1, #20] 80060f6: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 80060f8: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80060fc: 6b08 ldr r0, [r1, #48] @ 0x30 80060fe: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 8006100: f423 2370 bic.w r3, r3, #983040 @ 0xf0000 8006104: 6988 ldr r0, [r1, #24] 8006106: ea43 4300 orr.w r3, r3, r0, lsl #16 #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); 800610a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800610e: 69c8 ldr r0, [r1, #28] 8006110: 4303 orrs r3, r0 #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 8006112: 6810 ldr r0, [r2, #0] 8006114: 4d0f ldr r5, [pc, #60] @ (8006154 ) 8006116: 4c10 ldr r4, [pc, #64] @ (8006158 ) 8006118: 42a0 cmp r0, r4 800611a: bf18 it ne 800611c: 42a8 cmpne r0, r5 800611e: d110 bne.n 8006142 #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 8006120: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 8006124: 6a8c ldr r4, [r1, #40] @ 0x28 8006126: ea43 5304 orr.w r3, r3, r4, lsl #20 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 800612a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800612e: 6a0c ldr r4, [r1, #32] 8006130: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 8006132: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000 8006136: 6a4c ldr r4, [r1, #36] @ 0x24 8006138: 4323 orrs r3, r4 #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); 800613a: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 800613e: 6ac9 ldr r1, [r1, #44] @ 0x2c 8006140: 430b orrs r3, r1 #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 8006142: 6443 str r3, [r0, #68] @ 0x44 __HAL_UNLOCK(htim); 8006144: 2000 movs r0, #0 8006146: f882 003c strb.w r0, [r2, #60] @ 0x3c return HAL_OK; } 800614a: bc30 pop {r4, r5} 800614c: 4770 bx lr __HAL_LOCK(htim); 800614e: 2002 movs r0, #2 } 8006150: 4770 bx lr 8006152: bf00 nop 8006154: 40010000 .word 0x40010000 8006158: 40010400 .word 0x40010400 0800615c : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800615c: e7fe b.n 800615c 0800615e : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800615e: e7fe b.n 800615e 08006160 : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8006160: e7fe b.n 8006160 08006162 : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8006162: e7fe b.n 8006162 08006164 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8006164: e7fe b.n 8006164 08006166 : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8006166: 4770 bx lr 08006168 : /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8006168: 4770 bx lr 0800616a : /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800616a: 4770 bx lr 0800616c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800616c: b508 push {r3, lr} /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800616e: f7fa fce9 bl 8000b44 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8006172: bd08 pop {r3, pc} 08006174 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8006174: b508 push {r3, lr} /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8006176: 4802 ldr r0, [pc, #8] @ (8006180 ) 8006178: f7fb fea8 bl 8001ecc /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 800617c: bd08 pop {r3, pc} 800617e: bf00 nop 8006180: 200002e8 .word 0x200002e8 08006184 : /** * @brief This function handles ADC1 and ADC2 global interrupts. */ void ADC_IRQHandler(void) { 8006184: b508 push {r3, lr} /* USER CODE BEGIN ADC_IRQn 0 */ /* USER CODE END ADC_IRQn 0 */ HAL_ADC_IRQHandler(&hadc1); 8006186: 4802 ldr r0, [pc, #8] @ (8006190 ) 8006188: f7fa fd4a bl 8000c20 /* USER CODE BEGIN ADC_IRQn 1 */ /* USER CODE END ADC_IRQn 1 */ } 800618c: bd08 pop {r3, pc} 800618e: bf00 nop 8006190: 20000360 .word 0x20000360 08006194 : __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8006194: 4a2b ldr r2, [pc, #172] @ (8006244 ) 8006196: f8d2 3088 ldr.w r3, [r2, #136] @ 0x88 800619a: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800619e: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80061a2: 4b29 ldr r3, [pc, #164] @ (8006248 ) 80061a4: 681b ldr r3, [r3, #0] 80061a6: f003 030f and.w r3, r3, #15 80061aa: 2b02 cmp r3, #2 80061ac: d806 bhi.n 80061bc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80061ae: 4a26 ldr r2, [pc, #152] @ (8006248 ) 80061b0: 6813 ldr r3, [r2, #0] 80061b2: f023 030f bic.w r3, r3, #15 80061b6: f043 0303 orr.w r3, r3, #3 80061ba: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 80061bc: 4b23 ldr r3, [pc, #140] @ (800624c ) 80061be: 681a ldr r2, [r3, #0] 80061c0: f042 0201 orr.w r2, r2, #1 80061c4: 601a str r2, [r3, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 80061c6: 2200 movs r2, #0 80061c8: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 80061ca: 6819 ldr r1, [r3, #0] 80061cc: 4a20 ldr r2, [pc, #128] @ (8006250 ) 80061ce: 400a ands r2, r1 80061d0: 601a str r2, [r3, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80061d2: 4b1d ldr r3, [pc, #116] @ (8006248 ) 80061d4: 681b ldr r3, [r3, #0] 80061d6: f013 0f0c tst.w r3, #12 80061da: d006 beq.n 80061ea { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80061dc: 4a1a ldr r2, [pc, #104] @ (8006248 ) 80061de: 6813 ldr r3, [r2, #0] 80061e0: f023 030f bic.w r3, r3, #15 80061e4: f043 0303 orr.w r3, r3, #3 80061e8: 6013 str r3, [r2, #0] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; #else /* Reset CDCFGR1 register */ RCC->CDCFGR1 = 0x00000000; 80061ea: 4b18 ldr r3, [pc, #96] @ (800624c ) 80061ec: 2200 movs r2, #0 80061ee: 619a str r2, [r3, #24] /* Reset CDCFGR2 register */ RCC->CDCFGR2 = 0x00000000; 80061f0: 61da str r2, [r3, #28] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; 80061f2: 621a str r2, [r3, #32] #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 80061f4: 4917 ldr r1, [pc, #92] @ (8006254 ) 80061f6: 6299 str r1, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 80061f8: 4917 ldr r1, [pc, #92] @ (8006258 ) 80061fa: 62d9 str r1, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 80061fc: 4917 ldr r1, [pc, #92] @ (800625c ) 80061fe: 6319 str r1, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 8006200: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8006202: 6399 str r1, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 8006204: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 8006206: 6419 str r1, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8006208: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 800620a: 6819 ldr r1, [r3, #0] 800620c: f421 2180 bic.w r1, r1, #262144 @ 0x40000 8006210: 6019 str r1, [r3, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8006212: 661a str r2, [r3, #96] @ 0x60 #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #else if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) 8006214: f8d3 3134 ldr.w r3, [r3, #308] @ 0x134 8006218: f413 5f80 tst.w r3, #4096 @ 0x1000 800621c: d110 bne.n 8006240 { /* Enable the FMC interface clock */ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 800621e: 4b0b ldr r3, [pc, #44] @ (800624c ) 8006220: f8d3 2134 ldr.w r2, [r3, #308] @ 0x134 8006224: f442 5280 orr.w r2, r2, #4096 @ 0x1000 8006228: f8c3 2134 str.w r2, [r3, #308] @ 0x134 /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 800622c: 4a0c ldr r2, [pc, #48] @ (8006260 ) 800622e: f243 01d2 movw r1, #12498 @ 0x30d2 8006232: 6011 str r1, [r2, #0] /* Disable the FMC interface clock */ CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); 8006234: f8d3 2134 ldr.w r2, [r3, #308] @ 0x134 8006238: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800623c: f8c3 2134 str.w r2, [r3, #308] @ 0x134 #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8006240: 4770 bx lr 8006242: bf00 nop 8006244: e000ed00 .word 0xe000ed00 8006248: 52002000 .word 0x52002000 800624c: 58024400 .word 0x58024400 8006250: eaf6ed7f .word 0xeaf6ed7f 8006254: 02020200 .word 0x02020200 8006258: 01ff0000 .word 0x01ff0000 800625c: 01010280 .word 0x01010280 8006260: 52004000 .word 0x52004000 08006264 : #if defined(SMPS) /* Exit Run* mode by disabling SMPS and enabling LDO */ PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; #else /* Enable LDO mode */ PWR->CR3 |= PWR_CR3_LDOEN; 8006264: 4a05 ldr r2, [pc, #20] @ (800627c ) 8006266: 68d3 ldr r3, [r2, #12] 8006268: f043 0302 orr.w r3, r3, #2 800626c: 60d3 str r3, [r2, #12] #endif /* SMPS */ /* Wait till voltage level flag is set */ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) 800626e: 4b03 ldr r3, [pc, #12] @ (800627c ) 8006270: 685b ldr r3, [r3, #4] 8006272: f413 5f00 tst.w r3, #8192 @ 0x2000 8006276: d0fa beq.n 800626e while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) {} #else /* No system power supply configuration is selected at exit Run* mode */ #endif /* USE_PWR_LDO_SUPPLY */ } 8006278: 4770 bx lr 800627a: bf00 nop 800627c: 58024800 .word 0x58024800 08006280 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8006280: f8df d038 ldr.w sp, [pc, #56] @ 80062bc /* Call the ExitRun0Mode function to configure the power supply */ bl ExitRun0Mode 8006284: f7ff ffee bl 8006264 /* Call the clock system initialization function.*/ bl SystemInit 8006288: f7ff ff84 bl 8006194 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800628c: 480c ldr r0, [pc, #48] @ (80062c0 ) ldr r1, =_edata 800628e: 490d ldr r1, [pc, #52] @ (80062c4 ) ldr r2, =_sidata 8006290: 4a0d ldr r2, [pc, #52] @ (80062c8 ) movs r3, #0 8006292: 2300 movs r3, #0 b LoopCopyDataInit 8006294: e002 b.n 800629c 08006296 : CopyDataInit: ldr r4, [r2, r3] 8006296: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8006298: 50c4 str r4, [r0, r3] adds r3, r3, #4 800629a: 3304 adds r3, #4 0800629c : LoopCopyDataInit: adds r4, r0, r3 800629c: 18c4 adds r4, r0, r3 cmp r4, r1 800629e: 428c cmp r4, r1 bcc CopyDataInit 80062a0: d3f9 bcc.n 8006296 /* Zero fill the bss segment. */ ldr r2, =_sbss 80062a2: 4a0a ldr r2, [pc, #40] @ (80062cc ) ldr r4, =_ebss 80062a4: 4c0a ldr r4, [pc, #40] @ (80062d0 ) movs r3, #0 80062a6: 2300 movs r3, #0 b LoopFillZerobss 80062a8: e001 b.n 80062ae 080062aa : FillZerobss: str r3, [r2] 80062aa: 6013 str r3, [r2, #0] adds r2, r2, #4 80062ac: 3204 adds r2, #4 080062ae : LoopFillZerobss: cmp r2, r4 80062ae: 42a2 cmp r2, r4 bcc FillZerobss 80062b0: d3fb bcc.n 80062aa /* Call static constructors */ bl __libc_init_array 80062b2: f000 f819 bl 80062e8 <__libc_init_array> /* Call the application's entry point.*/ bl main 80062b6: f7fa fb91 bl 80009dc
bx lr 80062ba: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80062bc: 20020000 .word 0x20020000 ldr r0, =_sdata 80062c0: 20000000 .word 0x20000000 ldr r1, =_edata 80062c4: 20000010 .word 0x20000010 ldr r2, =_sidata 80062c8: 080063d0 .word 0x080063d0 ldr r2, =_sbss 80062cc: 20000010 .word 0x20000010 ldr r4, =_ebss 80062d0: 200003cc .word 0x200003cc 080062d4 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80062d4: e7fe b.n 80062d4 080062d6 : 80062d6: 4402 add r2, r0 80062d8: 4603 mov r3, r0 80062da: 4293 cmp r3, r2 80062dc: d100 bne.n 80062e0 80062de: 4770 bx lr 80062e0: f803 1b01 strb.w r1, [r3], #1 80062e4: e7f9 b.n 80062da ... 080062e8 <__libc_init_array>: 80062e8: b570 push {r4, r5, r6, lr} 80062ea: 4b0d ldr r3, [pc, #52] @ (8006320 <__libc_init_array+0x38>) 80062ec: 4d0d ldr r5, [pc, #52] @ (8006324 <__libc_init_array+0x3c>) 80062ee: 1b5b subs r3, r3, r5 80062f0: 109c asrs r4, r3, #2 80062f2: 2600 movs r6, #0 80062f4: 42a6 cmp r6, r4 80062f6: d109 bne.n 800630c <__libc_init_array+0x24> 80062f8: f000 f828 bl 800634c <_init> 80062fc: 4d0a ldr r5, [pc, #40] @ (8006328 <__libc_init_array+0x40>) 80062fe: 4b0b ldr r3, [pc, #44] @ (800632c <__libc_init_array+0x44>) 8006300: 1b5b subs r3, r3, r5 8006302: 109c asrs r4, r3, #2 8006304: 2600 movs r6, #0 8006306: 42a6 cmp r6, r4 8006308: d105 bne.n 8006316 <__libc_init_array+0x2e> 800630a: bd70 pop {r4, r5, r6, pc} 800630c: f855 3b04 ldr.w r3, [r5], #4 8006310: 4798 blx r3 8006312: 3601 adds r6, #1 8006314: e7ee b.n 80062f4 <__libc_init_array+0xc> 8006316: f855 3b04 ldr.w r3, [r5], #4 800631a: 4798 blx r3 800631c: 3601 adds r6, #1 800631e: e7f2 b.n 8006306 <__libc_init_array+0x1e> 8006320: 080063c8 .word 0x080063c8 8006324: 080063c8 .word 0x080063c8 8006328: 080063c8 .word 0x080063c8 800632c: 080063cc .word 0x080063cc 08006330 : 8006330: 440a add r2, r1 8006332: 4291 cmp r1, r2 8006334: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8006338: d100 bne.n 800633c 800633a: 4770 bx lr 800633c: b510 push {r4, lr} 800633e: f811 4b01 ldrb.w r4, [r1], #1 8006342: f803 4f01 strb.w r4, [r3, #1]! 8006346: 4291 cmp r1, r2 8006348: d1f9 bne.n 800633e 800634a: bd10 pop {r4, pc} 0800634c <_init>: 800634c: b5f8 push {r3, r4, r5, r6, r7, lr} 800634e: bf00 nop 8006350: bcf8 pop {r3, r4, r5, r6, r7} 8006352: bc08 pop {r3} 8006354: 469e mov lr, r3 8006356: 4770 bx lr 08006358 <_fini>: 8006358: b5f8 push {r3, r4, r5, r6, r7, lr} 800635a: bf00 nop 800635c: bcf8 pop {r3, r4, r5, r6, r7} 800635e: bc08 pop {r3} 8006360: 469e mov lr, r3 8006362: 4770 bx lr