18139 lines
701 KiB
Plaintext
18139 lines
701 KiB
Plaintext
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PDU_FT25.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 000070b4 08000188 08000188 00001188 2**3
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000038 0800723c 0800723c 0000823c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08007274 08007274 0000900c 2**0
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CONTENTS
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4 .ARM 00000000 08007274 08007274 0000900c 2**0
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CONTENTS
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5 .preinit_array 00000000 08007274 08007274 0000900c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08007274 08007274 00008274 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08007278 08007278 00008278 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 0000000c 20000000 0800727c 00009000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 000002f4 2000000c 08007288 0000900c 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000300 08007288 00009300 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0000900c 2**0
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CONTENTS, READONLY
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12 .debug_info 00015a5c 00000000 00000000 0000903c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00002f4b 00000000 00000000 0001ea98 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00001148 00000000 00000000 000219e8 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 00000d74 00000000 00000000 00022b30 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 0001ea2e 00000000 00000000 000238a4 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 000170a1 00000000 00000000 000422d2 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000b7df6 00000000 00000000 00059373 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 00111169 2**0
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CONTENTS, READONLY
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20 .debug_frame 0000494c 00000000 00000000 001111ac 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000071 00000000 00000000 00115af8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000188 <__do_global_dtors_aux>:
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8000188: b510 push {r4, lr}
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800018a: 4c05 ldr r4, [pc, #20] @ (80001a0 <__do_global_dtors_aux+0x18>)
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800018c: 7823 ldrb r3, [r4, #0]
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800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
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8000190: 4b04 ldr r3, [pc, #16] @ (80001a4 <__do_global_dtors_aux+0x1c>)
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8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
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8000194: 4804 ldr r0, [pc, #16] @ (80001a8 <__do_global_dtors_aux+0x20>)
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8000196: f3af 8000 nop.w
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800019a: 2301 movs r3, #1
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800019c: 7023 strb r3, [r4, #0]
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800019e: bd10 pop {r4, pc}
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80001a0: 2000000c .word 0x2000000c
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80001a4: 00000000 .word 0x00000000
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80001a8: 08007224 .word 0x08007224
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080001ac <frame_dummy>:
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80001ac: b508 push {r3, lr}
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80001ae: 4b03 ldr r3, [pc, #12] @ (80001bc <frame_dummy+0x10>)
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80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
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80001b2: 4903 ldr r1, [pc, #12] @ (80001c0 <frame_dummy+0x14>)
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80001b4: 4803 ldr r0, [pc, #12] @ (80001c4 <frame_dummy+0x18>)
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80001b6: f3af 8000 nop.w
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80001ba: bd08 pop {r3, pc}
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80001bc: 00000000 .word 0x00000000
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80001c0: 20000010 .word 0x20000010
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80001c4: 08007224 .word 0x08007224
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080001c8 <__aeabi_dmul>:
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80001c8: b570 push {r4, r5, r6, lr}
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80001ca: f04f 0cff mov.w ip, #255 @ 0xff
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80001ce: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
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80001d2: ea1c 5411 ands.w r4, ip, r1, lsr #20
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80001d6: bf1d ittte ne
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80001d8: ea1c 5513 andsne.w r5, ip, r3, lsr #20
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80001dc: ea94 0f0c teqne r4, ip
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80001e0: ea95 0f0c teqne r5, ip
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80001e4: f000 f8de bleq 80003a4 <__aeabi_dmul+0x1dc>
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80001e8: 442c add r4, r5
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80001ea: ea81 0603 eor.w r6, r1, r3
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80001ee: ea21 514c bic.w r1, r1, ip, lsl #21
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80001f2: ea23 534c bic.w r3, r3, ip, lsl #21
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80001f6: ea50 3501 orrs.w r5, r0, r1, lsl #12
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80001fa: bf18 it ne
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80001fc: ea52 3503 orrsne.w r5, r2, r3, lsl #12
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8000200: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
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8000204: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
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8000208: d038 beq.n 800027c <__aeabi_dmul+0xb4>
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800020a: fba0 ce02 umull ip, lr, r0, r2
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800020e: f04f 0500 mov.w r5, #0
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8000212: fbe1 e502 umlal lr, r5, r1, r2
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8000216: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
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800021a: fbe0 e503 umlal lr, r5, r0, r3
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800021e: f04f 0600 mov.w r6, #0
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8000222: fbe1 5603 umlal r5, r6, r1, r3
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8000226: f09c 0f00 teq ip, #0
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800022a: bf18 it ne
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800022c: f04e 0e01 orrne.w lr, lr, #1
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8000230: f1a4 04ff sub.w r4, r4, #255 @ 0xff
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8000234: f5b6 7f00 cmp.w r6, #512 @ 0x200
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8000238: f564 7440 sbc.w r4, r4, #768 @ 0x300
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800023c: d204 bcs.n 8000248 <__aeabi_dmul+0x80>
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800023e: ea5f 0e4e movs.w lr, lr, lsl #1
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8000242: 416d adcs r5, r5
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8000244: eb46 0606 adc.w r6, r6, r6
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8000248: ea42 21c6 orr.w r1, r2, r6, lsl #11
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800024c: ea41 5155 orr.w r1, r1, r5, lsr #21
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8000250: ea4f 20c5 mov.w r0, r5, lsl #11
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8000254: ea40 505e orr.w r0, r0, lr, lsr #21
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8000258: ea4f 2ece mov.w lr, lr, lsl #11
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800025c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
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8000260: bf88 it hi
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8000262: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
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8000266: d81e bhi.n 80002a6 <__aeabi_dmul+0xde>
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8000268: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
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800026c: bf08 it eq
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800026e: ea5f 0e50 movseq.w lr, r0, lsr #1
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8000272: f150 0000 adcs.w r0, r0, #0
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8000276: eb41 5104 adc.w r1, r1, r4, lsl #20
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800027a: bd70 pop {r4, r5, r6, pc}
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800027c: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
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8000280: ea46 0101 orr.w r1, r6, r1
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8000284: ea40 0002 orr.w r0, r0, r2
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8000288: ea81 0103 eor.w r1, r1, r3
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800028c: ebb4 045c subs.w r4, r4, ip, lsr #1
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8000290: bfc2 ittt gt
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8000292: ebd4 050c rsbsgt r5, r4, ip
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8000296: ea41 5104 orrgt.w r1, r1, r4, lsl #20
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800029a: bd70 popgt {r4, r5, r6, pc}
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800029c: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
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80002a0: f04f 0e00 mov.w lr, #0
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80002a4: 3c01 subs r4, #1
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80002a6: f300 80ab bgt.w 8000400 <__aeabi_dmul+0x238>
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80002aa: f114 0f36 cmn.w r4, #54 @ 0x36
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80002ae: bfde ittt le
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80002b0: 2000 movle r0, #0
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80002b2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
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80002b6: bd70 pople {r4, r5, r6, pc}
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80002b8: f1c4 0400 rsb r4, r4, #0
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80002bc: 3c20 subs r4, #32
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80002be: da35 bge.n 800032c <__aeabi_dmul+0x164>
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80002c0: 340c adds r4, #12
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80002c2: dc1b bgt.n 80002fc <__aeabi_dmul+0x134>
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80002c4: f104 0414 add.w r4, r4, #20
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80002c8: f1c4 0520 rsb r5, r4, #32
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80002cc: fa00 f305 lsl.w r3, r0, r5
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80002d0: fa20 f004 lsr.w r0, r0, r4
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80002d4: fa01 f205 lsl.w r2, r1, r5
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80002d8: ea40 0002 orr.w r0, r0, r2
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80002dc: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
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80002e0: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
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80002e4: eb10 70d3 adds.w r0, r0, r3, lsr #31
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80002e8: fa21 f604 lsr.w r6, r1, r4
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80002ec: eb42 0106 adc.w r1, r2, r6
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80002f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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80002f4: bf08 it eq
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80002f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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80002fa: bd70 pop {r4, r5, r6, pc}
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80002fc: f1c4 040c rsb r4, r4, #12
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8000300: f1c4 0520 rsb r5, r4, #32
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8000304: fa00 f304 lsl.w r3, r0, r4
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8000308: fa20 f005 lsr.w r0, r0, r5
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800030c: fa01 f204 lsl.w r2, r1, r4
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8000310: ea40 0002 orr.w r0, r0, r2
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8000314: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
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8000318: eb10 70d3 adds.w r0, r0, r3, lsr #31
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800031c: f141 0100 adc.w r1, r1, #0
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8000320: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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8000324: bf08 it eq
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8000326: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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800032a: bd70 pop {r4, r5, r6, pc}
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800032c: f1c4 0520 rsb r5, r4, #32
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8000330: fa00 f205 lsl.w r2, r0, r5
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8000334: ea4e 0e02 orr.w lr, lr, r2
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8000338: fa20 f304 lsr.w r3, r0, r4
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800033c: fa01 f205 lsl.w r2, r1, r5
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8000340: ea43 0302 orr.w r3, r3, r2
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8000344: fa21 f004 lsr.w r0, r1, r4
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8000348: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
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800034c: fa21 f204 lsr.w r2, r1, r4
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8000350: ea20 0002 bic.w r0, r0, r2
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8000354: eb00 70d3 add.w r0, r0, r3, lsr #31
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8000358: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
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800035c: bf08 it eq
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800035e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
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8000362: bd70 pop {r4, r5, r6, pc}
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8000364: f094 0f00 teq r4, #0
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8000368: d10f bne.n 800038a <__aeabi_dmul+0x1c2>
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800036a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
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800036e: 0040 lsls r0, r0, #1
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8000370: eb41 0101 adc.w r1, r1, r1
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8000374: f411 1f80 tst.w r1, #1048576 @ 0x100000
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8000378: bf08 it eq
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800037a: 3c01 subeq r4, #1
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800037c: d0f7 beq.n 800036e <__aeabi_dmul+0x1a6>
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800037e: ea41 0106 orr.w r1, r1, r6
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8000382: f095 0f00 teq r5, #0
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8000386: bf18 it ne
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8000388: 4770 bxne lr
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800038a: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
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800038e: 0052 lsls r2, r2, #1
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8000390: eb43 0303 adc.w r3, r3, r3
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8000394: f413 1f80 tst.w r3, #1048576 @ 0x100000
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8000398: bf08 it eq
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800039a: 3d01 subeq r5, #1
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800039c: d0f7 beq.n 800038e <__aeabi_dmul+0x1c6>
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800039e: ea43 0306 orr.w r3, r3, r6
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80003a2: 4770 bx lr
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80003a4: ea94 0f0c teq r4, ip
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80003a8: ea0c 5513 and.w r5, ip, r3, lsr #20
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80003ac: bf18 it ne
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80003ae: ea95 0f0c teqne r5, ip
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80003b2: d00c beq.n 80003ce <__aeabi_dmul+0x206>
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80003b4: ea50 0641 orrs.w r6, r0, r1, lsl #1
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80003b8: bf18 it ne
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80003ba: ea52 0643 orrsne.w r6, r2, r3, lsl #1
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80003be: d1d1 bne.n 8000364 <__aeabi_dmul+0x19c>
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80003c0: ea81 0103 eor.w r1, r1, r3
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80003c4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
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80003c8: f04f 0000 mov.w r0, #0
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80003cc: bd70 pop {r4, r5, r6, pc}
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80003ce: ea50 0641 orrs.w r6, r0, r1, lsl #1
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80003d2: bf06 itte eq
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80003d4: 4610 moveq r0, r2
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80003d6: 4619 moveq r1, r3
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80003d8: ea52 0643 orrsne.w r6, r2, r3, lsl #1
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80003dc: d019 beq.n 8000412 <__aeabi_dmul+0x24a>
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80003de: ea94 0f0c teq r4, ip
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80003e2: d102 bne.n 80003ea <__aeabi_dmul+0x222>
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80003e4: ea50 3601 orrs.w r6, r0, r1, lsl #12
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80003e8: d113 bne.n 8000412 <__aeabi_dmul+0x24a>
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80003ea: ea95 0f0c teq r5, ip
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80003ee: d105 bne.n 80003fc <__aeabi_dmul+0x234>
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80003f0: ea52 3603 orrs.w r6, r2, r3, lsl #12
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80003f4: bf1c itt ne
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80003f6: 4610 movne r0, r2
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80003f8: 4619 movne r1, r3
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80003fa: d10a bne.n 8000412 <__aeabi_dmul+0x24a>
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80003fc: ea81 0103 eor.w r1, r1, r3
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8000400: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
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8000404: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
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8000408: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
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800040c: f04f 0000 mov.w r0, #0
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8000410: bd70 pop {r4, r5, r6, pc}
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8000412: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
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8000416: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
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800041a: bd70 pop {r4, r5, r6, pc}
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0800041c <__aeabi_drsub>:
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800041c: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
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8000420: e002 b.n 8000428 <__adddf3>
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8000422: bf00 nop
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08000424 <__aeabi_dsub>:
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8000424: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
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08000428 <__adddf3>:
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8000428: b530 push {r4, r5, lr}
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800042a: ea4f 0441 mov.w r4, r1, lsl #1
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800042e: ea4f 0543 mov.w r5, r3, lsl #1
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8000432: ea94 0f05 teq r4, r5
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8000436: bf08 it eq
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8000438: ea90 0f02 teqeq r0, r2
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800043c: bf1f itttt ne
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800043e: ea54 0c00 orrsne.w ip, r4, r0
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8000442: ea55 0c02 orrsne.w ip, r5, r2
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8000446: ea7f 5c64 mvnsne.w ip, r4, asr #21
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800044a: ea7f 5c65 mvnsne.w ip, r5, asr #21
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800044e: f000 80e2 beq.w 8000616 <__adddf3+0x1ee>
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8000452: ea4f 5454 mov.w r4, r4, lsr #21
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8000456: ebd4 5555 rsbs r5, r4, r5, lsr #21
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800045a: bfb8 it lt
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800045c: 426d neglt r5, r5
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800045e: dd0c ble.n 800047a <__adddf3+0x52>
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8000460: 442c add r4, r5
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8000462: ea80 0202 eor.w r2, r0, r2
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8000466: ea81 0303 eor.w r3, r1, r3
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800046a: ea82 0000 eor.w r0, r2, r0
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800046e: ea83 0101 eor.w r1, r3, r1
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8000472: ea80 0202 eor.w r2, r0, r2
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8000476: ea81 0303 eor.w r3, r1, r3
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800047a: 2d36 cmp r5, #54 @ 0x36
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800047c: bf88 it hi
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800047e: bd30 pophi {r4, r5, pc}
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8000480: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
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8000484: ea4f 3101 mov.w r1, r1, lsl #12
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8000488: f44f 1c80 mov.w ip, #1048576 @ 0x100000
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800048c: ea4c 3111 orr.w r1, ip, r1, lsr #12
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8000490: d002 beq.n 8000498 <__adddf3+0x70>
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8000492: 4240 negs r0, r0
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8000494: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
8000498: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
|
|
800049c: ea4f 3303 mov.w r3, r3, lsl #12
|
|
80004a0: ea4c 3313 orr.w r3, ip, r3, lsr #12
|
|
80004a4: d002 beq.n 80004ac <__adddf3+0x84>
|
|
80004a6: 4252 negs r2, r2
|
|
80004a8: eb63 0343 sbc.w r3, r3, r3, lsl #1
|
|
80004ac: ea94 0f05 teq r4, r5
|
|
80004b0: f000 80a7 beq.w 8000602 <__adddf3+0x1da>
|
|
80004b4: f1a4 0401 sub.w r4, r4, #1
|
|
80004b8: f1d5 0e20 rsbs lr, r5, #32
|
|
80004bc: db0d blt.n 80004da <__adddf3+0xb2>
|
|
80004be: fa02 fc0e lsl.w ip, r2, lr
|
|
80004c2: fa22 f205 lsr.w r2, r2, r5
|
|
80004c6: 1880 adds r0, r0, r2
|
|
80004c8: f141 0100 adc.w r1, r1, #0
|
|
80004cc: fa03 f20e lsl.w r2, r3, lr
|
|
80004d0: 1880 adds r0, r0, r2
|
|
80004d2: fa43 f305 asr.w r3, r3, r5
|
|
80004d6: 4159 adcs r1, r3
|
|
80004d8: e00e b.n 80004f8 <__adddf3+0xd0>
|
|
80004da: f1a5 0520 sub.w r5, r5, #32
|
|
80004de: f10e 0e20 add.w lr, lr, #32
|
|
80004e2: 2a01 cmp r2, #1
|
|
80004e4: fa03 fc0e lsl.w ip, r3, lr
|
|
80004e8: bf28 it cs
|
|
80004ea: f04c 0c02 orrcs.w ip, ip, #2
|
|
80004ee: fa43 f305 asr.w r3, r3, r5
|
|
80004f2: 18c0 adds r0, r0, r3
|
|
80004f4: eb51 71e3 adcs.w r1, r1, r3, asr #31
|
|
80004f8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
80004fc: d507 bpl.n 800050e <__adddf3+0xe6>
|
|
80004fe: f04f 0e00 mov.w lr, #0
|
|
8000502: f1dc 0c00 rsbs ip, ip, #0
|
|
8000506: eb7e 0000 sbcs.w r0, lr, r0
|
|
800050a: eb6e 0101 sbc.w r1, lr, r1
|
|
800050e: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
|
|
8000512: d31b bcc.n 800054c <__adddf3+0x124>
|
|
8000514: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
|
|
8000518: d30c bcc.n 8000534 <__adddf3+0x10c>
|
|
800051a: 0849 lsrs r1, r1, #1
|
|
800051c: ea5f 0030 movs.w r0, r0, rrx
|
|
8000520: ea4f 0c3c mov.w ip, ip, rrx
|
|
8000524: f104 0401 add.w r4, r4, #1
|
|
8000528: ea4f 5244 mov.w r2, r4, lsl #21
|
|
800052c: f512 0f80 cmn.w r2, #4194304 @ 0x400000
|
|
8000530: f080 809a bcs.w 8000668 <__adddf3+0x240>
|
|
8000534: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
|
|
8000538: bf08 it eq
|
|
800053a: ea5f 0c50 movseq.w ip, r0, lsr #1
|
|
800053e: f150 0000 adcs.w r0, r0, #0
|
|
8000542: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
8000546: ea41 0105 orr.w r1, r1, r5
|
|
800054a: bd30 pop {r4, r5, pc}
|
|
800054c: ea5f 0c4c movs.w ip, ip, lsl #1
|
|
8000550: 4140 adcs r0, r0
|
|
8000552: eb41 0101 adc.w r1, r1, r1
|
|
8000556: 3c01 subs r4, #1
|
|
8000558: bf28 it cs
|
|
800055a: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
|
|
800055e: d2e9 bcs.n 8000534 <__adddf3+0x10c>
|
|
8000560: f091 0f00 teq r1, #0
|
|
8000564: bf04 itt eq
|
|
8000566: 4601 moveq r1, r0
|
|
8000568: 2000 moveq r0, #0
|
|
800056a: fab1 f381 clz r3, r1
|
|
800056e: bf08 it eq
|
|
8000570: 3320 addeq r3, #32
|
|
8000572: f1a3 030b sub.w r3, r3, #11
|
|
8000576: f1b3 0220 subs.w r2, r3, #32
|
|
800057a: da0c bge.n 8000596 <__adddf3+0x16e>
|
|
800057c: 320c adds r2, #12
|
|
800057e: dd08 ble.n 8000592 <__adddf3+0x16a>
|
|
8000580: f102 0c14 add.w ip, r2, #20
|
|
8000584: f1c2 020c rsb r2, r2, #12
|
|
8000588: fa01 f00c lsl.w r0, r1, ip
|
|
800058c: fa21 f102 lsr.w r1, r1, r2
|
|
8000590: e00c b.n 80005ac <__adddf3+0x184>
|
|
8000592: f102 0214 add.w r2, r2, #20
|
|
8000596: bfd8 it le
|
|
8000598: f1c2 0c20 rsble ip, r2, #32
|
|
800059c: fa01 f102 lsl.w r1, r1, r2
|
|
80005a0: fa20 fc0c lsr.w ip, r0, ip
|
|
80005a4: bfdc itt le
|
|
80005a6: ea41 010c orrle.w r1, r1, ip
|
|
80005aa: 4090 lslle r0, r2
|
|
80005ac: 1ae4 subs r4, r4, r3
|
|
80005ae: bfa2 ittt ge
|
|
80005b0: eb01 5104 addge.w r1, r1, r4, lsl #20
|
|
80005b4: 4329 orrge r1, r5
|
|
80005b6: bd30 popge {r4, r5, pc}
|
|
80005b8: ea6f 0404 mvn.w r4, r4
|
|
80005bc: 3c1f subs r4, #31
|
|
80005be: da1c bge.n 80005fa <__adddf3+0x1d2>
|
|
80005c0: 340c adds r4, #12
|
|
80005c2: dc0e bgt.n 80005e2 <__adddf3+0x1ba>
|
|
80005c4: f104 0414 add.w r4, r4, #20
|
|
80005c8: f1c4 0220 rsb r2, r4, #32
|
|
80005cc: fa20 f004 lsr.w r0, r0, r4
|
|
80005d0: fa01 f302 lsl.w r3, r1, r2
|
|
80005d4: ea40 0003 orr.w r0, r0, r3
|
|
80005d8: fa21 f304 lsr.w r3, r1, r4
|
|
80005dc: ea45 0103 orr.w r1, r5, r3
|
|
80005e0: bd30 pop {r4, r5, pc}
|
|
80005e2: f1c4 040c rsb r4, r4, #12
|
|
80005e6: f1c4 0220 rsb r2, r4, #32
|
|
80005ea: fa20 f002 lsr.w r0, r0, r2
|
|
80005ee: fa01 f304 lsl.w r3, r1, r4
|
|
80005f2: ea40 0003 orr.w r0, r0, r3
|
|
80005f6: 4629 mov r1, r5
|
|
80005f8: bd30 pop {r4, r5, pc}
|
|
80005fa: fa21 f004 lsr.w r0, r1, r4
|
|
80005fe: 4629 mov r1, r5
|
|
8000600: bd30 pop {r4, r5, pc}
|
|
8000602: f094 0f00 teq r4, #0
|
|
8000606: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
|
|
800060a: bf06 itte eq
|
|
800060c: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
|
|
8000610: 3401 addeq r4, #1
|
|
8000612: 3d01 subne r5, #1
|
|
8000614: e74e b.n 80004b4 <__adddf3+0x8c>
|
|
8000616: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
800061a: bf18 it ne
|
|
800061c: ea7f 5c65 mvnsne.w ip, r5, asr #21
|
|
8000620: d029 beq.n 8000676 <__adddf3+0x24e>
|
|
8000622: ea94 0f05 teq r4, r5
|
|
8000626: bf08 it eq
|
|
8000628: ea90 0f02 teqeq r0, r2
|
|
800062c: d005 beq.n 800063a <__adddf3+0x212>
|
|
800062e: ea54 0c00 orrs.w ip, r4, r0
|
|
8000632: bf04 itt eq
|
|
8000634: 4619 moveq r1, r3
|
|
8000636: 4610 moveq r0, r2
|
|
8000638: bd30 pop {r4, r5, pc}
|
|
800063a: ea91 0f03 teq r1, r3
|
|
800063e: bf1e ittt ne
|
|
8000640: 2100 movne r1, #0
|
|
8000642: 2000 movne r0, #0
|
|
8000644: bd30 popne {r4, r5, pc}
|
|
8000646: ea5f 5c54 movs.w ip, r4, lsr #21
|
|
800064a: d105 bne.n 8000658 <__adddf3+0x230>
|
|
800064c: 0040 lsls r0, r0, #1
|
|
800064e: 4149 adcs r1, r1
|
|
8000650: bf28 it cs
|
|
8000652: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
|
|
8000656: bd30 pop {r4, r5, pc}
|
|
8000658: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
|
|
800065c: bf3c itt cc
|
|
800065e: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
|
|
8000662: bd30 popcc {r4, r5, pc}
|
|
8000664: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
8000668: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
|
|
800066c: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
8000670: f04f 0000 mov.w r0, #0
|
|
8000674: bd30 pop {r4, r5, pc}
|
|
8000676: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
800067a: bf1a itte ne
|
|
800067c: 4619 movne r1, r3
|
|
800067e: 4610 movne r0, r2
|
|
8000680: ea7f 5c65 mvnseq.w ip, r5, asr #21
|
|
8000684: bf1c itt ne
|
|
8000686: 460b movne r3, r1
|
|
8000688: 4602 movne r2, r0
|
|
800068a: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
800068e: bf06 itte eq
|
|
8000690: ea52 3503 orrseq.w r5, r2, r3, lsl #12
|
|
8000694: ea91 0f03 teqeq r1, r3
|
|
8000698: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
|
|
800069c: bd30 pop {r4, r5, pc}
|
|
800069e: bf00 nop
|
|
|
|
080006a0 <__aeabi_ui2d>:
|
|
80006a0: f090 0f00 teq r0, #0
|
|
80006a4: bf04 itt eq
|
|
80006a6: 2100 moveq r1, #0
|
|
80006a8: 4770 bxeq lr
|
|
80006aa: b530 push {r4, r5, lr}
|
|
80006ac: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80006b0: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80006b4: f04f 0500 mov.w r5, #0
|
|
80006b8: f04f 0100 mov.w r1, #0
|
|
80006bc: e750 b.n 8000560 <__adddf3+0x138>
|
|
80006be: bf00 nop
|
|
|
|
080006c0 <__aeabi_i2d>:
|
|
80006c0: f090 0f00 teq r0, #0
|
|
80006c4: bf04 itt eq
|
|
80006c6: 2100 moveq r1, #0
|
|
80006c8: 4770 bxeq lr
|
|
80006ca: b530 push {r4, r5, lr}
|
|
80006cc: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80006d0: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80006d4: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
|
|
80006d8: bf48 it mi
|
|
80006da: 4240 negmi r0, r0
|
|
80006dc: f04f 0100 mov.w r1, #0
|
|
80006e0: e73e b.n 8000560 <__adddf3+0x138>
|
|
80006e2: bf00 nop
|
|
|
|
080006e4 <__aeabi_f2d>:
|
|
80006e4: 0042 lsls r2, r0, #1
|
|
80006e6: ea4f 01e2 mov.w r1, r2, asr #3
|
|
80006ea: ea4f 0131 mov.w r1, r1, rrx
|
|
80006ee: ea4f 7002 mov.w r0, r2, lsl #28
|
|
80006f2: bf1f itttt ne
|
|
80006f4: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
|
|
80006f8: f093 4f7f teqne r3, #4278190080 @ 0xff000000
|
|
80006fc: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
|
|
8000700: 4770 bxne lr
|
|
8000702: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
|
|
8000706: bf08 it eq
|
|
8000708: 4770 bxeq lr
|
|
800070a: f093 4f7f teq r3, #4278190080 @ 0xff000000
|
|
800070e: bf04 itt eq
|
|
8000710: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
|
|
8000714: 4770 bxeq lr
|
|
8000716: b530 push {r4, r5, lr}
|
|
8000718: f44f 7460 mov.w r4, #896 @ 0x380
|
|
800071c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
8000720: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000724: e71c b.n 8000560 <__adddf3+0x138>
|
|
8000726: bf00 nop
|
|
|
|
08000728 <__aeabi_ul2d>:
|
|
8000728: ea50 0201 orrs.w r2, r0, r1
|
|
800072c: bf08 it eq
|
|
800072e: 4770 bxeq lr
|
|
8000730: b530 push {r4, r5, lr}
|
|
8000732: f04f 0500 mov.w r5, #0
|
|
8000736: e00a b.n 800074e <__aeabi_l2d+0x16>
|
|
|
|
08000738 <__aeabi_l2d>:
|
|
8000738: ea50 0201 orrs.w r2, r0, r1
|
|
800073c: bf08 it eq
|
|
800073e: 4770 bxeq lr
|
|
8000740: b530 push {r4, r5, lr}
|
|
8000742: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
|
|
8000746: d502 bpl.n 800074e <__aeabi_l2d+0x16>
|
|
8000748: 4240 negs r0, r0
|
|
800074a: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
800074e: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000752: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000756: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
800075a: f43f aed8 beq.w 800050e <__adddf3+0xe6>
|
|
800075e: f04f 0203 mov.w r2, #3
|
|
8000762: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
8000766: bf18 it ne
|
|
8000768: 3203 addne r2, #3
|
|
800076a: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
800076e: bf18 it ne
|
|
8000770: 3203 addne r2, #3
|
|
8000772: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
8000776: f1c2 0320 rsb r3, r2, #32
|
|
800077a: fa00 fc03 lsl.w ip, r0, r3
|
|
800077e: fa20 f002 lsr.w r0, r0, r2
|
|
8000782: fa01 fe03 lsl.w lr, r1, r3
|
|
8000786: ea40 000e orr.w r0, r0, lr
|
|
800078a: fa21 f102 lsr.w r1, r1, r2
|
|
800078e: 4414 add r4, r2
|
|
8000790: e6bd b.n 800050e <__adddf3+0xe6>
|
|
8000792: bf00 nop
|
|
|
|
08000794 <__aeabi_d2uiz>:
|
|
8000794: 004a lsls r2, r1, #1
|
|
8000796: d211 bcs.n 80007bc <__aeabi_d2uiz+0x28>
|
|
8000798: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
800079c: d211 bcs.n 80007c2 <__aeabi_d2uiz+0x2e>
|
|
800079e: d50d bpl.n 80007bc <__aeabi_d2uiz+0x28>
|
|
80007a0: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
80007a4: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
80007a8: d40e bmi.n 80007c8 <__aeabi_d2uiz+0x34>
|
|
80007aa: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
80007ae: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
80007b2: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
80007b6: fa23 f002 lsr.w r0, r3, r2
|
|
80007ba: 4770 bx lr
|
|
80007bc: f04f 0000 mov.w r0, #0
|
|
80007c0: 4770 bx lr
|
|
80007c2: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
80007c6: d102 bne.n 80007ce <__aeabi_d2uiz+0x3a>
|
|
80007c8: f04f 30ff mov.w r0, #4294967295
|
|
80007cc: 4770 bx lr
|
|
80007ce: f04f 0000 mov.w r0, #0
|
|
80007d2: 4770 bx lr
|
|
|
|
080007d4 <can_init>:
|
|
|
|
|
|
extern uint32_t lastheartbeat;
|
|
extern int inhibit_SDC;
|
|
|
|
void can_init(CAN_HandleTypeDef* hcan){
|
|
80007d4: b580 push {r7, lr}
|
|
80007d6: b082 sub sp, #8
|
|
80007d8: af00 add r7, sp, #0
|
|
80007da: 6078 str r0, [r7, #4]
|
|
ftcan_init(hcan);
|
|
80007dc: 6878 ldr r0, [r7, #4]
|
|
80007de: f000 f94d bl 8000a7c <ftcan_init>
|
|
ftcan_add_filter(0x00, 0x00); // no filter
|
|
80007e2: 2100 movs r1, #0
|
|
80007e4: 2000 movs r0, #0
|
|
80007e6: f000 f98d bl 8000b04 <ftcan_add_filter>
|
|
}
|
|
80007ea: bf00 nop
|
|
80007ec: 3708 adds r7, #8
|
|
80007ee: 46bd mov sp, r7
|
|
80007f0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080007f4 <can_sendloop>:
|
|
|
|
void can_sendloop(){
|
|
80007f4: b580 push {r7, lr}
|
|
80007f6: b084 sub sp, #16
|
|
80007f8: af00 add r7, sp, #0
|
|
static uint8_t additionaltxcounter = 0;
|
|
|
|
uint8_t status_data[3];
|
|
status_data[0] = update_ports.porta.porta;
|
|
80007fa: 4b76 ldr r3, [pc, #472] @ (80009d4 <can_sendloop+0x1e0>)
|
|
80007fc: 781b ldrb r3, [r3, #0]
|
|
80007fe: 733b strb r3, [r7, #12]
|
|
status_data[1] = update_ports.portb.portb;
|
|
8000800: 4b74 ldr r3, [pc, #464] @ (80009d4 <can_sendloop+0x1e0>)
|
|
8000802: 785b ldrb r3, [r3, #1]
|
|
8000804: 737b strb r3, [r7, #13]
|
|
status_data[2] = !inhibit_SDC;
|
|
8000806: 4b74 ldr r3, [pc, #464] @ (80009d8 <can_sendloop+0x1e4>)
|
|
8000808: 681b ldr r3, [r3, #0]
|
|
800080a: 2b00 cmp r3, #0
|
|
800080c: bf0c ite eq
|
|
800080e: 2301 moveq r3, #1
|
|
8000810: 2300 movne r3, #0
|
|
8000812: b2db uxtb r3, r3
|
|
8000814: 73bb strb r3, [r7, #14]
|
|
ftcan_transmit(TX_STATUS_MSG_ID, status_data, 3);
|
|
8000816: f107 030c add.w r3, r7, #12
|
|
800081a: 2203 movs r2, #3
|
|
800081c: 4619 mov r1, r3
|
|
800081e: 20c9 movs r0, #201 @ 0xc9
|
|
8000820: f000 f94c bl 8000abc <ftcan_transmit>
|
|
|
|
uint8_t data[8];
|
|
|
|
switch (additionaltxcounter) {
|
|
8000824: 4b6d ldr r3, [pc, #436] @ (80009dc <can_sendloop+0x1e8>)
|
|
8000826: 781b ldrb r3, [r3, #0]
|
|
8000828: 2b03 cmp r3, #3
|
|
800082a: f200 80c1 bhi.w 80009b0 <can_sendloop+0x1bc>
|
|
800082e: a201 add r2, pc, #4 @ (adr r2, 8000834 <can_sendloop+0x40>)
|
|
8000830: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8000834: 08000845 .word 0x08000845
|
|
8000838: 080008a3 .word 0x080008a3
|
|
800083c: 08000901 .word 0x08000901
|
|
8000840: 0800095f .word 0x0800095f
|
|
case 0:
|
|
data[0] = current_measurements_adc_val.alwayson >> 8;
|
|
8000844: 4b66 ldr r3, [pc, #408] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000846: 8a1b ldrh r3, [r3, #16]
|
|
8000848: 0a1b lsrs r3, r3, #8
|
|
800084a: b29b uxth r3, r3
|
|
800084c: b2db uxtb r3, r3
|
|
800084e: 713b strb r3, [r7, #4]
|
|
data[1] = current_measurements_adc_val.alwayson & 0xFF;
|
|
8000850: 4b63 ldr r3, [pc, #396] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000852: 8a1b ldrh r3, [r3, #16]
|
|
8000854: b2db uxtb r3, r3
|
|
8000856: 717b strb r3, [r7, #5]
|
|
data[2] = current_measurements_adc_val.misc >> 8;
|
|
8000858: 4b61 ldr r3, [pc, #388] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800085a: 89db ldrh r3, [r3, #14]
|
|
800085c: 0a1b lsrs r3, r3, #8
|
|
800085e: b29b uxth r3, r3
|
|
8000860: b2db uxtb r3, r3
|
|
8000862: 71bb strb r3, [r7, #6]
|
|
data[3] = current_measurements_adc_val.misc & 0xFF;
|
|
8000864: 4b5e ldr r3, [pc, #376] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000866: 89db ldrh r3, [r3, #14]
|
|
8000868: b2db uxtb r3, r3
|
|
800086a: 71fb strb r3, [r7, #7]
|
|
data[4] = current_measurements_adc_val.inverter >> 8;
|
|
800086c: 4b5c ldr r3, [pc, #368] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800086e: 895b ldrh r3, [r3, #10]
|
|
8000870: 0a1b lsrs r3, r3, #8
|
|
8000872: b29b uxth r3, r3
|
|
8000874: b2db uxtb r3, r3
|
|
8000876: 723b strb r3, [r7, #8]
|
|
data[5] = current_measurements_adc_val.inverter & 0xFF;
|
|
8000878: 4b59 ldr r3, [pc, #356] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800087a: 895b ldrh r3, [r3, #10]
|
|
800087c: b2db uxtb r3, r3
|
|
800087e: 727b strb r3, [r7, #9]
|
|
data[6] = current_measurements_adc_val.sdc >> 8;
|
|
8000880: 4b57 ldr r3, [pc, #348] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000882: 8a5b ldrh r3, [r3, #18]
|
|
8000884: 0a1b lsrs r3, r3, #8
|
|
8000886: b29b uxth r3, r3
|
|
8000888: b2db uxtb r3, r3
|
|
800088a: 72bb strb r3, [r7, #10]
|
|
data[7] = current_measurements_adc_val.sdc & 0xFF;
|
|
800088c: 4b54 ldr r3, [pc, #336] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800088e: 8a5b ldrh r3, [r3, #18]
|
|
8000890: b2db uxtb r3, r3
|
|
8000892: 72fb strb r3, [r7, #11]
|
|
ftcan_transmit(CUR_CHANNELS_1_ID, data, 8);
|
|
8000894: 1d3b adds r3, r7, #4
|
|
8000896: 2208 movs r2, #8
|
|
8000898: 4619 mov r1, r3
|
|
800089a: 20ca movs r0, #202 @ 0xca
|
|
800089c: f000 f90e bl 8000abc <ftcan_transmit>
|
|
break;
|
|
80008a0: e087 b.n 80009b2 <can_sendloop+0x1be>
|
|
|
|
case 1:
|
|
data[0] = current_measurements_adc_val.acc_cooling >> 8;
|
|
80008a2: 4b4f ldr r3, [pc, #316] @ (80009e0 <can_sendloop+0x1ec>)
|
|
80008a4: 881b ldrh r3, [r3, #0]
|
|
80008a6: 0a1b lsrs r3, r3, #8
|
|
80008a8: b29b uxth r3, r3
|
|
80008aa: b2db uxtb r3, r3
|
|
80008ac: 713b strb r3, [r7, #4]
|
|
data[1] = current_measurements_adc_val.acc_cooling & 0xFF;
|
|
80008ae: 4b4c ldr r3, [pc, #304] @ (80009e0 <can_sendloop+0x1ec>)
|
|
80008b0: 881b ldrh r3, [r3, #0]
|
|
80008b2: b2db uxtb r3, r3
|
|
80008b4: 717b strb r3, [r7, #5]
|
|
data[2] = current_measurements_adc_val.ts_cooling >> 8;
|
|
80008b6: 4b4a ldr r3, [pc, #296] @ (80009e0 <can_sendloop+0x1ec>)
|
|
80008b8: 885b ldrh r3, [r3, #2]
|
|
80008ba: 0a1b lsrs r3, r3, #8
|
|
80008bc: b29b uxth r3, r3
|
|
80008be: b2db uxtb r3, r3
|
|
80008c0: 71bb strb r3, [r7, #6]
|
|
data[3] = current_measurements_adc_val.ts_cooling & 0xFF;
|
|
80008c2: 4b47 ldr r3, [pc, #284] @ (80009e0 <can_sendloop+0x1ec>)
|
|
80008c4: 885b ldrh r3, [r3, #2]
|
|
80008c6: b2db uxtb r3, r3
|
|
80008c8: 71fb strb r3, [r7, #7]
|
|
data[4] = current_measurements_adc_val.acu >> 8;
|
|
80008ca: 4b45 ldr r3, [pc, #276] @ (80009e0 <can_sendloop+0x1ec>)
|
|
80008cc: 88db ldrh r3, [r3, #6]
|
|
80008ce: 0a1b lsrs r3, r3, #8
|
|
80008d0: b29b uxth r3, r3
|
|
80008d2: b2db uxtb r3, r3
|
|
80008d4: 723b strb r3, [r7, #8]
|
|
data[5] = current_measurements_adc_val.acu & 0xFF;
|
|
80008d6: 4b42 ldr r3, [pc, #264] @ (80009e0 <can_sendloop+0x1ec>)
|
|
80008d8: 88db ldrh r3, [r3, #6]
|
|
80008da: b2db uxtb r3, r3
|
|
80008dc: 727b strb r3, [r7, #9]
|
|
data[6] = current_measurements_adc_val.epsc >> 8;
|
|
80008de: 4b40 ldr r3, [pc, #256] @ (80009e0 <can_sendloop+0x1ec>)
|
|
80008e0: 891b ldrh r3, [r3, #8]
|
|
80008e2: 0a1b lsrs r3, r3, #8
|
|
80008e4: b29b uxth r3, r3
|
|
80008e6: b2db uxtb r3, r3
|
|
80008e8: 72bb strb r3, [r7, #10]
|
|
data[7] = current_measurements_adc_val.epsc & 0xFF;
|
|
80008ea: 4b3d ldr r3, [pc, #244] @ (80009e0 <can_sendloop+0x1ec>)
|
|
80008ec: 891b ldrh r3, [r3, #8]
|
|
80008ee: b2db uxtb r3, r3
|
|
80008f0: 72fb strb r3, [r7, #11]
|
|
ftcan_transmit(CUR_CHANNELS_2_ID, data, 8);
|
|
80008f2: 1d3b adds r3, r7, #4
|
|
80008f4: 2208 movs r2, #8
|
|
80008f6: 4619 mov r1, r3
|
|
80008f8: 20cb movs r0, #203 @ 0xcb
|
|
80008fa: f000 f8df bl 8000abc <ftcan_transmit>
|
|
break;
|
|
80008fe: e058 b.n 80009b2 <can_sendloop+0x1be>
|
|
|
|
case 2:
|
|
data[0] = current_measurements_adc_val.ebs1 >> 8;
|
|
8000900: 4b37 ldr r3, [pc, #220] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000902: 8a9b ldrh r3, [r3, #20]
|
|
8000904: 0a1b lsrs r3, r3, #8
|
|
8000906: b29b uxth r3, r3
|
|
8000908: b2db uxtb r3, r3
|
|
800090a: 713b strb r3, [r7, #4]
|
|
data[1] = current_measurements_adc_val.ebs1 & 0xFF;
|
|
800090c: 4b34 ldr r3, [pc, #208] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800090e: 8a9b ldrh r3, [r3, #20]
|
|
8000910: b2db uxtb r3, r3
|
|
8000912: 717b strb r3, [r7, #5]
|
|
data[2] = current_measurements_adc_val.ebs2 >> 8;
|
|
8000914: 4b32 ldr r3, [pc, #200] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000916: 8adb ldrh r3, [r3, #22]
|
|
8000918: 0a1b lsrs r3, r3, #8
|
|
800091a: b29b uxth r3, r3
|
|
800091c: b2db uxtb r3, r3
|
|
800091e: 71bb strb r3, [r7, #6]
|
|
data[3] = current_measurements_adc_val.ebs2 & 0xFF;
|
|
8000920: 4b2f ldr r3, [pc, #188] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000922: 8adb ldrh r3, [r3, #22]
|
|
8000924: b2db uxtb r3, r3
|
|
8000926: 71fb strb r3, [r7, #7]
|
|
data[4] = current_measurements_adc_val.ebs3 >> 8;
|
|
8000928: 4b2d ldr r3, [pc, #180] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800092a: 8b1b ldrh r3, [r3, #24]
|
|
800092c: 0a1b lsrs r3, r3, #8
|
|
800092e: b29b uxth r3, r3
|
|
8000930: b2db uxtb r3, r3
|
|
8000932: 723b strb r3, [r7, #8]
|
|
data[5] = current_measurements_adc_val.ebs3 & 0xFF;
|
|
8000934: 4b2a ldr r3, [pc, #168] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000936: 8b1b ldrh r3, [r3, #24]
|
|
8000938: b2db uxtb r3, r3
|
|
800093a: 727b strb r3, [r7, #9]
|
|
data[6] = current_measurements_adc_val.drs >> 8;
|
|
800093c: 4b28 ldr r3, [pc, #160] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800093e: 889b ldrh r3, [r3, #4]
|
|
8000940: 0a1b lsrs r3, r3, #8
|
|
8000942: b29b uxth r3, r3
|
|
8000944: b2db uxtb r3, r3
|
|
8000946: 72bb strb r3, [r7, #10]
|
|
data[7] = current_measurements_adc_val.drs & 0xFF;
|
|
8000948: 4b25 ldr r3, [pc, #148] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800094a: 889b ldrh r3, [r3, #4]
|
|
800094c: b2db uxtb r3, r3
|
|
800094e: 72fb strb r3, [r7, #11]
|
|
ftcan_transmit(CUR_CHANNELS_3_ID, data, 8);
|
|
8000950: 1d3b adds r3, r7, #4
|
|
8000952: 2208 movs r2, #8
|
|
8000954: 4619 mov r1, r3
|
|
8000956: 20cc movs r0, #204 @ 0xcc
|
|
8000958: f000 f8b0 bl 8000abc <ftcan_transmit>
|
|
break;
|
|
800095c: e029 b.n 80009b2 <can_sendloop+0x1be>
|
|
|
|
case 3:
|
|
data[0] = current_measurements_adc_val.lidar >> 8;
|
|
800095e: 4b20 ldr r3, [pc, #128] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000960: 899b ldrh r3, [r3, #12]
|
|
8000962: 0a1b lsrs r3, r3, #8
|
|
8000964: b29b uxth r3, r3
|
|
8000966: b2db uxtb r3, r3
|
|
8000968: 713b strb r3, [r7, #4]
|
|
data[1] = current_measurements_adc_val.lidar & 0xFF;
|
|
800096a: 4b1d ldr r3, [pc, #116] @ (80009e0 <can_sendloop+0x1ec>)
|
|
800096c: 899b ldrh r3, [r3, #12]
|
|
800096e: b2db uxtb r3, r3
|
|
8000970: 717b strb r3, [r7, #5]
|
|
data[2] = current_measurements_adc_val.lvms_v >> 8;
|
|
8000972: 4b1b ldr r3, [pc, #108] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000974: 8b9b ldrh r3, [r3, #28]
|
|
8000976: 0a1b lsrs r3, r3, #8
|
|
8000978: b29b uxth r3, r3
|
|
800097a: b2db uxtb r3, r3
|
|
800097c: 71bb strb r3, [r7, #6]
|
|
data[3] = current_measurements_adc_val.lvms_v & 0xFF;
|
|
800097e: 4b18 ldr r3, [pc, #96] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000980: 8b9b ldrh r3, [r3, #28]
|
|
8000982: b2db uxtb r3, r3
|
|
8000984: 71fb strb r3, [r7, #7]
|
|
data[4] = current_measurements_adc_val.asms_v >> 8;
|
|
8000986: 4b16 ldr r3, [pc, #88] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000988: 8bdb ldrh r3, [r3, #30]
|
|
800098a: 0a1b lsrs r3, r3, #8
|
|
800098c: b29b uxth r3, r3
|
|
800098e: b2db uxtb r3, r3
|
|
8000990: 723b strb r3, [r7, #8]
|
|
data[5] = current_measurements_adc_val.asms_v & 0xFF;
|
|
8000992: 4b13 ldr r3, [pc, #76] @ (80009e0 <can_sendloop+0x1ec>)
|
|
8000994: 8bdb ldrh r3, [r3, #30]
|
|
8000996: b2db uxtb r3, r3
|
|
8000998: 727b strb r3, [r7, #9]
|
|
data[6] = 0x01; // not used (transmits 313)
|
|
800099a: 2301 movs r3, #1
|
|
800099c: 72bb strb r3, [r7, #10]
|
|
data[7] = 0x39; // not used (transmits 313)
|
|
800099e: 2339 movs r3, #57 @ 0x39
|
|
80009a0: 72fb strb r3, [r7, #11]
|
|
ftcan_transmit(CUR_CHANNELS_4_ID, data, 8);
|
|
80009a2: 1d3b adds r3, r7, #4
|
|
80009a4: 2208 movs r2, #8
|
|
80009a6: 4619 mov r1, r3
|
|
80009a8: 20cd movs r0, #205 @ 0xcd
|
|
80009aa: f000 f887 bl 8000abc <ftcan_transmit>
|
|
break;
|
|
80009ae: e000 b.n 80009b2 <can_sendloop+0x1be>
|
|
|
|
default:
|
|
break;
|
|
80009b0: bf00 nop
|
|
}
|
|
|
|
additionaltxcounter = (additionaltxcounter + 1) % 4;
|
|
80009b2: 4b0a ldr r3, [pc, #40] @ (80009dc <can_sendloop+0x1e8>)
|
|
80009b4: 781b ldrb r3, [r3, #0]
|
|
80009b6: 3301 adds r3, #1
|
|
80009b8: 425a negs r2, r3
|
|
80009ba: f003 0303 and.w r3, r3, #3
|
|
80009be: f002 0203 and.w r2, r2, #3
|
|
80009c2: bf58 it pl
|
|
80009c4: 4253 negpl r3, r2
|
|
80009c6: b2da uxtb r2, r3
|
|
80009c8: 4b04 ldr r3, [pc, #16] @ (80009dc <can_sendloop+0x1e8>)
|
|
80009ca: 701a strb r2, [r3, #0]
|
|
}
|
|
80009cc: bf00 nop
|
|
80009ce: 3710 adds r7, #16
|
|
80009d0: 46bd mov sp, r7
|
|
80009d2: bd80 pop {r7, pc}
|
|
80009d4: 200002e8 .word 0x200002e8
|
|
80009d8: 200002f0 .word 0x200002f0
|
|
80009dc: 2000002d .word 0x2000002d
|
|
80009e0: 20000098 .word 0x20000098
|
|
|
|
080009e4 <can_error_report>:
|
|
|
|
void can_error_report(){
|
|
80009e4: b580 push {r7, lr}
|
|
80009e6: b082 sub sp, #8
|
|
80009e8: af00 add r7, sp, #0
|
|
uint8_t error_data[2];
|
|
error_data[0] = error.group1.group1;
|
|
80009ea: 4b08 ldr r3, [pc, #32] @ (8000a0c <can_error_report+0x28>)
|
|
80009ec: 781b ldrb r3, [r3, #0]
|
|
80009ee: 713b strb r3, [r7, #4]
|
|
error_data[1] = error.group2.group2;
|
|
80009f0: 4b06 ldr r3, [pc, #24] @ (8000a0c <can_error_report+0x28>)
|
|
80009f2: 785b ldrb r3, [r3, #1]
|
|
80009f4: 717b strb r3, [r7, #5]
|
|
ftcan_transmit(ERROR_ID, error_data, 2);
|
|
80009f6: 1d3b adds r3, r7, #4
|
|
80009f8: 2202 movs r2, #2
|
|
80009fa: 4619 mov r1, r3
|
|
80009fc: 20ce movs r0, #206 @ 0xce
|
|
80009fe: f000 f85d bl 8000abc <ftcan_transmit>
|
|
}
|
|
8000a02: bf00 nop
|
|
8000a04: 3708 adds r7, #8
|
|
8000a06: 46bd mov sp, r7
|
|
8000a08: bd80 pop {r7, pc}
|
|
8000a0a: bf00 nop
|
|
8000a0c: 200002f4 .word 0x200002f4
|
|
|
|
08000a10 <ftcan_msg_received_cb>:
|
|
|
|
void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t* data){
|
|
8000a10: b580 push {r7, lr}
|
|
8000a12: b084 sub sp, #16
|
|
8000a14: af00 add r7, sp, #0
|
|
8000a16: 4603 mov r3, r0
|
|
8000a18: 60b9 str r1, [r7, #8]
|
|
8000a1a: 607a str r2, [r7, #4]
|
|
8000a1c: 81fb strh r3, [r7, #14]
|
|
canmsg_received = 1;
|
|
8000a1e: 4b13 ldr r3, [pc, #76] @ (8000a6c <ftcan_msg_received_cb+0x5c>)
|
|
8000a20: 2201 movs r2, #1
|
|
8000a22: 701a strb r2, [r3, #0]
|
|
if((id == RX_STATUS_MSG_ID) && (datalen == 3)){
|
|
8000a24: 89fb ldrh r3, [r7, #14]
|
|
8000a26: 2bc8 cmp r3, #200 @ 0xc8
|
|
8000a28: d110 bne.n 8000a4c <ftcan_msg_received_cb+0x3c>
|
|
8000a2a: 68bb ldr r3, [r7, #8]
|
|
8000a2c: 2b03 cmp r3, #3
|
|
8000a2e: d10d bne.n 8000a4c <ftcan_msg_received_cb+0x3c>
|
|
rxstate.iostatus.porta.porta = data[0];
|
|
8000a30: 687b ldr r3, [r7, #4]
|
|
8000a32: 781a ldrb r2, [r3, #0]
|
|
8000a34: 4b0e ldr r3, [pc, #56] @ (8000a70 <ftcan_msg_received_cb+0x60>)
|
|
8000a36: 701a strb r2, [r3, #0]
|
|
rxstate.iostatus.portb.portb = data[1];
|
|
8000a38: 687b ldr r3, [r7, #4]
|
|
8000a3a: 3301 adds r3, #1
|
|
8000a3c: 781a ldrb r2, [r3, #0]
|
|
8000a3e: 4b0c ldr r3, [pc, #48] @ (8000a70 <ftcan_msg_received_cb+0x60>)
|
|
8000a40: 705a strb r2, [r3, #1]
|
|
rxstate.checksum = data[2];
|
|
8000a42: 687b ldr r3, [r7, #4]
|
|
8000a44: 3302 adds r3, #2
|
|
8000a46: 781a ldrb r2, [r3, #0]
|
|
8000a48: 4b09 ldr r3, [pc, #36] @ (8000a70 <ftcan_msg_received_cb+0x60>)
|
|
8000a4a: 709a strb r2, [r3, #2]
|
|
}
|
|
|
|
if (id == RX_STATUS_HEARTBEAT){
|
|
8000a4c: 89fb ldrh r3, [r7, #14]
|
|
8000a4e: 2bc7 cmp r3, #199 @ 0xc7
|
|
8000a50: d107 bne.n 8000a62 <ftcan_msg_received_cb+0x52>
|
|
lastheartbeat = HAL_GetTick();
|
|
8000a52: f001 fc4f bl 80022f4 <HAL_GetTick>
|
|
8000a56: 4603 mov r3, r0
|
|
8000a58: 4a06 ldr r2, [pc, #24] @ (8000a74 <ftcan_msg_received_cb+0x64>)
|
|
8000a5a: 6013 str r3, [r2, #0]
|
|
inhibit_SDC = 0;
|
|
8000a5c: 4b06 ldr r3, [pc, #24] @ (8000a78 <ftcan_msg_received_cb+0x68>)
|
|
8000a5e: 2200 movs r2, #0
|
|
8000a60: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
8000a62: bf00 nop
|
|
8000a64: 3710 adds r7, #16
|
|
8000a66: 46bd mov sp, r7
|
|
8000a68: bd80 pop {r7, pc}
|
|
8000a6a: bf00 nop
|
|
8000a6c: 2000002c .word 0x2000002c
|
|
8000a70: 20000028 .word 0x20000028
|
|
8000a74: 200002ec .word 0x200002ec
|
|
8000a78: 200002f0 .word 0x200002f0
|
|
|
|
08000a7c <ftcan_init>:
|
|
#include <string.h>
|
|
|
|
#if defined(FTCAN_IS_BXCAN)
|
|
static CAN_HandleTypeDef *hcan;
|
|
|
|
HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) {
|
|
8000a7c: b580 push {r7, lr}
|
|
8000a7e: b084 sub sp, #16
|
|
8000a80: af00 add r7, sp, #0
|
|
8000a82: 6078 str r0, [r7, #4]
|
|
hcan = handle;
|
|
8000a84: 4a0c ldr r2, [pc, #48] @ (8000ab8 <ftcan_init+0x3c>)
|
|
8000a86: 687b ldr r3, [r7, #4]
|
|
8000a88: 6013 str r3, [r2, #0]
|
|
|
|
HAL_StatusTypeDef status =
|
|
HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING);
|
|
8000a8a: 4b0b ldr r3, [pc, #44] @ (8000ab8 <ftcan_init+0x3c>)
|
|
8000a8c: 681b ldr r3, [r3, #0]
|
|
8000a8e: 2102 movs r1, #2
|
|
8000a90: 4618 mov r0, r3
|
|
8000a92: f003 f9ba bl 8003e0a <HAL_CAN_ActivateNotification>
|
|
8000a96: 4603 mov r3, r0
|
|
8000a98: 73fb strb r3, [r7, #15]
|
|
if (status != HAL_OK) {
|
|
8000a9a: 7bfb ldrb r3, [r7, #15]
|
|
8000a9c: 2b00 cmp r3, #0
|
|
8000a9e: d001 beq.n 8000aa4 <ftcan_init+0x28>
|
|
return status;
|
|
8000aa0: 7bfb ldrb r3, [r7, #15]
|
|
8000aa2: e005 b.n 8000ab0 <ftcan_init+0x34>
|
|
}
|
|
|
|
return HAL_CAN_Start(hcan);
|
|
8000aa4: 4b04 ldr r3, [pc, #16] @ (8000ab8 <ftcan_init+0x3c>)
|
|
8000aa6: 681b ldr r3, [r3, #0]
|
|
8000aa8: 4618 mov r0, r3
|
|
8000aaa: f002 ff78 bl 800399e <HAL_CAN_Start>
|
|
8000aae: 4603 mov r3, r0
|
|
}
|
|
8000ab0: 4618 mov r0, r3
|
|
8000ab2: 3710 adds r7, #16
|
|
8000ab4: 46bd mov sp, r7
|
|
8000ab6: bd80 pop {r7, pc}
|
|
8000ab8: 20000030 .word 0x20000030
|
|
|
|
08000abc <ftcan_transmit>:
|
|
|
|
HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data,
|
|
size_t datalen) {
|
|
8000abc: b580 push {r7, lr}
|
|
8000abe: b086 sub sp, #24
|
|
8000ac0: af00 add r7, sp, #0
|
|
8000ac2: 4603 mov r3, r0
|
|
8000ac4: 60b9 str r1, [r7, #8]
|
|
8000ac6: 607a str r2, [r7, #4]
|
|
8000ac8: 81fb strh r3, [r7, #14]
|
|
static CAN_TxHeaderTypeDef header;
|
|
header.StdId = id;
|
|
8000aca: 89fb ldrh r3, [r7, #14]
|
|
8000acc: 4a0b ldr r2, [pc, #44] @ (8000afc <ftcan_transmit+0x40>)
|
|
8000ace: 6013 str r3, [r2, #0]
|
|
header.IDE = CAN_ID_STD;
|
|
8000ad0: 4b0a ldr r3, [pc, #40] @ (8000afc <ftcan_transmit+0x40>)
|
|
8000ad2: 2200 movs r2, #0
|
|
8000ad4: 609a str r2, [r3, #8]
|
|
header.RTR = CAN_RTR_DATA;
|
|
8000ad6: 4b09 ldr r3, [pc, #36] @ (8000afc <ftcan_transmit+0x40>)
|
|
8000ad8: 2200 movs r2, #0
|
|
8000ada: 60da str r2, [r3, #12]
|
|
header.DLC = datalen;
|
|
8000adc: 4a07 ldr r2, [pc, #28] @ (8000afc <ftcan_transmit+0x40>)
|
|
8000ade: 687b ldr r3, [r7, #4]
|
|
8000ae0: 6113 str r3, [r2, #16]
|
|
uint32_t mailbox;
|
|
return HAL_CAN_AddTxMessage(hcan, &header, data, &mailbox);
|
|
8000ae2: 4b07 ldr r3, [pc, #28] @ (8000b00 <ftcan_transmit+0x44>)
|
|
8000ae4: 6818 ldr r0, [r3, #0]
|
|
8000ae6: f107 0314 add.w r3, r7, #20
|
|
8000aea: 68ba ldr r2, [r7, #8]
|
|
8000aec: 4903 ldr r1, [pc, #12] @ (8000afc <ftcan_transmit+0x40>)
|
|
8000aee: f002 ff9a bl 8003a26 <HAL_CAN_AddTxMessage>
|
|
8000af2: 4603 mov r3, r0
|
|
}
|
|
8000af4: 4618 mov r0, r3
|
|
8000af6: 3718 adds r7, #24
|
|
8000af8: 46bd mov sp, r7
|
|
8000afa: bd80 pop {r7, pc}
|
|
8000afc: 20000034 .word 0x20000034
|
|
8000b00: 20000030 .word 0x20000030
|
|
|
|
08000b04 <ftcan_add_filter>:
|
|
|
|
HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) {
|
|
8000b04: b580 push {r7, lr}
|
|
8000b06: b084 sub sp, #16
|
|
8000b08: af00 add r7, sp, #0
|
|
8000b0a: 4603 mov r3, r0
|
|
8000b0c: 460a mov r2, r1
|
|
8000b0e: 80fb strh r3, [r7, #6]
|
|
8000b10: 4613 mov r3, r2
|
|
8000b12: 80bb strh r3, [r7, #4]
|
|
static uint32_t next_filter_no = 0;
|
|
static CAN_FilterTypeDef filter;
|
|
if (next_filter_no % 2 == 0) {
|
|
8000b14: 4b26 ldr r3, [pc, #152] @ (8000bb0 <ftcan_add_filter+0xac>)
|
|
8000b16: 681b ldr r3, [r3, #0]
|
|
8000b18: f003 0301 and.w r3, r3, #1
|
|
8000b1c: 2b00 cmp r3, #0
|
|
8000b1e: d110 bne.n 8000b42 <ftcan_add_filter+0x3e>
|
|
filter.FilterIdHigh = id << 5;
|
|
8000b20: 88fb ldrh r3, [r7, #6]
|
|
8000b22: 015b lsls r3, r3, #5
|
|
8000b24: 4a23 ldr r2, [pc, #140] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b26: 6013 str r3, [r2, #0]
|
|
filter.FilterMaskIdHigh = mask << 5;
|
|
8000b28: 88bb ldrh r3, [r7, #4]
|
|
8000b2a: 015b lsls r3, r3, #5
|
|
8000b2c: 4a21 ldr r2, [pc, #132] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b2e: 6093 str r3, [r2, #8]
|
|
filter.FilterIdLow = id << 5;
|
|
8000b30: 88fb ldrh r3, [r7, #6]
|
|
8000b32: 015b lsls r3, r3, #5
|
|
8000b34: 4a1f ldr r2, [pc, #124] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b36: 6053 str r3, [r2, #4]
|
|
filter.FilterMaskIdLow = mask << 5;
|
|
8000b38: 88bb ldrh r3, [r7, #4]
|
|
8000b3a: 015b lsls r3, r3, #5
|
|
8000b3c: 4a1d ldr r2, [pc, #116] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b3e: 60d3 str r3, [r2, #12]
|
|
8000b40: e007 b.n 8000b52 <ftcan_add_filter+0x4e>
|
|
} else {
|
|
// Leave high filter untouched from the last configuration
|
|
filter.FilterIdLow = id << 5;
|
|
8000b42: 88fb ldrh r3, [r7, #6]
|
|
8000b44: 015b lsls r3, r3, #5
|
|
8000b46: 4a1b ldr r2, [pc, #108] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b48: 6053 str r3, [r2, #4]
|
|
filter.FilterMaskIdLow = mask << 5;
|
|
8000b4a: 88bb ldrh r3, [r7, #4]
|
|
8000b4c: 015b lsls r3, r3, #5
|
|
8000b4e: 4a19 ldr r2, [pc, #100] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b50: 60d3 str r3, [r2, #12]
|
|
}
|
|
filter.FilterFIFOAssignment = CAN_FILTER_FIFO0;
|
|
8000b52: 4b18 ldr r3, [pc, #96] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b54: 2200 movs r2, #0
|
|
8000b56: 611a str r2, [r3, #16]
|
|
filter.FilterBank = next_filter_no / 2;
|
|
8000b58: 4b15 ldr r3, [pc, #84] @ (8000bb0 <ftcan_add_filter+0xac>)
|
|
8000b5a: 681b ldr r3, [r3, #0]
|
|
8000b5c: 085b lsrs r3, r3, #1
|
|
8000b5e: 4a15 ldr r2, [pc, #84] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b60: 6153 str r3, [r2, #20]
|
|
if (filter.FilterBank > FTCAN_NUM_FILTERS + 1) {
|
|
8000b62: 4b14 ldr r3, [pc, #80] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b64: 695b ldr r3, [r3, #20]
|
|
8000b66: 2b0e cmp r3, #14
|
|
8000b68: d901 bls.n 8000b6e <ftcan_add_filter+0x6a>
|
|
return HAL_ERROR;
|
|
8000b6a: 2301 movs r3, #1
|
|
8000b6c: e01c b.n 8000ba8 <ftcan_add_filter+0xa4>
|
|
}
|
|
filter.FilterMode = CAN_FILTERMODE_IDMASK;
|
|
8000b6e: 4b11 ldr r3, [pc, #68] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b70: 2200 movs r2, #0
|
|
8000b72: 619a str r2, [r3, #24]
|
|
filter.FilterScale = CAN_FILTERSCALE_16BIT;
|
|
8000b74: 4b0f ldr r3, [pc, #60] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b76: 2200 movs r2, #0
|
|
8000b78: 61da str r2, [r3, #28]
|
|
filter.FilterActivation = CAN_FILTER_ENABLE;
|
|
8000b7a: 4b0e ldr r3, [pc, #56] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b7c: 2201 movs r2, #1
|
|
8000b7e: 621a str r2, [r3, #32]
|
|
|
|
// Disable slave filters
|
|
// TODO: Some STM32 have multiple CAN peripherals, and one uses the slave
|
|
// filter bank
|
|
filter.SlaveStartFilterBank = FTCAN_NUM_FILTERS;
|
|
8000b80: 4b0c ldr r3, [pc, #48] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b82: 220d movs r2, #13
|
|
8000b84: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
HAL_StatusTypeDef status = HAL_CAN_ConfigFilter(hcan, &filter);
|
|
8000b86: 4b0c ldr r3, [pc, #48] @ (8000bb8 <ftcan_add_filter+0xb4>)
|
|
8000b88: 681b ldr r3, [r3, #0]
|
|
8000b8a: 490a ldr r1, [pc, #40] @ (8000bb4 <ftcan_add_filter+0xb0>)
|
|
8000b8c: 4618 mov r0, r3
|
|
8000b8e: f002 fe3c bl 800380a <HAL_CAN_ConfigFilter>
|
|
8000b92: 4603 mov r3, r0
|
|
8000b94: 73fb strb r3, [r7, #15]
|
|
if (status == HAL_OK) {
|
|
8000b96: 7bfb ldrb r3, [r7, #15]
|
|
8000b98: 2b00 cmp r3, #0
|
|
8000b9a: d104 bne.n 8000ba6 <ftcan_add_filter+0xa2>
|
|
next_filter_no++;
|
|
8000b9c: 4b04 ldr r3, [pc, #16] @ (8000bb0 <ftcan_add_filter+0xac>)
|
|
8000b9e: 681b ldr r3, [r3, #0]
|
|
8000ba0: 3301 adds r3, #1
|
|
8000ba2: 4a03 ldr r2, [pc, #12] @ (8000bb0 <ftcan_add_filter+0xac>)
|
|
8000ba4: 6013 str r3, [r2, #0]
|
|
}
|
|
return status;
|
|
8000ba6: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8000ba8: 4618 mov r0, r3
|
|
8000baa: 3710 adds r7, #16
|
|
8000bac: 46bd mov sp, r7
|
|
8000bae: bd80 pop {r7, pc}
|
|
8000bb0: 2000004c .word 0x2000004c
|
|
8000bb4: 20000050 .word 0x20000050
|
|
8000bb8: 20000030 .word 0x20000030
|
|
|
|
08000bbc <HAL_CAN_RxFifo0MsgPendingCallback>:
|
|
|
|
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) {
|
|
8000bbc: b580 push {r7, lr}
|
|
8000bbe: b08c sub sp, #48 @ 0x30
|
|
8000bc0: af00 add r7, sp, #0
|
|
8000bc2: 6078 str r0, [r7, #4]
|
|
if (handle != hcan) {
|
|
8000bc4: 4b12 ldr r3, [pc, #72] @ (8000c10 <HAL_CAN_RxFifo0MsgPendingCallback+0x54>)
|
|
8000bc6: 681b ldr r3, [r3, #0]
|
|
8000bc8: 687a ldr r2, [r7, #4]
|
|
8000bca: 429a cmp r2, r3
|
|
8000bcc: d117 bne.n 8000bfe <HAL_CAN_RxFifo0MsgPendingCallback+0x42>
|
|
return;
|
|
}
|
|
CAN_RxHeaderTypeDef header;
|
|
uint8_t data[8];
|
|
if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) {
|
|
8000bce: 4b10 ldr r3, [pc, #64] @ (8000c10 <HAL_CAN_RxFifo0MsgPendingCallback+0x54>)
|
|
8000bd0: 6818 ldr r0, [r3, #0]
|
|
8000bd2: f107 030c add.w r3, r7, #12
|
|
8000bd6: f107 0214 add.w r2, r7, #20
|
|
8000bda: 2100 movs r1, #0
|
|
8000bdc: f002 fff3 bl 8003bc6 <HAL_CAN_GetRxMessage>
|
|
8000be0: 4603 mov r3, r0
|
|
8000be2: 2b00 cmp r3, #0
|
|
8000be4: d10d bne.n 8000c02 <HAL_CAN_RxFifo0MsgPendingCallback+0x46>
|
|
return;
|
|
}
|
|
|
|
if (header.IDE != CAN_ID_STD) {
|
|
8000be6: 69fb ldr r3, [r7, #28]
|
|
8000be8: 2b00 cmp r3, #0
|
|
8000bea: d10c bne.n 8000c06 <HAL_CAN_RxFifo0MsgPendingCallback+0x4a>
|
|
return;
|
|
}
|
|
|
|
ftcan_msg_received_cb(header.StdId, header.DLC, data);
|
|
8000bec: 697b ldr r3, [r7, #20]
|
|
8000bee: b29b uxth r3, r3
|
|
8000bf0: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8000bf2: f107 020c add.w r2, r7, #12
|
|
8000bf6: 4618 mov r0, r3
|
|
8000bf8: f7ff ff0a bl 8000a10 <ftcan_msg_received_cb>
|
|
8000bfc: e004 b.n 8000c08 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
|
|
return;
|
|
8000bfe: bf00 nop
|
|
8000c00: e002 b.n 8000c08 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
|
|
return;
|
|
8000c02: bf00 nop
|
|
8000c04: e000 b.n 8000c08 <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
|
|
return;
|
|
8000c06: bf00 nop
|
|
}
|
|
8000c08: 3730 adds r7, #48 @ 0x30
|
|
8000c0a: 46bd mov sp, r7
|
|
8000c0c: bd80 pop {r7, pc}
|
|
8000c0e: bf00 nop
|
|
8000c10: 20000030 .word 0x20000030
|
|
|
|
08000c14 <ChannelControl_init>:
|
|
extern current_measurements current_measurements_adc_val;
|
|
|
|
extern int inhibit_SDC;
|
|
volatile int prev_epsc_state;
|
|
|
|
void ChannelControl_init(){
|
|
8000c14: b580 push {r7, lr}
|
|
8000c16: af00 add r7, sp, #0
|
|
update_ports.porta.porta = 0;
|
|
8000c18: 4b09 ldr r3, [pc, #36] @ (8000c40 <ChannelControl_init+0x2c>)
|
|
8000c1a: 2200 movs r2, #0
|
|
8000c1c: 701a strb r2, [r3, #0]
|
|
update_ports.portb.portb = 0;
|
|
8000c1e: 4b08 ldr r3, [pc, #32] @ (8000c40 <ChannelControl_init+0x2c>)
|
|
8000c20: 2200 movs r2, #0
|
|
8000c22: 705a strb r2, [r3, #1]
|
|
update_ports.portb.alwayson = 1;
|
|
8000c24: 4a06 ldr r2, [pc, #24] @ (8000c40 <ChannelControl_init+0x2c>)
|
|
8000c26: 7853 ldrb r3, [r2, #1]
|
|
8000c28: f043 0301 orr.w r3, r3, #1
|
|
8000c2c: 7053 strb r3, [r2, #1]
|
|
ChannelControl_UpdateGPIOs(update_ports);
|
|
8000c2e: 4b04 ldr r3, [pc, #16] @ (8000c40 <ChannelControl_init+0x2c>)
|
|
8000c30: 8818 ldrh r0, [r3, #0]
|
|
8000c32: f000 f809 bl 8000c48 <ChannelControl_UpdateGPIOs>
|
|
prev_epsc_state = 0;
|
|
8000c36: 4b03 ldr r3, [pc, #12] @ (8000c44 <ChannelControl_init+0x30>)
|
|
8000c38: 2200 movs r2, #0
|
|
8000c3a: 601a str r2, [r3, #0]
|
|
}
|
|
8000c3c: bf00 nop
|
|
8000c3e: bd80 pop {r7, pc}
|
|
8000c40: 200002e8 .word 0x200002e8
|
|
8000c44: 20000078 .word 0x20000078
|
|
|
|
08000c48 <ChannelControl_UpdateGPIOs>:
|
|
|
|
|
|
void ChannelControl_UpdateGPIOs(enable_gpios UpdatePorts){
|
|
8000c48: b580 push {r7, lr}
|
|
8000c4a: b082 sub sp, #8
|
|
8000c4c: af00 add r7, sp, #0
|
|
8000c4e: 80b8 strh r0, [r7, #4]
|
|
UpdatePorts.portb.alwayson = 1; // ensure always on stays always on
|
|
8000c50: 797b ldrb r3, [r7, #5]
|
|
8000c52: f043 0301 orr.w r3, r3, #1
|
|
8000c56: 717b strb r3, [r7, #5]
|
|
if (inhibit_SDC == 1){
|
|
8000c58: 4b76 ldr r3, [pc, #472] @ (8000e34 <ChannelControl_UpdateGPIOs+0x1ec>)
|
|
8000c5a: 681b ldr r3, [r3, #0]
|
|
8000c5c: 2b01 cmp r3, #1
|
|
8000c5e: d109 bne.n 8000c74 <ChannelControl_UpdateGPIOs+0x2c>
|
|
UpdatePorts.portb.sdc = 0;
|
|
8000c60: 797b ldrb r3, [r7, #5]
|
|
8000c62: f36f 0341 bfc r3, #1, #1
|
|
8000c66: 717b strb r3, [r7, #5]
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, 1);
|
|
8000c68: 2201 movs r2, #1
|
|
8000c6a: f44f 7100 mov.w r1, #512 @ 0x200
|
|
8000c6e: 4872 ldr r0, [pc, #456] @ (8000e38 <ChannelControl_UpdateGPIOs+0x1f0>)
|
|
8000c70: f003 ff5e bl 8004b30 <HAL_GPIO_WritePin>
|
|
}
|
|
HAL_GPIO_WritePin(IN1_GPIO_Port, IN1_Pin, (GPIO_PinState)UpdatePorts.porta.acc_cooling); // Acc-Cooling
|
|
8000c74: 793b ldrb r3, [r7, #4]
|
|
8000c76: f3c3 0300 ubfx r3, r3, #0, #1
|
|
8000c7a: b2db uxtb r3, r3
|
|
8000c7c: 461a mov r2, r3
|
|
8000c7e: f44f 7100 mov.w r1, #512 @ 0x200
|
|
8000c82: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8000c86: f003 ff53 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN2_GPIO_Port, IN2_Pin, (GPIO_PinState)UpdatePorts.porta.ts_cooling); // TS-Cooling
|
|
8000c8a: 793b ldrb r3, [r7, #4]
|
|
8000c8c: f3c3 0340 ubfx r3, r3, #1, #1
|
|
8000c90: b2db uxtb r3, r3
|
|
8000c92: 461a mov r2, r3
|
|
8000c94: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000c98: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8000c9c: f003 ff48 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN3_GPIO_Port, IN3_Pin, (GPIO_PinState)UpdatePorts.porta.drs); // DRS
|
|
8000ca0: 793b ldrb r3, [r7, #4]
|
|
8000ca2: f3c3 0380 ubfx r3, r3, #2, #1
|
|
8000ca6: b2db uxtb r3, r3
|
|
8000ca8: 461a mov r2, r3
|
|
8000caa: f44f 5180 mov.w r1, #4096 @ 0x1000
|
|
8000cae: 4863 ldr r0, [pc, #396] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000cb0: f003 ff3e bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN4_GPIO_Port, IN4_Pin, (GPIO_PinState)UpdatePorts.porta.acu); // ACU
|
|
8000cb4: 793b ldrb r3, [r7, #4]
|
|
8000cb6: f3c3 03c0 ubfx r3, r3, #3, #1
|
|
8000cba: b2db uxtb r3, r3
|
|
8000cbc: 461a mov r2, r3
|
|
8000cbe: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
8000cc2: 485e ldr r0, [pc, #376] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000cc4: f003 ff34 bl 8004b30 <HAL_GPIO_WritePin>
|
|
|
|
if (prev_epsc_state == 0 && UpdatePorts.porta.epsc == 1){
|
|
8000cc8: 4b5d ldr r3, [pc, #372] @ (8000e40 <ChannelControl_UpdateGPIOs+0x1f8>)
|
|
8000cca: 681b ldr r3, [r3, #0]
|
|
8000ccc: 2b00 cmp r3, #0
|
|
8000cce: d135 bne.n 8000d3c <ChannelControl_UpdateGPIOs+0xf4>
|
|
8000cd0: 793b ldrb r3, [r7, #4]
|
|
8000cd2: f003 0310 and.w r3, r3, #16
|
|
8000cd6: b2db uxtb r3, r3
|
|
8000cd8: 2b00 cmp r3, #0
|
|
8000cda: d02f beq.n 8000d3c <ChannelControl_UpdateGPIOs+0xf4>
|
|
HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 1); // enable precharge
|
|
8000cdc: 2201 movs r2, #1
|
|
8000cde: 2140 movs r1, #64 @ 0x40
|
|
8000ce0: 4856 ldr r0, [pc, #344] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000ce2: f003 ff25 bl 8004b30 <HAL_GPIO_WritePin>
|
|
if (current_measurements_adc_val.epsc_precharge >= (0.95f * current_measurements_adc_val.asms_v)) { // check if precharge is complete (no while loop needed, this function is called by the main while-loop)
|
|
8000ce6: 4b57 ldr r3, [pc, #348] @ (8000e44 <ChannelControl_UpdateGPIOs+0x1fc>)
|
|
8000ce8: 8b5b ldrh r3, [r3, #26]
|
|
8000cea: ee07 3a90 vmov s15, r3
|
|
8000cee: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8000cf2: 4b54 ldr r3, [pc, #336] @ (8000e44 <ChannelControl_UpdateGPIOs+0x1fc>)
|
|
8000cf4: 8bdb ldrh r3, [r3, #30]
|
|
8000cf6: ee07 3a90 vmov s15, r3
|
|
8000cfa: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8000cfe: eddf 6a52 vldr s13, [pc, #328] @ 8000e48 <ChannelControl_UpdateGPIOs+0x200>
|
|
8000d02: ee67 7aa6 vmul.f32 s15, s15, s13
|
|
8000d06: eeb4 7ae7 vcmpe.f32 s14, s15
|
|
8000d0a: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8000d0e: db15 blt.n 8000d3c <ChannelControl_UpdateGPIOs+0xf4>
|
|
HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc); // switch on PROFET
|
|
8000d10: 793b ldrb r3, [r7, #4]
|
|
8000d12: f3c3 1300 ubfx r3, r3, #4, #1
|
|
8000d16: b2db uxtb r3, r3
|
|
8000d18: 461a mov r2, r3
|
|
8000d1a: f44f 4180 mov.w r1, #16384 @ 0x4000
|
|
8000d1e: 4847 ldr r0, [pc, #284] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000d20: f003 ff06 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // disengage precharge
|
|
8000d24: 2200 movs r2, #0
|
|
8000d26: 2140 movs r1, #64 @ 0x40
|
|
8000d28: 4844 ldr r0, [pc, #272] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000d2a: f003 ff01 bl 8004b30 <HAL_GPIO_WritePin>
|
|
prev_epsc_state = UpdatePorts.porta.epsc;
|
|
8000d2e: 793b ldrb r3, [r7, #4]
|
|
8000d30: f3c3 1300 ubfx r3, r3, #4, #1
|
|
8000d34: b2db uxtb r3, r3
|
|
8000d36: 461a mov r2, r3
|
|
8000d38: 4b41 ldr r3, [pc, #260] @ (8000e40 <ChannelControl_UpdateGPIOs+0x1f8>)
|
|
8000d3a: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
if ((prev_epsc_state == 1 && UpdatePorts.porta.epsc == 0) || (prev_epsc_state == UpdatePorts.porta.epsc)){
|
|
8000d3c: 4b40 ldr r3, [pc, #256] @ (8000e40 <ChannelControl_UpdateGPIOs+0x1f8>)
|
|
8000d3e: 681b ldr r3, [r3, #0]
|
|
8000d40: 2b01 cmp r3, #1
|
|
8000d42: d105 bne.n 8000d50 <ChannelControl_UpdateGPIOs+0x108>
|
|
8000d44: 793b ldrb r3, [r7, #4]
|
|
8000d46: f003 0310 and.w r3, r3, #16
|
|
8000d4a: b2db uxtb r3, r3
|
|
8000d4c: 2b00 cmp r3, #0
|
|
8000d4e: d008 beq.n 8000d62 <ChannelControl_UpdateGPIOs+0x11a>
|
|
8000d50: 793b ldrb r3, [r7, #4]
|
|
8000d52: f3c3 1300 ubfx r3, r3, #4, #1
|
|
8000d56: b2db uxtb r3, r3
|
|
8000d58: 461a mov r2, r3
|
|
8000d5a: 4b39 ldr r3, [pc, #228] @ (8000e40 <ChannelControl_UpdateGPIOs+0x1f8>)
|
|
8000d5c: 681b ldr r3, [r3, #0]
|
|
8000d5e: 429a cmp r2, r3
|
|
8000d60: d115 bne.n 8000d8e <ChannelControl_UpdateGPIOs+0x146>
|
|
HAL_GPIO_WritePin(PC_EN_GPIO_Port, PC_EN_Pin, 0); // ensure precharge is disabled, when not needed or stopped before completion
|
|
8000d62: 2200 movs r2, #0
|
|
8000d64: 2140 movs r1, #64 @ 0x40
|
|
8000d66: 4835 ldr r0, [pc, #212] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000d68: f003 fee2 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN5_GPIO_Port, IN5_Pin, (GPIO_PinState)UpdatePorts.porta.epsc);
|
|
8000d6c: 793b ldrb r3, [r7, #4]
|
|
8000d6e: f3c3 1300 ubfx r3, r3, #4, #1
|
|
8000d72: b2db uxtb r3, r3
|
|
8000d74: 461a mov r2, r3
|
|
8000d76: f44f 4180 mov.w r1, #16384 @ 0x4000
|
|
8000d7a: 4830 ldr r0, [pc, #192] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000d7c: f003 fed8 bl 8004b30 <HAL_GPIO_WritePin>
|
|
prev_epsc_state = UpdatePorts.porta.epsc;
|
|
8000d80: 793b ldrb r3, [r7, #4]
|
|
8000d82: f3c3 1300 ubfx r3, r3, #4, #1
|
|
8000d86: b2db uxtb r3, r3
|
|
8000d88: 461a mov r2, r3
|
|
8000d8a: 4b2d ldr r3, [pc, #180] @ (8000e40 <ChannelControl_UpdateGPIOs+0x1f8>)
|
|
8000d8c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
HAL_GPIO_WritePin(IN6_GPIO_Port, IN6_Pin, (GPIO_PinState)UpdatePorts.porta.inverter); // inverter
|
|
8000d8e: 793b ldrb r3, [r7, #4]
|
|
8000d90: f3c3 1340 ubfx r3, r3, #5, #1
|
|
8000d94: b2db uxtb r3, r3
|
|
8000d96: 461a mov r2, r3
|
|
8000d98: f44f 6180 mov.w r1, #1024 @ 0x400
|
|
8000d9c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8000da0: f003 fec6 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN7_GPIO_Port, IN7_Pin, (GPIO_PinState)UpdatePorts.porta.lidar); // lidar
|
|
8000da4: 793b ldrb r3, [r7, #4]
|
|
8000da6: f3c3 1380 ubfx r3, r3, #6, #1
|
|
8000daa: b2db uxtb r3, r3
|
|
8000dac: 461a mov r2, r3
|
|
8000dae: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000db2: 4822 ldr r0, [pc, #136] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000db4: f003 febc bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN8_GPIO_Port, IN8_Pin, (GPIO_PinState)UpdatePorts.porta.misc); // MISC
|
|
8000db8: 793b ldrb r3, [r7, #4]
|
|
8000dba: f3c3 13c0 ubfx r3, r3, #7, #1
|
|
8000dbe: b2db uxtb r3, r3
|
|
8000dc0: 461a mov r2, r3
|
|
8000dc2: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
8000dc6: 481d ldr r0, [pc, #116] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000dc8: f003 feb2 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN9_GPIO_Port, IN9_Pin, (GPIO_PinState)UpdatePorts.portb.alwayson); // always on
|
|
8000dcc: 797b ldrb r3, [r7, #5]
|
|
8000dce: f3c3 0300 ubfx r3, r3, #0, #1
|
|
8000dd2: b2db uxtb r3, r3
|
|
8000dd4: 461a mov r2, r3
|
|
8000dd6: f44f 6100 mov.w r1, #2048 @ 0x800
|
|
8000dda: 4818 ldr r0, [pc, #96] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000ddc: f003 fea8 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN10_GPIO_Port, IN10_Pin, (GPIO_PinState)UpdatePorts.portb.sdc); // SDC
|
|
8000de0: 797b ldrb r3, [r7, #5]
|
|
8000de2: f3c3 0340 ubfx r3, r3, #1, #1
|
|
8000de6: b2db uxtb r3, r3
|
|
8000de8: 461a mov r2, r3
|
|
8000dea: f44f 7100 mov.w r1, #512 @ 0x200
|
|
8000dee: 4813 ldr r0, [pc, #76] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000df0: f003 fe9e bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN11_GPIO_Port, IN11_Pin, (GPIO_PinState)UpdatePorts.portb.ebs1); // EBS 1
|
|
8000df4: 797b ldrb r3, [r7, #5]
|
|
8000df6: f3c3 0380 ubfx r3, r3, #2, #1
|
|
8000dfa: b2db uxtb r3, r3
|
|
8000dfc: 461a mov r2, r3
|
|
8000dfe: 2104 movs r1, #4
|
|
8000e00: 480e ldr r0, [pc, #56] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000e02: f003 fe95 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN12_GPIO_Port, IN12_Pin, (GPIO_PinState)UpdatePorts.portb.ebs2); // EBS 2
|
|
8000e06: 797b ldrb r3, [r7, #5]
|
|
8000e08: f3c3 03c0 ubfx r3, r3, #3, #1
|
|
8000e0c: b2db uxtb r3, r3
|
|
8000e0e: 461a mov r2, r3
|
|
8000e10: 2102 movs r1, #2
|
|
8000e12: 480a ldr r0, [pc, #40] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000e14: f003 fe8c bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(IN13_GPIO_Port, IN13_Pin, (GPIO_PinState)UpdatePorts.portb.ebs3); // EBS 3
|
|
8000e18: 797b ldrb r3, [r7, #5]
|
|
8000e1a: f3c3 1300 ubfx r3, r3, #4, #1
|
|
8000e1e: b2db uxtb r3, r3
|
|
8000e20: 461a mov r2, r3
|
|
8000e22: f44f 6180 mov.w r1, #1024 @ 0x400
|
|
8000e26: 4805 ldr r0, [pc, #20] @ (8000e3c <ChannelControl_UpdateGPIOs+0x1f4>)
|
|
8000e28: f003 fe82 bl 8004b30 <HAL_GPIO_WritePin>
|
|
}
|
|
8000e2c: bf00 nop
|
|
8000e2e: 3708 adds r7, #8
|
|
8000e30: 46bd mov sp, r7
|
|
8000e32: bd80 pop {r7, pc}
|
|
8000e34: 200002f0 .word 0x200002f0
|
|
8000e38: 48000800 .word 0x48000800
|
|
8000e3c: 48000400 .word 0x48000400
|
|
8000e40: 20000078 .word 0x20000078
|
|
8000e44: 20000098 .word 0x20000098
|
|
8000e48: 3f733333 .word 0x3f733333
|
|
|
|
08000e4c <current_monitor_init>:
|
|
GPIO_PinState valve3 = GPIO_PIN_RESET;
|
|
|
|
ADC_HandleTypeDef* adc1;
|
|
ADC_HandleTypeDef* adc2;
|
|
|
|
void current_monitor_init(ADC_HandleTypeDef* hadc1, ADC_HandleTypeDef* hadc2, TIM_HandleTypeDef* trigtim) {
|
|
8000e4c: b580 push {r7, lr}
|
|
8000e4e: b084 sub sp, #16
|
|
8000e50: af00 add r7, sp, #0
|
|
8000e52: 60f8 str r0, [r7, #12]
|
|
8000e54: 60b9 str r1, [r7, #8]
|
|
8000e56: 607a str r2, [r7, #4]
|
|
HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3);
|
|
8000e58: 4b12 ldr r3, [pc, #72] @ (8000ea4 <current_monitor_init+0x58>)
|
|
8000e5a: 781b ldrb r3, [r3, #0]
|
|
8000e5c: 461a mov r2, r3
|
|
8000e5e: 2110 movs r1, #16
|
|
8000e60: 4811 ldr r0, [pc, #68] @ (8000ea8 <current_monitor_init+0x5c>)
|
|
8000e62: f003 fe65 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2);
|
|
8000e66: 4b11 ldr r3, [pc, #68] @ (8000eac <current_monitor_init+0x60>)
|
|
8000e68: 781b ldrb r3, [r3, #0]
|
|
8000e6a: 461a mov r2, r3
|
|
8000e6c: 2120 movs r1, #32
|
|
8000e6e: 480e ldr r0, [pc, #56] @ (8000ea8 <current_monitor_init+0x5c>)
|
|
8000e70: f003 fe5e bl 8004b30 <HAL_GPIO_WritePin>
|
|
adc1 = hadc1;
|
|
8000e74: 4a0e ldr r2, [pc, #56] @ (8000eb0 <current_monitor_init+0x64>)
|
|
8000e76: 68fb ldr r3, [r7, #12]
|
|
8000e78: 6013 str r3, [r2, #0]
|
|
adc2 = hadc2;
|
|
8000e7a: 4a0e ldr r2, [pc, #56] @ (8000eb4 <current_monitor_init+0x68>)
|
|
8000e7c: 68bb ldr r3, [r7, #8]
|
|
8000e7e: 6013 str r3, [r2, #0]
|
|
HAL_TIM_Base_Start(trigtim);
|
|
8000e80: 6878 ldr r0, [r7, #4]
|
|
8000e82: f005 fab7 bl 80063f4 <HAL_TIM_Base_Start>
|
|
HAL_ADC_Start_DMA(hadc1, (uint32_t*)adc_channels1.adcbuffer, 8);
|
|
8000e86: 2208 movs r2, #8
|
|
8000e88: 490b ldr r1, [pc, #44] @ (8000eb8 <current_monitor_init+0x6c>)
|
|
8000e8a: 68f8 ldr r0, [r7, #12]
|
|
8000e8c: f001 fc12 bl 80026b4 <HAL_ADC_Start_DMA>
|
|
HAL_ADC_Start_DMA(hadc2, (uint32_t*)adc_channels2.adcbuffer, 6);
|
|
8000e90: 2206 movs r2, #6
|
|
8000e92: 490a ldr r1, [pc, #40] @ (8000ebc <current_monitor_init+0x70>)
|
|
8000e94: 68b8 ldr r0, [r7, #8]
|
|
8000e96: f001 fc0d bl 80026b4 <HAL_ADC_Start_DMA>
|
|
}
|
|
8000e9a: bf00 nop
|
|
8000e9c: 3710 adds r7, #16
|
|
8000e9e: 46bd mov sp, r7
|
|
8000ea0: bd80 pop {r7, pc}
|
|
8000ea2: bf00 nop
|
|
8000ea4: 200000b9 .word 0x200000b9
|
|
8000ea8: 48000400 .word 0x48000400
|
|
8000eac: 200000b8 .word 0x200000b8
|
|
8000eb0: 200000bc .word 0x200000bc
|
|
8000eb4: 200000c0 .word 0x200000c0
|
|
8000eb8: 2000007c .word 0x2000007c
|
|
8000ebc: 2000008c .word 0x2000008c
|
|
|
|
08000ec0 <current_monitor_checklimits>:
|
|
|
|
uint8_t current_monitor_checklimits() {return 0;} // TODO: implement properly
|
|
8000ec0: b480 push {r7}
|
|
8000ec2: af00 add r7, sp, #0
|
|
8000ec4: 2300 movs r3, #0
|
|
8000ec6: 4618 mov r0, r3
|
|
8000ec8: 46bd mov sp, r7
|
|
8000eca: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000ece: 4770 bx lr
|
|
|
|
08000ed0 <HAL_ADC_ConvCpltCallback>:
|
|
|
|
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) {
|
|
8000ed0: b580 push {r7, lr}
|
|
8000ed2: b082 sub sp, #8
|
|
8000ed4: af00 add r7, sp, #0
|
|
8000ed6: 6078 str r0, [r7, #4]
|
|
if (hadc == adc1){
|
|
8000ed8: 4b30 ldr r3, [pc, #192] @ (8000f9c <HAL_ADC_ConvCpltCallback+0xcc>)
|
|
8000eda: 681b ldr r3, [r3, #0]
|
|
8000edc: 687a ldr r2, [r7, #4]
|
|
8000ede: 429a cmp r2, r3
|
|
8000ee0: d168 bne.n 8000fb4 <HAL_ADC_ConvCpltCallback+0xe4>
|
|
if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_RESET){
|
|
8000ee2: 4b2f ldr r3, [pc, #188] @ (8000fa0 <HAL_ADC_ConvCpltCallback+0xd0>)
|
|
8000ee4: 781b ldrb r3, [r3, #0]
|
|
8000ee6: 2b00 cmp r3, #0
|
|
8000ee8: d118 bne.n 8000f1c <HAL_ADC_ConvCpltCallback+0x4c>
|
|
8000eea: 4b2e ldr r3, [pc, #184] @ (8000fa4 <HAL_ADC_ConvCpltCallback+0xd4>)
|
|
8000eec: 781b ldrb r3, [r3, #0]
|
|
8000eee: 2b00 cmp r3, #0
|
|
8000ef0: d114 bne.n 8000f1c <HAL_ADC_ConvCpltCallback+0x4c>
|
|
current_measurements_adc_val.ebs1 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
|
|
8000ef2: 4b2d ldr r3, [pc, #180] @ (8000fa8 <HAL_ADC_ConvCpltCallback+0xd8>)
|
|
8000ef4: 881b ldrh r3, [r3, #0]
|
|
8000ef6: b29b uxth r3, r3
|
|
8000ef8: ee07 3a90 vmov s15, r3
|
|
8000efc: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8000f00: ed9f 7a2a vldr s14, [pc, #168] @ 8000fac <HAL_ADC_ConvCpltCallback+0xdc>
|
|
8000f04: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000f08: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8000f0c: ee17 3a90 vmov r3, s15
|
|
8000f10: b29a uxth r2, r3
|
|
8000f12: 4b27 ldr r3, [pc, #156] @ (8000fb0 <HAL_ADC_ConvCpltCallback+0xe0>)
|
|
8000f14: 829a strh r2, [r3, #20]
|
|
valve2 = GPIO_PIN_SET;
|
|
8000f16: 4b22 ldr r3, [pc, #136] @ (8000fa0 <HAL_ADC_ConvCpltCallback+0xd0>)
|
|
8000f18: 2201 movs r2, #1
|
|
8000f1a: 701a strb r2, [r3, #0]
|
|
}
|
|
if (valve2 == GPIO_PIN_SET && valve3 == GPIO_PIN_RESET){
|
|
8000f1c: 4b20 ldr r3, [pc, #128] @ (8000fa0 <HAL_ADC_ConvCpltCallback+0xd0>)
|
|
8000f1e: 781b ldrb r3, [r3, #0]
|
|
8000f20: 2b01 cmp r3, #1
|
|
8000f22: d11b bne.n 8000f5c <HAL_ADC_ConvCpltCallback+0x8c>
|
|
8000f24: 4b1f ldr r3, [pc, #124] @ (8000fa4 <HAL_ADC_ConvCpltCallback+0xd4>)
|
|
8000f26: 781b ldrb r3, [r3, #0]
|
|
8000f28: 2b00 cmp r3, #0
|
|
8000f2a: d117 bne.n 8000f5c <HAL_ADC_ConvCpltCallback+0x8c>
|
|
current_measurements_adc_val.ebs2 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
|
|
8000f2c: 4b1e ldr r3, [pc, #120] @ (8000fa8 <HAL_ADC_ConvCpltCallback+0xd8>)
|
|
8000f2e: 881b ldrh r3, [r3, #0]
|
|
8000f30: b29b uxth r3, r3
|
|
8000f32: ee07 3a90 vmov s15, r3
|
|
8000f36: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8000f3a: ed9f 7a1c vldr s14, [pc, #112] @ 8000fac <HAL_ADC_ConvCpltCallback+0xdc>
|
|
8000f3e: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000f42: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8000f46: ee17 3a90 vmov r3, s15
|
|
8000f4a: b29a uxth r2, r3
|
|
8000f4c: 4b18 ldr r3, [pc, #96] @ (8000fb0 <HAL_ADC_ConvCpltCallback+0xe0>)
|
|
8000f4e: 82da strh r2, [r3, #22]
|
|
valve2 = GPIO_PIN_RESET;
|
|
8000f50: 4b13 ldr r3, [pc, #76] @ (8000fa0 <HAL_ADC_ConvCpltCallback+0xd0>)
|
|
8000f52: 2200 movs r2, #0
|
|
8000f54: 701a strb r2, [r3, #0]
|
|
valve3 = GPIO_PIN_SET;
|
|
8000f56: 4b13 ldr r3, [pc, #76] @ (8000fa4 <HAL_ADC_ConvCpltCallback+0xd4>)
|
|
8000f58: 2201 movs r2, #1
|
|
8000f5a: 701a strb r2, [r3, #0]
|
|
}
|
|
if (valve2 == GPIO_PIN_RESET && valve3 == GPIO_PIN_SET){
|
|
8000f5c: 4b10 ldr r3, [pc, #64] @ (8000fa0 <HAL_ADC_ConvCpltCallback+0xd0>)
|
|
8000f5e: 781b ldrb r3, [r3, #0]
|
|
8000f60: 2b00 cmp r3, #0
|
|
8000f62: f040 80b9 bne.w 80010d8 <HAL_ADC_ConvCpltCallback+0x208>
|
|
8000f66: 4b0f ldr r3, [pc, #60] @ (8000fa4 <HAL_ADC_ConvCpltCallback+0xd4>)
|
|
8000f68: 781b ldrb r3, [r3, #0]
|
|
8000f6a: 2b01 cmp r3, #1
|
|
8000f6c: f040 80b4 bne.w 80010d8 <HAL_ADC_ConvCpltCallback+0x208>
|
|
current_measurements_adc_val.ebs3 = adc_channels1.adcbank1.isense11 * CURR_SENSE_FACTOR_1A;
|
|
8000f70: 4b0d ldr r3, [pc, #52] @ (8000fa8 <HAL_ADC_ConvCpltCallback+0xd8>)
|
|
8000f72: 881b ldrh r3, [r3, #0]
|
|
8000f74: b29b uxth r3, r3
|
|
8000f76: ee07 3a90 vmov s15, r3
|
|
8000f7a: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8000f7e: ed9f 7a0b vldr s14, [pc, #44] @ 8000fac <HAL_ADC_ConvCpltCallback+0xdc>
|
|
8000f82: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000f86: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8000f8a: ee17 3a90 vmov r3, s15
|
|
8000f8e: b29a uxth r2, r3
|
|
8000f90: 4b07 ldr r3, [pc, #28] @ (8000fb0 <HAL_ADC_ConvCpltCallback+0xe0>)
|
|
8000f92: 831a strh r2, [r3, #24]
|
|
valve3 = GPIO_PIN_RESET;
|
|
8000f94: 4b03 ldr r3, [pc, #12] @ (8000fa4 <HAL_ADC_ConvCpltCallback+0xd4>)
|
|
8000f96: 2200 movs r2, #0
|
|
8000f98: 701a strb r2, [r3, #0]
|
|
8000f9a: e09d b.n 80010d8 <HAL_ADC_ConvCpltCallback+0x208>
|
|
8000f9c: 200000bc .word 0x200000bc
|
|
8000fa0: 200000b8 .word 0x200000b8
|
|
8000fa4: 200000b9 .word 0x200000b9
|
|
8000fa8: 2000007c .word 0x2000007c
|
|
8000fac: 3d778f79 .word 0x3d778f79
|
|
8000fb0: 20000098 .word 0x20000098
|
|
}
|
|
}
|
|
else {
|
|
current_measurements_adc_val.lvms_v = adc_channels1.adcbank1.lvms_vsense * LV_SENSE_FACTOR;
|
|
8000fb4: 4b88 ldr r3, [pc, #544] @ (80011d8 <HAL_ADC_ConvCpltCallback+0x308>)
|
|
8000fb6: 885b ldrh r3, [r3, #2]
|
|
8000fb8: b29b uxth r3, r3
|
|
8000fba: 4618 mov r0, r3
|
|
8000fbc: f7ff fb80 bl 80006c0 <__aeabi_i2d>
|
|
8000fc0: a383 add r3, pc, #524 @ (adr r3, 80011d0 <HAL_ADC_ConvCpltCallback+0x300>)
|
|
8000fc2: e9d3 2300 ldrd r2, r3, [r3]
|
|
8000fc6: f7ff f8ff bl 80001c8 <__aeabi_dmul>
|
|
8000fca: 4602 mov r2, r0
|
|
8000fcc: 460b mov r3, r1
|
|
8000fce: 4610 mov r0, r2
|
|
8000fd0: 4619 mov r1, r3
|
|
8000fd2: f7ff fbdf bl 8000794 <__aeabi_d2uiz>
|
|
8000fd6: 4603 mov r3, r0
|
|
8000fd8: b29a uxth r2, r3
|
|
8000fda: 4b80 ldr r3, [pc, #512] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8000fdc: 839a strh r2, [r3, #28]
|
|
current_measurements_adc_val.acc_cooling = adc_channels1.adcbank1.isense1 * CURR_SENSE_FACTOR_9A;
|
|
8000fde: 4b7e ldr r3, [pc, #504] @ (80011d8 <HAL_ADC_ConvCpltCallback+0x308>)
|
|
8000fe0: 889b ldrh r3, [r3, #4]
|
|
8000fe2: b29b uxth r3, r3
|
|
8000fe4: ee07 3a90 vmov s15, r3
|
|
8000fe8: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8000fec: ed9f 7a7c vldr s14, [pc, #496] @ 80011e0 <HAL_ADC_ConvCpltCallback+0x310>
|
|
8000ff0: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8000ff4: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8000ff8: ee17 3a90 vmov r3, s15
|
|
8000ffc: b29a uxth r2, r3
|
|
8000ffe: 4b77 ldr r3, [pc, #476] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8001000: 801a strh r2, [r3, #0]
|
|
current_measurements_adc_val.ts_cooling = adc_channels1.adcbank1.isense2 * CURR_SENSE_FACTOR_9A;
|
|
8001002: 4b75 ldr r3, [pc, #468] @ (80011d8 <HAL_ADC_ConvCpltCallback+0x308>)
|
|
8001004: 88db ldrh r3, [r3, #6]
|
|
8001006: b29b uxth r3, r3
|
|
8001008: ee07 3a90 vmov s15, r3
|
|
800100c: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001010: ed9f 7a73 vldr s14, [pc, #460] @ 80011e0 <HAL_ADC_ConvCpltCallback+0x310>
|
|
8001014: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001018: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
800101c: ee17 3a90 vmov r3, s15
|
|
8001020: b29a uxth r2, r3
|
|
8001022: 4b6e ldr r3, [pc, #440] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8001024: 805a strh r2, [r3, #2]
|
|
current_measurements_adc_val.alwayson = adc_channels1.adcbank1.isense9 * CURR_SENSE_FACTOR_9A;
|
|
8001026: 4b6c ldr r3, [pc, #432] @ (80011d8 <HAL_ADC_ConvCpltCallback+0x308>)
|
|
8001028: 891b ldrh r3, [r3, #8]
|
|
800102a: b29b uxth r3, r3
|
|
800102c: ee07 3a90 vmov s15, r3
|
|
8001030: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001034: ed9f 7a6a vldr s14, [pc, #424] @ 80011e0 <HAL_ADC_ConvCpltCallback+0x310>
|
|
8001038: ee67 7a87 vmul.f32 s15, s15, s14
|
|
800103c: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001040: ee17 3a90 vmov r3, s15
|
|
8001044: b29a uxth r2, r3
|
|
8001046: 4b65 ldr r3, [pc, #404] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8001048: 821a strh r2, [r3, #16]
|
|
current_measurements_adc_val.asms_v = adc_channels1.adcbank1.asms_vsense * LV_SENSE_FACTOR;
|
|
800104a: 4b63 ldr r3, [pc, #396] @ (80011d8 <HAL_ADC_ConvCpltCallback+0x308>)
|
|
800104c: 895b ldrh r3, [r3, #10]
|
|
800104e: b29b uxth r3, r3
|
|
8001050: 4618 mov r0, r3
|
|
8001052: f7ff fb35 bl 80006c0 <__aeabi_i2d>
|
|
8001056: a35e add r3, pc, #376 @ (adr r3, 80011d0 <HAL_ADC_ConvCpltCallback+0x300>)
|
|
8001058: e9d3 2300 ldrd r2, r3, [r3]
|
|
800105c: f7ff f8b4 bl 80001c8 <__aeabi_dmul>
|
|
8001060: 4602 mov r2, r0
|
|
8001062: 460b mov r3, r1
|
|
8001064: 4610 mov r0, r2
|
|
8001066: 4619 mov r1, r3
|
|
8001068: f7ff fb94 bl 8000794 <__aeabi_d2uiz>
|
|
800106c: 4603 mov r3, r0
|
|
800106e: b29a uxth r2, r3
|
|
8001070: 4b5a ldr r3, [pc, #360] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8001072: 83da strh r2, [r3, #30]
|
|
current_measurements_adc_val.sdc = adc_channels1.adcbank1.isense10 * CURR_SENSE_FACTOR_4_5A;
|
|
8001074: 4b58 ldr r3, [pc, #352] @ (80011d8 <HAL_ADC_ConvCpltCallback+0x308>)
|
|
8001076: 899b ldrh r3, [r3, #12]
|
|
8001078: b29b uxth r3, r3
|
|
800107a: ee07 3a90 vmov s15, r3
|
|
800107e: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001082: ed9f 7a58 vldr s14, [pc, #352] @ 80011e4 <HAL_ADC_ConvCpltCallback+0x314>
|
|
8001086: ee67 7a87 vmul.f32 s15, s15, s14
|
|
800108a: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
800108e: ee17 3a90 vmov r3, s15
|
|
8001092: b29a uxth r2, r3
|
|
8001094: 4b51 ldr r3, [pc, #324] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8001096: 825a strh r2, [r3, #18]
|
|
current_measurements_adc_val.inverter = adc_channels1.adcbank1.isense6 * CURR_SENSE_FACTOR_9A;
|
|
8001098: 4b4f ldr r3, [pc, #316] @ (80011d8 <HAL_ADC_ConvCpltCallback+0x308>)
|
|
800109a: 89db ldrh r3, [r3, #14]
|
|
800109c: b29b uxth r3, r3
|
|
800109e: ee07 3a90 vmov s15, r3
|
|
80010a2: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80010a6: ed9f 7a4e vldr s14, [pc, #312] @ 80011e0 <HAL_ADC_ConvCpltCallback+0x310>
|
|
80010aa: ee67 7a87 vmul.f32 s15, s15, s14
|
|
80010ae: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
80010b2: ee17 3a90 vmov r3, s15
|
|
80010b6: b29a uxth r2, r3
|
|
80010b8: 4b48 ldr r3, [pc, #288] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
80010ba: 815a strh r2, [r3, #10]
|
|
|
|
HAL_GPIO_WritePin(DSEL0_GPIO_Port, DSEL0_Pin, valve3);
|
|
80010bc: 4b4a ldr r3, [pc, #296] @ (80011e8 <HAL_ADC_ConvCpltCallback+0x318>)
|
|
80010be: 781b ldrb r3, [r3, #0]
|
|
80010c0: 461a mov r2, r3
|
|
80010c2: 2110 movs r1, #16
|
|
80010c4: 4849 ldr r0, [pc, #292] @ (80011ec <HAL_ADC_ConvCpltCallback+0x31c>)
|
|
80010c6: f003 fd33 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(DSEL1_GPIO_Port, DSEL1_Pin, valve2);
|
|
80010ca: 4b49 ldr r3, [pc, #292] @ (80011f0 <HAL_ADC_ConvCpltCallback+0x320>)
|
|
80010cc: 781b ldrb r3, [r3, #0]
|
|
80010ce: 461a mov r2, r3
|
|
80010d0: 2120 movs r1, #32
|
|
80010d2: 4846 ldr r0, [pc, #280] @ (80011ec <HAL_ADC_ConvCpltCallback+0x31c>)
|
|
80010d4: f003 fd2c bl 8004b30 <HAL_GPIO_WritePin>
|
|
}
|
|
if (hadc == adc2){
|
|
80010d8: 4b46 ldr r3, [pc, #280] @ (80011f4 <HAL_ADC_ConvCpltCallback+0x324>)
|
|
80010da: 681b ldr r3, [r3, #0]
|
|
80010dc: 687a ldr r2, [r7, #4]
|
|
80010de: 429a cmp r2, r3
|
|
80010e0: d16e bne.n 80011c0 <HAL_ADC_ConvCpltCallback+0x2f0>
|
|
current_measurements_adc_val.drs = adc_channels2.adcbank2.isense3 * CURR_SENSE_FACTOR_4_5A;
|
|
80010e2: 4b45 ldr r3, [pc, #276] @ (80011f8 <HAL_ADC_ConvCpltCallback+0x328>)
|
|
80010e4: 881b ldrh r3, [r3, #0]
|
|
80010e6: b29b uxth r3, r3
|
|
80010e8: ee07 3a90 vmov s15, r3
|
|
80010ec: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80010f0: ed9f 7a3c vldr s14, [pc, #240] @ 80011e4 <HAL_ADC_ConvCpltCallback+0x314>
|
|
80010f4: ee67 7a87 vmul.f32 s15, s15, s14
|
|
80010f8: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
80010fc: ee17 3a90 vmov r3, s15
|
|
8001100: b29a uxth r2, r3
|
|
8001102: 4b36 ldr r3, [pc, #216] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8001104: 809a strh r2, [r3, #4]
|
|
current_measurements_adc_val.misc = adc_channels2.adcbank2.isense8 * CURR_SENSE_FACTOR_4_5A;
|
|
8001106: 4b3c ldr r3, [pc, #240] @ (80011f8 <HAL_ADC_ConvCpltCallback+0x328>)
|
|
8001108: 885b ldrh r3, [r3, #2]
|
|
800110a: b29b uxth r3, r3
|
|
800110c: ee07 3a90 vmov s15, r3
|
|
8001110: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001114: ed9f 7a33 vldr s14, [pc, #204] @ 80011e4 <HAL_ADC_ConvCpltCallback+0x314>
|
|
8001118: ee67 7a87 vmul.f32 s15, s15, s14
|
|
800111c: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001120: ee17 3a90 vmov r3, s15
|
|
8001124: b29a uxth r2, r3
|
|
8001126: 4b2d ldr r3, [pc, #180] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8001128: 81da strh r2, [r3, #14]
|
|
current_measurements_adc_val.acu = adc_channels2.adcbank2.isense4 * CURR_SENSE_FACTOR_9A;
|
|
800112a: 4b33 ldr r3, [pc, #204] @ (80011f8 <HAL_ADC_ConvCpltCallback+0x328>)
|
|
800112c: 889b ldrh r3, [r3, #4]
|
|
800112e: b29b uxth r3, r3
|
|
8001130: ee07 3a90 vmov s15, r3
|
|
8001134: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001138: ed9f 7a29 vldr s14, [pc, #164] @ 80011e0 <HAL_ADC_ConvCpltCallback+0x310>
|
|
800113c: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001140: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001144: ee17 3a90 vmov r3, s15
|
|
8001148: b29a uxth r2, r3
|
|
800114a: 4b24 ldr r3, [pc, #144] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
800114c: 80da strh r2, [r3, #6]
|
|
current_measurements_adc_val.epsc = adc_channels2.adcbank2.isense5 * CURR_SENSE_FACTOR_9A;
|
|
800114e: 4b2a ldr r3, [pc, #168] @ (80011f8 <HAL_ADC_ConvCpltCallback+0x328>)
|
|
8001150: 88db ldrh r3, [r3, #6]
|
|
8001152: b29b uxth r3, r3
|
|
8001154: ee07 3a90 vmov s15, r3
|
|
8001158: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
800115c: ed9f 7a20 vldr s14, [pc, #128] @ 80011e0 <HAL_ADC_ConvCpltCallback+0x310>
|
|
8001160: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001164: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001168: ee17 3a90 vmov r3, s15
|
|
800116c: b29a uxth r2, r3
|
|
800116e: 4b1b ldr r3, [pc, #108] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
8001170: 811a strh r2, [r3, #8]
|
|
current_measurements_adc_val.epsc_precharge = adc_channels2.adcbank2.pc_read * LV_SENSE_FACTOR;
|
|
8001172: 4b21 ldr r3, [pc, #132] @ (80011f8 <HAL_ADC_ConvCpltCallback+0x328>)
|
|
8001174: 891b ldrh r3, [r3, #8]
|
|
8001176: b29b uxth r3, r3
|
|
8001178: 4618 mov r0, r3
|
|
800117a: f7ff faa1 bl 80006c0 <__aeabi_i2d>
|
|
800117e: a314 add r3, pc, #80 @ (adr r3, 80011d0 <HAL_ADC_ConvCpltCallback+0x300>)
|
|
8001180: e9d3 2300 ldrd r2, r3, [r3]
|
|
8001184: f7ff f820 bl 80001c8 <__aeabi_dmul>
|
|
8001188: 4602 mov r2, r0
|
|
800118a: 460b mov r3, r1
|
|
800118c: 4610 mov r0, r2
|
|
800118e: 4619 mov r1, r3
|
|
8001190: f7ff fb00 bl 8000794 <__aeabi_d2uiz>
|
|
8001194: 4603 mov r3, r0
|
|
8001196: b29a uxth r2, r3
|
|
8001198: 4b10 ldr r3, [pc, #64] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
800119a: 835a strh r2, [r3, #26]
|
|
current_measurements_adc_val.lidar = adc_channels2.adcbank2.isense7 * CURR_SENSE_FACTOR_4_5A;
|
|
800119c: 4b16 ldr r3, [pc, #88] @ (80011f8 <HAL_ADC_ConvCpltCallback+0x328>)
|
|
800119e: 895b ldrh r3, [r3, #10]
|
|
80011a0: b29b uxth r3, r3
|
|
80011a2: ee07 3a90 vmov s15, r3
|
|
80011a6: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80011aa: ed9f 7a0e vldr s14, [pc, #56] @ 80011e4 <HAL_ADC_ConvCpltCallback+0x314>
|
|
80011ae: ee67 7a87 vmul.f32 s15, s15, s14
|
|
80011b2: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
80011b6: ee17 3a90 vmov r3, s15
|
|
80011ba: b29a uxth r2, r3
|
|
80011bc: 4b07 ldr r3, [pc, #28] @ (80011dc <HAL_ADC_ConvCpltCallback+0x30c>)
|
|
80011be: 819a strh r2, [r3, #12]
|
|
}
|
|
|
|
check_plausibility();
|
|
80011c0: f000 fc3a bl 8001a38 <check_plausibility>
|
|
}
|
|
80011c4: bf00 nop
|
|
80011c6: 3708 adds r7, #8
|
|
80011c8: 46bd mov sp, r7
|
|
80011ca: bd80 pop {r7, pc}
|
|
80011cc: f3af 8000 nop.w
|
|
80011d0: a56db813 .word 0xa56db813
|
|
80011d4: 401a0c2d .word 0x401a0c2d
|
|
80011d8: 2000007c .word 0x2000007c
|
|
80011dc: 20000098 .word 0x20000098
|
|
80011e0: 40279e79 .word 0x40279e79
|
|
80011e4: 3f9ab9ab .word 0x3f9ab9ab
|
|
80011e8: 200000b9 .word 0x200000b9
|
|
80011ec: 48000400 .word 0x48000400
|
|
80011f0: 200000b8 .word 0x200000b8
|
|
80011f4: 200000c0 .word 0x200000c0
|
|
80011f8: 2000008c .word 0x2000008c
|
|
|
|
080011fc <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
80011fc: b580 push {r7, lr}
|
|
80011fe: b082 sub sp, #8
|
|
8001200: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8001202: f001 f81d bl 8002240 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8001206: f000 f8e5 bl 80013d4 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
800120a: f000 fb89 bl 8001920 <MX_GPIO_Init>
|
|
MX_DMA_Init();
|
|
800120e: f000 fb55 bl 80018bc <MX_DMA_Init>
|
|
MX_ADC1_Init();
|
|
8001212: f000 f93b bl 800148c <MX_ADC1_Init>
|
|
MX_ADC2_Init();
|
|
8001216: f000 fa0d bl 8001634 <MX_ADC2_Init>
|
|
MX_CAN_Init();
|
|
800121a: f000 fab1 bl 8001780 <MX_CAN_Init>
|
|
MX_UART4_Init();
|
|
800121e: f000 fb1d bl 800185c <MX_UART4_Init>
|
|
MX_TIM6_Init();
|
|
8001222: f000 fae3 bl 80017ec <MX_TIM6_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
ChannelControl_init();
|
|
8001226: f7ff fcf5 bl 8000c14 <ChannelControl_init>
|
|
can_init(&hcan);
|
|
800122a: 4860 ldr r0, [pc, #384] @ (80013ac <main+0x1b0>)
|
|
800122c: f7ff fad2 bl 80007d4 <can_init>
|
|
current_monitor_init(&hadc1, &hadc2, &htim6);
|
|
8001230: 4a5f ldr r2, [pc, #380] @ (80013b0 <main+0x1b4>)
|
|
8001232: 4960 ldr r1, [pc, #384] @ (80013b4 <main+0x1b8>)
|
|
8001234: 4860 ldr r0, [pc, #384] @ (80013b8 <main+0x1bc>)
|
|
8001236: f7ff fe09 bl 8000e4c <current_monitor_init>
|
|
uint32_t lasttick = HAL_GetTick(); // time in ms since start
|
|
800123a: f001 f85b bl 80022f4 <HAL_GetTick>
|
|
800123e: 6078 str r0, [r7, #4]
|
|
|
|
// begin start-up animation
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET);
|
|
8001240: 2201 movs r2, #1
|
|
8001242: f44f 7100 mov.w r1, #512 @ 0x200
|
|
8001246: 485d ldr r0, [pc, #372] @ (80013bc <main+0x1c0>)
|
|
8001248: f003 fc72 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_Delay(100);
|
|
800124c: 2064 movs r0, #100 @ 0x64
|
|
800124e: f001 f85d bl 800230c <HAL_Delay>
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
|
|
8001252: 2200 movs r2, #0
|
|
8001254: f44f 7100 mov.w r1, #512 @ 0x200
|
|
8001258: 4858 ldr r0, [pc, #352] @ (80013bc <main+0x1c0>)
|
|
800125a: f003 fc69 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET);
|
|
800125e: 2201 movs r2, #1
|
|
8001260: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8001264: 4855 ldr r0, [pc, #340] @ (80013bc <main+0x1c0>)
|
|
8001266: f003 fc63 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_Delay(100);
|
|
800126a: 2064 movs r0, #100 @ 0x64
|
|
800126c: f001 f84e bl 800230c <HAL_Delay>
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
|
|
8001270: 2200 movs r2, #0
|
|
8001272: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8001276: 4851 ldr r0, [pc, #324] @ (80013bc <main+0x1c0>)
|
|
8001278: f003 fc5a bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_SET);
|
|
800127c: 2201 movs r2, #1
|
|
800127e: 2180 movs r1, #128 @ 0x80
|
|
8001280: 484e ldr r0, [pc, #312] @ (80013bc <main+0x1c0>)
|
|
8001282: f003 fc55 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_Delay(100);
|
|
8001286: 2064 movs r0, #100 @ 0x64
|
|
8001288: f001 f840 bl 800230c <HAL_Delay>
|
|
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
|
|
800128c: 2200 movs r2, #0
|
|
800128e: 2180 movs r1, #128 @ 0x80
|
|
8001290: 484a ldr r0, [pc, #296] @ (80013bc <main+0x1c0>)
|
|
8001292: f003 fc4d bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET);
|
|
8001296: 2201 movs r2, #1
|
|
8001298: 2140 movs r1, #64 @ 0x40
|
|
800129a: 4848 ldr r0, [pc, #288] @ (80013bc <main+0x1c0>)
|
|
800129c: f003 fc48 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_Delay(100);
|
|
80012a0: 2064 movs r0, #100 @ 0x64
|
|
80012a2: f001 f833 bl 800230c <HAL_Delay>
|
|
HAL_GPIO_WritePin(LED4_GPIO_Port, LED3_Pin, GPIO_PIN_SET);
|
|
80012a6: 2201 movs r2, #1
|
|
80012a8: 2180 movs r1, #128 @ 0x80
|
|
80012aa: 4844 ldr r0, [pc, #272] @ (80013bc <main+0x1c0>)
|
|
80012ac: f003 fc40 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_Delay(100);
|
|
80012b0: 2064 movs r0, #100 @ 0x64
|
|
80012b2: f001 f82b bl 800230c <HAL_Delay>
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_SET);
|
|
80012b6: 2201 movs r2, #1
|
|
80012b8: f44f 7180 mov.w r1, #256 @ 0x100
|
|
80012bc: 483f ldr r0, [pc, #252] @ (80013bc <main+0x1c0>)
|
|
80012be: f003 fc37 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_Delay(100);
|
|
80012c2: 2064 movs r0, #100 @ 0x64
|
|
80012c4: f001 f822 bl 800230c <HAL_Delay>
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_SET);
|
|
80012c8: 2201 movs r2, #1
|
|
80012ca: f44f 7100 mov.w r1, #512 @ 0x200
|
|
80012ce: 483b ldr r0, [pc, #236] @ (80013bc <main+0x1c0>)
|
|
80012d0: f003 fc2e bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_Delay(100);
|
|
80012d4: 2064 movs r0, #100 @ 0x64
|
|
80012d6: f001 f819 bl 800230c <HAL_Delay>
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
|
|
80012da: 2200 movs r2, #0
|
|
80012dc: f44f 7100 mov.w r1, #512 @ 0x200
|
|
80012e0: 4836 ldr r0, [pc, #216] @ (80013bc <main+0x1c0>)
|
|
80012e2: f003 fc25 bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET);
|
|
80012e6: 2200 movs r2, #0
|
|
80012e8: f44f 7180 mov.w r1, #256 @ 0x100
|
|
80012ec: 4833 ldr r0, [pc, #204] @ (80013bc <main+0x1c0>)
|
|
80012ee: f003 fc1f bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
|
|
80012f2: 2200 movs r2, #0
|
|
80012f4: 2180 movs r1, #128 @ 0x80
|
|
80012f6: 4831 ldr r0, [pc, #196] @ (80013bc <main+0x1c0>)
|
|
80012f8: f003 fc1a bl 8004b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_RESET);
|
|
80012fc: 2200 movs r2, #0
|
|
80012fe: 2140 movs r1, #64 @ 0x40
|
|
8001300: 482e ldr r0, [pc, #184] @ (80013bc <main+0x1c0>)
|
|
8001302: f003 fc15 bl 8004b30 <HAL_GPIO_WritePin>
|
|
// end start-up animation
|
|
|
|
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, GPIO_PIN_SET); // indicates running STM
|
|
8001306: 2201 movs r2, #1
|
|
8001308: 2140 movs r1, #64 @ 0x40
|
|
800130a: 482c ldr r0, [pc, #176] @ (80013bc <main+0x1c0>)
|
|
800130c: f003 fc10 bl 8004b30 <HAL_GPIO_WritePin>
|
|
|
|
|
|
inhibit_SDC = 0; // allow SDC to be closed
|
|
8001310: 4b2b ldr r3, [pc, #172] @ (80013c0 <main+0x1c4>)
|
|
8001312: 2200 movs r2, #0
|
|
8001314: 601a str r2, [r3, #0]
|
|
while (1)
|
|
{
|
|
/* USER CODE END WHILE */
|
|
|
|
/* USER CODE BEGIN 3 */
|
|
if (canmsg_received){
|
|
8001316: 4b2b ldr r3, [pc, #172] @ (80013c4 <main+0x1c8>)
|
|
8001318: 781b ldrb r3, [r3, #0]
|
|
800131a: b2db uxtb r3, r3
|
|
800131c: 2b00 cmp r3, #0
|
|
800131e: d006 beq.n 800132e <main+0x132>
|
|
canmsg_received = 0;
|
|
8001320: 4b28 ldr r3, [pc, #160] @ (80013c4 <main+0x1c8>)
|
|
8001322: 2200 movs r2, #0
|
|
8001324: 701a strb r2, [r3, #0]
|
|
update_ports = rxstate.iostatus;
|
|
8001326: 4a28 ldr r2, [pc, #160] @ (80013c8 <main+0x1cc>)
|
|
8001328: 4b28 ldr r3, [pc, #160] @ (80013cc <main+0x1d0>)
|
|
800132a: 881b ldrh r3, [r3, #0]
|
|
800132c: 8013 strh r3, [r2, #0]
|
|
}
|
|
if ((HAL_GetTick() - lasttick) > 100u){
|
|
800132e: f000 ffe1 bl 80022f4 <HAL_GetTick>
|
|
8001332: 4602 mov r2, r0
|
|
8001334: 687b ldr r3, [r7, #4]
|
|
8001336: 1ad3 subs r3, r2, r3
|
|
8001338: 2b64 cmp r3, #100 @ 0x64
|
|
800133a: d908 bls.n 800134e <main+0x152>
|
|
lasttick = HAL_GetTick();
|
|
800133c: f000 ffda bl 80022f4 <HAL_GetTick>
|
|
8001340: 6078 str r0, [r7, #4]
|
|
check_plausibility();
|
|
8001342: f000 fb79 bl 8001a38 <check_plausibility>
|
|
can_sendloop();
|
|
8001346: f7ff fa55 bl 80007f4 <can_sendloop>
|
|
can_error_report();
|
|
800134a: f7ff fb4b bl 80009e4 <can_error_report>
|
|
}
|
|
if (((HAL_GetTick() - lastheartbeat) > 200U) && (HAL_GetTick() > 1000U)) {
|
|
800134e: f000 ffd1 bl 80022f4 <HAL_GetTick>
|
|
8001352: 4602 mov r2, r0
|
|
8001354: 4b1e ldr r3, [pc, #120] @ (80013d0 <main+0x1d4>)
|
|
8001356: 681b ldr r3, [r3, #0]
|
|
8001358: 1ad3 subs r3, r2, r3
|
|
800135a: 2bc8 cmp r3, #200 @ 0xc8
|
|
800135c: d908 bls.n 8001370 <main+0x174>
|
|
800135e: f000 ffc9 bl 80022f4 <HAL_GetTick>
|
|
8001362: 4603 mov r3, r0
|
|
8001364: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
8001368: d902 bls.n 8001370 <main+0x174>
|
|
inhibit_SDC = 1;
|
|
800136a: 4b15 ldr r3, [pc, #84] @ (80013c0 <main+0x1c4>)
|
|
800136c: 2201 movs r2, #1
|
|
800136e: 601a str r2, [r3, #0]
|
|
}
|
|
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (GPIO_PinState)!update_ports.portb.sdc); // indicates open SDC
|
|
8001370: 4b15 ldr r3, [pc, #84] @ (80013c8 <main+0x1cc>)
|
|
8001372: 785b ldrb r3, [r3, #1]
|
|
8001374: f3c3 0340 ubfx r3, r3, #1, #1
|
|
8001378: b2db uxtb r3, r3
|
|
800137a: f083 0301 eor.w r3, r3, #1
|
|
800137e: b2db uxtb r3, r3
|
|
8001380: 461a mov r2, r3
|
|
8001382: f44f 7100 mov.w r1, #512 @ 0x200
|
|
8001386: 480d ldr r0, [pc, #52] @ (80013bc <main+0x1c0>)
|
|
8001388: f003 fbd2 bl 8004b30 <HAL_GPIO_WritePin>
|
|
|
|
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (GPIO_PinState)inhibit_SDC); // indicates watchdog-status
|
|
800138c: 4b0c ldr r3, [pc, #48] @ (80013c0 <main+0x1c4>)
|
|
800138e: 681b ldr r3, [r3, #0]
|
|
8001390: b2db uxtb r3, r3
|
|
8001392: 461a mov r2, r3
|
|
8001394: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8001398: 4808 ldr r0, [pc, #32] @ (80013bc <main+0x1c0>)
|
|
800139a: f003 fbc9 bl 8004b30 <HAL_GPIO_WritePin>
|
|
|
|
ChannelControl_UpdateGPIOs(update_ports);
|
|
800139e: 4b0a ldr r3, [pc, #40] @ (80013c8 <main+0x1cc>)
|
|
80013a0: 8818 ldrh r0, [r3, #0]
|
|
80013a2: f7ff fc51 bl 8000c48 <ChannelControl_UpdateGPIOs>
|
|
|
|
current_monitor_checklimits(); // currently not implemented
|
|
80013a6: f7ff fd8b bl 8000ec0 <current_monitor_checklimits>
|
|
if (canmsg_received){
|
|
80013aa: e7b4 b.n 8001316 <main+0x11a>
|
|
80013ac: 200001ec .word 0x200001ec
|
|
80013b0: 20000214 .word 0x20000214
|
|
80013b4: 20000114 .word 0x20000114
|
|
80013b8: 200000c4 .word 0x200000c4
|
|
80013bc: 48000800 .word 0x48000800
|
|
80013c0: 200002f0 .word 0x200002f0
|
|
80013c4: 2000002c .word 0x2000002c
|
|
80013c8: 200002e8 .word 0x200002e8
|
|
80013cc: 20000028 .word 0x20000028
|
|
80013d0: 200002ec .word 0x200002ec
|
|
|
|
080013d4 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
80013d4: b580 push {r7, lr}
|
|
80013d6: b09c sub sp, #112 @ 0x70
|
|
80013d8: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
80013da: f107 0348 add.w r3, r7, #72 @ 0x48
|
|
80013de: 2228 movs r2, #40 @ 0x28
|
|
80013e0: 2100 movs r1, #0
|
|
80013e2: 4618 mov r0, r3
|
|
80013e4: f005 fef1 bl 80071ca <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
80013e8: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
80013ec: 2200 movs r2, #0
|
|
80013ee: 601a str r2, [r3, #0]
|
|
80013f0: 605a str r2, [r3, #4]
|
|
80013f2: 609a str r2, [r3, #8]
|
|
80013f4: 60da str r2, [r3, #12]
|
|
80013f6: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
80013f8: 463b mov r3, r7
|
|
80013fa: 2234 movs r2, #52 @ 0x34
|
|
80013fc: 2100 movs r1, #0
|
|
80013fe: 4618 mov r0, r3
|
|
8001400: f005 fee3 bl 80071ca <memset>
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
8001404: 2301 movs r3, #1
|
|
8001406: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
8001408: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
800140c: 64fb str r3, [r7, #76] @ 0x4c
|
|
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
|
|
800140e: 2300 movs r3, #0
|
|
8001410: 653b str r3, [r7, #80] @ 0x50
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
8001412: 2301 movs r3, #1
|
|
8001414: 65bb str r3, [r7, #88] @ 0x58
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8001416: 2302 movs r3, #2
|
|
8001418: 667b str r3, [r7, #100] @ 0x64
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
800141a: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
800141e: 66bb str r3, [r7, #104] @ 0x68
|
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
|
|
8001420: f44f 2300 mov.w r3, #524288 @ 0x80000
|
|
8001424: 66fb str r3, [r7, #108] @ 0x6c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8001426: f107 0348 add.w r3, r7, #72 @ 0x48
|
|
800142a: 4618 mov r0, r3
|
|
800142c: f003 fb98 bl 8004b60 <HAL_RCC_OscConfig>
|
|
8001430: 4603 mov r3, r0
|
|
8001432: 2b00 cmp r3, #0
|
|
8001434: d001 beq.n 800143a <SystemClock_Config+0x66>
|
|
{
|
|
Error_Handler();
|
|
8001436: f000 faf9 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
800143a: 230f movs r3, #15
|
|
800143c: 637b str r3, [r7, #52] @ 0x34
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
|
|
800143e: 2301 movs r3, #1
|
|
8001440: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8001442: 2300 movs r3, #0
|
|
8001444: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8001446: 2300 movs r3, #0
|
|
8001448: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
800144a: 2300 movs r3, #0
|
|
800144c: 647b str r3, [r7, #68] @ 0x44
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
|
800144e: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8001452: 2100 movs r1, #0
|
|
8001454: 4618 mov r0, r3
|
|
8001456: f004 fbc1 bl 8005bdc <HAL_RCC_ClockConfig>
|
|
800145a: 4603 mov r3, r0
|
|
800145c: 2b00 cmp r3, #0
|
|
800145e: d001 beq.n 8001464 <SystemClock_Config+0x90>
|
|
{
|
|
Error_Handler();
|
|
8001460: f000 fae4 bl 8001a2c <Error_Handler>
|
|
}
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_ADC12;
|
|
8001464: 2388 movs r3, #136 @ 0x88
|
|
8001466: 603b str r3, [r7, #0]
|
|
PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1;
|
|
8001468: 2300 movs r3, #0
|
|
800146a: 617b str r3, [r7, #20]
|
|
PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1;
|
|
800146c: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8001470: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8001472: 463b mov r3, r7
|
|
8001474: 4618 mov r0, r3
|
|
8001476: f004 fdd3 bl 8006020 <HAL_RCCEx_PeriphCLKConfig>
|
|
800147a: 4603 mov r3, r0
|
|
800147c: 2b00 cmp r3, #0
|
|
800147e: d001 beq.n 8001484 <SystemClock_Config+0xb0>
|
|
{
|
|
Error_Handler();
|
|
8001480: f000 fad4 bl 8001a2c <Error_Handler>
|
|
}
|
|
}
|
|
8001484: bf00 nop
|
|
8001486: 3770 adds r7, #112 @ 0x70
|
|
8001488: 46bd mov sp, r7
|
|
800148a: bd80 pop {r7, pc}
|
|
|
|
0800148c <MX_ADC1_Init>:
|
|
* @brief ADC1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_ADC1_Init(void)
|
|
{
|
|
800148c: b580 push {r7, lr}
|
|
800148e: b08a sub sp, #40 @ 0x28
|
|
8001490: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC1_Init 0 */
|
|
|
|
/* USER CODE END ADC1_Init 0 */
|
|
|
|
ADC_MultiModeTypeDef multimode = {0};
|
|
8001492: f107 031c add.w r3, r7, #28
|
|
8001496: 2200 movs r2, #0
|
|
8001498: 601a str r2, [r3, #0]
|
|
800149a: 605a str r2, [r3, #4]
|
|
800149c: 609a str r2, [r3, #8]
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
800149e: 1d3b adds r3, r7, #4
|
|
80014a0: 2200 movs r2, #0
|
|
80014a2: 601a str r2, [r3, #0]
|
|
80014a4: 605a str r2, [r3, #4]
|
|
80014a6: 609a str r2, [r3, #8]
|
|
80014a8: 60da str r2, [r3, #12]
|
|
80014aa: 611a str r2, [r3, #16]
|
|
80014ac: 615a str r2, [r3, #20]
|
|
|
|
/* USER CODE END ADC1_Init 1 */
|
|
|
|
/** Common config
|
|
*/
|
|
hadc1.Instance = ADC1;
|
|
80014ae: 4b60 ldr r3, [pc, #384] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014b0: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
80014b4: 601a str r2, [r3, #0]
|
|
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
|
|
80014b6: 4b5e ldr r3, [pc, #376] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014b8: 2200 movs r2, #0
|
|
80014ba: 605a str r2, [r3, #4]
|
|
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
|
|
80014bc: 4b5c ldr r3, [pc, #368] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014be: 2200 movs r2, #0
|
|
80014c0: 609a str r2, [r3, #8]
|
|
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
|
|
80014c2: 4b5b ldr r3, [pc, #364] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014c4: 2201 movs r2, #1
|
|
80014c6: 611a str r2, [r3, #16]
|
|
hadc1.Init.ContinuousConvMode = DISABLE;
|
|
80014c8: 4b59 ldr r3, [pc, #356] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014ca: 2200 movs r2, #0
|
|
80014cc: 765a strb r2, [r3, #25]
|
|
hadc1.Init.DiscontinuousConvMode = DISABLE;
|
|
80014ce: 4b58 ldr r3, [pc, #352] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014d0: 2200 movs r2, #0
|
|
80014d2: f883 2020 strb.w r2, [r3, #32]
|
|
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
|
|
80014d6: 4b56 ldr r3, [pc, #344] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014d8: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
80014dc: 62da str r2, [r3, #44] @ 0x2c
|
|
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO;
|
|
80014de: 4b54 ldr r3, [pc, #336] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014e0: f44f 7250 mov.w r2, #832 @ 0x340
|
|
80014e4: 629a str r2, [r3, #40] @ 0x28
|
|
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
80014e6: 4b52 ldr r3, [pc, #328] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014e8: 2200 movs r2, #0
|
|
80014ea: 60da str r2, [r3, #12]
|
|
hadc1.Init.NbrOfConversion = 8;
|
|
80014ec: 4b50 ldr r3, [pc, #320] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014ee: 2208 movs r2, #8
|
|
80014f0: 61da str r2, [r3, #28]
|
|
hadc1.Init.DMAContinuousRequests = ENABLE;
|
|
80014f2: 4b4f ldr r3, [pc, #316] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014f4: 2201 movs r2, #1
|
|
80014f6: f883 2030 strb.w r2, [r3, #48] @ 0x30
|
|
hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
|
|
80014fa: 4b4d ldr r3, [pc, #308] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80014fc: 2208 movs r2, #8
|
|
80014fe: 615a str r2, [r3, #20]
|
|
hadc1.Init.LowPowerAutoWait = DISABLE;
|
|
8001500: 4b4b ldr r3, [pc, #300] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
8001502: 2200 movs r2, #0
|
|
8001504: 761a strb r2, [r3, #24]
|
|
hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
|
|
8001506: 4b4a ldr r3, [pc, #296] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
8001508: 2200 movs r2, #0
|
|
800150a: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
|
800150c: 4848 ldr r0, [pc, #288] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
800150e: f000 ff3f bl 8002390 <HAL_ADC_Init>
|
|
8001512: 4603 mov r3, r0
|
|
8001514: 2b00 cmp r3, #0
|
|
8001516: d001 beq.n 800151c <MX_ADC1_Init+0x90>
|
|
{
|
|
Error_Handler();
|
|
8001518: f000 fa88 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure the ADC multi-mode
|
|
*/
|
|
multimode.Mode = ADC_MODE_INDEPENDENT;
|
|
800151c: 2300 movs r3, #0
|
|
800151e: 61fb str r3, [r7, #28]
|
|
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
|
|
8001520: f107 031c add.w r3, r7, #28
|
|
8001524: 4619 mov r1, r3
|
|
8001526: 4842 ldr r0, [pc, #264] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
8001528: f001 fe7e bl 8003228 <HAL_ADCEx_MultiModeConfigChannel>
|
|
800152c: 4603 mov r3, r0
|
|
800152e: 2b00 cmp r3, #0
|
|
8001530: d001 beq.n 8001536 <MX_ADC1_Init+0xaa>
|
|
{
|
|
Error_Handler();
|
|
8001532: f000 fa7b bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_5;
|
|
8001536: 2305 movs r3, #5
|
|
8001538: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
800153a: 2301 movs r3, #1
|
|
800153c: 60bb str r3, [r7, #8]
|
|
sConfig.SingleDiff = ADC_SINGLE_ENDED;
|
|
800153e: 2300 movs r3, #0
|
|
8001540: 613b str r3, [r7, #16]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_61CYCLES_5;
|
|
8001542: 2305 movs r3, #5
|
|
8001544: 60fb str r3, [r7, #12]
|
|
sConfig.OffsetNumber = ADC_OFFSET_NONE;
|
|
8001546: 2300 movs r3, #0
|
|
8001548: 617b str r3, [r7, #20]
|
|
sConfig.Offset = 0;
|
|
800154a: 2300 movs r3, #0
|
|
800154c: 61bb str r3, [r7, #24]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
800154e: 1d3b adds r3, r7, #4
|
|
8001550: 4619 mov r1, r3
|
|
8001552: 4837 ldr r0, [pc, #220] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
8001554: f001 fbaa bl 8002cac <HAL_ADC_ConfigChannel>
|
|
8001558: 4603 mov r3, r0
|
|
800155a: 2b00 cmp r3, #0
|
|
800155c: d001 beq.n 8001562 <MX_ADC1_Init+0xd6>
|
|
{
|
|
Error_Handler();
|
|
800155e: f000 fa65 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_6;
|
|
8001562: 2306 movs r3, #6
|
|
8001564: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_2;
|
|
8001566: 2302 movs r3, #2
|
|
8001568: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
800156a: 1d3b adds r3, r7, #4
|
|
800156c: 4619 mov r1, r3
|
|
800156e: 4830 ldr r0, [pc, #192] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
8001570: f001 fb9c bl 8002cac <HAL_ADC_ConfigChannel>
|
|
8001574: 4603 mov r3, r0
|
|
8001576: 2b00 cmp r3, #0
|
|
8001578: d001 beq.n 800157e <MX_ADC1_Init+0xf2>
|
|
{
|
|
Error_Handler();
|
|
800157a: f000 fa57 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_2;
|
|
800157e: 2302 movs r3, #2
|
|
8001580: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_3;
|
|
8001582: 2303 movs r3, #3
|
|
8001584: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8001586: 1d3b adds r3, r7, #4
|
|
8001588: 4619 mov r1, r3
|
|
800158a: 4829 ldr r0, [pc, #164] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
800158c: f001 fb8e bl 8002cac <HAL_ADC_ConfigChannel>
|
|
8001590: 4603 mov r3, r0
|
|
8001592: 2b00 cmp r3, #0
|
|
8001594: d001 beq.n 800159a <MX_ADC1_Init+0x10e>
|
|
{
|
|
Error_Handler();
|
|
8001596: f000 fa49 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_3;
|
|
800159a: 2303 movs r3, #3
|
|
800159c: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_4;
|
|
800159e: 2304 movs r3, #4
|
|
80015a0: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
80015a2: 1d3b adds r3, r7, #4
|
|
80015a4: 4619 mov r1, r3
|
|
80015a6: 4822 ldr r0, [pc, #136] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80015a8: f001 fb80 bl 8002cac <HAL_ADC_ConfigChannel>
|
|
80015ac: 4603 mov r3, r0
|
|
80015ae: 2b00 cmp r3, #0
|
|
80015b0: d001 beq.n 80015b6 <MX_ADC1_Init+0x12a>
|
|
{
|
|
Error_Handler();
|
|
80015b2: f000 fa3b bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_4;
|
|
80015b6: 2304 movs r3, #4
|
|
80015b8: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_5;
|
|
80015ba: 2305 movs r3, #5
|
|
80015bc: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
80015be: 1d3b adds r3, r7, #4
|
|
80015c0: 4619 mov r1, r3
|
|
80015c2: 481b ldr r0, [pc, #108] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80015c4: f001 fb72 bl 8002cac <HAL_ADC_ConfigChannel>
|
|
80015c8: 4603 mov r3, r0
|
|
80015ca: 2b00 cmp r3, #0
|
|
80015cc: d001 beq.n 80015d2 <MX_ADC1_Init+0x146>
|
|
{
|
|
Error_Handler();
|
|
80015ce: f000 fa2d bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_1;
|
|
80015d2: 2301 movs r3, #1
|
|
80015d4: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_6;
|
|
80015d6: 2306 movs r3, #6
|
|
80015d8: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
80015da: 1d3b adds r3, r7, #4
|
|
80015dc: 4619 mov r1, r3
|
|
80015de: 4814 ldr r0, [pc, #80] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80015e0: f001 fb64 bl 8002cac <HAL_ADC_ConfigChannel>
|
|
80015e4: 4603 mov r3, r0
|
|
80015e6: 2b00 cmp r3, #0
|
|
80015e8: d001 beq.n 80015ee <MX_ADC1_Init+0x162>
|
|
{
|
|
Error_Handler();
|
|
80015ea: f000 fa1f bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_7;
|
|
80015ee: 2307 movs r3, #7
|
|
80015f0: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_7;
|
|
80015f2: 2307 movs r3, #7
|
|
80015f4: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
80015f6: 1d3b adds r3, r7, #4
|
|
80015f8: 4619 mov r1, r3
|
|
80015fa: 480d ldr r0, [pc, #52] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
80015fc: f001 fb56 bl 8002cac <HAL_ADC_ConfigChannel>
|
|
8001600: 4603 mov r3, r0
|
|
8001602: 2b00 cmp r3, #0
|
|
8001604: d001 beq.n 800160a <MX_ADC1_Init+0x17e>
|
|
{
|
|
Error_Handler();
|
|
8001606: f000 fa11 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_8;
|
|
800160a: 2308 movs r3, #8
|
|
800160c: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_8;
|
|
800160e: 2308 movs r3, #8
|
|
8001610: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8001612: 1d3b adds r3, r7, #4
|
|
8001614: 4619 mov r1, r3
|
|
8001616: 4806 ldr r0, [pc, #24] @ (8001630 <MX_ADC1_Init+0x1a4>)
|
|
8001618: f001 fb48 bl 8002cac <HAL_ADC_ConfigChannel>
|
|
800161c: 4603 mov r3, r0
|
|
800161e: 2b00 cmp r3, #0
|
|
8001620: d001 beq.n 8001626 <MX_ADC1_Init+0x19a>
|
|
{
|
|
Error_Handler();
|
|
8001622: f000 fa03 bl 8001a2c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC1_Init 2 */
|
|
|
|
/* USER CODE END ADC1_Init 2 */
|
|
|
|
}
|
|
8001626: bf00 nop
|
|
8001628: 3728 adds r7, #40 @ 0x28
|
|
800162a: 46bd mov sp, r7
|
|
800162c: bd80 pop {r7, pc}
|
|
800162e: bf00 nop
|
|
8001630: 200000c4 .word 0x200000c4
|
|
|
|
08001634 <MX_ADC2_Init>:
|
|
* @brief ADC2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_ADC2_Init(void)
|
|
{
|
|
8001634: b580 push {r7, lr}
|
|
8001636: b086 sub sp, #24
|
|
8001638: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC2_Init 0 */
|
|
|
|
/* USER CODE END ADC2_Init 0 */
|
|
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
800163a: 463b mov r3, r7
|
|
800163c: 2200 movs r2, #0
|
|
800163e: 601a str r2, [r3, #0]
|
|
8001640: 605a str r2, [r3, #4]
|
|
8001642: 609a str r2, [r3, #8]
|
|
8001644: 60da str r2, [r3, #12]
|
|
8001646: 611a str r2, [r3, #16]
|
|
8001648: 615a str r2, [r3, #20]
|
|
|
|
/* USER CODE END ADC2_Init 1 */
|
|
|
|
/** Common config
|
|
*/
|
|
hadc2.Instance = ADC2;
|
|
800164a: 4b4b ldr r3, [pc, #300] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
800164c: 4a4b ldr r2, [pc, #300] @ (800177c <MX_ADC2_Init+0x148>)
|
|
800164e: 601a str r2, [r3, #0]
|
|
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
|
|
8001650: 4b49 ldr r3, [pc, #292] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001652: 2200 movs r2, #0
|
|
8001654: 605a str r2, [r3, #4]
|
|
hadc2.Init.Resolution = ADC_RESOLUTION_12B;
|
|
8001656: 4b48 ldr r3, [pc, #288] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001658: 2200 movs r2, #0
|
|
800165a: 609a str r2, [r3, #8]
|
|
hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
|
|
800165c: 4b46 ldr r3, [pc, #280] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
800165e: 2201 movs r2, #1
|
|
8001660: 611a str r2, [r3, #16]
|
|
hadc2.Init.ContinuousConvMode = DISABLE;
|
|
8001662: 4b45 ldr r3, [pc, #276] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001664: 2200 movs r2, #0
|
|
8001666: 765a strb r2, [r3, #25]
|
|
hadc2.Init.DiscontinuousConvMode = DISABLE;
|
|
8001668: 4b43 ldr r3, [pc, #268] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
800166a: 2200 movs r2, #0
|
|
800166c: f883 2020 strb.w r2, [r3, #32]
|
|
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
|
|
8001670: 4b41 ldr r3, [pc, #260] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001672: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001676: 62da str r2, [r3, #44] @ 0x2c
|
|
hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T6_TRGO;
|
|
8001678: 4b3f ldr r3, [pc, #252] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
800167a: f44f 7250 mov.w r2, #832 @ 0x340
|
|
800167e: 629a str r2, [r3, #40] @ 0x28
|
|
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
8001680: 4b3d ldr r3, [pc, #244] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001682: 2200 movs r2, #0
|
|
8001684: 60da str r2, [r3, #12]
|
|
hadc2.Init.NbrOfConversion = 6;
|
|
8001686: 4b3c ldr r3, [pc, #240] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001688: 2206 movs r2, #6
|
|
800168a: 61da str r2, [r3, #28]
|
|
hadc2.Init.DMAContinuousRequests = ENABLE;
|
|
800168c: 4b3a ldr r3, [pc, #232] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
800168e: 2201 movs r2, #1
|
|
8001690: f883 2030 strb.w r2, [r3, #48] @ 0x30
|
|
hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
|
|
8001694: 4b38 ldr r3, [pc, #224] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001696: 2208 movs r2, #8
|
|
8001698: 615a str r2, [r3, #20]
|
|
hadc2.Init.LowPowerAutoWait = DISABLE;
|
|
800169a: 4b37 ldr r3, [pc, #220] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
800169c: 2200 movs r2, #0
|
|
800169e: 761a strb r2, [r3, #24]
|
|
hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
|
|
80016a0: 4b35 ldr r3, [pc, #212] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
80016a2: 2200 movs r2, #0
|
|
80016a4: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_ADC_Init(&hadc2) != HAL_OK)
|
|
80016a6: 4834 ldr r0, [pc, #208] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
80016a8: f000 fe72 bl 8002390 <HAL_ADC_Init>
|
|
80016ac: 4603 mov r3, r0
|
|
80016ae: 2b00 cmp r3, #0
|
|
80016b0: d001 beq.n 80016b6 <MX_ADC2_Init+0x82>
|
|
{
|
|
Error_Handler();
|
|
80016b2: f000 f9bb bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_1;
|
|
80016b6: 2301 movs r3, #1
|
|
80016b8: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
80016ba: 2301 movs r3, #1
|
|
80016bc: 607b str r3, [r7, #4]
|
|
sConfig.SingleDiff = ADC_SINGLE_ENDED;
|
|
80016be: 2300 movs r3, #0
|
|
80016c0: 60fb str r3, [r7, #12]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_61CYCLES_5;
|
|
80016c2: 2305 movs r3, #5
|
|
80016c4: 60bb str r3, [r7, #8]
|
|
sConfig.OffsetNumber = ADC_OFFSET_NONE;
|
|
80016c6: 2300 movs r3, #0
|
|
80016c8: 613b str r3, [r7, #16]
|
|
sConfig.Offset = 0;
|
|
80016ca: 2300 movs r3, #0
|
|
80016cc: 617b str r3, [r7, #20]
|
|
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
|
80016ce: 463b mov r3, r7
|
|
80016d0: 4619 mov r1, r3
|
|
80016d2: 4829 ldr r0, [pc, #164] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
80016d4: f001 faea bl 8002cac <HAL_ADC_ConfigChannel>
|
|
80016d8: 4603 mov r3, r0
|
|
80016da: 2b00 cmp r3, #0
|
|
80016dc: d001 beq.n 80016e2 <MX_ADC2_Init+0xae>
|
|
{
|
|
Error_Handler();
|
|
80016de: f000 f9a5 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_2;
|
|
80016e2: 2302 movs r3, #2
|
|
80016e4: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_2;
|
|
80016e6: 2302 movs r3, #2
|
|
80016e8: 607b str r3, [r7, #4]
|
|
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
|
80016ea: 463b mov r3, r7
|
|
80016ec: 4619 mov r1, r3
|
|
80016ee: 4822 ldr r0, [pc, #136] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
80016f0: f001 fadc bl 8002cac <HAL_ADC_ConfigChannel>
|
|
80016f4: 4603 mov r3, r0
|
|
80016f6: 2b00 cmp r3, #0
|
|
80016f8: d001 beq.n 80016fe <MX_ADC2_Init+0xca>
|
|
{
|
|
Error_Handler();
|
|
80016fa: f000 f997 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_3;
|
|
80016fe: 2303 movs r3, #3
|
|
8001700: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_3;
|
|
8001702: 2303 movs r3, #3
|
|
8001704: 607b str r3, [r7, #4]
|
|
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
|
8001706: 463b mov r3, r7
|
|
8001708: 4619 mov r1, r3
|
|
800170a: 481b ldr r0, [pc, #108] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
800170c: f001 face bl 8002cac <HAL_ADC_ConfigChannel>
|
|
8001710: 4603 mov r3, r0
|
|
8001712: 2b00 cmp r3, #0
|
|
8001714: d001 beq.n 800171a <MX_ADC2_Init+0xe6>
|
|
{
|
|
Error_Handler();
|
|
8001716: f000 f989 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_4;
|
|
800171a: 2304 movs r3, #4
|
|
800171c: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_4;
|
|
800171e: 2304 movs r3, #4
|
|
8001720: 607b str r3, [r7, #4]
|
|
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
|
8001722: 463b mov r3, r7
|
|
8001724: 4619 mov r1, r3
|
|
8001726: 4814 ldr r0, [pc, #80] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001728: f001 fac0 bl 8002cac <HAL_ADC_ConfigChannel>
|
|
800172c: 4603 mov r3, r0
|
|
800172e: 2b00 cmp r3, #0
|
|
8001730: d001 beq.n 8001736 <MX_ADC2_Init+0x102>
|
|
{
|
|
Error_Handler();
|
|
8001732: f000 f97b bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_5;
|
|
8001736: 2305 movs r3, #5
|
|
8001738: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_5;
|
|
800173a: 2305 movs r3, #5
|
|
800173c: 607b str r3, [r7, #4]
|
|
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
|
800173e: 463b mov r3, r7
|
|
8001740: 4619 mov r1, r3
|
|
8001742: 480d ldr r0, [pc, #52] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001744: f001 fab2 bl 8002cac <HAL_ADC_ConfigChannel>
|
|
8001748: 4603 mov r3, r0
|
|
800174a: 2b00 cmp r3, #0
|
|
800174c: d001 beq.n 8001752 <MX_ADC2_Init+0x11e>
|
|
{
|
|
Error_Handler();
|
|
800174e: f000 f96d bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_9;
|
|
8001752: 2309 movs r3, #9
|
|
8001754: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_6;
|
|
8001756: 2306 movs r3, #6
|
|
8001758: 607b str r3, [r7, #4]
|
|
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
|
800175a: 463b mov r3, r7
|
|
800175c: 4619 mov r1, r3
|
|
800175e: 4806 ldr r0, [pc, #24] @ (8001778 <MX_ADC2_Init+0x144>)
|
|
8001760: f001 faa4 bl 8002cac <HAL_ADC_ConfigChannel>
|
|
8001764: 4603 mov r3, r0
|
|
8001766: 2b00 cmp r3, #0
|
|
8001768: d001 beq.n 800176e <MX_ADC2_Init+0x13a>
|
|
{
|
|
Error_Handler();
|
|
800176a: f000 f95f bl 8001a2c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC2_Init 2 */
|
|
|
|
/* USER CODE END ADC2_Init 2 */
|
|
|
|
}
|
|
800176e: bf00 nop
|
|
8001770: 3718 adds r7, #24
|
|
8001772: 46bd mov sp, r7
|
|
8001774: bd80 pop {r7, pc}
|
|
8001776: bf00 nop
|
|
8001778: 20000114 .word 0x20000114
|
|
800177c: 50000100 .word 0x50000100
|
|
|
|
08001780 <MX_CAN_Init>:
|
|
* @brief CAN Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_CAN_Init(void)
|
|
{
|
|
8001780: b580 push {r7, lr}
|
|
8001782: af00 add r7, sp, #0
|
|
/* USER CODE END CAN_Init 0 */
|
|
|
|
/* USER CODE BEGIN CAN_Init 1 */
|
|
|
|
/* USER CODE END CAN_Init 1 */
|
|
hcan.Instance = CAN;
|
|
8001784: 4b17 ldr r3, [pc, #92] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
8001786: 4a18 ldr r2, [pc, #96] @ (80017e8 <MX_CAN_Init+0x68>)
|
|
8001788: 601a str r2, [r3, #0]
|
|
hcan.Init.Prescaler = 2;
|
|
800178a: 4b16 ldr r3, [pc, #88] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
800178c: 2202 movs r2, #2
|
|
800178e: 605a str r2, [r3, #4]
|
|
hcan.Init.Mode = CAN_MODE_NORMAL;
|
|
8001790: 4b14 ldr r3, [pc, #80] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
8001792: 2200 movs r2, #0
|
|
8001794: 609a str r2, [r3, #8]
|
|
hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;
|
|
8001796: 4b13 ldr r3, [pc, #76] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
8001798: 2200 movs r2, #0
|
|
800179a: 60da str r2, [r3, #12]
|
|
hcan.Init.TimeSeg1 = CAN_BS1_13TQ;
|
|
800179c: 4b11 ldr r3, [pc, #68] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
800179e: f44f 2240 mov.w r2, #786432 @ 0xc0000
|
|
80017a2: 611a str r2, [r3, #16]
|
|
hcan.Init.TimeSeg2 = CAN_BS2_2TQ;
|
|
80017a4: 4b0f ldr r3, [pc, #60] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
80017a6: f44f 1280 mov.w r2, #1048576 @ 0x100000
|
|
80017aa: 615a str r2, [r3, #20]
|
|
hcan.Init.TimeTriggeredMode = DISABLE;
|
|
80017ac: 4b0d ldr r3, [pc, #52] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
80017ae: 2200 movs r2, #0
|
|
80017b0: 761a strb r2, [r3, #24]
|
|
hcan.Init.AutoBusOff = DISABLE;
|
|
80017b2: 4b0c ldr r3, [pc, #48] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
80017b4: 2200 movs r2, #0
|
|
80017b6: 765a strb r2, [r3, #25]
|
|
hcan.Init.AutoWakeUp = DISABLE;
|
|
80017b8: 4b0a ldr r3, [pc, #40] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
80017ba: 2200 movs r2, #0
|
|
80017bc: 769a strb r2, [r3, #26]
|
|
hcan.Init.AutoRetransmission = DISABLE;
|
|
80017be: 4b09 ldr r3, [pc, #36] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
80017c0: 2200 movs r2, #0
|
|
80017c2: 76da strb r2, [r3, #27]
|
|
hcan.Init.ReceiveFifoLocked = DISABLE;
|
|
80017c4: 4b07 ldr r3, [pc, #28] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
80017c6: 2200 movs r2, #0
|
|
80017c8: 771a strb r2, [r3, #28]
|
|
hcan.Init.TransmitFifoPriority = DISABLE;
|
|
80017ca: 4b06 ldr r3, [pc, #24] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
80017cc: 2200 movs r2, #0
|
|
80017ce: 775a strb r2, [r3, #29]
|
|
if (HAL_CAN_Init(&hcan) != HAL_OK)
|
|
80017d0: 4804 ldr r0, [pc, #16] @ (80017e4 <MX_CAN_Init+0x64>)
|
|
80017d2: f001 ff1f bl 8003614 <HAL_CAN_Init>
|
|
80017d6: 4603 mov r3, r0
|
|
80017d8: 2b00 cmp r3, #0
|
|
80017da: d001 beq.n 80017e0 <MX_CAN_Init+0x60>
|
|
{
|
|
Error_Handler();
|
|
80017dc: f000 f926 bl 8001a2c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN CAN_Init 2 */
|
|
|
|
/* USER CODE END CAN_Init 2 */
|
|
|
|
}
|
|
80017e0: bf00 nop
|
|
80017e2: bd80 pop {r7, pc}
|
|
80017e4: 200001ec .word 0x200001ec
|
|
80017e8: 40006400 .word 0x40006400
|
|
|
|
080017ec <MX_TIM6_Init>:
|
|
* @brief TIM6 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM6_Init(void)
|
|
{
|
|
80017ec: b580 push {r7, lr}
|
|
80017ee: b084 sub sp, #16
|
|
80017f0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM6_Init 0 */
|
|
|
|
/* USER CODE END TIM6_Init 0 */
|
|
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
80017f2: 1d3b adds r3, r7, #4
|
|
80017f4: 2200 movs r2, #0
|
|
80017f6: 601a str r2, [r3, #0]
|
|
80017f8: 605a str r2, [r3, #4]
|
|
80017fa: 609a str r2, [r3, #8]
|
|
|
|
/* USER CODE BEGIN TIM6_Init 1 */
|
|
|
|
/* USER CODE END TIM6_Init 1 */
|
|
htim6.Instance = TIM6;
|
|
80017fc: 4b15 ldr r3, [pc, #84] @ (8001854 <MX_TIM6_Init+0x68>)
|
|
80017fe: 4a16 ldr r2, [pc, #88] @ (8001858 <MX_TIM6_Init+0x6c>)
|
|
8001800: 601a str r2, [r3, #0]
|
|
htim6.Init.Prescaler = 400;
|
|
8001802: 4b14 ldr r3, [pc, #80] @ (8001854 <MX_TIM6_Init+0x68>)
|
|
8001804: f44f 72c8 mov.w r2, #400 @ 0x190
|
|
8001808: 605a str r2, [r3, #4]
|
|
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800180a: 4b12 ldr r3, [pc, #72] @ (8001854 <MX_TIM6_Init+0x68>)
|
|
800180c: 2200 movs r2, #0
|
|
800180e: 609a str r2, [r3, #8]
|
|
htim6.Init.Period = 8000-1;
|
|
8001810: 4b10 ldr r3, [pc, #64] @ (8001854 <MX_TIM6_Init+0x68>)
|
|
8001812: f641 723f movw r2, #7999 @ 0x1f3f
|
|
8001816: 60da str r2, [r3, #12]
|
|
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001818: 4b0e ldr r3, [pc, #56] @ (8001854 <MX_TIM6_Init+0x68>)
|
|
800181a: 2200 movs r2, #0
|
|
800181c: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
|
|
800181e: 480d ldr r0, [pc, #52] @ (8001854 <MX_TIM6_Init+0x68>)
|
|
8001820: f004 fd90 bl 8006344 <HAL_TIM_Base_Init>
|
|
8001824: 4603 mov r3, r0
|
|
8001826: 2b00 cmp r3, #0
|
|
8001828: d001 beq.n 800182e <MX_TIM6_Init+0x42>
|
|
{
|
|
Error_Handler();
|
|
800182a: f000 f8ff bl 8001a2c <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
|
|
800182e: 2320 movs r3, #32
|
|
8001830: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8001832: 2300 movs r3, #0
|
|
8001834: 60fb str r3, [r7, #12]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
|
|
8001836: 1d3b adds r3, r7, #4
|
|
8001838: 4619 mov r1, r3
|
|
800183a: 4806 ldr r0, [pc, #24] @ (8001854 <MX_TIM6_Init+0x68>)
|
|
800183c: f004 fff6 bl 800682c <HAL_TIMEx_MasterConfigSynchronization>
|
|
8001840: 4603 mov r3, r0
|
|
8001842: 2b00 cmp r3, #0
|
|
8001844: d001 beq.n 800184a <MX_TIM6_Init+0x5e>
|
|
{
|
|
Error_Handler();
|
|
8001846: f000 f8f1 bl 8001a2c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM6_Init 2 */
|
|
|
|
/* USER CODE END TIM6_Init 2 */
|
|
|
|
}
|
|
800184a: bf00 nop
|
|
800184c: 3710 adds r7, #16
|
|
800184e: 46bd mov sp, r7
|
|
8001850: bd80 pop {r7, pc}
|
|
8001852: bf00 nop
|
|
8001854: 20000214 .word 0x20000214
|
|
8001858: 40001000 .word 0x40001000
|
|
|
|
0800185c <MX_UART4_Init>:
|
|
* @brief UART4 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART4_Init(void)
|
|
{
|
|
800185c: b580 push {r7, lr}
|
|
800185e: af00 add r7, sp, #0
|
|
/* USER CODE END UART4_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART4_Init 1 */
|
|
|
|
/* USER CODE END UART4_Init 1 */
|
|
huart4.Instance = UART4;
|
|
8001860: 4b14 ldr r3, [pc, #80] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
8001862: 4a15 ldr r2, [pc, #84] @ (80018b8 <MX_UART4_Init+0x5c>)
|
|
8001864: 601a str r2, [r3, #0]
|
|
huart4.Init.BaudRate = 115200;
|
|
8001866: 4b13 ldr r3, [pc, #76] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
8001868: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
800186c: 605a str r2, [r3, #4]
|
|
huart4.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800186e: 4b11 ldr r3, [pc, #68] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
8001870: 2200 movs r2, #0
|
|
8001872: 609a str r2, [r3, #8]
|
|
huart4.Init.StopBits = UART_STOPBITS_1;
|
|
8001874: 4b0f ldr r3, [pc, #60] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
8001876: 2200 movs r2, #0
|
|
8001878: 60da str r2, [r3, #12]
|
|
huart4.Init.Parity = UART_PARITY_NONE;
|
|
800187a: 4b0e ldr r3, [pc, #56] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
800187c: 2200 movs r2, #0
|
|
800187e: 611a str r2, [r3, #16]
|
|
huart4.Init.Mode = UART_MODE_TX_RX;
|
|
8001880: 4b0c ldr r3, [pc, #48] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
8001882: 220c movs r2, #12
|
|
8001884: 615a str r2, [r3, #20]
|
|
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001886: 4b0b ldr r3, [pc, #44] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
8001888: 2200 movs r2, #0
|
|
800188a: 619a str r2, [r3, #24]
|
|
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
800188c: 4b09 ldr r3, [pc, #36] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
800188e: 2200 movs r2, #0
|
|
8001890: 61da str r2, [r3, #28]
|
|
huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8001892: 4b08 ldr r3, [pc, #32] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
8001894: 2200 movs r2, #0
|
|
8001896: 621a str r2, [r3, #32]
|
|
huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8001898: 4b06 ldr r3, [pc, #24] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
800189a: 2200 movs r2, #0
|
|
800189c: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_UART_Init(&huart4) != HAL_OK)
|
|
800189e: 4805 ldr r0, [pc, #20] @ (80018b4 <MX_UART4_Init+0x58>)
|
|
80018a0: f005 f856 bl 8006950 <HAL_UART_Init>
|
|
80018a4: 4603 mov r3, r0
|
|
80018a6: 2b00 cmp r3, #0
|
|
80018a8: d001 beq.n 80018ae <MX_UART4_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
80018aa: f000 f8bf bl 8001a2c <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART4_Init 2 */
|
|
|
|
/* USER CODE END UART4_Init 2 */
|
|
|
|
}
|
|
80018ae: bf00 nop
|
|
80018b0: bd80 pop {r7, pc}
|
|
80018b2: bf00 nop
|
|
80018b4: 20000260 .word 0x20000260
|
|
80018b8: 40004c00 .word 0x40004c00
|
|
|
|
080018bc <MX_DMA_Init>:
|
|
|
|
/**
|
|
* Enable DMA controller clock
|
|
*/
|
|
static void MX_DMA_Init(void)
|
|
{
|
|
80018bc: b580 push {r7, lr}
|
|
80018be: b082 sub sp, #8
|
|
80018c0: af00 add r7, sp, #0
|
|
|
|
/* DMA controller clock enable */
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
80018c2: 4b16 ldr r3, [pc, #88] @ (800191c <MX_DMA_Init+0x60>)
|
|
80018c4: 695b ldr r3, [r3, #20]
|
|
80018c6: 4a15 ldr r2, [pc, #84] @ (800191c <MX_DMA_Init+0x60>)
|
|
80018c8: f043 0301 orr.w r3, r3, #1
|
|
80018cc: 6153 str r3, [r2, #20]
|
|
80018ce: 4b13 ldr r3, [pc, #76] @ (800191c <MX_DMA_Init+0x60>)
|
|
80018d0: 695b ldr r3, [r3, #20]
|
|
80018d2: f003 0301 and.w r3, r3, #1
|
|
80018d6: 607b str r3, [r7, #4]
|
|
80018d8: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_DMA2_CLK_ENABLE();
|
|
80018da: 4b10 ldr r3, [pc, #64] @ (800191c <MX_DMA_Init+0x60>)
|
|
80018dc: 695b ldr r3, [r3, #20]
|
|
80018de: 4a0f ldr r2, [pc, #60] @ (800191c <MX_DMA_Init+0x60>)
|
|
80018e0: f043 0302 orr.w r3, r3, #2
|
|
80018e4: 6153 str r3, [r2, #20]
|
|
80018e6: 4b0d ldr r3, [pc, #52] @ (800191c <MX_DMA_Init+0x60>)
|
|
80018e8: 695b ldr r3, [r3, #20]
|
|
80018ea: f003 0302 and.w r3, r3, #2
|
|
80018ee: 603b str r3, [r7, #0]
|
|
80018f0: 683b ldr r3, [r7, #0]
|
|
|
|
/* DMA interrupt init */
|
|
/* DMA1_Channel1_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
|
|
80018f2: 2200 movs r2, #0
|
|
80018f4: 2100 movs r1, #0
|
|
80018f6: 200b movs r0, #11
|
|
80018f8: f002 fdb7 bl 800446a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
|
|
80018fc: 200b movs r0, #11
|
|
80018fe: f002 fdd0 bl 80044a2 <HAL_NVIC_EnableIRQ>
|
|
/* DMA2_Channel1_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(DMA2_Channel1_IRQn, 0, 0);
|
|
8001902: 2200 movs r2, #0
|
|
8001904: 2100 movs r1, #0
|
|
8001906: 2038 movs r0, #56 @ 0x38
|
|
8001908: f002 fdaf bl 800446a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2_Channel1_IRQn);
|
|
800190c: 2038 movs r0, #56 @ 0x38
|
|
800190e: f002 fdc8 bl 80044a2 <HAL_NVIC_EnableIRQ>
|
|
|
|
}
|
|
8001912: bf00 nop
|
|
8001914: 3708 adds r7, #8
|
|
8001916: 46bd mov sp, r7
|
|
8001918: bd80 pop {r7, pc}
|
|
800191a: bf00 nop
|
|
800191c: 40021000 .word 0x40021000
|
|
|
|
08001920 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8001920: b580 push {r7, lr}
|
|
8001922: b08a sub sp, #40 @ 0x28
|
|
8001924: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001926: f107 0314 add.w r3, r7, #20
|
|
800192a: 2200 movs r2, #0
|
|
800192c: 601a str r2, [r3, #0]
|
|
800192e: 605a str r2, [r3, #4]
|
|
8001930: 609a str r2, [r3, #8]
|
|
8001932: 60da str r2, [r3, #12]
|
|
8001934: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8001936: 4b3a ldr r3, [pc, #232] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
8001938: 695b ldr r3, [r3, #20]
|
|
800193a: 4a39 ldr r2, [pc, #228] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
800193c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8001940: 6153 str r3, [r2, #20]
|
|
8001942: 4b37 ldr r3, [pc, #220] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
8001944: 695b ldr r3, [r3, #20]
|
|
8001946: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800194a: 613b str r3, [r7, #16]
|
|
800194c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800194e: 4b34 ldr r3, [pc, #208] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
8001950: 695b ldr r3, [r3, #20]
|
|
8001952: 4a33 ldr r2, [pc, #204] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
8001954: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8001958: 6153 str r3, [r2, #20]
|
|
800195a: 4b31 ldr r3, [pc, #196] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
800195c: 695b ldr r3, [r3, #20]
|
|
800195e: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8001962: 60fb str r3, [r7, #12]
|
|
8001964: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001966: 4b2e ldr r3, [pc, #184] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
8001968: 695b ldr r3, [r3, #20]
|
|
800196a: 4a2d ldr r2, [pc, #180] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
800196c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001970: 6153 str r3, [r2, #20]
|
|
8001972: 4b2b ldr r3, [pc, #172] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
8001974: 695b ldr r3, [r3, #20]
|
|
8001976: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800197a: 60bb str r3, [r7, #8]
|
|
800197c: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800197e: 4b28 ldr r3, [pc, #160] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
8001980: 695b ldr r3, [r3, #20]
|
|
8001982: 4a27 ldr r2, [pc, #156] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
8001984: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8001988: 6153 str r3, [r2, #20]
|
|
800198a: 4b25 ldr r3, [pc, #148] @ (8001a20 <MX_GPIO_Init+0x100>)
|
|
800198c: 695b ldr r3, [r3, #20]
|
|
800198e: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8001992: 607b str r3, [r7, #4]
|
|
8001994: 687b ldr r3, [r7, #4]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOB, IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin
|
|
8001996: 2200 movs r2, #0
|
|
8001998: f64f 7176 movw r1, #65398 @ 0xff76
|
|
800199c: 4821 ldr r0, [pc, #132] @ (8001a24 <MX_GPIO_Init+0x104>)
|
|
800199e: f003 f8c7 bl 8004b30 <HAL_GPIO_WritePin>
|
|
|IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin
|
|
|DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin
|
|
|IN10_Pin, GPIO_PIN_RESET);
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin, GPIO_PIN_RESET);
|
|
80019a2: 2200 movs r2, #0
|
|
80019a4: f44f 7170 mov.w r1, #960 @ 0x3c0
|
|
80019a8: 481f ldr r0, [pc, #124] @ (8001a28 <MX_GPIO_Init+0x108>)
|
|
80019aa: f003 f8c1 bl 8004b30 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, IN2_Pin|IN1_Pin|IN6_Pin, GPIO_PIN_RESET);
|
|
80019ae: 2200 movs r2, #0
|
|
80019b0: f44f 61e0 mov.w r1, #1792 @ 0x700
|
|
80019b4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80019b8: f003 f8ba bl 8004b30 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : IN12_Pin IN11_Pin IN13_Pin IN9_Pin
|
|
IN3_Pin IN8_Pin IN5_Pin IN4_Pin
|
|
DSEL0_Pin DSEL1_Pin PC_EN_Pin IN7_Pin
|
|
IN10_Pin */
|
|
GPIO_InitStruct.Pin = IN12_Pin|IN11_Pin|IN13_Pin|IN9_Pin
|
|
80019bc: f64f 7376 movw r3, #65398 @ 0xff76
|
|
80019c0: 617b str r3, [r7, #20]
|
|
|IN3_Pin|IN8_Pin|IN5_Pin|IN4_Pin
|
|
|DSEL0_Pin|DSEL1_Pin|PC_EN_Pin|IN7_Pin
|
|
|IN10_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80019c2: 2301 movs r3, #1
|
|
80019c4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80019c6: 2300 movs r3, #0
|
|
80019c8: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80019ca: 2300 movs r3, #0
|
|
80019cc: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80019ce: f107 0314 add.w r3, r7, #20
|
|
80019d2: 4619 mov r1, r3
|
|
80019d4: 4813 ldr r0, [pc, #76] @ (8001a24 <MX_GPIO_Init+0x104>)
|
|
80019d6: f002 ff31 bl 800483c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LED4_Pin LED3_Pin LED2_Pin LED1_Pin */
|
|
GPIO_InitStruct.Pin = LED4_Pin|LED3_Pin|LED2_Pin|LED1_Pin;
|
|
80019da: f44f 7370 mov.w r3, #960 @ 0x3c0
|
|
80019de: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80019e0: 2301 movs r3, #1
|
|
80019e2: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80019e4: 2300 movs r3, #0
|
|
80019e6: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80019e8: 2300 movs r3, #0
|
|
80019ea: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80019ec: f107 0314 add.w r3, r7, #20
|
|
80019f0: 4619 mov r1, r3
|
|
80019f2: 480d ldr r0, [pc, #52] @ (8001a28 <MX_GPIO_Init+0x108>)
|
|
80019f4: f002 ff22 bl 800483c <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : IN2_Pin IN1_Pin IN6_Pin */
|
|
GPIO_InitStruct.Pin = IN2_Pin|IN1_Pin|IN6_Pin;
|
|
80019f8: f44f 63e0 mov.w r3, #1792 @ 0x700
|
|
80019fc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80019fe: 2301 movs r3, #1
|
|
8001a00: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001a02: 2300 movs r3, #0
|
|
8001a04: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001a06: 2300 movs r3, #0
|
|
8001a08: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001a0a: f107 0314 add.w r3, r7, #20
|
|
8001a0e: 4619 mov r1, r3
|
|
8001a10: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001a14: f002 ff12 bl 800483c <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8001a18: bf00 nop
|
|
8001a1a: 3728 adds r7, #40 @ 0x28
|
|
8001a1c: 46bd mov sp, r7
|
|
8001a1e: bd80 pop {r7, pc}
|
|
8001a20: 40021000 .word 0x40021000
|
|
8001a24: 48000400 .word 0x48000400
|
|
8001a28: 48000800 .word 0x48000800
|
|
|
|
08001a2c <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8001a2c: b480 push {r7}
|
|
8001a2e: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8001a30: b672 cpsid i
|
|
}
|
|
8001a32: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8001a34: bf00 nop
|
|
8001a36: e7fd b.n 8001a34 <Error_Handler+0x8>
|
|
|
|
08001a38 <check_plausibility>:
|
|
extern enable_gpios update_ports;
|
|
extern current_measurements current_measurements_adc_val;
|
|
volatile err_states error;
|
|
extern int inhibit_SDC;
|
|
|
|
void check_plausibility() {
|
|
8001a38: b480 push {r7}
|
|
8001a3a: af00 add r7, sp, #0
|
|
if (!update_ports.portb.sdc || inhibit_SDC == 1) {error.group1.sdc_open = 1;}
|
|
8001a3c: 4b9c ldr r3, [pc, #624] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001a3e: 785b ldrb r3, [r3, #1]
|
|
8001a40: f003 0302 and.w r3, r3, #2
|
|
8001a44: b2db uxtb r3, r3
|
|
8001a46: 2b00 cmp r3, #0
|
|
8001a48: d003 beq.n 8001a52 <check_plausibility+0x1a>
|
|
8001a4a: 4b9a ldr r3, [pc, #616] @ (8001cb4 <check_plausibility+0x27c>)
|
|
8001a4c: 681b ldr r3, [r3, #0]
|
|
8001a4e: 2b01 cmp r3, #1
|
|
8001a50: d105 bne.n 8001a5e <check_plausibility+0x26>
|
|
8001a52: 4a99 ldr r2, [pc, #612] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001a54: 7813 ldrb r3, [r2, #0]
|
|
8001a56: f043 0301 orr.w r3, r3, #1
|
|
8001a5a: 7013 strb r3, [r2, #0]
|
|
8001a5c: e004 b.n 8001a68 <check_plausibility+0x30>
|
|
else {error.group1.sdc_open = 0;}
|
|
8001a5e: 4a96 ldr r2, [pc, #600] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001a60: 7813 ldrb r3, [r2, #0]
|
|
8001a62: f36f 0300 bfc r3, #0, #1
|
|
8001a66: 7013 strb r3, [r2, #0]
|
|
|
|
if (update_ports.porta.acc_cooling == 1 && current_measurements_adc_val.acc_cooling == 0) {
|
|
8001a68: 4b91 ldr r3, [pc, #580] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001a6a: 781b ldrb r3, [r3, #0]
|
|
8001a6c: f003 0301 and.w r3, r3, #1
|
|
8001a70: b2db uxtb r3, r3
|
|
8001a72: 2b00 cmp r3, #0
|
|
8001a74: d009 beq.n 8001a8a <check_plausibility+0x52>
|
|
8001a76: 4b91 ldr r3, [pc, #580] @ (8001cbc <check_plausibility+0x284>)
|
|
8001a78: 881b ldrh r3, [r3, #0]
|
|
8001a7a: 2b00 cmp r3, #0
|
|
8001a7c: d105 bne.n 8001a8a <check_plausibility+0x52>
|
|
error.group1.noload_acc_cooling = 1;
|
|
8001a7e: 4a8e ldr r2, [pc, #568] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001a80: 7813 ldrb r3, [r2, #0]
|
|
8001a82: f043 0302 orr.w r3, r3, #2
|
|
8001a86: 7013 strb r3, [r2, #0]
|
|
8001a88: e004 b.n 8001a94 <check_plausibility+0x5c>
|
|
}
|
|
else {
|
|
error.group1.noload_acc_cooling = 0;
|
|
8001a8a: 4a8b ldr r2, [pc, #556] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001a8c: 7813 ldrb r3, [r2, #0]
|
|
8001a8e: f36f 0341 bfc r3, #1, #1
|
|
8001a92: 7013 strb r3, [r2, #0]
|
|
}
|
|
|
|
if (update_ports.porta.ts_cooling == 1 && current_measurements_adc_val.ts_cooling == 0) {
|
|
8001a94: 4b86 ldr r3, [pc, #536] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001a96: 781b ldrb r3, [r3, #0]
|
|
8001a98: f003 0302 and.w r3, r3, #2
|
|
8001a9c: b2db uxtb r3, r3
|
|
8001a9e: 2b00 cmp r3, #0
|
|
8001aa0: d009 beq.n 8001ab6 <check_plausibility+0x7e>
|
|
8001aa2: 4b86 ldr r3, [pc, #536] @ (8001cbc <check_plausibility+0x284>)
|
|
8001aa4: 885b ldrh r3, [r3, #2]
|
|
8001aa6: 2b00 cmp r3, #0
|
|
8001aa8: d105 bne.n 8001ab6 <check_plausibility+0x7e>
|
|
error.group1.noload_ts_cooling = 1;
|
|
8001aaa: 4a83 ldr r2, [pc, #524] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001aac: 7813 ldrb r3, [r2, #0]
|
|
8001aae: f043 0304 orr.w r3, r3, #4
|
|
8001ab2: 7013 strb r3, [r2, #0]
|
|
8001ab4: e004 b.n 8001ac0 <check_plausibility+0x88>
|
|
}
|
|
else {
|
|
error.group1.noload_ts_cooling = 0;
|
|
8001ab6: 4a80 ldr r2, [pc, #512] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001ab8: 7813 ldrb r3, [r2, #0]
|
|
8001aba: f36f 0382 bfc r3, #2, #1
|
|
8001abe: 7013 strb r3, [r2, #0]
|
|
}
|
|
|
|
if (update_ports.porta.drs == 1 && current_measurements_adc_val.drs == 0) {
|
|
8001ac0: 4b7b ldr r3, [pc, #492] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001ac2: 781b ldrb r3, [r3, #0]
|
|
8001ac4: f003 0304 and.w r3, r3, #4
|
|
8001ac8: b2db uxtb r3, r3
|
|
8001aca: 2b00 cmp r3, #0
|
|
8001acc: d009 beq.n 8001ae2 <check_plausibility+0xaa>
|
|
8001ace: 4b7b ldr r3, [pc, #492] @ (8001cbc <check_plausibility+0x284>)
|
|
8001ad0: 889b ldrh r3, [r3, #4]
|
|
8001ad2: 2b00 cmp r3, #0
|
|
8001ad4: d105 bne.n 8001ae2 <check_plausibility+0xaa>
|
|
error.group1.noload_drs = 1;
|
|
8001ad6: 4a78 ldr r2, [pc, #480] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001ad8: 7813 ldrb r3, [r2, #0]
|
|
8001ada: f043 0308 orr.w r3, r3, #8
|
|
8001ade: 7013 strb r3, [r2, #0]
|
|
8001ae0: e004 b.n 8001aec <check_plausibility+0xb4>
|
|
}
|
|
else {
|
|
error.group1.noload_drs = 0;
|
|
8001ae2: 4a75 ldr r2, [pc, #468] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001ae4: 7813 ldrb r3, [r2, #0]
|
|
8001ae6: f36f 03c3 bfc r3, #3, #1
|
|
8001aea: 7013 strb r3, [r2, #0]
|
|
}
|
|
|
|
if (update_ports.porta.acu == 1 && current_measurements_adc_val.acu == 0) {
|
|
8001aec: 4b70 ldr r3, [pc, #448] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001aee: 781b ldrb r3, [r3, #0]
|
|
8001af0: f003 0308 and.w r3, r3, #8
|
|
8001af4: b2db uxtb r3, r3
|
|
8001af6: 2b00 cmp r3, #0
|
|
8001af8: d009 beq.n 8001b0e <check_plausibility+0xd6>
|
|
8001afa: 4b70 ldr r3, [pc, #448] @ (8001cbc <check_plausibility+0x284>)
|
|
8001afc: 88db ldrh r3, [r3, #6]
|
|
8001afe: 2b00 cmp r3, #0
|
|
8001b00: d105 bne.n 8001b0e <check_plausibility+0xd6>
|
|
error.group1.noload_acu = 1;
|
|
8001b02: 4a6d ldr r2, [pc, #436] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001b04: 7813 ldrb r3, [r2, #0]
|
|
8001b06: f043 0310 orr.w r3, r3, #16
|
|
8001b0a: 7013 strb r3, [r2, #0]
|
|
8001b0c: e004 b.n 8001b18 <check_plausibility+0xe0>
|
|
}
|
|
else {
|
|
error.group1.noload_acu = 0;
|
|
8001b0e: 4a6a ldr r2, [pc, #424] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001b10: 7813 ldrb r3, [r2, #0]
|
|
8001b12: f36f 1304 bfc r3, #4, #1
|
|
8001b16: 7013 strb r3, [r2, #0]
|
|
}
|
|
|
|
if (update_ports.porta.epsc == 1 && current_measurements_adc_val.epsc == 0) {
|
|
8001b18: 4b65 ldr r3, [pc, #404] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001b1a: 781b ldrb r3, [r3, #0]
|
|
8001b1c: f003 0310 and.w r3, r3, #16
|
|
8001b20: b2db uxtb r3, r3
|
|
8001b22: 2b00 cmp r3, #0
|
|
8001b24: d009 beq.n 8001b3a <check_plausibility+0x102>
|
|
8001b26: 4b65 ldr r3, [pc, #404] @ (8001cbc <check_plausibility+0x284>)
|
|
8001b28: 891b ldrh r3, [r3, #8]
|
|
8001b2a: 2b00 cmp r3, #0
|
|
8001b2c: d105 bne.n 8001b3a <check_plausibility+0x102>
|
|
error.group1.noload_epsc = 1;
|
|
8001b2e: 4a62 ldr r2, [pc, #392] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001b30: 7813 ldrb r3, [r2, #0]
|
|
8001b32: f043 0320 orr.w r3, r3, #32
|
|
8001b36: 7013 strb r3, [r2, #0]
|
|
8001b38: e004 b.n 8001b44 <check_plausibility+0x10c>
|
|
}
|
|
else {
|
|
error.group1.noload_epsc = 0;
|
|
8001b3a: 4a5f ldr r2, [pc, #380] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001b3c: 7813 ldrb r3, [r2, #0]
|
|
8001b3e: f36f 1345 bfc r3, #5, #1
|
|
8001b42: 7013 strb r3, [r2, #0]
|
|
}
|
|
|
|
if (update_ports.porta.inverter == 1 && current_measurements_adc_val.inverter == 0) {
|
|
8001b44: 4b5a ldr r3, [pc, #360] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001b46: 781b ldrb r3, [r3, #0]
|
|
8001b48: f003 0320 and.w r3, r3, #32
|
|
8001b4c: b2db uxtb r3, r3
|
|
8001b4e: 2b00 cmp r3, #0
|
|
8001b50: d009 beq.n 8001b66 <check_plausibility+0x12e>
|
|
8001b52: 4b5a ldr r3, [pc, #360] @ (8001cbc <check_plausibility+0x284>)
|
|
8001b54: 895b ldrh r3, [r3, #10]
|
|
8001b56: 2b00 cmp r3, #0
|
|
8001b58: d105 bne.n 8001b66 <check_plausibility+0x12e>
|
|
error.group1.noload_inverter = 1;
|
|
8001b5a: 4a57 ldr r2, [pc, #348] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001b5c: 7813 ldrb r3, [r2, #0]
|
|
8001b5e: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8001b62: 7013 strb r3, [r2, #0]
|
|
8001b64: e004 b.n 8001b70 <check_plausibility+0x138>
|
|
}
|
|
else {
|
|
error.group1.noload_inverter = 0;
|
|
8001b66: 4a54 ldr r2, [pc, #336] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001b68: 7813 ldrb r3, [r2, #0]
|
|
8001b6a: f36f 1386 bfc r3, #6, #1
|
|
8001b6e: 7013 strb r3, [r2, #0]
|
|
}
|
|
|
|
if (update_ports.porta.lidar == 1 && current_measurements_adc_val.lidar == 0) {
|
|
8001b70: 4b4f ldr r3, [pc, #316] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001b72: 781b ldrb r3, [r3, #0]
|
|
8001b74: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8001b78: b2db uxtb r3, r3
|
|
8001b7a: 2b00 cmp r3, #0
|
|
8001b7c: d009 beq.n 8001b92 <check_plausibility+0x15a>
|
|
8001b7e: 4b4f ldr r3, [pc, #316] @ (8001cbc <check_plausibility+0x284>)
|
|
8001b80: 899b ldrh r3, [r3, #12]
|
|
8001b82: 2b00 cmp r3, #0
|
|
8001b84: d105 bne.n 8001b92 <check_plausibility+0x15a>
|
|
error.group1.noload_lidar = 1;
|
|
8001b86: 4a4c ldr r2, [pc, #304] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001b88: 7813 ldrb r3, [r2, #0]
|
|
8001b8a: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8001b8e: 7013 strb r3, [r2, #0]
|
|
8001b90: e004 b.n 8001b9c <check_plausibility+0x164>
|
|
}
|
|
else {
|
|
error.group1.noload_lidar = 0;
|
|
8001b92: 4a49 ldr r2, [pc, #292] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001b94: 7813 ldrb r3, [r2, #0]
|
|
8001b96: f36f 13c7 bfc r3, #7, #1
|
|
8001b9a: 7013 strb r3, [r2, #0]
|
|
}
|
|
|
|
if (update_ports.porta.misc == 1 && current_measurements_adc_val.misc == 0) {
|
|
8001b9c: 4b44 ldr r3, [pc, #272] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001b9e: 781b ldrb r3, [r3, #0]
|
|
8001ba0: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
8001ba4: b2db uxtb r3, r3
|
|
8001ba6: 2b00 cmp r3, #0
|
|
8001ba8: d009 beq.n 8001bbe <check_plausibility+0x186>
|
|
8001baa: 4b44 ldr r3, [pc, #272] @ (8001cbc <check_plausibility+0x284>)
|
|
8001bac: 89db ldrh r3, [r3, #14]
|
|
8001bae: 2b00 cmp r3, #0
|
|
8001bb0: d105 bne.n 8001bbe <check_plausibility+0x186>
|
|
error.group2.noload_misc = 1;
|
|
8001bb2: 4a41 ldr r2, [pc, #260] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001bb4: 7853 ldrb r3, [r2, #1]
|
|
8001bb6: f043 0301 orr.w r3, r3, #1
|
|
8001bba: 7053 strb r3, [r2, #1]
|
|
8001bbc: e004 b.n 8001bc8 <check_plausibility+0x190>
|
|
}
|
|
else {
|
|
error.group2.noload_misc = 0;
|
|
8001bbe: 4a3e ldr r2, [pc, #248] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001bc0: 7853 ldrb r3, [r2, #1]
|
|
8001bc2: f36f 0300 bfc r3, #0, #1
|
|
8001bc6: 7053 strb r3, [r2, #1]
|
|
}
|
|
|
|
if (update_ports.portb.alwayson == 1 && current_measurements_adc_val.alwayson == 0) {
|
|
8001bc8: 4b39 ldr r3, [pc, #228] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001bca: 785b ldrb r3, [r3, #1]
|
|
8001bcc: f003 0301 and.w r3, r3, #1
|
|
8001bd0: b2db uxtb r3, r3
|
|
8001bd2: 2b00 cmp r3, #0
|
|
8001bd4: d009 beq.n 8001bea <check_plausibility+0x1b2>
|
|
8001bd6: 4b39 ldr r3, [pc, #228] @ (8001cbc <check_plausibility+0x284>)
|
|
8001bd8: 8a1b ldrh r3, [r3, #16]
|
|
8001bda: 2b00 cmp r3, #0
|
|
8001bdc: d105 bne.n 8001bea <check_plausibility+0x1b2>
|
|
error.group2.noload_alwayson = 1;
|
|
8001bde: 4a36 ldr r2, [pc, #216] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001be0: 7853 ldrb r3, [r2, #1]
|
|
8001be2: f043 0302 orr.w r3, r3, #2
|
|
8001be6: 7053 strb r3, [r2, #1]
|
|
8001be8: e004 b.n 8001bf4 <check_plausibility+0x1bc>
|
|
}
|
|
else {
|
|
error.group2.noload_alwayson = 0;
|
|
8001bea: 4a33 ldr r2, [pc, #204] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001bec: 7853 ldrb r3, [r2, #1]
|
|
8001bee: f36f 0341 bfc r3, #1, #1
|
|
8001bf2: 7053 strb r3, [r2, #1]
|
|
}
|
|
|
|
if (update_ports.portb.sdc == 1 && current_measurements_adc_val.sdc == 0) {
|
|
8001bf4: 4b2e ldr r3, [pc, #184] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001bf6: 785b ldrb r3, [r3, #1]
|
|
8001bf8: f003 0302 and.w r3, r3, #2
|
|
8001bfc: b2db uxtb r3, r3
|
|
8001bfe: 2b00 cmp r3, #0
|
|
8001c00: d009 beq.n 8001c16 <check_plausibility+0x1de>
|
|
8001c02: 4b2e ldr r3, [pc, #184] @ (8001cbc <check_plausibility+0x284>)
|
|
8001c04: 8a5b ldrh r3, [r3, #18]
|
|
8001c06: 2b00 cmp r3, #0
|
|
8001c08: d105 bne.n 8001c16 <check_plausibility+0x1de>
|
|
error.group2.noload_sdc = 1;
|
|
8001c0a: 4a2b ldr r2, [pc, #172] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001c0c: 7853 ldrb r3, [r2, #1]
|
|
8001c0e: f043 0304 orr.w r3, r3, #4
|
|
8001c12: 7053 strb r3, [r2, #1]
|
|
8001c14: e004 b.n 8001c20 <check_plausibility+0x1e8>
|
|
}
|
|
else {
|
|
error.group2.noload_sdc = 0;
|
|
8001c16: 4a28 ldr r2, [pc, #160] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001c18: 7853 ldrb r3, [r2, #1]
|
|
8001c1a: f36f 0382 bfc r3, #2, #1
|
|
8001c1e: 7053 strb r3, [r2, #1]
|
|
}
|
|
|
|
if (update_ports.portb.ebs1 == 1 && current_measurements_adc_val.ebs1 == 0) {
|
|
8001c20: 4b23 ldr r3, [pc, #140] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001c22: 785b ldrb r3, [r3, #1]
|
|
8001c24: f003 0304 and.w r3, r3, #4
|
|
8001c28: b2db uxtb r3, r3
|
|
8001c2a: 2b00 cmp r3, #0
|
|
8001c2c: d009 beq.n 8001c42 <check_plausibility+0x20a>
|
|
8001c2e: 4b23 ldr r3, [pc, #140] @ (8001cbc <check_plausibility+0x284>)
|
|
8001c30: 8a9b ldrh r3, [r3, #20]
|
|
8001c32: 2b00 cmp r3, #0
|
|
8001c34: d105 bne.n 8001c42 <check_plausibility+0x20a>
|
|
error.group2.noload_ebs1 = 1;
|
|
8001c36: 4a20 ldr r2, [pc, #128] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001c38: 7853 ldrb r3, [r2, #1]
|
|
8001c3a: f043 0308 orr.w r3, r3, #8
|
|
8001c3e: 7053 strb r3, [r2, #1]
|
|
8001c40: e004 b.n 8001c4c <check_plausibility+0x214>
|
|
}
|
|
else {
|
|
error.group2.noload_ebs1 = 0;
|
|
8001c42: 4a1d ldr r2, [pc, #116] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001c44: 7853 ldrb r3, [r2, #1]
|
|
8001c46: f36f 03c3 bfc r3, #3, #1
|
|
8001c4a: 7053 strb r3, [r2, #1]
|
|
}
|
|
|
|
if (update_ports.portb.ebs2 == 1 && current_measurements_adc_val.ebs2 == 0) {
|
|
8001c4c: 4b18 ldr r3, [pc, #96] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001c4e: 785b ldrb r3, [r3, #1]
|
|
8001c50: f003 0308 and.w r3, r3, #8
|
|
8001c54: b2db uxtb r3, r3
|
|
8001c56: 2b00 cmp r3, #0
|
|
8001c58: d009 beq.n 8001c6e <check_plausibility+0x236>
|
|
8001c5a: 4b18 ldr r3, [pc, #96] @ (8001cbc <check_plausibility+0x284>)
|
|
8001c5c: 8adb ldrh r3, [r3, #22]
|
|
8001c5e: 2b00 cmp r3, #0
|
|
8001c60: d105 bne.n 8001c6e <check_plausibility+0x236>
|
|
error.group2.noload_ebs2 = 1;
|
|
8001c62: 4a15 ldr r2, [pc, #84] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001c64: 7853 ldrb r3, [r2, #1]
|
|
8001c66: f043 0310 orr.w r3, r3, #16
|
|
8001c6a: 7053 strb r3, [r2, #1]
|
|
8001c6c: e004 b.n 8001c78 <check_plausibility+0x240>
|
|
}
|
|
else {
|
|
error.group2.noload_ebs2 = 0;
|
|
8001c6e: 4a12 ldr r2, [pc, #72] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001c70: 7853 ldrb r3, [r2, #1]
|
|
8001c72: f36f 1304 bfc r3, #4, #1
|
|
8001c76: 7053 strb r3, [r2, #1]
|
|
}
|
|
|
|
if (update_ports.portb.ebs3 == 1 && current_measurements_adc_val.ebs3 == 0) {
|
|
8001c78: 4b0d ldr r3, [pc, #52] @ (8001cb0 <check_plausibility+0x278>)
|
|
8001c7a: 785b ldrb r3, [r3, #1]
|
|
8001c7c: f003 0310 and.w r3, r3, #16
|
|
8001c80: b2db uxtb r3, r3
|
|
8001c82: 2b00 cmp r3, #0
|
|
8001c84: d009 beq.n 8001c9a <check_plausibility+0x262>
|
|
8001c86: 4b0d ldr r3, [pc, #52] @ (8001cbc <check_plausibility+0x284>)
|
|
8001c88: 8b1b ldrh r3, [r3, #24]
|
|
8001c8a: 2b00 cmp r3, #0
|
|
8001c8c: d105 bne.n 8001c9a <check_plausibility+0x262>
|
|
error.group2.noload_ebs3 = 1;
|
|
8001c8e: 4a0a ldr r2, [pc, #40] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001c90: 7853 ldrb r3, [r2, #1]
|
|
8001c92: f043 0320 orr.w r3, r3, #32
|
|
8001c96: 7053 strb r3, [r2, #1]
|
|
8001c98: e005 b.n 8001ca6 <check_plausibility+0x26e>
|
|
}
|
|
else {
|
|
error.group2.noload_ebs3 = 0;
|
|
8001c9a: 4a07 ldr r2, [pc, #28] @ (8001cb8 <check_plausibility+0x280>)
|
|
8001c9c: 7853 ldrb r3, [r2, #1]
|
|
8001c9e: f36f 1345 bfc r3, #5, #1
|
|
8001ca2: 7053 strb r3, [r2, #1]
|
|
}
|
|
}
|
|
8001ca4: bf00 nop
|
|
8001ca6: bf00 nop
|
|
8001ca8: 46bd mov sp, r7
|
|
8001caa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001cae: 4770 bx lr
|
|
8001cb0: 200002e8 .word 0x200002e8
|
|
8001cb4: 200002f0 .word 0x200002f0
|
|
8001cb8: 200002f4 .word 0x200002f4
|
|
8001cbc: 20000098 .word 0x20000098
|
|
|
|
08001cc0 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8001cc0: b480 push {r7}
|
|
8001cc2: b083 sub sp, #12
|
|
8001cc4: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8001cc6: 4b0f ldr r3, [pc, #60] @ (8001d04 <HAL_MspInit+0x44>)
|
|
8001cc8: 699b ldr r3, [r3, #24]
|
|
8001cca: 4a0e ldr r2, [pc, #56] @ (8001d04 <HAL_MspInit+0x44>)
|
|
8001ccc: f043 0301 orr.w r3, r3, #1
|
|
8001cd0: 6193 str r3, [r2, #24]
|
|
8001cd2: 4b0c ldr r3, [pc, #48] @ (8001d04 <HAL_MspInit+0x44>)
|
|
8001cd4: 699b ldr r3, [r3, #24]
|
|
8001cd6: f003 0301 and.w r3, r3, #1
|
|
8001cda: 607b str r3, [r7, #4]
|
|
8001cdc: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8001cde: 4b09 ldr r3, [pc, #36] @ (8001d04 <HAL_MspInit+0x44>)
|
|
8001ce0: 69db ldr r3, [r3, #28]
|
|
8001ce2: 4a08 ldr r2, [pc, #32] @ (8001d04 <HAL_MspInit+0x44>)
|
|
8001ce4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8001ce8: 61d3 str r3, [r2, #28]
|
|
8001cea: 4b06 ldr r3, [pc, #24] @ (8001d04 <HAL_MspInit+0x44>)
|
|
8001cec: 69db ldr r3, [r3, #28]
|
|
8001cee: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001cf2: 603b str r3, [r7, #0]
|
|
8001cf4: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8001cf6: bf00 nop
|
|
8001cf8: 370c adds r7, #12
|
|
8001cfa: 46bd mov sp, r7
|
|
8001cfc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001d00: 4770 bx lr
|
|
8001d02: bf00 nop
|
|
8001d04: 40021000 .word 0x40021000
|
|
|
|
08001d08 <HAL_ADC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hadc: ADC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8001d08: b580 push {r7, lr}
|
|
8001d0a: b08e sub sp, #56 @ 0x38
|
|
8001d0c: af00 add r7, sp, #0
|
|
8001d0e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001d10: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8001d14: 2200 movs r2, #0
|
|
8001d16: 601a str r2, [r3, #0]
|
|
8001d18: 605a str r2, [r3, #4]
|
|
8001d1a: 609a str r2, [r3, #8]
|
|
8001d1c: 60da str r2, [r3, #12]
|
|
8001d1e: 611a str r2, [r3, #16]
|
|
if(hadc->Instance==ADC1)
|
|
8001d20: 687b ldr r3, [r7, #4]
|
|
8001d22: 681b ldr r3, [r3, #0]
|
|
8001d24: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8001d28: f040 808f bne.w 8001e4a <HAL_ADC_MspInit+0x142>
|
|
{
|
|
/* USER CODE BEGIN ADC1_MspInit 0 */
|
|
|
|
/* USER CODE END ADC1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
HAL_RCC_ADC12_CLK_ENABLED++;
|
|
8001d2c: 4b86 ldr r3, [pc, #536] @ (8001f48 <HAL_ADC_MspInit+0x240>)
|
|
8001d2e: 681b ldr r3, [r3, #0]
|
|
8001d30: 3301 adds r3, #1
|
|
8001d32: 4a85 ldr r2, [pc, #532] @ (8001f48 <HAL_ADC_MspInit+0x240>)
|
|
8001d34: 6013 str r3, [r2, #0]
|
|
if(HAL_RCC_ADC12_CLK_ENABLED==1){
|
|
8001d36: 4b84 ldr r3, [pc, #528] @ (8001f48 <HAL_ADC_MspInit+0x240>)
|
|
8001d38: 681b ldr r3, [r3, #0]
|
|
8001d3a: 2b01 cmp r3, #1
|
|
8001d3c: d10b bne.n 8001d56 <HAL_ADC_MspInit+0x4e>
|
|
__HAL_RCC_ADC12_CLK_ENABLE();
|
|
8001d3e: 4b83 ldr r3, [pc, #524] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d40: 695b ldr r3, [r3, #20]
|
|
8001d42: 4a82 ldr r2, [pc, #520] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d44: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8001d48: 6153 str r3, [r2, #20]
|
|
8001d4a: 4b80 ldr r3, [pc, #512] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d4c: 695b ldr r3, [r3, #20]
|
|
8001d4e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001d52: 623b str r3, [r7, #32]
|
|
8001d54: 6a3b ldr r3, [r7, #32]
|
|
}
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8001d56: 4b7d ldr r3, [pc, #500] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d58: 695b ldr r3, [r3, #20]
|
|
8001d5a: 4a7c ldr r2, [pc, #496] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d5c: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8001d60: 6153 str r3, [r2, #20]
|
|
8001d62: 4b7a ldr r3, [pc, #488] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d64: 695b ldr r3, [r3, #20]
|
|
8001d66: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8001d6a: 61fb str r3, [r7, #28]
|
|
8001d6c: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001d6e: 4b77 ldr r3, [pc, #476] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d70: 695b ldr r3, [r3, #20]
|
|
8001d72: 4a76 ldr r2, [pc, #472] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d74: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001d78: 6153 str r3, [r2, #20]
|
|
8001d7a: 4b74 ldr r3, [pc, #464] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d7c: 695b ldr r3, [r3, #20]
|
|
8001d7e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001d82: 61bb str r3, [r7, #24]
|
|
8001d84: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8001d86: 4b71 ldr r3, [pc, #452] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d88: 695b ldr r3, [r3, #20]
|
|
8001d8a: 4a70 ldr r2, [pc, #448] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d8c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8001d90: 6153 str r3, [r2, #20]
|
|
8001d92: 4b6e ldr r3, [pc, #440] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001d94: 695b ldr r3, [r3, #20]
|
|
8001d96: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8001d9a: 617b str r3, [r7, #20]
|
|
8001d9c: 697b ldr r3, [r7, #20]
|
|
PA1 ------> ADC1_IN2
|
|
PA2 ------> ADC1_IN3
|
|
PA3 ------> ADC1_IN4
|
|
PF4 ------> ADC1_IN5
|
|
*/
|
|
GPIO_InitStruct.Pin = LVMS_Vsense_Pin|IS10_Pin|IS6_Pin;
|
|
8001d9e: 2307 movs r3, #7
|
|
8001da0: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8001da2: 2303 movs r3, #3
|
|
8001da4: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001da6: 2300 movs r3, #0
|
|
8001da8: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8001daa: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8001dae: 4619 mov r1, r3
|
|
8001db0: 4867 ldr r0, [pc, #412] @ (8001f50 <HAL_ADC_MspInit+0x248>)
|
|
8001db2: f002 fd43 bl 800483c <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = ASMS_Vsense_Pin|IS1_Pin|IS2_Pin|IS9_Pin;
|
|
8001db6: 230f movs r3, #15
|
|
8001db8: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8001dba: 2303 movs r3, #3
|
|
8001dbc: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001dbe: 2300 movs r3, #0
|
|
8001dc0: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001dc2: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8001dc6: 4619 mov r1, r3
|
|
8001dc8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001dcc: f002 fd36 bl 800483c <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = IS11_Pin;
|
|
8001dd0: 2310 movs r3, #16
|
|
8001dd2: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8001dd4: 2303 movs r3, #3
|
|
8001dd6: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001dd8: 2300 movs r3, #0
|
|
8001dda: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(IS11_GPIO_Port, &GPIO_InitStruct);
|
|
8001ddc: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8001de0: 4619 mov r1, r3
|
|
8001de2: 485c ldr r0, [pc, #368] @ (8001f54 <HAL_ADC_MspInit+0x24c>)
|
|
8001de4: f002 fd2a bl 800483c <HAL_GPIO_Init>
|
|
|
|
/* ADC1 DMA Init */
|
|
/* ADC1 Init */
|
|
hdma_adc1.Instance = DMA1_Channel1;
|
|
8001de8: 4b5b ldr r3, [pc, #364] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001dea: 4a5c ldr r2, [pc, #368] @ (8001f5c <HAL_ADC_MspInit+0x254>)
|
|
8001dec: 601a str r2, [r3, #0]
|
|
hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8001dee: 4b5a ldr r3, [pc, #360] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001df0: 2200 movs r2, #0
|
|
8001df2: 605a str r2, [r3, #4]
|
|
hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001df4: 4b58 ldr r3, [pc, #352] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001df6: 2200 movs r2, #0
|
|
8001df8: 609a str r2, [r3, #8]
|
|
hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001dfa: 4b57 ldr r3, [pc, #348] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001dfc: 2280 movs r2, #128 @ 0x80
|
|
8001dfe: 60da str r2, [r3, #12]
|
|
hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
|
|
8001e00: 4b55 ldr r3, [pc, #340] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001e02: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8001e06: 611a str r2, [r3, #16]
|
|
hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
|
|
8001e08: 4b53 ldr r3, [pc, #332] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001e0a: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001e0e: 615a str r2, [r3, #20]
|
|
hdma_adc1.Init.Mode = DMA_CIRCULAR;
|
|
8001e10: 4b51 ldr r3, [pc, #324] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001e12: 2220 movs r2, #32
|
|
8001e14: 619a str r2, [r3, #24]
|
|
hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001e16: 4b50 ldr r3, [pc, #320] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001e18: 2200 movs r2, #0
|
|
8001e1a: 61da str r2, [r3, #28]
|
|
if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
|
|
8001e1c: 484e ldr r0, [pc, #312] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001e1e: f002 fb5a bl 80044d6 <HAL_DMA_Init>
|
|
8001e22: 4603 mov r3, r0
|
|
8001e24: 2b00 cmp r3, #0
|
|
8001e26: d001 beq.n 8001e2c <HAL_ADC_MspInit+0x124>
|
|
{
|
|
Error_Handler();
|
|
8001e28: f7ff fe00 bl 8001a2c <Error_Handler>
|
|
}
|
|
|
|
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
|
|
8001e2c: 687b ldr r3, [r7, #4]
|
|
8001e2e: 4a4a ldr r2, [pc, #296] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001e30: 639a str r2, [r3, #56] @ 0x38
|
|
8001e32: 4a49 ldr r2, [pc, #292] @ (8001f58 <HAL_ADC_MspInit+0x250>)
|
|
8001e34: 687b ldr r3, [r7, #4]
|
|
8001e36: 6253 str r3, [r2, #36] @ 0x24
|
|
|
|
/* ADC1 interrupt Init */
|
|
HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
|
|
8001e38: 2200 movs r2, #0
|
|
8001e3a: 2100 movs r1, #0
|
|
8001e3c: 2012 movs r0, #18
|
|
8001e3e: f002 fb14 bl 800446a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
|
|
8001e42: 2012 movs r0, #18
|
|
8001e44: f002 fb2d bl 80044a2 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN ADC2_MspInit 1 */
|
|
|
|
/* USER CODE END ADC2_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8001e48: e07a b.n 8001f40 <HAL_ADC_MspInit+0x238>
|
|
else if(hadc->Instance==ADC2)
|
|
8001e4a: 687b ldr r3, [r7, #4]
|
|
8001e4c: 681b ldr r3, [r3, #0]
|
|
8001e4e: 4a44 ldr r2, [pc, #272] @ (8001f60 <HAL_ADC_MspInit+0x258>)
|
|
8001e50: 4293 cmp r3, r2
|
|
8001e52: d175 bne.n 8001f40 <HAL_ADC_MspInit+0x238>
|
|
HAL_RCC_ADC12_CLK_ENABLED++;
|
|
8001e54: 4b3c ldr r3, [pc, #240] @ (8001f48 <HAL_ADC_MspInit+0x240>)
|
|
8001e56: 681b ldr r3, [r3, #0]
|
|
8001e58: 3301 adds r3, #1
|
|
8001e5a: 4a3b ldr r2, [pc, #236] @ (8001f48 <HAL_ADC_MspInit+0x240>)
|
|
8001e5c: 6013 str r3, [r2, #0]
|
|
if(HAL_RCC_ADC12_CLK_ENABLED==1){
|
|
8001e5e: 4b3a ldr r3, [pc, #232] @ (8001f48 <HAL_ADC_MspInit+0x240>)
|
|
8001e60: 681b ldr r3, [r3, #0]
|
|
8001e62: 2b01 cmp r3, #1
|
|
8001e64: d10b bne.n 8001e7e <HAL_ADC_MspInit+0x176>
|
|
__HAL_RCC_ADC12_CLK_ENABLE();
|
|
8001e66: 4b39 ldr r3, [pc, #228] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001e68: 695b ldr r3, [r3, #20]
|
|
8001e6a: 4a38 ldr r2, [pc, #224] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001e6c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8001e70: 6153 str r3, [r2, #20]
|
|
8001e72: 4b36 ldr r3, [pc, #216] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001e74: 695b ldr r3, [r3, #20]
|
|
8001e76: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001e7a: 613b str r3, [r7, #16]
|
|
8001e7c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8001e7e: 4b33 ldr r3, [pc, #204] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001e80: 695b ldr r3, [r3, #20]
|
|
8001e82: 4a32 ldr r2, [pc, #200] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001e84: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
8001e88: 6153 str r3, [r2, #20]
|
|
8001e8a: 4b30 ldr r3, [pc, #192] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001e8c: 695b ldr r3, [r3, #20]
|
|
8001e8e: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8001e92: 60fb str r3, [r7, #12]
|
|
8001e94: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001e96: 4b2d ldr r3, [pc, #180] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001e98: 695b ldr r3, [r3, #20]
|
|
8001e9a: 4a2c ldr r2, [pc, #176] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001e9c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001ea0: 6153 str r3, [r2, #20]
|
|
8001ea2: 4b2a ldr r3, [pc, #168] @ (8001f4c <HAL_ADC_MspInit+0x244>)
|
|
8001ea4: 695b ldr r3, [r3, #20]
|
|
8001ea6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001eaa: 60bb str r3, [r7, #8]
|
|
8001eac: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = IS7_Pin|PC_Read_Pin;
|
|
8001eae: 2318 movs r3, #24
|
|
8001eb0: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8001eb2: 2303 movs r3, #3
|
|
8001eb4: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001eb6: 2300 movs r3, #0
|
|
8001eb8: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8001eba: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8001ebe: 4619 mov r1, r3
|
|
8001ec0: 4823 ldr r0, [pc, #140] @ (8001f50 <HAL_ADC_MspInit+0x248>)
|
|
8001ec2: f002 fcbb bl 800483c <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = IS3_Pin|IS8_Pin|IS4_Pin|IS5_Pin;
|
|
8001ec6: 23f0 movs r3, #240 @ 0xf0
|
|
8001ec8: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8001eca: 2303 movs r3, #3
|
|
8001ecc: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001ece: 2300 movs r3, #0
|
|
8001ed0: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001ed2: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8001ed6: 4619 mov r1, r3
|
|
8001ed8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001edc: f002 fcae bl 800483c <HAL_GPIO_Init>
|
|
hdma_adc2.Instance = DMA2_Channel1;
|
|
8001ee0: 4b20 ldr r3, [pc, #128] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001ee2: 4a21 ldr r2, [pc, #132] @ (8001f68 <HAL_ADC_MspInit+0x260>)
|
|
8001ee4: 601a str r2, [r3, #0]
|
|
hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8001ee6: 4b1f ldr r3, [pc, #124] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001ee8: 2200 movs r2, #0
|
|
8001eea: 605a str r2, [r3, #4]
|
|
hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8001eec: 4b1d ldr r3, [pc, #116] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001eee: 2200 movs r2, #0
|
|
8001ef0: 609a str r2, [r3, #8]
|
|
hdma_adc2.Init.MemInc = DMA_MINC_ENABLE;
|
|
8001ef2: 4b1c ldr r3, [pc, #112] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001ef4: 2280 movs r2, #128 @ 0x80
|
|
8001ef6: 60da str r2, [r3, #12]
|
|
hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
|
|
8001ef8: 4b1a ldr r3, [pc, #104] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001efa: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8001efe: 611a str r2, [r3, #16]
|
|
hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
|
|
8001f00: 4b18 ldr r3, [pc, #96] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001f02: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8001f06: 615a str r2, [r3, #20]
|
|
hdma_adc2.Init.Mode = DMA_CIRCULAR;
|
|
8001f08: 4b16 ldr r3, [pc, #88] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001f0a: 2220 movs r2, #32
|
|
8001f0c: 619a str r2, [r3, #24]
|
|
hdma_adc2.Init.Priority = DMA_PRIORITY_LOW;
|
|
8001f0e: 4b15 ldr r3, [pc, #84] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001f10: 2200 movs r2, #0
|
|
8001f12: 61da str r2, [r3, #28]
|
|
if (HAL_DMA_Init(&hdma_adc2) != HAL_OK)
|
|
8001f14: 4813 ldr r0, [pc, #76] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001f16: f002 fade bl 80044d6 <HAL_DMA_Init>
|
|
8001f1a: 4603 mov r3, r0
|
|
8001f1c: 2b00 cmp r3, #0
|
|
8001f1e: d001 beq.n 8001f24 <HAL_ADC_MspInit+0x21c>
|
|
Error_Handler();
|
|
8001f20: f7ff fd84 bl 8001a2c <Error_Handler>
|
|
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2);
|
|
8001f24: 687b ldr r3, [r7, #4]
|
|
8001f26: 4a0f ldr r2, [pc, #60] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001f28: 639a str r2, [r3, #56] @ 0x38
|
|
8001f2a: 4a0e ldr r2, [pc, #56] @ (8001f64 <HAL_ADC_MspInit+0x25c>)
|
|
8001f2c: 687b ldr r3, [r7, #4]
|
|
8001f2e: 6253 str r3, [r2, #36] @ 0x24
|
|
HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
|
|
8001f30: 2200 movs r2, #0
|
|
8001f32: 2100 movs r1, #0
|
|
8001f34: 2012 movs r0, #18
|
|
8001f36: f002 fa98 bl 800446a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
|
|
8001f3a: 2012 movs r0, #18
|
|
8001f3c: f002 fab1 bl 80044a2 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8001f40: bf00 nop
|
|
8001f42: 3738 adds r7, #56 @ 0x38
|
|
8001f44: 46bd mov sp, r7
|
|
8001f46: bd80 pop {r7, pc}
|
|
8001f48: 200002f8 .word 0x200002f8
|
|
8001f4c: 40021000 .word 0x40021000
|
|
8001f50: 48000800 .word 0x48000800
|
|
8001f54: 48001400 .word 0x48001400
|
|
8001f58: 20000164 .word 0x20000164
|
|
8001f5c: 40020008 .word 0x40020008
|
|
8001f60: 50000100 .word 0x50000100
|
|
8001f64: 200001a8 .word 0x200001a8
|
|
8001f68: 40020408 .word 0x40020408
|
|
|
|
08001f6c <HAL_CAN_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hcan: CAN handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
|
|
{
|
|
8001f6c: b580 push {r7, lr}
|
|
8001f6e: b08a sub sp, #40 @ 0x28
|
|
8001f70: af00 add r7, sp, #0
|
|
8001f72: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001f74: f107 0314 add.w r3, r7, #20
|
|
8001f78: 2200 movs r2, #0
|
|
8001f7a: 601a str r2, [r3, #0]
|
|
8001f7c: 605a str r2, [r3, #4]
|
|
8001f7e: 609a str r2, [r3, #8]
|
|
8001f80: 60da str r2, [r3, #12]
|
|
8001f82: 611a str r2, [r3, #16]
|
|
if(hcan->Instance==CAN)
|
|
8001f84: 687b ldr r3, [r7, #4]
|
|
8001f86: 681b ldr r3, [r3, #0]
|
|
8001f88: 4a20 ldr r2, [pc, #128] @ (800200c <HAL_CAN_MspInit+0xa0>)
|
|
8001f8a: 4293 cmp r3, r2
|
|
8001f8c: d139 bne.n 8002002 <HAL_CAN_MspInit+0x96>
|
|
{
|
|
/* USER CODE BEGIN CAN_MspInit 0 */
|
|
|
|
/* USER CODE END CAN_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_CAN1_CLK_ENABLE();
|
|
8001f8e: 4b20 ldr r3, [pc, #128] @ (8002010 <HAL_CAN_MspInit+0xa4>)
|
|
8001f90: 69db ldr r3, [r3, #28]
|
|
8001f92: 4a1f ldr r2, [pc, #124] @ (8002010 <HAL_CAN_MspInit+0xa4>)
|
|
8001f94: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
8001f98: 61d3 str r3, [r2, #28]
|
|
8001f9a: 4b1d ldr r3, [pc, #116] @ (8002010 <HAL_CAN_MspInit+0xa4>)
|
|
8001f9c: 69db ldr r3, [r3, #28]
|
|
8001f9e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8001fa2: 613b str r3, [r7, #16]
|
|
8001fa4: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001fa6: 4b1a ldr r3, [pc, #104] @ (8002010 <HAL_CAN_MspInit+0xa4>)
|
|
8001fa8: 695b ldr r3, [r3, #20]
|
|
8001faa: 4a19 ldr r2, [pc, #100] @ (8002010 <HAL_CAN_MspInit+0xa4>)
|
|
8001fac: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001fb0: 6153 str r3, [r2, #20]
|
|
8001fb2: 4b17 ldr r3, [pc, #92] @ (8002010 <HAL_CAN_MspInit+0xa4>)
|
|
8001fb4: 695b ldr r3, [r3, #20]
|
|
8001fb6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001fba: 60fb str r3, [r7, #12]
|
|
8001fbc: 68fb ldr r3, [r7, #12]
|
|
/**CAN GPIO Configuration
|
|
PA11 ------> CAN_RX
|
|
PA12 ------> CAN_TX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
|
8001fbe: f44f 53c0 mov.w r3, #6144 @ 0x1800
|
|
8001fc2: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001fc4: 2302 movs r3, #2
|
|
8001fc6: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001fc8: 2300 movs r3, #0
|
|
8001fca: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
8001fcc: 2303 movs r3, #3
|
|
8001fce: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF9_CAN;
|
|
8001fd0: 2309 movs r3, #9
|
|
8001fd2: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001fd4: f107 0314 add.w r3, r7, #20
|
|
8001fd8: 4619 mov r1, r3
|
|
8001fda: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001fde: f002 fc2d bl 800483c <HAL_GPIO_Init>
|
|
|
|
/* CAN interrupt Init */
|
|
HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0);
|
|
8001fe2: 2200 movs r2, #0
|
|
8001fe4: 2100 movs r1, #0
|
|
8001fe6: 2014 movs r0, #20
|
|
8001fe8: f002 fa3f bl 800446a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
|
|
8001fec: 2014 movs r0, #20
|
|
8001fee: f002 fa58 bl 80044a2 <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
|
|
8001ff2: 2200 movs r2, #0
|
|
8001ff4: 2100 movs r1, #0
|
|
8001ff6: 2015 movs r0, #21
|
|
8001ff8: f002 fa37 bl 800446a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
|
|
8001ffc: 2015 movs r0, #21
|
|
8001ffe: f002 fa50 bl 80044a2 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END CAN_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8002002: bf00 nop
|
|
8002004: 3728 adds r7, #40 @ 0x28
|
|
8002006: 46bd mov sp, r7
|
|
8002008: bd80 pop {r7, pc}
|
|
800200a: bf00 nop
|
|
800200c: 40006400 .word 0x40006400
|
|
8002010: 40021000 .word 0x40021000
|
|
|
|
08002014 <HAL_TIM_Base_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_base: TIM_Base handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
{
|
|
8002014: b580 push {r7, lr}
|
|
8002016: b084 sub sp, #16
|
|
8002018: af00 add r7, sp, #0
|
|
800201a: 6078 str r0, [r7, #4]
|
|
if(htim_base->Instance==TIM6)
|
|
800201c: 687b ldr r3, [r7, #4]
|
|
800201e: 681b ldr r3, [r3, #0]
|
|
8002020: 4a0d ldr r2, [pc, #52] @ (8002058 <HAL_TIM_Base_MspInit+0x44>)
|
|
8002022: 4293 cmp r3, r2
|
|
8002024: d113 bne.n 800204e <HAL_TIM_Base_MspInit+0x3a>
|
|
{
|
|
/* USER CODE BEGIN TIM6_MspInit 0 */
|
|
|
|
/* USER CODE END TIM6_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM6_CLK_ENABLE();
|
|
8002026: 4b0d ldr r3, [pc, #52] @ (800205c <HAL_TIM_Base_MspInit+0x48>)
|
|
8002028: 69db ldr r3, [r3, #28]
|
|
800202a: 4a0c ldr r2, [pc, #48] @ (800205c <HAL_TIM_Base_MspInit+0x48>)
|
|
800202c: f043 0310 orr.w r3, r3, #16
|
|
8002030: 61d3 str r3, [r2, #28]
|
|
8002032: 4b0a ldr r3, [pc, #40] @ (800205c <HAL_TIM_Base_MspInit+0x48>)
|
|
8002034: 69db ldr r3, [r3, #28]
|
|
8002036: f003 0310 and.w r3, r3, #16
|
|
800203a: 60fb str r3, [r7, #12]
|
|
800203c: 68fb ldr r3, [r7, #12]
|
|
/* TIM6 interrupt Init */
|
|
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
|
|
800203e: 2200 movs r2, #0
|
|
8002040: 2100 movs r1, #0
|
|
8002042: 2036 movs r0, #54 @ 0x36
|
|
8002044: f002 fa11 bl 800446a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
|
|
8002048: 2036 movs r0, #54 @ 0x36
|
|
800204a: f002 fa2a bl 80044a2 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END TIM6_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
800204e: bf00 nop
|
|
8002050: 3710 adds r7, #16
|
|
8002052: 46bd mov sp, r7
|
|
8002054: bd80 pop {r7, pc}
|
|
8002056: bf00 nop
|
|
8002058: 40001000 .word 0x40001000
|
|
800205c: 40021000 .word 0x40021000
|
|
|
|
08002060 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8002060: b580 push {r7, lr}
|
|
8002062: b08a sub sp, #40 @ 0x28
|
|
8002064: af00 add r7, sp, #0
|
|
8002066: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002068: f107 0314 add.w r3, r7, #20
|
|
800206c: 2200 movs r2, #0
|
|
800206e: 601a str r2, [r3, #0]
|
|
8002070: 605a str r2, [r3, #4]
|
|
8002072: 609a str r2, [r3, #8]
|
|
8002074: 60da str r2, [r3, #12]
|
|
8002076: 611a str r2, [r3, #16]
|
|
if(huart->Instance==UART4)
|
|
8002078: 687b ldr r3, [r7, #4]
|
|
800207a: 681b ldr r3, [r3, #0]
|
|
800207c: 4a17 ldr r2, [pc, #92] @ (80020dc <HAL_UART_MspInit+0x7c>)
|
|
800207e: 4293 cmp r3, r2
|
|
8002080: d128 bne.n 80020d4 <HAL_UART_MspInit+0x74>
|
|
{
|
|
/* USER CODE BEGIN UART4_MspInit 0 */
|
|
|
|
/* USER CODE END UART4_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_UART4_CLK_ENABLE();
|
|
8002082: 4b17 ldr r3, [pc, #92] @ (80020e0 <HAL_UART_MspInit+0x80>)
|
|
8002084: 69db ldr r3, [r3, #28]
|
|
8002086: 4a16 ldr r2, [pc, #88] @ (80020e0 <HAL_UART_MspInit+0x80>)
|
|
8002088: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
800208c: 61d3 str r3, [r2, #28]
|
|
800208e: 4b14 ldr r3, [pc, #80] @ (80020e0 <HAL_UART_MspInit+0x80>)
|
|
8002090: 69db ldr r3, [r3, #28]
|
|
8002092: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8002096: 613b str r3, [r7, #16]
|
|
8002098: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800209a: 4b11 ldr r3, [pc, #68] @ (80020e0 <HAL_UART_MspInit+0x80>)
|
|
800209c: 695b ldr r3, [r3, #20]
|
|
800209e: 4a10 ldr r2, [pc, #64] @ (80020e0 <HAL_UART_MspInit+0x80>)
|
|
80020a0: f443 2300 orr.w r3, r3, #524288 @ 0x80000
|
|
80020a4: 6153 str r3, [r2, #20]
|
|
80020a6: 4b0e ldr r3, [pc, #56] @ (80020e0 <HAL_UART_MspInit+0x80>)
|
|
80020a8: 695b ldr r3, [r3, #20]
|
|
80020aa: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80020ae: 60fb str r3, [r7, #12]
|
|
80020b0: 68fb ldr r3, [r7, #12]
|
|
/**UART4 GPIO Configuration
|
|
PC10 ------> UART4_TX
|
|
PC11 ------> UART4_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
|
|
80020b2: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
80020b6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80020b8: 2302 movs r3, #2
|
|
80020ba: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80020bc: 2300 movs r3, #0
|
|
80020be: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
80020c0: 2303 movs r3, #3
|
|
80020c2: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_UART4;
|
|
80020c4: 2305 movs r3, #5
|
|
80020c6: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80020c8: f107 0314 add.w r3, r7, #20
|
|
80020cc: 4619 mov r1, r3
|
|
80020ce: 4805 ldr r0, [pc, #20] @ (80020e4 <HAL_UART_MspInit+0x84>)
|
|
80020d0: f002 fbb4 bl 800483c <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END UART4_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80020d4: bf00 nop
|
|
80020d6: 3728 adds r7, #40 @ 0x28
|
|
80020d8: 46bd mov sp, r7
|
|
80020da: bd80 pop {r7, pc}
|
|
80020dc: 40004c00 .word 0x40004c00
|
|
80020e0: 40021000 .word 0x40021000
|
|
80020e4: 48000800 .word 0x48000800
|
|
|
|
080020e8 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80020e8: b480 push {r7}
|
|
80020ea: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80020ec: bf00 nop
|
|
80020ee: e7fd b.n 80020ec <NMI_Handler+0x4>
|
|
|
|
080020f0 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80020f0: b480 push {r7}
|
|
80020f2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
80020f4: bf00 nop
|
|
80020f6: e7fd b.n 80020f4 <HardFault_Handler+0x4>
|
|
|
|
080020f8 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
80020f8: b480 push {r7}
|
|
80020fa: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
80020fc: bf00 nop
|
|
80020fe: e7fd b.n 80020fc <MemManage_Handler+0x4>
|
|
|
|
08002100 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8002100: b480 push {r7}
|
|
8002102: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8002104: bf00 nop
|
|
8002106: e7fd b.n 8002104 <BusFault_Handler+0x4>
|
|
|
|
08002108 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8002108: b480 push {r7}
|
|
800210a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
800210c: bf00 nop
|
|
800210e: e7fd b.n 800210c <UsageFault_Handler+0x4>
|
|
|
|
08002110 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8002110: b480 push {r7}
|
|
8002112: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8002114: bf00 nop
|
|
8002116: 46bd mov sp, r7
|
|
8002118: f85d 7b04 ldr.w r7, [sp], #4
|
|
800211c: 4770 bx lr
|
|
|
|
0800211e <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
800211e: b480 push {r7}
|
|
8002120: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8002122: bf00 nop
|
|
8002124: 46bd mov sp, r7
|
|
8002126: f85d 7b04 ldr.w r7, [sp], #4
|
|
800212a: 4770 bx lr
|
|
|
|
0800212c <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
800212c: b480 push {r7}
|
|
800212e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8002130: bf00 nop
|
|
8002132: 46bd mov sp, r7
|
|
8002134: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002138: 4770 bx lr
|
|
|
|
0800213a <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
800213a: b580 push {r7, lr}
|
|
800213c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
800213e: f000 f8c5 bl 80022cc <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8002142: bf00 nop
|
|
8002144: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08002148 <DMA1_Channel1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 channel1 global interrupt.
|
|
*/
|
|
void DMA1_Channel1_IRQHandler(void)
|
|
{
|
|
8002148: b580 push {r7, lr}
|
|
800214a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Channel1_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_adc1);
|
|
800214c: 4802 ldr r0, [pc, #8] @ (8002158 <DMA1_Channel1_IRQHandler+0x10>)
|
|
800214e: f002 fa68 bl 8004622 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Channel1_IRQn 1 */
|
|
}
|
|
8002152: bf00 nop
|
|
8002154: bd80 pop {r7, pc}
|
|
8002156: bf00 nop
|
|
8002158: 20000164 .word 0x20000164
|
|
|
|
0800215c <ADC1_2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles ADC1 and ADC2 interrupts.
|
|
*/
|
|
void ADC1_2_IRQHandler(void)
|
|
{
|
|
800215c: b580 push {r7, lr}
|
|
800215e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN ADC1_2_IRQn 0 */
|
|
|
|
/* USER CODE END ADC1_2_IRQn 0 */
|
|
HAL_ADC_IRQHandler(&hadc1);
|
|
8002160: 4803 ldr r0, [pc, #12] @ (8002170 <ADC1_2_IRQHandler+0x14>)
|
|
8002162: f000 fb81 bl 8002868 <HAL_ADC_IRQHandler>
|
|
HAL_ADC_IRQHandler(&hadc2);
|
|
8002166: 4803 ldr r0, [pc, #12] @ (8002174 <ADC1_2_IRQHandler+0x18>)
|
|
8002168: f000 fb7e bl 8002868 <HAL_ADC_IRQHandler>
|
|
/* USER CODE BEGIN ADC1_2_IRQn 1 */
|
|
|
|
/* USER CODE END ADC1_2_IRQn 1 */
|
|
}
|
|
800216c: bf00 nop
|
|
800216e: bd80 pop {r7, pc}
|
|
8002170: 200000c4 .word 0x200000c4
|
|
8002174: 20000114 .word 0x20000114
|
|
|
|
08002178 <USB_LP_CAN_RX0_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB low priority or CAN_RX0 interrupts.
|
|
*/
|
|
void USB_LP_CAN_RX0_IRQHandler(void)
|
|
{
|
|
8002178: b580 push {r7, lr}
|
|
800217a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */
|
|
|
|
/* USER CODE END USB_LP_CAN_RX0_IRQn 0 */
|
|
HAL_CAN_IRQHandler(&hcan);
|
|
800217c: 4802 ldr r0, [pc, #8] @ (8002188 <USB_LP_CAN_RX0_IRQHandler+0x10>)
|
|
800217e: f001 fe6a bl 8003e56 <HAL_CAN_IRQHandler>
|
|
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */
|
|
|
|
/* USER CODE END USB_LP_CAN_RX0_IRQn 1 */
|
|
}
|
|
8002182: bf00 nop
|
|
8002184: bd80 pop {r7, pc}
|
|
8002186: bf00 nop
|
|
8002188: 200001ec .word 0x200001ec
|
|
|
|
0800218c <CAN_RX1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles CAN RX1 interrupt.
|
|
*/
|
|
void CAN_RX1_IRQHandler(void)
|
|
{
|
|
800218c: b580 push {r7, lr}
|
|
800218e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN CAN_RX1_IRQn 0 */
|
|
|
|
/* USER CODE END CAN_RX1_IRQn 0 */
|
|
HAL_CAN_IRQHandler(&hcan);
|
|
8002190: 4802 ldr r0, [pc, #8] @ (800219c <CAN_RX1_IRQHandler+0x10>)
|
|
8002192: f001 fe60 bl 8003e56 <HAL_CAN_IRQHandler>
|
|
/* USER CODE BEGIN CAN_RX1_IRQn 1 */
|
|
|
|
/* USER CODE END CAN_RX1_IRQn 1 */
|
|
}
|
|
8002196: bf00 nop
|
|
8002198: bd80 pop {r7, pc}
|
|
800219a: bf00 nop
|
|
800219c: 200001ec .word 0x200001ec
|
|
|
|
080021a0 <TIM6_DAC_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles Timer 6 interrupt and DAC underrun interrupts.
|
|
*/
|
|
void TIM6_DAC_IRQHandler(void)
|
|
{
|
|
80021a0: b580 push {r7, lr}
|
|
80021a2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
|
|
|
|
/* USER CODE END TIM6_DAC_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim6);
|
|
80021a4: 4802 ldr r0, [pc, #8] @ (80021b0 <TIM6_DAC_IRQHandler+0x10>)
|
|
80021a6: f004 f97f bl 80064a8 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
|
|
|
|
/* USER CODE END TIM6_DAC_IRQn 1 */
|
|
}
|
|
80021aa: bf00 nop
|
|
80021ac: bd80 pop {r7, pc}
|
|
80021ae: bf00 nop
|
|
80021b0: 20000214 .word 0x20000214
|
|
|
|
080021b4 <DMA2_Channel1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA2 channel1 global interrupt.
|
|
*/
|
|
void DMA2_Channel1_IRQHandler(void)
|
|
{
|
|
80021b4: b580 push {r7, lr}
|
|
80021b6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA2_Channel1_IRQn 0 */
|
|
|
|
/* USER CODE END DMA2_Channel1_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_adc2);
|
|
80021b8: 4802 ldr r0, [pc, #8] @ (80021c4 <DMA2_Channel1_IRQHandler+0x10>)
|
|
80021ba: f002 fa32 bl 8004622 <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA2_Channel1_IRQn 1 */
|
|
|
|
/* USER CODE END DMA2_Channel1_IRQn 1 */
|
|
}
|
|
80021be: bf00 nop
|
|
80021c0: bd80 pop {r7, pc}
|
|
80021c2: bf00 nop
|
|
80021c4: 200001a8 .word 0x200001a8
|
|
|
|
080021c8 <SystemInit>:
|
|
* @brief Setup the microcontroller system
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
80021c8: b480 push {r7}
|
|
80021ca: af00 add r7, sp, #0
|
|
/* FPU settings --------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
80021cc: 4b06 ldr r3, [pc, #24] @ (80021e8 <SystemInit+0x20>)
|
|
80021ce: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80021d2: 4a05 ldr r2, [pc, #20] @ (80021e8 <SystemInit+0x20>)
|
|
80021d4: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
80021d8: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
80021dc: bf00 nop
|
|
80021de: 46bd mov sp, r7
|
|
80021e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80021e4: 4770 bx lr
|
|
80021e6: bf00 nop
|
|
80021e8: e000ed00 .word 0xe000ed00
|
|
|
|
080021ec <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Atollic update: set stack pointer */
|
|
80021ec: f8df d034 ldr.w sp, [pc, #52] @ 8002224 <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
80021f0: f7ff ffea bl 80021c8 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
80021f4: 480c ldr r0, [pc, #48] @ (8002228 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
80021f6: 490d ldr r1, [pc, #52] @ (800222c <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
80021f8: 4a0d ldr r2, [pc, #52] @ (8002230 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
80021fa: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
80021fc: e002 b.n 8002204 <LoopCopyDataInit>
|
|
|
|
080021fe <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
80021fe: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8002200: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8002202: 3304 adds r3, #4
|
|
|
|
08002204 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8002204: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8002206: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8002208: d3f9 bcc.n 80021fe <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800220a: 4a0a ldr r2, [pc, #40] @ (8002234 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
800220c: 4c0a ldr r4, [pc, #40] @ (8002238 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
800220e: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8002210: e001 b.n 8002216 <LoopFillZerobss>
|
|
|
|
08002212 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8002212: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8002214: 3204 adds r2, #4
|
|
|
|
08002216 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8002216: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8002218: d3fb bcc.n 8002212 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800221a: f004 ffdf bl 80071dc <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800221e: f7fe ffed bl 80011fc <main>
|
|
|
|
08002222 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
8002222: e7fe b.n 8002222 <LoopForever>
|
|
ldr sp, =_estack /* Atollic update: set stack pointer */
|
|
8002224: 20008000 .word 0x20008000
|
|
ldr r0, =_sdata
|
|
8002228: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
800222c: 2000000c .word 0x2000000c
|
|
ldr r2, =_sidata
|
|
8002230: 0800727c .word 0x0800727c
|
|
ldr r2, =_sbss
|
|
8002234: 2000000c .word 0x2000000c
|
|
ldr r4, =_ebss
|
|
8002238: 20000300 .word 0x20000300
|
|
|
|
0800223c <CAN_SCE_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
800223c: e7fe b.n 800223c <CAN_SCE_IRQHandler>
|
|
...
|
|
|
|
08002240 <HAL_Init>:
|
|
* In the default implementation,Systick is used as source of time base.
|
|
* The tick variable is incremented each 1ms in its ISR.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8002240: b580 push {r7, lr}
|
|
8002242: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch */
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
8002244: 4b08 ldr r3, [pc, #32] @ (8002268 <HAL_Init+0x28>)
|
|
8002246: 681b ldr r3, [r3, #0]
|
|
8002248: 4a07 ldr r2, [pc, #28] @ (8002268 <HAL_Init+0x28>)
|
|
800224a: f043 0310 orr.w r3, r3, #16
|
|
800224e: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8002250: 2003 movs r0, #3
|
|
8002252: f002 f8ff bl 8004454 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
8002256: 200f movs r0, #15
|
|
8002258: f000 f808 bl 800226c <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
800225c: f7ff fd30 bl 8001cc0 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8002260: 2300 movs r3, #0
|
|
}
|
|
8002262: 4618 mov r0, r3
|
|
8002264: bd80 pop {r7, pc}
|
|
8002266: bf00 nop
|
|
8002268: 40022000 .word 0x40022000
|
|
|
|
0800226c <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
800226c: b580 push {r7, lr}
|
|
800226e: b082 sub sp, #8
|
|
8002270: af00 add r7, sp, #0
|
|
8002272: 6078 str r0, [r7, #4]
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
|
8002274: 4b12 ldr r3, [pc, #72] @ (80022c0 <HAL_InitTick+0x54>)
|
|
8002276: 681a ldr r2, [r3, #0]
|
|
8002278: 4b12 ldr r3, [pc, #72] @ (80022c4 <HAL_InitTick+0x58>)
|
|
800227a: 781b ldrb r3, [r3, #0]
|
|
800227c: 4619 mov r1, r3
|
|
800227e: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8002282: fbb3 f3f1 udiv r3, r3, r1
|
|
8002286: fbb2 f3f3 udiv r3, r2, r3
|
|
800228a: 4618 mov r0, r3
|
|
800228c: f002 f917 bl 80044be <HAL_SYSTICK_Config>
|
|
8002290: 4603 mov r3, r0
|
|
8002292: 2b00 cmp r3, #0
|
|
8002294: d001 beq.n 800229a <HAL_InitTick+0x2e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002296: 2301 movs r3, #1
|
|
8002298: e00e b.n 80022b8 <HAL_InitTick+0x4c>
|
|
}
|
|
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
800229a: 687b ldr r3, [r7, #4]
|
|
800229c: 2b0f cmp r3, #15
|
|
800229e: d80a bhi.n 80022b6 <HAL_InitTick+0x4a>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80022a0: 2200 movs r2, #0
|
|
80022a2: 6879 ldr r1, [r7, #4]
|
|
80022a4: f04f 30ff mov.w r0, #4294967295
|
|
80022a8: f002 f8df bl 800446a <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80022ac: 4a06 ldr r2, [pc, #24] @ (80022c8 <HAL_InitTick+0x5c>)
|
|
80022ae: 687b ldr r3, [r7, #4]
|
|
80022b0: 6013 str r3, [r2, #0]
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80022b2: 2300 movs r3, #0
|
|
80022b4: e000 b.n 80022b8 <HAL_InitTick+0x4c>
|
|
return HAL_ERROR;
|
|
80022b6: 2301 movs r3, #1
|
|
}
|
|
80022b8: 4618 mov r0, r3
|
|
80022ba: 3708 adds r7, #8
|
|
80022bc: 46bd mov sp, r7
|
|
80022be: bd80 pop {r7, pc}
|
|
80022c0: 20000000 .word 0x20000000
|
|
80022c4: 20000008 .word 0x20000008
|
|
80022c8: 20000004 .word 0x20000004
|
|
|
|
080022cc <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80022cc: b480 push {r7}
|
|
80022ce: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80022d0: 4b06 ldr r3, [pc, #24] @ (80022ec <HAL_IncTick+0x20>)
|
|
80022d2: 781b ldrb r3, [r3, #0]
|
|
80022d4: 461a mov r2, r3
|
|
80022d6: 4b06 ldr r3, [pc, #24] @ (80022f0 <HAL_IncTick+0x24>)
|
|
80022d8: 681b ldr r3, [r3, #0]
|
|
80022da: 4413 add r3, r2
|
|
80022dc: 4a04 ldr r2, [pc, #16] @ (80022f0 <HAL_IncTick+0x24>)
|
|
80022de: 6013 str r3, [r2, #0]
|
|
}
|
|
80022e0: bf00 nop
|
|
80022e2: 46bd mov sp, r7
|
|
80022e4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80022e8: 4770 bx lr
|
|
80022ea: bf00 nop
|
|
80022ec: 20000008 .word 0x20000008
|
|
80022f0: 200002fc .word 0x200002fc
|
|
|
|
080022f4 <HAL_GetTick>:
|
|
* @note The function is declared as __Weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80022f4: b480 push {r7}
|
|
80022f6: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80022f8: 4b03 ldr r3, [pc, #12] @ (8002308 <HAL_GetTick+0x14>)
|
|
80022fa: 681b ldr r3, [r3, #0]
|
|
}
|
|
80022fc: 4618 mov r0, r3
|
|
80022fe: 46bd mov sp, r7
|
|
8002300: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002304: 4770 bx lr
|
|
8002306: bf00 nop
|
|
8002308: 200002fc .word 0x200002fc
|
|
|
|
0800230c <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
800230c: b580 push {r7, lr}
|
|
800230e: b084 sub sp, #16
|
|
8002310: af00 add r7, sp, #0
|
|
8002312: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8002314: f7ff ffee bl 80022f4 <HAL_GetTick>
|
|
8002318: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
800231a: 687b ldr r3, [r7, #4]
|
|
800231c: 60fb str r3, [r7, #12]
|
|
|
|
/* Add freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
800231e: 68fb ldr r3, [r7, #12]
|
|
8002320: f1b3 3fff cmp.w r3, #4294967295
|
|
8002324: d005 beq.n 8002332 <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8002326: 4b0a ldr r3, [pc, #40] @ (8002350 <HAL_Delay+0x44>)
|
|
8002328: 781b ldrb r3, [r3, #0]
|
|
800232a: 461a mov r2, r3
|
|
800232c: 68fb ldr r3, [r7, #12]
|
|
800232e: 4413 add r3, r2
|
|
8002330: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
8002332: bf00 nop
|
|
8002334: f7ff ffde bl 80022f4 <HAL_GetTick>
|
|
8002338: 4602 mov r2, r0
|
|
800233a: 68bb ldr r3, [r7, #8]
|
|
800233c: 1ad3 subs r3, r2, r3
|
|
800233e: 68fa ldr r2, [r7, #12]
|
|
8002340: 429a cmp r2, r3
|
|
8002342: d8f7 bhi.n 8002334 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8002344: bf00 nop
|
|
8002346: bf00 nop
|
|
8002348: 3710 adds r7, #16
|
|
800234a: 46bd mov sp, r7
|
|
800234c: bd80 pop {r7, pc}
|
|
800234e: bf00 nop
|
|
8002350: 20000008 .word 0x20000008
|
|
|
|
08002354 <HAL_ADC_ConvHalfCpltCallback>:
|
|
* @brief Conversion DMA half-transfer callback in non blocking mode
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002354: b480 push {r7}
|
|
8002356: b083 sub sp, #12
|
|
8002358: af00 add r7, sp, #0
|
|
800235a: 6078 str r0, [r7, #4]
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
|
|
*/
|
|
}
|
|
800235c: bf00 nop
|
|
800235e: 370c adds r7, #12
|
|
8002360: 46bd mov sp, r7
|
|
8002362: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002366: 4770 bx lr
|
|
|
|
08002368 <HAL_ADC_LevelOutOfWindowCallback>:
|
|
* @brief Analog watchdog callback in non blocking mode.
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002368: b480 push {r7}
|
|
800236a: b083 sub sp, #12
|
|
800236c: af00 add r7, sp, #0
|
|
800236e: 6078 str r0, [r7, #4]
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
|
|
*/
|
|
}
|
|
8002370: bf00 nop
|
|
8002372: 370c adds r7, #12
|
|
8002374: 46bd mov sp, r7
|
|
8002376: f85d 7b04 ldr.w r7, [sp], #4
|
|
800237a: 4770 bx lr
|
|
|
|
0800237c <HAL_ADC_ErrorCallback>:
|
|
* (ADC conversion with interruption or transfer by DMA)
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
|
|
{
|
|
800237c: b480 push {r7}
|
|
800237e: b083 sub sp, #12
|
|
8002380: af00 add r7, sp, #0
|
|
8002382: 6078 str r0, [r7, #4]
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADC_ErrorCallback must be implemented in the user file.
|
|
*/
|
|
}
|
|
8002384: bf00 nop
|
|
8002386: 370c adds r7, #12
|
|
8002388: 46bd mov sp, r7
|
|
800238a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800238e: 4770 bx lr
|
|
|
|
08002390 <HAL_ADC_Init>:
|
|
* without disabling the other ADCs sharing the same common group.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002390: b580 push {r7, lr}
|
|
8002392: b09a sub sp, #104 @ 0x68
|
|
8002394: af00 add r7, sp, #0
|
|
8002396: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8002398: 2300 movs r3, #0
|
|
800239a: f887 3067 strb.w r3, [r7, #103] @ 0x67
|
|
ADC_Common_TypeDef *tmpADC_Common;
|
|
ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
|
|
uint32_t tmpCFGR = 0U;
|
|
800239e: 2300 movs r3, #0
|
|
80023a0: 663b str r3, [r7, #96] @ 0x60
|
|
__IO uint32_t wait_loop_index = 0U;
|
|
80023a2: 2300 movs r3, #0
|
|
80023a4: 60bb str r3, [r7, #8]
|
|
|
|
/* Check ADC handle */
|
|
if(hadc == NULL)
|
|
80023a6: 687b ldr r3, [r7, #4]
|
|
80023a8: 2b00 cmp r3, #0
|
|
80023aa: d101 bne.n 80023b0 <HAL_ADC_Init+0x20>
|
|
{
|
|
return HAL_ERROR;
|
|
80023ac: 2301 movs r3, #1
|
|
80023ae: e172 b.n 8002696 <HAL_ADC_Init+0x306>
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
|
|
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
|
|
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
|
|
|
|
if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
|
|
80023b0: 687b ldr r3, [r7, #4]
|
|
80023b2: 691b ldr r3, [r3, #16]
|
|
80023b4: 2b00 cmp r3, #0
|
|
assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
|
|
}
|
|
}
|
|
|
|
/* Configuration of ADC core parameters and ADC MSP related parameters */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
|
|
80023b6: 687b ldr r3, [r7, #4]
|
|
80023b8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80023ba: f003 0310 and.w r3, r3, #16
|
|
80023be: 2b00 cmp r3, #0
|
|
80023c0: d176 bne.n 80024b0 <HAL_ADC_Init+0x120>
|
|
/* procedure. */
|
|
|
|
/* Actions performed only if ADC is coming from state reset: */
|
|
/* - Initialization of ADC MSP */
|
|
/* - ADC voltage regulator enable */
|
|
if (hadc->State == HAL_ADC_STATE_RESET)
|
|
80023c2: 687b ldr r3, [r7, #4]
|
|
80023c4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80023c6: 2b00 cmp r3, #0
|
|
80023c8: d152 bne.n 8002470 <HAL_ADC_Init+0xe0>
|
|
{
|
|
/* Initialize ADC error code */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
80023ca: 687b ldr r3, [r7, #4]
|
|
80023cc: 2200 movs r2, #0
|
|
80023ce: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Initialize HAL ADC API internal variables */
|
|
hadc->InjectionConfig.ChannelCount = 0U;
|
|
80023d0: 687b ldr r3, [r7, #4]
|
|
80023d2: 2200 movs r2, #0
|
|
80023d4: 64da str r2, [r3, #76] @ 0x4c
|
|
hadc->InjectionConfig.ContextQueue = 0U;
|
|
80023d6: 687b ldr r3, [r7, #4]
|
|
80023d8: 2200 movs r2, #0
|
|
80023da: 649a str r2, [r3, #72] @ 0x48
|
|
|
|
/* Allocate lock resource and initialize it */
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
80023dc: 687b ldr r3, [r7, #4]
|
|
80023de: 2200 movs r2, #0
|
|
80023e0: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware */
|
|
hadc->MspInitCallback(hadc);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_ADC_MspInit(hadc);
|
|
80023e4: 6878 ldr r0, [r7, #4]
|
|
80023e6: f7ff fc8f bl 8001d08 <HAL_ADC_MspInit>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
|
|
/* Enable voltage regulator (if disabled at this step) */
|
|
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
|
|
80023ea: 687b ldr r3, [r7, #4]
|
|
80023ec: 681b ldr r3, [r3, #0]
|
|
80023ee: 689b ldr r3, [r3, #8]
|
|
80023f0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80023f4: 2b00 cmp r3, #0
|
|
80023f6: d13b bne.n 8002470 <HAL_ADC_Init+0xe0>
|
|
/* enabling the ADC. This temporization must be implemented by */
|
|
/* software and is equal to 10 us in the worst case */
|
|
/* process/temperature/power supply. */
|
|
|
|
/* Disable the ADC (if not already disabled) */
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
80023f8: 6878 ldr r0, [r7, #4]
|
|
80023fa: f001 f8a5 bl 8003548 <ADC_Disable>
|
|
80023fe: 4603 mov r3, r0
|
|
8002400: f887 3067 strb.w r3, [r7, #103] @ 0x67
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
/* Configuration of ADC parameters if previous preliminary actions */
|
|
/* are correctly completed. */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
|
|
8002404: 687b ldr r3, [r7, #4]
|
|
8002406: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002408: f003 0310 and.w r3, r3, #16
|
|
800240c: 2b00 cmp r3, #0
|
|
800240e: d12f bne.n 8002470 <HAL_ADC_Init+0xe0>
|
|
8002410: f897 3067 ldrb.w r3, [r7, #103] @ 0x67
|
|
8002414: 2b00 cmp r3, #0
|
|
8002416: d12b bne.n 8002470 <HAL_ADC_Init+0xe0>
|
|
(tmp_hal_status == HAL_OK) )
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002418: 687b ldr r3, [r7, #4]
|
|
800241a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800241c: f423 5388 bic.w r3, r3, #4352 @ 0x1100
|
|
8002420: f023 0302 bic.w r3, r3, #2
|
|
8002424: f043 0202 orr.w r2, r3, #2
|
|
8002428: 687b ldr r3, [r7, #4]
|
|
800242a: 641a str r2, [r3, #64] @ 0x40
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_BUSY_INTERNAL);
|
|
|
|
/* Set the intermediate state before moving the ADC voltage */
|
|
/* regulator to state enable. */
|
|
CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0));
|
|
800242c: 687b ldr r3, [r7, #4]
|
|
800242e: 681b ldr r3, [r3, #0]
|
|
8002430: 689a ldr r2, [r3, #8]
|
|
8002432: 687b ldr r3, [r7, #4]
|
|
8002434: 681b ldr r3, [r3, #0]
|
|
8002436: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000
|
|
800243a: 609a str r2, [r3, #8]
|
|
/* Set ADVREGEN bits to 0x01U */
|
|
SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0);
|
|
800243c: 687b ldr r3, [r7, #4]
|
|
800243e: 681b ldr r3, [r3, #0]
|
|
8002440: 689a ldr r2, [r3, #8]
|
|
8002442: 687b ldr r3, [r7, #4]
|
|
8002444: 681b ldr r3, [r3, #0]
|
|
8002446: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000
|
|
800244a: 609a str r2, [r3, #8]
|
|
|
|
/* Delay for ADC stabilization time. */
|
|
/* Compute number of CPU cycles to wait for */
|
|
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
|
|
800244c: 4b94 ldr r3, [pc, #592] @ (80026a0 <HAL_ADC_Init+0x310>)
|
|
800244e: 681b ldr r3, [r3, #0]
|
|
8002450: 4a94 ldr r2, [pc, #592] @ (80026a4 <HAL_ADC_Init+0x314>)
|
|
8002452: fba2 2303 umull r2, r3, r2, r3
|
|
8002456: 0c9a lsrs r2, r3, #18
|
|
8002458: 4613 mov r3, r2
|
|
800245a: 009b lsls r3, r3, #2
|
|
800245c: 4413 add r3, r2
|
|
800245e: 005b lsls r3, r3, #1
|
|
8002460: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
8002462: e002 b.n 800246a <HAL_ADC_Init+0xda>
|
|
{
|
|
wait_loop_index--;
|
|
8002464: 68bb ldr r3, [r7, #8]
|
|
8002466: 3b01 subs r3, #1
|
|
8002468: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
800246a: 68bb ldr r3, [r7, #8]
|
|
800246c: 2b00 cmp r3, #0
|
|
800246e: d1f9 bne.n 8002464 <HAL_ADC_Init+0xd4>
|
|
}
|
|
|
|
/* Verification that ADC voltage regulator is correctly enabled, whether */
|
|
/* or not ADC is coming from state reset (if any potential problem of */
|
|
/* clocking, voltage regulator would not be enabled). */
|
|
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
|
|
8002470: 687b ldr r3, [r7, #4]
|
|
8002472: 681b ldr r3, [r3, #0]
|
|
8002474: 689b ldr r3, [r3, #8]
|
|
8002476: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800247a: 2b00 cmp r3, #0
|
|
800247c: d007 beq.n 800248e <HAL_ADC_Init+0xfe>
|
|
HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) )
|
|
800247e: 687b ldr r3, [r7, #4]
|
|
8002480: 681b ldr r3, [r3, #0]
|
|
8002482: 689b ldr r3, [r3, #8]
|
|
8002484: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) ||
|
|
8002488: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
800248c: d110 bne.n 80024b0 <HAL_ADC_Init+0x120>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
800248e: 687b ldr r3, [r7, #4]
|
|
8002490: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002492: f023 0312 bic.w r3, r3, #18
|
|
8002496: f043 0210 orr.w r2, r3, #16
|
|
800249a: 687b ldr r3, [r7, #4]
|
|
800249c: 641a str r2, [r3, #64] @ 0x40
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
800249e: 687b ldr r3, [r7, #4]
|
|
80024a0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80024a2: f043 0201 orr.w r2, r3, #1
|
|
80024a6: 687b ldr r3, [r7, #4]
|
|
80024a8: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
80024aa: 2301 movs r3, #1
|
|
80024ac: f887 3067 strb.w r3, [r7, #103] @ 0x67
|
|
|
|
/* Configuration of ADC parameters if previous preliminary actions are */
|
|
/* correctly completed and if there is no conversion on going on regular */
|
|
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
|
|
/* called to update a parameter on the fly). */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
|
|
80024b0: 687b ldr r3, [r7, #4]
|
|
80024b2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80024b4: f003 0310 and.w r3, r3, #16
|
|
80024b8: 2b00 cmp r3, #0
|
|
80024ba: f040 80df bne.w 800267c <HAL_ADC_Init+0x2ec>
|
|
80024be: f897 3067 ldrb.w r3, [r7, #103] @ 0x67
|
|
80024c2: 2b00 cmp r3, #0
|
|
80024c4: f040 80da bne.w 800267c <HAL_ADC_Init+0x2ec>
|
|
(tmp_hal_status == HAL_OK) &&
|
|
(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
|
|
80024c8: 687b ldr r3, [r7, #4]
|
|
80024ca: 681b ldr r3, [r3, #0]
|
|
80024cc: 689b ldr r3, [r3, #8]
|
|
80024ce: f003 0304 and.w r3, r3, #4
|
|
(tmp_hal_status == HAL_OK) &&
|
|
80024d2: 2b00 cmp r3, #0
|
|
80024d4: f040 80d2 bne.w 800267c <HAL_ADC_Init+0x2ec>
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
80024d8: 687b ldr r3, [r7, #4]
|
|
80024da: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80024dc: f423 7381 bic.w r3, r3, #258 @ 0x102
|
|
80024e0: f043 0202 orr.w r2, r3, #2
|
|
80024e4: 687b ldr r3, [r7, #4]
|
|
80024e6: 641a str r2, [r3, #64] @ 0x40
|
|
/* Configuration of common ADC parameters */
|
|
|
|
/* Pointer to the common control register to which is belonging hadc */
|
|
/* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
|
|
/* control registers) */
|
|
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
|
|
80024e8: 4b6f ldr r3, [pc, #444] @ (80026a8 <HAL_ADC_Init+0x318>)
|
|
80024ea: 65fb str r3, [r7, #92] @ 0x5c
|
|
|
|
/* Set handle of the other ADC sharing the same common register */
|
|
ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
|
|
80024ec: 687b ldr r3, [r7, #4]
|
|
80024ee: 681b ldr r3, [r3, #0]
|
|
80024f0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
80024f4: d102 bne.n 80024fc <HAL_ADC_Init+0x16c>
|
|
80024f6: 4b6d ldr r3, [pc, #436] @ (80026ac <HAL_ADC_Init+0x31c>)
|
|
80024f8: 60fb str r3, [r7, #12]
|
|
80024fa: e002 b.n 8002502 <HAL_ADC_Init+0x172>
|
|
80024fc: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
8002500: 60fb str r3, [r7, #12]
|
|
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Multimode clock configuration */
|
|
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
|
8002502: 687b ldr r3, [r7, #4]
|
|
8002504: 681b ldr r3, [r3, #0]
|
|
8002506: 689b ldr r3, [r3, #8]
|
|
8002508: f003 0303 and.w r3, r3, #3
|
|
800250c: 2b01 cmp r3, #1
|
|
800250e: d108 bne.n 8002522 <HAL_ADC_Init+0x192>
|
|
8002510: 687b ldr r3, [r7, #4]
|
|
8002512: 681b ldr r3, [r3, #0]
|
|
8002514: 681b ldr r3, [r3, #0]
|
|
8002516: f003 0301 and.w r3, r3, #1
|
|
800251a: 2b01 cmp r3, #1
|
|
800251c: d101 bne.n 8002522 <HAL_ADC_Init+0x192>
|
|
800251e: 2301 movs r3, #1
|
|
8002520: e000 b.n 8002524 <HAL_ADC_Init+0x194>
|
|
8002522: 2300 movs r3, #0
|
|
8002524: 2b00 cmp r3, #0
|
|
8002526: d11c bne.n 8002562 <HAL_ADC_Init+0x1d2>
|
|
((tmphadcSharingSameCommonRegister.Instance == NULL) ||
|
|
8002528: 68fb ldr r3, [r7, #12]
|
|
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
|
800252a: 2b00 cmp r3, #0
|
|
800252c: d010 beq.n 8002550 <HAL_ADC_Init+0x1c0>
|
|
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
|
|
800252e: 68fb ldr r3, [r7, #12]
|
|
8002530: 689b ldr r3, [r3, #8]
|
|
8002532: f003 0303 and.w r3, r3, #3
|
|
8002536: 2b01 cmp r3, #1
|
|
8002538: d107 bne.n 800254a <HAL_ADC_Init+0x1ba>
|
|
800253a: 68fb ldr r3, [r7, #12]
|
|
800253c: 681b ldr r3, [r3, #0]
|
|
800253e: f003 0301 and.w r3, r3, #1
|
|
8002542: 2b01 cmp r3, #1
|
|
8002544: d101 bne.n 800254a <HAL_ADC_Init+0x1ba>
|
|
8002546: 2301 movs r3, #1
|
|
8002548: e000 b.n 800254c <HAL_ADC_Init+0x1bc>
|
|
800254a: 2300 movs r3, #0
|
|
((tmphadcSharingSameCommonRegister.Instance == NULL) ||
|
|
800254c: 2b00 cmp r3, #0
|
|
800254e: d108 bne.n 8002562 <HAL_ADC_Init+0x1d2>
|
|
/* into HAL_ADCEx_MultiModeConfigChannel() ) */
|
|
/* - internal measurement paths: Vbat, temperature sensor, Vref */
|
|
/* (set into HAL_ADC_ConfigChannel() or */
|
|
/* HAL_ADCEx_InjectedConfigChannel() ) */
|
|
|
|
MODIFY_REG(tmpADC_Common->CCR ,
|
|
8002550: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8002552: 689b ldr r3, [r3, #8]
|
|
8002554: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
8002558: 687b ldr r3, [r7, #4]
|
|
800255a: 685b ldr r3, [r3, #4]
|
|
800255c: 431a orrs r2, r3
|
|
800255e: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8002560: 609a str r2, [r3, #8]
|
|
/* - external trigger to start conversion */
|
|
/* - external trigger polarity */
|
|
/* - continuous conversion mode */
|
|
/* - overrun */
|
|
/* - discontinuous mode */
|
|
SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
8002562: 687b ldr r3, [r7, #4]
|
|
8002564: 7e5b ldrb r3, [r3, #25]
|
|
8002566: 035b lsls r3, r3, #13
|
|
8002568: 687a ldr r2, [r7, #4]
|
|
800256a: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
800256c: 2a01 cmp r2, #1
|
|
800256e: d002 beq.n 8002576 <HAL_ADC_Init+0x1e6>
|
|
8002570: f44f 5280 mov.w r2, #4096 @ 0x1000
|
|
8002574: e000 b.n 8002578 <HAL_ADC_Init+0x1e8>
|
|
8002576: 2200 movs r2, #0
|
|
8002578: 431a orrs r2, r3
|
|
800257a: 687b ldr r3, [r7, #4]
|
|
800257c: 68db ldr r3, [r3, #12]
|
|
800257e: 431a orrs r2, r3
|
|
8002580: 687b ldr r3, [r7, #4]
|
|
8002582: 689b ldr r3, [r3, #8]
|
|
8002584: 4313 orrs r3, r2
|
|
8002586: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
8002588: 4313 orrs r3, r2
|
|
800258a: 663b str r3, [r7, #96] @ 0x60
|
|
ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
|
|
hadc->Init.DataAlign |
|
|
hadc->Init.Resolution );
|
|
|
|
/* Enable discontinuous mode only if continuous mode is disabled */
|
|
if (hadc->Init.DiscontinuousConvMode == ENABLE)
|
|
800258c: 687b ldr r3, [r7, #4]
|
|
800258e: f893 3020 ldrb.w r3, [r3, #32]
|
|
8002592: 2b01 cmp r3, #1
|
|
8002594: d11b bne.n 80025ce <HAL_ADC_Init+0x23e>
|
|
{
|
|
if (hadc->Init.ContinuousConvMode == DISABLE)
|
|
8002596: 687b ldr r3, [r7, #4]
|
|
8002598: 7e5b ldrb r3, [r3, #25]
|
|
800259a: 2b00 cmp r3, #0
|
|
800259c: d109 bne.n 80025b2 <HAL_ADC_Init+0x222>
|
|
{
|
|
/* Enable the selected ADC regular discontinuous mode */
|
|
/* Set the number of channels to be converted in discontinuous mode */
|
|
SET_BIT(tmpCFGR, ADC_CFGR_DISCEN |
|
|
800259e: 687b ldr r3, [r7, #4]
|
|
80025a0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80025a2: 3b01 subs r3, #1
|
|
80025a4: 045a lsls r2, r3, #17
|
|
80025a6: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
80025a8: 4313 orrs r3, r2
|
|
80025aa: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80025ae: 663b str r3, [r7, #96] @ 0x60
|
|
80025b0: e00d b.n 80025ce <HAL_ADC_Init+0x23e>
|
|
/* ADC regular group discontinuous was intended to be enabled, */
|
|
/* but ADC regular group modes continuous and sequencer discontinuous */
|
|
/* cannot be enabled simultaneously. */
|
|
|
|
/* Update ADC state machine to error */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
80025b2: 687b ldr r3, [r7, #4]
|
|
80025b4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80025b6: f023 0322 bic.w r3, r3, #34 @ 0x22
|
|
80025ba: f043 0220 orr.w r2, r3, #32
|
|
80025be: 687b ldr r3, [r7, #4]
|
|
80025c0: 641a str r2, [r3, #64] @ 0x40
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
80025c2: 687b ldr r3, [r7, #4]
|
|
80025c4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80025c6: f043 0201 orr.w r2, r3, #1
|
|
80025ca: 687b ldr r3, [r7, #4]
|
|
80025cc: 645a str r2, [r3, #68] @ 0x44
|
|
/* Enable external trigger if trigger selection is different of software */
|
|
/* start. */
|
|
/* Note: This configuration keeps the hardware feature of parameter */
|
|
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
|
|
/* software start. */
|
|
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
|
|
80025ce: 687b ldr r3, [r7, #4]
|
|
80025d0: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80025d2: 2b01 cmp r3, #1
|
|
80025d4: d007 beq.n 80025e6 <HAL_ADC_Init+0x256>
|
|
{
|
|
SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) |
|
|
80025d6: 687b ldr r3, [r7, #4]
|
|
80025d8: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
80025da: 687b ldr r3, [r7, #4]
|
|
80025dc: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80025de: 4313 orrs r3, r2
|
|
80025e0: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
80025e2: 4313 orrs r3, r2
|
|
80025e4: 663b str r3, [r7, #96] @ 0x60
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular and injected groups: */
|
|
/* - DMA continuous request */
|
|
/* - LowPowerAutoWait feature */
|
|
if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
|
|
80025e6: 687b ldr r3, [r7, #4]
|
|
80025e8: 681b ldr r3, [r3, #0]
|
|
80025ea: 689b ldr r3, [r3, #8]
|
|
80025ec: f003 030c and.w r3, r3, #12
|
|
80025f0: 2b00 cmp r3, #0
|
|
80025f2: d114 bne.n 800261e <HAL_ADC_Init+0x28e>
|
|
{
|
|
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY |
|
|
80025f4: 687b ldr r3, [r7, #4]
|
|
80025f6: 681b ldr r3, [r3, #0]
|
|
80025f8: 68db ldr r3, [r3, #12]
|
|
80025fa: 687a ldr r2, [r7, #4]
|
|
80025fc: 6812 ldr r2, [r2, #0]
|
|
80025fe: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8002602: f023 0302 bic.w r3, r3, #2
|
|
8002606: 60d3 str r3, [r2, #12]
|
|
ADC_CFGR_DMACFG );
|
|
|
|
SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
8002608: 687b ldr r3, [r7, #4]
|
|
800260a: 7e1b ldrb r3, [r3, #24]
|
|
800260c: 039a lsls r2, r3, #14
|
|
800260e: 687b ldr r3, [r7, #4]
|
|
8002610: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
|
|
8002614: 005b lsls r3, r3, #1
|
|
8002616: 4313 orrs r3, r2
|
|
8002618: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
800261a: 4313 orrs r3, r2
|
|
800261c: 663b str r3, [r7, #96] @ 0x60
|
|
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
|
|
}
|
|
|
|
/* Update ADC configuration register with previous settings */
|
|
MODIFY_REG(hadc->Instance->CFGR,
|
|
800261e: 687b ldr r3, [r7, #4]
|
|
8002620: 681b ldr r3, [r3, #0]
|
|
8002622: 68da ldr r2, [r3, #12]
|
|
8002624: 4b22 ldr r3, [pc, #136] @ (80026b0 <HAL_ADC_Init+0x320>)
|
|
8002626: 4013 ands r3, r2
|
|
8002628: 687a ldr r2, [r7, #4]
|
|
800262a: 6812 ldr r2, [r2, #0]
|
|
800262c: 6e39 ldr r1, [r7, #96] @ 0x60
|
|
800262e: 430b orrs r3, r1
|
|
8002630: 60d3 str r3, [r2, #12]
|
|
/* Parameter "NbrOfConversion" is discarded. */
|
|
/* Note: Scan mode is not present by hardware on this device, but */
|
|
/* emulated by software for alignment over all STM32 devices. */
|
|
/* - if scan mode is enabled, regular channels sequence length is set to */
|
|
/* parameter "NbrOfConversion" */
|
|
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
|
|
8002632: 687b ldr r3, [r7, #4]
|
|
8002634: 691b ldr r3, [r3, #16]
|
|
8002636: 2b01 cmp r3, #1
|
|
8002638: d10c bne.n 8002654 <HAL_ADC_Init+0x2c4>
|
|
{
|
|
/* Set number of ranks in regular group sequencer */
|
|
MODIFY_REG(hadc->Instance->SQR1 ,
|
|
800263a: 687b ldr r3, [r7, #4]
|
|
800263c: 681b ldr r3, [r3, #0]
|
|
800263e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8002640: f023 010f bic.w r1, r3, #15
|
|
8002644: 687b ldr r3, [r7, #4]
|
|
8002646: 69db ldr r3, [r3, #28]
|
|
8002648: 1e5a subs r2, r3, #1
|
|
800264a: 687b ldr r3, [r7, #4]
|
|
800264c: 681b ldr r3, [r3, #0]
|
|
800264e: 430a orrs r2, r1
|
|
8002650: 631a str r2, [r3, #48] @ 0x30
|
|
8002652: e007 b.n 8002664 <HAL_ADC_Init+0x2d4>
|
|
ADC_SQR1_L ,
|
|
(hadc->Init.NbrOfConversion - (uint8_t)1U) );
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
|
|
8002654: 687b ldr r3, [r7, #4]
|
|
8002656: 681b ldr r3, [r3, #0]
|
|
8002658: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
800265a: 687b ldr r3, [r7, #4]
|
|
800265c: 681b ldr r3, [r3, #0]
|
|
800265e: f022 020f bic.w r2, r2, #15
|
|
8002662: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8002664: 687b ldr r3, [r7, #4]
|
|
8002666: 2200 movs r2, #0
|
|
8002668: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Set the ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
800266a: 687b ldr r3, [r7, #4]
|
|
800266c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800266e: f023 0303 bic.w r3, r3, #3
|
|
8002672: f043 0201 orr.w r2, r3, #1
|
|
8002676: 687b ldr r3, [r7, #4]
|
|
8002678: 641a str r2, [r3, #64] @ 0x40
|
|
800267a: e00a b.n 8002692 <HAL_ADC_Init+0x302>
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
800267c: 687b ldr r3, [r7, #4]
|
|
800267e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002680: f023 0312 bic.w r3, r3, #18
|
|
8002684: f043 0210 orr.w r2, r3, #16
|
|
8002688: 687b ldr r3, [r7, #4]
|
|
800268a: 641a str r2, [r3, #64] @ 0x40
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
800268c: 2301 movs r3, #1
|
|
800268e: f887 3067 strb.w r3, [r7, #103] @ 0x67
|
|
}
|
|
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8002692: f897 3067 ldrb.w r3, [r7, #103] @ 0x67
|
|
}
|
|
8002696: 4618 mov r0, r3
|
|
8002698: 3768 adds r7, #104 @ 0x68
|
|
800269a: 46bd mov sp, r7
|
|
800269c: bd80 pop {r7, pc}
|
|
800269e: bf00 nop
|
|
80026a0: 20000000 .word 0x20000000
|
|
80026a4: 431bde83 .word 0x431bde83
|
|
80026a8: 50000300 .word 0x50000300
|
|
80026ac: 50000100 .word 0x50000100
|
|
80026b0: fff0c007 .word 0xfff0c007
|
|
|
|
080026b4 <HAL_ADC_Start_DMA>:
|
|
* @param pData The destination Buffer address.
|
|
* @param Length The length of data to be transferred from ADC peripheral to memory.
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
|
|
{
|
|
80026b4: b580 push {r7, lr}
|
|
80026b6: b086 sub sp, #24
|
|
80026b8: af00 add r7, sp, #0
|
|
80026ba: 60f8 str r0, [r7, #12]
|
|
80026bc: 60b9 str r1, [r7, #8]
|
|
80026be: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
80026c0: 2300 movs r3, #0
|
|
80026c2: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Perform ADC enable and conversion start if no conversion is on going */
|
|
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
|
|
80026c4: 68fb ldr r3, [r7, #12]
|
|
80026c6: 681b ldr r3, [r3, #0]
|
|
80026c8: 689b ldr r3, [r3, #8]
|
|
80026ca: f003 0304 and.w r3, r3, #4
|
|
80026ce: 2b00 cmp r3, #0
|
|
80026d0: f040 80b9 bne.w 8002846 <HAL_ADC_Start_DMA+0x192>
|
|
{
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
80026d4: 68fb ldr r3, [r7, #12]
|
|
80026d6: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80026da: 2b01 cmp r3, #1
|
|
80026dc: d101 bne.n 80026e2 <HAL_ADC_Start_DMA+0x2e>
|
|
80026de: 2302 movs r3, #2
|
|
80026e0: e0b4 b.n 800284c <HAL_ADC_Start_DMA+0x198>
|
|
80026e2: 68fb ldr r3, [r7, #12]
|
|
80026e4: 2201 movs r2, #1
|
|
80026e6: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Verification if multimode is disabled (for devices with several ADC) */
|
|
/* If multimode is enabled, dedicated function multimode conversion */
|
|
/* start DMA must be used. */
|
|
if(ADC_COMMON_CCR_MULTI(hadc) == RESET)
|
|
80026ea: 4b5a ldr r3, [pc, #360] @ (8002854 <HAL_ADC_Start_DMA+0x1a0>)
|
|
80026ec: 689b ldr r3, [r3, #8]
|
|
80026ee: f003 031f and.w r3, r3, #31
|
|
80026f2: 2b00 cmp r3, #0
|
|
80026f4: f040 80a0 bne.w 8002838 <HAL_ADC_Start_DMA+0x184>
|
|
{
|
|
/* Enable the ADC peripheral */
|
|
tmp_hal_status = ADC_Enable(hadc);
|
|
80026f8: 68f8 ldr r0, [r7, #12]
|
|
80026fa: f000 fec1 bl 8003480 <ADC_Enable>
|
|
80026fe: 4603 mov r3, r0
|
|
8002700: 75fb strb r3, [r7, #23]
|
|
|
|
/* Start conversion if ADC is effectively enabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
8002702: 7dfb ldrb r3, [r7, #23]
|
|
8002704: 2b00 cmp r3, #0
|
|
8002706: f040 8092 bne.w 800282e <HAL_ADC_Start_DMA+0x17a>
|
|
{
|
|
/* Set ADC state */
|
|
/* - Clear state bitfield related to regular group conversion results */
|
|
/* - Set state bitfield related to regular operation */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
800270a: 68fb ldr r3, [r7, #12]
|
|
800270c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800270e: f423 6370 bic.w r3, r3, #3840 @ 0xf00
|
|
8002712: f023 0301 bic.w r3, r3, #1
|
|
8002716: f443 7280 orr.w r2, r3, #256 @ 0x100
|
|
800271a: 68fb ldr r3, [r7, #12]
|
|
800271c: 641a str r2, [r3, #64] @ 0x40
|
|
HAL_ADC_STATE_REG_BUSY);
|
|
|
|
/* Set group injected state (from auto-injection) and multimode state */
|
|
/* for all cases of multimode: independent mode, multimode ADC master */
|
|
/* or multimode ADC slave (for devices with several ADCs): */
|
|
if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
|
|
800271e: 4b4d ldr r3, [pc, #308] @ (8002854 <HAL_ADC_Start_DMA+0x1a0>)
|
|
8002720: 689b ldr r3, [r3, #8]
|
|
8002722: f003 031f and.w r3, r3, #31
|
|
8002726: 2b00 cmp r3, #0
|
|
8002728: d004 beq.n 8002734 <HAL_ADC_Start_DMA+0x80>
|
|
800272a: 68fb ldr r3, [r7, #12]
|
|
800272c: 681b ldr r3, [r3, #0]
|
|
800272e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8002732: d115 bne.n 8002760 <HAL_ADC_Start_DMA+0xac>
|
|
{
|
|
/* Set ADC state (ADC independent or master) */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
8002734: 68fb ldr r3, [r7, #12]
|
|
8002736: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002738: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
|
|
800273c: 68fb ldr r3, [r7, #12]
|
|
800273e: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* If conversions on group regular are also triggering group injected,*/
|
|
/* update ADC state. */
|
|
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
|
|
8002740: 68fb ldr r3, [r7, #12]
|
|
8002742: 681b ldr r3, [r3, #0]
|
|
8002744: 68db ldr r3, [r3, #12]
|
|
8002746: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800274a: 2b00 cmp r3, #0
|
|
800274c: d027 beq.n 800279e <HAL_ADC_Start_DMA+0xea>
|
|
{
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
|
|
800274e: 68fb ldr r3, [r7, #12]
|
|
8002750: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002752: f423 5340 bic.w r3, r3, #12288 @ 0x3000
|
|
8002756: f443 5280 orr.w r2, r3, #4096 @ 0x1000
|
|
800275a: 68fb ldr r3, [r7, #12]
|
|
800275c: 641a str r2, [r3, #64] @ 0x40
|
|
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
|
|
800275e: e01e b.n 800279e <HAL_ADC_Start_DMA+0xea>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set ADC state (ADC slave) */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
8002760: 68fb ldr r3, [r7, #12]
|
|
8002762: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002764: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
|
|
8002768: 68fb ldr r3, [r7, #12]
|
|
800276a: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* If conversions on group regular are also triggering group injected,*/
|
|
/* update ADC state. */
|
|
if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
|
|
800276c: 68fb ldr r3, [r7, #12]
|
|
800276e: 681b ldr r3, [r3, #0]
|
|
8002770: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8002774: d004 beq.n 8002780 <HAL_ADC_Start_DMA+0xcc>
|
|
8002776: 68fb ldr r3, [r7, #12]
|
|
8002778: 681b ldr r3, [r3, #0]
|
|
800277a: 4a37 ldr r2, [pc, #220] @ (8002858 <HAL_ADC_Start_DMA+0x1a4>)
|
|
800277c: 4293 cmp r3, r2
|
|
800277e: d10e bne.n 800279e <HAL_ADC_Start_DMA+0xea>
|
|
8002780: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
8002784: 68db ldr r3, [r3, #12]
|
|
8002786: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800278a: 2b00 cmp r3, #0
|
|
800278c: d007 beq.n 800279e <HAL_ADC_Start_DMA+0xea>
|
|
{
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
|
|
800278e: 68fb ldr r3, [r7, #12]
|
|
8002790: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002792: f423 5340 bic.w r3, r3, #12288 @ 0x3000
|
|
8002796: f443 5280 orr.w r2, r3, #4096 @ 0x1000
|
|
800279a: 68fb ldr r3, [r7, #12]
|
|
800279c: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
}
|
|
|
|
/* State machine update: Check if an injected conversion is ongoing */
|
|
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
|
|
800279e: 68fb ldr r3, [r7, #12]
|
|
80027a0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80027a2: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80027a6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80027aa: d106 bne.n 80027ba <HAL_ADC_Start_DMA+0x106>
|
|
{
|
|
/* Reset ADC error code fields related to conversions on group regular*/
|
|
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
|
|
80027ac: 68fb ldr r3, [r7, #12]
|
|
80027ae: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80027b0: f023 0206 bic.w r2, r3, #6
|
|
80027b4: 68fb ldr r3, [r7, #12]
|
|
80027b6: 645a str r2, [r3, #68] @ 0x44
|
|
80027b8: e002 b.n 80027c0 <HAL_ADC_Start_DMA+0x10c>
|
|
}
|
|
else
|
|
{
|
|
/* Reset ADC all error code fields */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
80027ba: 68fb ldr r3, [r7, #12]
|
|
80027bc: 2200 movs r2, #0
|
|
80027be: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
80027c0: 68fb ldr r3, [r7, #12]
|
|
80027c2: 2200 movs r2, #0
|
|
80027c4: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
|
|
/* Set the DMA transfer complete callback */
|
|
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
|
|
80027c8: 68fb ldr r3, [r7, #12]
|
|
80027ca: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80027cc: 4a23 ldr r2, [pc, #140] @ (800285c <HAL_ADC_Start_DMA+0x1a8>)
|
|
80027ce: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Set the DMA half transfer complete callback */
|
|
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
|
|
80027d0: 68fb ldr r3, [r7, #12]
|
|
80027d2: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80027d4: 4a22 ldr r2, [pc, #136] @ (8002860 <HAL_ADC_Start_DMA+0x1ac>)
|
|
80027d6: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the DMA error callback */
|
|
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
|
|
80027d8: 68fb ldr r3, [r7, #12]
|
|
80027da: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80027dc: 4a21 ldr r2, [pc, #132] @ (8002864 <HAL_ADC_Start_DMA+0x1b0>)
|
|
80027de: 631a str r2, [r3, #48] @ 0x30
|
|
/* start (in case of SW start): */
|
|
|
|
/* Clear regular group conversion flag and overrun flag */
|
|
/* (To ensure of no unknown state from potential previous ADC */
|
|
/* operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
|
|
80027e0: 68fb ldr r3, [r7, #12]
|
|
80027e2: 681b ldr r3, [r3, #0]
|
|
80027e4: 221c movs r2, #28
|
|
80027e6: 601a str r2, [r3, #0]
|
|
|
|
/* Enable ADC overrun interrupt */
|
|
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
|
|
80027e8: 68fb ldr r3, [r7, #12]
|
|
80027ea: 681b ldr r3, [r3, #0]
|
|
80027ec: 685a ldr r2, [r3, #4]
|
|
80027ee: 68fb ldr r3, [r7, #12]
|
|
80027f0: 681b ldr r3, [r3, #0]
|
|
80027f2: f042 0210 orr.w r2, r2, #16
|
|
80027f6: 605a str r2, [r3, #4]
|
|
|
|
/* Enable ADC DMA mode */
|
|
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
|
|
80027f8: 68fb ldr r3, [r7, #12]
|
|
80027fa: 681b ldr r3, [r3, #0]
|
|
80027fc: 68da ldr r2, [r3, #12]
|
|
80027fe: 68fb ldr r3, [r7, #12]
|
|
8002800: 681b ldr r3, [r3, #0]
|
|
8002802: f042 0201 orr.w r2, r2, #1
|
|
8002806: 60da str r2, [r3, #12]
|
|
|
|
/* Start the DMA channel */
|
|
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
|
|
8002808: 68fb ldr r3, [r7, #12]
|
|
800280a: 6b98 ldr r0, [r3, #56] @ 0x38
|
|
800280c: 68fb ldr r3, [r7, #12]
|
|
800280e: 681b ldr r3, [r3, #0]
|
|
8002810: 3340 adds r3, #64 @ 0x40
|
|
8002812: 4619 mov r1, r3
|
|
8002814: 68ba ldr r2, [r7, #8]
|
|
8002816: 687b ldr r3, [r7, #4]
|
|
8002818: f001 fea4 bl 8004564 <HAL_DMA_Start_IT>
|
|
|
|
/* Enable conversion of regular group. */
|
|
/* If software start has been selected, conversion starts immediately.*/
|
|
/* If external trigger has been selected, conversion will start at */
|
|
/* next trigger event. */
|
|
SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
|
|
800281c: 68fb ldr r3, [r7, #12]
|
|
800281e: 681b ldr r3, [r3, #0]
|
|
8002820: 689a ldr r2, [r3, #8]
|
|
8002822: 68fb ldr r3, [r7, #12]
|
|
8002824: 681b ldr r3, [r3, #0]
|
|
8002826: f042 0204 orr.w r2, r2, #4
|
|
800282a: 609a str r2, [r3, #8]
|
|
800282c: e00d b.n 800284a <HAL_ADC_Start_DMA+0x196>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
800282e: 68fb ldr r3, [r7, #12]
|
|
8002830: 2200 movs r2, #0
|
|
8002832: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
8002836: e008 b.n 800284a <HAL_ADC_Start_DMA+0x196>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_ERROR;
|
|
8002838: 2301 movs r3, #1
|
|
800283a: 75fb strb r3, [r7, #23]
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
800283c: 68fb ldr r3, [r7, #12]
|
|
800283e: 2200 movs r2, #0
|
|
8002840: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
8002844: e001 b.n 800284a <HAL_ADC_Start_DMA+0x196>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_BUSY;
|
|
8002846: 2302 movs r3, #2
|
|
8002848: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
800284a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800284c: 4618 mov r0, r3
|
|
800284e: 3718 adds r7, #24
|
|
8002850: 46bd mov sp, r7
|
|
8002852: bd80 pop {r7, pc}
|
|
8002854: 50000300 .word 0x50000300
|
|
8002858: 50000100 .word 0x50000100
|
|
800285c: 080033b5 .word 0x080033b5
|
|
8002860: 0800342f .word 0x0800342f
|
|
8002864: 0800344b .word 0x0800344b
|
|
|
|
08002868 <HAL_ADC_IRQHandler>:
|
|
* @brief Handles ADC interrupt request.
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002868: b580 push {r7, lr}
|
|
800286a: b088 sub sp, #32
|
|
800286c: af00 add r7, sp, #0
|
|
800286e: 6078 str r0, [r7, #4]
|
|
uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */
|
|
8002870: 2300 movs r3, #0
|
|
8002872: 61fb str r3, [r7, #28]
|
|
ADC_Common_TypeDef *tmpADC_Common;
|
|
uint32_t tmp_cfgr = 0x0U;
|
|
8002874: 2300 movs r3, #0
|
|
8002876: 61bb str r3, [r7, #24]
|
|
uint32_t tmp_cfgr_jqm = 0x0U;
|
|
8002878: 2300 movs r3, #0
|
|
800287a: 617b str r3, [r7, #20]
|
|
uint32_t tmp_isr = hadc->Instance->ISR;
|
|
800287c: 687b ldr r3, [r7, #4]
|
|
800287e: 681b ldr r3, [r3, #0]
|
|
8002880: 681b ldr r3, [r3, #0]
|
|
8002882: 613b str r3, [r7, #16]
|
|
uint32_t tmp_ier = hadc->Instance->IER;
|
|
8002884: 687b ldr r3, [r7, #4]
|
|
8002886: 681b ldr r3, [r3, #0]
|
|
8002888: 685b ldr r3, [r3, #4]
|
|
800288a: 60fb str r3, [r7, #12]
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
|
|
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
|
|
|
|
/* ========== Check End of Conversion flag for regular group ========== */
|
|
if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
|
|
800288c: 693b ldr r3, [r7, #16]
|
|
800288e: f003 0304 and.w r3, r3, #4
|
|
8002892: 2b00 cmp r3, #0
|
|
8002894: d004 beq.n 80028a0 <HAL_ADC_IRQHandler+0x38>
|
|
8002896: 68fb ldr r3, [r7, #12]
|
|
8002898: f003 0304 and.w r3, r3, #4
|
|
800289c: 2b00 cmp r3, #0
|
|
800289e: d109 bne.n 80028b4 <HAL_ADC_IRQHandler+0x4c>
|
|
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
|
|
80028a0: 693b ldr r3, [r7, #16]
|
|
80028a2: f003 0308 and.w r3, r3, #8
|
|
if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
|
|
80028a6: 2b00 cmp r3, #0
|
|
80028a8: d076 beq.n 8002998 <HAL_ADC_IRQHandler+0x130>
|
|
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) )
|
|
80028aa: 68fb ldr r3, [r7, #12]
|
|
80028ac: f003 0308 and.w r3, r3, #8
|
|
80028b0: 2b00 cmp r3, #0
|
|
80028b2: d071 beq.n 8002998 <HAL_ADC_IRQHandler+0x130>
|
|
{
|
|
/* Update state machine on conversion status if not in error state */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
|
|
80028b4: 687b ldr r3, [r7, #4]
|
|
80028b6: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80028b8: f003 0310 and.w r3, r3, #16
|
|
80028bc: 2b00 cmp r3, #0
|
|
80028be: d105 bne.n 80028cc <HAL_ADC_IRQHandler+0x64>
|
|
{
|
|
/* Set ADC state */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
|
|
80028c0: 687b ldr r3, [r7, #4]
|
|
80028c2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80028c4: f443 7200 orr.w r2, r3, #512 @ 0x200
|
|
80028c8: 687b ldr r3, [r7, #4]
|
|
80028ca: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
|
|
/* Get relevant register CFGR in ADC instance of ADC master or slave */
|
|
/* in function of multimode state (for devices with multimode */
|
|
/* available). */
|
|
if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
|
|
80028cc: 4b82 ldr r3, [pc, #520] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
80028ce: 689b ldr r3, [r3, #8]
|
|
80028d0: f003 031f and.w r3, r3, #31
|
|
80028d4: 2b00 cmp r3, #0
|
|
80028d6: d010 beq.n 80028fa <HAL_ADC_IRQHandler+0x92>
|
|
80028d8: 4b7f ldr r3, [pc, #508] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
80028da: 689b ldr r3, [r3, #8]
|
|
80028dc: f003 031f and.w r3, r3, #31
|
|
80028e0: 2b05 cmp r3, #5
|
|
80028e2: d00a beq.n 80028fa <HAL_ADC_IRQHandler+0x92>
|
|
80028e4: 4b7c ldr r3, [pc, #496] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
80028e6: 689b ldr r3, [r3, #8]
|
|
80028e8: f003 031f and.w r3, r3, #31
|
|
80028ec: 2b09 cmp r3, #9
|
|
80028ee: d004 beq.n 80028fa <HAL_ADC_IRQHandler+0x92>
|
|
80028f0: 687b ldr r3, [r7, #4]
|
|
80028f2: 681b ldr r3, [r3, #0]
|
|
80028f4: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
80028f8: d104 bne.n 8002904 <HAL_ADC_IRQHandler+0x9c>
|
|
{
|
|
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
|
80028fa: 687b ldr r3, [r7, #4]
|
|
80028fc: 681b ldr r3, [r3, #0]
|
|
80028fe: 68db ldr r3, [r3, #12]
|
|
8002900: 61bb str r3, [r7, #24]
|
|
8002902: e003 b.n 800290c <HAL_ADC_IRQHandler+0xa4>
|
|
}
|
|
else
|
|
{
|
|
tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
|
|
8002904: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
8002908: 68db ldr r3, [r3, #12]
|
|
800290a: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
/* Disable interruption if no further conversion upcoming by regular */
|
|
/* external trigger or by continuous mode, */
|
|
/* and if scan sequence if completed. */
|
|
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
|
|
800290c: 687b ldr r3, [r7, #4]
|
|
800290e: 681b ldr r3, [r3, #0]
|
|
8002910: 68db ldr r3, [r3, #12]
|
|
8002912: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
8002916: 2b00 cmp r3, #0
|
|
8002918: d137 bne.n 800298a <HAL_ADC_IRQHandler+0x122>
|
|
(READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) )
|
|
800291a: 69bb ldr r3, [r7, #24]
|
|
800291c: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
|
|
8002920: 2b00 cmp r3, #0
|
|
8002922: d132 bne.n 800298a <HAL_ADC_IRQHandler+0x122>
|
|
{
|
|
/* If End of Sequence is reached, disable interrupts */
|
|
if((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS)
|
|
8002924: 693b ldr r3, [r7, #16]
|
|
8002926: f003 0308 and.w r3, r3, #8
|
|
800292a: 2b00 cmp r3, #0
|
|
800292c: d02d beq.n 800298a <HAL_ADC_IRQHandler+0x122>
|
|
{
|
|
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
|
|
/* ADSTART==0 (no conversion on going) */
|
|
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
|
|
800292e: 687b ldr r3, [r7, #4]
|
|
8002930: 681b ldr r3, [r3, #0]
|
|
8002932: 689b ldr r3, [r3, #8]
|
|
8002934: f003 0304 and.w r3, r3, #4
|
|
8002938: 2b00 cmp r3, #0
|
|
800293a: d11a bne.n 8002972 <HAL_ADC_IRQHandler+0x10a>
|
|
{
|
|
/* Disable ADC end of sequence conversion interrupt */
|
|
/* Note: Overrun interrupt was enabled with EOC interrupt in */
|
|
/* HAL_Start_IT(), but is not disabled here because can be used */
|
|
/* by overrun IRQ process below. */
|
|
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
|
|
800293c: 687b ldr r3, [r7, #4]
|
|
800293e: 681b ldr r3, [r3, #0]
|
|
8002940: 685a ldr r2, [r3, #4]
|
|
8002942: 687b ldr r3, [r7, #4]
|
|
8002944: 681b ldr r3, [r3, #0]
|
|
8002946: f022 020c bic.w r2, r2, #12
|
|
800294a: 605a str r2, [r3, #4]
|
|
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
800294c: 687b ldr r3, [r7, #4]
|
|
800294e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002950: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
8002954: 687b ldr r3, [r7, #4]
|
|
8002956: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
|
|
8002958: 687b ldr r3, [r7, #4]
|
|
800295a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800295c: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8002960: 2b00 cmp r3, #0
|
|
8002962: d112 bne.n 800298a <HAL_ADC_IRQHandler+0x122>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
|
8002964: 687b ldr r3, [r7, #4]
|
|
8002966: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002968: f043 0201 orr.w r2, r3, #1
|
|
800296c: 687b ldr r3, [r7, #4]
|
|
800296e: 641a str r2, [r3, #64] @ 0x40
|
|
8002970: e00b b.n 800298a <HAL_ADC_IRQHandler+0x122>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002972: 687b ldr r3, [r7, #4]
|
|
8002974: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002976: f043 0210 orr.w r2, r3, #16
|
|
800297a: 687b ldr r3, [r7, #4]
|
|
800297c: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
800297e: 687b ldr r3, [r7, #4]
|
|
8002980: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002982: f043 0201 orr.w r2, r3, #1
|
|
8002986: 687b ldr r3, [r7, #4]
|
|
8002988: 645a str r2, [r3, #68] @ 0x44
|
|
/* from EOC or EOS, possibility to use: */
|
|
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
hadc->ConvCpltCallback(hadc);
|
|
#else
|
|
HAL_ADC_ConvCpltCallback(hadc);
|
|
800298a: 6878 ldr r0, [r7, #4]
|
|
800298c: f7fe faa0 bl 8000ed0 <HAL_ADC_ConvCpltCallback>
|
|
/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
|
|
/* conversion flags clear induces the release of the preserved */
|
|
/* data. */
|
|
/* Therefore, if the preserved data value is needed, it must be */
|
|
/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
|
|
8002990: 687b ldr r3, [r7, #4]
|
|
8002992: 681b ldr r3, [r3, #0]
|
|
8002994: 220c movs r2, #12
|
|
8002996: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
|
|
/* ========== Check End of Conversion flag for injected group ========== */
|
|
if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
|
|
8002998: 693b ldr r3, [r7, #16]
|
|
800299a: f003 0320 and.w r3, r3, #32
|
|
800299e: 2b00 cmp r3, #0
|
|
80029a0: d004 beq.n 80029ac <HAL_ADC_IRQHandler+0x144>
|
|
80029a2: 68fb ldr r3, [r7, #12]
|
|
80029a4: f003 0320 and.w r3, r3, #32
|
|
80029a8: 2b00 cmp r3, #0
|
|
80029aa: d10b bne.n 80029c4 <HAL_ADC_IRQHandler+0x15c>
|
|
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
|
|
80029ac: 693b ldr r3, [r7, #16]
|
|
80029ae: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
|
|
80029b2: 2b00 cmp r3, #0
|
|
80029b4: f000 80a5 beq.w 8002b02 <HAL_ADC_IRQHandler+0x29a>
|
|
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) )
|
|
80029b8: 68fb ldr r3, [r7, #12]
|
|
80029ba: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80029be: 2b00 cmp r3, #0
|
|
80029c0: f000 809f beq.w 8002b02 <HAL_ADC_IRQHandler+0x29a>
|
|
{
|
|
/* Set ADC state */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
|
|
80029c4: 687b ldr r3, [r7, #4]
|
|
80029c6: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80029c8: f443 5200 orr.w r2, r3, #8192 @ 0x2000
|
|
80029cc: 687b ldr r3, [r7, #4]
|
|
80029ce: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Get relevant register CFGR in ADC instance of ADC master or slave */
|
|
/* in function of multimode state (for devices with multimode */
|
|
/* available). */
|
|
if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc))
|
|
80029d0: 4b41 ldr r3, [pc, #260] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
80029d2: 689b ldr r3, [r3, #8]
|
|
80029d4: f003 031f and.w r3, r3, #31
|
|
80029d8: 2b00 cmp r3, #0
|
|
80029da: d010 beq.n 80029fe <HAL_ADC_IRQHandler+0x196>
|
|
80029dc: 4b3e ldr r3, [pc, #248] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
80029de: 689b ldr r3, [r3, #8]
|
|
80029e0: f003 031f and.w r3, r3, #31
|
|
80029e4: 2b05 cmp r3, #5
|
|
80029e6: d00a beq.n 80029fe <HAL_ADC_IRQHandler+0x196>
|
|
80029e8: 4b3b ldr r3, [pc, #236] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
80029ea: 689b ldr r3, [r3, #8]
|
|
80029ec: f003 031f and.w r3, r3, #31
|
|
80029f0: 2b09 cmp r3, #9
|
|
80029f2: d004 beq.n 80029fe <HAL_ADC_IRQHandler+0x196>
|
|
80029f4: 687b ldr r3, [r7, #4]
|
|
80029f6: 681b ldr r3, [r3, #0]
|
|
80029f8: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
80029fc: d104 bne.n 8002a08 <HAL_ADC_IRQHandler+0x1a0>
|
|
{
|
|
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
|
80029fe: 687b ldr r3, [r7, #4]
|
|
8002a00: 681b ldr r3, [r3, #0]
|
|
8002a02: 68db ldr r3, [r3, #12]
|
|
8002a04: 61bb str r3, [r7, #24]
|
|
8002a06: e003 b.n 8002a10 <HAL_ADC_IRQHandler+0x1a8>
|
|
}
|
|
else
|
|
{
|
|
tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
|
|
8002a08: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
8002a0c: 68db ldr r3, [r3, #12]
|
|
8002a0e: 61bb str r3, [r7, #24]
|
|
/* Disable interruption if no further conversion upcoming by injected */
|
|
/* external trigger or by automatic injected conversion with regular */
|
|
/* group having no further conversion upcoming (same conditions as */
|
|
/* regular group interruption disabling above), */
|
|
/* and if injected scan sequence is completed. */
|
|
if(ADC_IS_SOFTWARE_START_INJECTED(hadc))
|
|
8002a10: 687b ldr r3, [r7, #4]
|
|
8002a12: 681b ldr r3, [r3, #0]
|
|
8002a14: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8002a16: f003 03c0 and.w r3, r3, #192 @ 0xc0
|
|
8002a1a: 2b00 cmp r3, #0
|
|
8002a1c: d16a bne.n 8002af4 <HAL_ADC_IRQHandler+0x28c>
|
|
{
|
|
if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) ||
|
|
8002a1e: 69bb ldr r3, [r7, #24]
|
|
8002a20: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002a24: 2b00 cmp r3, #0
|
|
8002a26: d00b beq.n 8002a40 <HAL_ADC_IRQHandler+0x1d8>
|
|
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
|
|
8002a28: 687b ldr r3, [r7, #4]
|
|
8002a2a: 681b ldr r3, [r3, #0]
|
|
8002a2c: 68db ldr r3, [r3, #12]
|
|
8002a2e: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
if((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) ||
|
|
8002a32: 2b00 cmp r3, #0
|
|
8002a34: d15e bne.n 8002af4 <HAL_ADC_IRQHandler+0x28c>
|
|
(READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) )
|
|
8002a36: 69bb ldr r3, [r7, #24]
|
|
8002a38: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
|
|
8002a3c: 2b00 cmp r3, #0
|
|
8002a3e: d159 bne.n 8002af4 <HAL_ADC_IRQHandler+0x28c>
|
|
{
|
|
/* If End of Sequence is reached, disable interrupts */
|
|
if((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS)
|
|
8002a40: 693b ldr r3, [r7, #16]
|
|
8002a42: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002a46: 2b00 cmp r3, #0
|
|
8002a48: d054 beq.n 8002af4 <HAL_ADC_IRQHandler+0x28c>
|
|
{
|
|
|
|
/* Get relevant register CFGR in ADC instance of ADC master or slave */
|
|
/* in function of multimode state (for devices with multimode */
|
|
/* available). */
|
|
if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc))
|
|
8002a4a: 4b23 ldr r3, [pc, #140] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
8002a4c: 689b ldr r3, [r3, #8]
|
|
8002a4e: f003 031f and.w r3, r3, #31
|
|
8002a52: 2b00 cmp r3, #0
|
|
8002a54: d010 beq.n 8002a78 <HAL_ADC_IRQHandler+0x210>
|
|
8002a56: 4b20 ldr r3, [pc, #128] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
8002a58: 689b ldr r3, [r3, #8]
|
|
8002a5a: f003 031f and.w r3, r3, #31
|
|
8002a5e: 2b06 cmp r3, #6
|
|
8002a60: d00a beq.n 8002a78 <HAL_ADC_IRQHandler+0x210>
|
|
8002a62: 4b1d ldr r3, [pc, #116] @ (8002ad8 <HAL_ADC_IRQHandler+0x270>)
|
|
8002a64: 689b ldr r3, [r3, #8]
|
|
8002a66: f003 031f and.w r3, r3, #31
|
|
8002a6a: 2b07 cmp r3, #7
|
|
8002a6c: d004 beq.n 8002a78 <HAL_ADC_IRQHandler+0x210>
|
|
8002a6e: 687b ldr r3, [r7, #4]
|
|
8002a70: 681b ldr r3, [r3, #0]
|
|
8002a72: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8002a76: d104 bne.n 8002a82 <HAL_ADC_IRQHandler+0x21a>
|
|
{
|
|
tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR);
|
|
8002a78: 687b ldr r3, [r7, #4]
|
|
8002a7a: 681b ldr r3, [r3, #0]
|
|
8002a7c: 68db ldr r3, [r3, #12]
|
|
8002a7e: 617b str r3, [r7, #20]
|
|
8002a80: e003 b.n 8002a8a <HAL_ADC_IRQHandler+0x222>
|
|
}
|
|
else
|
|
{
|
|
tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR);
|
|
8002a82: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
8002a86: 68db ldr r3, [r3, #12]
|
|
8002a88: 617b str r3, [r7, #20]
|
|
/* when the last context has been fully processed, JSQR is reset */
|
|
/* by the hardware. Even if no injected conversion is planned to come */
|
|
/* (queue empty, triggers are ignored), it can start again */
|
|
/* immediately after setting a new context (JADSTART is still set). */
|
|
/* Therefore, state of HAL ADC injected group is kept to busy. */
|
|
if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET)
|
|
8002a8a: 697b ldr r3, [r7, #20]
|
|
8002a8c: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8002a90: 2b00 cmp r3, #0
|
|
8002a92: d12f bne.n 8002af4 <HAL_ADC_IRQHandler+0x28c>
|
|
{
|
|
/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
|
|
/* JADSTART==0 (no conversion on going) */
|
|
if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
|
|
8002a94: 687b ldr r3, [r7, #4]
|
|
8002a96: 681b ldr r3, [r3, #0]
|
|
8002a98: 689b ldr r3, [r3, #8]
|
|
8002a9a: f003 0308 and.w r3, r3, #8
|
|
8002a9e: 2b00 cmp r3, #0
|
|
8002aa0: d11c bne.n 8002adc <HAL_ADC_IRQHandler+0x274>
|
|
{
|
|
/* Disable ADC end of sequence conversion interrupt */
|
|
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
|
|
8002aa2: 687b ldr r3, [r7, #4]
|
|
8002aa4: 681b ldr r3, [r3, #0]
|
|
8002aa6: 685a ldr r2, [r3, #4]
|
|
8002aa8: 687b ldr r3, [r7, #4]
|
|
8002aaa: 681b ldr r3, [r3, #0]
|
|
8002aac: f022 0260 bic.w r2, r2, #96 @ 0x60
|
|
8002ab0: 605a str r2, [r3, #4]
|
|
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
|
8002ab2: 687b ldr r3, [r7, #4]
|
|
8002ab4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002ab6: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
8002aba: 687b ldr r3, [r7, #4]
|
|
8002abc: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
|
|
8002abe: 687b ldr r3, [r7, #4]
|
|
8002ac0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002ac2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002ac6: 2b00 cmp r3, #0
|
|
8002ac8: d114 bne.n 8002af4 <HAL_ADC_IRQHandler+0x28c>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
|
8002aca: 687b ldr r3, [r7, #4]
|
|
8002acc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002ace: f043 0201 orr.w r2, r3, #1
|
|
8002ad2: 687b ldr r3, [r7, #4]
|
|
8002ad4: 641a str r2, [r3, #64] @ 0x40
|
|
8002ad6: e00d b.n 8002af4 <HAL_ADC_IRQHandler+0x28c>
|
|
8002ad8: 50000300 .word 0x50000300
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002adc: 687b ldr r3, [r7, #4]
|
|
8002ade: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002ae0: f043 0210 orr.w r2, r3, #16
|
|
8002ae4: 687b ldr r3, [r7, #4]
|
|
8002ae6: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002ae8: 687b ldr r3, [r7, #4]
|
|
8002aea: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002aec: f043 0201 orr.w r2, r3, #1
|
|
8002af0: 687b ldr r3, [r7, #4]
|
|
8002af2: 645a str r2, [r3, #68] @ 0x44
|
|
/* from JEOC or JEOS, possibility to use: */
|
|
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
hadc->InjectedConvCpltCallback(hadc);
|
|
#else
|
|
HAL_ADCEx_InjectedConvCpltCallback(hadc);
|
|
8002af4: 6878 ldr r0, [r7, #4]
|
|
8002af6: f000 f8b1 bl 8002c5c <HAL_ADCEx_InjectedConvCpltCallback>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
|
|
/* Clear injected group conversion flag */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
|
|
8002afa: 687b ldr r3, [r7, #4]
|
|
8002afc: 681b ldr r3, [r3, #0]
|
|
8002afe: 2260 movs r2, #96 @ 0x60
|
|
8002b00: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* ========== Check analog watchdog 1 flag ========== */
|
|
if(((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
|
|
8002b02: 693b ldr r3, [r7, #16]
|
|
8002b04: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002b08: 2b00 cmp r3, #0
|
|
8002b0a: d011 beq.n 8002b30 <HAL_ADC_IRQHandler+0x2c8>
|
|
8002b0c: 68fb ldr r3, [r7, #12]
|
|
8002b0e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002b12: 2b00 cmp r3, #0
|
|
8002b14: d00c beq.n 8002b30 <HAL_ADC_IRQHandler+0x2c8>
|
|
{
|
|
/* Set ADC state */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
|
|
8002b16: 687b ldr r3, [r7, #4]
|
|
8002b18: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002b1a: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8002b1e: 687b ldr r3, [r7, #4]
|
|
8002b20: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Level out of window 1 callback */
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
hadc->LevelOutOfWindowCallback(hadc);
|
|
#else
|
|
HAL_ADC_LevelOutOfWindowCallback(hadc);
|
|
8002b22: 6878 ldr r0, [r7, #4]
|
|
8002b24: f7ff fc20 bl 8002368 <HAL_ADC_LevelOutOfWindowCallback>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
/* Clear ADC analog watchdog flag */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
|
|
8002b28: 687b ldr r3, [r7, #4]
|
|
8002b2a: 681b ldr r3, [r3, #0]
|
|
8002b2c: 2280 movs r2, #128 @ 0x80
|
|
8002b2e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* ========== Check analog watchdog 2 flag ========== */
|
|
if(((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
|
|
8002b30: 693b ldr r3, [r7, #16]
|
|
8002b32: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002b36: 2b00 cmp r3, #0
|
|
8002b38: d012 beq.n 8002b60 <HAL_ADC_IRQHandler+0x2f8>
|
|
8002b3a: 68fb ldr r3, [r7, #12]
|
|
8002b3c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002b40: 2b00 cmp r3, #0
|
|
8002b42: d00d beq.n 8002b60 <HAL_ADC_IRQHandler+0x2f8>
|
|
{
|
|
/* Set ADC state */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
|
|
8002b44: 687b ldr r3, [r7, #4]
|
|
8002b46: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002b48: f443 3200 orr.w r2, r3, #131072 @ 0x20000
|
|
8002b4c: 687b ldr r3, [r7, #4]
|
|
8002b4e: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Level out of window 2 callback */
|
|
HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
|
|
8002b50: 6878 ldr r0, [r7, #4]
|
|
8002b52: f000 f897 bl 8002c84 <HAL_ADCEx_LevelOutOfWindow2Callback>
|
|
/* Clear ADC analog watchdog flag */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
|
|
8002b56: 687b ldr r3, [r7, #4]
|
|
8002b58: 681b ldr r3, [r3, #0]
|
|
8002b5a: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8002b5e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* ========== Check analog watchdog 3 flag ========== */
|
|
if(((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
|
|
8002b60: 693b ldr r3, [r7, #16]
|
|
8002b62: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8002b66: 2b00 cmp r3, #0
|
|
8002b68: d012 beq.n 8002b90 <HAL_ADC_IRQHandler+0x328>
|
|
8002b6a: 68fb ldr r3, [r7, #12]
|
|
8002b6c: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8002b70: 2b00 cmp r3, #0
|
|
8002b72: d00d beq.n 8002b90 <HAL_ADC_IRQHandler+0x328>
|
|
{
|
|
/* Set ADC state */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
|
|
8002b74: 687b ldr r3, [r7, #4]
|
|
8002b76: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002b78: f443 2280 orr.w r2, r3, #262144 @ 0x40000
|
|
8002b7c: 687b ldr r3, [r7, #4]
|
|
8002b7e: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Level out of window 3 callback */
|
|
HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
|
|
8002b80: 6878 ldr r0, [r7, #4]
|
|
8002b82: f000 f889 bl 8002c98 <HAL_ADCEx_LevelOutOfWindow3Callback>
|
|
/* Clear ADC analog watchdog flag */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
|
|
8002b86: 687b ldr r3, [r7, #4]
|
|
8002b88: 681b ldr r3, [r3, #0]
|
|
8002b8a: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8002b8e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* ========== Check Overrun flag ========== */
|
|
if(((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
|
|
8002b90: 693b ldr r3, [r7, #16]
|
|
8002b92: f003 0310 and.w r3, r3, #16
|
|
8002b96: 2b00 cmp r3, #0
|
|
8002b98: d03b beq.n 8002c12 <HAL_ADC_IRQHandler+0x3aa>
|
|
8002b9a: 68fb ldr r3, [r7, #12]
|
|
8002b9c: f003 0310 and.w r3, r3, #16
|
|
8002ba0: 2b00 cmp r3, #0
|
|
8002ba2: d036 beq.n 8002c12 <HAL_ADC_IRQHandler+0x3aa>
|
|
/* overrun event is not considered as an error. */
|
|
/* (cf ref manual "Managing conversions without using the DMA and */
|
|
/* without overrun ") */
|
|
/* Exception for usage with DMA overrun event always considered as an */
|
|
/* error. */
|
|
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
|
|
8002ba4: 687b ldr r3, [r7, #4]
|
|
8002ba6: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8002ba8: 2b01 cmp r3, #1
|
|
8002baa: d102 bne.n 8002bb2 <HAL_ADC_IRQHandler+0x34a>
|
|
{
|
|
overrun_error = 1U;
|
|
8002bac: 2301 movs r3, #1
|
|
8002bae: 61fb str r3, [r7, #28]
|
|
8002bb0: e019 b.n 8002be6 <HAL_ADC_IRQHandler+0x37e>
|
|
else
|
|
{
|
|
/* Pointer to the common control register to which is belonging hadc */
|
|
/* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
|
|
/* control registers) */
|
|
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
|
|
8002bb2: 4b29 ldr r3, [pc, #164] @ (8002c58 <HAL_ADC_IRQHandler+0x3f0>)
|
|
8002bb4: 60bb str r3, [r7, #8]
|
|
|
|
/* Check DMA configuration, depending on MultiMode set or not */
|
|
if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT)
|
|
8002bb6: 68bb ldr r3, [r7, #8]
|
|
8002bb8: 689b ldr r3, [r3, #8]
|
|
8002bba: f003 031f and.w r3, r3, #31
|
|
8002bbe: 2b00 cmp r3, #0
|
|
8002bc0: d109 bne.n 8002bd6 <HAL_ADC_IRQHandler+0x36e>
|
|
{
|
|
if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
|
|
8002bc2: 687b ldr r3, [r7, #4]
|
|
8002bc4: 681b ldr r3, [r3, #0]
|
|
8002bc6: 68db ldr r3, [r3, #12]
|
|
8002bc8: f003 0301 and.w r3, r3, #1
|
|
8002bcc: 2b01 cmp r3, #1
|
|
8002bce: d10a bne.n 8002be6 <HAL_ADC_IRQHandler+0x37e>
|
|
{
|
|
overrun_error = 1U;
|
|
8002bd0: 2301 movs r3, #1
|
|
8002bd2: 61fb str r3, [r7, #28]
|
|
8002bd4: e007 b.n 8002be6 <HAL_ADC_IRQHandler+0x37e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* MultiMode is enabled, Common Control Register MDMA bits must be checked */
|
|
if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET)
|
|
8002bd6: 68bb ldr r3, [r7, #8]
|
|
8002bd8: 689b ldr r3, [r3, #8]
|
|
8002bda: f403 4340 and.w r3, r3, #49152 @ 0xc000
|
|
8002bde: 2b00 cmp r3, #0
|
|
8002be0: d001 beq.n 8002be6 <HAL_ADC_IRQHandler+0x37e>
|
|
{
|
|
overrun_error = 1U;
|
|
8002be2: 2301 movs r3, #1
|
|
8002be4: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
}
|
|
|
|
if (overrun_error == 1U)
|
|
8002be6: 69fb ldr r3, [r7, #28]
|
|
8002be8: 2b01 cmp r3, #1
|
|
8002bea: d10e bne.n 8002c0a <HAL_ADC_IRQHandler+0x3a2>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
|
|
8002bec: 687b ldr r3, [r7, #4]
|
|
8002bee: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002bf0: f443 6280 orr.w r2, r3, #1024 @ 0x400
|
|
8002bf4: 687b ldr r3, [r7, #4]
|
|
8002bf6: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
|
|
8002bf8: 687b ldr r3, [r7, #4]
|
|
8002bfa: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002bfc: f043 0202 orr.w r2, r3, #2
|
|
8002c00: 687b ldr r3, [r7, #4]
|
|
8002c02: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Error callback */
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
hadc->ErrorCallback(hadc);
|
|
#else
|
|
HAL_ADC_ErrorCallback(hadc);
|
|
8002c04: 6878 ldr r0, [r7, #4]
|
|
8002c06: f7ff fbb9 bl 800237c <HAL_ADC_ErrorCallback>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Clear the Overrun flag */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
|
|
8002c0a: 687b ldr r3, [r7, #4]
|
|
8002c0c: 681b ldr r3, [r3, #0]
|
|
8002c0e: 2210 movs r2, #16
|
|
8002c10: 601a str r2, [r3, #0]
|
|
|
|
}
|
|
|
|
|
|
/* ========== Check Injected context queue overflow flag ========== */
|
|
if(((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
|
|
8002c12: 693b ldr r3, [r7, #16]
|
|
8002c14: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002c18: 2b00 cmp r3, #0
|
|
8002c1a: d018 beq.n 8002c4e <HAL_ADC_IRQHandler+0x3e6>
|
|
8002c1c: 68fb ldr r3, [r7, #12]
|
|
8002c1e: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002c22: 2b00 cmp r3, #0
|
|
8002c24: d013 beq.n 8002c4e <HAL_ADC_IRQHandler+0x3e6>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
|
|
8002c26: 687b ldr r3, [r7, #4]
|
|
8002c28: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002c2a: f443 4280 orr.w r2, r3, #16384 @ 0x4000
|
|
8002c2e: 687b ldr r3, [r7, #4]
|
|
8002c30: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
|
|
8002c32: 687b ldr r3, [r7, #4]
|
|
8002c34: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8002c36: f043 0208 orr.w r2, r3, #8
|
|
8002c3a: 687b ldr r3, [r7, #4]
|
|
8002c3c: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Clear the Injected context queue overflow flag */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
|
|
8002c3e: 687b ldr r3, [r7, #4]
|
|
8002c40: 681b ldr r3, [r3, #0]
|
|
8002c42: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8002c46: 601a str r2, [r3, #0]
|
|
|
|
/* Error callback */
|
|
HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
|
|
8002c48: 6878 ldr r0, [r7, #4]
|
|
8002c4a: f000 f811 bl 8002c70 <HAL_ADCEx_InjectedQueueOverflowCallback>
|
|
}
|
|
|
|
}
|
|
8002c4e: bf00 nop
|
|
8002c50: 3720 adds r7, #32
|
|
8002c52: 46bd mov sp, r7
|
|
8002c54: bd80 pop {r7, pc}
|
|
8002c56: bf00 nop
|
|
8002c58: 50000300 .word 0x50000300
|
|
|
|
08002c5c <HAL_ADCEx_InjectedConvCpltCallback>:
|
|
* @brief Injected conversion complete callback in non blocking mode
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002c5c: b480 push {r7}
|
|
8002c5e: b083 sub sp, #12
|
|
8002c60: af00 add r7, sp, #0
|
|
8002c62: 6078 str r0, [r7, #4]
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8002c64: bf00 nop
|
|
8002c66: 370c adds r7, #12
|
|
8002c68: 46bd mov sp, r7
|
|
8002c6a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002c6e: 4770 bx lr
|
|
|
|
08002c70 <HAL_ADCEx_InjectedQueueOverflowCallback>:
|
|
contexts).
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002c70: b480 push {r7}
|
|
8002c72: b083 sub sp, #12
|
|
8002c74: af00 add r7, sp, #0
|
|
8002c76: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
|
|
in the user file.
|
|
*/
|
|
}
|
|
8002c78: bf00 nop
|
|
8002c7a: 370c adds r7, #12
|
|
8002c7c: 46bd mov sp, r7
|
|
8002c7e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002c82: 4770 bx lr
|
|
|
|
08002c84 <HAL_ADCEx_LevelOutOfWindow2Callback>:
|
|
* @brief Analog watchdog 2 callback in non blocking mode.
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002c84: b480 push {r7}
|
|
8002c86: b083 sub sp, #12
|
|
8002c88: af00 add r7, sp, #0
|
|
8002c8a: 6078 str r0, [r7, #4]
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file.
|
|
*/
|
|
}
|
|
8002c8c: bf00 nop
|
|
8002c8e: 370c adds r7, #12
|
|
8002c90: 46bd mov sp, r7
|
|
8002c92: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002c96: 4770 bx lr
|
|
|
|
08002c98 <HAL_ADCEx_LevelOutOfWindow3Callback>:
|
|
* @brief Analog watchdog 3 callback in non blocking mode.
|
|
* @param hadc ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002c98: b480 push {r7}
|
|
8002c9a: b083 sub sp, #12
|
|
8002c9c: af00 add r7, sp, #0
|
|
8002c9e: 6078 str r0, [r7, #4]
|
|
UNUSED(hadc);
|
|
|
|
/* NOTE : This function should not be modified. When the callback is needed,
|
|
function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file.
|
|
*/
|
|
}
|
|
8002ca0: bf00 nop
|
|
8002ca2: 370c adds r7, #12
|
|
8002ca4: 46bd mov sp, r7
|
|
8002ca6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002caa: 4770 bx lr
|
|
|
|
08002cac <HAL_ADC_ConfigChannel>:
|
|
* @param hadc ADC handle
|
|
* @param sConfig Structure ADC channel for regular group.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
|
|
{
|
|
8002cac: b480 push {r7}
|
|
8002cae: b09b sub sp, #108 @ 0x6c
|
|
8002cb0: af00 add r7, sp, #0
|
|
8002cb2: 6078 str r0, [r7, #4]
|
|
8002cb4: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8002cb6: 2300 movs r3, #0
|
|
8002cb8: f887 3067 strb.w r3, [r7, #103] @ 0x67
|
|
ADC_Common_TypeDef *tmpADC_Common;
|
|
ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
|
|
uint32_t tmpOffsetShifted;
|
|
__IO uint32_t wait_loop_index = 0U;
|
|
8002cbc: 2300 movs r3, #0
|
|
8002cbe: 60bb str r3, [r7, #8]
|
|
{
|
|
assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8002cc0: 687b ldr r3, [r7, #4]
|
|
8002cc2: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8002cc6: 2b01 cmp r3, #1
|
|
8002cc8: d101 bne.n 8002cce <HAL_ADC_ConfigChannel+0x22>
|
|
8002cca: 2302 movs r3, #2
|
|
8002ccc: e2a1 b.n 8003212 <HAL_ADC_ConfigChannel+0x566>
|
|
8002cce: 687b ldr r3, [r7, #4]
|
|
8002cd0: 2201 movs r2, #1
|
|
8002cd2: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Channel number */
|
|
/* - Channel rank */
|
|
if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
|
|
8002cd6: 687b ldr r3, [r7, #4]
|
|
8002cd8: 681b ldr r3, [r3, #0]
|
|
8002cda: 689b ldr r3, [r3, #8]
|
|
8002cdc: f003 0304 and.w r3, r3, #4
|
|
8002ce0: 2b00 cmp r3, #0
|
|
8002ce2: f040 8285 bne.w 80031f0 <HAL_ADC_ConfigChannel+0x544>
|
|
{
|
|
/* Regular sequence configuration */
|
|
/* For Rank 1 to 4U */
|
|
if (sConfig->Rank < 5U)
|
|
8002ce6: 683b ldr r3, [r7, #0]
|
|
8002ce8: 685b ldr r3, [r3, #4]
|
|
8002cea: 2b04 cmp r3, #4
|
|
8002cec: d81c bhi.n 8002d28 <HAL_ADC_ConfigChannel+0x7c>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR1,
|
|
8002cee: 687b ldr r3, [r7, #4]
|
|
8002cf0: 681b ldr r3, [r3, #0]
|
|
8002cf2: 6b19 ldr r1, [r3, #48] @ 0x30
|
|
8002cf4: 683b ldr r3, [r7, #0]
|
|
8002cf6: 685a ldr r2, [r3, #4]
|
|
8002cf8: 4613 mov r3, r2
|
|
8002cfa: 005b lsls r3, r3, #1
|
|
8002cfc: 4413 add r3, r2
|
|
8002cfe: 005b lsls r3, r3, #1
|
|
8002d00: 461a mov r2, r3
|
|
8002d02: 231f movs r3, #31
|
|
8002d04: 4093 lsls r3, r2
|
|
8002d06: 43db mvns r3, r3
|
|
8002d08: 4019 ands r1, r3
|
|
8002d0a: 683b ldr r3, [r7, #0]
|
|
8002d0c: 6818 ldr r0, [r3, #0]
|
|
8002d0e: 683b ldr r3, [r7, #0]
|
|
8002d10: 685a ldr r2, [r3, #4]
|
|
8002d12: 4613 mov r3, r2
|
|
8002d14: 005b lsls r3, r3, #1
|
|
8002d16: 4413 add r3, r2
|
|
8002d18: 005b lsls r3, r3, #1
|
|
8002d1a: fa00 f203 lsl.w r2, r0, r3
|
|
8002d1e: 687b ldr r3, [r7, #4]
|
|
8002d20: 681b ldr r3, [r3, #0]
|
|
8002d22: 430a orrs r2, r1
|
|
8002d24: 631a str r2, [r3, #48] @ 0x30
|
|
8002d26: e063 b.n 8002df0 <HAL_ADC_ConfigChannel+0x144>
|
|
ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
|
|
ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
|
|
}
|
|
/* For Rank 5 to 9U */
|
|
else if (sConfig->Rank < 10U)
|
|
8002d28: 683b ldr r3, [r7, #0]
|
|
8002d2a: 685b ldr r3, [r3, #4]
|
|
8002d2c: 2b09 cmp r3, #9
|
|
8002d2e: d81e bhi.n 8002d6e <HAL_ADC_ConfigChannel+0xc2>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR2,
|
|
8002d30: 687b ldr r3, [r7, #4]
|
|
8002d32: 681b ldr r3, [r3, #0]
|
|
8002d34: 6b59 ldr r1, [r3, #52] @ 0x34
|
|
8002d36: 683b ldr r3, [r7, #0]
|
|
8002d38: 685a ldr r2, [r3, #4]
|
|
8002d3a: 4613 mov r3, r2
|
|
8002d3c: 005b lsls r3, r3, #1
|
|
8002d3e: 4413 add r3, r2
|
|
8002d40: 005b lsls r3, r3, #1
|
|
8002d42: 3b1e subs r3, #30
|
|
8002d44: 221f movs r2, #31
|
|
8002d46: fa02 f303 lsl.w r3, r2, r3
|
|
8002d4a: 43db mvns r3, r3
|
|
8002d4c: 4019 ands r1, r3
|
|
8002d4e: 683b ldr r3, [r7, #0]
|
|
8002d50: 6818 ldr r0, [r3, #0]
|
|
8002d52: 683b ldr r3, [r7, #0]
|
|
8002d54: 685a ldr r2, [r3, #4]
|
|
8002d56: 4613 mov r3, r2
|
|
8002d58: 005b lsls r3, r3, #1
|
|
8002d5a: 4413 add r3, r2
|
|
8002d5c: 005b lsls r3, r3, #1
|
|
8002d5e: 3b1e subs r3, #30
|
|
8002d60: fa00 f203 lsl.w r2, r0, r3
|
|
8002d64: 687b ldr r3, [r7, #4]
|
|
8002d66: 681b ldr r3, [r3, #0]
|
|
8002d68: 430a orrs r2, r1
|
|
8002d6a: 635a str r2, [r3, #52] @ 0x34
|
|
8002d6c: e040 b.n 8002df0 <HAL_ADC_ConfigChannel+0x144>
|
|
ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) ,
|
|
ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
|
|
}
|
|
/* For Rank 10 to 14U */
|
|
else if (sConfig->Rank < 15U)
|
|
8002d6e: 683b ldr r3, [r7, #0]
|
|
8002d70: 685b ldr r3, [r3, #4]
|
|
8002d72: 2b0e cmp r3, #14
|
|
8002d74: d81e bhi.n 8002db4 <HAL_ADC_ConfigChannel+0x108>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR3 ,
|
|
8002d76: 687b ldr r3, [r7, #4]
|
|
8002d78: 681b ldr r3, [r3, #0]
|
|
8002d7a: 6b99 ldr r1, [r3, #56] @ 0x38
|
|
8002d7c: 683b ldr r3, [r7, #0]
|
|
8002d7e: 685a ldr r2, [r3, #4]
|
|
8002d80: 4613 mov r3, r2
|
|
8002d82: 005b lsls r3, r3, #1
|
|
8002d84: 4413 add r3, r2
|
|
8002d86: 005b lsls r3, r3, #1
|
|
8002d88: 3b3c subs r3, #60 @ 0x3c
|
|
8002d8a: 221f movs r2, #31
|
|
8002d8c: fa02 f303 lsl.w r3, r2, r3
|
|
8002d90: 43db mvns r3, r3
|
|
8002d92: 4019 ands r1, r3
|
|
8002d94: 683b ldr r3, [r7, #0]
|
|
8002d96: 6818 ldr r0, [r3, #0]
|
|
8002d98: 683b ldr r3, [r7, #0]
|
|
8002d9a: 685a ldr r2, [r3, #4]
|
|
8002d9c: 4613 mov r3, r2
|
|
8002d9e: 005b lsls r3, r3, #1
|
|
8002da0: 4413 add r3, r2
|
|
8002da2: 005b lsls r3, r3, #1
|
|
8002da4: 3b3c subs r3, #60 @ 0x3c
|
|
8002da6: fa00 f203 lsl.w r2, r0, r3
|
|
8002daa: 687b ldr r3, [r7, #4]
|
|
8002dac: 681b ldr r3, [r3, #0]
|
|
8002dae: 430a orrs r2, r1
|
|
8002db0: 639a str r2, [r3, #56] @ 0x38
|
|
8002db2: e01d b.n 8002df0 <HAL_ADC_ConfigChannel+0x144>
|
|
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
|
|
}
|
|
/* For Rank 15 to 16U */
|
|
else
|
|
{
|
|
MODIFY_REG(hadc->Instance->SQR4 ,
|
|
8002db4: 687b ldr r3, [r7, #4]
|
|
8002db6: 681b ldr r3, [r3, #0]
|
|
8002db8: 6bd9 ldr r1, [r3, #60] @ 0x3c
|
|
8002dba: 683b ldr r3, [r7, #0]
|
|
8002dbc: 685a ldr r2, [r3, #4]
|
|
8002dbe: 4613 mov r3, r2
|
|
8002dc0: 005b lsls r3, r3, #1
|
|
8002dc2: 4413 add r3, r2
|
|
8002dc4: 005b lsls r3, r3, #1
|
|
8002dc6: 3b5a subs r3, #90 @ 0x5a
|
|
8002dc8: 221f movs r2, #31
|
|
8002dca: fa02 f303 lsl.w r3, r2, r3
|
|
8002dce: 43db mvns r3, r3
|
|
8002dd0: 4019 ands r1, r3
|
|
8002dd2: 683b ldr r3, [r7, #0]
|
|
8002dd4: 6818 ldr r0, [r3, #0]
|
|
8002dd6: 683b ldr r3, [r7, #0]
|
|
8002dd8: 685a ldr r2, [r3, #4]
|
|
8002dda: 4613 mov r3, r2
|
|
8002ddc: 005b lsls r3, r3, #1
|
|
8002dde: 4413 add r3, r2
|
|
8002de0: 005b lsls r3, r3, #1
|
|
8002de2: 3b5a subs r3, #90 @ 0x5a
|
|
8002de4: fa00 f203 lsl.w r2, r0, r3
|
|
8002de8: 687b ldr r3, [r7, #4]
|
|
8002dea: 681b ldr r3, [r3, #0]
|
|
8002dec: 430a orrs r2, r1
|
|
8002dee: 63da str r2, [r3, #60] @ 0x3c
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Channel sampling time */
|
|
/* - Channel offset */
|
|
if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
|
|
8002df0: 687b ldr r3, [r7, #4]
|
|
8002df2: 681b ldr r3, [r3, #0]
|
|
8002df4: 689b ldr r3, [r3, #8]
|
|
8002df6: f003 030c and.w r3, r3, #12
|
|
8002dfa: 2b00 cmp r3, #0
|
|
8002dfc: f040 80e5 bne.w 8002fca <HAL_ADC_ConfigChannel+0x31e>
|
|
{
|
|
/* Channel sampling time configuration */
|
|
/* For channels 10 to 18U */
|
|
if (sConfig->Channel >= ADC_CHANNEL_10)
|
|
8002e00: 683b ldr r3, [r7, #0]
|
|
8002e02: 681b ldr r3, [r3, #0]
|
|
8002e04: 2b09 cmp r3, #9
|
|
8002e06: d91c bls.n 8002e42 <HAL_ADC_ConfigChannel+0x196>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SMPR2 ,
|
|
8002e08: 687b ldr r3, [r7, #4]
|
|
8002e0a: 681b ldr r3, [r3, #0]
|
|
8002e0c: 6999 ldr r1, [r3, #24]
|
|
8002e0e: 683b ldr r3, [r7, #0]
|
|
8002e10: 681a ldr r2, [r3, #0]
|
|
8002e12: 4613 mov r3, r2
|
|
8002e14: 005b lsls r3, r3, #1
|
|
8002e16: 4413 add r3, r2
|
|
8002e18: 3b1e subs r3, #30
|
|
8002e1a: 2207 movs r2, #7
|
|
8002e1c: fa02 f303 lsl.w r3, r2, r3
|
|
8002e20: 43db mvns r3, r3
|
|
8002e22: 4019 ands r1, r3
|
|
8002e24: 683b ldr r3, [r7, #0]
|
|
8002e26: 6898 ldr r0, [r3, #8]
|
|
8002e28: 683b ldr r3, [r7, #0]
|
|
8002e2a: 681a ldr r2, [r3, #0]
|
|
8002e2c: 4613 mov r3, r2
|
|
8002e2e: 005b lsls r3, r3, #1
|
|
8002e30: 4413 add r3, r2
|
|
8002e32: 3b1e subs r3, #30
|
|
8002e34: fa00 f203 lsl.w r2, r0, r3
|
|
8002e38: 687b ldr r3, [r7, #4]
|
|
8002e3a: 681b ldr r3, [r3, #0]
|
|
8002e3c: 430a orrs r2, r1
|
|
8002e3e: 619a str r2, [r3, #24]
|
|
8002e40: e019 b.n 8002e76 <HAL_ADC_ConfigChannel+0x1ca>
|
|
ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) ,
|
|
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
|
|
}
|
|
else /* For channels 1 to 9U */
|
|
{
|
|
MODIFY_REG(hadc->Instance->SMPR1 ,
|
|
8002e42: 687b ldr r3, [r7, #4]
|
|
8002e44: 681b ldr r3, [r3, #0]
|
|
8002e46: 6959 ldr r1, [r3, #20]
|
|
8002e48: 683b ldr r3, [r7, #0]
|
|
8002e4a: 681a ldr r2, [r3, #0]
|
|
8002e4c: 4613 mov r3, r2
|
|
8002e4e: 005b lsls r3, r3, #1
|
|
8002e50: 4413 add r3, r2
|
|
8002e52: 2207 movs r2, #7
|
|
8002e54: fa02 f303 lsl.w r3, r2, r3
|
|
8002e58: 43db mvns r3, r3
|
|
8002e5a: 4019 ands r1, r3
|
|
8002e5c: 683b ldr r3, [r7, #0]
|
|
8002e5e: 6898 ldr r0, [r3, #8]
|
|
8002e60: 683b ldr r3, [r7, #0]
|
|
8002e62: 681a ldr r2, [r3, #0]
|
|
8002e64: 4613 mov r3, r2
|
|
8002e66: 005b lsls r3, r3, #1
|
|
8002e68: 4413 add r3, r2
|
|
8002e6a: fa00 f203 lsl.w r2, r0, r3
|
|
8002e6e: 687b ldr r3, [r7, #4]
|
|
8002e70: 681b ldr r3, [r3, #0]
|
|
8002e72: 430a orrs r2, r1
|
|
8002e74: 615a str r2, [r3, #20]
|
|
/* Configure the offset: offset enable/disable, channel, offset value */
|
|
|
|
/* Shift the offset in function of the selected ADC resolution. */
|
|
/* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */
|
|
/* to 0. */
|
|
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
|
|
8002e76: 683b ldr r3, [r7, #0]
|
|
8002e78: 695a ldr r2, [r3, #20]
|
|
8002e7a: 687b ldr r3, [r7, #4]
|
|
8002e7c: 681b ldr r3, [r3, #0]
|
|
8002e7e: 68db ldr r3, [r3, #12]
|
|
8002e80: 08db lsrs r3, r3, #3
|
|
8002e82: f003 0303 and.w r3, r3, #3
|
|
8002e86: 005b lsls r3, r3, #1
|
|
8002e88: fa02 f303 lsl.w r3, r2, r3
|
|
8002e8c: 663b str r3, [r7, #96] @ 0x60
|
|
|
|
/* Configure the selected offset register: */
|
|
/* - Enable offset */
|
|
/* - Set channel number */
|
|
/* - Set offset value */
|
|
switch (sConfig->OffsetNumber)
|
|
8002e8e: 683b ldr r3, [r7, #0]
|
|
8002e90: 691b ldr r3, [r3, #16]
|
|
8002e92: 3b01 subs r3, #1
|
|
8002e94: 2b03 cmp r3, #3
|
|
8002e96: d84f bhi.n 8002f38 <HAL_ADC_ConfigChannel+0x28c>
|
|
8002e98: a201 add r2, pc, #4 @ (adr r2, 8002ea0 <HAL_ADC_ConfigChannel+0x1f4>)
|
|
8002e9a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8002e9e: bf00 nop
|
|
8002ea0: 08002eb1 .word 0x08002eb1
|
|
8002ea4: 08002ed3 .word 0x08002ed3
|
|
8002ea8: 08002ef5 .word 0x08002ef5
|
|
8002eac: 08002f17 .word 0x08002f17
|
|
{
|
|
case ADC_OFFSET_1:
|
|
/* Configure offset register 1U */
|
|
MODIFY_REG(hadc->Instance->OFR1 ,
|
|
8002eb0: 687b ldr r3, [r7, #4]
|
|
8002eb2: 681b ldr r3, [r3, #0]
|
|
8002eb4: 6e1a ldr r2, [r3, #96] @ 0x60
|
|
8002eb6: 4b9c ldr r3, [pc, #624] @ (8003128 <HAL_ADC_ConfigChannel+0x47c>)
|
|
8002eb8: 4013 ands r3, r2
|
|
8002eba: 683a ldr r2, [r7, #0]
|
|
8002ebc: 6812 ldr r2, [r2, #0]
|
|
8002ebe: 0691 lsls r1, r2, #26
|
|
8002ec0: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
8002ec2: 430a orrs r2, r1
|
|
8002ec4: 431a orrs r2, r3
|
|
8002ec6: 687b ldr r3, [r7, #4]
|
|
8002ec8: 681b ldr r3, [r3, #0]
|
|
8002eca: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
|
|
8002ece: 661a str r2, [r3, #96] @ 0x60
|
|
ADC_OFR1_OFFSET1_CH |
|
|
ADC_OFR1_OFFSET1 ,
|
|
ADC_OFR1_OFFSET1_EN |
|
|
ADC_OFR_CHANNEL(sConfig->Channel) |
|
|
tmpOffsetShifted );
|
|
break;
|
|
8002ed0: e07b b.n 8002fca <HAL_ADC_ConfigChannel+0x31e>
|
|
|
|
case ADC_OFFSET_2:
|
|
/* Configure offset register 2U */
|
|
MODIFY_REG(hadc->Instance->OFR2 ,
|
|
8002ed2: 687b ldr r3, [r7, #4]
|
|
8002ed4: 681b ldr r3, [r3, #0]
|
|
8002ed6: 6e5a ldr r2, [r3, #100] @ 0x64
|
|
8002ed8: 4b93 ldr r3, [pc, #588] @ (8003128 <HAL_ADC_ConfigChannel+0x47c>)
|
|
8002eda: 4013 ands r3, r2
|
|
8002edc: 683a ldr r2, [r7, #0]
|
|
8002ede: 6812 ldr r2, [r2, #0]
|
|
8002ee0: 0691 lsls r1, r2, #26
|
|
8002ee2: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
8002ee4: 430a orrs r2, r1
|
|
8002ee6: 431a orrs r2, r3
|
|
8002ee8: 687b ldr r3, [r7, #4]
|
|
8002eea: 681b ldr r3, [r3, #0]
|
|
8002eec: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
|
|
8002ef0: 665a str r2, [r3, #100] @ 0x64
|
|
ADC_OFR2_OFFSET2_CH |
|
|
ADC_OFR2_OFFSET2 ,
|
|
ADC_OFR2_OFFSET2_EN |
|
|
ADC_OFR_CHANNEL(sConfig->Channel) |
|
|
tmpOffsetShifted );
|
|
break;
|
|
8002ef2: e06a b.n 8002fca <HAL_ADC_ConfigChannel+0x31e>
|
|
|
|
case ADC_OFFSET_3:
|
|
/* Configure offset register 3U */
|
|
MODIFY_REG(hadc->Instance->OFR3 ,
|
|
8002ef4: 687b ldr r3, [r7, #4]
|
|
8002ef6: 681b ldr r3, [r3, #0]
|
|
8002ef8: 6e9a ldr r2, [r3, #104] @ 0x68
|
|
8002efa: 4b8b ldr r3, [pc, #556] @ (8003128 <HAL_ADC_ConfigChannel+0x47c>)
|
|
8002efc: 4013 ands r3, r2
|
|
8002efe: 683a ldr r2, [r7, #0]
|
|
8002f00: 6812 ldr r2, [r2, #0]
|
|
8002f02: 0691 lsls r1, r2, #26
|
|
8002f04: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
8002f06: 430a orrs r2, r1
|
|
8002f08: 431a orrs r2, r3
|
|
8002f0a: 687b ldr r3, [r7, #4]
|
|
8002f0c: 681b ldr r3, [r3, #0]
|
|
8002f0e: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
|
|
8002f12: 669a str r2, [r3, #104] @ 0x68
|
|
ADC_OFR3_OFFSET3_CH |
|
|
ADC_OFR3_OFFSET3 ,
|
|
ADC_OFR3_OFFSET3_EN |
|
|
ADC_OFR_CHANNEL(sConfig->Channel) |
|
|
tmpOffsetShifted );
|
|
break;
|
|
8002f14: e059 b.n 8002fca <HAL_ADC_ConfigChannel+0x31e>
|
|
|
|
case ADC_OFFSET_4:
|
|
/* Configure offset register 4U */
|
|
MODIFY_REG(hadc->Instance->OFR4 ,
|
|
8002f16: 687b ldr r3, [r7, #4]
|
|
8002f18: 681b ldr r3, [r3, #0]
|
|
8002f1a: 6eda ldr r2, [r3, #108] @ 0x6c
|
|
8002f1c: 4b82 ldr r3, [pc, #520] @ (8003128 <HAL_ADC_ConfigChannel+0x47c>)
|
|
8002f1e: 4013 ands r3, r2
|
|
8002f20: 683a ldr r2, [r7, #0]
|
|
8002f22: 6812 ldr r2, [r2, #0]
|
|
8002f24: 0691 lsls r1, r2, #26
|
|
8002f26: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
8002f28: 430a orrs r2, r1
|
|
8002f2a: 431a orrs r2, r3
|
|
8002f2c: 687b ldr r3, [r7, #4]
|
|
8002f2e: 681b ldr r3, [r3, #0]
|
|
8002f30: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000
|
|
8002f34: 66da str r2, [r3, #108] @ 0x6c
|
|
ADC_OFR4_OFFSET4_CH |
|
|
ADC_OFR4_OFFSET4 ,
|
|
ADC_OFR4_OFFSET4_EN |
|
|
ADC_OFR_CHANNEL(sConfig->Channel) |
|
|
tmpOffsetShifted );
|
|
break;
|
|
8002f36: e048 b.n 8002fca <HAL_ADC_ConfigChannel+0x31e>
|
|
|
|
/* Case ADC_OFFSET_NONE */
|
|
default :
|
|
/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */
|
|
/* enabled. If this is the case, offset OFRx is disabled. */
|
|
if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
|
|
8002f38: 687b ldr r3, [r7, #4]
|
|
8002f3a: 681b ldr r3, [r3, #0]
|
|
8002f3c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002f3e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
|
|
8002f42: 683b ldr r3, [r7, #0]
|
|
8002f44: 681b ldr r3, [r3, #0]
|
|
8002f46: 069b lsls r3, r3, #26
|
|
8002f48: 429a cmp r2, r3
|
|
8002f4a: d107 bne.n 8002f5c <HAL_ADC_ConfigChannel+0x2b0>
|
|
{
|
|
/* Disable offset OFR1*/
|
|
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
|
|
8002f4c: 687b ldr r3, [r7, #4]
|
|
8002f4e: 681b ldr r3, [r3, #0]
|
|
8002f50: 6e1a ldr r2, [r3, #96] @ 0x60
|
|
8002f52: 687b ldr r3, [r7, #4]
|
|
8002f54: 681b ldr r3, [r3, #0]
|
|
8002f56: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
|
|
8002f5a: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
|
|
8002f5c: 687b ldr r3, [r7, #4]
|
|
8002f5e: 681b ldr r3, [r3, #0]
|
|
8002f60: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8002f62: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
|
|
8002f66: 683b ldr r3, [r7, #0]
|
|
8002f68: 681b ldr r3, [r3, #0]
|
|
8002f6a: 069b lsls r3, r3, #26
|
|
8002f6c: 429a cmp r2, r3
|
|
8002f6e: d107 bne.n 8002f80 <HAL_ADC_ConfigChannel+0x2d4>
|
|
{
|
|
/* Disable offset OFR2*/
|
|
CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN);
|
|
8002f70: 687b ldr r3, [r7, #4]
|
|
8002f72: 681b ldr r3, [r3, #0]
|
|
8002f74: 6e5a ldr r2, [r3, #100] @ 0x64
|
|
8002f76: 687b ldr r3, [r7, #4]
|
|
8002f78: 681b ldr r3, [r3, #0]
|
|
8002f7a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
|
|
8002f7e: 665a str r2, [r3, #100] @ 0x64
|
|
}
|
|
if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
|
|
8002f80: 687b ldr r3, [r7, #4]
|
|
8002f82: 681b ldr r3, [r3, #0]
|
|
8002f84: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8002f86: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
|
|
8002f8a: 683b ldr r3, [r7, #0]
|
|
8002f8c: 681b ldr r3, [r3, #0]
|
|
8002f8e: 069b lsls r3, r3, #26
|
|
8002f90: 429a cmp r2, r3
|
|
8002f92: d107 bne.n 8002fa4 <HAL_ADC_ConfigChannel+0x2f8>
|
|
{
|
|
/* Disable offset OFR3*/
|
|
CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN);
|
|
8002f94: 687b ldr r3, [r7, #4]
|
|
8002f96: 681b ldr r3, [r3, #0]
|
|
8002f98: 6e9a ldr r2, [r3, #104] @ 0x68
|
|
8002f9a: 687b ldr r3, [r7, #4]
|
|
8002f9c: 681b ldr r3, [r3, #0]
|
|
8002f9e: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
|
|
8002fa2: 669a str r2, [r3, #104] @ 0x68
|
|
}
|
|
if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
|
|
8002fa4: 687b ldr r3, [r7, #4]
|
|
8002fa6: 681b ldr r3, [r3, #0]
|
|
8002fa8: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8002faa: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
|
|
8002fae: 683b ldr r3, [r7, #0]
|
|
8002fb0: 681b ldr r3, [r3, #0]
|
|
8002fb2: 069b lsls r3, r3, #26
|
|
8002fb4: 429a cmp r2, r3
|
|
8002fb6: d107 bne.n 8002fc8 <HAL_ADC_ConfigChannel+0x31c>
|
|
{
|
|
/* Disable offset OFR4*/
|
|
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
|
|
8002fb8: 687b ldr r3, [r7, #4]
|
|
8002fba: 681b ldr r3, [r3, #0]
|
|
8002fbc: 6eda ldr r2, [r3, #108] @ 0x6c
|
|
8002fbe: 687b ldr r3, [r7, #4]
|
|
8002fc0: 681b ldr r3, [r3, #0]
|
|
8002fc2: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
|
|
8002fc6: 66da str r2, [r3, #108] @ 0x6c
|
|
}
|
|
break;
|
|
8002fc8: bf00 nop
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Single or differential mode */
|
|
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
|
|
if (ADC_IS_ENABLE(hadc) == RESET)
|
|
8002fca: 687b ldr r3, [r7, #4]
|
|
8002fcc: 681b ldr r3, [r3, #0]
|
|
8002fce: 689b ldr r3, [r3, #8]
|
|
8002fd0: f003 0303 and.w r3, r3, #3
|
|
8002fd4: 2b01 cmp r3, #1
|
|
8002fd6: d108 bne.n 8002fea <HAL_ADC_ConfigChannel+0x33e>
|
|
8002fd8: 687b ldr r3, [r7, #4]
|
|
8002fda: 681b ldr r3, [r3, #0]
|
|
8002fdc: 681b ldr r3, [r3, #0]
|
|
8002fde: f003 0301 and.w r3, r3, #1
|
|
8002fe2: 2b01 cmp r3, #1
|
|
8002fe4: d101 bne.n 8002fea <HAL_ADC_ConfigChannel+0x33e>
|
|
8002fe6: 2301 movs r3, #1
|
|
8002fe8: e000 b.n 8002fec <HAL_ADC_ConfigChannel+0x340>
|
|
8002fea: 2300 movs r3, #0
|
|
8002fec: 2b00 cmp r3, #0
|
|
8002fee: f040 810a bne.w 8003206 <HAL_ADC_ConfigChannel+0x55a>
|
|
{
|
|
/* Configuration of differential mode */
|
|
if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
|
|
8002ff2: 683b ldr r3, [r7, #0]
|
|
8002ff4: 68db ldr r3, [r3, #12]
|
|
8002ff6: 2b01 cmp r3, #1
|
|
8002ff8: d00f beq.n 800301a <HAL_ADC_ConfigChannel+0x36e>
|
|
{
|
|
/* Disable differential mode (default mode: single-ended) */
|
|
CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
|
|
8002ffa: 687b ldr r3, [r7, #4]
|
|
8002ffc: 681b ldr r3, [r3, #0]
|
|
8002ffe: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0
|
|
8003002: 683b ldr r3, [r7, #0]
|
|
8003004: 681b ldr r3, [r3, #0]
|
|
8003006: 2201 movs r2, #1
|
|
8003008: fa02 f303 lsl.w r3, r2, r3
|
|
800300c: 43da mvns r2, r3
|
|
800300e: 687b ldr r3, [r7, #4]
|
|
8003010: 681b ldr r3, [r3, #0]
|
|
8003012: 400a ands r2, r1
|
|
8003014: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
|
|
8003018: e049 b.n 80030ae <HAL_ADC_ConfigChannel+0x402>
|
|
}
|
|
else
|
|
{
|
|
/* Enable differential mode */
|
|
SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
|
|
800301a: 687b ldr r3, [r7, #4]
|
|
800301c: 681b ldr r3, [r3, #0]
|
|
800301e: f8d3 10b0 ldr.w r1, [r3, #176] @ 0xb0
|
|
8003022: 683b ldr r3, [r7, #0]
|
|
8003024: 681b ldr r3, [r3, #0]
|
|
8003026: 2201 movs r2, #1
|
|
8003028: 409a lsls r2, r3
|
|
800302a: 687b ldr r3, [r7, #4]
|
|
800302c: 681b ldr r3, [r3, #0]
|
|
800302e: 430a orrs r2, r1
|
|
8003030: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
|
|
|
|
/* Channel sampling time configuration (channel ADC_INx +1 */
|
|
/* corresponding to differential negative input). */
|
|
/* For channels 10 to 18U */
|
|
if (sConfig->Channel >= ADC_CHANNEL_10)
|
|
8003034: 683b ldr r3, [r7, #0]
|
|
8003036: 681b ldr r3, [r3, #0]
|
|
8003038: 2b09 cmp r3, #9
|
|
800303a: d91c bls.n 8003076 <HAL_ADC_ConfigChannel+0x3ca>
|
|
{
|
|
MODIFY_REG(hadc->Instance->SMPR2,
|
|
800303c: 687b ldr r3, [r7, #4]
|
|
800303e: 681b ldr r3, [r3, #0]
|
|
8003040: 6999 ldr r1, [r3, #24]
|
|
8003042: 683b ldr r3, [r7, #0]
|
|
8003044: 681a ldr r2, [r3, #0]
|
|
8003046: 4613 mov r3, r2
|
|
8003048: 005b lsls r3, r3, #1
|
|
800304a: 4413 add r3, r2
|
|
800304c: 3b1b subs r3, #27
|
|
800304e: 2207 movs r2, #7
|
|
8003050: fa02 f303 lsl.w r3, r2, r3
|
|
8003054: 43db mvns r3, r3
|
|
8003056: 4019 ands r1, r3
|
|
8003058: 683b ldr r3, [r7, #0]
|
|
800305a: 6898 ldr r0, [r3, #8]
|
|
800305c: 683b ldr r3, [r7, #0]
|
|
800305e: 681a ldr r2, [r3, #0]
|
|
8003060: 4613 mov r3, r2
|
|
8003062: 005b lsls r3, r3, #1
|
|
8003064: 4413 add r3, r2
|
|
8003066: 3b1b subs r3, #27
|
|
8003068: fa00 f203 lsl.w r2, r0, r3
|
|
800306c: 687b ldr r3, [r7, #4]
|
|
800306e: 681b ldr r3, [r3, #0]
|
|
8003070: 430a orrs r2, r1
|
|
8003072: 619a str r2, [r3, #24]
|
|
8003074: e01b b.n 80030ae <HAL_ADC_ConfigChannel+0x402>
|
|
ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) ,
|
|
ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) );
|
|
}
|
|
else /* For channels 1 to 9U */
|
|
{
|
|
MODIFY_REG(hadc->Instance->SMPR1,
|
|
8003076: 687b ldr r3, [r7, #4]
|
|
8003078: 681b ldr r3, [r3, #0]
|
|
800307a: 6959 ldr r1, [r3, #20]
|
|
800307c: 683b ldr r3, [r7, #0]
|
|
800307e: 681b ldr r3, [r3, #0]
|
|
8003080: 1c5a adds r2, r3, #1
|
|
8003082: 4613 mov r3, r2
|
|
8003084: 005b lsls r3, r3, #1
|
|
8003086: 4413 add r3, r2
|
|
8003088: 2207 movs r2, #7
|
|
800308a: fa02 f303 lsl.w r3, r2, r3
|
|
800308e: 43db mvns r3, r3
|
|
8003090: 4019 ands r1, r3
|
|
8003092: 683b ldr r3, [r7, #0]
|
|
8003094: 6898 ldr r0, [r3, #8]
|
|
8003096: 683b ldr r3, [r7, #0]
|
|
8003098: 681b ldr r3, [r3, #0]
|
|
800309a: 1c5a adds r2, r3, #1
|
|
800309c: 4613 mov r3, r2
|
|
800309e: 005b lsls r3, r3, #1
|
|
80030a0: 4413 add r3, r2
|
|
80030a2: fa00 f203 lsl.w r2, r0, r3
|
|
80030a6: 687b ldr r3, [r7, #4]
|
|
80030a8: 681b ldr r3, [r3, #0]
|
|
80030aa: 430a orrs r2, r1
|
|
80030ac: 615a str r2, [r3, #20]
|
|
|
|
/* Configuration of common ADC parameters */
|
|
/* Pointer to the common control register to which is belonging hadc */
|
|
/* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
|
|
/* control registers) */
|
|
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
|
|
80030ae: 4b1f ldr r3, [pc, #124] @ (800312c <HAL_ADC_ConfigChannel+0x480>)
|
|
80030b0: 65fb str r3, [r7, #92] @ 0x5c
|
|
|
|
/* If the requested internal measurement path has already been enabled, */
|
|
/* bypass the configuration processing. */
|
|
if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
|
|
80030b2: 683b ldr r3, [r7, #0]
|
|
80030b4: 681b ldr r3, [r3, #0]
|
|
80030b6: 2b10 cmp r3, #16
|
|
80030b8: d105 bne.n 80030c6 <HAL_ADC_ConfigChannel+0x41a>
|
|
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
|
|
80030ba: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80030bc: 689b ldr r3, [r3, #8]
|
|
80030be: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
|
|
80030c2: 2b00 cmp r3, #0
|
|
80030c4: d015 beq.n 80030f2 <HAL_ADC_ConfigChannel+0x446>
|
|
( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
|
|
80030c6: 683b ldr r3, [r7, #0]
|
|
80030c8: 681b ldr r3, [r3, #0]
|
|
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
|
|
80030ca: 2b11 cmp r3, #17
|
|
80030cc: d105 bne.n 80030da <HAL_ADC_ConfigChannel+0x42e>
|
|
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
|
|
80030ce: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80030d0: 689b ldr r3, [r3, #8]
|
|
80030d2: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
|
|
80030d6: 2b00 cmp r3, #0
|
|
80030d8: d00b beq.n 80030f2 <HAL_ADC_ConfigChannel+0x446>
|
|
( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
|
|
80030da: 683b ldr r3, [r7, #0]
|
|
80030dc: 681b ldr r3, [r3, #0]
|
|
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
|
|
80030de: 2b12 cmp r3, #18
|
|
80030e0: f040 8091 bne.w 8003206 <HAL_ADC_ConfigChannel+0x55a>
|
|
(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
|
|
80030e4: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80030e6: 689b ldr r3, [r3, #8]
|
|
80030e8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
|
|
80030ec: 2b00 cmp r3, #0
|
|
80030ee: f040 808a bne.w 8003206 <HAL_ADC_ConfigChannel+0x55a>
|
|
)
|
|
{
|
|
/* Configuration of common ADC parameters (continuation) */
|
|
/* Set handle of the other ADC sharing the same common register */
|
|
ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
|
|
80030f2: 687b ldr r3, [r7, #4]
|
|
80030f4: 681b ldr r3, [r3, #0]
|
|
80030f6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
80030fa: d102 bne.n 8003102 <HAL_ADC_ConfigChannel+0x456>
|
|
80030fc: 4b0c ldr r3, [pc, #48] @ (8003130 <HAL_ADC_ConfigChannel+0x484>)
|
|
80030fe: 60fb str r3, [r7, #12]
|
|
8003100: e002 b.n 8003108 <HAL_ADC_ConfigChannel+0x45c>
|
|
8003102: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
8003106: 60fb str r3, [r7, #12]
|
|
|
|
/* Software is allowed to change common parameters only when all ADCs */
|
|
/* of the common group are disabled. */
|
|
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
|
8003108: 687b ldr r3, [r7, #4]
|
|
800310a: 681b ldr r3, [r3, #0]
|
|
800310c: 689b ldr r3, [r3, #8]
|
|
800310e: f003 0303 and.w r3, r3, #3
|
|
8003112: 2b01 cmp r3, #1
|
|
8003114: d10e bne.n 8003134 <HAL_ADC_ConfigChannel+0x488>
|
|
8003116: 687b ldr r3, [r7, #4]
|
|
8003118: 681b ldr r3, [r3, #0]
|
|
800311a: 681b ldr r3, [r3, #0]
|
|
800311c: f003 0301 and.w r3, r3, #1
|
|
8003120: 2b01 cmp r3, #1
|
|
8003122: d107 bne.n 8003134 <HAL_ADC_ConfigChannel+0x488>
|
|
8003124: 2301 movs r3, #1
|
|
8003126: e006 b.n 8003136 <HAL_ADC_ConfigChannel+0x48a>
|
|
8003128: 83fff000 .word 0x83fff000
|
|
800312c: 50000300 .word 0x50000300
|
|
8003130: 50000100 .word 0x50000100
|
|
8003134: 2300 movs r3, #0
|
|
8003136: 2b00 cmp r3, #0
|
|
8003138: d150 bne.n 80031dc <HAL_ADC_ConfigChannel+0x530>
|
|
( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
|
|
800313a: 68fb ldr r3, [r7, #12]
|
|
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
|
800313c: 2b00 cmp r3, #0
|
|
800313e: d010 beq.n 8003162 <HAL_ADC_ConfigChannel+0x4b6>
|
|
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) )
|
|
8003140: 68fb ldr r3, [r7, #12]
|
|
8003142: 689b ldr r3, [r3, #8]
|
|
8003144: f003 0303 and.w r3, r3, #3
|
|
8003148: 2b01 cmp r3, #1
|
|
800314a: d107 bne.n 800315c <HAL_ADC_ConfigChannel+0x4b0>
|
|
800314c: 68fb ldr r3, [r7, #12]
|
|
800314e: 681b ldr r3, [r3, #0]
|
|
8003150: f003 0301 and.w r3, r3, #1
|
|
8003154: 2b01 cmp r3, #1
|
|
8003156: d101 bne.n 800315c <HAL_ADC_ConfigChannel+0x4b0>
|
|
8003158: 2301 movs r3, #1
|
|
800315a: e000 b.n 800315e <HAL_ADC_ConfigChannel+0x4b2>
|
|
800315c: 2300 movs r3, #0
|
|
( (tmphadcSharingSameCommonRegister.Instance == NULL) ||
|
|
800315e: 2b00 cmp r3, #0
|
|
8003160: d13c bne.n 80031dc <HAL_ADC_ConfigChannel+0x530>
|
|
{
|
|
/* If Channel_16 is selected, enable Temp. sensor measurement path */
|
|
/* Note: Temp. sensor internal channels available on ADC1 only */
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
|
|
8003162: 683b ldr r3, [r7, #0]
|
|
8003164: 681b ldr r3, [r3, #0]
|
|
8003166: 2b10 cmp r3, #16
|
|
8003168: d11d bne.n 80031a6 <HAL_ADC_ConfigChannel+0x4fa>
|
|
800316a: 687b ldr r3, [r7, #4]
|
|
800316c: 681b ldr r3, [r3, #0]
|
|
800316e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8003172: d118 bne.n 80031a6 <HAL_ADC_ConfigChannel+0x4fa>
|
|
{
|
|
SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
|
|
8003174: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8003176: 689b ldr r3, [r3, #8]
|
|
8003178: f443 0200 orr.w r2, r3, #8388608 @ 0x800000
|
|
800317c: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
800317e: 609a str r2, [r3, #8]
|
|
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Compute number of CPU cycles to wait for */
|
|
wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
|
|
8003180: 4b27 ldr r3, [pc, #156] @ (8003220 <HAL_ADC_ConfigChannel+0x574>)
|
|
8003182: 681b ldr r3, [r3, #0]
|
|
8003184: 4a27 ldr r2, [pc, #156] @ (8003224 <HAL_ADC_ConfigChannel+0x578>)
|
|
8003186: fba2 2303 umull r2, r3, r2, r3
|
|
800318a: 0c9a lsrs r2, r3, #18
|
|
800318c: 4613 mov r3, r2
|
|
800318e: 009b lsls r3, r3, #2
|
|
8003190: 4413 add r3, r2
|
|
8003192: 005b lsls r3, r3, #1
|
|
8003194: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
8003196: e002 b.n 800319e <HAL_ADC_ConfigChannel+0x4f2>
|
|
{
|
|
wait_loop_index--;
|
|
8003198: 68bb ldr r3, [r7, #8]
|
|
800319a: 3b01 subs r3, #1
|
|
800319c: 60bb str r3, [r7, #8]
|
|
while(wait_loop_index != 0U)
|
|
800319e: 68bb ldr r3, [r7, #8]
|
|
80031a0: 2b00 cmp r3, #0
|
|
80031a2: d1f9 bne.n 8003198 <HAL_ADC_ConfigChannel+0x4ec>
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
|
|
80031a4: e02e b.n 8003204 <HAL_ADC_ConfigChannel+0x558>
|
|
}
|
|
}
|
|
/* If Channel_17 is selected, enable VBAT measurement path */
|
|
/* Note: VBAT internal channels available on ADC1 only */
|
|
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
|
|
80031a6: 683b ldr r3, [r7, #0]
|
|
80031a8: 681b ldr r3, [r3, #0]
|
|
80031aa: 2b11 cmp r3, #17
|
|
80031ac: d10b bne.n 80031c6 <HAL_ADC_ConfigChannel+0x51a>
|
|
80031ae: 687b ldr r3, [r7, #4]
|
|
80031b0: 681b ldr r3, [r3, #0]
|
|
80031b2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
80031b6: d106 bne.n 80031c6 <HAL_ADC_ConfigChannel+0x51a>
|
|
{
|
|
SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
|
|
80031b8: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80031ba: 689b ldr r3, [r3, #8]
|
|
80031bc: f043 7280 orr.w r2, r3, #16777216 @ 0x1000000
|
|
80031c0: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80031c2: 609a str r2, [r3, #8]
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
|
|
80031c4: e01e b.n 8003204 <HAL_ADC_ConfigChannel+0x558>
|
|
}
|
|
/* If Channel_18 is selected, enable VREFINT measurement path */
|
|
/* Note: VrefInt internal channels available on all ADCs, but only */
|
|
/* one ADC is allowed to be connected to VrefInt at the same */
|
|
/* time. */
|
|
else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
|
|
80031c6: 683b ldr r3, [r7, #0]
|
|
80031c8: 681b ldr r3, [r3, #0]
|
|
80031ca: 2b12 cmp r3, #18
|
|
80031cc: d11a bne.n 8003204 <HAL_ADC_ConfigChannel+0x558>
|
|
{
|
|
SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
|
|
80031ce: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80031d0: 689b ldr r3, [r3, #8]
|
|
80031d2: f443 0280 orr.w r2, r3, #4194304 @ 0x400000
|
|
80031d6: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80031d8: 609a str r2, [r3, #8]
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
|
|
80031da: e013 b.n 8003204 <HAL_ADC_ConfigChannel+0x558>
|
|
/* enabled and other ADC of the common group are enabled, internal */
|
|
/* measurement paths cannot be enabled. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
80031dc: 687b ldr r3, [r7, #4]
|
|
80031de: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80031e0: f043 0220 orr.w r2, r3, #32
|
|
80031e4: 687b ldr r3, [r7, #4]
|
|
80031e6: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
80031e8: 2301 movs r3, #1
|
|
80031ea: f887 3067 strb.w r3, [r7, #103] @ 0x67
|
|
80031ee: e00a b.n 8003206 <HAL_ADC_ConfigChannel+0x55a>
|
|
/* channel could be done on neither of the channel configuration structure */
|
|
/* parameters. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
80031f0: 687b ldr r3, [r7, #4]
|
|
80031f2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80031f4: f043 0220 orr.w r2, r3, #32
|
|
80031f8: 687b ldr r3, [r7, #4]
|
|
80031fa: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
80031fc: 2301 movs r3, #1
|
|
80031fe: f887 3067 strb.w r3, [r7, #103] @ 0x67
|
|
8003202: e000 b.n 8003206 <HAL_ADC_ConfigChannel+0x55a>
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
|
|
8003204: bf00 nop
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8003206: 687b ldr r3, [r7, #4]
|
|
8003208: 2200 movs r2, #0
|
|
800320a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
800320e: f897 3067 ldrb.w r3, [r7, #103] @ 0x67
|
|
}
|
|
8003212: 4618 mov r0, r3
|
|
8003214: 376c adds r7, #108 @ 0x6c
|
|
8003216: 46bd mov sp, r7
|
|
8003218: f85d 7b04 ldr.w r7, [sp], #4
|
|
800321c: 4770 bx lr
|
|
800321e: bf00 nop
|
|
8003220: 20000000 .word 0x20000000
|
|
8003224: 431bde83 .word 0x431bde83
|
|
|
|
08003228 <HAL_ADCEx_MultiModeConfigChannel>:
|
|
* @param hadc ADC handle
|
|
* @param multimode Structure of ADC multimode configuration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
|
|
{
|
|
8003228: b480 push {r7}
|
|
800322a: b099 sub sp, #100 @ 0x64
|
|
800322c: af00 add r7, sp, #0
|
|
800322e: 6078 str r0, [r7, #4]
|
|
8003230: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8003232: 2300 movs r3, #0
|
|
8003234: f887 305f strb.w r3, [r7, #95] @ 0x5f
|
|
assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
|
|
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
|
|
}
|
|
|
|
/* Set handle of the other ADC sharing the same common register */
|
|
ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
|
|
8003238: 687b ldr r3, [r7, #4]
|
|
800323a: 681b ldr r3, [r3, #0]
|
|
800323c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8003240: d102 bne.n 8003248 <HAL_ADCEx_MultiModeConfigChannel+0x20>
|
|
8003242: 4b5a ldr r3, [pc, #360] @ (80033ac <HAL_ADCEx_MultiModeConfigChannel+0x184>)
|
|
8003244: 60bb str r3, [r7, #8]
|
|
8003246: e002 b.n 800324e <HAL_ADCEx_MultiModeConfigChannel+0x26>
|
|
8003248: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
800324c: 60bb str r3, [r7, #8]
|
|
if (tmphadcSharingSameCommonRegister.Instance == NULL)
|
|
800324e: 68bb ldr r3, [r7, #8]
|
|
8003250: 2b00 cmp r3, #0
|
|
8003252: d101 bne.n 8003258 <HAL_ADCEx_MultiModeConfigChannel+0x30>
|
|
{
|
|
/* Return function status */
|
|
return HAL_ERROR;
|
|
8003254: 2301 movs r3, #1
|
|
8003256: e0a2 b.n 800339e <HAL_ADCEx_MultiModeConfigChannel+0x176>
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8003258: 687b ldr r3, [r7, #4]
|
|
800325a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
800325e: 2b01 cmp r3, #1
|
|
8003260: d101 bne.n 8003266 <HAL_ADCEx_MultiModeConfigChannel+0x3e>
|
|
8003262: 2302 movs r3, #2
|
|
8003264: e09b b.n 800339e <HAL_ADCEx_MultiModeConfigChannel+0x176>
|
|
8003266: 687b ldr r3, [r7, #4]
|
|
8003268: 2201 movs r2, #1
|
|
800326a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Multimode DMA configuration */
|
|
/* - Multimode DMA mode */
|
|
if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
|
|
800326e: 687b ldr r3, [r7, #4]
|
|
8003270: 681b ldr r3, [r3, #0]
|
|
8003272: 689b ldr r3, [r3, #8]
|
|
8003274: f003 0304 and.w r3, r3, #4
|
|
8003278: 2b00 cmp r3, #0
|
|
800327a: d17f bne.n 800337c <HAL_ADCEx_MultiModeConfigChannel+0x154>
|
|
&& (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) )
|
|
800327c: 68bb ldr r3, [r7, #8]
|
|
800327e: 689b ldr r3, [r3, #8]
|
|
8003280: f003 0304 and.w r3, r3, #4
|
|
8003284: 2b00 cmp r3, #0
|
|
8003286: d179 bne.n 800337c <HAL_ADCEx_MultiModeConfigChannel+0x154>
|
|
{
|
|
/* Pointer to the common control register to which is belonging hadc */
|
|
/* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
|
|
/* control registers) */
|
|
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
|
|
8003288: 4b49 ldr r3, [pc, #292] @ (80033b0 <HAL_ADCEx_MultiModeConfigChannel+0x188>)
|
|
800328a: 65bb str r3, [r7, #88] @ 0x58
|
|
|
|
/* If multimode is selected, configure all multimode parameters. */
|
|
/* Otherwise, reset multimode parameters (can be used in case of */
|
|
/* transition from multimode to independent mode). */
|
|
if(multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
800328c: 683b ldr r3, [r7, #0]
|
|
800328e: 681b ldr r3, [r3, #0]
|
|
8003290: 2b00 cmp r3, #0
|
|
8003292: d040 beq.n 8003316 <HAL_ADCEx_MultiModeConfigChannel+0xee>
|
|
{
|
|
/* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
|
|
/* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
|
|
/* - DMA access mode */
|
|
MODIFY_REG(tmpADC_Common->CCR ,
|
|
8003294: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8003296: 689b ldr r3, [r3, #8]
|
|
8003298: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
800329c: 683b ldr r3, [r7, #0]
|
|
800329e: 6859 ldr r1, [r3, #4]
|
|
80032a0: 687b ldr r3, [r7, #4]
|
|
80032a2: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
|
|
80032a6: 035b lsls r3, r3, #13
|
|
80032a8: 430b orrs r3, r1
|
|
80032aa: 431a orrs r2, r3
|
|
80032ac: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80032ae: 609a str r2, [r3, #8]
|
|
/* parameters, their setting is bypassed without error reporting */
|
|
/* (as it can be the expected behaviour in case of intended action */
|
|
/* to update parameter above (which fulfills the ADC state */
|
|
/* condition: no conversion on going on group regular) */
|
|
/* on the fly). */
|
|
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
|
80032b0: 687b ldr r3, [r7, #4]
|
|
80032b2: 681b ldr r3, [r3, #0]
|
|
80032b4: 689b ldr r3, [r3, #8]
|
|
80032b6: f003 0303 and.w r3, r3, #3
|
|
80032ba: 2b01 cmp r3, #1
|
|
80032bc: d108 bne.n 80032d0 <HAL_ADCEx_MultiModeConfigChannel+0xa8>
|
|
80032be: 687b ldr r3, [r7, #4]
|
|
80032c0: 681b ldr r3, [r3, #0]
|
|
80032c2: 681b ldr r3, [r3, #0]
|
|
80032c4: f003 0301 and.w r3, r3, #1
|
|
80032c8: 2b01 cmp r3, #1
|
|
80032ca: d101 bne.n 80032d0 <HAL_ADCEx_MultiModeConfigChannel+0xa8>
|
|
80032cc: 2301 movs r3, #1
|
|
80032ce: e000 b.n 80032d2 <HAL_ADCEx_MultiModeConfigChannel+0xaa>
|
|
80032d0: 2300 movs r3, #0
|
|
80032d2: 2b00 cmp r3, #0
|
|
80032d4: d15c bne.n 8003390 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
|
|
80032d6: 68bb ldr r3, [r7, #8]
|
|
80032d8: 689b ldr r3, [r3, #8]
|
|
80032da: f003 0303 and.w r3, r3, #3
|
|
80032de: 2b01 cmp r3, #1
|
|
80032e0: d107 bne.n 80032f2 <HAL_ADCEx_MultiModeConfigChannel+0xca>
|
|
80032e2: 68bb ldr r3, [r7, #8]
|
|
80032e4: 681b ldr r3, [r3, #0]
|
|
80032e6: f003 0301 and.w r3, r3, #1
|
|
80032ea: 2b01 cmp r3, #1
|
|
80032ec: d101 bne.n 80032f2 <HAL_ADCEx_MultiModeConfigChannel+0xca>
|
|
80032ee: 2301 movs r3, #1
|
|
80032f0: e000 b.n 80032f4 <HAL_ADCEx_MultiModeConfigChannel+0xcc>
|
|
80032f2: 2300 movs r3, #0
|
|
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
|
80032f4: 2b00 cmp r3, #0
|
|
80032f6: d14b bne.n 8003390 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
{
|
|
MODIFY_REG(tmpADC_Common->CCR ,
|
|
80032f8: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80032fa: 689b ldr r3, [r3, #8]
|
|
80032fc: f423 6371 bic.w r3, r3, #3856 @ 0xf10
|
|
8003300: f023 030f bic.w r3, r3, #15
|
|
8003304: 683a ldr r2, [r7, #0]
|
|
8003306: 6811 ldr r1, [r2, #0]
|
|
8003308: 683a ldr r2, [r7, #0]
|
|
800330a: 6892 ldr r2, [r2, #8]
|
|
800330c: 430a orrs r2, r1
|
|
800330e: 431a orrs r2, r3
|
|
8003310: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8003312: 609a str r2, [r3, #8]
|
|
if(multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
8003314: e03c b.n 8003390 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
multimode->TwoSamplingDelay );
|
|
}
|
|
}
|
|
else /* ADC_MODE_INDEPENDENT */
|
|
{
|
|
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
|
|
8003316: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8003318: 689b ldr r3, [r3, #8]
|
|
800331a: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
800331e: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8003320: 609a str r2, [r3, #8]
|
|
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Multimode mode selection */
|
|
/* - Multimode delay */
|
|
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
|
8003322: 687b ldr r3, [r7, #4]
|
|
8003324: 681b ldr r3, [r3, #0]
|
|
8003326: 689b ldr r3, [r3, #8]
|
|
8003328: f003 0303 and.w r3, r3, #3
|
|
800332c: 2b01 cmp r3, #1
|
|
800332e: d108 bne.n 8003342 <HAL_ADCEx_MultiModeConfigChannel+0x11a>
|
|
8003330: 687b ldr r3, [r7, #4]
|
|
8003332: 681b ldr r3, [r3, #0]
|
|
8003334: 681b ldr r3, [r3, #0]
|
|
8003336: f003 0301 and.w r3, r3, #1
|
|
800333a: 2b01 cmp r3, #1
|
|
800333c: d101 bne.n 8003342 <HAL_ADCEx_MultiModeConfigChannel+0x11a>
|
|
800333e: 2301 movs r3, #1
|
|
8003340: e000 b.n 8003344 <HAL_ADCEx_MultiModeConfigChannel+0x11c>
|
|
8003342: 2300 movs r3, #0
|
|
8003344: 2b00 cmp r3, #0
|
|
8003346: d123 bne.n 8003390 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
(ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) )
|
|
8003348: 68bb ldr r3, [r7, #8]
|
|
800334a: 689b ldr r3, [r3, #8]
|
|
800334c: f003 0303 and.w r3, r3, #3
|
|
8003350: 2b01 cmp r3, #1
|
|
8003352: d107 bne.n 8003364 <HAL_ADCEx_MultiModeConfigChannel+0x13c>
|
|
8003354: 68bb ldr r3, [r7, #8]
|
|
8003356: 681b ldr r3, [r3, #0]
|
|
8003358: f003 0301 and.w r3, r3, #1
|
|
800335c: 2b01 cmp r3, #1
|
|
800335e: d101 bne.n 8003364 <HAL_ADCEx_MultiModeConfigChannel+0x13c>
|
|
8003360: 2301 movs r3, #1
|
|
8003362: e000 b.n 8003366 <HAL_ADCEx_MultiModeConfigChannel+0x13e>
|
|
8003364: 2300 movs r3, #0
|
|
if ((ADC_IS_ENABLE(hadc) == RESET) &&
|
|
8003366: 2b00 cmp r3, #0
|
|
8003368: d112 bne.n 8003390 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
{
|
|
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY);
|
|
800336a: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
800336c: 689b ldr r3, [r3, #8]
|
|
800336e: f423 6371 bic.w r3, r3, #3856 @ 0xf10
|
|
8003372: f023 030f bic.w r3, r3, #15
|
|
8003376: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8003378: 6093 str r3, [r2, #8]
|
|
if(multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
800337a: e009 b.n 8003390 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
/* If one of the ADC sharing the same common group is enabled, no update */
|
|
/* could be done on neither of the multimode structure parameters. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
800337c: 687b ldr r3, [r7, #4]
|
|
800337e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003380: f043 0220 orr.w r2, r3, #32
|
|
8003384: 687b ldr r3, [r7, #4]
|
|
8003386: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8003388: 2301 movs r3, #1
|
|
800338a: f887 305f strb.w r3, [r7, #95] @ 0x5f
|
|
800338e: e000 b.n 8003392 <HAL_ADCEx_MultiModeConfigChannel+0x16a>
|
|
if(multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
8003390: bf00 nop
|
|
}
|
|
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8003392: 687b ldr r3, [r7, #4]
|
|
8003394: 2200 movs r2, #0
|
|
8003396: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
800339a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f
|
|
}
|
|
800339e: 4618 mov r0, r3
|
|
80033a0: 3764 adds r7, #100 @ 0x64
|
|
80033a2: 46bd mov sp, r7
|
|
80033a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80033a8: 4770 bx lr
|
|
80033aa: bf00 nop
|
|
80033ac: 50000100 .word 0x50000100
|
|
80033b0: 50000300 .word 0x50000300
|
|
|
|
080033b4 <ADC_DMAConvCplt>:
|
|
* @brief DMA transfer complete callback.
|
|
* @param hdma pointer to DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80033b4: b580 push {r7, lr}
|
|
80033b6: b084 sub sp, #16
|
|
80033b8: af00 add r7, sp, #0
|
|
80033ba: 6078 str r0, [r7, #4]
|
|
/* Retrieve ADC handle corresponding to current DMA handle */
|
|
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
80033bc: 687b ldr r3, [r7, #4]
|
|
80033be: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80033c0: 60fb str r3, [r7, #12]
|
|
|
|
/* Update state machine on conversion status if not in error state */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
|
|
80033c2: 68fb ldr r3, [r7, #12]
|
|
80033c4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80033c6: f003 0350 and.w r3, r3, #80 @ 0x50
|
|
80033ca: 2b00 cmp r3, #0
|
|
80033cc: d126 bne.n 800341c <ADC_DMAConvCplt+0x68>
|
|
{
|
|
/* Update ADC state machine */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
|
|
80033ce: 68fb ldr r3, [r7, #12]
|
|
80033d0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80033d2: f443 7200 orr.w r2, r3, #512 @ 0x200
|
|
80033d6: 68fb ldr r3, [r7, #12]
|
|
80033d8: 641a str r2, [r3, #64] @ 0x40
|
|
/* Determine whether any further conversion upcoming on group regular */
|
|
/* by external trigger, continuous mode or scan sequence on going. */
|
|
/* Note: On STM32F3 devices, in case of sequencer enabled */
|
|
/* (several ranks selected), end of conversion flag is raised */
|
|
/* at the end of the sequence. */
|
|
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
|
|
80033da: 68fb ldr r3, [r7, #12]
|
|
80033dc: 681b ldr r3, [r3, #0]
|
|
80033de: 68db ldr r3, [r3, #12]
|
|
80033e0: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
80033e4: 2b00 cmp r3, #0
|
|
80033e6: d115 bne.n 8003414 <ADC_DMAConvCplt+0x60>
|
|
(hadc->Init.ContinuousConvMode == DISABLE) )
|
|
80033e8: 68fb ldr r3, [r7, #12]
|
|
80033ea: 7e5b ldrb r3, [r3, #25]
|
|
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
|
|
80033ec: 2b00 cmp r3, #0
|
|
80033ee: d111 bne.n 8003414 <ADC_DMAConvCplt+0x60>
|
|
{
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
80033f0: 68fb ldr r3, [r7, #12]
|
|
80033f2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80033f4: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
80033f8: 68fb ldr r3, [r7, #12]
|
|
80033fa: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
|
|
80033fc: 68fb ldr r3, [r7, #12]
|
|
80033fe: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003400: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8003404: 2b00 cmp r3, #0
|
|
8003406: d105 bne.n 8003414 <ADC_DMAConvCplt+0x60>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
|
8003408: 68fb ldr r3, [r7, #12]
|
|
800340a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800340c: f043 0201 orr.w r2, r3, #1
|
|
8003410: 68fb ldr r3, [r7, #12]
|
|
8003412: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Conversion complete callback */
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
hadc->ConvCpltCallback(hadc);
|
|
#else
|
|
HAL_ADC_ConvCpltCallback(hadc);
|
|
8003414: 68f8 ldr r0, [r7, #12]
|
|
8003416: f7fd fd5b bl 8000ed0 <HAL_ADC_ConvCpltCallback>
|
|
else
|
|
{
|
|
/* Call DMA error callback */
|
|
hadc->DMA_Handle->XferErrorCallback(hdma);
|
|
}
|
|
}
|
|
800341a: e004 b.n 8003426 <ADC_DMAConvCplt+0x72>
|
|
hadc->DMA_Handle->XferErrorCallback(hdma);
|
|
800341c: 68fb ldr r3, [r7, #12]
|
|
800341e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003420: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003422: 6878 ldr r0, [r7, #4]
|
|
8003424: 4798 blx r3
|
|
}
|
|
8003426: bf00 nop
|
|
8003428: 3710 adds r7, #16
|
|
800342a: 46bd mov sp, r7
|
|
800342c: bd80 pop {r7, pc}
|
|
|
|
0800342e <ADC_DMAHalfConvCplt>:
|
|
* @brief DMA half transfer complete callback.
|
|
* @param hdma pointer to DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800342e: b580 push {r7, lr}
|
|
8003430: b084 sub sp, #16
|
|
8003432: af00 add r7, sp, #0
|
|
8003434: 6078 str r0, [r7, #4]
|
|
/* Retrieve ADC handle corresponding to current DMA handle */
|
|
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
8003436: 687b ldr r3, [r7, #4]
|
|
8003438: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800343a: 60fb str r3, [r7, #12]
|
|
|
|
/* Half conversion callback */
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
hadc->ConvHalfCpltCallback(hadc);
|
|
#else
|
|
HAL_ADC_ConvHalfCpltCallback(hadc);
|
|
800343c: 68f8 ldr r0, [r7, #12]
|
|
800343e: f7fe ff89 bl 8002354 <HAL_ADC_ConvHalfCpltCallback>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
}
|
|
8003442: bf00 nop
|
|
8003444: 3710 adds r7, #16
|
|
8003446: 46bd mov sp, r7
|
|
8003448: bd80 pop {r7, pc}
|
|
|
|
0800344a <ADC_DMAError>:
|
|
* @brief DMA error callback
|
|
* @param hdma pointer to DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800344a: b580 push {r7, lr}
|
|
800344c: b084 sub sp, #16
|
|
800344e: af00 add r7, sp, #0
|
|
8003450: 6078 str r0, [r7, #4]
|
|
/* Retrieve ADC handle corresponding to current DMA handle */
|
|
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
|
|
8003452: 687b ldr r3, [r7, #4]
|
|
8003454: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003456: 60fb str r3, [r7, #12]
|
|
|
|
/* Set ADC state */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
|
|
8003458: 68fb ldr r3, [r7, #12]
|
|
800345a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800345c: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8003460: 68fb ldr r3, [r7, #12]
|
|
8003462: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set ADC error code to DMA error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
|
|
8003464: 68fb ldr r3, [r7, #12]
|
|
8003466: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8003468: f043 0204 orr.w r2, r3, #4
|
|
800346c: 68fb ldr r3, [r7, #12]
|
|
800346e: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Error callback */
|
|
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
|
hadc->ErrorCallback(hadc);
|
|
#else
|
|
HAL_ADC_ErrorCallback(hadc);
|
|
8003470: 68f8 ldr r0, [r7, #12]
|
|
8003472: f7fe ff83 bl 800237c <HAL_ADC_ErrorCallback>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
}
|
|
8003476: bf00 nop
|
|
8003478: 3710 adds r7, #16
|
|
800347a: 46bd mov sp, r7
|
|
800347c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08003480 <ADC_Enable>:
|
|
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8003480: b580 push {r7, lr}
|
|
8003482: b084 sub sp, #16
|
|
8003484: af00 add r7, sp, #0
|
|
8003486: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
8003488: 2300 movs r3, #0
|
|
800348a: 60fb str r3, [r7, #12]
|
|
|
|
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
|
|
/* enabling phase not yet completed: flag ADC ready not yet set). */
|
|
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
|
|
/* causes: ADC clock not running, ...). */
|
|
if (ADC_IS_ENABLE(hadc) == RESET)
|
|
800348c: 687b ldr r3, [r7, #4]
|
|
800348e: 681b ldr r3, [r3, #0]
|
|
8003490: 689b ldr r3, [r3, #8]
|
|
8003492: f003 0303 and.w r3, r3, #3
|
|
8003496: 2b01 cmp r3, #1
|
|
8003498: d108 bne.n 80034ac <ADC_Enable+0x2c>
|
|
800349a: 687b ldr r3, [r7, #4]
|
|
800349c: 681b ldr r3, [r3, #0]
|
|
800349e: 681b ldr r3, [r3, #0]
|
|
80034a0: f003 0301 and.w r3, r3, #1
|
|
80034a4: 2b01 cmp r3, #1
|
|
80034a6: d101 bne.n 80034ac <ADC_Enable+0x2c>
|
|
80034a8: 2301 movs r3, #1
|
|
80034aa: e000 b.n 80034ae <ADC_Enable+0x2e>
|
|
80034ac: 2300 movs r3, #0
|
|
80034ae: 2b00 cmp r3, #0
|
|
80034b0: d143 bne.n 800353a <ADC_Enable+0xba>
|
|
{
|
|
/* Check if conditions to enable the ADC are fulfilled */
|
|
if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
|
|
80034b2: 687b ldr r3, [r7, #4]
|
|
80034b4: 681b ldr r3, [r3, #0]
|
|
80034b6: 689a ldr r2, [r3, #8]
|
|
80034b8: 4b22 ldr r3, [pc, #136] @ (8003544 <ADC_Enable+0xc4>)
|
|
80034ba: 4013 ands r3, r2
|
|
80034bc: 2b00 cmp r3, #0
|
|
80034be: d00d beq.n 80034dc <ADC_Enable+0x5c>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
80034c0: 687b ldr r3, [r7, #4]
|
|
80034c2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80034c4: f043 0210 orr.w r2, r3, #16
|
|
80034c8: 687b ldr r3, [r7, #4]
|
|
80034ca: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
80034cc: 687b ldr r3, [r7, #4]
|
|
80034ce: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80034d0: f043 0201 orr.w r2, r3, #1
|
|
80034d4: 687b ldr r3, [r7, #4]
|
|
80034d6: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
return HAL_ERROR;
|
|
80034d8: 2301 movs r3, #1
|
|
80034da: e02f b.n 800353c <ADC_Enable+0xbc>
|
|
}
|
|
|
|
/* Enable the ADC peripheral */
|
|
__HAL_ADC_ENABLE(hadc);
|
|
80034dc: 687b ldr r3, [r7, #4]
|
|
80034de: 681b ldr r3, [r3, #0]
|
|
80034e0: 689a ldr r2, [r3, #8]
|
|
80034e2: 687b ldr r3, [r7, #4]
|
|
80034e4: 681b ldr r3, [r3, #0]
|
|
80034e6: f042 0201 orr.w r2, r2, #1
|
|
80034ea: 609a str r2, [r3, #8]
|
|
|
|
/* Wait for ADC effectively enabled */
|
|
tickstart = HAL_GetTick();
|
|
80034ec: f7fe ff02 bl 80022f4 <HAL_GetTick>
|
|
80034f0: 60f8 str r0, [r7, #12]
|
|
|
|
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
|
|
80034f2: e01b b.n 800352c <ADC_Enable+0xac>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
|
|
80034f4: f7fe fefe bl 80022f4 <HAL_GetTick>
|
|
80034f8: 4602 mov r2, r0
|
|
80034fa: 68fb ldr r3, [r7, #12]
|
|
80034fc: 1ad3 subs r3, r2, r3
|
|
80034fe: 2b02 cmp r3, #2
|
|
8003500: d914 bls.n 800352c <ADC_Enable+0xac>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
|
|
8003502: 687b ldr r3, [r7, #4]
|
|
8003504: 681b ldr r3, [r3, #0]
|
|
8003506: 681b ldr r3, [r3, #0]
|
|
8003508: f003 0301 and.w r3, r3, #1
|
|
800350c: 2b01 cmp r3, #1
|
|
800350e: d00d beq.n 800352c <ADC_Enable+0xac>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8003510: 687b ldr r3, [r7, #4]
|
|
8003512: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003514: f043 0210 orr.w r2, r3, #16
|
|
8003518: 687b ldr r3, [r7, #4]
|
|
800351a: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
800351c: 687b ldr r3, [r7, #4]
|
|
800351e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8003520: f043 0201 orr.w r2, r3, #1
|
|
8003524: 687b ldr r3, [r7, #4]
|
|
8003526: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
return HAL_ERROR;
|
|
8003528: 2301 movs r3, #1
|
|
800352a: e007 b.n 800353c <ADC_Enable+0xbc>
|
|
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
|
|
800352c: 687b ldr r3, [r7, #4]
|
|
800352e: 681b ldr r3, [r3, #0]
|
|
8003530: 681b ldr r3, [r3, #0]
|
|
8003532: f003 0301 and.w r3, r3, #1
|
|
8003536: 2b01 cmp r3, #1
|
|
8003538: d1dc bne.n 80034f4 <ADC_Enable+0x74>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
800353a: 2300 movs r3, #0
|
|
}
|
|
800353c: 4618 mov r0, r3
|
|
800353e: 3710 adds r7, #16
|
|
8003540: 46bd mov sp, r7
|
|
8003542: bd80 pop {r7, pc}
|
|
8003544: 8000003f .word 0x8000003f
|
|
|
|
08003548 <ADC_Disable>:
|
|
* stopped.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8003548: b580 push {r7, lr}
|
|
800354a: b084 sub sp, #16
|
|
800354c: af00 add r7, sp, #0
|
|
800354e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
8003550: 2300 movs r3, #0
|
|
8003552: 60fb str r3, [r7, #12]
|
|
|
|
/* Verification if ADC is not already disabled: */
|
|
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
|
|
/* disabled. */
|
|
if (ADC_IS_ENABLE(hadc) != RESET )
|
|
8003554: 687b ldr r3, [r7, #4]
|
|
8003556: 681b ldr r3, [r3, #0]
|
|
8003558: 689b ldr r3, [r3, #8]
|
|
800355a: f003 0303 and.w r3, r3, #3
|
|
800355e: 2b01 cmp r3, #1
|
|
8003560: d108 bne.n 8003574 <ADC_Disable+0x2c>
|
|
8003562: 687b ldr r3, [r7, #4]
|
|
8003564: 681b ldr r3, [r3, #0]
|
|
8003566: 681b ldr r3, [r3, #0]
|
|
8003568: f003 0301 and.w r3, r3, #1
|
|
800356c: 2b01 cmp r3, #1
|
|
800356e: d101 bne.n 8003574 <ADC_Disable+0x2c>
|
|
8003570: 2301 movs r3, #1
|
|
8003572: e000 b.n 8003576 <ADC_Disable+0x2e>
|
|
8003574: 2300 movs r3, #0
|
|
8003576: 2b00 cmp r3, #0
|
|
8003578: d047 beq.n 800360a <ADC_Disable+0xc2>
|
|
{
|
|
/* Check if conditions to disable the ADC are fulfilled */
|
|
if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
|
|
800357a: 687b ldr r3, [r7, #4]
|
|
800357c: 681b ldr r3, [r3, #0]
|
|
800357e: 689b ldr r3, [r3, #8]
|
|
8003580: f003 030d and.w r3, r3, #13
|
|
8003584: 2b01 cmp r3, #1
|
|
8003586: d10f bne.n 80035a8 <ADC_Disable+0x60>
|
|
{
|
|
/* Disable the ADC peripheral */
|
|
__HAL_ADC_DISABLE(hadc);
|
|
8003588: 687b ldr r3, [r7, #4]
|
|
800358a: 681b ldr r3, [r3, #0]
|
|
800358c: 689a ldr r2, [r3, #8]
|
|
800358e: 687b ldr r3, [r7, #4]
|
|
8003590: 681b ldr r3, [r3, #0]
|
|
8003592: f042 0202 orr.w r2, r2, #2
|
|
8003596: 609a str r2, [r3, #8]
|
|
8003598: 687b ldr r3, [r7, #4]
|
|
800359a: 681b ldr r3, [r3, #0]
|
|
800359c: 2203 movs r2, #3
|
|
800359e: 601a str r2, [r3, #0]
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Wait for ADC effectively disabled */
|
|
tickstart = HAL_GetTick();
|
|
80035a0: f7fe fea8 bl 80022f4 <HAL_GetTick>
|
|
80035a4: 60f8 str r0, [r7, #12]
|
|
|
|
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
|
|
80035a6: e029 b.n 80035fc <ADC_Disable+0xb4>
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
80035a8: 687b ldr r3, [r7, #4]
|
|
80035aa: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80035ac: f043 0210 orr.w r2, r3, #16
|
|
80035b0: 687b ldr r3, [r7, #4]
|
|
80035b2: 641a str r2, [r3, #64] @ 0x40
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
80035b4: 687b ldr r3, [r7, #4]
|
|
80035b6: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80035b8: f043 0201 orr.w r2, r3, #1
|
|
80035bc: 687b ldr r3, [r7, #4]
|
|
80035be: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
80035c0: 2301 movs r3, #1
|
|
80035c2: e023 b.n 800360c <ADC_Disable+0xc4>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
|
|
80035c4: f7fe fe96 bl 80022f4 <HAL_GetTick>
|
|
80035c8: 4602 mov r2, r0
|
|
80035ca: 68fb ldr r3, [r7, #12]
|
|
80035cc: 1ad3 subs r3, r2, r3
|
|
80035ce: 2b02 cmp r3, #2
|
|
80035d0: d914 bls.n 80035fc <ADC_Disable+0xb4>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
|
|
80035d2: 687b ldr r3, [r7, #4]
|
|
80035d4: 681b ldr r3, [r3, #0]
|
|
80035d6: 689b ldr r3, [r3, #8]
|
|
80035d8: f003 0301 and.w r3, r3, #1
|
|
80035dc: 2b01 cmp r3, #1
|
|
80035de: d10d bne.n 80035fc <ADC_Disable+0xb4>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
80035e0: 687b ldr r3, [r7, #4]
|
|
80035e2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80035e4: f043 0210 orr.w r2, r3, #16
|
|
80035e8: 687b ldr r3, [r7, #4]
|
|
80035ea: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Set ADC error code to ADC IP internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
80035ec: 687b ldr r3, [r7, #4]
|
|
80035ee: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80035f0: f043 0201 orr.w r2, r3, #1
|
|
80035f4: 687b ldr r3, [r7, #4]
|
|
80035f6: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
return HAL_ERROR;
|
|
80035f8: 2301 movs r3, #1
|
|
80035fa: e007 b.n 800360c <ADC_Disable+0xc4>
|
|
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
|
|
80035fc: 687b ldr r3, [r7, #4]
|
|
80035fe: 681b ldr r3, [r3, #0]
|
|
8003600: 689b ldr r3, [r3, #8]
|
|
8003602: f003 0301 and.w r3, r3, #1
|
|
8003606: 2b01 cmp r3, #1
|
|
8003608: d0dc beq.n 80035c4 <ADC_Disable+0x7c>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
800360a: 2300 movs r3, #0
|
|
}
|
|
800360c: 4618 mov r0, r3
|
|
800360e: 3710 adds r7, #16
|
|
8003610: 46bd mov sp, r7
|
|
8003612: bd80 pop {r7, pc}
|
|
|
|
08003614 <HAL_CAN_Init>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
|
|
{
|
|
8003614: b580 push {r7, lr}
|
|
8003616: b084 sub sp, #16
|
|
8003618: af00 add r7, sp, #0
|
|
800361a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Check CAN handle */
|
|
if (hcan == NULL)
|
|
800361c: 687b ldr r3, [r7, #4]
|
|
800361e: 2b00 cmp r3, #0
|
|
8003620: d101 bne.n 8003626 <HAL_CAN_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003622: 2301 movs r3, #1
|
|
8003624: e0ed b.n 8003802 <HAL_CAN_Init+0x1ee>
|
|
/* Init the low level hardware: CLOCK, NVIC */
|
|
hcan->MspInitCallback(hcan);
|
|
}
|
|
|
|
#else
|
|
if (hcan->State == HAL_CAN_STATE_RESET)
|
|
8003626: 687b ldr r3, [r7, #4]
|
|
8003628: f893 3020 ldrb.w r3, [r3, #32]
|
|
800362c: b2db uxtb r3, r3
|
|
800362e: 2b00 cmp r3, #0
|
|
8003630: d102 bne.n 8003638 <HAL_CAN_Init+0x24>
|
|
{
|
|
/* Init the low level hardware: CLOCK, NVIC */
|
|
HAL_CAN_MspInit(hcan);
|
|
8003632: 6878 ldr r0, [r7, #4]
|
|
8003634: f7fe fc9a bl 8001f6c <HAL_CAN_MspInit>
|
|
}
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
|
|
/* Request initialisation */
|
|
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
|
|
8003638: 687b ldr r3, [r7, #4]
|
|
800363a: 681b ldr r3, [r3, #0]
|
|
800363c: 681a ldr r2, [r3, #0]
|
|
800363e: 687b ldr r3, [r7, #4]
|
|
8003640: 681b ldr r3, [r3, #0]
|
|
8003642: f042 0201 orr.w r2, r2, #1
|
|
8003646: 601a str r2, [r3, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003648: f7fe fe54 bl 80022f4 <HAL_GetTick>
|
|
800364c: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait initialisation acknowledge */
|
|
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
|
|
800364e: e012 b.n 8003676 <HAL_CAN_Init+0x62>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
|
|
8003650: f7fe fe50 bl 80022f4 <HAL_GetTick>
|
|
8003654: 4602 mov r2, r0
|
|
8003656: 68fb ldr r3, [r7, #12]
|
|
8003658: 1ad3 subs r3, r2, r3
|
|
800365a: 2b0a cmp r3, #10
|
|
800365c: d90b bls.n 8003676 <HAL_CAN_Init+0x62>
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
|
|
800365e: 687b ldr r3, [r7, #4]
|
|
8003660: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003662: f443 3200 orr.w r2, r3, #131072 @ 0x20000
|
|
8003666: 687b ldr r3, [r7, #4]
|
|
8003668: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_ERROR;
|
|
800366a: 687b ldr r3, [r7, #4]
|
|
800366c: 2205 movs r2, #5
|
|
800366e: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_ERROR;
|
|
8003672: 2301 movs r3, #1
|
|
8003674: e0c5 b.n 8003802 <HAL_CAN_Init+0x1ee>
|
|
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
|
|
8003676: 687b ldr r3, [r7, #4]
|
|
8003678: 681b ldr r3, [r3, #0]
|
|
800367a: 685b ldr r3, [r3, #4]
|
|
800367c: f003 0301 and.w r3, r3, #1
|
|
8003680: 2b00 cmp r3, #0
|
|
8003682: d0e5 beq.n 8003650 <HAL_CAN_Init+0x3c>
|
|
}
|
|
}
|
|
|
|
/* Exit from sleep mode */
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
|
|
8003684: 687b ldr r3, [r7, #4]
|
|
8003686: 681b ldr r3, [r3, #0]
|
|
8003688: 681a ldr r2, [r3, #0]
|
|
800368a: 687b ldr r3, [r7, #4]
|
|
800368c: 681b ldr r3, [r3, #0]
|
|
800368e: f022 0202 bic.w r2, r2, #2
|
|
8003692: 601a str r2, [r3, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8003694: f7fe fe2e bl 80022f4 <HAL_GetTick>
|
|
8003698: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check Sleep mode leave acknowledge */
|
|
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
|
|
800369a: e012 b.n 80036c2 <HAL_CAN_Init+0xae>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
|
|
800369c: f7fe fe2a bl 80022f4 <HAL_GetTick>
|
|
80036a0: 4602 mov r2, r0
|
|
80036a2: 68fb ldr r3, [r7, #12]
|
|
80036a4: 1ad3 subs r3, r2, r3
|
|
80036a6: 2b0a cmp r3, #10
|
|
80036a8: d90b bls.n 80036c2 <HAL_CAN_Init+0xae>
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
|
|
80036aa: 687b ldr r3, [r7, #4]
|
|
80036ac: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80036ae: f443 3200 orr.w r2, r3, #131072 @ 0x20000
|
|
80036b2: 687b ldr r3, [r7, #4]
|
|
80036b4: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_ERROR;
|
|
80036b6: 687b ldr r3, [r7, #4]
|
|
80036b8: 2205 movs r2, #5
|
|
80036ba: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_ERROR;
|
|
80036be: 2301 movs r3, #1
|
|
80036c0: e09f b.n 8003802 <HAL_CAN_Init+0x1ee>
|
|
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
|
|
80036c2: 687b ldr r3, [r7, #4]
|
|
80036c4: 681b ldr r3, [r3, #0]
|
|
80036c6: 685b ldr r3, [r3, #4]
|
|
80036c8: f003 0302 and.w r3, r3, #2
|
|
80036cc: 2b00 cmp r3, #0
|
|
80036ce: d1e5 bne.n 800369c <HAL_CAN_Init+0x88>
|
|
}
|
|
}
|
|
|
|
/* Set the time triggered communication mode */
|
|
if (hcan->Init.TimeTriggeredMode == ENABLE)
|
|
80036d0: 687b ldr r3, [r7, #4]
|
|
80036d2: 7e1b ldrb r3, [r3, #24]
|
|
80036d4: 2b01 cmp r3, #1
|
|
80036d6: d108 bne.n 80036ea <HAL_CAN_Init+0xd6>
|
|
{
|
|
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
|
|
80036d8: 687b ldr r3, [r7, #4]
|
|
80036da: 681b ldr r3, [r3, #0]
|
|
80036dc: 681a ldr r2, [r3, #0]
|
|
80036de: 687b ldr r3, [r7, #4]
|
|
80036e0: 681b ldr r3, [r3, #0]
|
|
80036e2: f042 0280 orr.w r2, r2, #128 @ 0x80
|
|
80036e6: 601a str r2, [r3, #0]
|
|
80036e8: e007 b.n 80036fa <HAL_CAN_Init+0xe6>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
|
|
80036ea: 687b ldr r3, [r7, #4]
|
|
80036ec: 681b ldr r3, [r3, #0]
|
|
80036ee: 681a ldr r2, [r3, #0]
|
|
80036f0: 687b ldr r3, [r7, #4]
|
|
80036f2: 681b ldr r3, [r3, #0]
|
|
80036f4: f022 0280 bic.w r2, r2, #128 @ 0x80
|
|
80036f8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set the automatic bus-off management */
|
|
if (hcan->Init.AutoBusOff == ENABLE)
|
|
80036fa: 687b ldr r3, [r7, #4]
|
|
80036fc: 7e5b ldrb r3, [r3, #25]
|
|
80036fe: 2b01 cmp r3, #1
|
|
8003700: d108 bne.n 8003714 <HAL_CAN_Init+0x100>
|
|
{
|
|
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
|
|
8003702: 687b ldr r3, [r7, #4]
|
|
8003704: 681b ldr r3, [r3, #0]
|
|
8003706: 681a ldr r2, [r3, #0]
|
|
8003708: 687b ldr r3, [r7, #4]
|
|
800370a: 681b ldr r3, [r3, #0]
|
|
800370c: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
8003710: 601a str r2, [r3, #0]
|
|
8003712: e007 b.n 8003724 <HAL_CAN_Init+0x110>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
|
|
8003714: 687b ldr r3, [r7, #4]
|
|
8003716: 681b ldr r3, [r3, #0]
|
|
8003718: 681a ldr r2, [r3, #0]
|
|
800371a: 687b ldr r3, [r7, #4]
|
|
800371c: 681b ldr r3, [r3, #0]
|
|
800371e: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8003722: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set the automatic wake-up mode */
|
|
if (hcan->Init.AutoWakeUp == ENABLE)
|
|
8003724: 687b ldr r3, [r7, #4]
|
|
8003726: 7e9b ldrb r3, [r3, #26]
|
|
8003728: 2b01 cmp r3, #1
|
|
800372a: d108 bne.n 800373e <HAL_CAN_Init+0x12a>
|
|
{
|
|
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
|
|
800372c: 687b ldr r3, [r7, #4]
|
|
800372e: 681b ldr r3, [r3, #0]
|
|
8003730: 681a ldr r2, [r3, #0]
|
|
8003732: 687b ldr r3, [r7, #4]
|
|
8003734: 681b ldr r3, [r3, #0]
|
|
8003736: f042 0220 orr.w r2, r2, #32
|
|
800373a: 601a str r2, [r3, #0]
|
|
800373c: e007 b.n 800374e <HAL_CAN_Init+0x13a>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
|
|
800373e: 687b ldr r3, [r7, #4]
|
|
8003740: 681b ldr r3, [r3, #0]
|
|
8003742: 681a ldr r2, [r3, #0]
|
|
8003744: 687b ldr r3, [r7, #4]
|
|
8003746: 681b ldr r3, [r3, #0]
|
|
8003748: f022 0220 bic.w r2, r2, #32
|
|
800374c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set the automatic retransmission */
|
|
if (hcan->Init.AutoRetransmission == ENABLE)
|
|
800374e: 687b ldr r3, [r7, #4]
|
|
8003750: 7edb ldrb r3, [r3, #27]
|
|
8003752: 2b01 cmp r3, #1
|
|
8003754: d108 bne.n 8003768 <HAL_CAN_Init+0x154>
|
|
{
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
|
|
8003756: 687b ldr r3, [r7, #4]
|
|
8003758: 681b ldr r3, [r3, #0]
|
|
800375a: 681a ldr r2, [r3, #0]
|
|
800375c: 687b ldr r3, [r7, #4]
|
|
800375e: 681b ldr r3, [r3, #0]
|
|
8003760: f022 0210 bic.w r2, r2, #16
|
|
8003764: 601a str r2, [r3, #0]
|
|
8003766: e007 b.n 8003778 <HAL_CAN_Init+0x164>
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
|
|
8003768: 687b ldr r3, [r7, #4]
|
|
800376a: 681b ldr r3, [r3, #0]
|
|
800376c: 681a ldr r2, [r3, #0]
|
|
800376e: 687b ldr r3, [r7, #4]
|
|
8003770: 681b ldr r3, [r3, #0]
|
|
8003772: f042 0210 orr.w r2, r2, #16
|
|
8003776: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set the receive FIFO locked mode */
|
|
if (hcan->Init.ReceiveFifoLocked == ENABLE)
|
|
8003778: 687b ldr r3, [r7, #4]
|
|
800377a: 7f1b ldrb r3, [r3, #28]
|
|
800377c: 2b01 cmp r3, #1
|
|
800377e: d108 bne.n 8003792 <HAL_CAN_Init+0x17e>
|
|
{
|
|
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
|
|
8003780: 687b ldr r3, [r7, #4]
|
|
8003782: 681b ldr r3, [r3, #0]
|
|
8003784: 681a ldr r2, [r3, #0]
|
|
8003786: 687b ldr r3, [r7, #4]
|
|
8003788: 681b ldr r3, [r3, #0]
|
|
800378a: f042 0208 orr.w r2, r2, #8
|
|
800378e: 601a str r2, [r3, #0]
|
|
8003790: e007 b.n 80037a2 <HAL_CAN_Init+0x18e>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
|
|
8003792: 687b ldr r3, [r7, #4]
|
|
8003794: 681b ldr r3, [r3, #0]
|
|
8003796: 681a ldr r2, [r3, #0]
|
|
8003798: 687b ldr r3, [r7, #4]
|
|
800379a: 681b ldr r3, [r3, #0]
|
|
800379c: f022 0208 bic.w r2, r2, #8
|
|
80037a0: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set the transmit FIFO priority */
|
|
if (hcan->Init.TransmitFifoPriority == ENABLE)
|
|
80037a2: 687b ldr r3, [r7, #4]
|
|
80037a4: 7f5b ldrb r3, [r3, #29]
|
|
80037a6: 2b01 cmp r3, #1
|
|
80037a8: d108 bne.n 80037bc <HAL_CAN_Init+0x1a8>
|
|
{
|
|
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
|
|
80037aa: 687b ldr r3, [r7, #4]
|
|
80037ac: 681b ldr r3, [r3, #0]
|
|
80037ae: 681a ldr r2, [r3, #0]
|
|
80037b0: 687b ldr r3, [r7, #4]
|
|
80037b2: 681b ldr r3, [r3, #0]
|
|
80037b4: f042 0204 orr.w r2, r2, #4
|
|
80037b8: 601a str r2, [r3, #0]
|
|
80037ba: e007 b.n 80037cc <HAL_CAN_Init+0x1b8>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
|
|
80037bc: 687b ldr r3, [r7, #4]
|
|
80037be: 681b ldr r3, [r3, #0]
|
|
80037c0: 681a ldr r2, [r3, #0]
|
|
80037c2: 687b ldr r3, [r7, #4]
|
|
80037c4: 681b ldr r3, [r3, #0]
|
|
80037c6: f022 0204 bic.w r2, r2, #4
|
|
80037ca: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set the bit timing register */
|
|
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
|
|
80037cc: 687b ldr r3, [r7, #4]
|
|
80037ce: 689a ldr r2, [r3, #8]
|
|
80037d0: 687b ldr r3, [r7, #4]
|
|
80037d2: 68db ldr r3, [r3, #12]
|
|
80037d4: 431a orrs r2, r3
|
|
80037d6: 687b ldr r3, [r7, #4]
|
|
80037d8: 691b ldr r3, [r3, #16]
|
|
80037da: 431a orrs r2, r3
|
|
80037dc: 687b ldr r3, [r7, #4]
|
|
80037de: 695b ldr r3, [r3, #20]
|
|
80037e0: ea42 0103 orr.w r1, r2, r3
|
|
80037e4: 687b ldr r3, [r7, #4]
|
|
80037e6: 685b ldr r3, [r3, #4]
|
|
80037e8: 1e5a subs r2, r3, #1
|
|
80037ea: 687b ldr r3, [r7, #4]
|
|
80037ec: 681b ldr r3, [r3, #0]
|
|
80037ee: 430a orrs r2, r1
|
|
80037f0: 61da str r2, [r3, #28]
|
|
hcan->Init.TimeSeg1 |
|
|
hcan->Init.TimeSeg2 |
|
|
(hcan->Init.Prescaler - 1U)));
|
|
|
|
/* Initialize the error code */
|
|
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
|
|
80037f2: 687b ldr r3, [r7, #4]
|
|
80037f4: 2200 movs r2, #0
|
|
80037f6: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Initialize the CAN state */
|
|
hcan->State = HAL_CAN_STATE_READY;
|
|
80037f8: 687b ldr r3, [r7, #4]
|
|
80037fa: 2201 movs r2, #1
|
|
80037fc: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8003800: 2300 movs r3, #0
|
|
}
|
|
8003802: 4618 mov r0, r3
|
|
8003804: 3710 adds r7, #16
|
|
8003806: 46bd mov sp, r7
|
|
8003808: bd80 pop {r7, pc}
|
|
|
|
0800380a <HAL_CAN_ConfigFilter>:
|
|
* @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
|
|
* contains the filter configuration information.
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
|
|
{
|
|
800380a: b480 push {r7}
|
|
800380c: b087 sub sp, #28
|
|
800380e: af00 add r7, sp, #0
|
|
8003810: 6078 str r0, [r7, #4]
|
|
8003812: 6039 str r1, [r7, #0]
|
|
uint32_t filternbrbitpos;
|
|
CAN_TypeDef *can_ip = hcan->Instance;
|
|
8003814: 687b ldr r3, [r7, #4]
|
|
8003816: 681b ldr r3, [r3, #0]
|
|
8003818: 617b str r3, [r7, #20]
|
|
HAL_CAN_StateTypeDef state = hcan->State;
|
|
800381a: 687b ldr r3, [r7, #4]
|
|
800381c: f893 3020 ldrb.w r3, [r3, #32]
|
|
8003820: 74fb strb r3, [r7, #19]
|
|
|
|
if ((state == HAL_CAN_STATE_READY) ||
|
|
8003822: 7cfb ldrb r3, [r7, #19]
|
|
8003824: 2b01 cmp r3, #1
|
|
8003826: d003 beq.n 8003830 <HAL_CAN_ConfigFilter+0x26>
|
|
8003828: 7cfb ldrb r3, [r7, #19]
|
|
800382a: 2b02 cmp r3, #2
|
|
800382c: f040 80aa bne.w 8003984 <HAL_CAN_ConfigFilter+0x17a>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
|
|
|
|
/* Initialisation mode for the filter */
|
|
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
|
|
8003830: 697b ldr r3, [r7, #20]
|
|
8003832: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200
|
|
8003836: f043 0201 orr.w r2, r3, #1
|
|
800383a: 697b ldr r3, [r7, #20]
|
|
800383c: f8c3 2200 str.w r2, [r3, #512] @ 0x200
|
|
|
|
/* Convert filter number into bit position */
|
|
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
|
|
8003840: 683b ldr r3, [r7, #0]
|
|
8003842: 695b ldr r3, [r3, #20]
|
|
8003844: f003 031f and.w r3, r3, #31
|
|
8003848: 2201 movs r2, #1
|
|
800384a: fa02 f303 lsl.w r3, r2, r3
|
|
800384e: 60fb str r3, [r7, #12]
|
|
|
|
/* Filter Deactivation */
|
|
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
|
|
8003850: 697b ldr r3, [r7, #20]
|
|
8003852: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c
|
|
8003856: 68fb ldr r3, [r7, #12]
|
|
8003858: 43db mvns r3, r3
|
|
800385a: 401a ands r2, r3
|
|
800385c: 697b ldr r3, [r7, #20]
|
|
800385e: f8c3 221c str.w r2, [r3, #540] @ 0x21c
|
|
|
|
/* Filter Scale */
|
|
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
|
|
8003862: 683b ldr r3, [r7, #0]
|
|
8003864: 69db ldr r3, [r3, #28]
|
|
8003866: 2b00 cmp r3, #0
|
|
8003868: d123 bne.n 80038b2 <HAL_CAN_ConfigFilter+0xa8>
|
|
{
|
|
/* 16-bit scale for the filter */
|
|
CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
|
|
800386a: 697b ldr r3, [r7, #20]
|
|
800386c: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c
|
|
8003870: 68fb ldr r3, [r7, #12]
|
|
8003872: 43db mvns r3, r3
|
|
8003874: 401a ands r2, r3
|
|
8003876: 697b ldr r3, [r7, #20]
|
|
8003878: f8c3 220c str.w r2, [r3, #524] @ 0x20c
|
|
|
|
/* First 16-bit identifier and First 16-bit mask */
|
|
/* Or First 16-bit identifier and Second 16-bit identifier */
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
|
|
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
|
|
800387c: 683b ldr r3, [r7, #0]
|
|
800387e: 68db ldr r3, [r3, #12]
|
|
8003880: 0419 lsls r1, r3, #16
|
|
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
|
|
8003882: 683b ldr r3, [r7, #0]
|
|
8003884: 685b ldr r3, [r3, #4]
|
|
8003886: b29b uxth r3, r3
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
|
|
8003888: 683a ldr r2, [r7, #0]
|
|
800388a: 6952 ldr r2, [r2, #20]
|
|
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
|
|
800388c: 4319 orrs r1, r3
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
|
|
800388e: 697b ldr r3, [r7, #20]
|
|
8003890: 3248 adds r2, #72 @ 0x48
|
|
8003892: f843 1032 str.w r1, [r3, r2, lsl #3]
|
|
|
|
/* Second 16-bit identifier and Second 16-bit mask */
|
|
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
|
|
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
|
|
8003896: 683b ldr r3, [r7, #0]
|
|
8003898: 689b ldr r3, [r3, #8]
|
|
800389a: 0419 lsls r1, r3, #16
|
|
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
|
|
800389c: 683b ldr r3, [r7, #0]
|
|
800389e: 681b ldr r3, [r3, #0]
|
|
80038a0: b29a uxth r2, r3
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
|
|
80038a2: 683b ldr r3, [r7, #0]
|
|
80038a4: 695b ldr r3, [r3, #20]
|
|
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
|
|
80038a6: 430a orrs r2, r1
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
|
|
80038a8: 6979 ldr r1, [r7, #20]
|
|
80038aa: 3348 adds r3, #72 @ 0x48
|
|
80038ac: 00db lsls r3, r3, #3
|
|
80038ae: 440b add r3, r1
|
|
80038b0: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
|
|
80038b2: 683b ldr r3, [r7, #0]
|
|
80038b4: 69db ldr r3, [r3, #28]
|
|
80038b6: 2b01 cmp r3, #1
|
|
80038b8: d122 bne.n 8003900 <HAL_CAN_ConfigFilter+0xf6>
|
|
{
|
|
/* 32-bit scale for the filter */
|
|
SET_BIT(can_ip->FS1R, filternbrbitpos);
|
|
80038ba: 697b ldr r3, [r7, #20]
|
|
80038bc: f8d3 220c ldr.w r2, [r3, #524] @ 0x20c
|
|
80038c0: 68fb ldr r3, [r7, #12]
|
|
80038c2: 431a orrs r2, r3
|
|
80038c4: 697b ldr r3, [r7, #20]
|
|
80038c6: f8c3 220c str.w r2, [r3, #524] @ 0x20c
|
|
|
|
/* 32-bit identifier or First 32-bit identifier */
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
|
|
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
|
|
80038ca: 683b ldr r3, [r7, #0]
|
|
80038cc: 681b ldr r3, [r3, #0]
|
|
80038ce: 0419 lsls r1, r3, #16
|
|
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
|
|
80038d0: 683b ldr r3, [r7, #0]
|
|
80038d2: 685b ldr r3, [r3, #4]
|
|
80038d4: b29b uxth r3, r3
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
|
|
80038d6: 683a ldr r2, [r7, #0]
|
|
80038d8: 6952 ldr r2, [r2, #20]
|
|
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
|
|
80038da: 4319 orrs r1, r3
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
|
|
80038dc: 697b ldr r3, [r7, #20]
|
|
80038de: 3248 adds r2, #72 @ 0x48
|
|
80038e0: f843 1032 str.w r1, [r3, r2, lsl #3]
|
|
|
|
/* 32-bit mask or Second 32-bit identifier */
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
|
|
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
|
|
80038e4: 683b ldr r3, [r7, #0]
|
|
80038e6: 689b ldr r3, [r3, #8]
|
|
80038e8: 0419 lsls r1, r3, #16
|
|
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
|
|
80038ea: 683b ldr r3, [r7, #0]
|
|
80038ec: 68db ldr r3, [r3, #12]
|
|
80038ee: b29a uxth r2, r3
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
|
|
80038f0: 683b ldr r3, [r7, #0]
|
|
80038f2: 695b ldr r3, [r3, #20]
|
|
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
|
|
80038f4: 430a orrs r2, r1
|
|
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
|
|
80038f6: 6979 ldr r1, [r7, #20]
|
|
80038f8: 3348 adds r3, #72 @ 0x48
|
|
80038fa: 00db lsls r3, r3, #3
|
|
80038fc: 440b add r3, r1
|
|
80038fe: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Filter Mode */
|
|
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
|
|
8003900: 683b ldr r3, [r7, #0]
|
|
8003902: 699b ldr r3, [r3, #24]
|
|
8003904: 2b00 cmp r3, #0
|
|
8003906: d109 bne.n 800391c <HAL_CAN_ConfigFilter+0x112>
|
|
{
|
|
/* Id/Mask mode for the filter*/
|
|
CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
|
|
8003908: 697b ldr r3, [r7, #20]
|
|
800390a: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
800390e: 68fb ldr r3, [r7, #12]
|
|
8003910: 43db mvns r3, r3
|
|
8003912: 401a ands r2, r3
|
|
8003914: 697b ldr r3, [r7, #20]
|
|
8003916: f8c3 2204 str.w r2, [r3, #516] @ 0x204
|
|
800391a: e007 b.n 800392c <HAL_CAN_ConfigFilter+0x122>
|
|
}
|
|
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
|
|
{
|
|
/* Identifier list mode for the filter*/
|
|
SET_BIT(can_ip->FM1R, filternbrbitpos);
|
|
800391c: 697b ldr r3, [r7, #20]
|
|
800391e: f8d3 2204 ldr.w r2, [r3, #516] @ 0x204
|
|
8003922: 68fb ldr r3, [r7, #12]
|
|
8003924: 431a orrs r2, r3
|
|
8003926: 697b ldr r3, [r7, #20]
|
|
8003928: f8c3 2204 str.w r2, [r3, #516] @ 0x204
|
|
}
|
|
|
|
/* Filter FIFO assignment */
|
|
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
|
|
800392c: 683b ldr r3, [r7, #0]
|
|
800392e: 691b ldr r3, [r3, #16]
|
|
8003930: 2b00 cmp r3, #0
|
|
8003932: d109 bne.n 8003948 <HAL_CAN_ConfigFilter+0x13e>
|
|
{
|
|
/* FIFO 0 assignation for the filter */
|
|
CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
|
|
8003934: 697b ldr r3, [r7, #20]
|
|
8003936: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214
|
|
800393a: 68fb ldr r3, [r7, #12]
|
|
800393c: 43db mvns r3, r3
|
|
800393e: 401a ands r2, r3
|
|
8003940: 697b ldr r3, [r7, #20]
|
|
8003942: f8c3 2214 str.w r2, [r3, #532] @ 0x214
|
|
8003946: e007 b.n 8003958 <HAL_CAN_ConfigFilter+0x14e>
|
|
}
|
|
else
|
|
{
|
|
/* FIFO 1 assignation for the filter */
|
|
SET_BIT(can_ip->FFA1R, filternbrbitpos);
|
|
8003948: 697b ldr r3, [r7, #20]
|
|
800394a: f8d3 2214 ldr.w r2, [r3, #532] @ 0x214
|
|
800394e: 68fb ldr r3, [r7, #12]
|
|
8003950: 431a orrs r2, r3
|
|
8003952: 697b ldr r3, [r7, #20]
|
|
8003954: f8c3 2214 str.w r2, [r3, #532] @ 0x214
|
|
}
|
|
|
|
/* Filter activation */
|
|
if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
|
|
8003958: 683b ldr r3, [r7, #0]
|
|
800395a: 6a1b ldr r3, [r3, #32]
|
|
800395c: 2b01 cmp r3, #1
|
|
800395e: d107 bne.n 8003970 <HAL_CAN_ConfigFilter+0x166>
|
|
{
|
|
SET_BIT(can_ip->FA1R, filternbrbitpos);
|
|
8003960: 697b ldr r3, [r7, #20]
|
|
8003962: f8d3 221c ldr.w r2, [r3, #540] @ 0x21c
|
|
8003966: 68fb ldr r3, [r7, #12]
|
|
8003968: 431a orrs r2, r3
|
|
800396a: 697b ldr r3, [r7, #20]
|
|
800396c: f8c3 221c str.w r2, [r3, #540] @ 0x21c
|
|
}
|
|
|
|
/* Leave the initialisation mode for the filter */
|
|
CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
|
|
8003970: 697b ldr r3, [r7, #20]
|
|
8003972: f8d3 3200 ldr.w r3, [r3, #512] @ 0x200
|
|
8003976: f023 0201 bic.w r2, r3, #1
|
|
800397a: 697b ldr r3, [r7, #20]
|
|
800397c: f8c3 2200 str.w r2, [r3, #512] @ 0x200
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8003980: 2300 movs r3, #0
|
|
8003982: e006 b.n 8003992 <HAL_CAN_ConfigFilter+0x188>
|
|
}
|
|
else
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
|
|
8003984: 687b ldr r3, [r7, #4]
|
|
8003986: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003988: f443 2280 orr.w r2, r3, #262144 @ 0x40000
|
|
800398c: 687b ldr r3, [r7, #4]
|
|
800398e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8003990: 2301 movs r3, #1
|
|
}
|
|
}
|
|
8003992: 4618 mov r0, r3
|
|
8003994: 371c adds r7, #28
|
|
8003996: 46bd mov sp, r7
|
|
8003998: f85d 7b04 ldr.w r7, [sp], #4
|
|
800399c: 4770 bx lr
|
|
|
|
0800399e <HAL_CAN_Start>:
|
|
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
|
|
{
|
|
800399e: b580 push {r7, lr}
|
|
80039a0: b084 sub sp, #16
|
|
80039a2: af00 add r7, sp, #0
|
|
80039a4: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
if (hcan->State == HAL_CAN_STATE_READY)
|
|
80039a6: 687b ldr r3, [r7, #4]
|
|
80039a8: f893 3020 ldrb.w r3, [r3, #32]
|
|
80039ac: b2db uxtb r3, r3
|
|
80039ae: 2b01 cmp r3, #1
|
|
80039b0: d12e bne.n 8003a10 <HAL_CAN_Start+0x72>
|
|
{
|
|
/* Change CAN peripheral state */
|
|
hcan->State = HAL_CAN_STATE_LISTENING;
|
|
80039b2: 687b ldr r3, [r7, #4]
|
|
80039b4: 2202 movs r2, #2
|
|
80039b6: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
/* Request leave initialisation */
|
|
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
|
|
80039ba: 687b ldr r3, [r7, #4]
|
|
80039bc: 681b ldr r3, [r3, #0]
|
|
80039be: 681a ldr r2, [r3, #0]
|
|
80039c0: 687b ldr r3, [r7, #4]
|
|
80039c2: 681b ldr r3, [r3, #0]
|
|
80039c4: f022 0201 bic.w r2, r2, #1
|
|
80039c8: 601a str r2, [r3, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80039ca: f7fe fc93 bl 80022f4 <HAL_GetTick>
|
|
80039ce: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait the acknowledge */
|
|
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
|
|
80039d0: e012 b.n 80039f8 <HAL_CAN_Start+0x5a>
|
|
{
|
|
/* Check for the Timeout */
|
|
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
|
|
80039d2: f7fe fc8f bl 80022f4 <HAL_GetTick>
|
|
80039d6: 4602 mov r2, r0
|
|
80039d8: 68fb ldr r3, [r7, #12]
|
|
80039da: 1ad3 subs r3, r2, r3
|
|
80039dc: 2b0a cmp r3, #10
|
|
80039de: d90b bls.n 80039f8 <HAL_CAN_Start+0x5a>
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
|
|
80039e0: 687b ldr r3, [r7, #4]
|
|
80039e2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80039e4: f443 3200 orr.w r2, r3, #131072 @ 0x20000
|
|
80039e8: 687b ldr r3, [r7, #4]
|
|
80039ea: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Change CAN state */
|
|
hcan->State = HAL_CAN_STATE_ERROR;
|
|
80039ec: 687b ldr r3, [r7, #4]
|
|
80039ee: 2205 movs r2, #5
|
|
80039f0: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_ERROR;
|
|
80039f4: 2301 movs r3, #1
|
|
80039f6: e012 b.n 8003a1e <HAL_CAN_Start+0x80>
|
|
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
|
|
80039f8: 687b ldr r3, [r7, #4]
|
|
80039fa: 681b ldr r3, [r3, #0]
|
|
80039fc: 685b ldr r3, [r3, #4]
|
|
80039fe: f003 0301 and.w r3, r3, #1
|
|
8003a02: 2b00 cmp r3, #0
|
|
8003a04: d1e5 bne.n 80039d2 <HAL_CAN_Start+0x34>
|
|
}
|
|
}
|
|
|
|
/* Reset the CAN ErrorCode */
|
|
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
|
|
8003a06: 687b ldr r3, [r7, #4]
|
|
8003a08: 2200 movs r2, #0
|
|
8003a0a: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8003a0c: 2300 movs r3, #0
|
|
8003a0e: e006 b.n 8003a1e <HAL_CAN_Start+0x80>
|
|
}
|
|
else
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
|
|
8003a10: 687b ldr r3, [r7, #4]
|
|
8003a12: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003a14: f443 2200 orr.w r2, r3, #524288 @ 0x80000
|
|
8003a18: 687b ldr r3, [r7, #4]
|
|
8003a1a: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8003a1c: 2301 movs r3, #1
|
|
}
|
|
}
|
|
8003a1e: 4618 mov r0, r3
|
|
8003a20: 3710 adds r7, #16
|
|
8003a22: 46bd mov sp, r7
|
|
8003a24: bd80 pop {r7, pc}
|
|
|
|
08003a26 <HAL_CAN_AddTxMessage>:
|
|
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
|
|
const uint8_t aData[], uint32_t *pTxMailbox)
|
|
{
|
|
8003a26: b480 push {r7}
|
|
8003a28: b089 sub sp, #36 @ 0x24
|
|
8003a2a: af00 add r7, sp, #0
|
|
8003a2c: 60f8 str r0, [r7, #12]
|
|
8003a2e: 60b9 str r1, [r7, #8]
|
|
8003a30: 607a str r2, [r7, #4]
|
|
8003a32: 603b str r3, [r7, #0]
|
|
uint32_t transmitmailbox;
|
|
HAL_CAN_StateTypeDef state = hcan->State;
|
|
8003a34: 68fb ldr r3, [r7, #12]
|
|
8003a36: f893 3020 ldrb.w r3, [r3, #32]
|
|
8003a3a: 77fb strb r3, [r7, #31]
|
|
uint32_t tsr = READ_REG(hcan->Instance->TSR);
|
|
8003a3c: 68fb ldr r3, [r7, #12]
|
|
8003a3e: 681b ldr r3, [r3, #0]
|
|
8003a40: 689b ldr r3, [r3, #8]
|
|
8003a42: 61bb str r3, [r7, #24]
|
|
{
|
|
assert_param(IS_CAN_EXTID(pHeader->ExtId));
|
|
}
|
|
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
|
|
|
|
if ((state == HAL_CAN_STATE_READY) ||
|
|
8003a44: 7ffb ldrb r3, [r7, #31]
|
|
8003a46: 2b01 cmp r3, #1
|
|
8003a48: d003 beq.n 8003a52 <HAL_CAN_AddTxMessage+0x2c>
|
|
8003a4a: 7ffb ldrb r3, [r7, #31]
|
|
8003a4c: 2b02 cmp r3, #2
|
|
8003a4e: f040 80ad bne.w 8003bac <HAL_CAN_AddTxMessage+0x186>
|
|
(state == HAL_CAN_STATE_LISTENING))
|
|
{
|
|
/* Check that all the Tx mailboxes are not full */
|
|
if (((tsr & CAN_TSR_TME0) != 0U) ||
|
|
8003a52: 69bb ldr r3, [r7, #24]
|
|
8003a54: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8003a58: 2b00 cmp r3, #0
|
|
8003a5a: d10a bne.n 8003a72 <HAL_CAN_AddTxMessage+0x4c>
|
|
((tsr & CAN_TSR_TME1) != 0U) ||
|
|
8003a5c: 69bb ldr r3, [r7, #24]
|
|
8003a5e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
if (((tsr & CAN_TSR_TME0) != 0U) ||
|
|
8003a62: 2b00 cmp r3, #0
|
|
8003a64: d105 bne.n 8003a72 <HAL_CAN_AddTxMessage+0x4c>
|
|
((tsr & CAN_TSR_TME2) != 0U))
|
|
8003a66: 69bb ldr r3, [r7, #24]
|
|
8003a68: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
((tsr & CAN_TSR_TME1) != 0U) ||
|
|
8003a6c: 2b00 cmp r3, #0
|
|
8003a6e: f000 8095 beq.w 8003b9c <HAL_CAN_AddTxMessage+0x176>
|
|
{
|
|
/* Select an empty transmit mailbox */
|
|
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
|
|
8003a72: 69bb ldr r3, [r7, #24]
|
|
8003a74: 0e1b lsrs r3, r3, #24
|
|
8003a76: f003 0303 and.w r3, r3, #3
|
|
8003a7a: 617b str r3, [r7, #20]
|
|
|
|
/* Store the Tx mailbox */
|
|
*pTxMailbox = (uint32_t)1 << transmitmailbox;
|
|
8003a7c: 2201 movs r2, #1
|
|
8003a7e: 697b ldr r3, [r7, #20]
|
|
8003a80: 409a lsls r2, r3
|
|
8003a82: 683b ldr r3, [r7, #0]
|
|
8003a84: 601a str r2, [r3, #0]
|
|
|
|
/* Set up the Id */
|
|
if (pHeader->IDE == CAN_ID_STD)
|
|
8003a86: 68bb ldr r3, [r7, #8]
|
|
8003a88: 689b ldr r3, [r3, #8]
|
|
8003a8a: 2b00 cmp r3, #0
|
|
8003a8c: d10d bne.n 8003aaa <HAL_CAN_AddTxMessage+0x84>
|
|
{
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
|
|
8003a8e: 68bb ldr r3, [r7, #8]
|
|
8003a90: 681b ldr r3, [r3, #0]
|
|
8003a92: 055a lsls r2, r3, #21
|
|
pHeader->RTR);
|
|
8003a94: 68bb ldr r3, [r7, #8]
|
|
8003a96: 68db ldr r3, [r3, #12]
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
|
|
8003a98: 68f9 ldr r1, [r7, #12]
|
|
8003a9a: 6809 ldr r1, [r1, #0]
|
|
8003a9c: 431a orrs r2, r3
|
|
8003a9e: 697b ldr r3, [r7, #20]
|
|
8003aa0: 3318 adds r3, #24
|
|
8003aa2: 011b lsls r3, r3, #4
|
|
8003aa4: 440b add r3, r1
|
|
8003aa6: 601a str r2, [r3, #0]
|
|
8003aa8: e00f b.n 8003aca <HAL_CAN_AddTxMessage+0xa4>
|
|
}
|
|
else
|
|
{
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
|
|
8003aaa: 68bb ldr r3, [r7, #8]
|
|
8003aac: 685b ldr r3, [r3, #4]
|
|
8003aae: 00da lsls r2, r3, #3
|
|
pHeader->IDE |
|
|
8003ab0: 68bb ldr r3, [r7, #8]
|
|
8003ab2: 689b ldr r3, [r3, #8]
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
|
|
8003ab4: 431a orrs r2, r3
|
|
pHeader->RTR);
|
|
8003ab6: 68bb ldr r3, [r7, #8]
|
|
8003ab8: 68db ldr r3, [r3, #12]
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
|
|
8003aba: 68f9 ldr r1, [r7, #12]
|
|
8003abc: 6809 ldr r1, [r1, #0]
|
|
pHeader->IDE |
|
|
8003abe: 431a orrs r2, r3
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
|
|
8003ac0: 697b ldr r3, [r7, #20]
|
|
8003ac2: 3318 adds r3, #24
|
|
8003ac4: 011b lsls r3, r3, #4
|
|
8003ac6: 440b add r3, r1
|
|
8003ac8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set up the DLC */
|
|
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
|
|
8003aca: 68fb ldr r3, [r7, #12]
|
|
8003acc: 6819 ldr r1, [r3, #0]
|
|
8003ace: 68bb ldr r3, [r7, #8]
|
|
8003ad0: 691a ldr r2, [r3, #16]
|
|
8003ad2: 697b ldr r3, [r7, #20]
|
|
8003ad4: 3318 adds r3, #24
|
|
8003ad6: 011b lsls r3, r3, #4
|
|
8003ad8: 440b add r3, r1
|
|
8003ada: 3304 adds r3, #4
|
|
8003adc: 601a str r2, [r3, #0]
|
|
|
|
/* Set up the Transmit Global Time mode */
|
|
if (pHeader->TransmitGlobalTime == ENABLE)
|
|
8003ade: 68bb ldr r3, [r7, #8]
|
|
8003ae0: 7d1b ldrb r3, [r3, #20]
|
|
8003ae2: 2b01 cmp r3, #1
|
|
8003ae4: d111 bne.n 8003b0a <HAL_CAN_AddTxMessage+0xe4>
|
|
{
|
|
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
|
|
8003ae6: 68fb ldr r3, [r7, #12]
|
|
8003ae8: 681a ldr r2, [r3, #0]
|
|
8003aea: 697b ldr r3, [r7, #20]
|
|
8003aec: 3318 adds r3, #24
|
|
8003aee: 011b lsls r3, r3, #4
|
|
8003af0: 4413 add r3, r2
|
|
8003af2: 3304 adds r3, #4
|
|
8003af4: 681b ldr r3, [r3, #0]
|
|
8003af6: 68fa ldr r2, [r7, #12]
|
|
8003af8: 6811 ldr r1, [r2, #0]
|
|
8003afa: f443 7280 orr.w r2, r3, #256 @ 0x100
|
|
8003afe: 697b ldr r3, [r7, #20]
|
|
8003b00: 3318 adds r3, #24
|
|
8003b02: 011b lsls r3, r3, #4
|
|
8003b04: 440b add r3, r1
|
|
8003b06: 3304 adds r3, #4
|
|
8003b08: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set up the data field */
|
|
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
|
|
8003b0a: 687b ldr r3, [r7, #4]
|
|
8003b0c: 3307 adds r3, #7
|
|
8003b0e: 781b ldrb r3, [r3, #0]
|
|
8003b10: 061a lsls r2, r3, #24
|
|
8003b12: 687b ldr r3, [r7, #4]
|
|
8003b14: 3306 adds r3, #6
|
|
8003b16: 781b ldrb r3, [r3, #0]
|
|
8003b18: 041b lsls r3, r3, #16
|
|
8003b1a: 431a orrs r2, r3
|
|
8003b1c: 687b ldr r3, [r7, #4]
|
|
8003b1e: 3305 adds r3, #5
|
|
8003b20: 781b ldrb r3, [r3, #0]
|
|
8003b22: 021b lsls r3, r3, #8
|
|
8003b24: 4313 orrs r3, r2
|
|
8003b26: 687a ldr r2, [r7, #4]
|
|
8003b28: 3204 adds r2, #4
|
|
8003b2a: 7812 ldrb r2, [r2, #0]
|
|
8003b2c: 4610 mov r0, r2
|
|
8003b2e: 68fa ldr r2, [r7, #12]
|
|
8003b30: 6811 ldr r1, [r2, #0]
|
|
8003b32: ea43 0200 orr.w r2, r3, r0
|
|
8003b36: 697b ldr r3, [r7, #20]
|
|
8003b38: 011b lsls r3, r3, #4
|
|
8003b3a: 440b add r3, r1
|
|
8003b3c: f503 73c6 add.w r3, r3, #396 @ 0x18c
|
|
8003b40: 601a str r2, [r3, #0]
|
|
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
|
|
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
|
|
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
|
|
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
|
|
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
|
|
8003b42: 687b ldr r3, [r7, #4]
|
|
8003b44: 3303 adds r3, #3
|
|
8003b46: 781b ldrb r3, [r3, #0]
|
|
8003b48: 061a lsls r2, r3, #24
|
|
8003b4a: 687b ldr r3, [r7, #4]
|
|
8003b4c: 3302 adds r3, #2
|
|
8003b4e: 781b ldrb r3, [r3, #0]
|
|
8003b50: 041b lsls r3, r3, #16
|
|
8003b52: 431a orrs r2, r3
|
|
8003b54: 687b ldr r3, [r7, #4]
|
|
8003b56: 3301 adds r3, #1
|
|
8003b58: 781b ldrb r3, [r3, #0]
|
|
8003b5a: 021b lsls r3, r3, #8
|
|
8003b5c: 4313 orrs r3, r2
|
|
8003b5e: 687a ldr r2, [r7, #4]
|
|
8003b60: 7812 ldrb r2, [r2, #0]
|
|
8003b62: 4610 mov r0, r2
|
|
8003b64: 68fa ldr r2, [r7, #12]
|
|
8003b66: 6811 ldr r1, [r2, #0]
|
|
8003b68: ea43 0200 orr.w r2, r3, r0
|
|
8003b6c: 697b ldr r3, [r7, #20]
|
|
8003b6e: 011b lsls r3, r3, #4
|
|
8003b70: 440b add r3, r1
|
|
8003b72: f503 73c4 add.w r3, r3, #392 @ 0x188
|
|
8003b76: 601a str r2, [r3, #0]
|
|
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
|
|
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
|
|
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
|
|
|
|
/* Request transmission */
|
|
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
|
|
8003b78: 68fb ldr r3, [r7, #12]
|
|
8003b7a: 681a ldr r2, [r3, #0]
|
|
8003b7c: 697b ldr r3, [r7, #20]
|
|
8003b7e: 3318 adds r3, #24
|
|
8003b80: 011b lsls r3, r3, #4
|
|
8003b82: 4413 add r3, r2
|
|
8003b84: 681b ldr r3, [r3, #0]
|
|
8003b86: 68fa ldr r2, [r7, #12]
|
|
8003b88: 6811 ldr r1, [r2, #0]
|
|
8003b8a: f043 0201 orr.w r2, r3, #1
|
|
8003b8e: 697b ldr r3, [r7, #20]
|
|
8003b90: 3318 adds r3, #24
|
|
8003b92: 011b lsls r3, r3, #4
|
|
8003b94: 440b add r3, r1
|
|
8003b96: 601a str r2, [r3, #0]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8003b98: 2300 movs r3, #0
|
|
8003b9a: e00e b.n 8003bba <HAL_CAN_AddTxMessage+0x194>
|
|
}
|
|
else
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
|
|
8003b9c: 68fb ldr r3, [r7, #12]
|
|
8003b9e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003ba0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
8003ba4: 68fb ldr r3, [r7, #12]
|
|
8003ba6: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8003ba8: 2301 movs r3, #1
|
|
8003baa: e006 b.n 8003bba <HAL_CAN_AddTxMessage+0x194>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
|
|
8003bac: 68fb ldr r3, [r7, #12]
|
|
8003bae: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003bb0: f443 2280 orr.w r2, r3, #262144 @ 0x40000
|
|
8003bb4: 68fb ldr r3, [r7, #12]
|
|
8003bb6: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8003bb8: 2301 movs r3, #1
|
|
}
|
|
}
|
|
8003bba: 4618 mov r0, r3
|
|
8003bbc: 3724 adds r7, #36 @ 0x24
|
|
8003bbe: 46bd mov sp, r7
|
|
8003bc0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003bc4: 4770 bx lr
|
|
|
|
08003bc6 <HAL_CAN_GetRxMessage>:
|
|
* @param aData array where the payload of the Rx frame will be stored.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
|
|
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
|
|
{
|
|
8003bc6: b480 push {r7}
|
|
8003bc8: b087 sub sp, #28
|
|
8003bca: af00 add r7, sp, #0
|
|
8003bcc: 60f8 str r0, [r7, #12]
|
|
8003bce: 60b9 str r1, [r7, #8]
|
|
8003bd0: 607a str r2, [r7, #4]
|
|
8003bd2: 603b str r3, [r7, #0]
|
|
HAL_CAN_StateTypeDef state = hcan->State;
|
|
8003bd4: 68fb ldr r3, [r7, #12]
|
|
8003bd6: f893 3020 ldrb.w r3, [r3, #32]
|
|
8003bda: 75fb strb r3, [r7, #23]
|
|
|
|
assert_param(IS_CAN_RX_FIFO(RxFifo));
|
|
|
|
if ((state == HAL_CAN_STATE_READY) ||
|
|
8003bdc: 7dfb ldrb r3, [r7, #23]
|
|
8003bde: 2b01 cmp r3, #1
|
|
8003be0: d003 beq.n 8003bea <HAL_CAN_GetRxMessage+0x24>
|
|
8003be2: 7dfb ldrb r3, [r7, #23]
|
|
8003be4: 2b02 cmp r3, #2
|
|
8003be6: f040 8103 bne.w 8003df0 <HAL_CAN_GetRxMessage+0x22a>
|
|
(state == HAL_CAN_STATE_LISTENING))
|
|
{
|
|
/* Check the Rx FIFO */
|
|
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
|
|
8003bea: 68bb ldr r3, [r7, #8]
|
|
8003bec: 2b00 cmp r3, #0
|
|
8003bee: d10e bne.n 8003c0e <HAL_CAN_GetRxMessage+0x48>
|
|
{
|
|
/* Check that the Rx FIFO 0 is not empty */
|
|
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
|
|
8003bf0: 68fb ldr r3, [r7, #12]
|
|
8003bf2: 681b ldr r3, [r3, #0]
|
|
8003bf4: 68db ldr r3, [r3, #12]
|
|
8003bf6: f003 0303 and.w r3, r3, #3
|
|
8003bfa: 2b00 cmp r3, #0
|
|
8003bfc: d116 bne.n 8003c2c <HAL_CAN_GetRxMessage+0x66>
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
|
|
8003bfe: 68fb ldr r3, [r7, #12]
|
|
8003c00: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003c02: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
8003c06: 68fb ldr r3, [r7, #12]
|
|
8003c08: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8003c0a: 2301 movs r3, #1
|
|
8003c0c: e0f7 b.n 8003dfe <HAL_CAN_GetRxMessage+0x238>
|
|
}
|
|
}
|
|
else /* Rx element is assigned to Rx FIFO 1 */
|
|
{
|
|
/* Check that the Rx FIFO 1 is not empty */
|
|
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
|
|
8003c0e: 68fb ldr r3, [r7, #12]
|
|
8003c10: 681b ldr r3, [r3, #0]
|
|
8003c12: 691b ldr r3, [r3, #16]
|
|
8003c14: f003 0303 and.w r3, r3, #3
|
|
8003c18: 2b00 cmp r3, #0
|
|
8003c1a: d107 bne.n 8003c2c <HAL_CAN_GetRxMessage+0x66>
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
|
|
8003c1c: 68fb ldr r3, [r7, #12]
|
|
8003c1e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003c20: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
8003c24: 68fb ldr r3, [r7, #12]
|
|
8003c26: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8003c28: 2301 movs r3, #1
|
|
8003c2a: e0e8 b.n 8003dfe <HAL_CAN_GetRxMessage+0x238>
|
|
}
|
|
}
|
|
|
|
/* Get the header */
|
|
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
|
|
8003c2c: 68fb ldr r3, [r7, #12]
|
|
8003c2e: 681a ldr r2, [r3, #0]
|
|
8003c30: 68bb ldr r3, [r7, #8]
|
|
8003c32: 331b adds r3, #27
|
|
8003c34: 011b lsls r3, r3, #4
|
|
8003c36: 4413 add r3, r2
|
|
8003c38: 681b ldr r3, [r3, #0]
|
|
8003c3a: f003 0204 and.w r2, r3, #4
|
|
8003c3e: 687b ldr r3, [r7, #4]
|
|
8003c40: 609a str r2, [r3, #8]
|
|
if (pHeader->IDE == CAN_ID_STD)
|
|
8003c42: 687b ldr r3, [r7, #4]
|
|
8003c44: 689b ldr r3, [r3, #8]
|
|
8003c46: 2b00 cmp r3, #0
|
|
8003c48: d10c bne.n 8003c64 <HAL_CAN_GetRxMessage+0x9e>
|
|
{
|
|
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
|
|
8003c4a: 68fb ldr r3, [r7, #12]
|
|
8003c4c: 681a ldr r2, [r3, #0]
|
|
8003c4e: 68bb ldr r3, [r7, #8]
|
|
8003c50: 331b adds r3, #27
|
|
8003c52: 011b lsls r3, r3, #4
|
|
8003c54: 4413 add r3, r2
|
|
8003c56: 681b ldr r3, [r3, #0]
|
|
8003c58: 0d5b lsrs r3, r3, #21
|
|
8003c5a: f3c3 020a ubfx r2, r3, #0, #11
|
|
8003c5e: 687b ldr r3, [r7, #4]
|
|
8003c60: 601a str r2, [r3, #0]
|
|
8003c62: e00b b.n 8003c7c <HAL_CAN_GetRxMessage+0xb6>
|
|
}
|
|
else
|
|
{
|
|
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
|
|
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
|
|
8003c64: 68fb ldr r3, [r7, #12]
|
|
8003c66: 681a ldr r2, [r3, #0]
|
|
8003c68: 68bb ldr r3, [r7, #8]
|
|
8003c6a: 331b adds r3, #27
|
|
8003c6c: 011b lsls r3, r3, #4
|
|
8003c6e: 4413 add r3, r2
|
|
8003c70: 681b ldr r3, [r3, #0]
|
|
8003c72: 08db lsrs r3, r3, #3
|
|
8003c74: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000
|
|
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
|
|
8003c78: 687b ldr r3, [r7, #4]
|
|
8003c7a: 605a str r2, [r3, #4]
|
|
}
|
|
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
|
|
8003c7c: 68fb ldr r3, [r7, #12]
|
|
8003c7e: 681a ldr r2, [r3, #0]
|
|
8003c80: 68bb ldr r3, [r7, #8]
|
|
8003c82: 331b adds r3, #27
|
|
8003c84: 011b lsls r3, r3, #4
|
|
8003c86: 4413 add r3, r2
|
|
8003c88: 681b ldr r3, [r3, #0]
|
|
8003c8a: f003 0202 and.w r2, r3, #2
|
|
8003c8e: 687b ldr r3, [r7, #4]
|
|
8003c90: 60da str r2, [r3, #12]
|
|
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
|
|
8003c92: 68fb ldr r3, [r7, #12]
|
|
8003c94: 681a ldr r2, [r3, #0]
|
|
8003c96: 68bb ldr r3, [r7, #8]
|
|
8003c98: 331b adds r3, #27
|
|
8003c9a: 011b lsls r3, r3, #4
|
|
8003c9c: 4413 add r3, r2
|
|
8003c9e: 3304 adds r3, #4
|
|
8003ca0: 681b ldr r3, [r3, #0]
|
|
8003ca2: f003 0308 and.w r3, r3, #8
|
|
8003ca6: 2b00 cmp r3, #0
|
|
8003ca8: d003 beq.n 8003cb2 <HAL_CAN_GetRxMessage+0xec>
|
|
{
|
|
/* Truncate DLC to 8 if received field is over range */
|
|
pHeader->DLC = 8U;
|
|
8003caa: 687b ldr r3, [r7, #4]
|
|
8003cac: 2208 movs r2, #8
|
|
8003cae: 611a str r2, [r3, #16]
|
|
8003cb0: e00b b.n 8003cca <HAL_CAN_GetRxMessage+0x104>
|
|
}
|
|
else
|
|
{
|
|
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
|
|
8003cb2: 68fb ldr r3, [r7, #12]
|
|
8003cb4: 681a ldr r2, [r3, #0]
|
|
8003cb6: 68bb ldr r3, [r7, #8]
|
|
8003cb8: 331b adds r3, #27
|
|
8003cba: 011b lsls r3, r3, #4
|
|
8003cbc: 4413 add r3, r2
|
|
8003cbe: 3304 adds r3, #4
|
|
8003cc0: 681b ldr r3, [r3, #0]
|
|
8003cc2: f003 020f and.w r2, r3, #15
|
|
8003cc6: 687b ldr r3, [r7, #4]
|
|
8003cc8: 611a str r2, [r3, #16]
|
|
}
|
|
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
|
|
8003cca: 68fb ldr r3, [r7, #12]
|
|
8003ccc: 681a ldr r2, [r3, #0]
|
|
8003cce: 68bb ldr r3, [r7, #8]
|
|
8003cd0: 331b adds r3, #27
|
|
8003cd2: 011b lsls r3, r3, #4
|
|
8003cd4: 4413 add r3, r2
|
|
8003cd6: 3304 adds r3, #4
|
|
8003cd8: 681b ldr r3, [r3, #0]
|
|
8003cda: 0a1b lsrs r3, r3, #8
|
|
8003cdc: b2da uxtb r2, r3
|
|
8003cde: 687b ldr r3, [r7, #4]
|
|
8003ce0: 619a str r2, [r3, #24]
|
|
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
|
|
8003ce2: 68fb ldr r3, [r7, #12]
|
|
8003ce4: 681a ldr r2, [r3, #0]
|
|
8003ce6: 68bb ldr r3, [r7, #8]
|
|
8003ce8: 331b adds r3, #27
|
|
8003cea: 011b lsls r3, r3, #4
|
|
8003cec: 4413 add r3, r2
|
|
8003cee: 3304 adds r3, #4
|
|
8003cf0: 681b ldr r3, [r3, #0]
|
|
8003cf2: 0c1b lsrs r3, r3, #16
|
|
8003cf4: b29a uxth r2, r3
|
|
8003cf6: 687b ldr r3, [r7, #4]
|
|
8003cf8: 615a str r2, [r3, #20]
|
|
|
|
/* Get the data */
|
|
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
|
|
8003cfa: 68fb ldr r3, [r7, #12]
|
|
8003cfc: 681a ldr r2, [r3, #0]
|
|
8003cfe: 68bb ldr r3, [r7, #8]
|
|
8003d00: 011b lsls r3, r3, #4
|
|
8003d02: 4413 add r3, r2
|
|
8003d04: f503 73dc add.w r3, r3, #440 @ 0x1b8
|
|
8003d08: 681b ldr r3, [r3, #0]
|
|
8003d0a: b2da uxtb r2, r3
|
|
8003d0c: 683b ldr r3, [r7, #0]
|
|
8003d0e: 701a strb r2, [r3, #0]
|
|
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
|
|
8003d10: 68fb ldr r3, [r7, #12]
|
|
8003d12: 681a ldr r2, [r3, #0]
|
|
8003d14: 68bb ldr r3, [r7, #8]
|
|
8003d16: 011b lsls r3, r3, #4
|
|
8003d18: 4413 add r3, r2
|
|
8003d1a: f503 73dc add.w r3, r3, #440 @ 0x1b8
|
|
8003d1e: 681b ldr r3, [r3, #0]
|
|
8003d20: 0a1a lsrs r2, r3, #8
|
|
8003d22: 683b ldr r3, [r7, #0]
|
|
8003d24: 3301 adds r3, #1
|
|
8003d26: b2d2 uxtb r2, r2
|
|
8003d28: 701a strb r2, [r3, #0]
|
|
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
|
|
8003d2a: 68fb ldr r3, [r7, #12]
|
|
8003d2c: 681a ldr r2, [r3, #0]
|
|
8003d2e: 68bb ldr r3, [r7, #8]
|
|
8003d30: 011b lsls r3, r3, #4
|
|
8003d32: 4413 add r3, r2
|
|
8003d34: f503 73dc add.w r3, r3, #440 @ 0x1b8
|
|
8003d38: 681b ldr r3, [r3, #0]
|
|
8003d3a: 0c1a lsrs r2, r3, #16
|
|
8003d3c: 683b ldr r3, [r7, #0]
|
|
8003d3e: 3302 adds r3, #2
|
|
8003d40: b2d2 uxtb r2, r2
|
|
8003d42: 701a strb r2, [r3, #0]
|
|
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
|
|
8003d44: 68fb ldr r3, [r7, #12]
|
|
8003d46: 681a ldr r2, [r3, #0]
|
|
8003d48: 68bb ldr r3, [r7, #8]
|
|
8003d4a: 011b lsls r3, r3, #4
|
|
8003d4c: 4413 add r3, r2
|
|
8003d4e: f503 73dc add.w r3, r3, #440 @ 0x1b8
|
|
8003d52: 681b ldr r3, [r3, #0]
|
|
8003d54: 0e1a lsrs r2, r3, #24
|
|
8003d56: 683b ldr r3, [r7, #0]
|
|
8003d58: 3303 adds r3, #3
|
|
8003d5a: b2d2 uxtb r2, r2
|
|
8003d5c: 701a strb r2, [r3, #0]
|
|
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
|
|
8003d5e: 68fb ldr r3, [r7, #12]
|
|
8003d60: 681a ldr r2, [r3, #0]
|
|
8003d62: 68bb ldr r3, [r7, #8]
|
|
8003d64: 011b lsls r3, r3, #4
|
|
8003d66: 4413 add r3, r2
|
|
8003d68: f503 73de add.w r3, r3, #444 @ 0x1bc
|
|
8003d6c: 681a ldr r2, [r3, #0]
|
|
8003d6e: 683b ldr r3, [r7, #0]
|
|
8003d70: 3304 adds r3, #4
|
|
8003d72: b2d2 uxtb r2, r2
|
|
8003d74: 701a strb r2, [r3, #0]
|
|
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
|
|
8003d76: 68fb ldr r3, [r7, #12]
|
|
8003d78: 681a ldr r2, [r3, #0]
|
|
8003d7a: 68bb ldr r3, [r7, #8]
|
|
8003d7c: 011b lsls r3, r3, #4
|
|
8003d7e: 4413 add r3, r2
|
|
8003d80: f503 73de add.w r3, r3, #444 @ 0x1bc
|
|
8003d84: 681b ldr r3, [r3, #0]
|
|
8003d86: 0a1a lsrs r2, r3, #8
|
|
8003d88: 683b ldr r3, [r7, #0]
|
|
8003d8a: 3305 adds r3, #5
|
|
8003d8c: b2d2 uxtb r2, r2
|
|
8003d8e: 701a strb r2, [r3, #0]
|
|
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
|
|
8003d90: 68fb ldr r3, [r7, #12]
|
|
8003d92: 681a ldr r2, [r3, #0]
|
|
8003d94: 68bb ldr r3, [r7, #8]
|
|
8003d96: 011b lsls r3, r3, #4
|
|
8003d98: 4413 add r3, r2
|
|
8003d9a: f503 73de add.w r3, r3, #444 @ 0x1bc
|
|
8003d9e: 681b ldr r3, [r3, #0]
|
|
8003da0: 0c1a lsrs r2, r3, #16
|
|
8003da2: 683b ldr r3, [r7, #0]
|
|
8003da4: 3306 adds r3, #6
|
|
8003da6: b2d2 uxtb r2, r2
|
|
8003da8: 701a strb r2, [r3, #0]
|
|
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
|
|
8003daa: 68fb ldr r3, [r7, #12]
|
|
8003dac: 681a ldr r2, [r3, #0]
|
|
8003dae: 68bb ldr r3, [r7, #8]
|
|
8003db0: 011b lsls r3, r3, #4
|
|
8003db2: 4413 add r3, r2
|
|
8003db4: f503 73de add.w r3, r3, #444 @ 0x1bc
|
|
8003db8: 681b ldr r3, [r3, #0]
|
|
8003dba: 0e1a lsrs r2, r3, #24
|
|
8003dbc: 683b ldr r3, [r7, #0]
|
|
8003dbe: 3307 adds r3, #7
|
|
8003dc0: b2d2 uxtb r2, r2
|
|
8003dc2: 701a strb r2, [r3, #0]
|
|
|
|
/* Release the FIFO */
|
|
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
|
|
8003dc4: 68bb ldr r3, [r7, #8]
|
|
8003dc6: 2b00 cmp r3, #0
|
|
8003dc8: d108 bne.n 8003ddc <HAL_CAN_GetRxMessage+0x216>
|
|
{
|
|
/* Release RX FIFO 0 */
|
|
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
|
|
8003dca: 68fb ldr r3, [r7, #12]
|
|
8003dcc: 681b ldr r3, [r3, #0]
|
|
8003dce: 68da ldr r2, [r3, #12]
|
|
8003dd0: 68fb ldr r3, [r7, #12]
|
|
8003dd2: 681b ldr r3, [r3, #0]
|
|
8003dd4: f042 0220 orr.w r2, r2, #32
|
|
8003dd8: 60da str r2, [r3, #12]
|
|
8003dda: e007 b.n 8003dec <HAL_CAN_GetRxMessage+0x226>
|
|
}
|
|
else /* Rx element is assigned to Rx FIFO 1 */
|
|
{
|
|
/* Release RX FIFO 1 */
|
|
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
|
|
8003ddc: 68fb ldr r3, [r7, #12]
|
|
8003dde: 681b ldr r3, [r3, #0]
|
|
8003de0: 691a ldr r2, [r3, #16]
|
|
8003de2: 68fb ldr r3, [r7, #12]
|
|
8003de4: 681b ldr r3, [r3, #0]
|
|
8003de6: f042 0220 orr.w r2, r2, #32
|
|
8003dea: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8003dec: 2300 movs r3, #0
|
|
8003dee: e006 b.n 8003dfe <HAL_CAN_GetRxMessage+0x238>
|
|
}
|
|
else
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
|
|
8003df0: 68fb ldr r3, [r7, #12]
|
|
8003df2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003df4: f443 2280 orr.w r2, r3, #262144 @ 0x40000
|
|
8003df8: 68fb ldr r3, [r7, #12]
|
|
8003dfa: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8003dfc: 2301 movs r3, #1
|
|
}
|
|
}
|
|
8003dfe: 4618 mov r0, r3
|
|
8003e00: 371c adds r7, #28
|
|
8003e02: 46bd mov sp, r7
|
|
8003e04: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003e08: 4770 bx lr
|
|
|
|
08003e0a <HAL_CAN_ActivateNotification>:
|
|
* @param ActiveITs indicates which interrupts will be enabled.
|
|
* This parameter can be any combination of @arg CAN_Interrupts.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
|
|
{
|
|
8003e0a: b480 push {r7}
|
|
8003e0c: b085 sub sp, #20
|
|
8003e0e: af00 add r7, sp, #0
|
|
8003e10: 6078 str r0, [r7, #4]
|
|
8003e12: 6039 str r1, [r7, #0]
|
|
HAL_CAN_StateTypeDef state = hcan->State;
|
|
8003e14: 687b ldr r3, [r7, #4]
|
|
8003e16: f893 3020 ldrb.w r3, [r3, #32]
|
|
8003e1a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check function parameters */
|
|
assert_param(IS_CAN_IT(ActiveITs));
|
|
|
|
if ((state == HAL_CAN_STATE_READY) ||
|
|
8003e1c: 7bfb ldrb r3, [r7, #15]
|
|
8003e1e: 2b01 cmp r3, #1
|
|
8003e20: d002 beq.n 8003e28 <HAL_CAN_ActivateNotification+0x1e>
|
|
8003e22: 7bfb ldrb r3, [r7, #15]
|
|
8003e24: 2b02 cmp r3, #2
|
|
8003e26: d109 bne.n 8003e3c <HAL_CAN_ActivateNotification+0x32>
|
|
(state == HAL_CAN_STATE_LISTENING))
|
|
{
|
|
/* Enable the selected interrupts */
|
|
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
|
|
8003e28: 687b ldr r3, [r7, #4]
|
|
8003e2a: 681b ldr r3, [r3, #0]
|
|
8003e2c: 6959 ldr r1, [r3, #20]
|
|
8003e2e: 687b ldr r3, [r7, #4]
|
|
8003e30: 681b ldr r3, [r3, #0]
|
|
8003e32: 683a ldr r2, [r7, #0]
|
|
8003e34: 430a orrs r2, r1
|
|
8003e36: 615a str r2, [r3, #20]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8003e38: 2300 movs r3, #0
|
|
8003e3a: e006 b.n 8003e4a <HAL_CAN_ActivateNotification+0x40>
|
|
}
|
|
else
|
|
{
|
|
/* Update error code */
|
|
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
|
|
8003e3c: 687b ldr r3, [r7, #4]
|
|
8003e3e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003e40: f443 2280 orr.w r2, r3, #262144 @ 0x40000
|
|
8003e44: 687b ldr r3, [r7, #4]
|
|
8003e46: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8003e48: 2301 movs r3, #1
|
|
}
|
|
}
|
|
8003e4a: 4618 mov r0, r3
|
|
8003e4c: 3714 adds r7, #20
|
|
8003e4e: 46bd mov sp, r7
|
|
8003e50: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003e54: 4770 bx lr
|
|
|
|
08003e56 <HAL_CAN_IRQHandler>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
|
|
{
|
|
8003e56: b580 push {r7, lr}
|
|
8003e58: b08a sub sp, #40 @ 0x28
|
|
8003e5a: af00 add r7, sp, #0
|
|
8003e5c: 6078 str r0, [r7, #4]
|
|
uint32_t errorcode = HAL_CAN_ERROR_NONE;
|
|
8003e5e: 2300 movs r3, #0
|
|
8003e60: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t interrupts = READ_REG(hcan->Instance->IER);
|
|
8003e62: 687b ldr r3, [r7, #4]
|
|
8003e64: 681b ldr r3, [r3, #0]
|
|
8003e66: 695b ldr r3, [r3, #20]
|
|
8003e68: 623b str r3, [r7, #32]
|
|
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
|
|
8003e6a: 687b ldr r3, [r7, #4]
|
|
8003e6c: 681b ldr r3, [r3, #0]
|
|
8003e6e: 685b ldr r3, [r3, #4]
|
|
8003e70: 61fb str r3, [r7, #28]
|
|
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
|
|
8003e72: 687b ldr r3, [r7, #4]
|
|
8003e74: 681b ldr r3, [r3, #0]
|
|
8003e76: 689b ldr r3, [r3, #8]
|
|
8003e78: 61bb str r3, [r7, #24]
|
|
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
|
|
8003e7a: 687b ldr r3, [r7, #4]
|
|
8003e7c: 681b ldr r3, [r3, #0]
|
|
8003e7e: 68db ldr r3, [r3, #12]
|
|
8003e80: 617b str r3, [r7, #20]
|
|
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
|
|
8003e82: 687b ldr r3, [r7, #4]
|
|
8003e84: 681b ldr r3, [r3, #0]
|
|
8003e86: 691b ldr r3, [r3, #16]
|
|
8003e88: 613b str r3, [r7, #16]
|
|
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
|
|
8003e8a: 687b ldr r3, [r7, #4]
|
|
8003e8c: 681b ldr r3, [r3, #0]
|
|
8003e8e: 699b ldr r3, [r3, #24]
|
|
8003e90: 60fb str r3, [r7, #12]
|
|
|
|
/* Transmit Mailbox empty interrupt management *****************************/
|
|
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
|
|
8003e92: 6a3b ldr r3, [r7, #32]
|
|
8003e94: f003 0301 and.w r3, r3, #1
|
|
8003e98: 2b00 cmp r3, #0
|
|
8003e9a: d07c beq.n 8003f96 <HAL_CAN_IRQHandler+0x140>
|
|
{
|
|
/* Transmit Mailbox 0 management *****************************************/
|
|
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
|
|
8003e9c: 69bb ldr r3, [r7, #24]
|
|
8003e9e: f003 0301 and.w r3, r3, #1
|
|
8003ea2: 2b00 cmp r3, #0
|
|
8003ea4: d023 beq.n 8003eee <HAL_CAN_IRQHandler+0x98>
|
|
{
|
|
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
|
|
8003ea6: 687b ldr r3, [r7, #4]
|
|
8003ea8: 681b ldr r3, [r3, #0]
|
|
8003eaa: 2201 movs r2, #1
|
|
8003eac: 609a str r2, [r3, #8]
|
|
|
|
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
|
|
8003eae: 69bb ldr r3, [r7, #24]
|
|
8003eb0: f003 0302 and.w r3, r3, #2
|
|
8003eb4: 2b00 cmp r3, #0
|
|
8003eb6: d003 beq.n 8003ec0 <HAL_CAN_IRQHandler+0x6a>
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->TxMailbox0CompleteCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_TxMailbox0CompleteCallback(hcan);
|
|
8003eb8: 6878 ldr r0, [r7, #4]
|
|
8003eba: f000 f983 bl 80041c4 <HAL_CAN_TxMailbox0CompleteCallback>
|
|
8003ebe: e016 b.n 8003eee <HAL_CAN_IRQHandler+0x98>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
if ((tsrflags & CAN_TSR_ALST0) != 0U)
|
|
8003ec0: 69bb ldr r3, [r7, #24]
|
|
8003ec2: f003 0304 and.w r3, r3, #4
|
|
8003ec6: 2b00 cmp r3, #0
|
|
8003ec8: d004 beq.n 8003ed4 <HAL_CAN_IRQHandler+0x7e>
|
|
{
|
|
/* Update error code */
|
|
errorcode |= HAL_CAN_ERROR_TX_ALST0;
|
|
8003eca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003ecc: f443 6300 orr.w r3, r3, #2048 @ 0x800
|
|
8003ed0: 627b str r3, [r7, #36] @ 0x24
|
|
8003ed2: e00c b.n 8003eee <HAL_CAN_IRQHandler+0x98>
|
|
}
|
|
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
|
|
8003ed4: 69bb ldr r3, [r7, #24]
|
|
8003ed6: f003 0308 and.w r3, r3, #8
|
|
8003eda: 2b00 cmp r3, #0
|
|
8003edc: d004 beq.n 8003ee8 <HAL_CAN_IRQHandler+0x92>
|
|
{
|
|
/* Update error code */
|
|
errorcode |= HAL_CAN_ERROR_TX_TERR0;
|
|
8003ede: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003ee0: f443 5380 orr.w r3, r3, #4096 @ 0x1000
|
|
8003ee4: 627b str r3, [r7, #36] @ 0x24
|
|
8003ee6: e002 b.n 8003eee <HAL_CAN_IRQHandler+0x98>
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->TxMailbox0AbortCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_TxMailbox0AbortCallback(hcan);
|
|
8003ee8: 6878 ldr r0, [r7, #4]
|
|
8003eea: f000 f989 bl 8004200 <HAL_CAN_TxMailbox0AbortCallback>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Transmit Mailbox 1 management *****************************************/
|
|
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
|
|
8003eee: 69bb ldr r3, [r7, #24]
|
|
8003ef0: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003ef4: 2b00 cmp r3, #0
|
|
8003ef6: d024 beq.n 8003f42 <HAL_CAN_IRQHandler+0xec>
|
|
{
|
|
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
|
|
8003ef8: 687b ldr r3, [r7, #4]
|
|
8003efa: 681b ldr r3, [r3, #0]
|
|
8003efc: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8003f00: 609a str r2, [r3, #8]
|
|
|
|
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
|
|
8003f02: 69bb ldr r3, [r7, #24]
|
|
8003f04: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8003f08: 2b00 cmp r3, #0
|
|
8003f0a: d003 beq.n 8003f14 <HAL_CAN_IRQHandler+0xbe>
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->TxMailbox1CompleteCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_TxMailbox1CompleteCallback(hcan);
|
|
8003f0c: 6878 ldr r0, [r7, #4]
|
|
8003f0e: f000 f963 bl 80041d8 <HAL_CAN_TxMailbox1CompleteCallback>
|
|
8003f12: e016 b.n 8003f42 <HAL_CAN_IRQHandler+0xec>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
if ((tsrflags & CAN_TSR_ALST1) != 0U)
|
|
8003f14: 69bb ldr r3, [r7, #24]
|
|
8003f16: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003f1a: 2b00 cmp r3, #0
|
|
8003f1c: d004 beq.n 8003f28 <HAL_CAN_IRQHandler+0xd2>
|
|
{
|
|
/* Update error code */
|
|
errorcode |= HAL_CAN_ERROR_TX_ALST1;
|
|
8003f1e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003f20: f443 5300 orr.w r3, r3, #8192 @ 0x2000
|
|
8003f24: 627b str r3, [r7, #36] @ 0x24
|
|
8003f26: e00c b.n 8003f42 <HAL_CAN_IRQHandler+0xec>
|
|
}
|
|
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
|
|
8003f28: 69bb ldr r3, [r7, #24]
|
|
8003f2a: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8003f2e: 2b00 cmp r3, #0
|
|
8003f30: d004 beq.n 8003f3c <HAL_CAN_IRQHandler+0xe6>
|
|
{
|
|
/* Update error code */
|
|
errorcode |= HAL_CAN_ERROR_TX_TERR1;
|
|
8003f32: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003f34: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8003f38: 627b str r3, [r7, #36] @ 0x24
|
|
8003f3a: e002 b.n 8003f42 <HAL_CAN_IRQHandler+0xec>
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->TxMailbox1AbortCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_TxMailbox1AbortCallback(hcan);
|
|
8003f3c: 6878 ldr r0, [r7, #4]
|
|
8003f3e: f000 f969 bl 8004214 <HAL_CAN_TxMailbox1AbortCallback>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Transmit Mailbox 2 management *****************************************/
|
|
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
|
|
8003f42: 69bb ldr r3, [r7, #24]
|
|
8003f44: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8003f48: 2b00 cmp r3, #0
|
|
8003f4a: d024 beq.n 8003f96 <HAL_CAN_IRQHandler+0x140>
|
|
{
|
|
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
|
|
8003f4c: 687b ldr r3, [r7, #4]
|
|
8003f4e: 681b ldr r3, [r3, #0]
|
|
8003f50: f44f 3280 mov.w r2, #65536 @ 0x10000
|
|
8003f54: 609a str r2, [r3, #8]
|
|
|
|
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
|
|
8003f56: 69bb ldr r3, [r7, #24]
|
|
8003f58: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003f5c: 2b00 cmp r3, #0
|
|
8003f5e: d003 beq.n 8003f68 <HAL_CAN_IRQHandler+0x112>
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->TxMailbox2CompleteCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_TxMailbox2CompleteCallback(hcan);
|
|
8003f60: 6878 ldr r0, [r7, #4]
|
|
8003f62: f000 f943 bl 80041ec <HAL_CAN_TxMailbox2CompleteCallback>
|
|
8003f66: e016 b.n 8003f96 <HAL_CAN_IRQHandler+0x140>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
if ((tsrflags & CAN_TSR_ALST2) != 0U)
|
|
8003f68: 69bb ldr r3, [r7, #24]
|
|
8003f6a: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8003f6e: 2b00 cmp r3, #0
|
|
8003f70: d004 beq.n 8003f7c <HAL_CAN_IRQHandler+0x126>
|
|
{
|
|
/* Update error code */
|
|
errorcode |= HAL_CAN_ERROR_TX_ALST2;
|
|
8003f72: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003f74: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8003f78: 627b str r3, [r7, #36] @ 0x24
|
|
8003f7a: e00c b.n 8003f96 <HAL_CAN_IRQHandler+0x140>
|
|
}
|
|
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
|
|
8003f7c: 69bb ldr r3, [r7, #24]
|
|
8003f7e: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8003f82: 2b00 cmp r3, #0
|
|
8003f84: d004 beq.n 8003f90 <HAL_CAN_IRQHandler+0x13a>
|
|
{
|
|
/* Update error code */
|
|
errorcode |= HAL_CAN_ERROR_TX_TERR2;
|
|
8003f86: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003f88: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003f8c: 627b str r3, [r7, #36] @ 0x24
|
|
8003f8e: e002 b.n 8003f96 <HAL_CAN_IRQHandler+0x140>
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->TxMailbox2AbortCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_TxMailbox2AbortCallback(hcan);
|
|
8003f90: 6878 ldr r0, [r7, #4]
|
|
8003f92: f000 f949 bl 8004228 <HAL_CAN_TxMailbox2AbortCallback>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Receive FIFO 0 overrun interrupt management *****************************/
|
|
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
|
|
8003f96: 6a3b ldr r3, [r7, #32]
|
|
8003f98: f003 0308 and.w r3, r3, #8
|
|
8003f9c: 2b00 cmp r3, #0
|
|
8003f9e: d00c beq.n 8003fba <HAL_CAN_IRQHandler+0x164>
|
|
{
|
|
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
|
|
8003fa0: 697b ldr r3, [r7, #20]
|
|
8003fa2: f003 0310 and.w r3, r3, #16
|
|
8003fa6: 2b00 cmp r3, #0
|
|
8003fa8: d007 beq.n 8003fba <HAL_CAN_IRQHandler+0x164>
|
|
{
|
|
/* Set CAN error code to Rx Fifo 0 overrun error */
|
|
errorcode |= HAL_CAN_ERROR_RX_FOV0;
|
|
8003faa: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003fac: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8003fb0: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Clear FIFO0 Overrun Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
|
|
8003fb2: 687b ldr r3, [r7, #4]
|
|
8003fb4: 681b ldr r3, [r3, #0]
|
|
8003fb6: 2210 movs r2, #16
|
|
8003fb8: 60da str r2, [r3, #12]
|
|
}
|
|
}
|
|
|
|
/* Receive FIFO 0 full interrupt management ********************************/
|
|
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
|
|
8003fba: 6a3b ldr r3, [r7, #32]
|
|
8003fbc: f003 0304 and.w r3, r3, #4
|
|
8003fc0: 2b00 cmp r3, #0
|
|
8003fc2: d00b beq.n 8003fdc <HAL_CAN_IRQHandler+0x186>
|
|
{
|
|
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
|
|
8003fc4: 697b ldr r3, [r7, #20]
|
|
8003fc6: f003 0308 and.w r3, r3, #8
|
|
8003fca: 2b00 cmp r3, #0
|
|
8003fcc: d006 beq.n 8003fdc <HAL_CAN_IRQHandler+0x186>
|
|
{
|
|
/* Clear FIFO 0 full Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
|
|
8003fce: 687b ldr r3, [r7, #4]
|
|
8003fd0: 681b ldr r3, [r3, #0]
|
|
8003fd2: 2208 movs r2, #8
|
|
8003fd4: 60da str r2, [r3, #12]
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->RxFifo0FullCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_RxFifo0FullCallback(hcan);
|
|
8003fd6: 6878 ldr r0, [r7, #4]
|
|
8003fd8: f000 f930 bl 800423c <HAL_CAN_RxFifo0FullCallback>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Receive FIFO 0 message pending interrupt management *********************/
|
|
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
|
|
8003fdc: 6a3b ldr r3, [r7, #32]
|
|
8003fde: f003 0302 and.w r3, r3, #2
|
|
8003fe2: 2b00 cmp r3, #0
|
|
8003fe4: d009 beq.n 8003ffa <HAL_CAN_IRQHandler+0x1a4>
|
|
{
|
|
/* Check if message is still pending */
|
|
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
|
|
8003fe6: 687b ldr r3, [r7, #4]
|
|
8003fe8: 681b ldr r3, [r3, #0]
|
|
8003fea: 68db ldr r3, [r3, #12]
|
|
8003fec: f003 0303 and.w r3, r3, #3
|
|
8003ff0: 2b00 cmp r3, #0
|
|
8003ff2: d002 beq.n 8003ffa <HAL_CAN_IRQHandler+0x1a4>
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->RxFifo0MsgPendingCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
|
|
8003ff4: 6878 ldr r0, [r7, #4]
|
|
8003ff6: f7fc fde1 bl 8000bbc <HAL_CAN_RxFifo0MsgPendingCallback>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Receive FIFO 1 overrun interrupt management *****************************/
|
|
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
|
|
8003ffa: 6a3b ldr r3, [r7, #32]
|
|
8003ffc: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8004000: 2b00 cmp r3, #0
|
|
8004002: d00c beq.n 800401e <HAL_CAN_IRQHandler+0x1c8>
|
|
{
|
|
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
|
|
8004004: 693b ldr r3, [r7, #16]
|
|
8004006: f003 0310 and.w r3, r3, #16
|
|
800400a: 2b00 cmp r3, #0
|
|
800400c: d007 beq.n 800401e <HAL_CAN_IRQHandler+0x1c8>
|
|
{
|
|
/* Set CAN error code to Rx Fifo 1 overrun error */
|
|
errorcode |= HAL_CAN_ERROR_RX_FOV1;
|
|
800400e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004010: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8004014: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Clear FIFO1 Overrun Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
|
|
8004016: 687b ldr r3, [r7, #4]
|
|
8004018: 681b ldr r3, [r3, #0]
|
|
800401a: 2210 movs r2, #16
|
|
800401c: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
|
|
/* Receive FIFO 1 full interrupt management ********************************/
|
|
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
|
|
800401e: 6a3b ldr r3, [r7, #32]
|
|
8004020: f003 0320 and.w r3, r3, #32
|
|
8004024: 2b00 cmp r3, #0
|
|
8004026: d00b beq.n 8004040 <HAL_CAN_IRQHandler+0x1ea>
|
|
{
|
|
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
|
|
8004028: 693b ldr r3, [r7, #16]
|
|
800402a: f003 0308 and.w r3, r3, #8
|
|
800402e: 2b00 cmp r3, #0
|
|
8004030: d006 beq.n 8004040 <HAL_CAN_IRQHandler+0x1ea>
|
|
{
|
|
/* Clear FIFO 1 full Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
|
|
8004032: 687b ldr r3, [r7, #4]
|
|
8004034: 681b ldr r3, [r3, #0]
|
|
8004036: 2208 movs r2, #8
|
|
8004038: 611a str r2, [r3, #16]
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->RxFifo1FullCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_RxFifo1FullCallback(hcan);
|
|
800403a: 6878 ldr r0, [r7, #4]
|
|
800403c: f000 f912 bl 8004264 <HAL_CAN_RxFifo1FullCallback>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Receive FIFO 1 message pending interrupt management *********************/
|
|
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
|
|
8004040: 6a3b ldr r3, [r7, #32]
|
|
8004042: f003 0310 and.w r3, r3, #16
|
|
8004046: 2b00 cmp r3, #0
|
|
8004048: d009 beq.n 800405e <HAL_CAN_IRQHandler+0x208>
|
|
{
|
|
/* Check if message is still pending */
|
|
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
|
|
800404a: 687b ldr r3, [r7, #4]
|
|
800404c: 681b ldr r3, [r3, #0]
|
|
800404e: 691b ldr r3, [r3, #16]
|
|
8004050: f003 0303 and.w r3, r3, #3
|
|
8004054: 2b00 cmp r3, #0
|
|
8004056: d002 beq.n 800405e <HAL_CAN_IRQHandler+0x208>
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->RxFifo1MsgPendingCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
|
|
8004058: 6878 ldr r0, [r7, #4]
|
|
800405a: f000 f8f9 bl 8004250 <HAL_CAN_RxFifo1MsgPendingCallback>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Sleep interrupt management *********************************************/
|
|
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
|
|
800405e: 6a3b ldr r3, [r7, #32]
|
|
8004060: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004064: 2b00 cmp r3, #0
|
|
8004066: d00b beq.n 8004080 <HAL_CAN_IRQHandler+0x22a>
|
|
{
|
|
if ((msrflags & CAN_MSR_SLAKI) != 0U)
|
|
8004068: 69fb ldr r3, [r7, #28]
|
|
800406a: f003 0310 and.w r3, r3, #16
|
|
800406e: 2b00 cmp r3, #0
|
|
8004070: d006 beq.n 8004080 <HAL_CAN_IRQHandler+0x22a>
|
|
{
|
|
/* Clear Sleep interrupt Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
|
|
8004072: 687b ldr r3, [r7, #4]
|
|
8004074: 681b ldr r3, [r3, #0]
|
|
8004076: 2210 movs r2, #16
|
|
8004078: 605a str r2, [r3, #4]
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->SleepCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_SleepCallback(hcan);
|
|
800407a: 6878 ldr r0, [r7, #4]
|
|
800407c: f000 f8fc bl 8004278 <HAL_CAN_SleepCallback>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* WakeUp interrupt management *********************************************/
|
|
if ((interrupts & CAN_IT_WAKEUP) != 0U)
|
|
8004080: 6a3b ldr r3, [r7, #32]
|
|
8004082: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8004086: 2b00 cmp r3, #0
|
|
8004088: d00b beq.n 80040a2 <HAL_CAN_IRQHandler+0x24c>
|
|
{
|
|
if ((msrflags & CAN_MSR_WKUI) != 0U)
|
|
800408a: 69fb ldr r3, [r7, #28]
|
|
800408c: f003 0308 and.w r3, r3, #8
|
|
8004090: 2b00 cmp r3, #0
|
|
8004092: d006 beq.n 80040a2 <HAL_CAN_IRQHandler+0x24c>
|
|
{
|
|
/* Clear WakeUp Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
|
|
8004094: 687b ldr r3, [r7, #4]
|
|
8004096: 681b ldr r3, [r3, #0]
|
|
8004098: 2208 movs r2, #8
|
|
800409a: 605a str r2, [r3, #4]
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->WakeUpFromRxMsgCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
|
|
800409c: 6878 ldr r0, [r7, #4]
|
|
800409e: f000 f8f5 bl 800428c <HAL_CAN_WakeUpFromRxMsgCallback>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Error interrupts management *********************************************/
|
|
if ((interrupts & CAN_IT_ERROR) != 0U)
|
|
80040a2: 6a3b ldr r3, [r7, #32]
|
|
80040a4: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80040a8: 2b00 cmp r3, #0
|
|
80040aa: d07b beq.n 80041a4 <HAL_CAN_IRQHandler+0x34e>
|
|
{
|
|
if ((msrflags & CAN_MSR_ERRI) != 0U)
|
|
80040ac: 69fb ldr r3, [r7, #28]
|
|
80040ae: f003 0304 and.w r3, r3, #4
|
|
80040b2: 2b00 cmp r3, #0
|
|
80040b4: d072 beq.n 800419c <HAL_CAN_IRQHandler+0x346>
|
|
{
|
|
/* Check Error Warning Flag */
|
|
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
|
|
80040b6: 6a3b ldr r3, [r7, #32]
|
|
80040b8: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80040bc: 2b00 cmp r3, #0
|
|
80040be: d008 beq.n 80040d2 <HAL_CAN_IRQHandler+0x27c>
|
|
((esrflags & CAN_ESR_EWGF) != 0U))
|
|
80040c0: 68fb ldr r3, [r7, #12]
|
|
80040c2: f003 0301 and.w r3, r3, #1
|
|
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
|
|
80040c6: 2b00 cmp r3, #0
|
|
80040c8: d003 beq.n 80040d2 <HAL_CAN_IRQHandler+0x27c>
|
|
{
|
|
/* Set CAN error code to Error Warning */
|
|
errorcode |= HAL_CAN_ERROR_EWG;
|
|
80040ca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80040cc: f043 0301 orr.w r3, r3, #1
|
|
80040d0: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* No need for clear of Error Warning Flag as read-only */
|
|
}
|
|
|
|
/* Check Error Passive Flag */
|
|
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
|
|
80040d2: 6a3b ldr r3, [r7, #32]
|
|
80040d4: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80040d8: 2b00 cmp r3, #0
|
|
80040da: d008 beq.n 80040ee <HAL_CAN_IRQHandler+0x298>
|
|
((esrflags & CAN_ESR_EPVF) != 0U))
|
|
80040dc: 68fb ldr r3, [r7, #12]
|
|
80040de: f003 0302 and.w r3, r3, #2
|
|
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
|
|
80040e2: 2b00 cmp r3, #0
|
|
80040e4: d003 beq.n 80040ee <HAL_CAN_IRQHandler+0x298>
|
|
{
|
|
/* Set CAN error code to Error Passive */
|
|
errorcode |= HAL_CAN_ERROR_EPV;
|
|
80040e6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80040e8: f043 0302 orr.w r3, r3, #2
|
|
80040ec: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* No need for clear of Error Passive Flag as read-only */
|
|
}
|
|
|
|
/* Check Bus-off Flag */
|
|
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
|
|
80040ee: 6a3b ldr r3, [r7, #32]
|
|
80040f0: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80040f4: 2b00 cmp r3, #0
|
|
80040f6: d008 beq.n 800410a <HAL_CAN_IRQHandler+0x2b4>
|
|
((esrflags & CAN_ESR_BOFF) != 0U))
|
|
80040f8: 68fb ldr r3, [r7, #12]
|
|
80040fa: f003 0304 and.w r3, r3, #4
|
|
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
|
|
80040fe: 2b00 cmp r3, #0
|
|
8004100: d003 beq.n 800410a <HAL_CAN_IRQHandler+0x2b4>
|
|
{
|
|
/* Set CAN error code to Bus-Off */
|
|
errorcode |= HAL_CAN_ERROR_BOF;
|
|
8004102: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004104: f043 0304 orr.w r3, r3, #4
|
|
8004108: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* No need for clear of Error Bus-Off as read-only */
|
|
}
|
|
|
|
/* Check Last Error Code Flag */
|
|
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
|
|
800410a: 6a3b ldr r3, [r7, #32]
|
|
800410c: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8004110: 2b00 cmp r3, #0
|
|
8004112: d043 beq.n 800419c <HAL_CAN_IRQHandler+0x346>
|
|
((esrflags & CAN_ESR_LEC) != 0U))
|
|
8004114: 68fb ldr r3, [r7, #12]
|
|
8004116: f003 0370 and.w r3, r3, #112 @ 0x70
|
|
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
|
|
800411a: 2b00 cmp r3, #0
|
|
800411c: d03e beq.n 800419c <HAL_CAN_IRQHandler+0x346>
|
|
{
|
|
switch (esrflags & CAN_ESR_LEC)
|
|
800411e: 68fb ldr r3, [r7, #12]
|
|
8004120: f003 0370 and.w r3, r3, #112 @ 0x70
|
|
8004124: 2b60 cmp r3, #96 @ 0x60
|
|
8004126: d02b beq.n 8004180 <HAL_CAN_IRQHandler+0x32a>
|
|
8004128: 2b60 cmp r3, #96 @ 0x60
|
|
800412a: d82e bhi.n 800418a <HAL_CAN_IRQHandler+0x334>
|
|
800412c: 2b50 cmp r3, #80 @ 0x50
|
|
800412e: d022 beq.n 8004176 <HAL_CAN_IRQHandler+0x320>
|
|
8004130: 2b50 cmp r3, #80 @ 0x50
|
|
8004132: d82a bhi.n 800418a <HAL_CAN_IRQHandler+0x334>
|
|
8004134: 2b40 cmp r3, #64 @ 0x40
|
|
8004136: d019 beq.n 800416c <HAL_CAN_IRQHandler+0x316>
|
|
8004138: 2b40 cmp r3, #64 @ 0x40
|
|
800413a: d826 bhi.n 800418a <HAL_CAN_IRQHandler+0x334>
|
|
800413c: 2b30 cmp r3, #48 @ 0x30
|
|
800413e: d010 beq.n 8004162 <HAL_CAN_IRQHandler+0x30c>
|
|
8004140: 2b30 cmp r3, #48 @ 0x30
|
|
8004142: d822 bhi.n 800418a <HAL_CAN_IRQHandler+0x334>
|
|
8004144: 2b10 cmp r3, #16
|
|
8004146: d002 beq.n 800414e <HAL_CAN_IRQHandler+0x2f8>
|
|
8004148: 2b20 cmp r3, #32
|
|
800414a: d005 beq.n 8004158 <HAL_CAN_IRQHandler+0x302>
|
|
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
|
|
/* Set CAN error code to CRC error */
|
|
errorcode |= HAL_CAN_ERROR_CRC;
|
|
break;
|
|
default:
|
|
break;
|
|
800414c: e01d b.n 800418a <HAL_CAN_IRQHandler+0x334>
|
|
errorcode |= HAL_CAN_ERROR_STF;
|
|
800414e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004150: f043 0308 orr.w r3, r3, #8
|
|
8004154: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004156: e019 b.n 800418c <HAL_CAN_IRQHandler+0x336>
|
|
errorcode |= HAL_CAN_ERROR_FOR;
|
|
8004158: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800415a: f043 0310 orr.w r3, r3, #16
|
|
800415e: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004160: e014 b.n 800418c <HAL_CAN_IRQHandler+0x336>
|
|
errorcode |= HAL_CAN_ERROR_ACK;
|
|
8004162: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004164: f043 0320 orr.w r3, r3, #32
|
|
8004168: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
800416a: e00f b.n 800418c <HAL_CAN_IRQHandler+0x336>
|
|
errorcode |= HAL_CAN_ERROR_BR;
|
|
800416c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800416e: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8004172: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004174: e00a b.n 800418c <HAL_CAN_IRQHandler+0x336>
|
|
errorcode |= HAL_CAN_ERROR_BD;
|
|
8004176: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004178: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
800417c: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
800417e: e005 b.n 800418c <HAL_CAN_IRQHandler+0x336>
|
|
errorcode |= HAL_CAN_ERROR_CRC;
|
|
8004180: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004182: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004186: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004188: e000 b.n 800418c <HAL_CAN_IRQHandler+0x336>
|
|
break;
|
|
800418a: bf00 nop
|
|
}
|
|
|
|
/* Clear Last error code Flag */
|
|
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
|
|
800418c: 687b ldr r3, [r7, #4]
|
|
800418e: 681b ldr r3, [r3, #0]
|
|
8004190: 699a ldr r2, [r3, #24]
|
|
8004192: 687b ldr r3, [r7, #4]
|
|
8004194: 681b ldr r3, [r3, #0]
|
|
8004196: f022 0270 bic.w r2, r2, #112 @ 0x70
|
|
800419a: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
|
|
/* Clear ERRI Flag */
|
|
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
|
|
800419c: 687b ldr r3, [r7, #4]
|
|
800419e: 681b ldr r3, [r3, #0]
|
|
80041a0: 2204 movs r2, #4
|
|
80041a2: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Call the Error call Back in case of Errors */
|
|
if (errorcode != HAL_CAN_ERROR_NONE)
|
|
80041a4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80041a6: 2b00 cmp r3, #0
|
|
80041a8: d008 beq.n 80041bc <HAL_CAN_IRQHandler+0x366>
|
|
{
|
|
/* Update error code in handle */
|
|
hcan->ErrorCode |= errorcode;
|
|
80041aa: 687b ldr r3, [r7, #4]
|
|
80041ac: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
80041ae: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80041b0: 431a orrs r2, r3
|
|
80041b2: 687b ldr r3, [r7, #4]
|
|
80041b4: 625a str r2, [r3, #36] @ 0x24
|
|
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
|
/* Call registered callback*/
|
|
hcan->ErrorCallback(hcan);
|
|
#else
|
|
/* Call weak (surcharged) callback */
|
|
HAL_CAN_ErrorCallback(hcan);
|
|
80041b6: 6878 ldr r0, [r7, #4]
|
|
80041b8: f000 f872 bl 80042a0 <HAL_CAN_ErrorCallback>
|
|
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
80041bc: bf00 nop
|
|
80041be: 3728 adds r7, #40 @ 0x28
|
|
80041c0: 46bd mov sp, r7
|
|
80041c2: bd80 pop {r7, pc}
|
|
|
|
080041c4 <HAL_CAN_TxMailbox0CompleteCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
80041c4: b480 push {r7}
|
|
80041c6: b083 sub sp, #12
|
|
80041c8: af00 add r7, sp, #0
|
|
80041ca: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
|
|
user file
|
|
*/
|
|
}
|
|
80041cc: bf00 nop
|
|
80041ce: 370c adds r7, #12
|
|
80041d0: 46bd mov sp, r7
|
|
80041d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80041d6: 4770 bx lr
|
|
|
|
080041d8 <HAL_CAN_TxMailbox1CompleteCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
80041d8: b480 push {r7}
|
|
80041da: b083 sub sp, #12
|
|
80041dc: af00 add r7, sp, #0
|
|
80041de: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
|
|
user file
|
|
*/
|
|
}
|
|
80041e0: bf00 nop
|
|
80041e2: 370c adds r7, #12
|
|
80041e4: 46bd mov sp, r7
|
|
80041e6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80041ea: 4770 bx lr
|
|
|
|
080041ec <HAL_CAN_TxMailbox2CompleteCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
80041ec: b480 push {r7}
|
|
80041ee: b083 sub sp, #12
|
|
80041f0: af00 add r7, sp, #0
|
|
80041f2: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
|
|
user file
|
|
*/
|
|
}
|
|
80041f4: bf00 nop
|
|
80041f6: 370c adds r7, #12
|
|
80041f8: 46bd mov sp, r7
|
|
80041fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80041fe: 4770 bx lr
|
|
|
|
08004200 <HAL_CAN_TxMailbox0AbortCallback>:
|
|
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
8004200: b480 push {r7}
|
|
8004202: b083 sub sp, #12
|
|
8004204: af00 add r7, sp, #0
|
|
8004206: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
|
|
user file
|
|
*/
|
|
}
|
|
8004208: bf00 nop
|
|
800420a: 370c adds r7, #12
|
|
800420c: 46bd mov sp, r7
|
|
800420e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004212: 4770 bx lr
|
|
|
|
08004214 <HAL_CAN_TxMailbox1AbortCallback>:
|
|
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
8004214: b480 push {r7}
|
|
8004216: b083 sub sp, #12
|
|
8004218: af00 add r7, sp, #0
|
|
800421a: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
|
|
user file
|
|
*/
|
|
}
|
|
800421c: bf00 nop
|
|
800421e: 370c adds r7, #12
|
|
8004220: 46bd mov sp, r7
|
|
8004222: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004226: 4770 bx lr
|
|
|
|
08004228 <HAL_CAN_TxMailbox2AbortCallback>:
|
|
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
8004228: b480 push {r7}
|
|
800422a: b083 sub sp, #12
|
|
800422c: af00 add r7, sp, #0
|
|
800422e: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
|
|
user file
|
|
*/
|
|
}
|
|
8004230: bf00 nop
|
|
8004232: 370c adds r7, #12
|
|
8004234: 46bd mov sp, r7
|
|
8004236: f85d 7b04 ldr.w r7, [sp], #4
|
|
800423a: 4770 bx lr
|
|
|
|
0800423c <HAL_CAN_RxFifo0FullCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
800423c: b480 push {r7}
|
|
800423e: b083 sub sp, #12
|
|
8004240: af00 add r7, sp, #0
|
|
8004242: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
|
|
file
|
|
*/
|
|
}
|
|
8004244: bf00 nop
|
|
8004246: 370c adds r7, #12
|
|
8004248: 46bd mov sp, r7
|
|
800424a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800424e: 4770 bx lr
|
|
|
|
08004250 <HAL_CAN_RxFifo1MsgPendingCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
8004250: b480 push {r7}
|
|
8004252: b083 sub sp, #12
|
|
8004254: af00 add r7, sp, #0
|
|
8004256: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
|
|
user file
|
|
*/
|
|
}
|
|
8004258: bf00 nop
|
|
800425a: 370c adds r7, #12
|
|
800425c: 46bd mov sp, r7
|
|
800425e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004262: 4770 bx lr
|
|
|
|
08004264 <HAL_CAN_RxFifo1FullCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
8004264: b480 push {r7}
|
|
8004266: b083 sub sp, #12
|
|
8004268: af00 add r7, sp, #0
|
|
800426a: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
|
|
file
|
|
*/
|
|
}
|
|
800426c: bf00 nop
|
|
800426e: 370c adds r7, #12
|
|
8004270: 46bd mov sp, r7
|
|
8004272: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004276: 4770 bx lr
|
|
|
|
08004278 <HAL_CAN_SleepCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
8004278: b480 push {r7}
|
|
800427a: b083 sub sp, #12
|
|
800427c: af00 add r7, sp, #0
|
|
800427e: 6078 str r0, [r7, #4]
|
|
UNUSED(hcan);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_SleepCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004280: bf00 nop
|
|
8004282: 370c adds r7, #12
|
|
8004284: 46bd mov sp, r7
|
|
8004286: f85d 7b04 ldr.w r7, [sp], #4
|
|
800428a: 4770 bx lr
|
|
|
|
0800428c <HAL_CAN_WakeUpFromRxMsgCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
800428c: b480 push {r7}
|
|
800428e: b083 sub sp, #12
|
|
8004290: af00 add r7, sp, #0
|
|
8004292: 6078 str r0, [r7, #4]
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
|
|
user file
|
|
*/
|
|
}
|
|
8004294: bf00 nop
|
|
8004296: 370c adds r7, #12
|
|
8004298: 46bd mov sp, r7
|
|
800429a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800429e: 4770 bx lr
|
|
|
|
080042a0 <HAL_CAN_ErrorCallback>:
|
|
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
|
|
* the configuration information for the specified CAN.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
|
|
{
|
|
80042a0: b480 push {r7}
|
|
80042a2: b083 sub sp, #12
|
|
80042a4: af00 add r7, sp, #0
|
|
80042a6: 6078 str r0, [r7, #4]
|
|
UNUSED(hcan);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_CAN_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80042a8: bf00 nop
|
|
80042aa: 370c adds r7, #12
|
|
80042ac: 46bd mov sp, r7
|
|
80042ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
80042b2: 4770 bx lr
|
|
|
|
080042b4 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80042b4: b480 push {r7}
|
|
80042b6: b085 sub sp, #20
|
|
80042b8: af00 add r7, sp, #0
|
|
80042ba: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80042bc: 687b ldr r3, [r7, #4]
|
|
80042be: f003 0307 and.w r3, r3, #7
|
|
80042c2: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80042c4: 4b0c ldr r3, [pc, #48] @ (80042f8 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80042c6: 68db ldr r3, [r3, #12]
|
|
80042c8: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80042ca: 68ba ldr r2, [r7, #8]
|
|
80042cc: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80042d0: 4013 ands r3, r2
|
|
80042d2: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80042d4: 68fb ldr r3, [r7, #12]
|
|
80042d6: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80042d8: 68bb ldr r3, [r7, #8]
|
|
80042da: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80042dc: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80042e0: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80042e4: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80042e6: 4a04 ldr r2, [pc, #16] @ (80042f8 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80042e8: 68bb ldr r3, [r7, #8]
|
|
80042ea: 60d3 str r3, [r2, #12]
|
|
}
|
|
80042ec: bf00 nop
|
|
80042ee: 3714 adds r7, #20
|
|
80042f0: 46bd mov sp, r7
|
|
80042f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80042f6: 4770 bx lr
|
|
80042f8: e000ed00 .word 0xe000ed00
|
|
|
|
080042fc <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80042fc: b480 push {r7}
|
|
80042fe: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8004300: 4b04 ldr r3, [pc, #16] @ (8004314 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8004302: 68db ldr r3, [r3, #12]
|
|
8004304: 0a1b lsrs r3, r3, #8
|
|
8004306: f003 0307 and.w r3, r3, #7
|
|
}
|
|
800430a: 4618 mov r0, r3
|
|
800430c: 46bd mov sp, r7
|
|
800430e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004312: 4770 bx lr
|
|
8004314: e000ed00 .word 0xe000ed00
|
|
|
|
08004318 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8004318: b480 push {r7}
|
|
800431a: b083 sub sp, #12
|
|
800431c: af00 add r7, sp, #0
|
|
800431e: 4603 mov r3, r0
|
|
8004320: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8004322: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8004326: 2b00 cmp r3, #0
|
|
8004328: db0b blt.n 8004342 <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
800432a: 79fb ldrb r3, [r7, #7]
|
|
800432c: f003 021f and.w r2, r3, #31
|
|
8004330: 4907 ldr r1, [pc, #28] @ (8004350 <__NVIC_EnableIRQ+0x38>)
|
|
8004332: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8004336: 095b lsrs r3, r3, #5
|
|
8004338: 2001 movs r0, #1
|
|
800433a: fa00 f202 lsl.w r2, r0, r2
|
|
800433e: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
}
|
|
}
|
|
8004342: bf00 nop
|
|
8004344: 370c adds r7, #12
|
|
8004346: 46bd mov sp, r7
|
|
8004348: f85d 7b04 ldr.w r7, [sp], #4
|
|
800434c: 4770 bx lr
|
|
800434e: bf00 nop
|
|
8004350: e000e100 .word 0xe000e100
|
|
|
|
08004354 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8004354: b480 push {r7}
|
|
8004356: b083 sub sp, #12
|
|
8004358: af00 add r7, sp, #0
|
|
800435a: 4603 mov r3, r0
|
|
800435c: 6039 str r1, [r7, #0]
|
|
800435e: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8004360: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8004364: 2b00 cmp r3, #0
|
|
8004366: db0a blt.n 800437e <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8004368: 683b ldr r3, [r7, #0]
|
|
800436a: b2da uxtb r2, r3
|
|
800436c: 490c ldr r1, [pc, #48] @ (80043a0 <__NVIC_SetPriority+0x4c>)
|
|
800436e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8004372: 0112 lsls r2, r2, #4
|
|
8004374: b2d2 uxtb r2, r2
|
|
8004376: 440b add r3, r1
|
|
8004378: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
800437c: e00a b.n 8004394 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800437e: 683b ldr r3, [r7, #0]
|
|
8004380: b2da uxtb r2, r3
|
|
8004382: 4908 ldr r1, [pc, #32] @ (80043a4 <__NVIC_SetPriority+0x50>)
|
|
8004384: 79fb ldrb r3, [r7, #7]
|
|
8004386: f003 030f and.w r3, r3, #15
|
|
800438a: 3b04 subs r3, #4
|
|
800438c: 0112 lsls r2, r2, #4
|
|
800438e: b2d2 uxtb r2, r2
|
|
8004390: 440b add r3, r1
|
|
8004392: 761a strb r2, [r3, #24]
|
|
}
|
|
8004394: bf00 nop
|
|
8004396: 370c adds r7, #12
|
|
8004398: 46bd mov sp, r7
|
|
800439a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800439e: 4770 bx lr
|
|
80043a0: e000e100 .word 0xe000e100
|
|
80043a4: e000ed00 .word 0xe000ed00
|
|
|
|
080043a8 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80043a8: b480 push {r7}
|
|
80043aa: b089 sub sp, #36 @ 0x24
|
|
80043ac: af00 add r7, sp, #0
|
|
80043ae: 60f8 str r0, [r7, #12]
|
|
80043b0: 60b9 str r1, [r7, #8]
|
|
80043b2: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80043b4: 68fb ldr r3, [r7, #12]
|
|
80043b6: f003 0307 and.w r3, r3, #7
|
|
80043ba: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
80043bc: 69fb ldr r3, [r7, #28]
|
|
80043be: f1c3 0307 rsb r3, r3, #7
|
|
80043c2: 2b04 cmp r3, #4
|
|
80043c4: bf28 it cs
|
|
80043c6: 2304 movcs r3, #4
|
|
80043c8: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80043ca: 69fb ldr r3, [r7, #28]
|
|
80043cc: 3304 adds r3, #4
|
|
80043ce: 2b06 cmp r3, #6
|
|
80043d0: d902 bls.n 80043d8 <NVIC_EncodePriority+0x30>
|
|
80043d2: 69fb ldr r3, [r7, #28]
|
|
80043d4: 3b03 subs r3, #3
|
|
80043d6: e000 b.n 80043da <NVIC_EncodePriority+0x32>
|
|
80043d8: 2300 movs r3, #0
|
|
80043da: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80043dc: f04f 32ff mov.w r2, #4294967295
|
|
80043e0: 69bb ldr r3, [r7, #24]
|
|
80043e2: fa02 f303 lsl.w r3, r2, r3
|
|
80043e6: 43da mvns r2, r3
|
|
80043e8: 68bb ldr r3, [r7, #8]
|
|
80043ea: 401a ands r2, r3
|
|
80043ec: 697b ldr r3, [r7, #20]
|
|
80043ee: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80043f0: f04f 31ff mov.w r1, #4294967295
|
|
80043f4: 697b ldr r3, [r7, #20]
|
|
80043f6: fa01 f303 lsl.w r3, r1, r3
|
|
80043fa: 43d9 mvns r1, r3
|
|
80043fc: 687b ldr r3, [r7, #4]
|
|
80043fe: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8004400: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8004402: 4618 mov r0, r3
|
|
8004404: 3724 adds r7, #36 @ 0x24
|
|
8004406: 46bd mov sp, r7
|
|
8004408: f85d 7b04 ldr.w r7, [sp], #4
|
|
800440c: 4770 bx lr
|
|
...
|
|
|
|
08004410 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8004410: b580 push {r7, lr}
|
|
8004412: b082 sub sp, #8
|
|
8004414: af00 add r7, sp, #0
|
|
8004416: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8004418: 687b ldr r3, [r7, #4]
|
|
800441a: 3b01 subs r3, #1
|
|
800441c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8004420: d301 bcc.n 8004426 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8004422: 2301 movs r3, #1
|
|
8004424: e00f b.n 8004446 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8004426: 4a0a ldr r2, [pc, #40] @ (8004450 <SysTick_Config+0x40>)
|
|
8004428: 687b ldr r3, [r7, #4]
|
|
800442a: 3b01 subs r3, #1
|
|
800442c: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
800442e: 210f movs r1, #15
|
|
8004430: f04f 30ff mov.w r0, #4294967295
|
|
8004434: f7ff ff8e bl 8004354 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8004438: 4b05 ldr r3, [pc, #20] @ (8004450 <SysTick_Config+0x40>)
|
|
800443a: 2200 movs r2, #0
|
|
800443c: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
800443e: 4b04 ldr r3, [pc, #16] @ (8004450 <SysTick_Config+0x40>)
|
|
8004440: 2207 movs r2, #7
|
|
8004442: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8004444: 2300 movs r3, #0
|
|
}
|
|
8004446: 4618 mov r0, r3
|
|
8004448: 3708 adds r7, #8
|
|
800444a: 46bd mov sp, r7
|
|
800444c: bd80 pop {r7, pc}
|
|
800444e: bf00 nop
|
|
8004450: e000e010 .word 0xe000e010
|
|
|
|
08004454 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8004454: b580 push {r7, lr}
|
|
8004456: b082 sub sp, #8
|
|
8004458: af00 add r7, sp, #0
|
|
800445a: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
800445c: 6878 ldr r0, [r7, #4]
|
|
800445e: f7ff ff29 bl 80042b4 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8004462: bf00 nop
|
|
8004464: 3708 adds r7, #8
|
|
8004466: 46bd mov sp, r7
|
|
8004468: bd80 pop {r7, pc}
|
|
|
|
0800446a <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
800446a: b580 push {r7, lr}
|
|
800446c: b086 sub sp, #24
|
|
800446e: af00 add r7, sp, #0
|
|
8004470: 4603 mov r3, r0
|
|
8004472: 60b9 str r1, [r7, #8]
|
|
8004474: 607a str r2, [r7, #4]
|
|
8004476: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
8004478: 2300 movs r3, #0
|
|
800447a: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
800447c: f7ff ff3e bl 80042fc <__NVIC_GetPriorityGrouping>
|
|
8004480: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8004482: 687a ldr r2, [r7, #4]
|
|
8004484: 68b9 ldr r1, [r7, #8]
|
|
8004486: 6978 ldr r0, [r7, #20]
|
|
8004488: f7ff ff8e bl 80043a8 <NVIC_EncodePriority>
|
|
800448c: 4602 mov r2, r0
|
|
800448e: f997 300f ldrsb.w r3, [r7, #15]
|
|
8004492: 4611 mov r1, r2
|
|
8004494: 4618 mov r0, r3
|
|
8004496: f7ff ff5d bl 8004354 <__NVIC_SetPriority>
|
|
}
|
|
800449a: bf00 nop
|
|
800449c: 3718 adds r7, #24
|
|
800449e: 46bd mov sp, r7
|
|
80044a0: bd80 pop {r7, pc}
|
|
|
|
080044a2 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80044a2: b580 push {r7, lr}
|
|
80044a4: b082 sub sp, #8
|
|
80044a6: af00 add r7, sp, #0
|
|
80044a8: 4603 mov r3, r0
|
|
80044aa: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
80044ac: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80044b0: 4618 mov r0, r3
|
|
80044b2: f7ff ff31 bl 8004318 <__NVIC_EnableIRQ>
|
|
}
|
|
80044b6: bf00 nop
|
|
80044b8: 3708 adds r7, #8
|
|
80044ba: 46bd mov sp, r7
|
|
80044bc: bd80 pop {r7, pc}
|
|
|
|
080044be <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
80044be: b580 push {r7, lr}
|
|
80044c0: b082 sub sp, #8
|
|
80044c2: af00 add r7, sp, #0
|
|
80044c4: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
80044c6: 6878 ldr r0, [r7, #4]
|
|
80044c8: f7ff ffa2 bl 8004410 <SysTick_Config>
|
|
80044cc: 4603 mov r3, r0
|
|
}
|
|
80044ce: 4618 mov r0, r3
|
|
80044d0: 3708 adds r7, #8
|
|
80044d2: 46bd mov sp, r7
|
|
80044d4: bd80 pop {r7, pc}
|
|
|
|
080044d6 <HAL_DMA_Init>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80044d6: b580 push {r7, lr}
|
|
80044d8: b084 sub sp, #16
|
|
80044da: af00 add r7, sp, #0
|
|
80044dc: 6078 str r0, [r7, #4]
|
|
uint32_t tmp = 0U;
|
|
80044de: 2300 movs r3, #0
|
|
80044e0: 60fb str r3, [r7, #12]
|
|
|
|
/* Check the DMA handle allocation */
|
|
if(NULL == hdma)
|
|
80044e2: 687b ldr r3, [r7, #4]
|
|
80044e4: 2b00 cmp r3, #0
|
|
80044e6: d101 bne.n 80044ec <HAL_DMA_Init+0x16>
|
|
{
|
|
return HAL_ERROR;
|
|
80044e8: 2301 movs r3, #1
|
|
80044ea: e037 b.n 800455c <HAL_DMA_Init+0x86>
|
|
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
|
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
|
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
|
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
80044ec: 687b ldr r3, [r7, #4]
|
|
80044ee: 2202 movs r2, #2
|
|
80044f0: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Get the CR register value */
|
|
tmp = hdma->Instance->CCR;
|
|
80044f4: 687b ldr r3, [r7, #4]
|
|
80044f6: 681b ldr r3, [r3, #0]
|
|
80044f8: 681b ldr r3, [r3, #0]
|
|
80044fa: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
|
|
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
|
80044fc: 68fb ldr r3, [r7, #12]
|
|
80044fe: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
|
|
8004502: f023 0330 bic.w r3, r3, #48 @ 0x30
|
|
8004506: 60fb str r3, [r7, #12]
|
|
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
|
|
DMA_CCR_DIR));
|
|
|
|
/* Prepare the DMA Channel configuration */
|
|
tmp |= hdma->Init.Direction |
|
|
8004508: 687b ldr r3, [r7, #4]
|
|
800450a: 685a ldr r2, [r3, #4]
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
800450c: 687b ldr r3, [r7, #4]
|
|
800450e: 689b ldr r3, [r3, #8]
|
|
tmp |= hdma->Init.Direction |
|
|
8004510: 431a orrs r2, r3
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
8004512: 687b ldr r3, [r7, #4]
|
|
8004514: 68db ldr r3, [r3, #12]
|
|
8004516: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8004518: 687b ldr r3, [r7, #4]
|
|
800451a: 691b ldr r3, [r3, #16]
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
800451c: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
800451e: 687b ldr r3, [r7, #4]
|
|
8004520: 695b ldr r3, [r3, #20]
|
|
8004522: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
8004524: 687b ldr r3, [r7, #4]
|
|
8004526: 699b ldr r3, [r3, #24]
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
8004528: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
800452a: 687b ldr r3, [r7, #4]
|
|
800452c: 69db ldr r3, [r3, #28]
|
|
800452e: 4313 orrs r3, r2
|
|
tmp |= hdma->Init.Direction |
|
|
8004530: 68fa ldr r2, [r7, #12]
|
|
8004532: 4313 orrs r3, r2
|
|
8004534: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to DMA Channel CR register */
|
|
hdma->Instance->CCR = tmp;
|
|
8004536: 687b ldr r3, [r7, #4]
|
|
8004538: 681b ldr r3, [r3, #0]
|
|
800453a: 68fa ldr r2, [r7, #12]
|
|
800453c: 601a str r2, [r3, #0]
|
|
|
|
/* Initialize DmaBaseAddress and ChannelIndex parameters used
|
|
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
|
|
DMA_CalcBaseAndBitshift(hdma);
|
|
800453e: 6878 ldr r0, [r7, #4]
|
|
8004540: f000 f940 bl 80047c4 <DMA_CalcBaseAndBitshift>
|
|
|
|
/* Initialise the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8004544: 687b ldr r3, [r7, #4]
|
|
8004546: 2200 movs r2, #0
|
|
8004548: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Initialize the DMA state*/
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800454a: 687b ldr r3, [r7, #4]
|
|
800454c: 2201 movs r2, #1
|
|
800454e: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Allocate lock resource and initialize it */
|
|
hdma->Lock = HAL_UNLOCKED;
|
|
8004552: 687b ldr r3, [r7, #4]
|
|
8004554: 2200 movs r2, #0
|
|
8004556: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_OK;
|
|
800455a: 2300 movs r3, #0
|
|
}
|
|
800455c: 4618 mov r0, r3
|
|
800455e: 3710 adds r7, #16
|
|
8004560: 46bd mov sp, r7
|
|
8004562: bd80 pop {r7, pc}
|
|
|
|
08004564 <HAL_DMA_Start_IT>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
8004564: b580 push {r7, lr}
|
|
8004566: b086 sub sp, #24
|
|
8004568: af00 add r7, sp, #0
|
|
800456a: 60f8 str r0, [r7, #12]
|
|
800456c: 60b9 str r1, [r7, #8]
|
|
800456e: 607a str r2, [r7, #4]
|
|
8004570: 603b str r3, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004572: 2300 movs r3, #0
|
|
8004574: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
8004576: 68fb ldr r3, [r7, #12]
|
|
8004578: f893 3020 ldrb.w r3, [r3, #32]
|
|
800457c: 2b01 cmp r3, #1
|
|
800457e: d101 bne.n 8004584 <HAL_DMA_Start_IT+0x20>
|
|
8004580: 2302 movs r3, #2
|
|
8004582: e04a b.n 800461a <HAL_DMA_Start_IT+0xb6>
|
|
8004584: 68fb ldr r3, [r7, #12]
|
|
8004586: 2201 movs r2, #1
|
|
8004588: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
800458c: 68fb ldr r3, [r7, #12]
|
|
800458e: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
|
|
8004592: 2b01 cmp r3, #1
|
|
8004594: d13a bne.n 800460c <HAL_DMA_Start_IT+0xa8>
|
|
{
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8004596: 68fb ldr r3, [r7, #12]
|
|
8004598: 2202 movs r2, #2
|
|
800459a: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
800459e: 68fb ldr r3, [r7, #12]
|
|
80045a0: 2200 movs r2, #0
|
|
80045a2: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Disable the peripheral */
|
|
hdma->Instance->CCR &= ~DMA_CCR_EN;
|
|
80045a4: 68fb ldr r3, [r7, #12]
|
|
80045a6: 681b ldr r3, [r3, #0]
|
|
80045a8: 681a ldr r2, [r3, #0]
|
|
80045aa: 68fb ldr r3, [r7, #12]
|
|
80045ac: 681b ldr r3, [r3, #0]
|
|
80045ae: f022 0201 bic.w r2, r2, #1
|
|
80045b2: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the source, destination address and the data length */
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
|
80045b4: 683b ldr r3, [r7, #0]
|
|
80045b6: 687a ldr r2, [r7, #4]
|
|
80045b8: 68b9 ldr r1, [r7, #8]
|
|
80045ba: 68f8 ldr r0, [r7, #12]
|
|
80045bc: f000 f8d4 bl 8004768 <DMA_SetConfig>
|
|
|
|
/* Enable the transfer complete, & transfer error interrupts */
|
|
/* Half transfer interrupt is optional: enable it only if associated callback is available */
|
|
if(NULL != hdma->XferHalfCpltCallback )
|
|
80045c0: 68fb ldr r3, [r7, #12]
|
|
80045c2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80045c4: 2b00 cmp r3, #0
|
|
80045c6: d008 beq.n 80045da <HAL_DMA_Start_IT+0x76>
|
|
{
|
|
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
|
80045c8: 68fb ldr r3, [r7, #12]
|
|
80045ca: 681b ldr r3, [r3, #0]
|
|
80045cc: 681a ldr r2, [r3, #0]
|
|
80045ce: 68fb ldr r3, [r7, #12]
|
|
80045d0: 681b ldr r3, [r3, #0]
|
|
80045d2: f042 020e orr.w r2, r2, #14
|
|
80045d6: 601a str r2, [r3, #0]
|
|
80045d8: e00f b.n 80045fa <HAL_DMA_Start_IT+0x96>
|
|
}
|
|
else
|
|
{
|
|
hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
|
|
80045da: 68fb ldr r3, [r7, #12]
|
|
80045dc: 681b ldr r3, [r3, #0]
|
|
80045de: 681a ldr r2, [r3, #0]
|
|
80045e0: 68fb ldr r3, [r7, #12]
|
|
80045e2: 681b ldr r3, [r3, #0]
|
|
80045e4: f042 020a orr.w r2, r2, #10
|
|
80045e8: 601a str r2, [r3, #0]
|
|
hdma->Instance->CCR &= ~DMA_IT_HT;
|
|
80045ea: 68fb ldr r3, [r7, #12]
|
|
80045ec: 681b ldr r3, [r3, #0]
|
|
80045ee: 681a ldr r2, [r3, #0]
|
|
80045f0: 68fb ldr r3, [r7, #12]
|
|
80045f2: 681b ldr r3, [r3, #0]
|
|
80045f4: f022 0204 bic.w r2, r2, #4
|
|
80045f8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Enable the Peripheral */
|
|
hdma->Instance->CCR |= DMA_CCR_EN;
|
|
80045fa: 68fb ldr r3, [r7, #12]
|
|
80045fc: 681b ldr r3, [r3, #0]
|
|
80045fe: 681a ldr r2, [r3, #0]
|
|
8004600: 68fb ldr r3, [r7, #12]
|
|
8004602: 681b ldr r3, [r3, #0]
|
|
8004604: f042 0201 orr.w r2, r2, #1
|
|
8004608: 601a str r2, [r3, #0]
|
|
800460a: e005 b.n 8004618 <HAL_DMA_Start_IT+0xb4>
|
|
}
|
|
else
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
800460c: 68fb ldr r3, [r7, #12]
|
|
800460e: 2200 movs r2, #0
|
|
8004610: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
/* Remain BUSY */
|
|
status = HAL_BUSY;
|
|
8004614: 2302 movs r3, #2
|
|
8004616: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return status;
|
|
8004618: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800461a: 4618 mov r0, r3
|
|
800461c: 3718 adds r7, #24
|
|
800461e: 46bd mov sp, r7
|
|
8004620: bd80 pop {r7, pc}
|
|
|
|
08004622 <HAL_DMA_IRQHandler>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8004622: b580 push {r7, lr}
|
|
8004624: b084 sub sp, #16
|
|
8004626: af00 add r7, sp, #0
|
|
8004628: 6078 str r0, [r7, #4]
|
|
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
|
800462a: 687b ldr r3, [r7, #4]
|
|
800462c: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800462e: 681b ldr r3, [r3, #0]
|
|
8004630: 60fb str r3, [r7, #12]
|
|
uint32_t source_it = hdma->Instance->CCR;
|
|
8004632: 687b ldr r3, [r7, #4]
|
|
8004634: 681b ldr r3, [r3, #0]
|
|
8004636: 681b ldr r3, [r3, #0]
|
|
8004638: 60bb str r3, [r7, #8]
|
|
|
|
/* Half Transfer Complete Interrupt management ******************************/
|
|
if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
|
|
800463a: 687b ldr r3, [r7, #4]
|
|
800463c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800463e: 2204 movs r2, #4
|
|
8004640: 409a lsls r2, r3
|
|
8004642: 68fb ldr r3, [r7, #12]
|
|
8004644: 4013 ands r3, r2
|
|
8004646: 2b00 cmp r3, #0
|
|
8004648: d024 beq.n 8004694 <HAL_DMA_IRQHandler+0x72>
|
|
800464a: 68bb ldr r3, [r7, #8]
|
|
800464c: f003 0304 and.w r3, r3, #4
|
|
8004650: 2b00 cmp r3, #0
|
|
8004652: d01f beq.n 8004694 <HAL_DMA_IRQHandler+0x72>
|
|
{
|
|
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
|
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
8004654: 687b ldr r3, [r7, #4]
|
|
8004656: 681b ldr r3, [r3, #0]
|
|
8004658: 681b ldr r3, [r3, #0]
|
|
800465a: f003 0320 and.w r3, r3, #32
|
|
800465e: 2b00 cmp r3, #0
|
|
8004660: d107 bne.n 8004672 <HAL_DMA_IRQHandler+0x50>
|
|
{
|
|
/* Disable the half transfer interrupt */
|
|
hdma->Instance->CCR &= ~DMA_IT_HT;
|
|
8004662: 687b ldr r3, [r7, #4]
|
|
8004664: 681b ldr r3, [r3, #0]
|
|
8004666: 681a ldr r2, [r3, #0]
|
|
8004668: 687b ldr r3, [r7, #4]
|
|
800466a: 681b ldr r3, [r3, #0]
|
|
800466c: f022 0204 bic.w r2, r2, #4
|
|
8004670: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Clear the half transfer complete flag */
|
|
hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
|
|
8004672: 687b ldr r3, [r7, #4]
|
|
8004674: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8004676: 687b ldr r3, [r7, #4]
|
|
8004678: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800467a: 2104 movs r1, #4
|
|
800467c: fa01 f202 lsl.w r2, r1, r2
|
|
8004680: 605a str r2, [r3, #4]
|
|
|
|
/* DMA peripheral state is not updated in Half Transfer */
|
|
/* State is updated only in Transfer Complete case */
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
8004682: 687b ldr r3, [r7, #4]
|
|
8004684: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004686: 2b00 cmp r3, #0
|
|
8004688: d06a beq.n 8004760 <HAL_DMA_IRQHandler+0x13e>
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
800468a: 687b ldr r3, [r7, #4]
|
|
800468c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800468e: 6878 ldr r0, [r7, #4]
|
|
8004690: 4798 blx r3
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
8004692: e065 b.n 8004760 <HAL_DMA_IRQHandler+0x13e>
|
|
}
|
|
}
|
|
|
|
/* Transfer Complete Interrupt management ***********************************/
|
|
else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
|
|
8004694: 687b ldr r3, [r7, #4]
|
|
8004696: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004698: 2202 movs r2, #2
|
|
800469a: 409a lsls r2, r3
|
|
800469c: 68fb ldr r3, [r7, #12]
|
|
800469e: 4013 ands r3, r2
|
|
80046a0: 2b00 cmp r3, #0
|
|
80046a2: d02c beq.n 80046fe <HAL_DMA_IRQHandler+0xdc>
|
|
80046a4: 68bb ldr r3, [r7, #8]
|
|
80046a6: f003 0302 and.w r3, r3, #2
|
|
80046aa: 2b00 cmp r3, #0
|
|
80046ac: d027 beq.n 80046fe <HAL_DMA_IRQHandler+0xdc>
|
|
{
|
|
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
80046ae: 687b ldr r3, [r7, #4]
|
|
80046b0: 681b ldr r3, [r3, #0]
|
|
80046b2: 681b ldr r3, [r3, #0]
|
|
80046b4: f003 0320 and.w r3, r3, #32
|
|
80046b8: 2b00 cmp r3, #0
|
|
80046ba: d10b bne.n 80046d4 <HAL_DMA_IRQHandler+0xb2>
|
|
{
|
|
/* Disable the transfer complete & transfer error interrupts */
|
|
/* if the DMA mode is not CIRCULAR */
|
|
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
|
|
80046bc: 687b ldr r3, [r7, #4]
|
|
80046be: 681b ldr r3, [r3, #0]
|
|
80046c0: 681a ldr r2, [r3, #0]
|
|
80046c2: 687b ldr r3, [r7, #4]
|
|
80046c4: 681b ldr r3, [r3, #0]
|
|
80046c6: f022 020a bic.w r2, r2, #10
|
|
80046ca: 601a str r2, [r3, #0]
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80046cc: 687b ldr r3, [r7, #4]
|
|
80046ce: 2201 movs r2, #1
|
|
80046d0: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
}
|
|
|
|
/* Clear the transfer complete flag */
|
|
hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
|
|
80046d4: 687b ldr r3, [r7, #4]
|
|
80046d6: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
80046d8: 687b ldr r3, [r7, #4]
|
|
80046da: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80046dc: 2102 movs r1, #2
|
|
80046de: fa01 f202 lsl.w r2, r1, r2
|
|
80046e2: 605a str r2, [r3, #4]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80046e4: 687b ldr r3, [r7, #4]
|
|
80046e6: 2200 movs r2, #0
|
|
80046e8: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
if(hdma->XferCpltCallback != NULL)
|
|
80046ec: 687b ldr r3, [r7, #4]
|
|
80046ee: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80046f0: 2b00 cmp r3, #0
|
|
80046f2: d035 beq.n 8004760 <HAL_DMA_IRQHandler+0x13e>
|
|
{
|
|
/* Transfer complete callback */
|
|
hdma->XferCpltCallback(hdma);
|
|
80046f4: 687b ldr r3, [r7, #4]
|
|
80046f6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80046f8: 6878 ldr r0, [r7, #4]
|
|
80046fa: 4798 blx r3
|
|
if(hdma->XferCpltCallback != NULL)
|
|
80046fc: e030 b.n 8004760 <HAL_DMA_IRQHandler+0x13e>
|
|
}
|
|
}
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
|
|
80046fe: 687b ldr r3, [r7, #4]
|
|
8004700: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004702: 2208 movs r2, #8
|
|
8004704: 409a lsls r2, r3
|
|
8004706: 68fb ldr r3, [r7, #12]
|
|
8004708: 4013 ands r3, r2
|
|
800470a: 2b00 cmp r3, #0
|
|
800470c: d028 beq.n 8004760 <HAL_DMA_IRQHandler+0x13e>
|
|
800470e: 68bb ldr r3, [r7, #8]
|
|
8004710: f003 0308 and.w r3, r3, #8
|
|
8004714: 2b00 cmp r3, #0
|
|
8004716: d023 beq.n 8004760 <HAL_DMA_IRQHandler+0x13e>
|
|
{
|
|
/* When a DMA transfer error occurs */
|
|
/* A hardware clear of its EN bits is performed */
|
|
/* Then, disable all DMA interrupts */
|
|
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
|
|
8004718: 687b ldr r3, [r7, #4]
|
|
800471a: 681b ldr r3, [r3, #0]
|
|
800471c: 681a ldr r2, [r3, #0]
|
|
800471e: 687b ldr r3, [r7, #4]
|
|
8004720: 681b ldr r3, [r3, #0]
|
|
8004722: f022 020e bic.w r2, r2, #14
|
|
8004726: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
|
|
8004728: 687b ldr r3, [r7, #4]
|
|
800472a: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
800472c: 687b ldr r3, [r7, #4]
|
|
800472e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004730: 2101 movs r1, #1
|
|
8004732: fa01 f202 lsl.w r2, r1, r2
|
|
8004736: 605a str r2, [r3, #4]
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
|
8004738: 687b ldr r3, [r7, #4]
|
|
800473a: 2201 movs r2, #1
|
|
800473c: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800473e: 687b ldr r3, [r7, #4]
|
|
8004740: 2201 movs r2, #1
|
|
8004742: f883 2021 strb.w r2, [r3, #33] @ 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8004746: 687b ldr r3, [r7, #4]
|
|
8004748: 2200 movs r2, #0
|
|
800474a: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
if(hdma->XferErrorCallback != NULL)
|
|
800474e: 687b ldr r3, [r7, #4]
|
|
8004750: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004752: 2b00 cmp r3, #0
|
|
8004754: d004 beq.n 8004760 <HAL_DMA_IRQHandler+0x13e>
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
8004756: 687b ldr r3, [r7, #4]
|
|
8004758: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800475a: 6878 ldr r0, [r7, #4]
|
|
800475c: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
800475e: e7ff b.n 8004760 <HAL_DMA_IRQHandler+0x13e>
|
|
8004760: bf00 nop
|
|
8004762: 3710 adds r7, #16
|
|
8004764: 46bd mov sp, r7
|
|
8004766: bd80 pop {r7, pc}
|
|
|
|
08004768 <DMA_SetConfig>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
8004768: b480 push {r7}
|
|
800476a: b085 sub sp, #20
|
|
800476c: af00 add r7, sp, #0
|
|
800476e: 60f8 str r0, [r7, #12]
|
|
8004770: 60b9 str r1, [r7, #8]
|
|
8004772: 607a str r2, [r7, #4]
|
|
8004774: 603b str r3, [r7, #0]
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
|
|
8004776: 68fb ldr r3, [r7, #12]
|
|
8004778: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
800477a: 68fb ldr r3, [r7, #12]
|
|
800477c: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800477e: 2101 movs r1, #1
|
|
8004780: fa01 f202 lsl.w r2, r1, r2
|
|
8004784: 605a str r2, [r3, #4]
|
|
|
|
/* Configure DMA Channel data length */
|
|
hdma->Instance->CNDTR = DataLength;
|
|
8004786: 68fb ldr r3, [r7, #12]
|
|
8004788: 681b ldr r3, [r3, #0]
|
|
800478a: 683a ldr r2, [r7, #0]
|
|
800478c: 605a str r2, [r3, #4]
|
|
|
|
/* Peripheral to Memory */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
800478e: 68fb ldr r3, [r7, #12]
|
|
8004790: 685b ldr r3, [r3, #4]
|
|
8004792: 2b10 cmp r3, #16
|
|
8004794: d108 bne.n 80047a8 <DMA_SetConfig+0x40>
|
|
{
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CPAR = DstAddress;
|
|
8004796: 68fb ldr r3, [r7, #12]
|
|
8004798: 681b ldr r3, [r3, #0]
|
|
800479a: 687a ldr r2, [r7, #4]
|
|
800479c: 609a str r2, [r3, #8]
|
|
|
|
/* Configure DMA Channel source address */
|
|
hdma->Instance->CMAR = SrcAddress;
|
|
800479e: 68fb ldr r3, [r7, #12]
|
|
80047a0: 681b ldr r3, [r3, #0]
|
|
80047a2: 68ba ldr r2, [r7, #8]
|
|
80047a4: 60da str r2, [r3, #12]
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CMAR = DstAddress;
|
|
}
|
|
}
|
|
80047a6: e007 b.n 80047b8 <DMA_SetConfig+0x50>
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
80047a8: 68fb ldr r3, [r7, #12]
|
|
80047aa: 681b ldr r3, [r3, #0]
|
|
80047ac: 68ba ldr r2, [r7, #8]
|
|
80047ae: 609a str r2, [r3, #8]
|
|
hdma->Instance->CMAR = DstAddress;
|
|
80047b0: 68fb ldr r3, [r7, #12]
|
|
80047b2: 681b ldr r3, [r3, #0]
|
|
80047b4: 687a ldr r2, [r7, #4]
|
|
80047b6: 60da str r2, [r3, #12]
|
|
}
|
|
80047b8: bf00 nop
|
|
80047ba: 3714 adds r7, #20
|
|
80047bc: 46bd mov sp, r7
|
|
80047be: f85d 7b04 ldr.w r7, [sp], #4
|
|
80047c2: 4770 bx lr
|
|
|
|
080047c4 <DMA_CalcBaseAndBitshift>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval None
|
|
*/
|
|
static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80047c4: b480 push {r7}
|
|
80047c6: b083 sub sp, #12
|
|
80047c8: af00 add r7, sp, #0
|
|
80047ca: 6078 str r0, [r7, #4]
|
|
#if defined (DMA2)
|
|
/* calculation of the channel index */
|
|
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
|
80047cc: 687b ldr r3, [r7, #4]
|
|
80047ce: 681b ldr r3, [r3, #0]
|
|
80047d0: 461a mov r2, r3
|
|
80047d2: 4b14 ldr r3, [pc, #80] @ (8004824 <DMA_CalcBaseAndBitshift+0x60>)
|
|
80047d4: 429a cmp r2, r3
|
|
80047d6: d80f bhi.n 80047f8 <DMA_CalcBaseAndBitshift+0x34>
|
|
{
|
|
/* DMA1 */
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
|
80047d8: 687b ldr r3, [r7, #4]
|
|
80047da: 681b ldr r3, [r3, #0]
|
|
80047dc: 461a mov r2, r3
|
|
80047de: 4b12 ldr r3, [pc, #72] @ (8004828 <DMA_CalcBaseAndBitshift+0x64>)
|
|
80047e0: 4413 add r3, r2
|
|
80047e2: 4a12 ldr r2, [pc, #72] @ (800482c <DMA_CalcBaseAndBitshift+0x68>)
|
|
80047e4: fba2 2303 umull r2, r3, r2, r3
|
|
80047e8: 091b lsrs r3, r3, #4
|
|
80047ea: 009a lsls r2, r3, #2
|
|
80047ec: 687b ldr r3, [r7, #4]
|
|
80047ee: 641a str r2, [r3, #64] @ 0x40
|
|
hdma->DmaBaseAddress = DMA1;
|
|
80047f0: 687b ldr r3, [r7, #4]
|
|
80047f2: 4a0f ldr r2, [pc, #60] @ (8004830 <DMA_CalcBaseAndBitshift+0x6c>)
|
|
80047f4: 63da str r2, [r3, #60] @ 0x3c
|
|
/* calculation of the channel index */
|
|
/* DMA1 */
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
|
hdma->DmaBaseAddress = DMA1;
|
|
#endif
|
|
}
|
|
80047f6: e00e b.n 8004816 <DMA_CalcBaseAndBitshift+0x52>
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
|
80047f8: 687b ldr r3, [r7, #4]
|
|
80047fa: 681b ldr r3, [r3, #0]
|
|
80047fc: 461a mov r2, r3
|
|
80047fe: 4b0d ldr r3, [pc, #52] @ (8004834 <DMA_CalcBaseAndBitshift+0x70>)
|
|
8004800: 4413 add r3, r2
|
|
8004802: 4a0a ldr r2, [pc, #40] @ (800482c <DMA_CalcBaseAndBitshift+0x68>)
|
|
8004804: fba2 2303 umull r2, r3, r2, r3
|
|
8004808: 091b lsrs r3, r3, #4
|
|
800480a: 009a lsls r2, r3, #2
|
|
800480c: 687b ldr r3, [r7, #4]
|
|
800480e: 641a str r2, [r3, #64] @ 0x40
|
|
hdma->DmaBaseAddress = DMA2;
|
|
8004810: 687b ldr r3, [r7, #4]
|
|
8004812: 4a09 ldr r2, [pc, #36] @ (8004838 <DMA_CalcBaseAndBitshift+0x74>)
|
|
8004814: 63da str r2, [r3, #60] @ 0x3c
|
|
}
|
|
8004816: bf00 nop
|
|
8004818: 370c adds r7, #12
|
|
800481a: 46bd mov sp, r7
|
|
800481c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004820: 4770 bx lr
|
|
8004822: bf00 nop
|
|
8004824: 40020407 .word 0x40020407
|
|
8004828: bffdfff8 .word 0xbffdfff8
|
|
800482c: cccccccd .word 0xcccccccd
|
|
8004830: 40020000 .word 0x40020000
|
|
8004834: bffdfbf8 .word 0xbffdfbf8
|
|
8004838: 40020400 .word 0x40020400
|
|
|
|
0800483c <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
800483c: b480 push {r7}
|
|
800483e: b087 sub sp, #28
|
|
8004840: af00 add r7, sp, #0
|
|
8004842: 6078 str r0, [r7, #4]
|
|
8004844: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8004846: 2300 movs r3, #0
|
|
8004848: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
800484a: e154 b.n 8004af6 <HAL_GPIO_Init+0x2ba>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
800484c: 683b ldr r3, [r7, #0]
|
|
800484e: 681a ldr r2, [r3, #0]
|
|
8004850: 2101 movs r1, #1
|
|
8004852: 697b ldr r3, [r7, #20]
|
|
8004854: fa01 f303 lsl.w r3, r1, r3
|
|
8004858: 4013 ands r3, r2
|
|
800485a: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
800485c: 68fb ldr r3, [r7, #12]
|
|
800485e: 2b00 cmp r3, #0
|
|
8004860: f000 8146 beq.w 8004af0 <HAL_GPIO_Init+0x2b4>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
8004864: 683b ldr r3, [r7, #0]
|
|
8004866: 685b ldr r3, [r3, #4]
|
|
8004868: f003 0303 and.w r3, r3, #3
|
|
800486c: 2b01 cmp r3, #1
|
|
800486e: d005 beq.n 800487c <HAL_GPIO_Init+0x40>
|
|
8004870: 683b ldr r3, [r7, #0]
|
|
8004872: 685b ldr r3, [r3, #4]
|
|
8004874: f003 0303 and.w r3, r3, #3
|
|
8004878: 2b02 cmp r3, #2
|
|
800487a: d130 bne.n 80048de <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
800487c: 687b ldr r3, [r7, #4]
|
|
800487e: 689b ldr r3, [r3, #8]
|
|
8004880: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
|
8004882: 697b ldr r3, [r7, #20]
|
|
8004884: 005b lsls r3, r3, #1
|
|
8004886: 2203 movs r2, #3
|
|
8004888: fa02 f303 lsl.w r3, r2, r3
|
|
800488c: 43db mvns r3, r3
|
|
800488e: 693a ldr r2, [r7, #16]
|
|
8004890: 4013 ands r3, r2
|
|
8004892: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
8004894: 683b ldr r3, [r7, #0]
|
|
8004896: 68da ldr r2, [r3, #12]
|
|
8004898: 697b ldr r3, [r7, #20]
|
|
800489a: 005b lsls r3, r3, #1
|
|
800489c: fa02 f303 lsl.w r3, r2, r3
|
|
80048a0: 693a ldr r2, [r7, #16]
|
|
80048a2: 4313 orrs r3, r2
|
|
80048a4: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
80048a6: 687b ldr r3, [r7, #4]
|
|
80048a8: 693a ldr r2, [r7, #16]
|
|
80048aa: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
80048ac: 687b ldr r3, [r7, #4]
|
|
80048ae: 685b ldr r3, [r3, #4]
|
|
80048b0: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
80048b2: 2201 movs r2, #1
|
|
80048b4: 697b ldr r3, [r7, #20]
|
|
80048b6: fa02 f303 lsl.w r3, r2, r3
|
|
80048ba: 43db mvns r3, r3
|
|
80048bc: 693a ldr r2, [r7, #16]
|
|
80048be: 4013 ands r3, r2
|
|
80048c0: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
80048c2: 683b ldr r3, [r7, #0]
|
|
80048c4: 685b ldr r3, [r3, #4]
|
|
80048c6: 091b lsrs r3, r3, #4
|
|
80048c8: f003 0201 and.w r2, r3, #1
|
|
80048cc: 697b ldr r3, [r7, #20]
|
|
80048ce: fa02 f303 lsl.w r3, r2, r3
|
|
80048d2: 693a ldr r2, [r7, #16]
|
|
80048d4: 4313 orrs r3, r2
|
|
80048d6: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
80048d8: 687b ldr r3, [r7, #4]
|
|
80048da: 693a ldr r2, [r7, #16]
|
|
80048dc: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
80048de: 683b ldr r3, [r7, #0]
|
|
80048e0: 685b ldr r3, [r3, #4]
|
|
80048e2: f003 0303 and.w r3, r3, #3
|
|
80048e6: 2b03 cmp r3, #3
|
|
80048e8: d017 beq.n 800491a <HAL_GPIO_Init+0xde>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
80048ea: 687b ldr r3, [r7, #4]
|
|
80048ec: 68db ldr r3, [r3, #12]
|
|
80048ee: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
|
|
80048f0: 697b ldr r3, [r7, #20]
|
|
80048f2: 005b lsls r3, r3, #1
|
|
80048f4: 2203 movs r2, #3
|
|
80048f6: fa02 f303 lsl.w r3, r2, r3
|
|
80048fa: 43db mvns r3, r3
|
|
80048fc: 693a ldr r2, [r7, #16]
|
|
80048fe: 4013 ands r3, r2
|
|
8004900: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
|
8004902: 683b ldr r3, [r7, #0]
|
|
8004904: 689a ldr r2, [r3, #8]
|
|
8004906: 697b ldr r3, [r7, #20]
|
|
8004908: 005b lsls r3, r3, #1
|
|
800490a: fa02 f303 lsl.w r3, r2, r3
|
|
800490e: 693a ldr r2, [r7, #16]
|
|
8004910: 4313 orrs r3, r2
|
|
8004912: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8004914: 687b ldr r3, [r7, #4]
|
|
8004916: 693a ldr r2, [r7, #16]
|
|
8004918: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
800491a: 683b ldr r3, [r7, #0]
|
|
800491c: 685b ldr r3, [r3, #4]
|
|
800491e: f003 0303 and.w r3, r3, #3
|
|
8004922: 2b02 cmp r3, #2
|
|
8004924: d123 bne.n 800496e <HAL_GPIO_Init+0x132>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
8004926: 697b ldr r3, [r7, #20]
|
|
8004928: 08da lsrs r2, r3, #3
|
|
800492a: 687b ldr r3, [r7, #4]
|
|
800492c: 3208 adds r2, #8
|
|
800492e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8004932: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8004934: 697b ldr r3, [r7, #20]
|
|
8004936: f003 0307 and.w r3, r3, #7
|
|
800493a: 009b lsls r3, r3, #2
|
|
800493c: 220f movs r2, #15
|
|
800493e: fa02 f303 lsl.w r3, r2, r3
|
|
8004942: 43db mvns r3, r3
|
|
8004944: 693a ldr r2, [r7, #16]
|
|
8004946: 4013 ands r3, r2
|
|
8004948: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
800494a: 683b ldr r3, [r7, #0]
|
|
800494c: 691a ldr r2, [r3, #16]
|
|
800494e: 697b ldr r3, [r7, #20]
|
|
8004950: f003 0307 and.w r3, r3, #7
|
|
8004954: 009b lsls r3, r3, #2
|
|
8004956: fa02 f303 lsl.w r3, r2, r3
|
|
800495a: 693a ldr r2, [r7, #16]
|
|
800495c: 4313 orrs r3, r2
|
|
800495e: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
8004960: 697b ldr r3, [r7, #20]
|
|
8004962: 08da lsrs r2, r3, #3
|
|
8004964: 687b ldr r3, [r7, #4]
|
|
8004966: 3208 adds r2, #8
|
|
8004968: 6939 ldr r1, [r7, #16]
|
|
800496a: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
800496e: 687b ldr r3, [r7, #4]
|
|
8004970: 681b ldr r3, [r3, #0]
|
|
8004972: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
|
8004974: 697b ldr r3, [r7, #20]
|
|
8004976: 005b lsls r3, r3, #1
|
|
8004978: 2203 movs r2, #3
|
|
800497a: fa02 f303 lsl.w r3, r2, r3
|
|
800497e: 43db mvns r3, r3
|
|
8004980: 693a ldr r2, [r7, #16]
|
|
8004982: 4013 ands r3, r2
|
|
8004984: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
8004986: 683b ldr r3, [r7, #0]
|
|
8004988: 685b ldr r3, [r3, #4]
|
|
800498a: f003 0203 and.w r2, r3, #3
|
|
800498e: 697b ldr r3, [r7, #20]
|
|
8004990: 005b lsls r3, r3, #1
|
|
8004992: fa02 f303 lsl.w r3, r2, r3
|
|
8004996: 693a ldr r2, [r7, #16]
|
|
8004998: 4313 orrs r3, r2
|
|
800499a: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
800499c: 687b ldr r3, [r7, #4]
|
|
800499e: 693a ldr r2, [r7, #16]
|
|
80049a0: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
80049a2: 683b ldr r3, [r7, #0]
|
|
80049a4: 685b ldr r3, [r3, #4]
|
|
80049a6: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
80049aa: 2b00 cmp r3, #0
|
|
80049ac: f000 80a0 beq.w 8004af0 <HAL_GPIO_Init+0x2b4>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80049b0: 4b58 ldr r3, [pc, #352] @ (8004b14 <HAL_GPIO_Init+0x2d8>)
|
|
80049b2: 699b ldr r3, [r3, #24]
|
|
80049b4: 4a57 ldr r2, [pc, #348] @ (8004b14 <HAL_GPIO_Init+0x2d8>)
|
|
80049b6: f043 0301 orr.w r3, r3, #1
|
|
80049ba: 6193 str r3, [r2, #24]
|
|
80049bc: 4b55 ldr r3, [pc, #340] @ (8004b14 <HAL_GPIO_Init+0x2d8>)
|
|
80049be: 699b ldr r3, [r3, #24]
|
|
80049c0: f003 0301 and.w r3, r3, #1
|
|
80049c4: 60bb str r3, [r7, #8]
|
|
80049c6: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
80049c8: 4a53 ldr r2, [pc, #332] @ (8004b18 <HAL_GPIO_Init+0x2dc>)
|
|
80049ca: 697b ldr r3, [r7, #20]
|
|
80049cc: 089b lsrs r3, r3, #2
|
|
80049ce: 3302 adds r3, #2
|
|
80049d0: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80049d4: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
80049d6: 697b ldr r3, [r7, #20]
|
|
80049d8: f003 0303 and.w r3, r3, #3
|
|
80049dc: 009b lsls r3, r3, #2
|
|
80049de: 220f movs r2, #15
|
|
80049e0: fa02 f303 lsl.w r3, r2, r3
|
|
80049e4: 43db mvns r3, r3
|
|
80049e6: 693a ldr r2, [r7, #16]
|
|
80049e8: 4013 ands r3, r2
|
|
80049ea: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
80049ec: 687b ldr r3, [r7, #4]
|
|
80049ee: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
80049f2: d019 beq.n 8004a28 <HAL_GPIO_Init+0x1ec>
|
|
80049f4: 687b ldr r3, [r7, #4]
|
|
80049f6: 4a49 ldr r2, [pc, #292] @ (8004b1c <HAL_GPIO_Init+0x2e0>)
|
|
80049f8: 4293 cmp r3, r2
|
|
80049fa: d013 beq.n 8004a24 <HAL_GPIO_Init+0x1e8>
|
|
80049fc: 687b ldr r3, [r7, #4]
|
|
80049fe: 4a48 ldr r2, [pc, #288] @ (8004b20 <HAL_GPIO_Init+0x2e4>)
|
|
8004a00: 4293 cmp r3, r2
|
|
8004a02: d00d beq.n 8004a20 <HAL_GPIO_Init+0x1e4>
|
|
8004a04: 687b ldr r3, [r7, #4]
|
|
8004a06: 4a47 ldr r2, [pc, #284] @ (8004b24 <HAL_GPIO_Init+0x2e8>)
|
|
8004a08: 4293 cmp r3, r2
|
|
8004a0a: d007 beq.n 8004a1c <HAL_GPIO_Init+0x1e0>
|
|
8004a0c: 687b ldr r3, [r7, #4]
|
|
8004a0e: 4a46 ldr r2, [pc, #280] @ (8004b28 <HAL_GPIO_Init+0x2ec>)
|
|
8004a10: 4293 cmp r3, r2
|
|
8004a12: d101 bne.n 8004a18 <HAL_GPIO_Init+0x1dc>
|
|
8004a14: 2304 movs r3, #4
|
|
8004a16: e008 b.n 8004a2a <HAL_GPIO_Init+0x1ee>
|
|
8004a18: 2305 movs r3, #5
|
|
8004a1a: e006 b.n 8004a2a <HAL_GPIO_Init+0x1ee>
|
|
8004a1c: 2303 movs r3, #3
|
|
8004a1e: e004 b.n 8004a2a <HAL_GPIO_Init+0x1ee>
|
|
8004a20: 2302 movs r3, #2
|
|
8004a22: e002 b.n 8004a2a <HAL_GPIO_Init+0x1ee>
|
|
8004a24: 2301 movs r3, #1
|
|
8004a26: e000 b.n 8004a2a <HAL_GPIO_Init+0x1ee>
|
|
8004a28: 2300 movs r3, #0
|
|
8004a2a: 697a ldr r2, [r7, #20]
|
|
8004a2c: f002 0203 and.w r2, r2, #3
|
|
8004a30: 0092 lsls r2, r2, #2
|
|
8004a32: 4093 lsls r3, r2
|
|
8004a34: 693a ldr r2, [r7, #16]
|
|
8004a36: 4313 orrs r3, r2
|
|
8004a38: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
8004a3a: 4937 ldr r1, [pc, #220] @ (8004b18 <HAL_GPIO_Init+0x2dc>)
|
|
8004a3c: 697b ldr r3, [r7, #20]
|
|
8004a3e: 089b lsrs r3, r3, #2
|
|
8004a40: 3302 adds r3, #2
|
|
8004a42: 693a ldr r2, [r7, #16]
|
|
8004a44: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8004a48: 4b38 ldr r3, [pc, #224] @ (8004b2c <HAL_GPIO_Init+0x2f0>)
|
|
8004a4a: 689b ldr r3, [r3, #8]
|
|
8004a4c: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8004a4e: 68fb ldr r3, [r7, #12]
|
|
8004a50: 43db mvns r3, r3
|
|
8004a52: 693a ldr r2, [r7, #16]
|
|
8004a54: 4013 ands r3, r2
|
|
8004a56: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
8004a58: 683b ldr r3, [r7, #0]
|
|
8004a5a: 685b ldr r3, [r3, #4]
|
|
8004a5c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8004a60: 2b00 cmp r3, #0
|
|
8004a62: d003 beq.n 8004a6c <HAL_GPIO_Init+0x230>
|
|
{
|
|
temp |= iocurrent;
|
|
8004a64: 693a ldr r2, [r7, #16]
|
|
8004a66: 68fb ldr r3, [r7, #12]
|
|
8004a68: 4313 orrs r3, r2
|
|
8004a6a: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8004a6c: 4a2f ldr r2, [pc, #188] @ (8004b2c <HAL_GPIO_Init+0x2f0>)
|
|
8004a6e: 693b ldr r3, [r7, #16]
|
|
8004a70: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8004a72: 4b2e ldr r3, [pc, #184] @ (8004b2c <HAL_GPIO_Init+0x2f0>)
|
|
8004a74: 68db ldr r3, [r3, #12]
|
|
8004a76: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8004a78: 68fb ldr r3, [r7, #12]
|
|
8004a7a: 43db mvns r3, r3
|
|
8004a7c: 693a ldr r2, [r7, #16]
|
|
8004a7e: 4013 ands r3, r2
|
|
8004a80: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
8004a82: 683b ldr r3, [r7, #0]
|
|
8004a84: 685b ldr r3, [r3, #4]
|
|
8004a86: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8004a8a: 2b00 cmp r3, #0
|
|
8004a8c: d003 beq.n 8004a96 <HAL_GPIO_Init+0x25a>
|
|
{
|
|
temp |= iocurrent;
|
|
8004a8e: 693a ldr r2, [r7, #16]
|
|
8004a90: 68fb ldr r3, [r7, #12]
|
|
8004a92: 4313 orrs r3, r2
|
|
8004a94: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8004a96: 4a25 ldr r2, [pc, #148] @ (8004b2c <HAL_GPIO_Init+0x2f0>)
|
|
8004a98: 693b ldr r3, [r7, #16]
|
|
8004a9a: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8004a9c: 4b23 ldr r3, [pc, #140] @ (8004b2c <HAL_GPIO_Init+0x2f0>)
|
|
8004a9e: 685b ldr r3, [r3, #4]
|
|
8004aa0: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8004aa2: 68fb ldr r3, [r7, #12]
|
|
8004aa4: 43db mvns r3, r3
|
|
8004aa6: 693a ldr r2, [r7, #16]
|
|
8004aa8: 4013 ands r3, r2
|
|
8004aaa: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
8004aac: 683b ldr r3, [r7, #0]
|
|
8004aae: 685b ldr r3, [r3, #4]
|
|
8004ab0: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004ab4: 2b00 cmp r3, #0
|
|
8004ab6: d003 beq.n 8004ac0 <HAL_GPIO_Init+0x284>
|
|
{
|
|
temp |= iocurrent;
|
|
8004ab8: 693a ldr r2, [r7, #16]
|
|
8004aba: 68fb ldr r3, [r7, #12]
|
|
8004abc: 4313 orrs r3, r2
|
|
8004abe: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8004ac0: 4a1a ldr r2, [pc, #104] @ (8004b2c <HAL_GPIO_Init+0x2f0>)
|
|
8004ac2: 693b ldr r3, [r7, #16]
|
|
8004ac4: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8004ac6: 4b19 ldr r3, [pc, #100] @ (8004b2c <HAL_GPIO_Init+0x2f0>)
|
|
8004ac8: 681b ldr r3, [r3, #0]
|
|
8004aca: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8004acc: 68fb ldr r3, [r7, #12]
|
|
8004ace: 43db mvns r3, r3
|
|
8004ad0: 693a ldr r2, [r7, #16]
|
|
8004ad2: 4013 ands r3, r2
|
|
8004ad4: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
8004ad6: 683b ldr r3, [r7, #0]
|
|
8004ad8: 685b ldr r3, [r3, #4]
|
|
8004ada: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8004ade: 2b00 cmp r3, #0
|
|
8004ae0: d003 beq.n 8004aea <HAL_GPIO_Init+0x2ae>
|
|
{
|
|
temp |= iocurrent;
|
|
8004ae2: 693a ldr r2, [r7, #16]
|
|
8004ae4: 68fb ldr r3, [r7, #12]
|
|
8004ae6: 4313 orrs r3, r2
|
|
8004ae8: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8004aea: 4a10 ldr r2, [pc, #64] @ (8004b2c <HAL_GPIO_Init+0x2f0>)
|
|
8004aec: 693b ldr r3, [r7, #16]
|
|
8004aee: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8004af0: 697b ldr r3, [r7, #20]
|
|
8004af2: 3301 adds r3, #1
|
|
8004af4: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8004af6: 683b ldr r3, [r7, #0]
|
|
8004af8: 681a ldr r2, [r3, #0]
|
|
8004afa: 697b ldr r3, [r7, #20]
|
|
8004afc: fa22 f303 lsr.w r3, r2, r3
|
|
8004b00: 2b00 cmp r3, #0
|
|
8004b02: f47f aea3 bne.w 800484c <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8004b06: bf00 nop
|
|
8004b08: bf00 nop
|
|
8004b0a: 371c adds r7, #28
|
|
8004b0c: 46bd mov sp, r7
|
|
8004b0e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b12: 4770 bx lr
|
|
8004b14: 40021000 .word 0x40021000
|
|
8004b18: 40010000 .word 0x40010000
|
|
8004b1c: 48000400 .word 0x48000400
|
|
8004b20: 48000800 .word 0x48000800
|
|
8004b24: 48000c00 .word 0x48000c00
|
|
8004b28: 48001000 .word 0x48001000
|
|
8004b2c: 40010400 .word 0x40010400
|
|
|
|
08004b30 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8004b30: b480 push {r7}
|
|
8004b32: b083 sub sp, #12
|
|
8004b34: af00 add r7, sp, #0
|
|
8004b36: 6078 str r0, [r7, #4]
|
|
8004b38: 460b mov r3, r1
|
|
8004b3a: 807b strh r3, [r7, #2]
|
|
8004b3c: 4613 mov r3, r2
|
|
8004b3e: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8004b40: 787b ldrb r3, [r7, #1]
|
|
8004b42: 2b00 cmp r3, #0
|
|
8004b44: d003 beq.n 8004b4e <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8004b46: 887a ldrh r2, [r7, #2]
|
|
8004b48: 687b ldr r3, [r7, #4]
|
|
8004b4a: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8004b4c: e002 b.n 8004b54 <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8004b4e: 887a ldrh r2, [r7, #2]
|
|
8004b50: 687b ldr r3, [r7, #4]
|
|
8004b52: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
8004b54: bf00 nop
|
|
8004b56: 370c adds r7, #12
|
|
8004b58: 46bd mov sp, r7
|
|
8004b5a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b5e: 4770 bx lr
|
|
|
|
08004b60 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8004b60: b580 push {r7, lr}
|
|
8004b62: f5ad 7d00 sub.w sp, sp, #512 @ 0x200
|
|
8004b66: af00 add r7, sp, #0
|
|
8004b68: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004b6c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004b70: 6018 str r0, [r3, #0]
|
|
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
|
|
uint32_t pll_config2;
|
|
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8004b72: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004b76: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004b7a: 681b ldr r3, [r3, #0]
|
|
8004b7c: 2b00 cmp r3, #0
|
|
8004b7e: d102 bne.n 8004b86 <HAL_RCC_OscConfig+0x26>
|
|
{
|
|
return HAL_ERROR;
|
|
8004b80: 2301 movs r3, #1
|
|
8004b82: f001 b823 b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8004b86: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004b8a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004b8e: 681b ldr r3, [r3, #0]
|
|
8004b90: 681b ldr r3, [r3, #0]
|
|
8004b92: f003 0301 and.w r3, r3, #1
|
|
8004b96: 2b00 cmp r3, #0
|
|
8004b98: f000 817d beq.w 8004e96 <HAL_RCC_OscConfig+0x336>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
8004b9c: 4bbc ldr r3, [pc, #752] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004b9e: 685b ldr r3, [r3, #4]
|
|
8004ba0: f003 030c and.w r3, r3, #12
|
|
8004ba4: 2b04 cmp r3, #4
|
|
8004ba6: d00c beq.n 8004bc2 <HAL_RCC_OscConfig+0x62>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
|
|
8004ba8: 4bb9 ldr r3, [pc, #740] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004baa: 685b ldr r3, [r3, #4]
|
|
8004bac: f003 030c and.w r3, r3, #12
|
|
8004bb0: 2b08 cmp r3, #8
|
|
8004bb2: d15c bne.n 8004c6e <HAL_RCC_OscConfig+0x10e>
|
|
8004bb4: 4bb6 ldr r3, [pc, #728] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004bb6: 685b ldr r3, [r3, #4]
|
|
8004bb8: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8004bbc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004bc0: d155 bne.n 8004c6e <HAL_RCC_OscConfig+0x10e>
|
|
8004bc2: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004bc6: f8c7 31f0 str.w r3, [r7, #496] @ 0x1f0
|
|
uint32_t result;
|
|
|
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
|
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
|
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004bca: f8d7 31f0 ldr.w r3, [r7, #496] @ 0x1f0
|
|
8004bce: fa93 f3a3 rbit r3, r3
|
|
8004bd2: f8c7 31ec str.w r3, [r7, #492] @ 0x1ec
|
|
result |= value & 1U;
|
|
s--;
|
|
}
|
|
result <<= s; /* shift when v's highest bits are zero */
|
|
#endif
|
|
return result;
|
|
8004bd6: f8d7 31ec ldr.w r3, [r7, #492] @ 0x1ec
|
|
{
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004bda: fab3 f383 clz r3, r3
|
|
8004bde: b2db uxtb r3, r3
|
|
8004be0: 095b lsrs r3, r3, #5
|
|
8004be2: b2db uxtb r3, r3
|
|
8004be4: f043 0301 orr.w r3, r3, #1
|
|
8004be8: b2db uxtb r3, r3
|
|
8004bea: 2b01 cmp r3, #1
|
|
8004bec: d102 bne.n 8004bf4 <HAL_RCC_OscConfig+0x94>
|
|
8004bee: 4ba8 ldr r3, [pc, #672] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004bf0: 681b ldr r3, [r3, #0]
|
|
8004bf2: e015 b.n 8004c20 <HAL_RCC_OscConfig+0xc0>
|
|
8004bf4: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004bf8: f8c7 31e8 str.w r3, [r7, #488] @ 0x1e8
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004bfc: f8d7 31e8 ldr.w r3, [r7, #488] @ 0x1e8
|
|
8004c00: fa93 f3a3 rbit r3, r3
|
|
8004c04: f8c7 31e4 str.w r3, [r7, #484] @ 0x1e4
|
|
8004c08: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004c0c: f8c7 31e0 str.w r3, [r7, #480] @ 0x1e0
|
|
8004c10: f8d7 31e0 ldr.w r3, [r7, #480] @ 0x1e0
|
|
8004c14: fa93 f3a3 rbit r3, r3
|
|
8004c18: f8c7 31dc str.w r3, [r7, #476] @ 0x1dc
|
|
8004c1c: 4b9c ldr r3, [pc, #624] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004c1e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004c20: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
8004c24: f8c7 21d8 str.w r2, [r7, #472] @ 0x1d8
|
|
8004c28: f8d7 21d8 ldr.w r2, [r7, #472] @ 0x1d8
|
|
8004c2c: fa92 f2a2 rbit r2, r2
|
|
8004c30: f8c7 21d4 str.w r2, [r7, #468] @ 0x1d4
|
|
return result;
|
|
8004c34: f8d7 21d4 ldr.w r2, [r7, #468] @ 0x1d4
|
|
8004c38: fab2 f282 clz r2, r2
|
|
8004c3c: b2d2 uxtb r2, r2
|
|
8004c3e: f042 0220 orr.w r2, r2, #32
|
|
8004c42: b2d2 uxtb r2, r2
|
|
8004c44: f002 021f and.w r2, r2, #31
|
|
8004c48: 2101 movs r1, #1
|
|
8004c4a: fa01 f202 lsl.w r2, r1, r2
|
|
8004c4e: 4013 ands r3, r2
|
|
8004c50: 2b00 cmp r3, #0
|
|
8004c52: f000 811f beq.w 8004e94 <HAL_RCC_OscConfig+0x334>
|
|
8004c56: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004c5a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004c5e: 681b ldr r3, [r3, #0]
|
|
8004c60: 685b ldr r3, [r3, #4]
|
|
8004c62: 2b00 cmp r3, #0
|
|
8004c64: f040 8116 bne.w 8004e94 <HAL_RCC_OscConfig+0x334>
|
|
{
|
|
return HAL_ERROR;
|
|
8004c68: 2301 movs r3, #1
|
|
8004c6a: f000 bfaf b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8004c6e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004c72: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004c76: 681b ldr r3, [r3, #0]
|
|
8004c78: 685b ldr r3, [r3, #4]
|
|
8004c7a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004c7e: d106 bne.n 8004c8e <HAL_RCC_OscConfig+0x12e>
|
|
8004c80: 4b83 ldr r3, [pc, #524] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004c82: 681b ldr r3, [r3, #0]
|
|
8004c84: 4a82 ldr r2, [pc, #520] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004c86: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004c8a: 6013 str r3, [r2, #0]
|
|
8004c8c: e036 b.n 8004cfc <HAL_RCC_OscConfig+0x19c>
|
|
8004c8e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004c92: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004c96: 681b ldr r3, [r3, #0]
|
|
8004c98: 685b ldr r3, [r3, #4]
|
|
8004c9a: 2b00 cmp r3, #0
|
|
8004c9c: d10c bne.n 8004cb8 <HAL_RCC_OscConfig+0x158>
|
|
8004c9e: 4b7c ldr r3, [pc, #496] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004ca0: 681b ldr r3, [r3, #0]
|
|
8004ca2: 4a7b ldr r2, [pc, #492] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004ca4: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8004ca8: 6013 str r3, [r2, #0]
|
|
8004caa: 4b79 ldr r3, [pc, #484] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cac: 681b ldr r3, [r3, #0]
|
|
8004cae: 4a78 ldr r2, [pc, #480] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cb0: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8004cb4: 6013 str r3, [r2, #0]
|
|
8004cb6: e021 b.n 8004cfc <HAL_RCC_OscConfig+0x19c>
|
|
8004cb8: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004cbc: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004cc0: 681b ldr r3, [r3, #0]
|
|
8004cc2: 685b ldr r3, [r3, #4]
|
|
8004cc4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8004cc8: d10c bne.n 8004ce4 <HAL_RCC_OscConfig+0x184>
|
|
8004cca: 4b71 ldr r3, [pc, #452] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004ccc: 681b ldr r3, [r3, #0]
|
|
8004cce: 4a70 ldr r2, [pc, #448] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cd0: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8004cd4: 6013 str r3, [r2, #0]
|
|
8004cd6: 4b6e ldr r3, [pc, #440] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cd8: 681b ldr r3, [r3, #0]
|
|
8004cda: 4a6d ldr r2, [pc, #436] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cdc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004ce0: 6013 str r3, [r2, #0]
|
|
8004ce2: e00b b.n 8004cfc <HAL_RCC_OscConfig+0x19c>
|
|
8004ce4: 4b6a ldr r3, [pc, #424] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004ce6: 681b ldr r3, [r3, #0]
|
|
8004ce8: 4a69 ldr r2, [pc, #420] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cea: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8004cee: 6013 str r3, [r2, #0]
|
|
8004cf0: 4b67 ldr r3, [pc, #412] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cf2: 681b ldr r3, [r3, #0]
|
|
8004cf4: 4a66 ldr r2, [pc, #408] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cf6: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8004cfa: 6013 str r3, [r2, #0]
|
|
|
|
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
|
|
/* Configure the HSE predivision factor --------------------------------*/
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
8004cfc: 4b64 ldr r3, [pc, #400] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004cfe: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004d00: f023 020f bic.w r2, r3, #15
|
|
8004d04: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004d08: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004d0c: 681b ldr r3, [r3, #0]
|
|
8004d0e: 689b ldr r3, [r3, #8]
|
|
8004d10: 495f ldr r1, [pc, #380] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004d12: 4313 orrs r3, r2
|
|
8004d14: 62cb str r3, [r1, #44] @ 0x2c
|
|
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8004d16: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004d1a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004d1e: 681b ldr r3, [r3, #0]
|
|
8004d20: 685b ldr r3, [r3, #4]
|
|
8004d22: 2b00 cmp r3, #0
|
|
8004d24: d059 beq.n 8004dda <HAL_RCC_OscConfig+0x27a>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004d26: f7fd fae5 bl 80022f4 <HAL_GetTick>
|
|
8004d2a: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till HSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004d2e: e00a b.n 8004d46 <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|
8004d30: f7fd fae0 bl 80022f4 <HAL_GetTick>
|
|
8004d34: 4602 mov r2, r0
|
|
8004d36: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
8004d3a: 1ad3 subs r3, r2, r3
|
|
8004d3c: 2b64 cmp r3, #100 @ 0x64
|
|
8004d3e: d902 bls.n 8004d46 <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004d40: 2303 movs r3, #3
|
|
8004d42: f000 bf43 b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8004d46: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004d4a: f8c7 31d0 str.w r3, [r7, #464] @ 0x1d0
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004d4e: f8d7 31d0 ldr.w r3, [r7, #464] @ 0x1d0
|
|
8004d52: fa93 f3a3 rbit r3, r3
|
|
8004d56: f8c7 31cc str.w r3, [r7, #460] @ 0x1cc
|
|
return result;
|
|
8004d5a: f8d7 31cc ldr.w r3, [r7, #460] @ 0x1cc
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004d5e: fab3 f383 clz r3, r3
|
|
8004d62: b2db uxtb r3, r3
|
|
8004d64: 095b lsrs r3, r3, #5
|
|
8004d66: b2db uxtb r3, r3
|
|
8004d68: f043 0301 orr.w r3, r3, #1
|
|
8004d6c: b2db uxtb r3, r3
|
|
8004d6e: 2b01 cmp r3, #1
|
|
8004d70: d102 bne.n 8004d78 <HAL_RCC_OscConfig+0x218>
|
|
8004d72: 4b47 ldr r3, [pc, #284] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004d74: 681b ldr r3, [r3, #0]
|
|
8004d76: e015 b.n 8004da4 <HAL_RCC_OscConfig+0x244>
|
|
8004d78: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004d7c: f8c7 31c8 str.w r3, [r7, #456] @ 0x1c8
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004d80: f8d7 31c8 ldr.w r3, [r7, #456] @ 0x1c8
|
|
8004d84: fa93 f3a3 rbit r3, r3
|
|
8004d88: f8c7 31c4 str.w r3, [r7, #452] @ 0x1c4
|
|
8004d8c: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004d90: f8c7 31c0 str.w r3, [r7, #448] @ 0x1c0
|
|
8004d94: f8d7 31c0 ldr.w r3, [r7, #448] @ 0x1c0
|
|
8004d98: fa93 f3a3 rbit r3, r3
|
|
8004d9c: f8c7 31bc str.w r3, [r7, #444] @ 0x1bc
|
|
8004da0: 4b3b ldr r3, [pc, #236] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004da2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004da4: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
8004da8: f8c7 21b8 str.w r2, [r7, #440] @ 0x1b8
|
|
8004dac: f8d7 21b8 ldr.w r2, [r7, #440] @ 0x1b8
|
|
8004db0: fa92 f2a2 rbit r2, r2
|
|
8004db4: f8c7 21b4 str.w r2, [r7, #436] @ 0x1b4
|
|
return result;
|
|
8004db8: f8d7 21b4 ldr.w r2, [r7, #436] @ 0x1b4
|
|
8004dbc: fab2 f282 clz r2, r2
|
|
8004dc0: b2d2 uxtb r2, r2
|
|
8004dc2: f042 0220 orr.w r2, r2, #32
|
|
8004dc6: b2d2 uxtb r2, r2
|
|
8004dc8: f002 021f and.w r2, r2, #31
|
|
8004dcc: 2101 movs r1, #1
|
|
8004dce: fa01 f202 lsl.w r2, r1, r2
|
|
8004dd2: 4013 ands r3, r2
|
|
8004dd4: 2b00 cmp r3, #0
|
|
8004dd6: d0ab beq.n 8004d30 <HAL_RCC_OscConfig+0x1d0>
|
|
8004dd8: e05d b.n 8004e96 <HAL_RCC_OscConfig+0x336>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004dda: f7fd fa8b bl 80022f4 <HAL_GetTick>
|
|
8004dde: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8004de2: e00a b.n 8004dfa <HAL_RCC_OscConfig+0x29a>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
|
|
8004de4: f7fd fa86 bl 80022f4 <HAL_GetTick>
|
|
8004de8: 4602 mov r2, r0
|
|
8004dea: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
8004dee: 1ad3 subs r3, r2, r3
|
|
8004df0: 2b64 cmp r3, #100 @ 0x64
|
|
8004df2: d902 bls.n 8004dfa <HAL_RCC_OscConfig+0x29a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004df4: 2303 movs r3, #3
|
|
8004df6: f000 bee9 b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8004dfa: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004dfe: f8c7 31b0 str.w r3, [r7, #432] @ 0x1b0
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004e02: f8d7 31b0 ldr.w r3, [r7, #432] @ 0x1b0
|
|
8004e06: fa93 f3a3 rbit r3, r3
|
|
8004e0a: f8c7 31ac str.w r3, [r7, #428] @ 0x1ac
|
|
return result;
|
|
8004e0e: f8d7 31ac ldr.w r3, [r7, #428] @ 0x1ac
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8004e12: fab3 f383 clz r3, r3
|
|
8004e16: b2db uxtb r3, r3
|
|
8004e18: 095b lsrs r3, r3, #5
|
|
8004e1a: b2db uxtb r3, r3
|
|
8004e1c: f043 0301 orr.w r3, r3, #1
|
|
8004e20: b2db uxtb r3, r3
|
|
8004e22: 2b01 cmp r3, #1
|
|
8004e24: d102 bne.n 8004e2c <HAL_RCC_OscConfig+0x2cc>
|
|
8004e26: 4b1a ldr r3, [pc, #104] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004e28: 681b ldr r3, [r3, #0]
|
|
8004e2a: e015 b.n 8004e58 <HAL_RCC_OscConfig+0x2f8>
|
|
8004e2c: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004e30: f8c7 31a8 str.w r3, [r7, #424] @ 0x1a8
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004e34: f8d7 31a8 ldr.w r3, [r7, #424] @ 0x1a8
|
|
8004e38: fa93 f3a3 rbit r3, r3
|
|
8004e3c: f8c7 31a4 str.w r3, [r7, #420] @ 0x1a4
|
|
8004e40: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8004e44: f8c7 31a0 str.w r3, [r7, #416] @ 0x1a0
|
|
8004e48: f8d7 31a0 ldr.w r3, [r7, #416] @ 0x1a0
|
|
8004e4c: fa93 f3a3 rbit r3, r3
|
|
8004e50: f8c7 319c str.w r3, [r7, #412] @ 0x19c
|
|
8004e54: 4b0e ldr r3, [pc, #56] @ (8004e90 <HAL_RCC_OscConfig+0x330>)
|
|
8004e56: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004e58: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
8004e5c: f8c7 2198 str.w r2, [r7, #408] @ 0x198
|
|
8004e60: f8d7 2198 ldr.w r2, [r7, #408] @ 0x198
|
|
8004e64: fa92 f2a2 rbit r2, r2
|
|
8004e68: f8c7 2194 str.w r2, [r7, #404] @ 0x194
|
|
return result;
|
|
8004e6c: f8d7 2194 ldr.w r2, [r7, #404] @ 0x194
|
|
8004e70: fab2 f282 clz r2, r2
|
|
8004e74: b2d2 uxtb r2, r2
|
|
8004e76: f042 0220 orr.w r2, r2, #32
|
|
8004e7a: b2d2 uxtb r2, r2
|
|
8004e7c: f002 021f and.w r2, r2, #31
|
|
8004e80: 2101 movs r1, #1
|
|
8004e82: fa01 f202 lsl.w r2, r1, r2
|
|
8004e86: 4013 ands r3, r2
|
|
8004e88: 2b00 cmp r3, #0
|
|
8004e8a: d1ab bne.n 8004de4 <HAL_RCC_OscConfig+0x284>
|
|
8004e8c: e003 b.n 8004e96 <HAL_RCC_OscConfig+0x336>
|
|
8004e8e: bf00 nop
|
|
8004e90: 40021000 .word 0x40021000
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004e94: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8004e96: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004e9a: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004e9e: 681b ldr r3, [r3, #0]
|
|
8004ea0: 681b ldr r3, [r3, #0]
|
|
8004ea2: f003 0302 and.w r3, r3, #2
|
|
8004ea6: 2b00 cmp r3, #0
|
|
8004ea8: f000 817d beq.w 80051a6 <HAL_RCC_OscConfig+0x646>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
8004eac: 4ba6 ldr r3, [pc, #664] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8004eae: 685b ldr r3, [r3, #4]
|
|
8004eb0: f003 030c and.w r3, r3, #12
|
|
8004eb4: 2b00 cmp r3, #0
|
|
8004eb6: d00b beq.n 8004ed0 <HAL_RCC_OscConfig+0x370>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
|
|
8004eb8: 4ba3 ldr r3, [pc, #652] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8004eba: 685b ldr r3, [r3, #4]
|
|
8004ebc: f003 030c and.w r3, r3, #12
|
|
8004ec0: 2b08 cmp r3, #8
|
|
8004ec2: d172 bne.n 8004faa <HAL_RCC_OscConfig+0x44a>
|
|
8004ec4: 4ba0 ldr r3, [pc, #640] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8004ec6: 685b ldr r3, [r3, #4]
|
|
8004ec8: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8004ecc: 2b00 cmp r3, #0
|
|
8004ece: d16c bne.n 8004faa <HAL_RCC_OscConfig+0x44a>
|
|
8004ed0: 2302 movs r3, #2
|
|
8004ed2: f8c7 3190 str.w r3, [r7, #400] @ 0x190
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004ed6: f8d7 3190 ldr.w r3, [r7, #400] @ 0x190
|
|
8004eda: fa93 f3a3 rbit r3, r3
|
|
8004ede: f8c7 318c str.w r3, [r7, #396] @ 0x18c
|
|
return result;
|
|
8004ee2: f8d7 318c ldr.w r3, [r7, #396] @ 0x18c
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004ee6: fab3 f383 clz r3, r3
|
|
8004eea: b2db uxtb r3, r3
|
|
8004eec: 095b lsrs r3, r3, #5
|
|
8004eee: b2db uxtb r3, r3
|
|
8004ef0: f043 0301 orr.w r3, r3, #1
|
|
8004ef4: b2db uxtb r3, r3
|
|
8004ef6: 2b01 cmp r3, #1
|
|
8004ef8: d102 bne.n 8004f00 <HAL_RCC_OscConfig+0x3a0>
|
|
8004efa: 4b93 ldr r3, [pc, #588] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8004efc: 681b ldr r3, [r3, #0]
|
|
8004efe: e013 b.n 8004f28 <HAL_RCC_OscConfig+0x3c8>
|
|
8004f00: 2302 movs r3, #2
|
|
8004f02: f8c7 3188 str.w r3, [r7, #392] @ 0x188
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004f06: f8d7 3188 ldr.w r3, [r7, #392] @ 0x188
|
|
8004f0a: fa93 f3a3 rbit r3, r3
|
|
8004f0e: f8c7 3184 str.w r3, [r7, #388] @ 0x184
|
|
8004f12: 2302 movs r3, #2
|
|
8004f14: f8c7 3180 str.w r3, [r7, #384] @ 0x180
|
|
8004f18: f8d7 3180 ldr.w r3, [r7, #384] @ 0x180
|
|
8004f1c: fa93 f3a3 rbit r3, r3
|
|
8004f20: f8c7 317c str.w r3, [r7, #380] @ 0x17c
|
|
8004f24: 4b88 ldr r3, [pc, #544] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8004f26: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004f28: 2202 movs r2, #2
|
|
8004f2a: f8c7 2178 str.w r2, [r7, #376] @ 0x178
|
|
8004f2e: f8d7 2178 ldr.w r2, [r7, #376] @ 0x178
|
|
8004f32: fa92 f2a2 rbit r2, r2
|
|
8004f36: f8c7 2174 str.w r2, [r7, #372] @ 0x174
|
|
return result;
|
|
8004f3a: f8d7 2174 ldr.w r2, [r7, #372] @ 0x174
|
|
8004f3e: fab2 f282 clz r2, r2
|
|
8004f42: b2d2 uxtb r2, r2
|
|
8004f44: f042 0220 orr.w r2, r2, #32
|
|
8004f48: b2d2 uxtb r2, r2
|
|
8004f4a: f002 021f and.w r2, r2, #31
|
|
8004f4e: 2101 movs r1, #1
|
|
8004f50: fa01 f202 lsl.w r2, r1, r2
|
|
8004f54: 4013 ands r3, r2
|
|
8004f56: 2b00 cmp r3, #0
|
|
8004f58: d00a beq.n 8004f70 <HAL_RCC_OscConfig+0x410>
|
|
8004f5a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004f5e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004f62: 681b ldr r3, [r3, #0]
|
|
8004f64: 691b ldr r3, [r3, #16]
|
|
8004f66: 2b01 cmp r3, #1
|
|
8004f68: d002 beq.n 8004f70 <HAL_RCC_OscConfig+0x410>
|
|
{
|
|
return HAL_ERROR;
|
|
8004f6a: 2301 movs r3, #1
|
|
8004f6c: f000 be2e b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004f70: 4b75 ldr r3, [pc, #468] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8004f72: 681b ldr r3, [r3, #0]
|
|
8004f74: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004f78: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004f7c: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004f80: 681b ldr r3, [r3, #0]
|
|
8004f82: 695b ldr r3, [r3, #20]
|
|
8004f84: 21f8 movs r1, #248 @ 0xf8
|
|
8004f86: f8c7 1170 str.w r1, [r7, #368] @ 0x170
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004f8a: f8d7 1170 ldr.w r1, [r7, #368] @ 0x170
|
|
8004f8e: fa91 f1a1 rbit r1, r1
|
|
8004f92: f8c7 116c str.w r1, [r7, #364] @ 0x16c
|
|
return result;
|
|
8004f96: f8d7 116c ldr.w r1, [r7, #364] @ 0x16c
|
|
8004f9a: fab1 f181 clz r1, r1
|
|
8004f9e: b2c9 uxtb r1, r1
|
|
8004fa0: 408b lsls r3, r1
|
|
8004fa2: 4969 ldr r1, [pc, #420] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8004fa4: 4313 orrs r3, r2
|
|
8004fa6: 600b str r3, [r1, #0]
|
|
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004fa8: e0fd b.n 80051a6 <HAL_RCC_OscConfig+0x646>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8004faa: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8004fae: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8004fb2: 681b ldr r3, [r3, #0]
|
|
8004fb4: 691b ldr r3, [r3, #16]
|
|
8004fb6: 2b00 cmp r3, #0
|
|
8004fb8: f000 8088 beq.w 80050cc <HAL_RCC_OscConfig+0x56c>
|
|
8004fbc: 2301 movs r3, #1
|
|
8004fbe: f8c7 3168 str.w r3, [r7, #360] @ 0x168
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8004fc2: f8d7 3168 ldr.w r3, [r7, #360] @ 0x168
|
|
8004fc6: fa93 f3a3 rbit r3, r3
|
|
8004fca: f8c7 3164 str.w r3, [r7, #356] @ 0x164
|
|
return result;
|
|
8004fce: f8d7 3164 ldr.w r3, [r7, #356] @ 0x164
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8004fd2: fab3 f383 clz r3, r3
|
|
8004fd6: b2db uxtb r3, r3
|
|
8004fd8: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
|
|
8004fdc: f503 1384 add.w r3, r3, #1081344 @ 0x108000
|
|
8004fe0: 009b lsls r3, r3, #2
|
|
8004fe2: 461a mov r2, r3
|
|
8004fe4: 2301 movs r3, #1
|
|
8004fe6: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004fe8: f7fd f984 bl 80022f4 <HAL_GetTick>
|
|
8004fec: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till HSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004ff0: e00a b.n 8005008 <HAL_RCC_OscConfig+0x4a8>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
8004ff2: f7fd f97f bl 80022f4 <HAL_GetTick>
|
|
8004ff6: 4602 mov r2, r0
|
|
8004ff8: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
8004ffc: 1ad3 subs r3, r2, r3
|
|
8004ffe: 2b02 cmp r3, #2
|
|
8005000: d902 bls.n 8005008 <HAL_RCC_OscConfig+0x4a8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005002: 2303 movs r3, #3
|
|
8005004: f000 bde2 b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8005008: 2302 movs r3, #2
|
|
800500a: f8c7 3160 str.w r3, [r7, #352] @ 0x160
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800500e: f8d7 3160 ldr.w r3, [r7, #352] @ 0x160
|
|
8005012: fa93 f3a3 rbit r3, r3
|
|
8005016: f8c7 315c str.w r3, [r7, #348] @ 0x15c
|
|
return result;
|
|
800501a: f8d7 315c ldr.w r3, [r7, #348] @ 0x15c
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800501e: fab3 f383 clz r3, r3
|
|
8005022: b2db uxtb r3, r3
|
|
8005024: 095b lsrs r3, r3, #5
|
|
8005026: b2db uxtb r3, r3
|
|
8005028: f043 0301 orr.w r3, r3, #1
|
|
800502c: b2db uxtb r3, r3
|
|
800502e: 2b01 cmp r3, #1
|
|
8005030: d102 bne.n 8005038 <HAL_RCC_OscConfig+0x4d8>
|
|
8005032: 4b45 ldr r3, [pc, #276] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8005034: 681b ldr r3, [r3, #0]
|
|
8005036: e013 b.n 8005060 <HAL_RCC_OscConfig+0x500>
|
|
8005038: 2302 movs r3, #2
|
|
800503a: f8c7 3158 str.w r3, [r7, #344] @ 0x158
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800503e: f8d7 3158 ldr.w r3, [r7, #344] @ 0x158
|
|
8005042: fa93 f3a3 rbit r3, r3
|
|
8005046: f8c7 3154 str.w r3, [r7, #340] @ 0x154
|
|
800504a: 2302 movs r3, #2
|
|
800504c: f8c7 3150 str.w r3, [r7, #336] @ 0x150
|
|
8005050: f8d7 3150 ldr.w r3, [r7, #336] @ 0x150
|
|
8005054: fa93 f3a3 rbit r3, r3
|
|
8005058: f8c7 314c str.w r3, [r7, #332] @ 0x14c
|
|
800505c: 4b3a ldr r3, [pc, #232] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
800505e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005060: 2202 movs r2, #2
|
|
8005062: f8c7 2148 str.w r2, [r7, #328] @ 0x148
|
|
8005066: f8d7 2148 ldr.w r2, [r7, #328] @ 0x148
|
|
800506a: fa92 f2a2 rbit r2, r2
|
|
800506e: f8c7 2144 str.w r2, [r7, #324] @ 0x144
|
|
return result;
|
|
8005072: f8d7 2144 ldr.w r2, [r7, #324] @ 0x144
|
|
8005076: fab2 f282 clz r2, r2
|
|
800507a: b2d2 uxtb r2, r2
|
|
800507c: f042 0220 orr.w r2, r2, #32
|
|
8005080: b2d2 uxtb r2, r2
|
|
8005082: f002 021f and.w r2, r2, #31
|
|
8005086: 2101 movs r1, #1
|
|
8005088: fa01 f202 lsl.w r2, r1, r2
|
|
800508c: 4013 ands r3, r2
|
|
800508e: 2b00 cmp r3, #0
|
|
8005090: d0af beq.n 8004ff2 <HAL_RCC_OscConfig+0x492>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8005092: 4b2d ldr r3, [pc, #180] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8005094: 681b ldr r3, [r3, #0]
|
|
8005096: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
800509a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800509e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
80050a2: 681b ldr r3, [r3, #0]
|
|
80050a4: 695b ldr r3, [r3, #20]
|
|
80050a6: 21f8 movs r1, #248 @ 0xf8
|
|
80050a8: f8c7 1140 str.w r1, [r7, #320] @ 0x140
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80050ac: f8d7 1140 ldr.w r1, [r7, #320] @ 0x140
|
|
80050b0: fa91 f1a1 rbit r1, r1
|
|
80050b4: f8c7 113c str.w r1, [r7, #316] @ 0x13c
|
|
return result;
|
|
80050b8: f8d7 113c ldr.w r1, [r7, #316] @ 0x13c
|
|
80050bc: fab1 f181 clz r1, r1
|
|
80050c0: b2c9 uxtb r1, r1
|
|
80050c2: 408b lsls r3, r1
|
|
80050c4: 4920 ldr r1, [pc, #128] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
80050c6: 4313 orrs r3, r2
|
|
80050c8: 600b str r3, [r1, #0]
|
|
80050ca: e06c b.n 80051a6 <HAL_RCC_OscConfig+0x646>
|
|
80050cc: 2301 movs r3, #1
|
|
80050ce: f8c7 3138 str.w r3, [r7, #312] @ 0x138
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80050d2: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138
|
|
80050d6: fa93 f3a3 rbit r3, r3
|
|
80050da: f8c7 3134 str.w r3, [r7, #308] @ 0x134
|
|
return result;
|
|
80050de: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
80050e2: fab3 f383 clz r3, r3
|
|
80050e6: b2db uxtb r3, r3
|
|
80050e8: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
|
|
80050ec: f503 1384 add.w r3, r3, #1081344 @ 0x108000
|
|
80050f0: 009b lsls r3, r3, #2
|
|
80050f2: 461a mov r2, r3
|
|
80050f4: 2300 movs r3, #0
|
|
80050f6: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80050f8: f7fd f8fc bl 80022f4 <HAL_GetTick>
|
|
80050fc: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8005100: e00a b.n 8005118 <HAL_RCC_OscConfig+0x5b8>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
8005102: f7fd f8f7 bl 80022f4 <HAL_GetTick>
|
|
8005106: 4602 mov r2, r0
|
|
8005108: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
800510c: 1ad3 subs r3, r2, r3
|
|
800510e: 2b02 cmp r3, #2
|
|
8005110: d902 bls.n 8005118 <HAL_RCC_OscConfig+0x5b8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005112: 2303 movs r3, #3
|
|
8005114: f000 bd5a b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8005118: 2302 movs r3, #2
|
|
800511a: f8c7 3130 str.w r3, [r7, #304] @ 0x130
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800511e: f8d7 3130 ldr.w r3, [r7, #304] @ 0x130
|
|
8005122: fa93 f3a3 rbit r3, r3
|
|
8005126: f8c7 312c str.w r3, [r7, #300] @ 0x12c
|
|
return result;
|
|
800512a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
800512e: fab3 f383 clz r3, r3
|
|
8005132: b2db uxtb r3, r3
|
|
8005134: 095b lsrs r3, r3, #5
|
|
8005136: b2db uxtb r3, r3
|
|
8005138: f043 0301 orr.w r3, r3, #1
|
|
800513c: b2db uxtb r3, r3
|
|
800513e: 2b01 cmp r3, #1
|
|
8005140: d104 bne.n 800514c <HAL_RCC_OscConfig+0x5ec>
|
|
8005142: 4b01 ldr r3, [pc, #4] @ (8005148 <HAL_RCC_OscConfig+0x5e8>)
|
|
8005144: 681b ldr r3, [r3, #0]
|
|
8005146: e015 b.n 8005174 <HAL_RCC_OscConfig+0x614>
|
|
8005148: 40021000 .word 0x40021000
|
|
800514c: 2302 movs r3, #2
|
|
800514e: f8c7 3128 str.w r3, [r7, #296] @ 0x128
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005152: f8d7 3128 ldr.w r3, [r7, #296] @ 0x128
|
|
8005156: fa93 f3a3 rbit r3, r3
|
|
800515a: f8c7 3124 str.w r3, [r7, #292] @ 0x124
|
|
800515e: 2302 movs r3, #2
|
|
8005160: f8c7 3120 str.w r3, [r7, #288] @ 0x120
|
|
8005164: f8d7 3120 ldr.w r3, [r7, #288] @ 0x120
|
|
8005168: fa93 f3a3 rbit r3, r3
|
|
800516c: f8c7 311c str.w r3, [r7, #284] @ 0x11c
|
|
8005170: 4bc8 ldr r3, [pc, #800] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
8005172: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005174: 2202 movs r2, #2
|
|
8005176: f8c7 2118 str.w r2, [r7, #280] @ 0x118
|
|
800517a: f8d7 2118 ldr.w r2, [r7, #280] @ 0x118
|
|
800517e: fa92 f2a2 rbit r2, r2
|
|
8005182: f8c7 2114 str.w r2, [r7, #276] @ 0x114
|
|
return result;
|
|
8005186: f8d7 2114 ldr.w r2, [r7, #276] @ 0x114
|
|
800518a: fab2 f282 clz r2, r2
|
|
800518e: b2d2 uxtb r2, r2
|
|
8005190: f042 0220 orr.w r2, r2, #32
|
|
8005194: b2d2 uxtb r2, r2
|
|
8005196: f002 021f and.w r2, r2, #31
|
|
800519a: 2101 movs r1, #1
|
|
800519c: fa01 f202 lsl.w r2, r1, r2
|
|
80051a0: 4013 ands r3, r2
|
|
80051a2: 2b00 cmp r3, #0
|
|
80051a4: d1ad bne.n 8005102 <HAL_RCC_OscConfig+0x5a2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
80051a6: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80051aa: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
80051ae: 681b ldr r3, [r3, #0]
|
|
80051b0: 681b ldr r3, [r3, #0]
|
|
80051b2: f003 0308 and.w r3, r3, #8
|
|
80051b6: 2b00 cmp r3, #0
|
|
80051b8: f000 8110 beq.w 80053dc <HAL_RCC_OscConfig+0x87c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
80051bc: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80051c0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
80051c4: 681b ldr r3, [r3, #0]
|
|
80051c6: 699b ldr r3, [r3, #24]
|
|
80051c8: 2b00 cmp r3, #0
|
|
80051ca: d079 beq.n 80052c0 <HAL_RCC_OscConfig+0x760>
|
|
80051cc: 2301 movs r3, #1
|
|
80051ce: f8c7 3110 str.w r3, [r7, #272] @ 0x110
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80051d2: f8d7 3110 ldr.w r3, [r7, #272] @ 0x110
|
|
80051d6: fa93 f3a3 rbit r3, r3
|
|
80051da: f8c7 310c str.w r3, [r7, #268] @ 0x10c
|
|
return result;
|
|
80051de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
80051e2: fab3 f383 clz r3, r3
|
|
80051e6: b2db uxtb r3, r3
|
|
80051e8: 461a mov r2, r3
|
|
80051ea: 4bab ldr r3, [pc, #684] @ (8005498 <HAL_RCC_OscConfig+0x938>)
|
|
80051ec: 4413 add r3, r2
|
|
80051ee: 009b lsls r3, r3, #2
|
|
80051f0: 461a mov r2, r3
|
|
80051f2: 2301 movs r3, #1
|
|
80051f4: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80051f6: f7fd f87d bl 80022f4 <HAL_GetTick>
|
|
80051fa: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till LSI is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80051fe: e00a b.n 8005216 <HAL_RCC_OscConfig+0x6b6>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
8005200: f7fd f878 bl 80022f4 <HAL_GetTick>
|
|
8005204: 4602 mov r2, r0
|
|
8005206: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
800520a: 1ad3 subs r3, r2, r3
|
|
800520c: 2b02 cmp r3, #2
|
|
800520e: d902 bls.n 8005216 <HAL_RCC_OscConfig+0x6b6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005210: 2303 movs r3, #3
|
|
8005212: f000 bcdb b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8005216: 2302 movs r3, #2
|
|
8005218: f8c7 3108 str.w r3, [r7, #264] @ 0x108
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800521c: f8d7 3108 ldr.w r3, [r7, #264] @ 0x108
|
|
8005220: fa93 f3a3 rbit r3, r3
|
|
8005224: f8c7 3104 str.w r3, [r7, #260] @ 0x104
|
|
8005228: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800522c: f5a3 7380 sub.w r3, r3, #256 @ 0x100
|
|
8005230: 2202 movs r2, #2
|
|
8005232: 601a str r2, [r3, #0]
|
|
8005234: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005238: f5a3 7380 sub.w r3, r3, #256 @ 0x100
|
|
800523c: 681b ldr r3, [r3, #0]
|
|
800523e: fa93 f2a3 rbit r2, r3
|
|
8005242: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005246: f5a3 7382 sub.w r3, r3, #260 @ 0x104
|
|
800524a: 601a str r2, [r3, #0]
|
|
800524c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005250: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005254: 2202 movs r2, #2
|
|
8005256: 601a str r2, [r3, #0]
|
|
8005258: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800525c: f5a3 7384 sub.w r3, r3, #264 @ 0x108
|
|
8005260: 681b ldr r3, [r3, #0]
|
|
8005262: fa93 f2a3 rbit r2, r3
|
|
8005266: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800526a: f5a3 7386 sub.w r3, r3, #268 @ 0x10c
|
|
800526e: 601a str r2, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8005270: 4b88 ldr r3, [pc, #544] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
8005272: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8005274: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005278: f5a3 7388 sub.w r3, r3, #272 @ 0x110
|
|
800527c: 2102 movs r1, #2
|
|
800527e: 6019 str r1, [r3, #0]
|
|
8005280: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005284: f5a3 7388 sub.w r3, r3, #272 @ 0x110
|
|
8005288: 681b ldr r3, [r3, #0]
|
|
800528a: fa93 f1a3 rbit r1, r3
|
|
800528e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005292: f5a3 738a sub.w r3, r3, #276 @ 0x114
|
|
8005296: 6019 str r1, [r3, #0]
|
|
return result;
|
|
8005298: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800529c: f5a3 738a sub.w r3, r3, #276 @ 0x114
|
|
80052a0: 681b ldr r3, [r3, #0]
|
|
80052a2: fab3 f383 clz r3, r3
|
|
80052a6: b2db uxtb r3, r3
|
|
80052a8: f043 0360 orr.w r3, r3, #96 @ 0x60
|
|
80052ac: b2db uxtb r3, r3
|
|
80052ae: f003 031f and.w r3, r3, #31
|
|
80052b2: 2101 movs r1, #1
|
|
80052b4: fa01 f303 lsl.w r3, r1, r3
|
|
80052b8: 4013 ands r3, r2
|
|
80052ba: 2b00 cmp r3, #0
|
|
80052bc: d0a0 beq.n 8005200 <HAL_RCC_OscConfig+0x6a0>
|
|
80052be: e08d b.n 80053dc <HAL_RCC_OscConfig+0x87c>
|
|
80052c0: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80052c4: f5a3 738c sub.w r3, r3, #280 @ 0x118
|
|
80052c8: 2201 movs r2, #1
|
|
80052ca: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80052cc: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80052d0: f5a3 738c sub.w r3, r3, #280 @ 0x118
|
|
80052d4: 681b ldr r3, [r3, #0]
|
|
80052d6: fa93 f2a3 rbit r2, r3
|
|
80052da: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80052de: f5a3 738e sub.w r3, r3, #284 @ 0x11c
|
|
80052e2: 601a str r2, [r3, #0]
|
|
return result;
|
|
80052e4: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80052e8: f5a3 738e sub.w r3, r3, #284 @ 0x11c
|
|
80052ec: 681b ldr r3, [r3, #0]
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
80052ee: fab3 f383 clz r3, r3
|
|
80052f2: b2db uxtb r3, r3
|
|
80052f4: 461a mov r2, r3
|
|
80052f6: 4b68 ldr r3, [pc, #416] @ (8005498 <HAL_RCC_OscConfig+0x938>)
|
|
80052f8: 4413 add r3, r2
|
|
80052fa: 009b lsls r3, r3, #2
|
|
80052fc: 461a mov r2, r3
|
|
80052fe: 2300 movs r3, #0
|
|
8005300: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8005302: f7fc fff7 bl 80022f4 <HAL_GetTick>
|
|
8005306: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
800530a: e00a b.n 8005322 <HAL_RCC_OscConfig+0x7c2>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
800530c: f7fc fff2 bl 80022f4 <HAL_GetTick>
|
|
8005310: 4602 mov r2, r0
|
|
8005312: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
8005316: 1ad3 subs r3, r2, r3
|
|
8005318: 2b02 cmp r3, #2
|
|
800531a: d902 bls.n 8005322 <HAL_RCC_OscConfig+0x7c2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800531c: 2303 movs r3, #3
|
|
800531e: f000 bc55 b.w 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8005322: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005326: f5a3 7390 sub.w r3, r3, #288 @ 0x120
|
|
800532a: 2202 movs r2, #2
|
|
800532c: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800532e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005332: f5a3 7390 sub.w r3, r3, #288 @ 0x120
|
|
8005336: 681b ldr r3, [r3, #0]
|
|
8005338: fa93 f2a3 rbit r2, r3
|
|
800533c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005340: f5a3 7392 sub.w r3, r3, #292 @ 0x124
|
|
8005344: 601a str r2, [r3, #0]
|
|
8005346: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800534a: f5a3 7394 sub.w r3, r3, #296 @ 0x128
|
|
800534e: 2202 movs r2, #2
|
|
8005350: 601a str r2, [r3, #0]
|
|
8005352: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005356: f5a3 7394 sub.w r3, r3, #296 @ 0x128
|
|
800535a: 681b ldr r3, [r3, #0]
|
|
800535c: fa93 f2a3 rbit r2, r3
|
|
8005360: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005364: f5a3 7396 sub.w r3, r3, #300 @ 0x12c
|
|
8005368: 601a str r2, [r3, #0]
|
|
800536a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800536e: f5a3 7398 sub.w r3, r3, #304 @ 0x130
|
|
8005372: 2202 movs r2, #2
|
|
8005374: 601a str r2, [r3, #0]
|
|
8005376: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800537a: f5a3 7398 sub.w r3, r3, #304 @ 0x130
|
|
800537e: 681b ldr r3, [r3, #0]
|
|
8005380: fa93 f2a3 rbit r2, r3
|
|
8005384: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005388: f5a3 739a sub.w r3, r3, #308 @ 0x134
|
|
800538c: 601a str r2, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
800538e: 4b41 ldr r3, [pc, #260] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
8005390: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8005392: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005396: f5a3 739c sub.w r3, r3, #312 @ 0x138
|
|
800539a: 2102 movs r1, #2
|
|
800539c: 6019 str r1, [r3, #0]
|
|
800539e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80053a2: f5a3 739c sub.w r3, r3, #312 @ 0x138
|
|
80053a6: 681b ldr r3, [r3, #0]
|
|
80053a8: fa93 f1a3 rbit r1, r3
|
|
80053ac: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80053b0: f5a3 739e sub.w r3, r3, #316 @ 0x13c
|
|
80053b4: 6019 str r1, [r3, #0]
|
|
return result;
|
|
80053b6: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80053ba: f5a3 739e sub.w r3, r3, #316 @ 0x13c
|
|
80053be: 681b ldr r3, [r3, #0]
|
|
80053c0: fab3 f383 clz r3, r3
|
|
80053c4: b2db uxtb r3, r3
|
|
80053c6: f043 0360 orr.w r3, r3, #96 @ 0x60
|
|
80053ca: b2db uxtb r3, r3
|
|
80053cc: f003 031f and.w r3, r3, #31
|
|
80053d0: 2101 movs r1, #1
|
|
80053d2: fa01 f303 lsl.w r3, r1, r3
|
|
80053d6: 4013 ands r3, r2
|
|
80053d8: 2b00 cmp r3, #0
|
|
80053da: d197 bne.n 800530c <HAL_RCC_OscConfig+0x7ac>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
80053dc: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80053e0: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
80053e4: 681b ldr r3, [r3, #0]
|
|
80053e6: 681b ldr r3, [r3, #0]
|
|
80053e8: f003 0304 and.w r3, r3, #4
|
|
80053ec: 2b00 cmp r3, #0
|
|
80053ee: f000 81a1 beq.w 8005734 <HAL_RCC_OscConfig+0xbd4>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
80053f2: 2300 movs r3, #0
|
|
80053f4: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
80053f8: 4b26 ldr r3, [pc, #152] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
80053fa: 69db ldr r3, [r3, #28]
|
|
80053fc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005400: 2b00 cmp r3, #0
|
|
8005402: d116 bne.n 8005432 <HAL_RCC_OscConfig+0x8d2>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8005404: 4b23 ldr r3, [pc, #140] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
8005406: 69db ldr r3, [r3, #28]
|
|
8005408: 4a22 ldr r2, [pc, #136] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
800540a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800540e: 61d3 str r3, [r2, #28]
|
|
8005410: 4b20 ldr r3, [pc, #128] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
8005412: 69db ldr r3, [r3, #28]
|
|
8005414: f003 5280 and.w r2, r3, #268435456 @ 0x10000000
|
|
8005418: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800541c: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
|
|
8005420: 601a str r2, [r3, #0]
|
|
8005422: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005426: f5a3 73fc sub.w r3, r3, #504 @ 0x1f8
|
|
800542a: 681b ldr r3, [r3, #0]
|
|
pwrclkchanged = SET;
|
|
800542c: 2301 movs r3, #1
|
|
800542e: f887 31ff strb.w r3, [r7, #511] @ 0x1ff
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8005432: 4b1a ldr r3, [pc, #104] @ (800549c <HAL_RCC_OscConfig+0x93c>)
|
|
8005434: 681b ldr r3, [r3, #0]
|
|
8005436: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800543a: 2b00 cmp r3, #0
|
|
800543c: d11a bne.n 8005474 <HAL_RCC_OscConfig+0x914>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
800543e: 4b17 ldr r3, [pc, #92] @ (800549c <HAL_RCC_OscConfig+0x93c>)
|
|
8005440: 681b ldr r3, [r3, #0]
|
|
8005442: 4a16 ldr r2, [pc, #88] @ (800549c <HAL_RCC_OscConfig+0x93c>)
|
|
8005444: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8005448: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
800544a: f7fc ff53 bl 80022f4 <HAL_GetTick>
|
|
800544e: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8005452: e009 b.n 8005468 <HAL_RCC_OscConfig+0x908>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8005454: f7fc ff4e bl 80022f4 <HAL_GetTick>
|
|
8005458: 4602 mov r2, r0
|
|
800545a: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
800545e: 1ad3 subs r3, r2, r3
|
|
8005460: 2b64 cmp r3, #100 @ 0x64
|
|
8005462: d901 bls.n 8005468 <HAL_RCC_OscConfig+0x908>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005464: 2303 movs r3, #3
|
|
8005466: e3b1 b.n 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8005468: 4b0c ldr r3, [pc, #48] @ (800549c <HAL_RCC_OscConfig+0x93c>)
|
|
800546a: 681b ldr r3, [r3, #0]
|
|
800546c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005470: 2b00 cmp r3, #0
|
|
8005472: d0ef beq.n 8005454 <HAL_RCC_OscConfig+0x8f4>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8005474: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005478: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
800547c: 681b ldr r3, [r3, #0]
|
|
800547e: 68db ldr r3, [r3, #12]
|
|
8005480: 2b01 cmp r3, #1
|
|
8005482: d10d bne.n 80054a0 <HAL_RCC_OscConfig+0x940>
|
|
8005484: 4b03 ldr r3, [pc, #12] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
8005486: 6a1b ldr r3, [r3, #32]
|
|
8005488: 4a02 ldr r2, [pc, #8] @ (8005494 <HAL_RCC_OscConfig+0x934>)
|
|
800548a: f043 0301 orr.w r3, r3, #1
|
|
800548e: 6213 str r3, [r2, #32]
|
|
8005490: e03c b.n 800550c <HAL_RCC_OscConfig+0x9ac>
|
|
8005492: bf00 nop
|
|
8005494: 40021000 .word 0x40021000
|
|
8005498: 10908120 .word 0x10908120
|
|
800549c: 40007000 .word 0x40007000
|
|
80054a0: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80054a4: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
80054a8: 681b ldr r3, [r3, #0]
|
|
80054aa: 68db ldr r3, [r3, #12]
|
|
80054ac: 2b00 cmp r3, #0
|
|
80054ae: d10c bne.n 80054ca <HAL_RCC_OscConfig+0x96a>
|
|
80054b0: 4bc1 ldr r3, [pc, #772] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054b2: 6a1b ldr r3, [r3, #32]
|
|
80054b4: 4ac0 ldr r2, [pc, #768] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054b6: f023 0301 bic.w r3, r3, #1
|
|
80054ba: 6213 str r3, [r2, #32]
|
|
80054bc: 4bbe ldr r3, [pc, #760] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054be: 6a1b ldr r3, [r3, #32]
|
|
80054c0: 4abd ldr r2, [pc, #756] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054c2: f023 0304 bic.w r3, r3, #4
|
|
80054c6: 6213 str r3, [r2, #32]
|
|
80054c8: e020 b.n 800550c <HAL_RCC_OscConfig+0x9ac>
|
|
80054ca: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80054ce: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
80054d2: 681b ldr r3, [r3, #0]
|
|
80054d4: 68db ldr r3, [r3, #12]
|
|
80054d6: 2b05 cmp r3, #5
|
|
80054d8: d10c bne.n 80054f4 <HAL_RCC_OscConfig+0x994>
|
|
80054da: 4bb7 ldr r3, [pc, #732] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054dc: 6a1b ldr r3, [r3, #32]
|
|
80054de: 4ab6 ldr r2, [pc, #728] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054e0: f043 0304 orr.w r3, r3, #4
|
|
80054e4: 6213 str r3, [r2, #32]
|
|
80054e6: 4bb4 ldr r3, [pc, #720] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054e8: 6a1b ldr r3, [r3, #32]
|
|
80054ea: 4ab3 ldr r2, [pc, #716] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054ec: f043 0301 orr.w r3, r3, #1
|
|
80054f0: 6213 str r3, [r2, #32]
|
|
80054f2: e00b b.n 800550c <HAL_RCC_OscConfig+0x9ac>
|
|
80054f4: 4bb0 ldr r3, [pc, #704] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054f6: 6a1b ldr r3, [r3, #32]
|
|
80054f8: 4aaf ldr r2, [pc, #700] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80054fa: f023 0301 bic.w r3, r3, #1
|
|
80054fe: 6213 str r3, [r2, #32]
|
|
8005500: 4bad ldr r3, [pc, #692] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
8005502: 6a1b ldr r3, [r3, #32]
|
|
8005504: 4aac ldr r2, [pc, #688] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
8005506: f023 0304 bic.w r3, r3, #4
|
|
800550a: 6213 str r3, [r2, #32]
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
800550c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005510: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8005514: 681b ldr r3, [r3, #0]
|
|
8005516: 68db ldr r3, [r3, #12]
|
|
8005518: 2b00 cmp r3, #0
|
|
800551a: f000 8081 beq.w 8005620 <HAL_RCC_OscConfig+0xac0>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800551e: f7fc fee9 bl 80022f4 <HAL_GetTick>
|
|
8005522: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till LSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8005526: e00b b.n 8005540 <HAL_RCC_OscConfig+0x9e0>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005528: f7fc fee4 bl 80022f4 <HAL_GetTick>
|
|
800552c: 4602 mov r2, r0
|
|
800552e: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
8005532: 1ad3 subs r3, r2, r3
|
|
8005534: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005538: 4293 cmp r3, r2
|
|
800553a: d901 bls.n 8005540 <HAL_RCC_OscConfig+0x9e0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800553c: 2303 movs r3, #3
|
|
800553e: e345 b.n 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8005540: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005544: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
|
|
8005548: 2202 movs r2, #2
|
|
800554a: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800554c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005550: f5a3 73a0 sub.w r3, r3, #320 @ 0x140
|
|
8005554: 681b ldr r3, [r3, #0]
|
|
8005556: fa93 f2a3 rbit r2, r3
|
|
800555a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800555e: f5a3 73a2 sub.w r3, r3, #324 @ 0x144
|
|
8005562: 601a str r2, [r3, #0]
|
|
8005564: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005568: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
|
|
800556c: 2202 movs r2, #2
|
|
800556e: 601a str r2, [r3, #0]
|
|
8005570: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005574: f5a3 73a4 sub.w r3, r3, #328 @ 0x148
|
|
8005578: 681b ldr r3, [r3, #0]
|
|
800557a: fa93 f2a3 rbit r2, r3
|
|
800557e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005582: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
|
|
8005586: 601a str r2, [r3, #0]
|
|
return result;
|
|
8005588: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800558c: f5a3 73a6 sub.w r3, r3, #332 @ 0x14c
|
|
8005590: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8005592: fab3 f383 clz r3, r3
|
|
8005596: b2db uxtb r3, r3
|
|
8005598: 095b lsrs r3, r3, #5
|
|
800559a: b2db uxtb r3, r3
|
|
800559c: f043 0302 orr.w r3, r3, #2
|
|
80055a0: b2db uxtb r3, r3
|
|
80055a2: 2b02 cmp r3, #2
|
|
80055a4: d102 bne.n 80055ac <HAL_RCC_OscConfig+0xa4c>
|
|
80055a6: 4b84 ldr r3, [pc, #528] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80055a8: 6a1b ldr r3, [r3, #32]
|
|
80055aa: e013 b.n 80055d4 <HAL_RCC_OscConfig+0xa74>
|
|
80055ac: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80055b0: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
|
|
80055b4: 2202 movs r2, #2
|
|
80055b6: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80055b8: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80055bc: f5a3 73a8 sub.w r3, r3, #336 @ 0x150
|
|
80055c0: 681b ldr r3, [r3, #0]
|
|
80055c2: fa93 f2a3 rbit r2, r3
|
|
80055c6: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80055ca: f5a3 73aa sub.w r3, r3, #340 @ 0x154
|
|
80055ce: 601a str r2, [r3, #0]
|
|
80055d0: 4b79 ldr r3, [pc, #484] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80055d2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80055d4: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80055d8: f5a2 72ac sub.w r2, r2, #344 @ 0x158
|
|
80055dc: 2102 movs r1, #2
|
|
80055de: 6011 str r1, [r2, #0]
|
|
80055e0: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80055e4: f5a2 72ac sub.w r2, r2, #344 @ 0x158
|
|
80055e8: 6812 ldr r2, [r2, #0]
|
|
80055ea: fa92 f1a2 rbit r1, r2
|
|
80055ee: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80055f2: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
|
|
80055f6: 6011 str r1, [r2, #0]
|
|
return result;
|
|
80055f8: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80055fc: f5a2 72ae sub.w r2, r2, #348 @ 0x15c
|
|
8005600: 6812 ldr r2, [r2, #0]
|
|
8005602: fab2 f282 clz r2, r2
|
|
8005606: b2d2 uxtb r2, r2
|
|
8005608: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
800560c: b2d2 uxtb r2, r2
|
|
800560e: f002 021f and.w r2, r2, #31
|
|
8005612: 2101 movs r1, #1
|
|
8005614: fa01 f202 lsl.w r2, r1, r2
|
|
8005618: 4013 ands r3, r2
|
|
800561a: 2b00 cmp r3, #0
|
|
800561c: d084 beq.n 8005528 <HAL_RCC_OscConfig+0x9c8>
|
|
800561e: e07f b.n 8005720 <HAL_RCC_OscConfig+0xbc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8005620: f7fc fe68 bl 80022f4 <HAL_GetTick>
|
|
8005624: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8005628: e00b b.n 8005642 <HAL_RCC_OscConfig+0xae2>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
800562a: f7fc fe63 bl 80022f4 <HAL_GetTick>
|
|
800562e: 4602 mov r2, r0
|
|
8005630: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
8005634: 1ad3 subs r3, r2, r3
|
|
8005636: f241 3288 movw r2, #5000 @ 0x1388
|
|
800563a: 4293 cmp r3, r2
|
|
800563c: d901 bls.n 8005642 <HAL_RCC_OscConfig+0xae2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800563e: 2303 movs r3, #3
|
|
8005640: e2c4 b.n 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8005642: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005646: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
|
|
800564a: 2202 movs r2, #2
|
|
800564c: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800564e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005652: f5a3 73b0 sub.w r3, r3, #352 @ 0x160
|
|
8005656: 681b ldr r3, [r3, #0]
|
|
8005658: fa93 f2a3 rbit r2, r3
|
|
800565c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005660: f5a3 73b2 sub.w r3, r3, #356 @ 0x164
|
|
8005664: 601a str r2, [r3, #0]
|
|
8005666: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800566a: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
|
|
800566e: 2202 movs r2, #2
|
|
8005670: 601a str r2, [r3, #0]
|
|
8005672: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005676: f5a3 73b4 sub.w r3, r3, #360 @ 0x168
|
|
800567a: 681b ldr r3, [r3, #0]
|
|
800567c: fa93 f2a3 rbit r2, r3
|
|
8005680: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005684: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
|
|
8005688: 601a str r2, [r3, #0]
|
|
return result;
|
|
800568a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800568e: f5a3 73b6 sub.w r3, r3, #364 @ 0x16c
|
|
8005692: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8005694: fab3 f383 clz r3, r3
|
|
8005698: b2db uxtb r3, r3
|
|
800569a: 095b lsrs r3, r3, #5
|
|
800569c: b2db uxtb r3, r3
|
|
800569e: f043 0302 orr.w r3, r3, #2
|
|
80056a2: b2db uxtb r3, r3
|
|
80056a4: 2b02 cmp r3, #2
|
|
80056a6: d102 bne.n 80056ae <HAL_RCC_OscConfig+0xb4e>
|
|
80056a8: 4b43 ldr r3, [pc, #268] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80056aa: 6a1b ldr r3, [r3, #32]
|
|
80056ac: e013 b.n 80056d6 <HAL_RCC_OscConfig+0xb76>
|
|
80056ae: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80056b2: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
|
|
80056b6: 2202 movs r2, #2
|
|
80056b8: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80056ba: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80056be: f5a3 73b8 sub.w r3, r3, #368 @ 0x170
|
|
80056c2: 681b ldr r3, [r3, #0]
|
|
80056c4: fa93 f2a3 rbit r2, r3
|
|
80056c8: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80056cc: f5a3 73ba sub.w r3, r3, #372 @ 0x174
|
|
80056d0: 601a str r2, [r3, #0]
|
|
80056d2: 4b39 ldr r3, [pc, #228] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
80056d4: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80056d6: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80056da: f5a2 72bc sub.w r2, r2, #376 @ 0x178
|
|
80056de: 2102 movs r1, #2
|
|
80056e0: 6011 str r1, [r2, #0]
|
|
80056e2: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80056e6: f5a2 72bc sub.w r2, r2, #376 @ 0x178
|
|
80056ea: 6812 ldr r2, [r2, #0]
|
|
80056ec: fa92 f1a2 rbit r1, r2
|
|
80056f0: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80056f4: f5a2 72be sub.w r2, r2, #380 @ 0x17c
|
|
80056f8: 6011 str r1, [r2, #0]
|
|
return result;
|
|
80056fa: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80056fe: f5a2 72be sub.w r2, r2, #380 @ 0x17c
|
|
8005702: 6812 ldr r2, [r2, #0]
|
|
8005704: fab2 f282 clz r2, r2
|
|
8005708: b2d2 uxtb r2, r2
|
|
800570a: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
800570e: b2d2 uxtb r2, r2
|
|
8005710: f002 021f and.w r2, r2, #31
|
|
8005714: 2101 movs r1, #1
|
|
8005716: fa01 f202 lsl.w r2, r1, r2
|
|
800571a: 4013 ands r3, r2
|
|
800571c: 2b00 cmp r3, #0
|
|
800571e: d184 bne.n 800562a <HAL_RCC_OscConfig+0xaca>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if(pwrclkchanged == SET)
|
|
8005720: f897 31ff ldrb.w r3, [r7, #511] @ 0x1ff
|
|
8005724: 2b01 cmp r3, #1
|
|
8005726: d105 bne.n 8005734 <HAL_RCC_OscConfig+0xbd4>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8005728: 4b23 ldr r3, [pc, #140] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
800572a: 69db ldr r3, [r3, #28]
|
|
800572c: 4a22 ldr r2, [pc, #136] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
800572e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8005732: 61d3 str r3, [r2, #28]
|
|
}
|
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8005734: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005738: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
800573c: 681b ldr r3, [r3, #0]
|
|
800573e: 69db ldr r3, [r3, #28]
|
|
8005740: 2b00 cmp r3, #0
|
|
8005742: f000 8242 beq.w 8005bca <HAL_RCC_OscConfig+0x106a>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
8005746: 4b1c ldr r3, [pc, #112] @ (80057b8 <HAL_RCC_OscConfig+0xc58>)
|
|
8005748: 685b ldr r3, [r3, #4]
|
|
800574a: f003 030c and.w r3, r3, #12
|
|
800574e: 2b08 cmp r3, #8
|
|
8005750: f000 8213 beq.w 8005b7a <HAL_RCC_OscConfig+0x101a>
|
|
{
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8005754: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005758: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
800575c: 681b ldr r3, [r3, #0]
|
|
800575e: 69db ldr r3, [r3, #28]
|
|
8005760: 2b02 cmp r3, #2
|
|
8005762: f040 8162 bne.w 8005a2a <HAL_RCC_OscConfig+0xeca>
|
|
8005766: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800576a: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
|
|
800576e: f04f 7280 mov.w r2, #16777216 @ 0x1000000
|
|
8005772: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005774: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005778: f5a3 73c0 sub.w r3, r3, #384 @ 0x180
|
|
800577c: 681b ldr r3, [r3, #0]
|
|
800577e: fa93 f2a3 rbit r2, r3
|
|
8005782: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005786: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
|
|
800578a: 601a str r2, [r3, #0]
|
|
return result;
|
|
800578c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005790: f5a3 73c2 sub.w r3, r3, #388 @ 0x184
|
|
8005794: 681b ldr r3, [r3, #0]
|
|
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
|
|
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
|
|
#endif
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8005796: fab3 f383 clz r3, r3
|
|
800579a: b2db uxtb r3, r3
|
|
800579c: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
|
|
80057a0: f503 1384 add.w r3, r3, #1081344 @ 0x108000
|
|
80057a4: 009b lsls r3, r3, #2
|
|
80057a6: 461a mov r2, r3
|
|
80057a8: 2300 movs r3, #0
|
|
80057aa: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80057ac: f7fc fda2 bl 80022f4 <HAL_GetTick>
|
|
80057b0: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80057b4: e00c b.n 80057d0 <HAL_RCC_OscConfig+0xc70>
|
|
80057b6: bf00 nop
|
|
80057b8: 40021000 .word 0x40021000
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
80057bc: f7fc fd9a bl 80022f4 <HAL_GetTick>
|
|
80057c0: 4602 mov r2, r0
|
|
80057c2: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
80057c6: 1ad3 subs r3, r2, r3
|
|
80057c8: 2b02 cmp r3, #2
|
|
80057ca: d901 bls.n 80057d0 <HAL_RCC_OscConfig+0xc70>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80057cc: 2303 movs r3, #3
|
|
80057ce: e1fd b.n 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
80057d0: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80057d4: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
|
|
80057d8: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
80057dc: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80057de: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80057e2: f5a3 73c4 sub.w r3, r3, #392 @ 0x188
|
|
80057e6: 681b ldr r3, [r3, #0]
|
|
80057e8: fa93 f2a3 rbit r2, r3
|
|
80057ec: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80057f0: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
|
|
80057f4: 601a str r2, [r3, #0]
|
|
return result;
|
|
80057f6: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80057fa: f5a3 73c6 sub.w r3, r3, #396 @ 0x18c
|
|
80057fe: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8005800: fab3 f383 clz r3, r3
|
|
8005804: b2db uxtb r3, r3
|
|
8005806: 095b lsrs r3, r3, #5
|
|
8005808: b2db uxtb r3, r3
|
|
800580a: f043 0301 orr.w r3, r3, #1
|
|
800580e: b2db uxtb r3, r3
|
|
8005810: 2b01 cmp r3, #1
|
|
8005812: d102 bne.n 800581a <HAL_RCC_OscConfig+0xcba>
|
|
8005814: 4bb0 ldr r3, [pc, #704] @ (8005ad8 <HAL_RCC_OscConfig+0xf78>)
|
|
8005816: 681b ldr r3, [r3, #0]
|
|
8005818: e027 b.n 800586a <HAL_RCC_OscConfig+0xd0a>
|
|
800581a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800581e: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
|
|
8005822: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
8005826: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005828: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800582c: f5a3 73c8 sub.w r3, r3, #400 @ 0x190
|
|
8005830: 681b ldr r3, [r3, #0]
|
|
8005832: fa93 f2a3 rbit r2, r3
|
|
8005836: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800583a: f5a3 73ca sub.w r3, r3, #404 @ 0x194
|
|
800583e: 601a str r2, [r3, #0]
|
|
8005840: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005844: f5a3 73cc sub.w r3, r3, #408 @ 0x198
|
|
8005848: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
800584c: 601a str r2, [r3, #0]
|
|
800584e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005852: f5a3 73cc sub.w r3, r3, #408 @ 0x198
|
|
8005856: 681b ldr r3, [r3, #0]
|
|
8005858: fa93 f2a3 rbit r2, r3
|
|
800585c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005860: f5a3 73ce sub.w r3, r3, #412 @ 0x19c
|
|
8005864: 601a str r2, [r3, #0]
|
|
8005866: 4b9c ldr r3, [pc, #624] @ (8005ad8 <HAL_RCC_OscConfig+0xf78>)
|
|
8005868: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800586a: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
800586e: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
|
|
8005872: f04f 7100 mov.w r1, #33554432 @ 0x2000000
|
|
8005876: 6011 str r1, [r2, #0]
|
|
8005878: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
800587c: f5a2 72d0 sub.w r2, r2, #416 @ 0x1a0
|
|
8005880: 6812 ldr r2, [r2, #0]
|
|
8005882: fa92 f1a2 rbit r1, r2
|
|
8005886: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
800588a: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
|
|
800588e: 6011 str r1, [r2, #0]
|
|
return result;
|
|
8005890: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
8005894: f5a2 72d2 sub.w r2, r2, #420 @ 0x1a4
|
|
8005898: 6812 ldr r2, [r2, #0]
|
|
800589a: fab2 f282 clz r2, r2
|
|
800589e: b2d2 uxtb r2, r2
|
|
80058a0: f042 0220 orr.w r2, r2, #32
|
|
80058a4: b2d2 uxtb r2, r2
|
|
80058a6: f002 021f and.w r2, r2, #31
|
|
80058aa: 2101 movs r1, #1
|
|
80058ac: fa01 f202 lsl.w r2, r1, r2
|
|
80058b0: 4013 ands r3, r2
|
|
80058b2: 2b00 cmp r3, #0
|
|
80058b4: d182 bne.n 80057bc <HAL_RCC_OscConfig+0xc5c>
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
RCC_OscInitStruct->PLL.PREDIV,
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
#else
|
|
/* Configure the main PLL clock source and multiplication factor. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
80058b6: 4b88 ldr r3, [pc, #544] @ (8005ad8 <HAL_RCC_OscConfig+0xf78>)
|
|
80058b8: 685b ldr r3, [r3, #4]
|
|
80058ba: f423 1274 bic.w r2, r3, #3997696 @ 0x3d0000
|
|
80058be: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80058c2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
80058c6: 681b ldr r3, [r3, #0]
|
|
80058c8: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
80058ca: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80058ce: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
80058d2: 681b ldr r3, [r3, #0]
|
|
80058d4: 6a1b ldr r3, [r3, #32]
|
|
80058d6: 430b orrs r3, r1
|
|
80058d8: 497f ldr r1, [pc, #508] @ (8005ad8 <HAL_RCC_OscConfig+0xf78>)
|
|
80058da: 4313 orrs r3, r2
|
|
80058dc: 604b str r3, [r1, #4]
|
|
80058de: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80058e2: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
|
|
80058e6: f04f 7280 mov.w r2, #16777216 @ 0x1000000
|
|
80058ea: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80058ec: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80058f0: f5a3 73d4 sub.w r3, r3, #424 @ 0x1a8
|
|
80058f4: 681b ldr r3, [r3, #0]
|
|
80058f6: fa93 f2a3 rbit r2, r3
|
|
80058fa: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80058fe: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
|
|
8005902: 601a str r2, [r3, #0]
|
|
return result;
|
|
8005904: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005908: f5a3 73d6 sub.w r3, r3, #428 @ 0x1ac
|
|
800590c: 681b ldr r3, [r3, #0]
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
800590e: fab3 f383 clz r3, r3
|
|
8005912: b2db uxtb r3, r3
|
|
8005914: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
|
|
8005918: f503 1384 add.w r3, r3, #1081344 @ 0x108000
|
|
800591c: 009b lsls r3, r3, #2
|
|
800591e: 461a mov r2, r3
|
|
8005920: 2301 movs r3, #1
|
|
8005922: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8005924: f7fc fce6 bl 80022f4 <HAL_GetTick>
|
|
8005928: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till PLL is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
800592c: e009 b.n 8005942 <HAL_RCC_OscConfig+0xde2>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
800592e: f7fc fce1 bl 80022f4 <HAL_GetTick>
|
|
8005932: 4602 mov r2, r0
|
|
8005934: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
8005938: 1ad3 subs r3, r2, r3
|
|
800593a: 2b02 cmp r3, #2
|
|
800593c: d901 bls.n 8005942 <HAL_RCC_OscConfig+0xde2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800593e: 2303 movs r3, #3
|
|
8005940: e144 b.n 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8005942: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005946: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
|
|
800594a: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
800594e: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005950: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005954: f5a3 73d8 sub.w r3, r3, #432 @ 0x1b0
|
|
8005958: 681b ldr r3, [r3, #0]
|
|
800595a: fa93 f2a3 rbit r2, r3
|
|
800595e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005962: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
|
|
8005966: 601a str r2, [r3, #0]
|
|
return result;
|
|
8005968: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800596c: f5a3 73da sub.w r3, r3, #436 @ 0x1b4
|
|
8005970: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8005972: fab3 f383 clz r3, r3
|
|
8005976: b2db uxtb r3, r3
|
|
8005978: 095b lsrs r3, r3, #5
|
|
800597a: b2db uxtb r3, r3
|
|
800597c: f043 0301 orr.w r3, r3, #1
|
|
8005980: b2db uxtb r3, r3
|
|
8005982: 2b01 cmp r3, #1
|
|
8005984: d102 bne.n 800598c <HAL_RCC_OscConfig+0xe2c>
|
|
8005986: 4b54 ldr r3, [pc, #336] @ (8005ad8 <HAL_RCC_OscConfig+0xf78>)
|
|
8005988: 681b ldr r3, [r3, #0]
|
|
800598a: e027 b.n 80059dc <HAL_RCC_OscConfig+0xe7c>
|
|
800598c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005990: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
|
|
8005994: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
8005998: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800599a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
800599e: f5a3 73dc sub.w r3, r3, #440 @ 0x1b8
|
|
80059a2: 681b ldr r3, [r3, #0]
|
|
80059a4: fa93 f2a3 rbit r2, r3
|
|
80059a8: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80059ac: f5a3 73de sub.w r3, r3, #444 @ 0x1bc
|
|
80059b0: 601a str r2, [r3, #0]
|
|
80059b2: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80059b6: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
|
|
80059ba: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
80059be: 601a str r2, [r3, #0]
|
|
80059c0: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80059c4: f5a3 73e0 sub.w r3, r3, #448 @ 0x1c0
|
|
80059c8: 681b ldr r3, [r3, #0]
|
|
80059ca: fa93 f2a3 rbit r2, r3
|
|
80059ce: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
80059d2: f5a3 73e2 sub.w r3, r3, #452 @ 0x1c4
|
|
80059d6: 601a str r2, [r3, #0]
|
|
80059d8: 4b3f ldr r3, [pc, #252] @ (8005ad8 <HAL_RCC_OscConfig+0xf78>)
|
|
80059da: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80059dc: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80059e0: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
|
|
80059e4: f04f 7100 mov.w r1, #33554432 @ 0x2000000
|
|
80059e8: 6011 str r1, [r2, #0]
|
|
80059ea: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80059ee: f5a2 72e4 sub.w r2, r2, #456 @ 0x1c8
|
|
80059f2: 6812 ldr r2, [r2, #0]
|
|
80059f4: fa92 f1a2 rbit r1, r2
|
|
80059f8: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
80059fc: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
|
|
8005a00: 6011 str r1, [r2, #0]
|
|
return result;
|
|
8005a02: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
8005a06: f5a2 72e6 sub.w r2, r2, #460 @ 0x1cc
|
|
8005a0a: 6812 ldr r2, [r2, #0]
|
|
8005a0c: fab2 f282 clz r2, r2
|
|
8005a10: b2d2 uxtb r2, r2
|
|
8005a12: f042 0220 orr.w r2, r2, #32
|
|
8005a16: b2d2 uxtb r2, r2
|
|
8005a18: f002 021f and.w r2, r2, #31
|
|
8005a1c: 2101 movs r1, #1
|
|
8005a1e: fa01 f202 lsl.w r2, r1, r2
|
|
8005a22: 4013 ands r3, r2
|
|
8005a24: 2b00 cmp r3, #0
|
|
8005a26: d082 beq.n 800592e <HAL_RCC_OscConfig+0xdce>
|
|
8005a28: e0cf b.n 8005bca <HAL_RCC_OscConfig+0x106a>
|
|
8005a2a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005a2e: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
|
|
8005a32: f04f 7280 mov.w r2, #16777216 @ 0x1000000
|
|
8005a36: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005a38: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005a3c: f5a3 73e8 sub.w r3, r3, #464 @ 0x1d0
|
|
8005a40: 681b ldr r3, [r3, #0]
|
|
8005a42: fa93 f2a3 rbit r2, r3
|
|
8005a46: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005a4a: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
|
|
8005a4e: 601a str r2, [r3, #0]
|
|
return result;
|
|
8005a50: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005a54: f5a3 73ea sub.w r3, r3, #468 @ 0x1d4
|
|
8005a58: 681b ldr r3, [r3, #0]
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8005a5a: fab3 f383 clz r3, r3
|
|
8005a5e: b2db uxtb r3, r3
|
|
8005a60: f103 5384 add.w r3, r3, #276824064 @ 0x10800000
|
|
8005a64: f503 1384 add.w r3, r3, #1081344 @ 0x108000
|
|
8005a68: 009b lsls r3, r3, #2
|
|
8005a6a: 461a mov r2, r3
|
|
8005a6c: 2300 movs r3, #0
|
|
8005a6e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8005a70: f7fc fc40 bl 80022f4 <HAL_GetTick>
|
|
8005a74: f8c7 01f8 str.w r0, [r7, #504] @ 0x1f8
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8005a78: e009 b.n 8005a8e <HAL_RCC_OscConfig+0xf2e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
8005a7a: f7fc fc3b bl 80022f4 <HAL_GetTick>
|
|
8005a7e: 4602 mov r2, r0
|
|
8005a80: f8d7 31f8 ldr.w r3, [r7, #504] @ 0x1f8
|
|
8005a84: 1ad3 subs r3, r2, r3
|
|
8005a86: 2b02 cmp r3, #2
|
|
8005a88: d901 bls.n 8005a8e <HAL_RCC_OscConfig+0xf2e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005a8a: 2303 movs r3, #3
|
|
8005a8c: e09e b.n 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
8005a8e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005a92: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
|
|
8005a96: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
8005a9a: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005a9c: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005aa0: f5a3 73ec sub.w r3, r3, #472 @ 0x1d8
|
|
8005aa4: 681b ldr r3, [r3, #0]
|
|
8005aa6: fa93 f2a3 rbit r2, r3
|
|
8005aaa: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005aae: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
|
|
8005ab2: 601a str r2, [r3, #0]
|
|
return result;
|
|
8005ab4: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005ab8: f5a3 73ee sub.w r3, r3, #476 @ 0x1dc
|
|
8005abc: 681b ldr r3, [r3, #0]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8005abe: fab3 f383 clz r3, r3
|
|
8005ac2: b2db uxtb r3, r3
|
|
8005ac4: 095b lsrs r3, r3, #5
|
|
8005ac6: b2db uxtb r3, r3
|
|
8005ac8: f043 0301 orr.w r3, r3, #1
|
|
8005acc: b2db uxtb r3, r3
|
|
8005ace: 2b01 cmp r3, #1
|
|
8005ad0: d104 bne.n 8005adc <HAL_RCC_OscConfig+0xf7c>
|
|
8005ad2: 4b01 ldr r3, [pc, #4] @ (8005ad8 <HAL_RCC_OscConfig+0xf78>)
|
|
8005ad4: 681b ldr r3, [r3, #0]
|
|
8005ad6: e029 b.n 8005b2c <HAL_RCC_OscConfig+0xfcc>
|
|
8005ad8: 40021000 .word 0x40021000
|
|
8005adc: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005ae0: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
|
|
8005ae4: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
8005ae8: 601a str r2, [r3, #0]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005aea: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005aee: f5a3 73f0 sub.w r3, r3, #480 @ 0x1e0
|
|
8005af2: 681b ldr r3, [r3, #0]
|
|
8005af4: fa93 f2a3 rbit r2, r3
|
|
8005af8: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005afc: f5a3 73f2 sub.w r3, r3, #484 @ 0x1e4
|
|
8005b00: 601a str r2, [r3, #0]
|
|
8005b02: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005b06: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
|
|
8005b0a: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
8005b0e: 601a str r2, [r3, #0]
|
|
8005b10: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005b14: f5a3 73f4 sub.w r3, r3, #488 @ 0x1e8
|
|
8005b18: 681b ldr r3, [r3, #0]
|
|
8005b1a: fa93 f2a3 rbit r2, r3
|
|
8005b1e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005b22: f5a3 73f6 sub.w r3, r3, #492 @ 0x1ec
|
|
8005b26: 601a str r2, [r3, #0]
|
|
8005b28: 4b2b ldr r3, [pc, #172] @ (8005bd8 <HAL_RCC_OscConfig+0x1078>)
|
|
8005b2a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005b2c: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
8005b30: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
|
|
8005b34: f04f 7100 mov.w r1, #33554432 @ 0x2000000
|
|
8005b38: 6011 str r1, [r2, #0]
|
|
8005b3a: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
8005b3e: f5a2 72f8 sub.w r2, r2, #496 @ 0x1f0
|
|
8005b42: 6812 ldr r2, [r2, #0]
|
|
8005b44: fa92 f1a2 rbit r1, r2
|
|
8005b48: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
8005b4c: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
|
|
8005b50: 6011 str r1, [r2, #0]
|
|
return result;
|
|
8005b52: f507 7200 add.w r2, r7, #512 @ 0x200
|
|
8005b56: f5a2 72fa sub.w r2, r2, #500 @ 0x1f4
|
|
8005b5a: 6812 ldr r2, [r2, #0]
|
|
8005b5c: fab2 f282 clz r2, r2
|
|
8005b60: b2d2 uxtb r2, r2
|
|
8005b62: f042 0220 orr.w r2, r2, #32
|
|
8005b66: b2d2 uxtb r2, r2
|
|
8005b68: f002 021f and.w r2, r2, #31
|
|
8005b6c: 2101 movs r1, #1
|
|
8005b6e: fa01 f202 lsl.w r2, r1, r2
|
|
8005b72: 4013 ands r3, r2
|
|
8005b74: 2b00 cmp r3, #0
|
|
8005b76: d180 bne.n 8005a7a <HAL_RCC_OscConfig+0xf1a>
|
|
8005b78: e027 b.n 8005bca <HAL_RCC_OscConfig+0x106a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8005b7a: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005b7e: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8005b82: 681b ldr r3, [r3, #0]
|
|
8005b84: 69db ldr r3, [r3, #28]
|
|
8005b86: 2b01 cmp r3, #1
|
|
8005b88: d101 bne.n 8005b8e <HAL_RCC_OscConfig+0x102e>
|
|
{
|
|
return HAL_ERROR;
|
|
8005b8a: 2301 movs r3, #1
|
|
8005b8c: e01e b.n 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->CFGR;
|
|
8005b8e: 4b12 ldr r3, [pc, #72] @ (8005bd8 <HAL_RCC_OscConfig+0x1078>)
|
|
8005b90: 685b ldr r3, [r3, #4]
|
|
8005b92: f8c7 31f4 str.w r3, [r7, #500] @ 0x1f4
|
|
pll_config2 = RCC->CFGR2;
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
|
|
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
|
|
#else
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8005b96: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
|
|
8005b9a: f403 3280 and.w r2, r3, #65536 @ 0x10000
|
|
8005b9e: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005ba2: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8005ba6: 681b ldr r3, [r3, #0]
|
|
8005ba8: 6a1b ldr r3, [r3, #32]
|
|
8005baa: 429a cmp r2, r3
|
|
8005bac: d10b bne.n 8005bc6 <HAL_RCC_OscConfig+0x1066>
|
|
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
|
|
8005bae: f8d7 31f4 ldr.w r3, [r7, #500] @ 0x1f4
|
|
8005bb2: f403 1270 and.w r2, r3, #3932160 @ 0x3c0000
|
|
8005bb6: f507 7300 add.w r3, r7, #512 @ 0x200
|
|
8005bba: f5a3 73fe sub.w r3, r3, #508 @ 0x1fc
|
|
8005bbe: 681b ldr r3, [r3, #0]
|
|
8005bc0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8005bc2: 429a cmp r2, r3
|
|
8005bc4: d001 beq.n 8005bca <HAL_RCC_OscConfig+0x106a>
|
|
#endif
|
|
{
|
|
return HAL_ERROR;
|
|
8005bc6: 2301 movs r3, #1
|
|
8005bc8: e000 b.n 8005bcc <HAL_RCC_OscConfig+0x106c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8005bca: 2300 movs r3, #0
|
|
}
|
|
8005bcc: 4618 mov r0, r3
|
|
8005bce: f507 7700 add.w r7, r7, #512 @ 0x200
|
|
8005bd2: 46bd mov sp, r7
|
|
8005bd4: bd80 pop {r7, pc}
|
|
8005bd6: bf00 nop
|
|
8005bd8: 40021000 .word 0x40021000
|
|
|
|
08005bdc <HAL_RCC_ClockConfig>:
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8005bdc: b580 push {r7, lr}
|
|
8005bde: b09e sub sp, #120 @ 0x78
|
|
8005be0: af00 add r7, sp, #0
|
|
8005be2: 6078 str r0, [r7, #4]
|
|
8005be4: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart = 0U;
|
|
8005be6: 2300 movs r3, #0
|
|
8005be8: 677b str r3, [r7, #116] @ 0x74
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
8005bea: 687b ldr r3, [r7, #4]
|
|
8005bec: 2b00 cmp r3, #0
|
|
8005bee: d101 bne.n 8005bf4 <HAL_RCC_ClockConfig+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
8005bf0: 2301 movs r3, #1
|
|
8005bf2: e162 b.n 8005eba <HAL_RCC_ClockConfig+0x2de>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8005bf4: 4b90 ldr r3, [pc, #576] @ (8005e38 <HAL_RCC_ClockConfig+0x25c>)
|
|
8005bf6: 681b ldr r3, [r3, #0]
|
|
8005bf8: f003 0307 and.w r3, r3, #7
|
|
8005bfc: 683a ldr r2, [r7, #0]
|
|
8005bfe: 429a cmp r2, r3
|
|
8005c00: d910 bls.n 8005c24 <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8005c02: 4b8d ldr r3, [pc, #564] @ (8005e38 <HAL_RCC_ClockConfig+0x25c>)
|
|
8005c04: 681b ldr r3, [r3, #0]
|
|
8005c06: f023 0207 bic.w r2, r3, #7
|
|
8005c0a: 498b ldr r1, [pc, #556] @ (8005e38 <HAL_RCC_ClockConfig+0x25c>)
|
|
8005c0c: 683b ldr r3, [r7, #0]
|
|
8005c0e: 4313 orrs r3, r2
|
|
8005c10: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8005c12: 4b89 ldr r3, [pc, #548] @ (8005e38 <HAL_RCC_ClockConfig+0x25c>)
|
|
8005c14: 681b ldr r3, [r3, #0]
|
|
8005c16: f003 0307 and.w r3, r3, #7
|
|
8005c1a: 683a ldr r2, [r7, #0]
|
|
8005c1c: 429a cmp r2, r3
|
|
8005c1e: d001 beq.n 8005c24 <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
return HAL_ERROR;
|
|
8005c20: 2301 movs r3, #1
|
|
8005c22: e14a b.n 8005eba <HAL_RCC_ClockConfig+0x2de>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8005c24: 687b ldr r3, [r7, #4]
|
|
8005c26: 681b ldr r3, [r3, #0]
|
|
8005c28: f003 0302 and.w r3, r3, #2
|
|
8005c2c: 2b00 cmp r3, #0
|
|
8005c2e: d008 beq.n 8005c42 <HAL_RCC_ClockConfig+0x66>
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8005c30: 4b82 ldr r3, [pc, #520] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005c32: 685b ldr r3, [r3, #4]
|
|
8005c34: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8005c38: 687b ldr r3, [r7, #4]
|
|
8005c3a: 689b ldr r3, [r3, #8]
|
|
8005c3c: 497f ldr r1, [pc, #508] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005c3e: 4313 orrs r3, r2
|
|
8005c40: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8005c42: 687b ldr r3, [r7, #4]
|
|
8005c44: 681b ldr r3, [r3, #0]
|
|
8005c46: f003 0301 and.w r3, r3, #1
|
|
8005c4a: 2b00 cmp r3, #0
|
|
8005c4c: f000 80dc beq.w 8005e08 <HAL_RCC_ClockConfig+0x22c>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8005c50: 687b ldr r3, [r7, #4]
|
|
8005c52: 685b ldr r3, [r3, #4]
|
|
8005c54: 2b01 cmp r3, #1
|
|
8005c56: d13c bne.n 8005cd2 <HAL_RCC_ClockConfig+0xf6>
|
|
8005c58: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8005c5c: 673b str r3, [r7, #112] @ 0x70
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005c5e: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8005c60: fa93 f3a3 rbit r3, r3
|
|
8005c64: 66fb str r3, [r7, #108] @ 0x6c
|
|
return result;
|
|
8005c66: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8005c68: fab3 f383 clz r3, r3
|
|
8005c6c: b2db uxtb r3, r3
|
|
8005c6e: 095b lsrs r3, r3, #5
|
|
8005c70: b2db uxtb r3, r3
|
|
8005c72: f043 0301 orr.w r3, r3, #1
|
|
8005c76: b2db uxtb r3, r3
|
|
8005c78: 2b01 cmp r3, #1
|
|
8005c7a: d102 bne.n 8005c82 <HAL_RCC_ClockConfig+0xa6>
|
|
8005c7c: 4b6f ldr r3, [pc, #444] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005c7e: 681b ldr r3, [r3, #0]
|
|
8005c80: e00f b.n 8005ca2 <HAL_RCC_ClockConfig+0xc6>
|
|
8005c82: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8005c86: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005c88: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8005c8a: fa93 f3a3 rbit r3, r3
|
|
8005c8e: 667b str r3, [r7, #100] @ 0x64
|
|
8005c90: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
8005c94: 663b str r3, [r7, #96] @ 0x60
|
|
8005c96: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8005c98: fa93 f3a3 rbit r3, r3
|
|
8005c9c: 65fb str r3, [r7, #92] @ 0x5c
|
|
8005c9e: 4b67 ldr r3, [pc, #412] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005ca0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005ca2: f44f 3200 mov.w r2, #131072 @ 0x20000
|
|
8005ca6: 65ba str r2, [r7, #88] @ 0x58
|
|
8005ca8: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8005caa: fa92 f2a2 rbit r2, r2
|
|
8005cae: 657a str r2, [r7, #84] @ 0x54
|
|
return result;
|
|
8005cb0: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8005cb2: fab2 f282 clz r2, r2
|
|
8005cb6: b2d2 uxtb r2, r2
|
|
8005cb8: f042 0220 orr.w r2, r2, #32
|
|
8005cbc: b2d2 uxtb r2, r2
|
|
8005cbe: f002 021f and.w r2, r2, #31
|
|
8005cc2: 2101 movs r1, #1
|
|
8005cc4: fa01 f202 lsl.w r2, r1, r2
|
|
8005cc8: 4013 ands r3, r2
|
|
8005cca: 2b00 cmp r3, #0
|
|
8005ccc: d17b bne.n 8005dc6 <HAL_RCC_ClockConfig+0x1ea>
|
|
{
|
|
return HAL_ERROR;
|
|
8005cce: 2301 movs r3, #1
|
|
8005cd0: e0f3 b.n 8005eba <HAL_RCC_ClockConfig+0x2de>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8005cd2: 687b ldr r3, [r7, #4]
|
|
8005cd4: 685b ldr r3, [r3, #4]
|
|
8005cd6: 2b02 cmp r3, #2
|
|
8005cd8: d13c bne.n 8005d54 <HAL_RCC_ClockConfig+0x178>
|
|
8005cda: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8005cde: 653b str r3, [r7, #80] @ 0x50
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005ce0: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8005ce2: fa93 f3a3 rbit r3, r3
|
|
8005ce6: 64fb str r3, [r7, #76] @ 0x4c
|
|
return result;
|
|
8005ce8: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8005cea: fab3 f383 clz r3, r3
|
|
8005cee: b2db uxtb r3, r3
|
|
8005cf0: 095b lsrs r3, r3, #5
|
|
8005cf2: b2db uxtb r3, r3
|
|
8005cf4: f043 0301 orr.w r3, r3, #1
|
|
8005cf8: b2db uxtb r3, r3
|
|
8005cfa: 2b01 cmp r3, #1
|
|
8005cfc: d102 bne.n 8005d04 <HAL_RCC_ClockConfig+0x128>
|
|
8005cfe: 4b4f ldr r3, [pc, #316] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005d00: 681b ldr r3, [r3, #0]
|
|
8005d02: e00f b.n 8005d24 <HAL_RCC_ClockConfig+0x148>
|
|
8005d04: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8005d08: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005d0a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8005d0c: fa93 f3a3 rbit r3, r3
|
|
8005d10: 647b str r3, [r7, #68] @ 0x44
|
|
8005d12: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8005d16: 643b str r3, [r7, #64] @ 0x40
|
|
8005d18: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8005d1a: fa93 f3a3 rbit r3, r3
|
|
8005d1e: 63fb str r3, [r7, #60] @ 0x3c
|
|
8005d20: 4b46 ldr r3, [pc, #280] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005d22: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005d24: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
8005d28: 63ba str r2, [r7, #56] @ 0x38
|
|
8005d2a: 6bba ldr r2, [r7, #56] @ 0x38
|
|
8005d2c: fa92 f2a2 rbit r2, r2
|
|
8005d30: 637a str r2, [r7, #52] @ 0x34
|
|
return result;
|
|
8005d32: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
8005d34: fab2 f282 clz r2, r2
|
|
8005d38: b2d2 uxtb r2, r2
|
|
8005d3a: f042 0220 orr.w r2, r2, #32
|
|
8005d3e: b2d2 uxtb r2, r2
|
|
8005d40: f002 021f and.w r2, r2, #31
|
|
8005d44: 2101 movs r1, #1
|
|
8005d46: fa01 f202 lsl.w r2, r1, r2
|
|
8005d4a: 4013 ands r3, r2
|
|
8005d4c: 2b00 cmp r3, #0
|
|
8005d4e: d13a bne.n 8005dc6 <HAL_RCC_ClockConfig+0x1ea>
|
|
{
|
|
return HAL_ERROR;
|
|
8005d50: 2301 movs r3, #1
|
|
8005d52: e0b2 b.n 8005eba <HAL_RCC_ClockConfig+0x2de>
|
|
8005d54: 2302 movs r3, #2
|
|
8005d56: 633b str r3, [r7, #48] @ 0x30
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005d58: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8005d5a: fa93 f3a3 rbit r3, r3
|
|
8005d5e: 62fb str r3, [r7, #44] @ 0x2c
|
|
return result;
|
|
8005d60: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8005d62: fab3 f383 clz r3, r3
|
|
8005d66: b2db uxtb r3, r3
|
|
8005d68: 095b lsrs r3, r3, #5
|
|
8005d6a: b2db uxtb r3, r3
|
|
8005d6c: f043 0301 orr.w r3, r3, #1
|
|
8005d70: b2db uxtb r3, r3
|
|
8005d72: 2b01 cmp r3, #1
|
|
8005d74: d102 bne.n 8005d7c <HAL_RCC_ClockConfig+0x1a0>
|
|
8005d76: 4b31 ldr r3, [pc, #196] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005d78: 681b ldr r3, [r3, #0]
|
|
8005d7a: e00d b.n 8005d98 <HAL_RCC_ClockConfig+0x1bc>
|
|
8005d7c: 2302 movs r3, #2
|
|
8005d7e: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005d80: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8005d82: fa93 f3a3 rbit r3, r3
|
|
8005d86: 627b str r3, [r7, #36] @ 0x24
|
|
8005d88: 2302 movs r3, #2
|
|
8005d8a: 623b str r3, [r7, #32]
|
|
8005d8c: 6a3b ldr r3, [r7, #32]
|
|
8005d8e: fa93 f3a3 rbit r3, r3
|
|
8005d92: 61fb str r3, [r7, #28]
|
|
8005d94: 4b29 ldr r3, [pc, #164] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005d96: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005d98: 2202 movs r2, #2
|
|
8005d9a: 61ba str r2, [r7, #24]
|
|
8005d9c: 69ba ldr r2, [r7, #24]
|
|
8005d9e: fa92 f2a2 rbit r2, r2
|
|
8005da2: 617a str r2, [r7, #20]
|
|
return result;
|
|
8005da4: 697a ldr r2, [r7, #20]
|
|
8005da6: fab2 f282 clz r2, r2
|
|
8005daa: b2d2 uxtb r2, r2
|
|
8005dac: f042 0220 orr.w r2, r2, #32
|
|
8005db0: b2d2 uxtb r2, r2
|
|
8005db2: f002 021f and.w r2, r2, #31
|
|
8005db6: 2101 movs r1, #1
|
|
8005db8: fa01 f202 lsl.w r2, r1, r2
|
|
8005dbc: 4013 ands r3, r2
|
|
8005dbe: 2b00 cmp r3, #0
|
|
8005dc0: d101 bne.n 8005dc6 <HAL_RCC_ClockConfig+0x1ea>
|
|
{
|
|
return HAL_ERROR;
|
|
8005dc2: 2301 movs r3, #1
|
|
8005dc4: e079 b.n 8005eba <HAL_RCC_ClockConfig+0x2de>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8005dc6: 4b1d ldr r3, [pc, #116] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005dc8: 685b ldr r3, [r3, #4]
|
|
8005dca: f023 0203 bic.w r2, r3, #3
|
|
8005dce: 687b ldr r3, [r7, #4]
|
|
8005dd0: 685b ldr r3, [r3, #4]
|
|
8005dd2: 491a ldr r1, [pc, #104] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005dd4: 4313 orrs r3, r2
|
|
8005dd6: 604b str r3, [r1, #4]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8005dd8: f7fc fa8c bl 80022f4 <HAL_GetTick>
|
|
8005ddc: 6778 str r0, [r7, #116] @ 0x74
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8005dde: e00a b.n 8005df6 <HAL_RCC_ClockConfig+0x21a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8005de0: f7fc fa88 bl 80022f4 <HAL_GetTick>
|
|
8005de4: 4602 mov r2, r0
|
|
8005de6: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8005de8: 1ad3 subs r3, r2, r3
|
|
8005dea: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005dee: 4293 cmp r3, r2
|
|
8005df0: d901 bls.n 8005df6 <HAL_RCC_ClockConfig+0x21a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005df2: 2303 movs r3, #3
|
|
8005df4: e061 b.n 8005eba <HAL_RCC_ClockConfig+0x2de>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8005df6: 4b11 ldr r3, [pc, #68] @ (8005e3c <HAL_RCC_ClockConfig+0x260>)
|
|
8005df8: 685b ldr r3, [r3, #4]
|
|
8005dfa: f003 020c and.w r2, r3, #12
|
|
8005dfe: 687b ldr r3, [r7, #4]
|
|
8005e00: 685b ldr r3, [r3, #4]
|
|
8005e02: 009b lsls r3, r3, #2
|
|
8005e04: 429a cmp r2, r3
|
|
8005e06: d1eb bne.n 8005de0 <HAL_RCC_ClockConfig+0x204>
|
|
}
|
|
}
|
|
}
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8005e08: 4b0b ldr r3, [pc, #44] @ (8005e38 <HAL_RCC_ClockConfig+0x25c>)
|
|
8005e0a: 681b ldr r3, [r3, #0]
|
|
8005e0c: f003 0307 and.w r3, r3, #7
|
|
8005e10: 683a ldr r2, [r7, #0]
|
|
8005e12: 429a cmp r2, r3
|
|
8005e14: d214 bcs.n 8005e40 <HAL_RCC_ClockConfig+0x264>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8005e16: 4b08 ldr r3, [pc, #32] @ (8005e38 <HAL_RCC_ClockConfig+0x25c>)
|
|
8005e18: 681b ldr r3, [r3, #0]
|
|
8005e1a: f023 0207 bic.w r2, r3, #7
|
|
8005e1e: 4906 ldr r1, [pc, #24] @ (8005e38 <HAL_RCC_ClockConfig+0x25c>)
|
|
8005e20: 683b ldr r3, [r7, #0]
|
|
8005e22: 4313 orrs r3, r2
|
|
8005e24: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8005e26: 4b04 ldr r3, [pc, #16] @ (8005e38 <HAL_RCC_ClockConfig+0x25c>)
|
|
8005e28: 681b ldr r3, [r3, #0]
|
|
8005e2a: f003 0307 and.w r3, r3, #7
|
|
8005e2e: 683a ldr r2, [r7, #0]
|
|
8005e30: 429a cmp r2, r3
|
|
8005e32: d005 beq.n 8005e40 <HAL_RCC_ClockConfig+0x264>
|
|
{
|
|
return HAL_ERROR;
|
|
8005e34: 2301 movs r3, #1
|
|
8005e36: e040 b.n 8005eba <HAL_RCC_ClockConfig+0x2de>
|
|
8005e38: 40022000 .word 0x40022000
|
|
8005e3c: 40021000 .word 0x40021000
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8005e40: 687b ldr r3, [r7, #4]
|
|
8005e42: 681b ldr r3, [r3, #0]
|
|
8005e44: f003 0304 and.w r3, r3, #4
|
|
8005e48: 2b00 cmp r3, #0
|
|
8005e4a: d008 beq.n 8005e5e <HAL_RCC_ClockConfig+0x282>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8005e4c: 4b1d ldr r3, [pc, #116] @ (8005ec4 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8005e4e: 685b ldr r3, [r3, #4]
|
|
8005e50: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
8005e54: 687b ldr r3, [r7, #4]
|
|
8005e56: 68db ldr r3, [r3, #12]
|
|
8005e58: 491a ldr r1, [pc, #104] @ (8005ec4 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8005e5a: 4313 orrs r3, r2
|
|
8005e5c: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8005e5e: 687b ldr r3, [r7, #4]
|
|
8005e60: 681b ldr r3, [r3, #0]
|
|
8005e62: f003 0308 and.w r3, r3, #8
|
|
8005e66: 2b00 cmp r3, #0
|
|
8005e68: d009 beq.n 8005e7e <HAL_RCC_ClockConfig+0x2a2>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8005e6a: 4b16 ldr r3, [pc, #88] @ (8005ec4 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8005e6c: 685b ldr r3, [r3, #4]
|
|
8005e6e: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
8005e72: 687b ldr r3, [r7, #4]
|
|
8005e74: 691b ldr r3, [r3, #16]
|
|
8005e76: 00db lsls r3, r3, #3
|
|
8005e78: 4912 ldr r1, [pc, #72] @ (8005ec4 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8005e7a: 4313 orrs r3, r2
|
|
8005e7c: 604b str r3, [r1, #4]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
|
|
8005e7e: f000 f829 bl 8005ed4 <HAL_RCC_GetSysClockFreq>
|
|
8005e82: 4601 mov r1, r0
|
|
8005e84: 4b0f ldr r3, [pc, #60] @ (8005ec4 <HAL_RCC_ClockConfig+0x2e8>)
|
|
8005e86: 685b ldr r3, [r3, #4]
|
|
8005e88: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8005e8c: 22f0 movs r2, #240 @ 0xf0
|
|
8005e8e: 613a str r2, [r7, #16]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005e90: 693a ldr r2, [r7, #16]
|
|
8005e92: fa92 f2a2 rbit r2, r2
|
|
8005e96: 60fa str r2, [r7, #12]
|
|
return result;
|
|
8005e98: 68fa ldr r2, [r7, #12]
|
|
8005e9a: fab2 f282 clz r2, r2
|
|
8005e9e: b2d2 uxtb r2, r2
|
|
8005ea0: 40d3 lsrs r3, r2
|
|
8005ea2: 4a09 ldr r2, [pc, #36] @ (8005ec8 <HAL_RCC_ClockConfig+0x2ec>)
|
|
8005ea4: 5cd3 ldrb r3, [r2, r3]
|
|
8005ea6: fa21 f303 lsr.w r3, r1, r3
|
|
8005eaa: 4a08 ldr r2, [pc, #32] @ (8005ecc <HAL_RCC_ClockConfig+0x2f0>)
|
|
8005eac: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick (uwTickPrio);
|
|
8005eae: 4b08 ldr r3, [pc, #32] @ (8005ed0 <HAL_RCC_ClockConfig+0x2f4>)
|
|
8005eb0: 681b ldr r3, [r3, #0]
|
|
8005eb2: 4618 mov r0, r3
|
|
8005eb4: f7fc f9da bl 800226c <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8005eb8: 2300 movs r3, #0
|
|
}
|
|
8005eba: 4618 mov r0, r3
|
|
8005ebc: 3778 adds r7, #120 @ 0x78
|
|
8005ebe: 46bd mov sp, r7
|
|
8005ec0: bd80 pop {r7, pc}
|
|
8005ec2: bf00 nop
|
|
8005ec4: 40021000 .word 0x40021000
|
|
8005ec8: 0800723c .word 0x0800723c
|
|
8005ecc: 20000000 .word 0x20000000
|
|
8005ed0: 20000004 .word 0x20000004
|
|
|
|
08005ed4 <HAL_RCC_GetSysClockFreq>:
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8005ed4: b480 push {r7}
|
|
8005ed6: b087 sub sp, #28
|
|
8005ed8: af00 add r7, sp, #0
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
8005eda: 2300 movs r3, #0
|
|
8005edc: 60fb str r3, [r7, #12]
|
|
8005ede: 2300 movs r3, #0
|
|
8005ee0: 60bb str r3, [r7, #8]
|
|
8005ee2: 2300 movs r3, #0
|
|
8005ee4: 617b str r3, [r7, #20]
|
|
8005ee6: 2300 movs r3, #0
|
|
8005ee8: 607b str r3, [r7, #4]
|
|
uint32_t sysclockfreq = 0U;
|
|
8005eea: 2300 movs r3, #0
|
|
8005eec: 613b str r3, [r7, #16]
|
|
|
|
tmpreg = RCC->CFGR;
|
|
8005eee: 4b1e ldr r3, [pc, #120] @ (8005f68 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
8005ef0: 685b ldr r3, [r3, #4]
|
|
8005ef2: 60fb str r3, [r7, #12]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
8005ef4: 68fb ldr r3, [r7, #12]
|
|
8005ef6: f003 030c and.w r3, r3, #12
|
|
8005efa: 2b04 cmp r3, #4
|
|
8005efc: d002 beq.n 8005f04 <HAL_RCC_GetSysClockFreq+0x30>
|
|
8005efe: 2b08 cmp r3, #8
|
|
8005f00: d003 beq.n 8005f0a <HAL_RCC_GetSysClockFreq+0x36>
|
|
8005f02: e026 b.n 8005f52 <HAL_RCC_GetSysClockFreq+0x7e>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8005f04: 4b19 ldr r3, [pc, #100] @ (8005f6c <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8005f06: 613b str r3, [r7, #16]
|
|
break;
|
|
8005f08: e026 b.n 8005f58 <HAL_RCC_GetSysClockFreq+0x84>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
|
|
8005f0a: 68fb ldr r3, [r7, #12]
|
|
8005f0c: 0c9b lsrs r3, r3, #18
|
|
8005f0e: f003 030f and.w r3, r3, #15
|
|
8005f12: 4a17 ldr r2, [pc, #92] @ (8005f70 <HAL_RCC_GetSysClockFreq+0x9c>)
|
|
8005f14: 5cd3 ldrb r3, [r2, r3]
|
|
8005f16: 607b str r3, [r7, #4]
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_Pos];
|
|
8005f18: 4b13 ldr r3, [pc, #76] @ (8005f68 <HAL_RCC_GetSysClockFreq+0x94>)
|
|
8005f1a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8005f1c: f003 030f and.w r3, r3, #15
|
|
8005f20: 4a14 ldr r2, [pc, #80] @ (8005f74 <HAL_RCC_GetSysClockFreq+0xa0>)
|
|
8005f22: 5cd3 ldrb r3, [r2, r3]
|
|
8005f24: 60bb str r3, [r7, #8]
|
|
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
|
|
8005f26: 68fb ldr r3, [r7, #12]
|
|
8005f28: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8005f2c: 2b00 cmp r3, #0
|
|
8005f2e: d008 beq.n 8005f42 <HAL_RCC_GetSysClockFreq+0x6e>
|
|
{
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
|
|
8005f30: 4a0e ldr r2, [pc, #56] @ (8005f6c <HAL_RCC_GetSysClockFreq+0x98>)
|
|
8005f32: 68bb ldr r3, [r7, #8]
|
|
8005f34: fbb2 f2f3 udiv r2, r2, r3
|
|
8005f38: 687b ldr r3, [r7, #4]
|
|
8005f3a: fb02 f303 mul.w r3, r2, r3
|
|
8005f3e: 617b str r3, [r7, #20]
|
|
8005f40: e004 b.n 8005f4c <HAL_RCC_GetSysClockFreq+0x78>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
|
|
8005f42: 687b ldr r3, [r7, #4]
|
|
8005f44: 4a0c ldr r2, [pc, #48] @ (8005f78 <HAL_RCC_GetSysClockFreq+0xa4>)
|
|
8005f46: fb02 f303 mul.w r3, r2, r3
|
|
8005f4a: 617b str r3, [r7, #20]
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
|
|
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
|
|
}
|
|
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
|
|
sysclockfreq = pllclk;
|
|
8005f4c: 697b ldr r3, [r7, #20]
|
|
8005f4e: 613b str r3, [r7, #16]
|
|
break;
|
|
8005f50: e002 b.n 8005f58 <HAL_RCC_GetSysClockFreq+0x84>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8005f52: 4b0a ldr r3, [pc, #40] @ (8005f7c <HAL_RCC_GetSysClockFreq+0xa8>)
|
|
8005f54: 613b str r3, [r7, #16]
|
|
break;
|
|
8005f56: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8005f58: 693b ldr r3, [r7, #16]
|
|
}
|
|
8005f5a: 4618 mov r0, r3
|
|
8005f5c: 371c adds r7, #28
|
|
8005f5e: 46bd mov sp, r7
|
|
8005f60: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f64: 4770 bx lr
|
|
8005f66: bf00 nop
|
|
8005f68: 40021000 .word 0x40021000
|
|
8005f6c: 00f42400 .word 0x00f42400
|
|
8005f70: 08007254 .word 0x08007254
|
|
8005f74: 08007264 .word 0x08007264
|
|
8005f78: 003d0900 .word 0x003d0900
|
|
8005f7c: 007a1200 .word 0x007a1200
|
|
|
|
08005f80 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8005f80: b480 push {r7}
|
|
8005f82: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8005f84: 4b03 ldr r3, [pc, #12] @ (8005f94 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
8005f86: 681b ldr r3, [r3, #0]
|
|
}
|
|
8005f88: 4618 mov r0, r3
|
|
8005f8a: 46bd mov sp, r7
|
|
8005f8c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f90: 4770 bx lr
|
|
8005f92: bf00 nop
|
|
8005f94: 20000000 .word 0x20000000
|
|
|
|
08005f98 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8005f98: b580 push {r7, lr}
|
|
8005f9a: b082 sub sp, #8
|
|
8005f9c: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
|
|
8005f9e: f7ff ffef bl 8005f80 <HAL_RCC_GetHCLKFreq>
|
|
8005fa2: 4601 mov r1, r0
|
|
8005fa4: 4b0b ldr r3, [pc, #44] @ (8005fd4 <HAL_RCC_GetPCLK1Freq+0x3c>)
|
|
8005fa6: 685b ldr r3, [r3, #4]
|
|
8005fa8: f403 63e0 and.w r3, r3, #1792 @ 0x700
|
|
8005fac: f44f 62e0 mov.w r2, #1792 @ 0x700
|
|
8005fb0: 607a str r2, [r7, #4]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005fb2: 687a ldr r2, [r7, #4]
|
|
8005fb4: fa92 f2a2 rbit r2, r2
|
|
8005fb8: 603a str r2, [r7, #0]
|
|
return result;
|
|
8005fba: 683a ldr r2, [r7, #0]
|
|
8005fbc: fab2 f282 clz r2, r2
|
|
8005fc0: b2d2 uxtb r2, r2
|
|
8005fc2: 40d3 lsrs r3, r2
|
|
8005fc4: 4a04 ldr r2, [pc, #16] @ (8005fd8 <HAL_RCC_GetPCLK1Freq+0x40>)
|
|
8005fc6: 5cd3 ldrb r3, [r2, r3]
|
|
8005fc8: fa21 f303 lsr.w r3, r1, r3
|
|
}
|
|
8005fcc: 4618 mov r0, r3
|
|
8005fce: 3708 adds r7, #8
|
|
8005fd0: 46bd mov sp, r7
|
|
8005fd2: bd80 pop {r7, pc}
|
|
8005fd4: 40021000 .word 0x40021000
|
|
8005fd8: 0800724c .word 0x0800724c
|
|
|
|
08005fdc <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
8005fdc: b580 push {r7, lr}
|
|
8005fde: b082 sub sp, #8
|
|
8005fe0: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
|
|
8005fe2: f7ff ffcd bl 8005f80 <HAL_RCC_GetHCLKFreq>
|
|
8005fe6: 4601 mov r1, r0
|
|
8005fe8: 4b0b ldr r3, [pc, #44] @ (8006018 <HAL_RCC_GetPCLK2Freq+0x3c>)
|
|
8005fea: 685b ldr r3, [r3, #4]
|
|
8005fec: f403 5360 and.w r3, r3, #14336 @ 0x3800
|
|
8005ff0: f44f 5260 mov.w r2, #14336 @ 0x3800
|
|
8005ff4: 607a str r2, [r7, #4]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005ff6: 687a ldr r2, [r7, #4]
|
|
8005ff8: fa92 f2a2 rbit r2, r2
|
|
8005ffc: 603a str r2, [r7, #0]
|
|
return result;
|
|
8005ffe: 683a ldr r2, [r7, #0]
|
|
8006000: fab2 f282 clz r2, r2
|
|
8006004: b2d2 uxtb r2, r2
|
|
8006006: 40d3 lsrs r3, r2
|
|
8006008: 4a04 ldr r2, [pc, #16] @ (800601c <HAL_RCC_GetPCLK2Freq+0x40>)
|
|
800600a: 5cd3 ldrb r3, [r2, r3]
|
|
800600c: fa21 f303 lsr.w r3, r1, r3
|
|
}
|
|
8006010: 4618 mov r0, r3
|
|
8006012: 3708 adds r7, #8
|
|
8006014: 46bd mov sp, r7
|
|
8006016: bd80 pop {r7, pc}
|
|
8006018: 40021000 .word 0x40021000
|
|
800601c: 0800724c .word 0x0800724c
|
|
|
|
08006020 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8006020: b580 push {r7, lr}
|
|
8006022: b092 sub sp, #72 @ 0x48
|
|
8006024: af00 add r7, sp, #0
|
|
8006026: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
8006028: 2300 movs r3, #0
|
|
800602a: 643b str r3, [r7, #64] @ 0x40
|
|
uint32_t temp_reg = 0U;
|
|
800602c: 2300 movs r3, #0
|
|
800602e: 63fb str r3, [r7, #60] @ 0x3c
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8006030: 2300 movs r3, #0
|
|
8006032: f887 3047 strb.w r3, [r7, #71] @ 0x47
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*---------------------------- RTC configuration -------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
8006036: 687b ldr r3, [r7, #4]
|
|
8006038: 681b ldr r3, [r3, #0]
|
|
800603a: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
800603e: 2b00 cmp r3, #0
|
|
8006040: f000 80d4 beq.w 80061ec <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
|
|
|
|
/* As soon as function is called to change RTC clock source, activation of the
|
|
power domain is done. */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8006044: 4b4e ldr r3, [pc, #312] @ (8006180 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8006046: 69db ldr r3, [r3, #28]
|
|
8006048: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800604c: 2b00 cmp r3, #0
|
|
800604e: d10e bne.n 800606e <HAL_RCCEx_PeriphCLKConfig+0x4e>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8006050: 4b4b ldr r3, [pc, #300] @ (8006180 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8006052: 69db ldr r3, [r3, #28]
|
|
8006054: 4a4a ldr r2, [pc, #296] @ (8006180 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8006056: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800605a: 61d3 str r3, [r2, #28]
|
|
800605c: 4b48 ldr r3, [pc, #288] @ (8006180 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800605e: 69db ldr r3, [r3, #28]
|
|
8006060: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8006064: 60bb str r3, [r7, #8]
|
|
8006066: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8006068: 2301 movs r3, #1
|
|
800606a: f887 3047 strb.w r3, [r7, #71] @ 0x47
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
800606e: 4b45 ldr r3, [pc, #276] @ (8006184 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
8006070: 681b ldr r3, [r3, #0]
|
|
8006072: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8006076: 2b00 cmp r3, #0
|
|
8006078: d118 bne.n 80060ac <HAL_RCCEx_PeriphCLKConfig+0x8c>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
800607a: 4b42 ldr r3, [pc, #264] @ (8006184 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
800607c: 681b ldr r3, [r3, #0]
|
|
800607e: 4a41 ldr r2, [pc, #260] @ (8006184 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
8006080: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8006084: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8006086: f7fc f935 bl 80022f4 <HAL_GetTick>
|
|
800608a: 6438 str r0, [r7, #64] @ 0x40
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
800608c: e008 b.n 80060a0 <HAL_RCCEx_PeriphCLKConfig+0x80>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800608e: f7fc f931 bl 80022f4 <HAL_GetTick>
|
|
8006092: 4602 mov r2, r0
|
|
8006094: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8006096: 1ad3 subs r3, r2, r3
|
|
8006098: 2b64 cmp r3, #100 @ 0x64
|
|
800609a: d901 bls.n 80060a0 <HAL_RCCEx_PeriphCLKConfig+0x80>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800609c: 2303 movs r3, #3
|
|
800609e: e14b b.n 8006338 <HAL_RCCEx_PeriphCLKConfig+0x318>
|
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
80060a0: 4b38 ldr r3, [pc, #224] @ (8006184 <HAL_RCCEx_PeriphCLKConfig+0x164>)
|
|
80060a2: 681b ldr r3, [r3, #0]
|
|
80060a4: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80060a8: 2b00 cmp r3, #0
|
|
80060aa: d0f0 beq.n 800608e <HAL_RCCEx_PeriphCLKConfig+0x6e>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
80060ac: 4b34 ldr r3, [pc, #208] @ (8006180 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
80060ae: 6a1b ldr r3, [r3, #32]
|
|
80060b0: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80060b4: 63fb str r3, [r7, #60] @ 0x3c
|
|
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
80060b6: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80060b8: 2b00 cmp r3, #0
|
|
80060ba: f000 8084 beq.w 80061c6 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
|
|
80060be: 687b ldr r3, [r7, #4]
|
|
80060c0: 685b ldr r3, [r3, #4]
|
|
80060c2: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80060c6: 6bfa ldr r2, [r7, #60] @ 0x3c
|
|
80060c8: 429a cmp r2, r3
|
|
80060ca: d07c beq.n 80061c6 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
80060cc: 4b2c ldr r3, [pc, #176] @ (8006180 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
80060ce: 6a1b ldr r3, [r3, #32]
|
|
80060d0: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80060d4: 63fb str r3, [r7, #60] @ 0x3c
|
|
80060d6: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80060da: 633b str r3, [r7, #48] @ 0x30
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80060dc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80060de: fa93 f3a3 rbit r3, r3
|
|
80060e2: 62fb str r3, [r7, #44] @ 0x2c
|
|
return result;
|
|
80060e4: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
80060e6: fab3 f383 clz r3, r3
|
|
80060ea: b2db uxtb r3, r3
|
|
80060ec: 461a mov r2, r3
|
|
80060ee: 4b26 ldr r3, [pc, #152] @ (8006188 <HAL_RCCEx_PeriphCLKConfig+0x168>)
|
|
80060f0: 4413 add r3, r2
|
|
80060f2: 009b lsls r3, r3, #2
|
|
80060f4: 461a mov r2, r3
|
|
80060f6: 2301 movs r3, #1
|
|
80060f8: 6013 str r3, [r2, #0]
|
|
80060fa: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80060fe: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8006100: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006102: fa93 f3a3 rbit r3, r3
|
|
8006106: 637b str r3, [r7, #52] @ 0x34
|
|
return result;
|
|
8006108: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
800610a: fab3 f383 clz r3, r3
|
|
800610e: b2db uxtb r3, r3
|
|
8006110: 461a mov r2, r3
|
|
8006112: 4b1d ldr r3, [pc, #116] @ (8006188 <HAL_RCCEx_PeriphCLKConfig+0x168>)
|
|
8006114: 4413 add r3, r2
|
|
8006116: 009b lsls r3, r3, #2
|
|
8006118: 461a mov r2, r3
|
|
800611a: 2300 movs r3, #0
|
|
800611c: 6013 str r3, [r2, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = temp_reg;
|
|
800611e: 4a18 ldr r2, [pc, #96] @ (8006180 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
8006120: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006122: 6213 str r3, [r2, #32]
|
|
|
|
/* Wait for LSERDY if LSE was enabled */
|
|
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
|
|
8006124: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006126: f003 0301 and.w r3, r3, #1
|
|
800612a: 2b00 cmp r3, #0
|
|
800612c: d04b beq.n 80061c6 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800612e: f7fc f8e1 bl 80022f4 <HAL_GetTick>
|
|
8006132: 6438 str r0, [r7, #64] @ 0x40
|
|
|
|
/* Wait till LSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8006134: e00a b.n 800614c <HAL_RCCEx_PeriphCLKConfig+0x12c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8006136: f7fc f8dd bl 80022f4 <HAL_GetTick>
|
|
800613a: 4602 mov r2, r0
|
|
800613c: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
800613e: 1ad3 subs r3, r2, r3
|
|
8006140: f241 3288 movw r2, #5000 @ 0x1388
|
|
8006144: 4293 cmp r3, r2
|
|
8006146: d901 bls.n 800614c <HAL_RCCEx_PeriphCLKConfig+0x12c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006148: 2303 movs r3, #3
|
|
800614a: e0f5 b.n 8006338 <HAL_RCCEx_PeriphCLKConfig+0x318>
|
|
800614c: 2302 movs r3, #2
|
|
800614e: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8006150: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006152: fa93 f3a3 rbit r3, r3
|
|
8006156: 627b str r3, [r7, #36] @ 0x24
|
|
8006158: 2302 movs r3, #2
|
|
800615a: 623b str r3, [r7, #32]
|
|
800615c: 6a3b ldr r3, [r7, #32]
|
|
800615e: fa93 f3a3 rbit r3, r3
|
|
8006162: 61fb str r3, [r7, #28]
|
|
return result;
|
|
8006164: 69fb ldr r3, [r7, #28]
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8006166: fab3 f383 clz r3, r3
|
|
800616a: b2db uxtb r3, r3
|
|
800616c: 095b lsrs r3, r3, #5
|
|
800616e: b2db uxtb r3, r3
|
|
8006170: f043 0302 orr.w r3, r3, #2
|
|
8006174: b2db uxtb r3, r3
|
|
8006176: 2b02 cmp r3, #2
|
|
8006178: d108 bne.n 800618c <HAL_RCCEx_PeriphCLKConfig+0x16c>
|
|
800617a: 4b01 ldr r3, [pc, #4] @ (8006180 <HAL_RCCEx_PeriphCLKConfig+0x160>)
|
|
800617c: 6a1b ldr r3, [r3, #32]
|
|
800617e: e00d b.n 800619c <HAL_RCCEx_PeriphCLKConfig+0x17c>
|
|
8006180: 40021000 .word 0x40021000
|
|
8006184: 40007000 .word 0x40007000
|
|
8006188: 10908100 .word 0x10908100
|
|
800618c: 2302 movs r3, #2
|
|
800618e: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8006190: 69bb ldr r3, [r7, #24]
|
|
8006192: fa93 f3a3 rbit r3, r3
|
|
8006196: 617b str r3, [r7, #20]
|
|
8006198: 4b69 ldr r3, [pc, #420] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
800619a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800619c: 2202 movs r2, #2
|
|
800619e: 613a str r2, [r7, #16]
|
|
80061a0: 693a ldr r2, [r7, #16]
|
|
80061a2: fa92 f2a2 rbit r2, r2
|
|
80061a6: 60fa str r2, [r7, #12]
|
|
return result;
|
|
80061a8: 68fa ldr r2, [r7, #12]
|
|
80061aa: fab2 f282 clz r2, r2
|
|
80061ae: b2d2 uxtb r2, r2
|
|
80061b0: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
80061b4: b2d2 uxtb r2, r2
|
|
80061b6: f002 021f and.w r2, r2, #31
|
|
80061ba: 2101 movs r1, #1
|
|
80061bc: fa01 f202 lsl.w r2, r1, r2
|
|
80061c0: 4013 ands r3, r2
|
|
80061c2: 2b00 cmp r3, #0
|
|
80061c4: d0b7 beq.n 8006136 <HAL_RCCEx_PeriphCLKConfig+0x116>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80061c6: 4b5e ldr r3, [pc, #376] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80061c8: 6a1b ldr r3, [r3, #32]
|
|
80061ca: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
80061ce: 687b ldr r3, [r7, #4]
|
|
80061d0: 685b ldr r3, [r3, #4]
|
|
80061d2: 495b ldr r1, [pc, #364] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80061d4: 4313 orrs r3, r2
|
|
80061d6: 620b str r3, [r1, #32]
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if(pwrclkchanged == SET)
|
|
80061d8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47
|
|
80061dc: 2b01 cmp r3, #1
|
|
80061de: d105 bne.n 80061ec <HAL_RCCEx_PeriphCLKConfig+0x1cc>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80061e0: 4b57 ldr r3, [pc, #348] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80061e2: 69db ldr r3, [r3, #28]
|
|
80061e4: 4a56 ldr r2, [pc, #344] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80061e6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80061ea: 61d3 str r3, [r2, #28]
|
|
}
|
|
}
|
|
|
|
/*------------------------------- USART1 Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
80061ec: 687b ldr r3, [r7, #4]
|
|
80061ee: 681b ldr r3, [r3, #0]
|
|
80061f0: f003 0301 and.w r3, r3, #1
|
|
80061f4: 2b00 cmp r3, #0
|
|
80061f6: d008 beq.n 800620a <HAL_RCCEx_PeriphCLKConfig+0x1ea>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
80061f8: 4b51 ldr r3, [pc, #324] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80061fa: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80061fc: f023 0203 bic.w r2, r3, #3
|
|
8006200: 687b ldr r3, [r7, #4]
|
|
8006202: 689b ldr r3, [r3, #8]
|
|
8006204: 494e ldr r1, [pc, #312] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006206: 4313 orrs r3, r2
|
|
8006208: 630b str r3, [r1, #48] @ 0x30
|
|
}
|
|
|
|
#if defined(RCC_CFGR3_USART2SW)
|
|
/*----------------------------- USART2 Configuration --------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
800620a: 687b ldr r3, [r7, #4]
|
|
800620c: 681b ldr r3, [r3, #0]
|
|
800620e: f003 0302 and.w r3, r3, #2
|
|
8006212: 2b00 cmp r3, #0
|
|
8006214: d008 beq.n 8006228 <HAL_RCCEx_PeriphCLKConfig+0x208>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
8006216: 4b4a ldr r3, [pc, #296] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006218: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800621a: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
800621e: 687b ldr r3, [r7, #4]
|
|
8006220: 68db ldr r3, [r3, #12]
|
|
8006222: 4947 ldr r1, [pc, #284] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006224: 4313 orrs r3, r2
|
|
8006226: 630b str r3, [r1, #48] @ 0x30
|
|
}
|
|
#endif /* RCC_CFGR3_USART2SW */
|
|
|
|
#if defined(RCC_CFGR3_USART3SW)
|
|
/*------------------------------ USART3 Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
8006228: 687b ldr r3, [r7, #4]
|
|
800622a: 681b ldr r3, [r3, #0]
|
|
800622c: f003 0304 and.w r3, r3, #4
|
|
8006230: 2b00 cmp r3, #0
|
|
8006232: d008 beq.n 8006246 <HAL_RCCEx_PeriphCLKConfig+0x226>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
8006234: 4b42 ldr r3, [pc, #264] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006236: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006238: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
|
|
800623c: 687b ldr r3, [r7, #4]
|
|
800623e: 691b ldr r3, [r3, #16]
|
|
8006240: 493f ldr r1, [pc, #252] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006242: 4313 orrs r3, r2
|
|
8006244: 630b str r3, [r1, #48] @ 0x30
|
|
}
|
|
#endif /* RCC_CFGR3_USART3SW */
|
|
|
|
/*------------------------------ I2C1 Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
8006246: 687b ldr r3, [r7, #4]
|
|
8006248: 681b ldr r3, [r3, #0]
|
|
800624a: f003 0320 and.w r3, r3, #32
|
|
800624e: 2b00 cmp r3, #0
|
|
8006250: d008 beq.n 8006264 <HAL_RCCEx_PeriphCLKConfig+0x244>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
8006252: 4b3b ldr r3, [pc, #236] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006254: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006256: f023 0210 bic.w r2, r3, #16
|
|
800625a: 687b ldr r3, [r7, #4]
|
|
800625c: 69db ldr r3, [r3, #28]
|
|
800625e: 4938 ldr r1, [pc, #224] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006260: 4313 orrs r3, r2
|
|
8006262: 630b str r3, [r1, #48] @ 0x30
|
|
#if defined(STM32F302xE) || defined(STM32F303xE)\
|
|
|| defined(STM32F302xC) || defined(STM32F303xC)\
|
|
|| defined(STM32F302x8) \
|
|
|| defined(STM32F373xC)
|
|
/*------------------------------ USB Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
|
|
8006264: 687b ldr r3, [r7, #4]
|
|
8006266: 681b ldr r3, [r3, #0]
|
|
8006268: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800626c: 2b00 cmp r3, #0
|
|
800626e: d008 beq.n 8006282 <HAL_RCCEx_PeriphCLKConfig+0x262>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
|
|
|
|
/* Configure the USB clock source */
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
|
|
8006270: 4b33 ldr r3, [pc, #204] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006272: 685b ldr r3, [r3, #4]
|
|
8006274: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
|
|
8006278: 687b ldr r3, [r7, #4]
|
|
800627a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800627c: 4930 ldr r1, [pc, #192] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
800627e: 4313 orrs r3, r2
|
|
8006280: 604b str r3, [r1, #4]
|
|
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|
|
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
|
|
|| defined(STM32F373xC) || defined(STM32F378xx)
|
|
|
|
/*------------------------------ I2C2 Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
8006282: 687b ldr r3, [r7, #4]
|
|
8006284: 681b ldr r3, [r3, #0]
|
|
8006286: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800628a: 2b00 cmp r3, #0
|
|
800628c: d008 beq.n 80062a0 <HAL_RCCEx_PeriphCLKConfig+0x280>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
800628e: 4b2c ldr r3, [pc, #176] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006290: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006292: f023 0220 bic.w r2, r3, #32
|
|
8006296: 687b ldr r3, [r7, #4]
|
|
8006298: 6a1b ldr r3, [r3, #32]
|
|
800629a: 4929 ldr r1, [pc, #164] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
800629c: 4313 orrs r3, r2
|
|
800629e: 630b str r3, [r1, #48] @ 0x30
|
|
|
|
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
|
|
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
|
|
|
|
/*------------------------------ UART4 Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
80062a0: 687b ldr r3, [r7, #4]
|
|
80062a2: 681b ldr r3, [r3, #0]
|
|
80062a4: f003 0308 and.w r3, r3, #8
|
|
80062a8: 2b00 cmp r3, #0
|
|
80062aa: d008 beq.n 80062be <HAL_RCCEx_PeriphCLKConfig+0x29e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
80062ac: 4b24 ldr r3, [pc, #144] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80062ae: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80062b0: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
80062b4: 687b ldr r3, [r7, #4]
|
|
80062b6: 695b ldr r3, [r3, #20]
|
|
80062b8: 4921 ldr r1, [pc, #132] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80062ba: 4313 orrs r3, r2
|
|
80062bc: 630b str r3, [r1, #48] @ 0x30
|
|
}
|
|
|
|
/*------------------------------ UART5 Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
|
80062be: 687b ldr r3, [r7, #4]
|
|
80062c0: 681b ldr r3, [r3, #0]
|
|
80062c2: f003 0310 and.w r3, r3, #16
|
|
80062c6: 2b00 cmp r3, #0
|
|
80062c8: d008 beq.n 80062dc <HAL_RCCEx_PeriphCLKConfig+0x2bc>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
|
|
|
/* Configure the UART5 clock source */
|
|
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
|
80062ca: 4b1d ldr r3, [pc, #116] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80062cc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80062ce: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
80062d2: 687b ldr r3, [r7, #4]
|
|
80062d4: 699b ldr r3, [r3, #24]
|
|
80062d6: 491a ldr r1, [pc, #104] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80062d8: 4313 orrs r3, r2
|
|
80062da: 630b str r3, [r1, #48] @ 0x30
|
|
|
|
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
|
|
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|
|
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
|
/*------------------------------ I2S Configuration ------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
|
|
80062dc: 687b ldr r3, [r7, #4]
|
|
80062de: 681b ldr r3, [r3, #0]
|
|
80062e0: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80062e4: 2b00 cmp r3, #0
|
|
80062e6: d008 beq.n 80062fa <HAL_RCCEx_PeriphCLKConfig+0x2da>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
|
|
|
|
/* Configure the I2S clock source */
|
|
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
|
|
80062e8: 4b15 ldr r3, [pc, #84] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80062ea: 685b ldr r3, [r3, #4]
|
|
80062ec: f423 0200 bic.w r2, r3, #8388608 @ 0x800000
|
|
80062f0: 687b ldr r3, [r7, #4]
|
|
80062f2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80062f4: 4912 ldr r1, [pc, #72] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
80062f6: 4313 orrs r3, r2
|
|
80062f8: 604b str r3, [r1, #4]
|
|
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
|
|
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|
|
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
|
|
|
/*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
|
|
80062fa: 687b ldr r3, [r7, #4]
|
|
80062fc: 681b ldr r3, [r3, #0]
|
|
80062fe: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006302: 2b00 cmp r3, #0
|
|
8006304: d008 beq.n 8006318 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
|
|
|
|
/* Configure the ADC12 clock source */
|
|
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
|
|
8006306: 4b0e ldr r3, [pc, #56] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006308: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800630a: f423 72f8 bic.w r2, r3, #496 @ 0x1f0
|
|
800630e: 687b ldr r3, [r7, #4]
|
|
8006310: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006312: 490b ldr r1, [pc, #44] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006314: 4313 orrs r3, r2
|
|
8006316: 62cb str r3, [r1, #44] @ 0x2c
|
|
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|
|
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
|
|
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
|
|
|
|
/*------------------------------ TIM1 clock Configuration ----------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
|
|
8006318: 687b ldr r3, [r7, #4]
|
|
800631a: 681b ldr r3, [r3, #0]
|
|
800631c: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8006320: 2b00 cmp r3, #0
|
|
8006322: d008 beq.n 8006336 <HAL_RCCEx_PeriphCLKConfig+0x316>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
|
|
|
|
/* Configure the TIM1 clock source */
|
|
__HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
|
|
8006324: 4b06 ldr r3, [pc, #24] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006326: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006328: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
800632c: 687b ldr r3, [r7, #4]
|
|
800632e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8006330: 4903 ldr r1, [pc, #12] @ (8006340 <HAL_RCCEx_PeriphCLKConfig+0x320>)
|
|
8006332: 4313 orrs r3, r2
|
|
8006334: 630b str r3, [r1, #48] @ 0x30
|
|
__HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
|
|
}
|
|
#endif /* STM32F303xE || STM32F398xx */
|
|
|
|
|
|
return HAL_OK;
|
|
8006336: 2300 movs r3, #0
|
|
}
|
|
8006338: 4618 mov r0, r3
|
|
800633a: 3748 adds r7, #72 @ 0x48
|
|
800633c: 46bd mov sp, r7
|
|
800633e: bd80 pop {r7, pc}
|
|
8006340: 40021000 .word 0x40021000
|
|
|
|
08006344 <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8006344: b580 push {r7, lr}
|
|
8006346: b082 sub sp, #8
|
|
8006348: af00 add r7, sp, #0
|
|
800634a: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800634c: 687b ldr r3, [r7, #4]
|
|
800634e: 2b00 cmp r3, #0
|
|
8006350: d101 bne.n 8006356 <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8006352: 2301 movs r3, #1
|
|
8006354: e049 b.n 80063ea <HAL_TIM_Base_Init+0xa6>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8006356: 687b ldr r3, [r7, #4]
|
|
8006358: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800635c: b2db uxtb r3, r3
|
|
800635e: 2b00 cmp r3, #0
|
|
8006360: d106 bne.n 8006370 <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8006362: 687b ldr r3, [r7, #4]
|
|
8006364: 2200 movs r2, #0
|
|
8006366: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
800636a: 6878 ldr r0, [r7, #4]
|
|
800636c: f7fb fe52 bl 8002014 <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8006370: 687b ldr r3, [r7, #4]
|
|
8006372: 2202 movs r2, #2
|
|
8006374: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8006378: 687b ldr r3, [r7, #4]
|
|
800637a: 681a ldr r2, [r3, #0]
|
|
800637c: 687b ldr r3, [r7, #4]
|
|
800637e: 3304 adds r3, #4
|
|
8006380: 4619 mov r1, r3
|
|
8006382: 4610 mov r0, r2
|
|
8006384: f000 f9c4 bl 8006710 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8006388: 687b ldr r3, [r7, #4]
|
|
800638a: 2201 movs r2, #1
|
|
800638c: f883 2048 strb.w r2, [r3, #72] @ 0x48
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8006390: 687b ldr r3, [r7, #4]
|
|
8006392: 2201 movs r2, #1
|
|
8006394: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8006398: 687b ldr r3, [r7, #4]
|
|
800639a: 2201 movs r2, #1
|
|
800639c: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
80063a0: 687b ldr r3, [r7, #4]
|
|
80063a2: 2201 movs r2, #1
|
|
80063a4: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
80063a8: 687b ldr r3, [r7, #4]
|
|
80063aa: 2201 movs r2, #1
|
|
80063ac: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
80063b0: 687b ldr r3, [r7, #4]
|
|
80063b2: 2201 movs r2, #1
|
|
80063b4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
80063b8: 687b ldr r3, [r7, #4]
|
|
80063ba: 2201 movs r2, #1
|
|
80063bc: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80063c0: 687b ldr r3, [r7, #4]
|
|
80063c2: 2201 movs r2, #1
|
|
80063c4: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
80063c8: 687b ldr r3, [r7, #4]
|
|
80063ca: 2201 movs r2, #1
|
|
80063cc: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
80063d0: 687b ldr r3, [r7, #4]
|
|
80063d2: 2201 movs r2, #1
|
|
80063d4: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
80063d8: 687b ldr r3, [r7, #4]
|
|
80063da: 2201 movs r2, #1
|
|
80063dc: f883 2047 strb.w r2, [r3, #71] @ 0x47
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80063e0: 687b ldr r3, [r7, #4]
|
|
80063e2: 2201 movs r2, #1
|
|
80063e4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80063e8: 2300 movs r3, #0
|
|
}
|
|
80063ea: 4618 mov r0, r3
|
|
80063ec: 3708 adds r7, #8
|
|
80063ee: 46bd mov sp, r7
|
|
80063f0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080063f4 <HAL_TIM_Base_Start>:
|
|
* @brief Starts the TIM Base generation.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
|
|
{
|
|
80063f4: b480 push {r7}
|
|
80063f6: b085 sub sp, #20
|
|
80063f8: af00 add r7, sp, #0
|
|
80063fa: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Check the TIM state */
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
80063fc: 687b ldr r3, [r7, #4]
|
|
80063fe: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8006402: b2db uxtb r3, r3
|
|
8006404: 2b01 cmp r3, #1
|
|
8006406: d001 beq.n 800640c <HAL_TIM_Base_Start+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
8006408: 2301 movs r3, #1
|
|
800640a: e03d b.n 8006488 <HAL_TIM_Base_Start+0x94>
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800640c: 687b ldr r3, [r7, #4]
|
|
800640e: 2202 movs r2, #2
|
|
8006410: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8006414: 687b ldr r3, [r7, #4]
|
|
8006416: 681b ldr r3, [r3, #0]
|
|
8006418: 4a1e ldr r2, [pc, #120] @ (8006494 <HAL_TIM_Base_Start+0xa0>)
|
|
800641a: 4293 cmp r3, r2
|
|
800641c: d013 beq.n 8006446 <HAL_TIM_Base_Start+0x52>
|
|
800641e: 687b ldr r3, [r7, #4]
|
|
8006420: 681b ldr r3, [r3, #0]
|
|
8006422: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8006426: d00e beq.n 8006446 <HAL_TIM_Base_Start+0x52>
|
|
8006428: 687b ldr r3, [r7, #4]
|
|
800642a: 681b ldr r3, [r3, #0]
|
|
800642c: 4a1a ldr r2, [pc, #104] @ (8006498 <HAL_TIM_Base_Start+0xa4>)
|
|
800642e: 4293 cmp r3, r2
|
|
8006430: d009 beq.n 8006446 <HAL_TIM_Base_Start+0x52>
|
|
8006432: 687b ldr r3, [r7, #4]
|
|
8006434: 681b ldr r3, [r3, #0]
|
|
8006436: 4a19 ldr r2, [pc, #100] @ (800649c <HAL_TIM_Base_Start+0xa8>)
|
|
8006438: 4293 cmp r3, r2
|
|
800643a: d004 beq.n 8006446 <HAL_TIM_Base_Start+0x52>
|
|
800643c: 687b ldr r3, [r7, #4]
|
|
800643e: 681b ldr r3, [r3, #0]
|
|
8006440: 4a17 ldr r2, [pc, #92] @ (80064a0 <HAL_TIM_Base_Start+0xac>)
|
|
8006442: 4293 cmp r3, r2
|
|
8006444: d115 bne.n 8006472 <HAL_TIM_Base_Start+0x7e>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8006446: 687b ldr r3, [r7, #4]
|
|
8006448: 681b ldr r3, [r3, #0]
|
|
800644a: 689a ldr r2, [r3, #8]
|
|
800644c: 4b15 ldr r3, [pc, #84] @ (80064a4 <HAL_TIM_Base_Start+0xb0>)
|
|
800644e: 4013 ands r3, r2
|
|
8006450: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8006452: 68fb ldr r3, [r7, #12]
|
|
8006454: 2b06 cmp r3, #6
|
|
8006456: d015 beq.n 8006484 <HAL_TIM_Base_Start+0x90>
|
|
8006458: 68fb ldr r3, [r7, #12]
|
|
800645a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800645e: d011 beq.n 8006484 <HAL_TIM_Base_Start+0x90>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8006460: 687b ldr r3, [r7, #4]
|
|
8006462: 681b ldr r3, [r3, #0]
|
|
8006464: 681a ldr r2, [r3, #0]
|
|
8006466: 687b ldr r3, [r7, #4]
|
|
8006468: 681b ldr r3, [r3, #0]
|
|
800646a: f042 0201 orr.w r2, r2, #1
|
|
800646e: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8006470: e008 b.n 8006484 <HAL_TIM_Base_Start+0x90>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8006472: 687b ldr r3, [r7, #4]
|
|
8006474: 681b ldr r3, [r3, #0]
|
|
8006476: 681a ldr r2, [r3, #0]
|
|
8006478: 687b ldr r3, [r7, #4]
|
|
800647a: 681b ldr r3, [r3, #0]
|
|
800647c: f042 0201 orr.w r2, r2, #1
|
|
8006480: 601a str r2, [r3, #0]
|
|
8006482: e000 b.n 8006486 <HAL_TIM_Base_Start+0x92>
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8006484: bf00 nop
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8006486: 2300 movs r3, #0
|
|
}
|
|
8006488: 4618 mov r0, r3
|
|
800648a: 3714 adds r7, #20
|
|
800648c: 46bd mov sp, r7
|
|
800648e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006492: 4770 bx lr
|
|
8006494: 40012c00 .word 0x40012c00
|
|
8006498: 40000400 .word 0x40000400
|
|
800649c: 40000800 .word 0x40000800
|
|
80064a0: 40014000 .word 0x40014000
|
|
80064a4: 00010007 .word 0x00010007
|
|
|
|
080064a8 <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
80064a8: b580 push {r7, lr}
|
|
80064aa: b084 sub sp, #16
|
|
80064ac: af00 add r7, sp, #0
|
|
80064ae: 6078 str r0, [r7, #4]
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
80064b0: 687b ldr r3, [r7, #4]
|
|
80064b2: 681b ldr r3, [r3, #0]
|
|
80064b4: 68db ldr r3, [r3, #12]
|
|
80064b6: 60fb str r3, [r7, #12]
|
|
uint32_t itflag = htim->Instance->SR;
|
|
80064b8: 687b ldr r3, [r7, #4]
|
|
80064ba: 681b ldr r3, [r3, #0]
|
|
80064bc: 691b ldr r3, [r3, #16]
|
|
80064be: 60bb str r3, [r7, #8]
|
|
|
|
/* Capture compare 1 event */
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
80064c0: 68bb ldr r3, [r7, #8]
|
|
80064c2: f003 0302 and.w r3, r3, #2
|
|
80064c6: 2b00 cmp r3, #0
|
|
80064c8: d020 beq.n 800650c <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
|
80064ca: 68fb ldr r3, [r7, #12]
|
|
80064cc: f003 0302 and.w r3, r3, #2
|
|
80064d0: 2b00 cmp r3, #0
|
|
80064d2: d01b beq.n 800650c <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
|
80064d4: 687b ldr r3, [r7, #4]
|
|
80064d6: 681b ldr r3, [r3, #0]
|
|
80064d8: f06f 0202 mvn.w r2, #2
|
|
80064dc: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
80064de: 687b ldr r3, [r7, #4]
|
|
80064e0: 2201 movs r2, #1
|
|
80064e2: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
80064e4: 687b ldr r3, [r7, #4]
|
|
80064e6: 681b ldr r3, [r3, #0]
|
|
80064e8: 699b ldr r3, [r3, #24]
|
|
80064ea: f003 0303 and.w r3, r3, #3
|
|
80064ee: 2b00 cmp r3, #0
|
|
80064f0: d003 beq.n 80064fa <HAL_TIM_IRQHandler+0x52>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80064f2: 6878 ldr r0, [r7, #4]
|
|
80064f4: f000 f8ee bl 80066d4 <HAL_TIM_IC_CaptureCallback>
|
|
80064f8: e005 b.n 8006506 <HAL_TIM_IRQHandler+0x5e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80064fa: 6878 ldr r0, [r7, #4]
|
|
80064fc: f000 f8e0 bl 80066c0 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8006500: 6878 ldr r0, [r7, #4]
|
|
8006502: f000 f8f1 bl 80066e8 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8006506: 687b ldr r3, [r7, #4]
|
|
8006508: 2200 movs r2, #0
|
|
800650a: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
|
800650c: 68bb ldr r3, [r7, #8]
|
|
800650e: f003 0304 and.w r3, r3, #4
|
|
8006512: 2b00 cmp r3, #0
|
|
8006514: d020 beq.n 8006558 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
|
8006516: 68fb ldr r3, [r7, #12]
|
|
8006518: f003 0304 and.w r3, r3, #4
|
|
800651c: 2b00 cmp r3, #0
|
|
800651e: d01b beq.n 8006558 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
|
8006520: 687b ldr r3, [r7, #4]
|
|
8006522: 681b ldr r3, [r3, #0]
|
|
8006524: f06f 0204 mvn.w r2, #4
|
|
8006528: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
800652a: 687b ldr r3, [r7, #4]
|
|
800652c: 2202 movs r2, #2
|
|
800652e: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
8006530: 687b ldr r3, [r7, #4]
|
|
8006532: 681b ldr r3, [r3, #0]
|
|
8006534: 699b ldr r3, [r3, #24]
|
|
8006536: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800653a: 2b00 cmp r3, #0
|
|
800653c: d003 beq.n 8006546 <HAL_TIM_IRQHandler+0x9e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800653e: 6878 ldr r0, [r7, #4]
|
|
8006540: f000 f8c8 bl 80066d4 <HAL_TIM_IC_CaptureCallback>
|
|
8006544: e005 b.n 8006552 <HAL_TIM_IRQHandler+0xaa>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8006546: 6878 ldr r0, [r7, #4]
|
|
8006548: f000 f8ba bl 80066c0 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800654c: 6878 ldr r0, [r7, #4]
|
|
800654e: f000 f8cb bl 80066e8 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8006552: 687b ldr r3, [r7, #4]
|
|
8006554: 2200 movs r2, #0
|
|
8006556: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
|
8006558: 68bb ldr r3, [r7, #8]
|
|
800655a: f003 0308 and.w r3, r3, #8
|
|
800655e: 2b00 cmp r3, #0
|
|
8006560: d020 beq.n 80065a4 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
|
8006562: 68fb ldr r3, [r7, #12]
|
|
8006564: f003 0308 and.w r3, r3, #8
|
|
8006568: 2b00 cmp r3, #0
|
|
800656a: d01b beq.n 80065a4 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
|
800656c: 687b ldr r3, [r7, #4]
|
|
800656e: 681b ldr r3, [r3, #0]
|
|
8006570: f06f 0208 mvn.w r2, #8
|
|
8006574: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
8006576: 687b ldr r3, [r7, #4]
|
|
8006578: 2204 movs r2, #4
|
|
800657a: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
800657c: 687b ldr r3, [r7, #4]
|
|
800657e: 681b ldr r3, [r3, #0]
|
|
8006580: 69db ldr r3, [r3, #28]
|
|
8006582: f003 0303 and.w r3, r3, #3
|
|
8006586: 2b00 cmp r3, #0
|
|
8006588: d003 beq.n 8006592 <HAL_TIM_IRQHandler+0xea>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800658a: 6878 ldr r0, [r7, #4]
|
|
800658c: f000 f8a2 bl 80066d4 <HAL_TIM_IC_CaptureCallback>
|
|
8006590: e005 b.n 800659e <HAL_TIM_IRQHandler+0xf6>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8006592: 6878 ldr r0, [r7, #4]
|
|
8006594: f000 f894 bl 80066c0 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8006598: 6878 ldr r0, [r7, #4]
|
|
800659a: f000 f8a5 bl 80066e8 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800659e: 687b ldr r3, [r7, #4]
|
|
80065a0: 2200 movs r2, #0
|
|
80065a2: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
|
80065a4: 68bb ldr r3, [r7, #8]
|
|
80065a6: f003 0310 and.w r3, r3, #16
|
|
80065aa: 2b00 cmp r3, #0
|
|
80065ac: d020 beq.n 80065f0 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
|
80065ae: 68fb ldr r3, [r7, #12]
|
|
80065b0: f003 0310 and.w r3, r3, #16
|
|
80065b4: 2b00 cmp r3, #0
|
|
80065b6: d01b beq.n 80065f0 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
|
80065b8: 687b ldr r3, [r7, #4]
|
|
80065ba: 681b ldr r3, [r3, #0]
|
|
80065bc: f06f 0210 mvn.w r2, #16
|
|
80065c0: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
80065c2: 687b ldr r3, [r7, #4]
|
|
80065c4: 2208 movs r2, #8
|
|
80065c6: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
80065c8: 687b ldr r3, [r7, #4]
|
|
80065ca: 681b ldr r3, [r3, #0]
|
|
80065cc: 69db ldr r3, [r3, #28]
|
|
80065ce: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80065d2: 2b00 cmp r3, #0
|
|
80065d4: d003 beq.n 80065de <HAL_TIM_IRQHandler+0x136>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80065d6: 6878 ldr r0, [r7, #4]
|
|
80065d8: f000 f87c bl 80066d4 <HAL_TIM_IC_CaptureCallback>
|
|
80065dc: e005 b.n 80065ea <HAL_TIM_IRQHandler+0x142>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80065de: 6878 ldr r0, [r7, #4]
|
|
80065e0: f000 f86e bl 80066c0 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
80065e4: 6878 ldr r0, [r7, #4]
|
|
80065e6: f000 f87f bl 80066e8 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
80065ea: 687b ldr r3, [r7, #4]
|
|
80065ec: 2200 movs r2, #0
|
|
80065ee: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
|
80065f0: 68bb ldr r3, [r7, #8]
|
|
80065f2: f003 0301 and.w r3, r3, #1
|
|
80065f6: 2b00 cmp r3, #0
|
|
80065f8: d00c beq.n 8006614 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
|
80065fa: 68fb ldr r3, [r7, #12]
|
|
80065fc: f003 0301 and.w r3, r3, #1
|
|
8006600: 2b00 cmp r3, #0
|
|
8006602: d007 beq.n 8006614 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
8006604: 687b ldr r3, [r7, #4]
|
|
8006606: 681b ldr r3, [r3, #0]
|
|
8006608: f06f 0201 mvn.w r2, #1
|
|
800660c: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
800660e: 6878 ldr r0, [r7, #4]
|
|
8006610: f000 f84c bl 80066ac <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
|
|
8006614: 68bb ldr r3, [r7, #8]
|
|
8006616: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800661a: 2b00 cmp r3, #0
|
|
800661c: d00c beq.n 8006638 <HAL_TIM_IRQHandler+0x190>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
800661e: 68fb ldr r3, [r7, #12]
|
|
8006620: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006624: 2b00 cmp r3, #0
|
|
8006626: d007 beq.n 8006638 <HAL_TIM_IRQHandler+0x190>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
|
|
8006628: 687b ldr r3, [r7, #4]
|
|
800662a: 681b ldr r3, [r3, #0]
|
|
800662c: f06f 0280 mvn.w r2, #128 @ 0x80
|
|
8006630: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8006632: 6878 ldr r0, [r7, #4]
|
|
8006634: f000 f978 bl 8006928 <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
#if defined(TIM_BDTR_BK2E)
|
|
/* TIM Break2 input event */
|
|
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
|
|
8006638: 68bb ldr r3, [r7, #8]
|
|
800663a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800663e: 2b00 cmp r3, #0
|
|
8006640: d00c beq.n 800665c <HAL_TIM_IRQHandler+0x1b4>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8006642: 68fb ldr r3, [r7, #12]
|
|
8006644: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006648: 2b00 cmp r3, #0
|
|
800664a: d007 beq.n 800665c <HAL_TIM_IRQHandler+0x1b4>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
|
800664c: 687b ldr r3, [r7, #4]
|
|
800664e: 681b ldr r3, [r3, #0]
|
|
8006650: f46f 7280 mvn.w r2, #256 @ 0x100
|
|
8006654: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->Break2Callback(htim);
|
|
#else
|
|
HAL_TIMEx_Break2Callback(htim);
|
|
8006656: 6878 ldr r0, [r7, #4]
|
|
8006658: f000 f970 bl 800693c <HAL_TIMEx_Break2Callback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
#endif /* TIM_BDTR_BK2E */
|
|
/* TIM Trigger detection event */
|
|
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
|
800665c: 68bb ldr r3, [r7, #8]
|
|
800665e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006662: 2b00 cmp r3, #0
|
|
8006664: d00c beq.n 8006680 <HAL_TIM_IRQHandler+0x1d8>
|
|
{
|
|
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
|
8006666: 68fb ldr r3, [r7, #12]
|
|
8006668: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800666c: 2b00 cmp r3, #0
|
|
800666e: d007 beq.n 8006680 <HAL_TIM_IRQHandler+0x1d8>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
8006670: 687b ldr r3, [r7, #4]
|
|
8006672: 681b ldr r3, [r3, #0]
|
|
8006674: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
8006678: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
800667a: 6878 ldr r0, [r7, #4]
|
|
800667c: f000 f83e bl 80066fc <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
|
8006680: 68bb ldr r3, [r7, #8]
|
|
8006682: f003 0320 and.w r3, r3, #32
|
|
8006686: 2b00 cmp r3, #0
|
|
8006688: d00c beq.n 80066a4 <HAL_TIM_IRQHandler+0x1fc>
|
|
{
|
|
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
|
800668a: 68fb ldr r3, [r7, #12]
|
|
800668c: f003 0320 and.w r3, r3, #32
|
|
8006690: 2b00 cmp r3, #0
|
|
8006692: d007 beq.n 80066a4 <HAL_TIM_IRQHandler+0x1fc>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
8006694: 687b ldr r3, [r7, #4]
|
|
8006696: 681b ldr r3, [r3, #0]
|
|
8006698: f06f 0220 mvn.w r2, #32
|
|
800669c: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
800669e: 6878 ldr r0, [r7, #4]
|
|
80066a0: f000 f938 bl 8006914 <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
80066a4: bf00 nop
|
|
80066a6: 3710 adds r7, #16
|
|
80066a8: 46bd mov sp, r7
|
|
80066aa: bd80 pop {r7, pc}
|
|
|
|
080066ac <HAL_TIM_PeriodElapsedCallback>:
|
|
* @brief Period elapsed callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80066ac: b480 push {r7}
|
|
80066ae: b083 sub sp, #12
|
|
80066b0: af00 add r7, sp, #0
|
|
80066b2: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80066b4: bf00 nop
|
|
80066b6: 370c adds r7, #12
|
|
80066b8: 46bd mov sp, r7
|
|
80066ba: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066be: 4770 bx lr
|
|
|
|
080066c0 <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80066c0: b480 push {r7}
|
|
80066c2: b083 sub sp, #12
|
|
80066c4: af00 add r7, sp, #0
|
|
80066c6: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80066c8: bf00 nop
|
|
80066ca: 370c adds r7, #12
|
|
80066cc: 46bd mov sp, r7
|
|
80066ce: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066d2: 4770 bx lr
|
|
|
|
080066d4 <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80066d4: b480 push {r7}
|
|
80066d6: b083 sub sp, #12
|
|
80066d8: af00 add r7, sp, #0
|
|
80066da: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80066dc: bf00 nop
|
|
80066de: 370c adds r7, #12
|
|
80066e0: 46bd mov sp, r7
|
|
80066e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066e6: 4770 bx lr
|
|
|
|
080066e8 <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80066e8: b480 push {r7}
|
|
80066ea: b083 sub sp, #12
|
|
80066ec: af00 add r7, sp, #0
|
|
80066ee: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80066f0: bf00 nop
|
|
80066f2: 370c adds r7, #12
|
|
80066f4: 46bd mov sp, r7
|
|
80066f6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80066fa: 4770 bx lr
|
|
|
|
080066fc <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80066fc: b480 push {r7}
|
|
80066fe: b083 sub sp, #12
|
|
8006700: af00 add r7, sp, #0
|
|
8006702: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006704: bf00 nop
|
|
8006706: 370c adds r7, #12
|
|
8006708: 46bd mov sp, r7
|
|
800670a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800670e: 4770 bx lr
|
|
|
|
08006710 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8006710: b480 push {r7}
|
|
8006712: b085 sub sp, #20
|
|
8006714: af00 add r7, sp, #0
|
|
8006716: 6078 str r0, [r7, #4]
|
|
8006718: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800671a: 687b ldr r3, [r7, #4]
|
|
800671c: 681b ldr r3, [r3, #0]
|
|
800671e: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8006720: 687b ldr r3, [r7, #4]
|
|
8006722: 4a3c ldr r2, [pc, #240] @ (8006814 <TIM_Base_SetConfig+0x104>)
|
|
8006724: 4293 cmp r3, r2
|
|
8006726: d00b beq.n 8006740 <TIM_Base_SetConfig+0x30>
|
|
8006728: 687b ldr r3, [r7, #4]
|
|
800672a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800672e: d007 beq.n 8006740 <TIM_Base_SetConfig+0x30>
|
|
8006730: 687b ldr r3, [r7, #4]
|
|
8006732: 4a39 ldr r2, [pc, #228] @ (8006818 <TIM_Base_SetConfig+0x108>)
|
|
8006734: 4293 cmp r3, r2
|
|
8006736: d003 beq.n 8006740 <TIM_Base_SetConfig+0x30>
|
|
8006738: 687b ldr r3, [r7, #4]
|
|
800673a: 4a38 ldr r2, [pc, #224] @ (800681c <TIM_Base_SetConfig+0x10c>)
|
|
800673c: 4293 cmp r3, r2
|
|
800673e: d108 bne.n 8006752 <TIM_Base_SetConfig+0x42>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
8006740: 68fb ldr r3, [r7, #12]
|
|
8006742: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8006746: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
8006748: 683b ldr r3, [r7, #0]
|
|
800674a: 685b ldr r3, [r3, #4]
|
|
800674c: 68fa ldr r2, [r7, #12]
|
|
800674e: 4313 orrs r3, r2
|
|
8006750: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
8006752: 687b ldr r3, [r7, #4]
|
|
8006754: 4a2f ldr r2, [pc, #188] @ (8006814 <TIM_Base_SetConfig+0x104>)
|
|
8006756: 4293 cmp r3, r2
|
|
8006758: d017 beq.n 800678a <TIM_Base_SetConfig+0x7a>
|
|
800675a: 687b ldr r3, [r7, #4]
|
|
800675c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8006760: d013 beq.n 800678a <TIM_Base_SetConfig+0x7a>
|
|
8006762: 687b ldr r3, [r7, #4]
|
|
8006764: 4a2c ldr r2, [pc, #176] @ (8006818 <TIM_Base_SetConfig+0x108>)
|
|
8006766: 4293 cmp r3, r2
|
|
8006768: d00f beq.n 800678a <TIM_Base_SetConfig+0x7a>
|
|
800676a: 687b ldr r3, [r7, #4]
|
|
800676c: 4a2b ldr r2, [pc, #172] @ (800681c <TIM_Base_SetConfig+0x10c>)
|
|
800676e: 4293 cmp r3, r2
|
|
8006770: d00b beq.n 800678a <TIM_Base_SetConfig+0x7a>
|
|
8006772: 687b ldr r3, [r7, #4]
|
|
8006774: 4a2a ldr r2, [pc, #168] @ (8006820 <TIM_Base_SetConfig+0x110>)
|
|
8006776: 4293 cmp r3, r2
|
|
8006778: d007 beq.n 800678a <TIM_Base_SetConfig+0x7a>
|
|
800677a: 687b ldr r3, [r7, #4]
|
|
800677c: 4a29 ldr r2, [pc, #164] @ (8006824 <TIM_Base_SetConfig+0x114>)
|
|
800677e: 4293 cmp r3, r2
|
|
8006780: d003 beq.n 800678a <TIM_Base_SetConfig+0x7a>
|
|
8006782: 687b ldr r3, [r7, #4]
|
|
8006784: 4a28 ldr r2, [pc, #160] @ (8006828 <TIM_Base_SetConfig+0x118>)
|
|
8006786: 4293 cmp r3, r2
|
|
8006788: d108 bne.n 800679c <TIM_Base_SetConfig+0x8c>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
800678a: 68fb ldr r3, [r7, #12]
|
|
800678c: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8006790: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
8006792: 683b ldr r3, [r7, #0]
|
|
8006794: 68db ldr r3, [r3, #12]
|
|
8006796: 68fa ldr r2, [r7, #12]
|
|
8006798: 4313 orrs r3, r2
|
|
800679a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
800679c: 68fb ldr r3, [r7, #12]
|
|
800679e: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
80067a2: 683b ldr r3, [r7, #0]
|
|
80067a4: 695b ldr r3, [r3, #20]
|
|
80067a6: 4313 orrs r3, r2
|
|
80067a8: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
80067aa: 687b ldr r3, [r7, #4]
|
|
80067ac: 68fa ldr r2, [r7, #12]
|
|
80067ae: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
80067b0: 683b ldr r3, [r7, #0]
|
|
80067b2: 689a ldr r2, [r3, #8]
|
|
80067b4: 687b ldr r3, [r7, #4]
|
|
80067b6: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
80067b8: 683b ldr r3, [r7, #0]
|
|
80067ba: 681a ldr r2, [r3, #0]
|
|
80067bc: 687b ldr r3, [r7, #4]
|
|
80067be: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
80067c0: 687b ldr r3, [r7, #4]
|
|
80067c2: 4a14 ldr r2, [pc, #80] @ (8006814 <TIM_Base_SetConfig+0x104>)
|
|
80067c4: 4293 cmp r3, r2
|
|
80067c6: d00b beq.n 80067e0 <TIM_Base_SetConfig+0xd0>
|
|
80067c8: 687b ldr r3, [r7, #4]
|
|
80067ca: 4a15 ldr r2, [pc, #84] @ (8006820 <TIM_Base_SetConfig+0x110>)
|
|
80067cc: 4293 cmp r3, r2
|
|
80067ce: d007 beq.n 80067e0 <TIM_Base_SetConfig+0xd0>
|
|
80067d0: 687b ldr r3, [r7, #4]
|
|
80067d2: 4a14 ldr r2, [pc, #80] @ (8006824 <TIM_Base_SetConfig+0x114>)
|
|
80067d4: 4293 cmp r3, r2
|
|
80067d6: d003 beq.n 80067e0 <TIM_Base_SetConfig+0xd0>
|
|
80067d8: 687b ldr r3, [r7, #4]
|
|
80067da: 4a13 ldr r2, [pc, #76] @ (8006828 <TIM_Base_SetConfig+0x118>)
|
|
80067dc: 4293 cmp r3, r2
|
|
80067de: d103 bne.n 80067e8 <TIM_Base_SetConfig+0xd8>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
80067e0: 683b ldr r3, [r7, #0]
|
|
80067e2: 691a ldr r2, [r3, #16]
|
|
80067e4: 687b ldr r3, [r7, #4]
|
|
80067e6: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
80067e8: 687b ldr r3, [r7, #4]
|
|
80067ea: 2201 movs r2, #1
|
|
80067ec: 615a str r2, [r3, #20]
|
|
|
|
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
|
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
|
80067ee: 687b ldr r3, [r7, #4]
|
|
80067f0: 691b ldr r3, [r3, #16]
|
|
80067f2: f003 0301 and.w r3, r3, #1
|
|
80067f6: 2b01 cmp r3, #1
|
|
80067f8: d105 bne.n 8006806 <TIM_Base_SetConfig+0xf6>
|
|
{
|
|
/* Clear the update flag */
|
|
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
|
80067fa: 687b ldr r3, [r7, #4]
|
|
80067fc: 691b ldr r3, [r3, #16]
|
|
80067fe: f023 0201 bic.w r2, r3, #1
|
|
8006802: 687b ldr r3, [r7, #4]
|
|
8006804: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
8006806: bf00 nop
|
|
8006808: 3714 adds r7, #20
|
|
800680a: 46bd mov sp, r7
|
|
800680c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006810: 4770 bx lr
|
|
8006812: bf00 nop
|
|
8006814: 40012c00 .word 0x40012c00
|
|
8006818: 40000400 .word 0x40000400
|
|
800681c: 40000800 .word 0x40000800
|
|
8006820: 40014000 .word 0x40014000
|
|
8006824: 40014400 .word 0x40014400
|
|
8006828: 40014800 .word 0x40014800
|
|
|
|
0800682c <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
800682c: b480 push {r7}
|
|
800682e: b085 sub sp, #20
|
|
8006830: af00 add r7, sp, #0
|
|
8006832: 6078 str r0, [r7, #4]
|
|
8006834: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8006836: 687b ldr r3, [r7, #4]
|
|
8006838: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
800683c: 2b01 cmp r3, #1
|
|
800683e: d101 bne.n 8006844 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8006840: 2302 movs r3, #2
|
|
8006842: e059 b.n 80068f8 <HAL_TIMEx_MasterConfigSynchronization+0xcc>
|
|
8006844: 687b ldr r3, [r7, #4]
|
|
8006846: 2201 movs r2, #1
|
|
8006848: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800684c: 687b ldr r3, [r7, #4]
|
|
800684e: 2202 movs r2, #2
|
|
8006850: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8006854: 687b ldr r3, [r7, #4]
|
|
8006856: 681b ldr r3, [r3, #0]
|
|
8006858: 685b ldr r3, [r3, #4]
|
|
800685a: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800685c: 687b ldr r3, [r7, #4]
|
|
800685e: 681b ldr r3, [r3, #0]
|
|
8006860: 689b ldr r3, [r3, #8]
|
|
8006862: 60bb str r3, [r7, #8]
|
|
|
|
#if defined(TIM_CR2_MMS2)
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
8006864: 687b ldr r3, [r7, #4]
|
|
8006866: 681b ldr r3, [r3, #0]
|
|
8006868: 4a26 ldr r2, [pc, #152] @ (8006904 <HAL_TIMEx_MasterConfigSynchronization+0xd8>)
|
|
800686a: 4293 cmp r3, r2
|
|
800686c: d108 bne.n 8006880 <HAL_TIMEx_MasterConfigSynchronization+0x54>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
800686e: 68fb ldr r3, [r7, #12]
|
|
8006870: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
|
|
8006874: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
8006876: 683b ldr r3, [r7, #0]
|
|
8006878: 685b ldr r3, [r3, #4]
|
|
800687a: 68fa ldr r2, [r7, #12]
|
|
800687c: 4313 orrs r3, r2
|
|
800687e: 60fb str r3, [r7, #12]
|
|
}
|
|
#endif /* TIM_CR2_MMS2 */
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8006880: 68fb ldr r3, [r7, #12]
|
|
8006882: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8006886: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8006888: 683b ldr r3, [r7, #0]
|
|
800688a: 681b ldr r3, [r3, #0]
|
|
800688c: 68fa ldr r2, [r7, #12]
|
|
800688e: 4313 orrs r3, r2
|
|
8006890: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8006892: 687b ldr r3, [r7, #4]
|
|
8006894: 681b ldr r3, [r3, #0]
|
|
8006896: 68fa ldr r2, [r7, #12]
|
|
8006898: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
800689a: 687b ldr r3, [r7, #4]
|
|
800689c: 681b ldr r3, [r3, #0]
|
|
800689e: 4a19 ldr r2, [pc, #100] @ (8006904 <HAL_TIMEx_MasterConfigSynchronization+0xd8>)
|
|
80068a0: 4293 cmp r3, r2
|
|
80068a2: d013 beq.n 80068cc <HAL_TIMEx_MasterConfigSynchronization+0xa0>
|
|
80068a4: 687b ldr r3, [r7, #4]
|
|
80068a6: 681b ldr r3, [r3, #0]
|
|
80068a8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80068ac: d00e beq.n 80068cc <HAL_TIMEx_MasterConfigSynchronization+0xa0>
|
|
80068ae: 687b ldr r3, [r7, #4]
|
|
80068b0: 681b ldr r3, [r3, #0]
|
|
80068b2: 4a15 ldr r2, [pc, #84] @ (8006908 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
|
|
80068b4: 4293 cmp r3, r2
|
|
80068b6: d009 beq.n 80068cc <HAL_TIMEx_MasterConfigSynchronization+0xa0>
|
|
80068b8: 687b ldr r3, [r7, #4]
|
|
80068ba: 681b ldr r3, [r3, #0]
|
|
80068bc: 4a13 ldr r2, [pc, #76] @ (800690c <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
|
|
80068be: 4293 cmp r3, r2
|
|
80068c0: d004 beq.n 80068cc <HAL_TIMEx_MasterConfigSynchronization+0xa0>
|
|
80068c2: 687b ldr r3, [r7, #4]
|
|
80068c4: 681b ldr r3, [r3, #0]
|
|
80068c6: 4a12 ldr r2, [pc, #72] @ (8006910 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
|
|
80068c8: 4293 cmp r3, r2
|
|
80068ca: d10c bne.n 80068e6 <HAL_TIMEx_MasterConfigSynchronization+0xba>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
80068cc: 68bb ldr r3, [r7, #8]
|
|
80068ce: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
80068d2: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
80068d4: 683b ldr r3, [r7, #0]
|
|
80068d6: 689b ldr r3, [r3, #8]
|
|
80068d8: 68ba ldr r2, [r7, #8]
|
|
80068da: 4313 orrs r3, r2
|
|
80068dc: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80068de: 687b ldr r3, [r7, #4]
|
|
80068e0: 681b ldr r3, [r3, #0]
|
|
80068e2: 68ba ldr r2, [r7, #8]
|
|
80068e4: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80068e6: 687b ldr r3, [r7, #4]
|
|
80068e8: 2201 movs r2, #1
|
|
80068ea: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
80068ee: 687b ldr r3, [r7, #4]
|
|
80068f0: 2200 movs r2, #0
|
|
80068f2: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
80068f6: 2300 movs r3, #0
|
|
}
|
|
80068f8: 4618 mov r0, r3
|
|
80068fa: 3714 adds r7, #20
|
|
80068fc: 46bd mov sp, r7
|
|
80068fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006902: 4770 bx lr
|
|
8006904: 40012c00 .word 0x40012c00
|
|
8006908: 40000400 .word 0x40000400
|
|
800690c: 40000800 .word 0x40000800
|
|
8006910: 40014000 .word 0x40014000
|
|
|
|
08006914 <HAL_TIMEx_CommutCallback>:
|
|
* @brief Commutation callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8006914: b480 push {r7}
|
|
8006916: b083 sub sp, #12
|
|
8006918: af00 add r7, sp, #0
|
|
800691a: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800691c: bf00 nop
|
|
800691e: 370c adds r7, #12
|
|
8006920: 46bd mov sp, r7
|
|
8006922: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006926: 4770 bx lr
|
|
|
|
08006928 <HAL_TIMEx_BreakCallback>:
|
|
* @brief Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8006928: b480 push {r7}
|
|
800692a: b083 sub sp, #12
|
|
800692c: af00 add r7, sp, #0
|
|
800692e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006930: bf00 nop
|
|
8006932: 370c adds r7, #12
|
|
8006934: 46bd mov sp, r7
|
|
8006936: f85d 7b04 ldr.w r7, [sp], #4
|
|
800693a: 4770 bx lr
|
|
|
|
0800693c <HAL_TIMEx_Break2Callback>:
|
|
* @brief Break2 detection callback in non blocking mode
|
|
* @param htim: TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800693c: b480 push {r7}
|
|
800693e: b083 sub sp, #12
|
|
8006940: af00 add r7, sp, #0
|
|
8006942: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_Break2Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006944: bf00 nop
|
|
8006946: 370c adds r7, #12
|
|
8006948: 46bd mov sp, r7
|
|
800694a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800694e: 4770 bx lr
|
|
|
|
08006950 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8006950: b580 push {r7, lr}
|
|
8006952: b082 sub sp, #8
|
|
8006954: af00 add r7, sp, #0
|
|
8006956: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8006958: 687b ldr r3, [r7, #4]
|
|
800695a: 2b00 cmp r3, #0
|
|
800695c: d101 bne.n 8006962 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800695e: 2301 movs r3, #1
|
|
8006960: e040 b.n 80069e4 <HAL_UART_Init+0x94>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8006962: 687b ldr r3, [r7, #4]
|
|
8006964: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8006966: 2b00 cmp r3, #0
|
|
8006968: d106 bne.n 8006978 <HAL_UART_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
800696a: 687b ldr r3, [r7, #4]
|
|
800696c: 2200 movs r2, #0
|
|
800696e: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8006972: 6878 ldr r0, [r7, #4]
|
|
8006974: f7fb fb74 bl 8002060 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8006978: 687b ldr r3, [r7, #4]
|
|
800697a: 2224 movs r2, #36 @ 0x24
|
|
800697c: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
800697e: 687b ldr r3, [r7, #4]
|
|
8006980: 681b ldr r3, [r3, #0]
|
|
8006982: 681a ldr r2, [r3, #0]
|
|
8006984: 687b ldr r3, [r7, #4]
|
|
8006986: 681b ldr r3, [r3, #0]
|
|
8006988: f022 0201 bic.w r2, r2, #1
|
|
800698c: 601a str r2, [r3, #0]
|
|
|
|
/* Perform advanced settings configuration */
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
800698e: 687b ldr r3, [r7, #4]
|
|
8006990: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006992: 2b00 cmp r3, #0
|
|
8006994: d002 beq.n 800699c <HAL_UART_Init+0x4c>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
8006996: 6878 ldr r0, [r7, #4]
|
|
8006998: f000 f9fc bl 8006d94 <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
800699c: 6878 ldr r0, [r7, #4]
|
|
800699e: f000 f825 bl 80069ec <UART_SetConfig>
|
|
80069a2: 4603 mov r3, r0
|
|
80069a4: 2b01 cmp r3, #1
|
|
80069a6: d101 bne.n 80069ac <HAL_UART_Init+0x5c>
|
|
{
|
|
return HAL_ERROR;
|
|
80069a8: 2301 movs r3, #1
|
|
80069aa: e01b b.n 80069e4 <HAL_UART_Init+0x94>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
80069ac: 687b ldr r3, [r7, #4]
|
|
80069ae: 681b ldr r3, [r3, #0]
|
|
80069b0: 685a ldr r2, [r3, #4]
|
|
80069b2: 687b ldr r3, [r7, #4]
|
|
80069b4: 681b ldr r3, [r3, #0]
|
|
80069b6: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
80069ba: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
80069bc: 687b ldr r3, [r7, #4]
|
|
80069be: 681b ldr r3, [r3, #0]
|
|
80069c0: 689a ldr r2, [r3, #8]
|
|
80069c2: 687b ldr r3, [r7, #4]
|
|
80069c4: 681b ldr r3, [r3, #0]
|
|
80069c6: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
80069ca: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
80069cc: 687b ldr r3, [r7, #4]
|
|
80069ce: 681b ldr r3, [r3, #0]
|
|
80069d0: 681a ldr r2, [r3, #0]
|
|
80069d2: 687b ldr r3, [r7, #4]
|
|
80069d4: 681b ldr r3, [r3, #0]
|
|
80069d6: f042 0201 orr.w r2, r2, #1
|
|
80069da: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
80069dc: 6878 ldr r0, [r7, #4]
|
|
80069de: f000 fa7b bl 8006ed8 <UART_CheckIdleState>
|
|
80069e2: 4603 mov r3, r0
|
|
}
|
|
80069e4: 4618 mov r0, r3
|
|
80069e6: 3708 adds r7, #8
|
|
80069e8: 46bd mov sp, r7
|
|
80069ea: bd80 pop {r7, pc}
|
|
|
|
080069ec <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
80069ec: b580 push {r7, lr}
|
|
80069ee: b088 sub sp, #32
|
|
80069f0: af00 add r7, sp, #0
|
|
80069f2: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
80069f4: 2300 movs r3, #0
|
|
80069f6: 77bb strb r3, [r7, #30]
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
80069f8: 687b ldr r3, [r7, #4]
|
|
80069fa: 689a ldr r2, [r3, #8]
|
|
80069fc: 687b ldr r3, [r7, #4]
|
|
80069fe: 691b ldr r3, [r3, #16]
|
|
8006a00: 431a orrs r2, r3
|
|
8006a02: 687b ldr r3, [r7, #4]
|
|
8006a04: 695b ldr r3, [r3, #20]
|
|
8006a06: 431a orrs r2, r3
|
|
8006a08: 687b ldr r3, [r7, #4]
|
|
8006a0a: 69db ldr r3, [r3, #28]
|
|
8006a0c: 4313 orrs r3, r2
|
|
8006a0e: 617b str r3, [r7, #20]
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
8006a10: 687b ldr r3, [r7, #4]
|
|
8006a12: 681b ldr r3, [r3, #0]
|
|
8006a14: 681b ldr r3, [r3, #0]
|
|
8006a16: f423 4316 bic.w r3, r3, #38400 @ 0x9600
|
|
8006a1a: f023 030c bic.w r3, r3, #12
|
|
8006a1e: 687a ldr r2, [r7, #4]
|
|
8006a20: 6812 ldr r2, [r2, #0]
|
|
8006a22: 6979 ldr r1, [r7, #20]
|
|
8006a24: 430b orrs r3, r1
|
|
8006a26: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8006a28: 687b ldr r3, [r7, #4]
|
|
8006a2a: 681b ldr r3, [r3, #0]
|
|
8006a2c: 685b ldr r3, [r3, #4]
|
|
8006a2e: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
8006a32: 687b ldr r3, [r7, #4]
|
|
8006a34: 68da ldr r2, [r3, #12]
|
|
8006a36: 687b ldr r3, [r7, #4]
|
|
8006a38: 681b ldr r3, [r3, #0]
|
|
8006a3a: 430a orrs r2, r1
|
|
8006a3c: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
8006a3e: 687b ldr r3, [r7, #4]
|
|
8006a40: 699b ldr r3, [r3, #24]
|
|
8006a42: 617b str r3, [r7, #20]
|
|
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
8006a44: 687b ldr r3, [r7, #4]
|
|
8006a46: 6a1b ldr r3, [r3, #32]
|
|
8006a48: 697a ldr r2, [r7, #20]
|
|
8006a4a: 4313 orrs r3, r2
|
|
8006a4c: 617b str r3, [r7, #20]
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
8006a4e: 687b ldr r3, [r7, #4]
|
|
8006a50: 681b ldr r3, [r3, #0]
|
|
8006a52: 689b ldr r3, [r3, #8]
|
|
8006a54: f423 6130 bic.w r1, r3, #2816 @ 0xb00
|
|
8006a58: 687b ldr r3, [r7, #4]
|
|
8006a5a: 681b ldr r3, [r3, #0]
|
|
8006a5c: 697a ldr r2, [r7, #20]
|
|
8006a5e: 430a orrs r2, r1
|
|
8006a60: 609a str r2, [r3, #8]
|
|
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
8006a62: 687b ldr r3, [r7, #4]
|
|
8006a64: 681b ldr r3, [r3, #0]
|
|
8006a66: 4aa7 ldr r2, [pc, #668] @ (8006d04 <UART_SetConfig+0x318>)
|
|
8006a68: 4293 cmp r3, r2
|
|
8006a6a: d120 bne.n 8006aae <UART_SetConfig+0xc2>
|
|
8006a6c: 4ba6 ldr r3, [pc, #664] @ (8006d08 <UART_SetConfig+0x31c>)
|
|
8006a6e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006a70: f003 0303 and.w r3, r3, #3
|
|
8006a74: 2b03 cmp r3, #3
|
|
8006a76: d817 bhi.n 8006aa8 <UART_SetConfig+0xbc>
|
|
8006a78: a201 add r2, pc, #4 @ (adr r2, 8006a80 <UART_SetConfig+0x94>)
|
|
8006a7a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006a7e: bf00 nop
|
|
8006a80: 08006a91 .word 0x08006a91
|
|
8006a84: 08006a9d .word 0x08006a9d
|
|
8006a88: 08006aa3 .word 0x08006aa3
|
|
8006a8c: 08006a97 .word 0x08006a97
|
|
8006a90: 2301 movs r3, #1
|
|
8006a92: 77fb strb r3, [r7, #31]
|
|
8006a94: e0b5 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006a96: 2302 movs r3, #2
|
|
8006a98: 77fb strb r3, [r7, #31]
|
|
8006a9a: e0b2 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006a9c: 2304 movs r3, #4
|
|
8006a9e: 77fb strb r3, [r7, #31]
|
|
8006aa0: e0af b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006aa2: 2308 movs r3, #8
|
|
8006aa4: 77fb strb r3, [r7, #31]
|
|
8006aa6: e0ac b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006aa8: 2310 movs r3, #16
|
|
8006aaa: 77fb strb r3, [r7, #31]
|
|
8006aac: e0a9 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006aae: 687b ldr r3, [r7, #4]
|
|
8006ab0: 681b ldr r3, [r3, #0]
|
|
8006ab2: 4a96 ldr r2, [pc, #600] @ (8006d0c <UART_SetConfig+0x320>)
|
|
8006ab4: 4293 cmp r3, r2
|
|
8006ab6: d124 bne.n 8006b02 <UART_SetConfig+0x116>
|
|
8006ab8: 4b93 ldr r3, [pc, #588] @ (8006d08 <UART_SetConfig+0x31c>)
|
|
8006aba: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006abc: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8006ac0: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
|
|
8006ac4: d011 beq.n 8006aea <UART_SetConfig+0xfe>
|
|
8006ac6: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
|
|
8006aca: d817 bhi.n 8006afc <UART_SetConfig+0x110>
|
|
8006acc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
|
|
8006ad0: d011 beq.n 8006af6 <UART_SetConfig+0x10a>
|
|
8006ad2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
|
|
8006ad6: d811 bhi.n 8006afc <UART_SetConfig+0x110>
|
|
8006ad8: 2b00 cmp r3, #0
|
|
8006ada: d003 beq.n 8006ae4 <UART_SetConfig+0xf8>
|
|
8006adc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8006ae0: d006 beq.n 8006af0 <UART_SetConfig+0x104>
|
|
8006ae2: e00b b.n 8006afc <UART_SetConfig+0x110>
|
|
8006ae4: 2300 movs r3, #0
|
|
8006ae6: 77fb strb r3, [r7, #31]
|
|
8006ae8: e08b b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006aea: 2302 movs r3, #2
|
|
8006aec: 77fb strb r3, [r7, #31]
|
|
8006aee: e088 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006af0: 2304 movs r3, #4
|
|
8006af2: 77fb strb r3, [r7, #31]
|
|
8006af4: e085 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006af6: 2308 movs r3, #8
|
|
8006af8: 77fb strb r3, [r7, #31]
|
|
8006afa: e082 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006afc: 2310 movs r3, #16
|
|
8006afe: 77fb strb r3, [r7, #31]
|
|
8006b00: e07f b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b02: 687b ldr r3, [r7, #4]
|
|
8006b04: 681b ldr r3, [r3, #0]
|
|
8006b06: 4a82 ldr r2, [pc, #520] @ (8006d10 <UART_SetConfig+0x324>)
|
|
8006b08: 4293 cmp r3, r2
|
|
8006b0a: d124 bne.n 8006b56 <UART_SetConfig+0x16a>
|
|
8006b0c: 4b7e ldr r3, [pc, #504] @ (8006d08 <UART_SetConfig+0x31c>)
|
|
8006b0e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006b10: f403 2340 and.w r3, r3, #786432 @ 0xc0000
|
|
8006b14: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
|
|
8006b18: d011 beq.n 8006b3e <UART_SetConfig+0x152>
|
|
8006b1a: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
|
|
8006b1e: d817 bhi.n 8006b50 <UART_SetConfig+0x164>
|
|
8006b20: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
|
|
8006b24: d011 beq.n 8006b4a <UART_SetConfig+0x15e>
|
|
8006b26: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
|
|
8006b2a: d811 bhi.n 8006b50 <UART_SetConfig+0x164>
|
|
8006b2c: 2b00 cmp r3, #0
|
|
8006b2e: d003 beq.n 8006b38 <UART_SetConfig+0x14c>
|
|
8006b30: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8006b34: d006 beq.n 8006b44 <UART_SetConfig+0x158>
|
|
8006b36: e00b b.n 8006b50 <UART_SetConfig+0x164>
|
|
8006b38: 2300 movs r3, #0
|
|
8006b3a: 77fb strb r3, [r7, #31]
|
|
8006b3c: e061 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b3e: 2302 movs r3, #2
|
|
8006b40: 77fb strb r3, [r7, #31]
|
|
8006b42: e05e b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b44: 2304 movs r3, #4
|
|
8006b46: 77fb strb r3, [r7, #31]
|
|
8006b48: e05b b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b4a: 2308 movs r3, #8
|
|
8006b4c: 77fb strb r3, [r7, #31]
|
|
8006b4e: e058 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b50: 2310 movs r3, #16
|
|
8006b52: 77fb strb r3, [r7, #31]
|
|
8006b54: e055 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b56: 687b ldr r3, [r7, #4]
|
|
8006b58: 681b ldr r3, [r3, #0]
|
|
8006b5a: 4a6e ldr r2, [pc, #440] @ (8006d14 <UART_SetConfig+0x328>)
|
|
8006b5c: 4293 cmp r3, r2
|
|
8006b5e: d124 bne.n 8006baa <UART_SetConfig+0x1be>
|
|
8006b60: 4b69 ldr r3, [pc, #420] @ (8006d08 <UART_SetConfig+0x31c>)
|
|
8006b62: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006b64: f403 1340 and.w r3, r3, #3145728 @ 0x300000
|
|
8006b68: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000
|
|
8006b6c: d011 beq.n 8006b92 <UART_SetConfig+0x1a6>
|
|
8006b6e: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000
|
|
8006b72: d817 bhi.n 8006ba4 <UART_SetConfig+0x1b8>
|
|
8006b74: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
8006b78: d011 beq.n 8006b9e <UART_SetConfig+0x1b2>
|
|
8006b7a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
8006b7e: d811 bhi.n 8006ba4 <UART_SetConfig+0x1b8>
|
|
8006b80: 2b00 cmp r3, #0
|
|
8006b82: d003 beq.n 8006b8c <UART_SetConfig+0x1a0>
|
|
8006b84: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8006b88: d006 beq.n 8006b98 <UART_SetConfig+0x1ac>
|
|
8006b8a: e00b b.n 8006ba4 <UART_SetConfig+0x1b8>
|
|
8006b8c: 2300 movs r3, #0
|
|
8006b8e: 77fb strb r3, [r7, #31]
|
|
8006b90: e037 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b92: 2302 movs r3, #2
|
|
8006b94: 77fb strb r3, [r7, #31]
|
|
8006b96: e034 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b98: 2304 movs r3, #4
|
|
8006b9a: 77fb strb r3, [r7, #31]
|
|
8006b9c: e031 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006b9e: 2308 movs r3, #8
|
|
8006ba0: 77fb strb r3, [r7, #31]
|
|
8006ba2: e02e b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006ba4: 2310 movs r3, #16
|
|
8006ba6: 77fb strb r3, [r7, #31]
|
|
8006ba8: e02b b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006baa: 687b ldr r3, [r7, #4]
|
|
8006bac: 681b ldr r3, [r3, #0]
|
|
8006bae: 4a5a ldr r2, [pc, #360] @ (8006d18 <UART_SetConfig+0x32c>)
|
|
8006bb0: 4293 cmp r3, r2
|
|
8006bb2: d124 bne.n 8006bfe <UART_SetConfig+0x212>
|
|
8006bb4: 4b54 ldr r3, [pc, #336] @ (8006d08 <UART_SetConfig+0x31c>)
|
|
8006bb6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8006bb8: f403 0340 and.w r3, r3, #12582912 @ 0xc00000
|
|
8006bbc: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
8006bc0: d011 beq.n 8006be6 <UART_SetConfig+0x1fa>
|
|
8006bc2: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
8006bc6: d817 bhi.n 8006bf8 <UART_SetConfig+0x20c>
|
|
8006bc8: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
8006bcc: d011 beq.n 8006bf2 <UART_SetConfig+0x206>
|
|
8006bce: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
8006bd2: d811 bhi.n 8006bf8 <UART_SetConfig+0x20c>
|
|
8006bd4: 2b00 cmp r3, #0
|
|
8006bd6: d003 beq.n 8006be0 <UART_SetConfig+0x1f4>
|
|
8006bd8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8006bdc: d006 beq.n 8006bec <UART_SetConfig+0x200>
|
|
8006bde: e00b b.n 8006bf8 <UART_SetConfig+0x20c>
|
|
8006be0: 2300 movs r3, #0
|
|
8006be2: 77fb strb r3, [r7, #31]
|
|
8006be4: e00d b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006be6: 2302 movs r3, #2
|
|
8006be8: 77fb strb r3, [r7, #31]
|
|
8006bea: e00a b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006bec: 2304 movs r3, #4
|
|
8006bee: 77fb strb r3, [r7, #31]
|
|
8006bf0: e007 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006bf2: 2308 movs r3, #8
|
|
8006bf4: 77fb strb r3, [r7, #31]
|
|
8006bf6: e004 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006bf8: 2310 movs r3, #16
|
|
8006bfa: 77fb strb r3, [r7, #31]
|
|
8006bfc: e001 b.n 8006c02 <UART_SetConfig+0x216>
|
|
8006bfe: 2310 movs r3, #16
|
|
8006c00: 77fb strb r3, [r7, #31]
|
|
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8006c02: 687b ldr r3, [r7, #4]
|
|
8006c04: 69db ldr r3, [r3, #28]
|
|
8006c06: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8006c0a: d15b bne.n 8006cc4 <UART_SetConfig+0x2d8>
|
|
{
|
|
switch (clocksource)
|
|
8006c0c: 7ffb ldrb r3, [r7, #31]
|
|
8006c0e: 2b08 cmp r3, #8
|
|
8006c10: d827 bhi.n 8006c62 <UART_SetConfig+0x276>
|
|
8006c12: a201 add r2, pc, #4 @ (adr r2, 8006c18 <UART_SetConfig+0x22c>)
|
|
8006c14: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006c18: 08006c3d .word 0x08006c3d
|
|
8006c1c: 08006c45 .word 0x08006c45
|
|
8006c20: 08006c4d .word 0x08006c4d
|
|
8006c24: 08006c63 .word 0x08006c63
|
|
8006c28: 08006c53 .word 0x08006c53
|
|
8006c2c: 08006c63 .word 0x08006c63
|
|
8006c30: 08006c63 .word 0x08006c63
|
|
8006c34: 08006c63 .word 0x08006c63
|
|
8006c38: 08006c5b .word 0x08006c5b
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006c3c: f7ff f9ac bl 8005f98 <HAL_RCC_GetPCLK1Freq>
|
|
8006c40: 61b8 str r0, [r7, #24]
|
|
break;
|
|
8006c42: e013 b.n 8006c6c <UART_SetConfig+0x280>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8006c44: f7ff f9ca bl 8005fdc <HAL_RCC_GetPCLK2Freq>
|
|
8006c48: 61b8 str r0, [r7, #24]
|
|
break;
|
|
8006c4a: e00f b.n 8006c6c <UART_SetConfig+0x280>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8006c4c: 4b33 ldr r3, [pc, #204] @ (8006d1c <UART_SetConfig+0x330>)
|
|
8006c4e: 61bb str r3, [r7, #24]
|
|
break;
|
|
8006c50: e00c b.n 8006c6c <UART_SetConfig+0x280>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8006c52: f7ff f93f bl 8005ed4 <HAL_RCC_GetSysClockFreq>
|
|
8006c56: 61b8 str r0, [r7, #24]
|
|
break;
|
|
8006c58: e008 b.n 8006c6c <UART_SetConfig+0x280>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8006c5a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8006c5e: 61bb str r3, [r7, #24]
|
|
break;
|
|
8006c60: e004 b.n 8006c6c <UART_SetConfig+0x280>
|
|
default:
|
|
pclk = 0U;
|
|
8006c62: 2300 movs r3, #0
|
|
8006c64: 61bb str r3, [r7, #24]
|
|
ret = HAL_ERROR;
|
|
8006c66: 2301 movs r3, #1
|
|
8006c68: 77bb strb r3, [r7, #30]
|
|
break;
|
|
8006c6a: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
8006c6c: 69bb ldr r3, [r7, #24]
|
|
8006c6e: 2b00 cmp r3, #0
|
|
8006c70: f000 8082 beq.w 8006d78 <UART_SetConfig+0x38c>
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
8006c74: 69bb ldr r3, [r7, #24]
|
|
8006c76: 005a lsls r2, r3, #1
|
|
8006c78: 687b ldr r3, [r7, #4]
|
|
8006c7a: 685b ldr r3, [r3, #4]
|
|
8006c7c: 085b lsrs r3, r3, #1
|
|
8006c7e: 441a add r2, r3
|
|
8006c80: 687b ldr r3, [r7, #4]
|
|
8006c82: 685b ldr r3, [r3, #4]
|
|
8006c84: fbb2 f3f3 udiv r3, r2, r3
|
|
8006c88: 613b str r3, [r7, #16]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8006c8a: 693b ldr r3, [r7, #16]
|
|
8006c8c: 2b0f cmp r3, #15
|
|
8006c8e: d916 bls.n 8006cbe <UART_SetConfig+0x2d2>
|
|
8006c90: 693b ldr r3, [r7, #16]
|
|
8006c92: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8006c96: d212 bcs.n 8006cbe <UART_SetConfig+0x2d2>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8006c98: 693b ldr r3, [r7, #16]
|
|
8006c9a: b29b uxth r3, r3
|
|
8006c9c: f023 030f bic.w r3, r3, #15
|
|
8006ca0: 81fb strh r3, [r7, #14]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
8006ca2: 693b ldr r3, [r7, #16]
|
|
8006ca4: 085b lsrs r3, r3, #1
|
|
8006ca6: b29b uxth r3, r3
|
|
8006ca8: f003 0307 and.w r3, r3, #7
|
|
8006cac: b29a uxth r2, r3
|
|
8006cae: 89fb ldrh r3, [r7, #14]
|
|
8006cb0: 4313 orrs r3, r2
|
|
8006cb2: 81fb strh r3, [r7, #14]
|
|
huart->Instance->BRR = brrtemp;
|
|
8006cb4: 687b ldr r3, [r7, #4]
|
|
8006cb6: 681b ldr r3, [r3, #0]
|
|
8006cb8: 89fa ldrh r2, [r7, #14]
|
|
8006cba: 60da str r2, [r3, #12]
|
|
8006cbc: e05c b.n 8006d78 <UART_SetConfig+0x38c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006cbe: 2301 movs r3, #1
|
|
8006cc0: 77bb strb r3, [r7, #30]
|
|
8006cc2: e059 b.n 8006d78 <UART_SetConfig+0x38c>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
8006cc4: 7ffb ldrb r3, [r7, #31]
|
|
8006cc6: 2b08 cmp r3, #8
|
|
8006cc8: d835 bhi.n 8006d36 <UART_SetConfig+0x34a>
|
|
8006cca: a201 add r2, pc, #4 @ (adr r2, 8006cd0 <UART_SetConfig+0x2e4>)
|
|
8006ccc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006cd0: 08006cf5 .word 0x08006cf5
|
|
8006cd4: 08006cfd .word 0x08006cfd
|
|
8006cd8: 08006d21 .word 0x08006d21
|
|
8006cdc: 08006d37 .word 0x08006d37
|
|
8006ce0: 08006d27 .word 0x08006d27
|
|
8006ce4: 08006d37 .word 0x08006d37
|
|
8006ce8: 08006d37 .word 0x08006d37
|
|
8006cec: 08006d37 .word 0x08006d37
|
|
8006cf0: 08006d2f .word 0x08006d2f
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006cf4: f7ff f950 bl 8005f98 <HAL_RCC_GetPCLK1Freq>
|
|
8006cf8: 61b8 str r0, [r7, #24]
|
|
break;
|
|
8006cfa: e021 b.n 8006d40 <UART_SetConfig+0x354>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8006cfc: f7ff f96e bl 8005fdc <HAL_RCC_GetPCLK2Freq>
|
|
8006d00: 61b8 str r0, [r7, #24]
|
|
break;
|
|
8006d02: e01d b.n 8006d40 <UART_SetConfig+0x354>
|
|
8006d04: 40013800 .word 0x40013800
|
|
8006d08: 40021000 .word 0x40021000
|
|
8006d0c: 40004400 .word 0x40004400
|
|
8006d10: 40004800 .word 0x40004800
|
|
8006d14: 40004c00 .word 0x40004c00
|
|
8006d18: 40005000 .word 0x40005000
|
|
8006d1c: 007a1200 .word 0x007a1200
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8006d20: 4b1b ldr r3, [pc, #108] @ (8006d90 <UART_SetConfig+0x3a4>)
|
|
8006d22: 61bb str r3, [r7, #24]
|
|
break;
|
|
8006d24: e00c b.n 8006d40 <UART_SetConfig+0x354>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8006d26: f7ff f8d5 bl 8005ed4 <HAL_RCC_GetSysClockFreq>
|
|
8006d2a: 61b8 str r0, [r7, #24]
|
|
break;
|
|
8006d2c: e008 b.n 8006d40 <UART_SetConfig+0x354>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8006d2e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8006d32: 61bb str r3, [r7, #24]
|
|
break;
|
|
8006d34: e004 b.n 8006d40 <UART_SetConfig+0x354>
|
|
default:
|
|
pclk = 0U;
|
|
8006d36: 2300 movs r3, #0
|
|
8006d38: 61bb str r3, [r7, #24]
|
|
ret = HAL_ERROR;
|
|
8006d3a: 2301 movs r3, #1
|
|
8006d3c: 77bb strb r3, [r7, #30]
|
|
break;
|
|
8006d3e: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
8006d40: 69bb ldr r3, [r7, #24]
|
|
8006d42: 2b00 cmp r3, #0
|
|
8006d44: d018 beq.n 8006d78 <UART_SetConfig+0x38c>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
8006d46: 687b ldr r3, [r7, #4]
|
|
8006d48: 685b ldr r3, [r3, #4]
|
|
8006d4a: 085a lsrs r2, r3, #1
|
|
8006d4c: 69bb ldr r3, [r7, #24]
|
|
8006d4e: 441a add r2, r3
|
|
8006d50: 687b ldr r3, [r7, #4]
|
|
8006d52: 685b ldr r3, [r3, #4]
|
|
8006d54: fbb2 f3f3 udiv r3, r2, r3
|
|
8006d58: 613b str r3, [r7, #16]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8006d5a: 693b ldr r3, [r7, #16]
|
|
8006d5c: 2b0f cmp r3, #15
|
|
8006d5e: d909 bls.n 8006d74 <UART_SetConfig+0x388>
|
|
8006d60: 693b ldr r3, [r7, #16]
|
|
8006d62: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8006d66: d205 bcs.n 8006d74 <UART_SetConfig+0x388>
|
|
{
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
8006d68: 693b ldr r3, [r7, #16]
|
|
8006d6a: b29a uxth r2, r3
|
|
8006d6c: 687b ldr r3, [r7, #4]
|
|
8006d6e: 681b ldr r3, [r3, #0]
|
|
8006d70: 60da str r2, [r3, #12]
|
|
8006d72: e001 b.n 8006d78 <UART_SetConfig+0x38c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006d74: 2301 movs r3, #1
|
|
8006d76: 77bb strb r3, [r7, #30]
|
|
}
|
|
}
|
|
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
8006d78: 687b ldr r3, [r7, #4]
|
|
8006d7a: 2200 movs r2, #0
|
|
8006d7c: 669a str r2, [r3, #104] @ 0x68
|
|
huart->TxISR = NULL;
|
|
8006d7e: 687b ldr r3, [r7, #4]
|
|
8006d80: 2200 movs r2, #0
|
|
8006d82: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
return ret;
|
|
8006d84: 7fbb ldrb r3, [r7, #30]
|
|
}
|
|
8006d86: 4618 mov r0, r3
|
|
8006d88: 3720 adds r7, #32
|
|
8006d8a: 46bd mov sp, r7
|
|
8006d8c: bd80 pop {r7, pc}
|
|
8006d8e: bf00 nop
|
|
8006d90: 007a1200 .word 0x007a1200
|
|
|
|
08006d94 <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8006d94: b480 push {r7}
|
|
8006d96: b083 sub sp, #12
|
|
8006d98: af00 add r7, sp, #0
|
|
8006d9a: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
8006d9c: 687b ldr r3, [r7, #4]
|
|
8006d9e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006da0: f003 0308 and.w r3, r3, #8
|
|
8006da4: 2b00 cmp r3, #0
|
|
8006da6: d00a beq.n 8006dbe <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
8006da8: 687b ldr r3, [r7, #4]
|
|
8006daa: 681b ldr r3, [r3, #0]
|
|
8006dac: 685b ldr r3, [r3, #4]
|
|
8006dae: f423 4100 bic.w r1, r3, #32768 @ 0x8000
|
|
8006db2: 687b ldr r3, [r7, #4]
|
|
8006db4: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8006db6: 687b ldr r3, [r7, #4]
|
|
8006db8: 681b ldr r3, [r3, #0]
|
|
8006dba: 430a orrs r2, r1
|
|
8006dbc: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
8006dbe: 687b ldr r3, [r7, #4]
|
|
8006dc0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006dc2: f003 0301 and.w r3, r3, #1
|
|
8006dc6: 2b00 cmp r3, #0
|
|
8006dc8: d00a beq.n 8006de0 <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
8006dca: 687b ldr r3, [r7, #4]
|
|
8006dcc: 681b ldr r3, [r3, #0]
|
|
8006dce: 685b ldr r3, [r3, #4]
|
|
8006dd0: f423 3100 bic.w r1, r3, #131072 @ 0x20000
|
|
8006dd4: 687b ldr r3, [r7, #4]
|
|
8006dd6: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
8006dd8: 687b ldr r3, [r7, #4]
|
|
8006dda: 681b ldr r3, [r3, #0]
|
|
8006ddc: 430a orrs r2, r1
|
|
8006dde: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8006de0: 687b ldr r3, [r7, #4]
|
|
8006de2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006de4: f003 0302 and.w r3, r3, #2
|
|
8006de8: 2b00 cmp r3, #0
|
|
8006dea: d00a beq.n 8006e02 <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
8006dec: 687b ldr r3, [r7, #4]
|
|
8006dee: 681b ldr r3, [r3, #0]
|
|
8006df0: 685b ldr r3, [r3, #4]
|
|
8006df2: f423 3180 bic.w r1, r3, #65536 @ 0x10000
|
|
8006df6: 687b ldr r3, [r7, #4]
|
|
8006df8: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8006dfa: 687b ldr r3, [r7, #4]
|
|
8006dfc: 681b ldr r3, [r3, #0]
|
|
8006dfe: 430a orrs r2, r1
|
|
8006e00: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8006e02: 687b ldr r3, [r7, #4]
|
|
8006e04: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006e06: f003 0304 and.w r3, r3, #4
|
|
8006e0a: 2b00 cmp r3, #0
|
|
8006e0c: d00a beq.n 8006e24 <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
8006e0e: 687b ldr r3, [r7, #4]
|
|
8006e10: 681b ldr r3, [r3, #0]
|
|
8006e12: 685b ldr r3, [r3, #4]
|
|
8006e14: f423 2180 bic.w r1, r3, #262144 @ 0x40000
|
|
8006e18: 687b ldr r3, [r7, #4]
|
|
8006e1a: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8006e1c: 687b ldr r3, [r7, #4]
|
|
8006e1e: 681b ldr r3, [r3, #0]
|
|
8006e20: 430a orrs r2, r1
|
|
8006e22: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8006e24: 687b ldr r3, [r7, #4]
|
|
8006e26: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006e28: f003 0310 and.w r3, r3, #16
|
|
8006e2c: 2b00 cmp r3, #0
|
|
8006e2e: d00a beq.n 8006e46 <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
8006e30: 687b ldr r3, [r7, #4]
|
|
8006e32: 681b ldr r3, [r3, #0]
|
|
8006e34: 689b ldr r3, [r3, #8]
|
|
8006e36: f423 5180 bic.w r1, r3, #4096 @ 0x1000
|
|
8006e3a: 687b ldr r3, [r7, #4]
|
|
8006e3c: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8006e3e: 687b ldr r3, [r7, #4]
|
|
8006e40: 681b ldr r3, [r3, #0]
|
|
8006e42: 430a orrs r2, r1
|
|
8006e44: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8006e46: 687b ldr r3, [r7, #4]
|
|
8006e48: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006e4a: f003 0320 and.w r3, r3, #32
|
|
8006e4e: 2b00 cmp r3, #0
|
|
8006e50: d00a beq.n 8006e68 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
8006e52: 687b ldr r3, [r7, #4]
|
|
8006e54: 681b ldr r3, [r3, #0]
|
|
8006e56: 689b ldr r3, [r3, #8]
|
|
8006e58: f423 5100 bic.w r1, r3, #8192 @ 0x2000
|
|
8006e5c: 687b ldr r3, [r7, #4]
|
|
8006e5e: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8006e60: 687b ldr r3, [r7, #4]
|
|
8006e62: 681b ldr r3, [r3, #0]
|
|
8006e64: 430a orrs r2, r1
|
|
8006e66: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
8006e68: 687b ldr r3, [r7, #4]
|
|
8006e6a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006e6c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006e70: 2b00 cmp r3, #0
|
|
8006e72: d01a beq.n 8006eaa <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
8006e74: 687b ldr r3, [r7, #4]
|
|
8006e76: 681b ldr r3, [r3, #0]
|
|
8006e78: 685b ldr r3, [r3, #4]
|
|
8006e7a: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
|
|
8006e7e: 687b ldr r3, [r7, #4]
|
|
8006e80: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8006e82: 687b ldr r3, [r7, #4]
|
|
8006e84: 681b ldr r3, [r3, #0]
|
|
8006e86: 430a orrs r2, r1
|
|
8006e88: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
8006e8a: 687b ldr r3, [r7, #4]
|
|
8006e8c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8006e8e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8006e92: d10a bne.n 8006eaa <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
8006e94: 687b ldr r3, [r7, #4]
|
|
8006e96: 681b ldr r3, [r3, #0]
|
|
8006e98: 685b ldr r3, [r3, #4]
|
|
8006e9a: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
|
|
8006e9e: 687b ldr r3, [r7, #4]
|
|
8006ea0: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8006ea2: 687b ldr r3, [r7, #4]
|
|
8006ea4: 681b ldr r3, [r3, #0]
|
|
8006ea6: 430a orrs r2, r1
|
|
8006ea8: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
8006eaa: 687b ldr r3, [r7, #4]
|
|
8006eac: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006eae: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006eb2: 2b00 cmp r3, #0
|
|
8006eb4: d00a beq.n 8006ecc <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
8006eb6: 687b ldr r3, [r7, #4]
|
|
8006eb8: 681b ldr r3, [r3, #0]
|
|
8006eba: 685b ldr r3, [r3, #4]
|
|
8006ebc: f423 2100 bic.w r1, r3, #524288 @ 0x80000
|
|
8006ec0: 687b ldr r3, [r7, #4]
|
|
8006ec2: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
8006ec4: 687b ldr r3, [r7, #4]
|
|
8006ec6: 681b ldr r3, [r3, #0]
|
|
8006ec8: 430a orrs r2, r1
|
|
8006eca: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
8006ecc: bf00 nop
|
|
8006ece: 370c adds r7, #12
|
|
8006ed0: 46bd mov sp, r7
|
|
8006ed2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006ed6: 4770 bx lr
|
|
|
|
08006ed8 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8006ed8: b580 push {r7, lr}
|
|
8006eda: b098 sub sp, #96 @ 0x60
|
|
8006edc: af02 add r7, sp, #8
|
|
8006ede: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006ee0: 687b ldr r3, [r7, #4]
|
|
8006ee2: 2200 movs r2, #0
|
|
8006ee4: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8006ee8: f7fb fa04 bl 80022f4 <HAL_GetTick>
|
|
8006eec: 6578 str r0, [r7, #84] @ 0x54
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
8006eee: 687b ldr r3, [r7, #4]
|
|
8006ef0: 681b ldr r3, [r3, #0]
|
|
8006ef2: 681b ldr r3, [r3, #0]
|
|
8006ef4: f003 0308 and.w r3, r3, #8
|
|
8006ef8: 2b08 cmp r3, #8
|
|
8006efa: d12e bne.n 8006f5a <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8006efc: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8006f00: 9300 str r3, [sp, #0]
|
|
8006f02: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8006f04: 2200 movs r2, #0
|
|
8006f06: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
8006f0a: 6878 ldr r0, [r7, #4]
|
|
8006f0c: f000 f88c bl 8007028 <UART_WaitOnFlagUntilTimeout>
|
|
8006f10: 4603 mov r3, r0
|
|
8006f12: 2b00 cmp r3, #0
|
|
8006f14: d021 beq.n 8006f5a <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
|
|
8006f16: 687b ldr r3, [r7, #4]
|
|
8006f18: 681b ldr r3, [r3, #0]
|
|
8006f1a: 63bb str r3, [r7, #56] @ 0x38
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006f1c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006f1e: e853 3f00 ldrex r3, [r3]
|
|
8006f22: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8006f24: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006f26: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8006f2a: 653b str r3, [r7, #80] @ 0x50
|
|
8006f2c: 687b ldr r3, [r7, #4]
|
|
8006f2e: 681b ldr r3, [r3, #0]
|
|
8006f30: 461a mov r2, r3
|
|
8006f32: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8006f34: 647b str r3, [r7, #68] @ 0x44
|
|
8006f36: 643a str r2, [r7, #64] @ 0x40
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006f38: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8006f3a: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8006f3c: e841 2300 strex r3, r2, [r1]
|
|
8006f40: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8006f42: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006f44: 2b00 cmp r3, #0
|
|
8006f46: d1e6 bne.n 8006f16 <UART_CheckIdleState+0x3e>
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006f48: 687b ldr r3, [r7, #4]
|
|
8006f4a: 2220 movs r2, #32
|
|
8006f4c: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006f4e: 687b ldr r3, [r7, #4]
|
|
8006f50: 2200 movs r2, #0
|
|
8006f52: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8006f56: 2303 movs r3, #3
|
|
8006f58: e062 b.n 8007020 <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
8006f5a: 687b ldr r3, [r7, #4]
|
|
8006f5c: 681b ldr r3, [r3, #0]
|
|
8006f5e: 681b ldr r3, [r3, #0]
|
|
8006f60: f003 0304 and.w r3, r3, #4
|
|
8006f64: 2b04 cmp r3, #4
|
|
8006f66: d149 bne.n 8006ffc <UART_CheckIdleState+0x124>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8006f68: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8006f6c: 9300 str r3, [sp, #0]
|
|
8006f6e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8006f70: 2200 movs r2, #0
|
|
8006f72: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
8006f76: 6878 ldr r0, [r7, #4]
|
|
8006f78: f000 f856 bl 8007028 <UART_WaitOnFlagUntilTimeout>
|
|
8006f7c: 4603 mov r3, r0
|
|
8006f7e: 2b00 cmp r3, #0
|
|
8006f80: d03c beq.n 8006ffc <UART_CheckIdleState+0x124>
|
|
{
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8006f82: 687b ldr r3, [r7, #4]
|
|
8006f84: 681b ldr r3, [r3, #0]
|
|
8006f86: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006f88: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006f8a: e853 3f00 ldrex r3, [r3]
|
|
8006f8e: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006f90: 6a3b ldr r3, [r7, #32]
|
|
8006f92: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006f96: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006f98: 687b ldr r3, [r7, #4]
|
|
8006f9a: 681b ldr r3, [r3, #0]
|
|
8006f9c: 461a mov r2, r3
|
|
8006f9e: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006fa0: 633b str r3, [r7, #48] @ 0x30
|
|
8006fa2: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006fa4: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8006fa6: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8006fa8: e841 2300 strex r3, r2, [r1]
|
|
8006fac: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006fae: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006fb0: 2b00 cmp r3, #0
|
|
8006fb2: d1e6 bne.n 8006f82 <UART_CheckIdleState+0xaa>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006fb4: 687b ldr r3, [r7, #4]
|
|
8006fb6: 681b ldr r3, [r3, #0]
|
|
8006fb8: 3308 adds r3, #8
|
|
8006fba: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006fbc: 693b ldr r3, [r7, #16]
|
|
8006fbe: e853 3f00 ldrex r3, [r3]
|
|
8006fc2: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006fc4: 68fb ldr r3, [r7, #12]
|
|
8006fc6: f023 0301 bic.w r3, r3, #1
|
|
8006fca: 64bb str r3, [r7, #72] @ 0x48
|
|
8006fcc: 687b ldr r3, [r7, #4]
|
|
8006fce: 681b ldr r3, [r3, #0]
|
|
8006fd0: 3308 adds r3, #8
|
|
8006fd2: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006fd4: 61fa str r2, [r7, #28]
|
|
8006fd6: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006fd8: 69b9 ldr r1, [r7, #24]
|
|
8006fda: 69fa ldr r2, [r7, #28]
|
|
8006fdc: e841 2300 strex r3, r2, [r1]
|
|
8006fe0: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006fe2: 697b ldr r3, [r7, #20]
|
|
8006fe4: 2b00 cmp r3, #0
|
|
8006fe6: d1e5 bne.n 8006fb4 <UART_CheckIdleState+0xdc>
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006fe8: 687b ldr r3, [r7, #4]
|
|
8006fea: 2220 movs r2, #32
|
|
8006fec: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006ff0: 687b ldr r3, [r7, #4]
|
|
8006ff2: 2200 movs r2, #0
|
|
8006ff4: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8006ff8: 2303 movs r3, #3
|
|
8006ffa: e011 b.n 8007020 <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006ffc: 687b ldr r3, [r7, #4]
|
|
8006ffe: 2220 movs r2, #32
|
|
8007000: 67da str r2, [r3, #124] @ 0x7c
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8007002: 687b ldr r3, [r7, #4]
|
|
8007004: 2220 movs r2, #32
|
|
8007006: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800700a: 687b ldr r3, [r7, #4]
|
|
800700c: 2200 movs r2, #0
|
|
800700e: 661a str r2, [r3, #96] @ 0x60
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8007010: 687b ldr r3, [r7, #4]
|
|
8007012: 2200 movs r2, #0
|
|
8007014: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8007016: 687b ldr r3, [r7, #4]
|
|
8007018: 2200 movs r2, #0
|
|
800701a: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_OK;
|
|
800701e: 2300 movs r3, #0
|
|
}
|
|
8007020: 4618 mov r0, r3
|
|
8007022: 3758 adds r7, #88 @ 0x58
|
|
8007024: 46bd mov sp, r7
|
|
8007026: bd80 pop {r7, pc}
|
|
|
|
08007028 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8007028: b580 push {r7, lr}
|
|
800702a: b084 sub sp, #16
|
|
800702c: af00 add r7, sp, #0
|
|
800702e: 60f8 str r0, [r7, #12]
|
|
8007030: 60b9 str r1, [r7, #8]
|
|
8007032: 603b str r3, [r7, #0]
|
|
8007034: 4613 mov r3, r2
|
|
8007036: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8007038: e04f b.n 80070da <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800703a: 69bb ldr r3, [r7, #24]
|
|
800703c: f1b3 3fff cmp.w r3, #4294967295
|
|
8007040: d04b beq.n 80070da <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8007042: f7fb f957 bl 80022f4 <HAL_GetTick>
|
|
8007046: 4602 mov r2, r0
|
|
8007048: 683b ldr r3, [r7, #0]
|
|
800704a: 1ad3 subs r3, r2, r3
|
|
800704c: 69ba ldr r2, [r7, #24]
|
|
800704e: 429a cmp r2, r3
|
|
8007050: d302 bcc.n 8007058 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
8007052: 69bb ldr r3, [r7, #24]
|
|
8007054: 2b00 cmp r3, #0
|
|
8007056: d101 bne.n 800705c <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
8007058: 2303 movs r3, #3
|
|
800705a: e04e b.n 80070fa <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
800705c: 68fb ldr r3, [r7, #12]
|
|
800705e: 681b ldr r3, [r3, #0]
|
|
8007060: 681b ldr r3, [r3, #0]
|
|
8007062: f003 0304 and.w r3, r3, #4
|
|
8007066: 2b00 cmp r3, #0
|
|
8007068: d037 beq.n 80070da <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
800706a: 68bb ldr r3, [r7, #8]
|
|
800706c: 2b80 cmp r3, #128 @ 0x80
|
|
800706e: d034 beq.n 80070da <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8007070: 68bb ldr r3, [r7, #8]
|
|
8007072: 2b40 cmp r3, #64 @ 0x40
|
|
8007074: d031 beq.n 80070da <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
8007076: 68fb ldr r3, [r7, #12]
|
|
8007078: 681b ldr r3, [r3, #0]
|
|
800707a: 69db ldr r3, [r3, #28]
|
|
800707c: f003 0308 and.w r3, r3, #8
|
|
8007080: 2b08 cmp r3, #8
|
|
8007082: d110 bne.n 80070a6 <UART_WaitOnFlagUntilTimeout+0x7e>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8007084: 68fb ldr r3, [r7, #12]
|
|
8007086: 681b ldr r3, [r3, #0]
|
|
8007088: 2208 movs r2, #8
|
|
800708a: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
800708c: 68f8 ldr r0, [r7, #12]
|
|
800708e: f000 f838 bl 8007102 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
8007092: 68fb ldr r3, [r7, #12]
|
|
8007094: 2208 movs r2, #8
|
|
8007096: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
800709a: 68fb ldr r3, [r7, #12]
|
|
800709c: 2200 movs r2, #0
|
|
800709e: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_ERROR;
|
|
80070a2: 2301 movs r3, #1
|
|
80070a4: e029 b.n 80070fa <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
80070a6: 68fb ldr r3, [r7, #12]
|
|
80070a8: 681b ldr r3, [r3, #0]
|
|
80070aa: 69db ldr r3, [r3, #28]
|
|
80070ac: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80070b0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80070b4: d111 bne.n 80070da <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
80070b6: 68fb ldr r3, [r7, #12]
|
|
80070b8: 681b ldr r3, [r3, #0]
|
|
80070ba: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
80070be: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
80070c0: 68f8 ldr r0, [r7, #12]
|
|
80070c2: f000 f81e bl 8007102 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
80070c6: 68fb ldr r3, [r7, #12]
|
|
80070c8: 2220 movs r2, #32
|
|
80070ca: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80070ce: 68fb ldr r3, [r7, #12]
|
|
80070d0: 2200 movs r2, #0
|
|
80070d2: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_TIMEOUT;
|
|
80070d6: 2303 movs r3, #3
|
|
80070d8: e00f b.n 80070fa <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
80070da: 68fb ldr r3, [r7, #12]
|
|
80070dc: 681b ldr r3, [r3, #0]
|
|
80070de: 69da ldr r2, [r3, #28]
|
|
80070e0: 68bb ldr r3, [r7, #8]
|
|
80070e2: 4013 ands r3, r2
|
|
80070e4: 68ba ldr r2, [r7, #8]
|
|
80070e6: 429a cmp r2, r3
|
|
80070e8: bf0c ite eq
|
|
80070ea: 2301 moveq r3, #1
|
|
80070ec: 2300 movne r3, #0
|
|
80070ee: b2db uxtb r3, r3
|
|
80070f0: 461a mov r2, r3
|
|
80070f2: 79fb ldrb r3, [r7, #7]
|
|
80070f4: 429a cmp r2, r3
|
|
80070f6: d0a0 beq.n 800703a <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80070f8: 2300 movs r3, #0
|
|
}
|
|
80070fa: 4618 mov r0, r3
|
|
80070fc: 3710 adds r7, #16
|
|
80070fe: 46bd mov sp, r7
|
|
8007100: bd80 pop {r7, pc}
|
|
|
|
08007102 <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
8007102: b480 push {r7}
|
|
8007104: b095 sub sp, #84 @ 0x54
|
|
8007106: af00 add r7, sp, #0
|
|
8007108: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
800710a: 687b ldr r3, [r7, #4]
|
|
800710c: 681b ldr r3, [r3, #0]
|
|
800710e: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007110: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8007112: e853 3f00 ldrex r3, [r3]
|
|
8007116: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8007118: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800711a: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
800711e: 64fb str r3, [r7, #76] @ 0x4c
|
|
8007120: 687b ldr r3, [r7, #4]
|
|
8007122: 681b ldr r3, [r3, #0]
|
|
8007124: 461a mov r2, r3
|
|
8007126: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8007128: 643b str r3, [r7, #64] @ 0x40
|
|
800712a: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800712c: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
800712e: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8007130: e841 2300 strex r3, r2, [r1]
|
|
8007134: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8007136: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8007138: 2b00 cmp r3, #0
|
|
800713a: d1e6 bne.n 800710a <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800713c: 687b ldr r3, [r7, #4]
|
|
800713e: 681b ldr r3, [r3, #0]
|
|
8007140: 3308 adds r3, #8
|
|
8007142: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007144: 6a3b ldr r3, [r7, #32]
|
|
8007146: e853 3f00 ldrex r3, [r3]
|
|
800714a: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
800714c: 69fb ldr r3, [r7, #28]
|
|
800714e: f023 0301 bic.w r3, r3, #1
|
|
8007152: 64bb str r3, [r7, #72] @ 0x48
|
|
8007154: 687b ldr r3, [r7, #4]
|
|
8007156: 681b ldr r3, [r3, #0]
|
|
8007158: 3308 adds r3, #8
|
|
800715a: 6cba ldr r2, [r7, #72] @ 0x48
|
|
800715c: 62fa str r2, [r7, #44] @ 0x2c
|
|
800715e: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007160: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8007162: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8007164: e841 2300 strex r3, r2, [r1]
|
|
8007168: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
800716a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800716c: 2b00 cmp r3, #0
|
|
800716e: d1e5 bne.n 800713c <UART_EndRxTransfer+0x3a>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8007170: 687b ldr r3, [r7, #4]
|
|
8007172: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8007174: 2b01 cmp r3, #1
|
|
8007176: d118 bne.n 80071aa <UART_EndRxTransfer+0xa8>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8007178: 687b ldr r3, [r7, #4]
|
|
800717a: 681b ldr r3, [r3, #0]
|
|
800717c: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800717e: 68fb ldr r3, [r7, #12]
|
|
8007180: e853 3f00 ldrex r3, [r3]
|
|
8007184: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8007186: 68bb ldr r3, [r7, #8]
|
|
8007188: f023 0310 bic.w r3, r3, #16
|
|
800718c: 647b str r3, [r7, #68] @ 0x44
|
|
800718e: 687b ldr r3, [r7, #4]
|
|
8007190: 681b ldr r3, [r3, #0]
|
|
8007192: 461a mov r2, r3
|
|
8007194: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8007196: 61bb str r3, [r7, #24]
|
|
8007198: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800719a: 6979 ldr r1, [r7, #20]
|
|
800719c: 69ba ldr r2, [r7, #24]
|
|
800719e: e841 2300 strex r3, r2, [r1]
|
|
80071a2: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80071a4: 693b ldr r3, [r7, #16]
|
|
80071a6: 2b00 cmp r3, #0
|
|
80071a8: d1e6 bne.n 8007178 <UART_EndRxTransfer+0x76>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80071aa: 687b ldr r3, [r7, #4]
|
|
80071ac: 2220 movs r2, #32
|
|
80071ae: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80071b2: 687b ldr r3, [r7, #4]
|
|
80071b4: 2200 movs r2, #0
|
|
80071b6: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
80071b8: 687b ldr r3, [r7, #4]
|
|
80071ba: 2200 movs r2, #0
|
|
80071bc: 669a str r2, [r3, #104] @ 0x68
|
|
}
|
|
80071be: bf00 nop
|
|
80071c0: 3754 adds r7, #84 @ 0x54
|
|
80071c2: 46bd mov sp, r7
|
|
80071c4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80071c8: 4770 bx lr
|
|
|
|
080071ca <memset>:
|
|
80071ca: 4402 add r2, r0
|
|
80071cc: 4603 mov r3, r0
|
|
80071ce: 4293 cmp r3, r2
|
|
80071d0: d100 bne.n 80071d4 <memset+0xa>
|
|
80071d2: 4770 bx lr
|
|
80071d4: f803 1b01 strb.w r1, [r3], #1
|
|
80071d8: e7f9 b.n 80071ce <memset+0x4>
|
|
...
|
|
|
|
080071dc <__libc_init_array>:
|
|
80071dc: b570 push {r4, r5, r6, lr}
|
|
80071de: 4d0d ldr r5, [pc, #52] @ (8007214 <__libc_init_array+0x38>)
|
|
80071e0: 4c0d ldr r4, [pc, #52] @ (8007218 <__libc_init_array+0x3c>)
|
|
80071e2: 1b64 subs r4, r4, r5
|
|
80071e4: 10a4 asrs r4, r4, #2
|
|
80071e6: 2600 movs r6, #0
|
|
80071e8: 42a6 cmp r6, r4
|
|
80071ea: d109 bne.n 8007200 <__libc_init_array+0x24>
|
|
80071ec: 4d0b ldr r5, [pc, #44] @ (800721c <__libc_init_array+0x40>)
|
|
80071ee: 4c0c ldr r4, [pc, #48] @ (8007220 <__libc_init_array+0x44>)
|
|
80071f0: f000 f818 bl 8007224 <_init>
|
|
80071f4: 1b64 subs r4, r4, r5
|
|
80071f6: 10a4 asrs r4, r4, #2
|
|
80071f8: 2600 movs r6, #0
|
|
80071fa: 42a6 cmp r6, r4
|
|
80071fc: d105 bne.n 800720a <__libc_init_array+0x2e>
|
|
80071fe: bd70 pop {r4, r5, r6, pc}
|
|
8007200: f855 3b04 ldr.w r3, [r5], #4
|
|
8007204: 4798 blx r3
|
|
8007206: 3601 adds r6, #1
|
|
8007208: e7ee b.n 80071e8 <__libc_init_array+0xc>
|
|
800720a: f855 3b04 ldr.w r3, [r5], #4
|
|
800720e: 4798 blx r3
|
|
8007210: 3601 adds r6, #1
|
|
8007212: e7f2 b.n 80071fa <__libc_init_array+0x1e>
|
|
8007214: 08007274 .word 0x08007274
|
|
8007218: 08007274 .word 0x08007274
|
|
800721c: 08007274 .word 0x08007274
|
|
8007220: 08007278 .word 0x08007278
|
|
|
|
08007224 <_init>:
|
|
8007224: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8007226: bf00 nop
|
|
8007228: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800722a: bc08 pop {r3}
|
|
800722c: 469e mov lr, r3
|
|
800722e: 4770 bx lr
|
|
|
|
08007230 <_fini>:
|
|
8007230: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8007232: bf00 nop
|
|
8007234: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8007236: bc08 pop {r3}
|
|
8007238: 469e mov lr, r3
|
|
800723a: 4770 bx lr
|